ramips: mt7620: split gsw hw_init to mac_init, ephy_init

[openwrt/staging/jow.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / gsw_mt7620.c

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
index 7c91e5840b64f0667cc343b908f40dea6787cdc6..615544cb1733c7209865e883ec83aa4972cc2878 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
@@ -61,26 +61,20 @@ static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
        return IRQ_HANDLED;
 }
 
-static void mt7620_hw_init(struct mt7620_gsw *gsw)
+static void mt7620_ephy_init(struct mt7620_gsw *gsw)
 {
        u32 i;
        u32 val;
        u32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1;
 
-       /* Internal ethernet requires PCIe RC mode */
-       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
-
-       mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
-
-       /* Enable MIB stats */
-       mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
-
        if (gsw->ephy_disable) {
                mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
                        (gsw->ephy_base << 16) | (0x1f << 24),
                        GSW_REG_GPC1);
 
                pr_info("gsw: internal ephy disabled\n");
+
+               return;
        } else if (gsw->ephy_base) {
                mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
                        (gsw->ephy_base << 16),
@@ -158,12 +152,6 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw)
        _mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
        _mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
 
-       /* CPU Port6 Force Link 1G, FC ON */
-       mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
-
-       /* Set Port 6 as CPU Port */
-       mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
-
        /* setup port 4 */
        if (gsw->port4_ephy) {
                val = rt_sysc_r32(SYSC_REG_CFG1);
@@ -177,6 +165,24 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw)
        }
 }
 
+static void mt7620_mac_init(struct mt7620_gsw *gsw)
+{
+       /* Internal ethernet requires PCIe RC mode */
+       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
+
+       /* Keep Global Clocks on Idle traffic */
+       mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
+
+       /* Set Port 6 to Force Link 1G, Flow Control ON */
+       mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
+
+       /* Set Port 6 as CPU Port */
+       mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
+
+       /* Enable MIB stats */
+       mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
+}
+
 static const struct of_device_id mediatek_gsw_match[] = {
        { .compatible = "mediatek,mt7620-gsw" },
        {},
@@ -222,7 +228,9 @@ int mtk_gsw_init(struct fe_priv *priv)
        else
                gsw->ephy_base = 0;
 
-       mt7620_hw_init(gsw);
+       mt7620_mac_init(gsw);
+
+       mt7620_ephy_init(gsw);
 
        if (gsw->irq) {
                request_irq(gsw->irq, gsw_interrupt_mt7620, 0,