realtek: Add specific PHY polling options to support the Zyxel XGS1250/XGS1210

[openwrt/staging/chunkeey.git] / target / linux / realtek / files-5.10 / drivers / net / ethernet / rtl838x_eth.h

diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h
index 223b42fa247931b6797dab005fdcbce254fab8c7..6013de6c73e7743810030efe19b37415398d4ba7 100644 (file)
--- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h
+++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h
@@ -194,6 +194,11 @@
 #define RTL930X_SMI_PORT0_15_POLLING_SEL       (0xCA08)
 #define RTL930X_SMI_PORT16_27_POLLING_SEL      (0xCA0C)
 
+#define RTL930X_SMI_10GPHY_POLLING_REG0_CFG    (0xCBB4)
+#define RTL930X_SMI_10GPHY_POLLING_REG9_CFG    (0xCBB8)
+#define RTL930X_SMI_10GPHY_POLLING_REG10_CFG   (0xCBBC)
+#define RTL930X_SMI_PRVTE_POLLING_CTRL         (0xCA10)
+
 /* Registers of the internal Serdes of the 8390 */
 #define RTL839X_SDS12_13_XSG0                  (0xB800)
 
@@ -290,7 +295,11 @@ inline u32 rtl839x_get_mac_link_sts(int p)
 
 inline u32 rtl930x_get_mac_link_sts(int port)
 {
-       return (sw_r32(RTL930X_MAC_LINK_STS) & BIT(port));
+       u32 link = sw_r32(RTL930X_MAC_LINK_STS);
+
+       link = sw_r32(RTL930X_MAC_LINK_STS);
+       pr_info("%s link state is %08x\n", __func__, link);
+       return link & BIT(port);
 }
 
 inline u32 rtl931x_get_mac_link_sts(int p)