realtek: timer: Activate for RTL930x devices

[openwrt/staging/dedeckeh.git] / target / linux / realtek / rtl930x / config-5.15

diff --git a/target/linux/realtek/rtl930x/config-5.15 b/target/linux/realtek/rtl930x/config-5.15
index 5e036166787ebdb52b8b0ad65b0ddbcaeaecfe3a..35365370efa4656ae3d06c32e9db23c1a38e6464 100644 (file)
--- a/target/linux/realtek/rtl930x/config-5.15
+++ b/target/linux/realtek/rtl930x/config-5.15
@@ -9,7 +9,6 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
 CONFIG_BOARD_SCACHE=y
-CONFIG_CEVT_RTL9300=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_COMMON_CLK=y
 # CONFIG_COMMON_CLK_REALTEK is not set
@@ -33,7 +32,6 @@ CONFIG_CPU_SUPPORTS_MSA=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
 CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
 CONFIG_DEBUG_SECTION_MISMATCH=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DTC=y
@@ -113,11 +111,11 @@ CONFIG_MIGRATION=y
 CONFIG_MIPS=y
 CONFIG_MIPS_ASID_BITS=8
 CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
 # CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
 CONFIG_MIPS_CMDLINE_FROM_DTB=y
 CONFIG_MIPS_CPU_SCACHE=y
 CONFIG_MIPS_EBPF_JIT=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 CONFIG_MIPS_LD_CAN_LINK_VDSO=y
 # CONFIG_MIPS_MT_SMP is not set
@@ -166,7 +164,7 @@ CONFIG_POWER_RESET_GPIO_RESTART=y
 CONFIG_POWER_RESET_SYSCON=y
 CONFIG_PTP_1588_CLOCK_OPTIONAL=y
 CONFIG_RATIONAL=y
-# CONFIG_REALTEK_OTTO_TIMER is not set
+CONFIG_REALTEK_OTTO_TIMER=y
 CONFIG_REALTEK_OTTO_WDT=y
 CONFIG_REALTEK_PHY=y
 CONFIG_REALTEK_SOC_PHY=y
@@ -199,6 +197,8 @@ CONFIG_SYS_SUPPORTS_MIPS16=y
 CONFIG_SYS_SUPPORTS_MULTITHREADING=y
 CONFIG_TARGET_ISA_REV=2
 CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
 CONFIG_TINY_SRCU=y
 CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y
 CONFIG_USE_OF=y