};
static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
-@@ -179,11 +177,19 @@ static int meson8b_init_prg_eth(struct m
+@@ -181,11 +179,19 @@ static int meson8b_init_prg_eth(struct m
{
int ret;
unsigned long clk_rate;
case PHY_INTERFACE_MODE_RGMII_TXID:
/* Generate a 25MHz clock for the PHY */
clk_rate = 25 * 1000 * 1000;
-@@ -196,9 +202,8 @@ static int meson8b_init_prg_eth(struct m
+@@ -198,9 +204,8 @@ static int meson8b_init_prg_eth(struct m
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
PRG_ETH0_INVERTED_RMII_CLK, 0);
break;
case PHY_INTERFACE_MODE_RMII:
-@@ -284,6 +289,11 @@ static int meson8b_dwmac_probe(struct pl
+@@ -286,6 +291,11 @@ static int meson8b_dwmac_probe(struct pl
goto err_remove_config_dt;
}
* stmmac_dma_operation_mode - HW DMA operation mode
* @priv: driver private structure
* Description: it is used for configuring the DMA operation mode register in
-@@ -1686,10 +1687,6 @@ static int stmmac_hw_setup(struct net_de
+@@ -1691,10 +1692,6 @@ static int stmmac_hw_setup(struct net_de
/* Copy the MAC addr into the HW */
priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
/* PS and related bits will be programmed according to the speed */
if (priv->hw->pcs) {
int speed = priv->plat->mac_port_sel_speed;
-@@ -1706,6 +1703,10 @@ static int stmmac_hw_setup(struct net_de
+@@ -1711,6 +1708,10 @@ static int stmmac_hw_setup(struct net_de
/* Initialize the MAC Core */
priv->hw->mac->core_init(priv->hw, dev->mtu);
ret = priv->hw->mac->rx_ipc(priv->hw);
if (!ret) {
netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
-@@ -1726,8 +1727,10 @@ static int stmmac_hw_setup(struct net_de
+@@ -1731,8 +1732,10 @@ static int stmmac_hw_setup(struct net_de
if (init_ptp) {
ret = stmmac_init_ptp(priv);
}
#ifdef CONFIG_DEBUG_FS
-@@ -1741,11 +1744,6 @@ static int stmmac_hw_setup(struct net_de
+@@ -1746,11 +1749,6 @@ static int stmmac_hw_setup(struct net_de
priv->hw->dma->start_tx(priv->ioaddr);
priv->hw->dma->start_rx(priv->ioaddr);
priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
-@@ -2535,7 +2533,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -2547,7 +2545,7 @@ static int stmmac_rx(struct stmmac_priv
if (unlikely(status == discard_frame)) {
priv->dev->stats.rx_errors++;
if (priv->hwts_rx_en && !priv->extend_desc) {
* with timestamp value, hence reinitialize
* them in stmmac_rx_refill() function so that
* device can reuse it.
-@@ -2558,7 +2556,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -2570,7 +2568,7 @@ static int stmmac_rx(struct stmmac_priv
frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
* (preallocated during init) then the packet is
* ignored
*/
-@@ -2778,7 +2776,7 @@ static netdev_features_t stmmac_fix_feat
+@@ -2790,7 +2788,7 @@ static netdev_features_t stmmac_fix_feat
/* Some GMAC devices have a bugged Jumbo frame support that
* needs to have the Tx COE disabled for oversized frames
* (due to limited buffer sizes). In this case we disable
*/
if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
features &= ~NETIF_F_CSUM_MASK;
-@@ -2924,9 +2922,7 @@ static void sysfs_display_ring(void *hea
+@@ -2936,9 +2934,7 @@ static void sysfs_display_ring(void *hea
struct dma_desc *p = (struct dma_desc *)head;
for (i = 0; i < size; i++) {
seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
i, (unsigned int)virt_to_phys(ep),
le32_to_cpu(ep->basic.des0),
-@@ -2935,7 +2931,6 @@ static void sysfs_display_ring(void *hea
+@@ -2947,7 +2943,6 @@ static void sysfs_display_ring(void *hea
le32_to_cpu(ep->basic.des3));
ep++;
} else {
seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
i, (unsigned int)virt_to_phys(ep),
le32_to_cpu(p->des0), le32_to_cpu(p->des1),
-@@ -3005,7 +3000,7 @@ static int stmmac_sysfs_dma_cap_read(str
+@@ -3017,7 +3012,7 @@ static int stmmac_sysfs_dma_cap_read(str
(priv->dma_cap.hash_filter) ? "Y" : "N");
seq_printf(seq, "\tMultiple MAC address registers: %s\n",
(priv->dma_cap.multi_addr) ? "Y" : "N");
(priv->dma_cap.pcs) ? "Y" : "N");
seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
(priv->dma_cap.sma_mdio) ? "Y" : "N");
-@@ -3281,44 +3276,8 @@ int stmmac_dvr_probe(struct device *devi
+@@ -3293,44 +3288,8 @@ int stmmac_dvr_probe(struct device *devi
if ((phyaddr >= 0) && (phyaddr <= 31))
priv->plat->phy_addr = phyaddr;
/* Init MAC and get the capabilities */
ret = stmmac_hw_init(priv);
-@@ -3404,10 +3363,6 @@ error_netdev_register:
+@@ -3416,10 +3375,6 @@ error_netdev_register:
error_mdio_register:
netif_napi_del(&priv->napi);
error_hw_init:
free_netdev(ndev);
return ret;
-@@ -3433,10 +3388,10 @@ int stmmac_dvr_remove(struct device *dev
+@@ -3445,10 +3400,10 @@ int stmmac_dvr_remove(struct device *dev
stmmac_set_mac(priv->ioaddr, false);
netif_carrier_off(ndev);
unregister_netdev(ndev);
if (priv->hw->pcs != STMMAC_PCS_RGMII &&
priv->hw->pcs != STMMAC_PCS_TBI &&
priv->hw->pcs != STMMAC_PCS_RTBI)
-@@ -3485,14 +3440,14 @@ int stmmac_suspend(struct device *dev)
+@@ -3497,14 +3452,14 @@ int stmmac_suspend(struct device *dev)
stmmac_set_mac(priv->ioaddr, false);
pinctrl_pm_select_sleep_state(priv->device);
/* Disable clock in case of PWM is off */
return 0;
}
EXPORT_SYMBOL_GPL(stmmac_suspend);
-@@ -3525,9 +3480,9 @@ int stmmac_resume(struct device *dev)
+@@ -3537,9 +3492,9 @@ int stmmac_resume(struct device *dev)
priv->irq_wake = 0;
} else {
pinctrl_pm_select_default_state(priv->device);
projects / openwrt / staging / dedeckeh.git / blobdiff