X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Ffiles%2Farch%2Fmips%2Fath79%2Fdev-eth.c;h=07cb12c8e9ff20ff03e239cf235bc03397041fa0;hb=e33dcd1cfe105cb0e1ad09887144e4911eac653f;hp=6445023ec45d402b48a41566125d14aca16e7d58;hpb=22c5f96c6bb37b3368ca0f0c828cbe760f5c7f58;p=openwrt%2Fstaging%2Fwigyori.git diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index 6445023ec4..07cb12c8e9 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -407,48 +407,14 @@ static void ath79_set_speed_dummy(int speed) { } -static void ath79_ddr_no_flush(void) -{ -} - static void ath79_ddr_flush_ge0(void) { - ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0); + ath79_ddr_wb_flush(0); } static void ath79_ddr_flush_ge1(void) { - ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1); -} - -static void ar724x_ddr_flush_ge0(void) -{ - ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0); -} - -static void ar724x_ddr_flush_ge1(void) -{ - ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1); -} - -static void ar91xx_ddr_flush_ge0(void) -{ - ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0); -} - -static void ar91xx_ddr_flush_ge1(void) -{ - ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1); -} - -static void ar933x_ddr_flush_ge0(void) -{ - ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0); -} - -static void ar933x_ddr_flush_ge1(void) -{ - ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1); + ath79_ddr_wb_flush(1); } static struct resource ath79_eth0_resources[] = { @@ -830,38 +796,18 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, iounmap(base); } -void __init ath79_setup_qca955x_eth_cfg(u32 mask, - unsigned int rxd, unsigned int rxdv, - unsigned int txd, unsigned int txe) +void __init ath79_setup_qca955x_eth_cfg(u32 mask) { void __iomem *base; - u32 t, m; - - m = QCA955X_ETH_CFG_RGMII_EN | - QCA955X_ETH_CFG_MII_GE0 | - QCA955X_ETH_CFG_GMII_GE0 | - QCA955X_ETH_CFG_MII_GE0_MASTER | - QCA955X_ETH_CFG_MII_GE0_SLAVE | - QCA955X_ETH_CFG_GE0_ERR_EN | - QCA955X_ETH_CFG_GE0_SGMII | - QCA955X_ETH_CFG_RMII_GE0 | - QCA955X_ETH_CFG_MII_CNTL_SPEED | - QCA955X_ETH_CFG_RMII_GE0_MASTER; - m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; - m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; - m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; - m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; + u32 t; base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); - t &= ~m; + t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII); + t |= mask; - t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; - t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; - t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; - t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); @@ -899,26 +845,25 @@ void __init ath79_register_eth(unsigned int id) return; } + if (id == 0) + pdata->ddr_flush = ath79_ddr_flush_ge0; + else + pdata->ddr_flush = ath79_ddr_flush_ge1; + switch (ath79_soc) { case ATH79_SOC_AR7130: - if (id == 0) { - pdata->ddr_flush = ath79_ddr_flush_ge0; + if (id == 0) pdata->set_speed = ath79_set_speed_ge0; - } else { - pdata->ddr_flush = ath79_ddr_flush_ge1; + else pdata->set_speed = ath79_set_speed_ge1; - } break; case ATH79_SOC_AR7141: case ATH79_SOC_AR7161: - if (id == 0) { - pdata->ddr_flush = ath79_ddr_flush_ge0; + if (id == 0) pdata->set_speed = ath79_set_speed_ge0; - } else { - pdata->ddr_flush = ath79_ddr_flush_ge1; + else pdata->set_speed = ath79_set_speed_ge1; - } pdata->has_gbit = 1; break; @@ -926,12 +871,10 @@ void __init ath79_register_eth(unsigned int id) if (id == 0) { pdata->reset_bit |= AR724X_RESET_GE0_MDIO | AR71XX_RESET_GE0_PHY; - pdata->ddr_flush = ar724x_ddr_flush_ge0; pdata->set_speed = ar7242_set_speed_ge0; } else { pdata->reset_bit |= AR724X_RESET_GE1_MDIO | AR71XX_RESET_GE1_PHY; - pdata->ddr_flush = ar724x_ddr_flush_ge1; pdata->set_speed = ath79_set_speed_dummy; } pdata->has_gbit = 1; @@ -954,18 +897,17 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR7240: if (id == 0) { pdata->reset_bit |= AR71XX_RESET_GE0_PHY; - pdata->ddr_flush = ar724x_ddr_flush_ge0; pdata->set_speed = ath79_set_speed_dummy; pdata->phy_mask = BIT(4); } else { pdata->reset_bit |= AR71XX_RESET_GE1_PHY; - pdata->ddr_flush = ar724x_ddr_flush_ge1; pdata->set_speed = ath79_set_speed_dummy; pdata->speed = SPEED_1000; pdata->duplex = DUPLEX_FULL; pdata->switch_data = &ath79_switch_data; + pdata->use_flow_control = 1; ath79_switch_data.phy_poll_mask |= BIT(4); } @@ -982,27 +924,15 @@ void __init ath79_register_eth(unsigned int id) pdata->fifo_cfg3 = 0x01f00140; break; - case ATH79_SOC_AR9130: - if (id == 0) { - pdata->ddr_flush = ar91xx_ddr_flush_ge0; - pdata->set_speed = ar91xx_set_speed_ge0; - } else { - pdata->ddr_flush = ar91xx_ddr_flush_ge1; - pdata->set_speed = ar91xx_set_speed_ge1; - } - pdata->is_ar91xx = 1; - break; - case ATH79_SOC_AR9132: - if (id == 0) { - pdata->ddr_flush = ar91xx_ddr_flush_ge0; + pdata->has_gbit = 1; + /* fall through */ + case ATH79_SOC_AR9130: + if (id == 0) pdata->set_speed = ar91xx_set_speed_ge0; - } else { - pdata->ddr_flush = ar91xx_ddr_flush_ge1; + else pdata->set_speed = ar91xx_set_speed_ge1; - } pdata->is_ar91xx = 1; - pdata->has_gbit = 1; break; case ATH79_SOC_AR9330: @@ -1010,20 +940,19 @@ void __init ath79_register_eth(unsigned int id) if (id == 0) { pdata->reset_bit = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO; - pdata->ddr_flush = ar933x_ddr_flush_ge0; pdata->set_speed = ath79_set_speed_dummy; pdata->phy_mask = BIT(4); } else { pdata->reset_bit = AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO; - pdata->ddr_flush = ar933x_ddr_flush_ge1; pdata->set_speed = ath79_set_speed_dummy; pdata->speed = SPEED_1000; pdata->has_gbit = 1; pdata->duplex = DUPLEX_FULL; pdata->switch_data = &ath79_switch_data; + pdata->use_flow_control = 1; ath79_switch_data.phy_poll_mask |= BIT(4); } @@ -1058,7 +987,6 @@ void __init ath79_register_eth(unsigned int id) ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH); } - pdata->ddr_flush = ath79_ddr_no_flush; pdata->has_gbit = 1; pdata->is_ar724x = 1; @@ -1089,11 +1017,11 @@ void __init ath79_register_eth(unsigned int id) pdata->speed = SPEED_1000; pdata->duplex = DUPLEX_FULL; pdata->switch_data = &ath79_switch_data; + pdata->use_flow_control = 1; ath79_switch_data.phy_poll_mask |= BIT(4); } - pdata->ddr_flush = ath79_ddr_no_flush; pdata->has_gbit = 1; pdata->is_ar724x = 1; @@ -1117,7 +1045,6 @@ void __init ath79_register_eth(unsigned int id) pdata->set_speed = qca955x_set_speed_sgmii; } - pdata->ddr_flush = ath79_ddr_no_flush; pdata->has_gbit = 1; pdata->is_ar724x = 1; @@ -1159,13 +1086,13 @@ void __init ath79_register_eth(unsigned int id) pdata->speed = SPEED_1000; pdata->duplex = DUPLEX_FULL; + pdata->use_flow_control = 1; /* reset the built-in switch */ ath79_device_reset_set(AR934X_RESET_ETH_SWITCH); ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH); } - pdata->ddr_flush = ath79_ddr_no_flush; pdata->has_gbit = 1; pdata->is_ar724x = 1;