X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Ffiles%2Farch%2Fmips%2Fath79%2Fmach-rbspi.c;h=cfd7373164eeea274462e7cee61bf8f33d4eb59a;hb=82626cc145610b8b6485d650693629ef0b943505;hp=3f68b94bcdf0f7bdd7ada6071ae1faa76a74172e;hpb=e1f3cf7ede923312a09fd37195b059a31072cd52;p=openwrt%2Fopenwrt.git diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c index 3f68b94bcd..cfd7373164 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c @@ -1,28 +1,34 @@ /* * MikroTik SPI-NOR RouterBOARDs support * + * - MikroTik RouterBOARD mAP 2nD * - MikroTik RouterBOARD mAP L-2nD * - MikroTik RouterBOARD 941L-2nD * - MikroTik RouterBOARD 951Ui-2nD + * - MikroTik RouterBOARD 952Ui-5ac2nD + * - MikroTik RouterBOARD 962UiGS-5HacT2HnT * - MikroTik RouterBOARD 750UP r2 + * - MikroTik RouterBOARD 750P-PBr2 * - MikroTik RouterBOARD 750 r2 * - MikroTik RouterBOARD LHG 5nD + * - MikroTik RouterBOARD wAP2nD * * Preliminary support for the following hardware - * - MikroTik RouterBOARD wAP2nD * - MikroTik RouterBOARD cAP2nD - * - MikroTik RouterBOARD mAP2nD * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same * hardware as the mAP L-2nD. It is unknown if they share the same board * identifier. * * Copyright (C) 2017 Thibaut VARENE + * Copyright (C) 2016 David Hutchison + * Copyright (C) 2017 Ryan Mounce * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation. */ +#include #include #include #include @@ -34,6 +40,8 @@ #include #include +#include + #include #include #include @@ -47,6 +55,7 @@ #include "dev-usb.h" #include "dev-wmac.h" #include "machtypes.h" +#include "pci.h" #include "routerboot.h" #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */ @@ -59,6 +68,7 @@ #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */ #define RBSPI_HAS_POE BIT(5) #define RBSPI_HAS_MDIO1 BIT(6) +#define RBSPI_HAS_PCI BIT(7) #define RB_ROUTERBOOT_OFFSET 0x0000 #define RB_BIOS_SIZE 0x1000 @@ -126,6 +136,7 @@ static struct flash_platform_data rbspi_spi_flash_data = { /* Several boards only have a single reset button wired to GPIO 16 */ #define RBSPI_GPIO_BTN_RESET16 16 +#define RBSPI_GPIO_BTN_RESET20 20 static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = { { @@ -138,6 +149,17 @@ static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = { }, }; +static struct gpio_keys_button rbspi_gpio_keys_reset20[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL, + .gpio = RBSPI_GPIO_BTN_RESET20, + .active_low = 1, + }, +}; + /* RB mAP L-2nD gpios */ #define RBMAPL_GPIO_LED_POWER 17 #define RBMAPL_GPIO_LED_USER 14 @@ -231,6 +253,83 @@ static struct gpio_led rb952_leds[] __initdata = { }, }; + +/* RB 962UiGS-5HacT2HnT gpios */ +#define RB962_GPIO_POE_STATUS 2 +#define RB962_GPIO_POE_POWER 3 +#define RB962_GPIO_LED_USER 12 +#define RB962_GPIO_USB_POWER 13 + +static struct gpio_led rb962_leds_gpio[] __initdata = { + { + .name = "rb:green:user", + .gpio = RB962_GPIO_LED_USER, + .active_low = 1, + }, +}; + +static const struct ar8327_led_info rb962_leds_ar8327[] = { + AR8327_LED_INFO(PHY0_0, HW, "rb:green:port1"), + AR8327_LED_INFO(PHY1_0, HW, "rb:green:port2"), + AR8327_LED_INFO(PHY2_0, HW, "rb:green:port3"), + AR8327_LED_INFO(PHY3_0, HW, "rb:green:port4"), + AR8327_LED_INFO(PHY4_0, HW, "rb:green:port5"), +}; + +static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .mac06_exchange_dis = true, +}; + +static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg = { + /* Use SGMII interface for GMAC6 of the AR8337 switch */ + .mode = AR8327_PAD_MAC_SGMII, + .rxclk_delay_en = true, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_led_cfg rb962_ar8327_led_cfg = { + .led_ctrl0 = 0xc737c737, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static struct ar8327_platform_data rb962_ar8327_data = { + .pad0_cfg = &rb962_ar8327_pad0_cfg, + .pad6_cfg = &rb962_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &rb962_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(rb962_leds_ar8327), + .leds = rb962_leds_ar8327, +}; + +static struct mdio_board_info rb962_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb962_ar8327_data, + }, +}; + /* RB wAP-2nD gpios */ #define RBWAP_GPIO_LED_USER 14 #define RBWAP_GPIO_LED_WLAN 11 @@ -306,7 +405,7 @@ static struct gpio_led rbmap_leds[] __initdata = { .active_low = 1, }, { .name = "rb:green:eth2", - .gpio = RBMAP_GPIO_LED_WLAN, + .gpio = RBMAP_GPIO_LED_LAN2, .active_low = 1, }, { .name = "rb:red:poe_out", @@ -389,6 +488,7 @@ static struct gpio_keys_button rblhg_gpio_keys[] __initdata = { static struct gen_74x164_chip_platform_data rbspi_ssr_data = { .base = RBSPI_SSR_GPIO_BASE, + .num_registers = 1, }; /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */ @@ -490,6 +590,9 @@ static void __init rbspi_peripherals_setup(u32 flags) if (flags & RBSPI_HAS_USB) ath79_register_usb(); + + if (flags & RBSPI_HAS_PCI) + ath79_register_pci(); } /* @@ -597,7 +700,7 @@ static void __init rbhapl_setup(void) } /* - * The hAP, hEX lite and hEX PoE lite share the same platform + * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform */ static void __init rbspi_952_750r2_setup(u32 flags) { @@ -606,8 +709,11 @@ static void __init rbspi_952_750r2_setup(u32 flags) rbspi_peripherals_setup(flags); - /* GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 */ - rbspi_network_setup(flags, 1, 5, 0); + /* + * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP), + * WLAN1 MAC IS HW MAC + 6 (hAP ac lite) + */ + rbspi_network_setup(flags, 1, 5, 6); if (flags & RBSPI_HAS_USB) gpio_request_one(RB952_GPIO_USB_POWER, @@ -628,22 +734,30 @@ static void __init rbspi_952_750r2_setup(u32 flags) } /* - * Init the hAP hardware (QCA953x). + * Init the hAP (ac lite) hardware (QCA953x). * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned * to LAN on the casing, and port 1 being assigned to "internet" (WAN). * Port 1 is connected to PHY4 (the ports are labelled in reverse physical * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the * internal switch for the LAN ports. * The device also has USB, PoE output and an SSR used for LED multiplexing. + * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a + * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1. */ static void __init rb952_setup(void) { - u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_WAN4 | RBSPI_HAS_USB | + u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB | RBSPI_HAS_SSR | RBSPI_HAS_POE; if (rbspi_platform_setup()) return; + /* differentiate the hAP from the hAP ac lite */ + if (strstr(mips_get_machine_name(), "952Ui-5ac2nD")) + flags |= RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI; + else + flags |= RBSPI_HAS_WLAN0; + rbspi_952_750r2_setup(flags); } @@ -651,7 +765,8 @@ static void __init rb952_setup(void) * Init the hEX (PoE) lite hardware (QCA953x). * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only - * without USB and POE. It shares the same bootloader board identifier. + * without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE + * lite, only without USB. It shares the same bootloader board identifier. */ static void __init rb750upr2_setup(void) { @@ -664,9 +779,75 @@ static void __init rb750upr2_setup(void) if (strstr(mips_get_machine_name(), "750UP r2")) flags |= RBSPI_HAS_USB | RBSPI_HAS_POE; + /* differentiate the Powerbox from the hEX lite */ + else if (strstr(mips_get_machine_name(), "750P r2")) + flags |= RBSPI_HAS_POE; + rbspi_952_750r2_setup(flags); } +/* + * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558). + * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is + * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the + * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order. + * The SFP cage is not assigned by default on RouterOS. Extra work is required + * to support this interface as it is directly connected to the SoC (eth1). + * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio + * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however + * they are not attached to GPIOs, extra work is required to support these. + * PoE and USB output power control is supported. + */ +static void __init rb962_setup(void) +{ + u32 flags = RBSPI_HAS_USB | RBSPI_HAS_POE | RBSPI_HAS_PCI; + + if (rbspi_platform_setup()) + return; + + rbspi_peripherals_setup(flags); + + /* Do not call rbspi_network_setup as we have a discrete switch chip */ + ath79_eth0_pll_data.pll_1000 = 0xae000000; + ath79_eth0_pll_data.pll_100 = 0xa0000101; + ath79_eth0_pll_data.pll_10 = 0xa0001313; + + ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(rb962_mdio0_info, + ARRAY_SIZE(rb962_mdio0_info)); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_register_eth(0); + + /* WLAN1 MAC is HW MAC + 7 */ + rbspi_wlan_init(1, 7); + + if (flags & RBSPI_HAS_USB) + gpio_request_one(RB962_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */ + if (flags & RBSPI_HAS_POE) + gpio_request_one(RB962_GPIO_POE_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW | + GPIOF_EXPORT_DIR_FIXED, + "POE power"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio), + rb962_leds_gpio); + + /* This device has a single reset button as gpio 20 */ + ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rbspi_gpio_keys_reset20), + rbspi_gpio_keys_reset20); +} + /* * Init the LHG hardware (AR9344). * The LHG 5nD has a single ethernet port connected to PHY0. @@ -692,7 +873,7 @@ static void __init rblhg_setup(void) } /* - * Init the wAP hardware (EXPERIMENTAL). + * Init the wAP hardware. * The wAP 2nD has a single ethernet port. */ static void __init rbwap_setup(void) @@ -708,6 +889,11 @@ static void __init rbwap_setup(void) rbspi_network_setup(flags, 0, 1, 0); ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds); + + /* wAP has a single reset button as GPIO 16 */ + ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rbspi_gpio_keys_reset16), + rbspi_gpio_keys_reset16); } /* @@ -734,13 +920,14 @@ static void __init rbcap_setup(void) } /* - * Init the mAP hardware (EXPERIMENTAL). - * The mAP 2nD has two ethernet ports, PoE output and an SSR for LED - * multiplexing. + * Init the mAP hardware. + * The mAP 2nD has two ethernet ports, PoE output, SSR for LED + * multiplexing and USB port. */ static void __init rbmap_setup(void) { - u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_SSR | RBSPI_HAS_POE; + u32 flags = RBSPI_HAS_USB | RBSPI_HAS_WLAN0 | + RBSPI_HAS_SSR | RBSPI_HAS_POE; if (rbspi_platform_setup()) return; @@ -753,16 +940,29 @@ static void __init rbmap_setup(void) if (flags & RBSPI_HAS_POE) gpio_request_one(RBMAP_GPIO_POE_POWER, - GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, "POE power"); + /* USB power GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */ + if (flags & RBSPI_HAS_USB) + gpio_request_one(RBMAP_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW | + GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds); + + /* mAP 2nD has a single reset button as gpio 16 */ + ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rbspi_gpio_keys_reset16), + rbspi_gpio_keys_reset16); } MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup); MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup); MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup); +MIPS_MACHINE_NONAME(ATH79_MACH_RB_962, "962", rb962_setup); MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup); MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup); MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup);