X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Fbrcm2708%2Fpatches-4.19%2F950-0732-drm-vc4-Add-support-for-YUV-color-encodings-and-rang.patch;fp=target%2Flinux%2Fbrcm2708%2Fpatches-4.19%2F950-0732-drm-vc4-Add-support-for-YUV-color-encodings-and-rang.patch;h=0000000000000000000000000000000000000000;hb=84d555aa74434392b682fd9eb0fa701c89a046d6;hp=76129fec22f5c47618695e0d5fa35ebfbc173306;hpb=953973c2991e8640549a55df7a0574a1abac8644;p=openwrt%2Fopenwrt.git diff --git a/target/linux/brcm2708/patches-4.19/950-0732-drm-vc4-Add-support-for-YUV-color-encodings-and-rang.patch b/target/linux/brcm2708/patches-4.19/950-0732-drm-vc4-Add-support-for-YUV-color-encodings-and-rang.patch deleted file mode 100644 index 76129fec22..0000000000 --- a/target/linux/brcm2708/patches-4.19/950-0732-drm-vc4-Add-support-for-YUV-color-encodings-and-rang.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 799c83fb9b72bcd473099e3da1395c92a5a581ff Mon Sep 17 00:00:00 2001 -From: Dave Stevenson -Date: Tue, 17 Sep 2019 18:28:17 +0100 -Subject: [PATCH] drm/vc4: Add support for YUV color encodings and - ranges - -The BT601/BT709 color encoding and limited vs full -range properties were not being exposed, defaulting -always to BT601 limited range. - -Expose the parameters and set the registers appropriately. - -Signed-off-by: Dave Stevenson ---- - drivers/gpu/drm/vc4/vc4_plane.c | 72 +++++++++++++++++++++++++++++++-- - drivers/gpu/drm/vc4/vc4_regs.h | 3 ++ - 2 files changed, 72 insertions(+), 3 deletions(-) - ---- a/drivers/gpu/drm/vc4/vc4_plane.c -+++ b/drivers/gpu/drm/vc4/vc4_plane.c -@@ -500,6 +500,53 @@ static void vc4_write_scaling_parameters - } - } - -+/* The colorspace conversion matrices are held in 3 entries in the dlist. -+ * Create an array of them, with entries for each full and limited mode, and -+ * each supported colorspace. -+ */ -+#define VC4_LIMITED_RANGE 0 -+#define VC4_FULL_RANGE 1 -+ -+static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = { -+ { -+ /* Limited range */ -+ { -+ /* BT601 */ -+ SCALER_CSC0_ITR_R_601_5, -+ SCALER_CSC1_ITR_R_601_5, -+ SCALER_CSC2_ITR_R_601_5, -+ }, { -+ /* BT709 */ -+ SCALER_CSC0_ITR_R_709_3, -+ SCALER_CSC1_ITR_R_709_3, -+ SCALER_CSC2_ITR_R_709_3, -+ }, { -+ /* BT2020. Not supported yet - copy 601 */ -+ SCALER_CSC0_ITR_R_601_5, -+ SCALER_CSC1_ITR_R_601_5, -+ SCALER_CSC2_ITR_R_601_5, -+ } -+ }, { -+ /* Full range */ -+ { -+ /* JFIF */ -+ SCALER_CSC0_JPEG_JFIF, -+ SCALER_CSC1_JPEG_JFIF, -+ SCALER_CSC2_JPEG_JFIF, -+ }, { -+ /* BT709 */ -+ SCALER_CSC0_ITR_R_709_3_FR, -+ SCALER_CSC1_ITR_R_709_3_FR, -+ SCALER_CSC2_ITR_R_709_3_FR, -+ }, { -+ /* BT2020. Not supported yet - copy JFIF */ -+ SCALER_CSC0_JPEG_JFIF, -+ SCALER_CSC1_JPEG_JFIF, -+ SCALER_CSC2_JPEG_JFIF, -+ } -+ } -+}; -+ - /* Writes out a full display list for an active plane to the plane's - * private dlist state. - */ -@@ -760,9 +807,20 @@ static int vc4_plane_mode_set(struct drm - - /* Colorspace conversion words */ - if (vc4_state->is_yuv) { -- vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5); -- vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5); -- vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5); -+ enum drm_color_encoding color_encoding = state->color_encoding; -+ enum drm_color_range color_range = state->color_range; -+ const u32 *ccm; -+ -+ if (color_encoding >= DRM_COLOR_ENCODING_MAX) -+ color_encoding = DRM_COLOR_YCBCR_BT601; -+ if (color_range >= DRM_COLOR_RANGE_MAX) -+ color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; -+ -+ ccm = colorspace_coeffs[color_range][color_encoding]; -+ -+ vc4_dlist_write(vc4_state, ccm[0]); -+ vc4_dlist_write(vc4_state, ccm[1]); -+ vc4_dlist_write(vc4_state, ccm[2]); - } - - if (vc4_state->x_scaling[0] != VC4_SCALING_NONE || -@@ -1116,5 +1174,13 @@ struct drm_plane *vc4_plane_init(struct - - drm_plane_create_alpha_property(plane); - -+ drm_plane_create_color_properties(plane, -+ BIT(DRM_COLOR_YCBCR_BT601) | -+ BIT(DRM_COLOR_YCBCR_BT709), -+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | -+ BIT(DRM_COLOR_YCBCR_FULL_RANGE), -+ DRM_COLOR_YCBCR_BT709, -+ DRM_COLOR_YCBCR_LIMITED_RANGE); -+ - return plane; - } ---- a/drivers/gpu/drm/vc4/vc4_regs.h -+++ b/drivers/gpu/drm/vc4/vc4_regs.h -@@ -972,6 +972,7 @@ enum hvs_pixel_format { - #define SCALER_CSC0_ITR_R_601_5 0x00f00000 - #define SCALER_CSC0_ITR_R_709_3 0x00f00000 - #define SCALER_CSC0_JPEG_JFIF 0x00000000 -+#define SCALER_CSC0_ITR_R_709_3_FR 0x00000000 - - /* S2.8 contribution of Cb to Green */ - #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22) -@@ -988,6 +989,7 @@ enum hvs_pixel_format { - #define SCALER_CSC1_ITR_R_601_5 0xe73304a8 - #define SCALER_CSC1_ITR_R_709_3 0xf2b784a8 - #define SCALER_CSC1_JPEG_JFIF 0xea34a400 -+#define SCALER_CSC1_ITR_R_709_3_FR 0xe23d0400 - - /* S2.8 contribution of Cb to Red */ - #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20) -@@ -1001,6 +1003,7 @@ enum hvs_pixel_format { - #define SCALER_CSC2_ITR_R_601_5 0x00066204 - #define SCALER_CSC2_ITR_R_709_3 0x00072a1c - #define SCALER_CSC2_JPEG_JFIF 0x000599c5 -+#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb - - #define SCALER_TPZ0_VERT_RECALC BIT(31) - #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)