X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Fgeneric%2Fbackport-6.1%2F790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch;fp=target%2Flinux%2Fgeneric%2Fbackport-6.1%2F790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch;h=3667dbf54a4d37900416a30253324e4a20054b58;hb=401a6ccfaf835da0008f1d7a01b7757e063777ff;hp=0000000000000000000000000000000000000000;hpb=d668c74fe6efb546f0fd65f0334a3f0bd7bf5df4;p=openwrt%2Fopenwrt.git diff --git a/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch b/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch new file mode 100644 index 0000000000..3667dbf54a --- /dev/null +++ b/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch @@ -0,0 +1,36 @@ +From 58a94eb63233bb2ede13b183b6a6a03aa0a2dfc3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Tue, 6 Feb 2024 01:08:07 +0300 +Subject: [PATCH 35/48] net: dsa: mt7530: correct port capabilities of MT7988 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +On the switch on the MT7988 SoC, as shown in Block Diagram 8.1.1.3 on page +125 of "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open +Version) v0.1", there are only 4 PHYs. That's port 0 to 3. Set the case for +ports which connect to switch PHYs to '0 ... 3'. + +Port 4 and 5 are not used at all in this design. + +Link: https://wiki.banana-pi.org/Banana_Pi_BPI-R4#Documents [1] +Acked-by: Daniel Golle +Reviewed-by: Vladimir Oltean +Signed-off-by: Arınç ÜNAL +Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-6-d7d92a185cb1@arinc9.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/mt7530.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2604,7 +2604,7 @@ static void mt7988_mac_port_get_caps(str + + switch (port) { + /* Ports which are connected to switch PHYs. There is no MII pinout. */ +- case 0 ... 4: ++ case 0 ... 3: + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + break;