X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Fipq806x%2Fpatches%2F0135-spi-qup-Add-support-for-v1.1.1.patch;h=86cce6132208d472a32cb873f21f22f92908ba21;hb=02629d8f87303a03e3ac36f48c508242d9b8cb09;hp=c1ccc21197c996b22ab76eb2456e92483f383ab3;hpb=7be0ed78e7cf578aa89996d408703ea2ab79a1e8;p=openwrt%2Fstaging%2Fstintel.git diff --git a/target/linux/ipq806x/patches/0135-spi-qup-Add-support-for-v1.1.1.patch b/target/linux/ipq806x/patches/0135-spi-qup-Add-support-for-v1.1.1.patch index c1ccc21197..86cce61322 100644 --- a/target/linux/ipq806x/patches/0135-spi-qup-Add-support-for-v1.1.1.patch +++ b/target/linux/ipq806x/patches/0135-spi-qup-Add-support-for-v1.1.1.patch @@ -11,11 +11,9 @@ Signed-off-by: Andy Gross drivers/spi/spi-qup.c | 36 ++++++++++++-------- 2 files changed, 27 insertions(+), 15 deletions(-) -diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt -index bee6ff2..e2c88df 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt -@@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz, up to four chip selects, programmable +@@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz, data path from 4 bits to 32 bits and numerous protocol variants. Required properties: @@ -28,8 +26,6 @@ index bee6ff2..e2c88df 100644 - reg: Should contain base register location and length - interrupts: Interrupt number used by this controller -diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c -index a404298..c137226 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -142,6 +142,7 @@ struct spi_qup { @@ -40,7 +36,7 @@ index a404298..c137226 100644 }; -@@ -420,7 +421,9 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) +@@ -420,7 +421,9 @@ static int spi_qup_io_config(struct spi_ config |= QUP_CONFIG_SPI_MODE; writel_relaxed(config, controller->base + QUP_CONFIG); @@ -51,7 +47,7 @@ index a404298..c137226 100644 return 0; } -@@ -486,7 +489,7 @@ static int spi_qup_probe(struct platform_device *pdev) +@@ -486,7 +489,7 @@ static int spi_qup_probe(struct platform struct resource *res; struct device *dev; void __iomem *base; @@ -60,7 +56,7 @@ index a404298..c137226 100644 int ret, irq, size; dev = &pdev->dev; -@@ -529,15 +532,6 @@ static int spi_qup_probe(struct platform_device *pdev) +@@ -529,15 +532,6 @@ static int spi_qup_probe(struct platform return ret; } @@ -76,7 +72,7 @@ index a404298..c137226 100644 master = spi_alloc_master(dev, sizeof(struct spi_qup)); if (!master) { clk_disable_unprepare(cclk); -@@ -570,6 +564,10 @@ static int spi_qup_probe(struct platform_device *pdev) +@@ -570,6 +564,10 @@ static int spi_qup_probe(struct platform controller->cclk = cclk; controller->irq = irq; @@ -87,7 +83,7 @@ index a404298..c137226 100644 spin_lock_init(&controller->lock); init_completion(&controller->done); -@@ -593,8 +591,8 @@ static int spi_qup_probe(struct platform_device *pdev) +@@ -593,8 +591,8 @@ static int spi_qup_probe(struct platform size = QUP_IO_M_INPUT_FIFO_SIZE(iomode); controller->in_fifo_sz = controller->in_blk_sz * (2 << size); @@ -98,7 +94,7 @@ index a404298..c137226 100644 controller->out_blk_sz, controller->out_fifo_sz); writel_relaxed(1, base + QUP_SW_RESET); -@@ -607,10 +605,19 @@ static int spi_qup_probe(struct platform_device *pdev) +@@ -607,10 +605,19 @@ static int spi_qup_probe(struct platform writel_relaxed(0, base + QUP_OPERATIONAL); writel_relaxed(0, base + QUP_IO_M_MODES); @@ -119,7 +115,7 @@ index a404298..c137226 100644 writel_relaxed(0, base + SPI_CONFIG); writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); -@@ -732,6 +739,7 @@ static int spi_qup_remove(struct platform_device *pdev) +@@ -732,6 +739,7 @@ static int spi_qup_remove(struct platfor } static struct of_device_id spi_qup_dt_match[] = { @@ -127,6 +123,3 @@ index a404298..c137226 100644 { .compatible = "qcom,spi-qup-v2.1.1", }, { .compatible = "qcom,spi-qup-v2.2.1", }, { } --- -1.7.10.4 -