X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Framips%2Fdts%2Fmt7621.dtsi;h=6d3c782430cc6bbd3ec7c03406d6066da1434294;hb=c073bf6bdf74db663dddf7806c2fd2488f836be8;hp=9fa9d0a5fa37455cd907fc918273a857c914368d;hpb=b4b0a55aabd2839c5c995bb226f528efca73eea5;p=openwrt%2Fopenwrt.git

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 9fa9d0a5fa..6d3c782430 100644
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -1,7 +1,7 @@
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
-	compatible = "ralink,mtk7620a-soc";
+	compatible = "mediatek,mtk7621-soc";
 
 	cpus {
 		cpu@0 {
@@ -72,8 +72,8 @@
 			compatible = "ns16550a";
 			reg = <0xc00 0x100>;
 
-/*			interrupt-parent = <&gic>;
-			interrupts = <26>;*/
+			interrupt-parent = <&gic>;
+			interrupts = <26>;
 
 			reg-shift = <2>;
 			reg-io-width = <4>;
@@ -92,8 +92,8 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-/*			pinctrl-names = "default";
-			pinctrl-0 = <&spi_pins>;*/
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi_pins>;
 
 			m25p80@0 {
 				#address-cells = <1>;
@@ -136,13 +136,91 @@
 		};
 	};
 
+	pinctrl {
+		compatible = "ralink,rt2880-pinmux";
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+		state_default: pinctrl0 {
+		};
+		spi_pins: spi {
+			spi {
+				ralink,group = "spi";
+				ralink,function = "spi";
+			};
+		};
+		i2c_pins: i2c {
+			i2c {
+				lantiq,group = "i2c";
+				lantiq,function = "i2c";
+			};
+		};
+		uart1_pins: uart1 {
+			uart1 {
+				ralink,group = "uart1";
+				ralink,function = "uart";
+			};
+		};
+		uart2_pins: uart2 {
+			uart2 {
+				ralink,group = "uart2";
+				ralink,function = "uart";
+			};
+		};
+		uart3_pins: uart3 {
+			uart3 {
+				ralink,group = "uart3";
+				ralink,function = "uart";
+			};
+		};
+		rgmii1_pins: rgmii1 {
+			rgmii1 {
+				ralink,group = "rgmii1";
+				ralink,function = "rgmii";
+			};
+		};
+		rgmii2_pins: rgmii2 {
+			rgmii2 {
+				ralink,group = "rgmii2";
+				ralink,function = "rgmii";
+			};
+		};
+		mdio_pins: mdio {
+			mdio {
+				ralink,group = "mdio";
+				ralink,function = "mdio";
+			};
+		};
+		pcie_pins: pcie {
+			pcie {
+				ralink,group = "pcie";
+				ralink,function = "pcie rst";
+			};
+		};
+		nand_pins: nand {
+			spi-nand {
+				ralink,group = "spi";
+				ralink,function = "nand";
+			};
+			sdhci-nand {
+				ralink,group = "sdhci";
+				ralink,function = "nand";
+			};
+		};
+		sdhci_pins: sdhci {
+			sdhci {
+				ralink,group = "sdhci";
+				ralink,function = "sdhci";
+			};
+		};
+	};
+
 	rstctrl: rstctrl {
 		compatible = "ralink,rt2880-reset";
 		#reset-cells = <1>;
 	};
 
 	sdhci@1E130000 {
-		compatible = "ralink,mt7620a-sdhci";
+		compatible = "ralink,mt7620-sdhci";
 		reg = <0x1E130000 4000>;
 
 		interrupt-parent = <&gic>;
@@ -150,7 +228,7 @@
 	};
 
 	xhci@1E1C0000 {
-		compatible = "xhci-platform1";
+		compatible = "xhci-platform";
 		reg = <0x1E1C0000 4000>;
 
 		interrupt-parent = <&gic>;
@@ -201,28 +279,9 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ralink,port-map = "llllw";
-		
 		interrupt-parent = <&gic>;
 		interrupts = <3>;
 
-/*		resets = <&rstctrl 21 &rstctrl 23>;
-		reset-names = "fe", "esw";
-
-		port@4 {
-			compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
-			reg = <4>;
-
-			status = "disabled";
-		};
-
-		port@5 {
-			compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
-			reg = <5>;
-
-			status = "disabled";
-		};
-*/
 		mdio-bus {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -230,9 +289,6 @@
 			phy1f: ethernet-phy@1f {
 				reg = <0x1f>;
 				phy-mode = "rgmii";
-		
-				interrupt-parent = <&gic>;
-				interrupts = <23>;
 			};
 		};
 	};
@@ -240,6 +296,7 @@
 	gsw@1e110000 {
 		compatible = "ralink,mt7620a-gsw";
 		reg = <0x1e110000 8000>;
-
+		interrupt-parent = <&gic>;
+		interrupts = <23>; 
 	};
 };