X-Git-Url: http://git.openwrt.org/?a=blobdiff_plain;f=target%2Flinux%2Framips%2Fdts%2Fmt7621.dtsi;h=7636f9d8000a55bd453de0dab1db685ef292fabf;hb=66d12ce667ce9cac249736eebfa95786a9ae2a54;hp=bc30597fdd286c600bcd2b50bf249492c412cc8e;hpb=9195d8da355d0d141ac02c9a5269452dc64ffd2d;p=openwrt%2Fopenwrt.git diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index bc30597fdd..7636f9d800 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -1,21 +1,32 @@ +/dts-v1/; + #include +#include +#include / { #address-cells = <1>; #size-cells = <1>; - compatible = "mediatek,mtk7621-soc"; + compatible = "mediatek,mt7621-soc"; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; compatible = "mips,mips1004Kc"; + reg = <0>; }; cpu@1 { + device_type = "cpu"; compatible = "mips,mips1004Kc"; + reg = <1>; }; }; - cpuintc: cpuintc@0 { + cpuintc: cpuintc { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; @@ -26,15 +37,18 @@ serial0 = &uartlite; }; - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; + chosen { + bootargs = "console=ttyS0,57600"; + }; - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; + pll: pll { + compatible = "mediatek,mt7621-pll", "syscon"; + + #clock-cells = <1>; + clock-output-names = "cpu", "bus"; }; - sysclock: sysclock@0 { + sysclock: sysclock { #clock-cells = <0>; compatible = "fixed-clock"; @@ -56,59 +70,92 @@ }; wdt: wdt@100 { - compatible = "mtk,mt7621-wdt"; + compatible = "mediatek,mt7621-wdt"; reg = <0x100 0x100>; }; - gpio@600 { + gpio: gpio@600 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "mediatek,mt7621-gpio"; + gpio-controller; + interrupt-controller; + reg = <0x600 0x100>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + i2c: i2c@900 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x900 0x100>; + + clocks = <&sysclock>; + + resets = <&rstctrl 16>; + reset-names = "i2c"; + #address-cells = <1>; #size-cells = <0>; - compatible = "mtk,mt7621-gpio"; - reg = <0x600 0x100>; + status = "disabled"; - gpio0: bank@0 { - reg = <0>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + }; - gpio1: bank@1 { - reg = <1>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; + i2s: i2s@a00 { + compatible = "mediatek,mt7621-i2s"; + reg = <0xa00 0x100>; - gpio2: bank@2 { - reg = <2>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; + clocks = <&sysclock>; + + resets = <&rstctrl 17>; + reset-names = "i2s"; + + interrupt-parent = <&gic>; + interrupts = ; + + txdma-req = <2>; + rxdma-req = <3>; + + dmas = <&gdma 4>, + <&gdma 6>; + dma-names = "tx", "rx"; + + status = "disabled"; + }; + + systick: systick@500 { + compatible = "ralink,mt7621-systick", "ralink,cevt-systick"; + reg = <0x500 0x10>; + + resets = <&rstctrl 28>; + reset-names = "intc"; + + interrupt-parent = <&gic>; + interrupts = ; }; memc: memc@5000 { compatible = "mtk,mt7621-memc"; - reg = <0x300 0x100>; + reg = <0x5000 0x1000>; }; cpc: cpc@1fbf0000 { - compatible = "mtk,mt7621-cpc"; - reg = <0x1fbf0000 0x8000>; + compatible = "mtk,mt7621-cpc"; + reg = <0x1fbf0000 0x8000>; }; mc: mc@1fbf8000 { - compatible = "mtk,mt7621-mc"; - reg = <0x1fbf8000 0x8000>; - }; + compatible = "mtk,mt7621-mc"; + reg = <0x1fbf8000 0x8000>; + }; uartlite: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; + clock-frequency = <50000000>; interrupt-parent = <&gic>; interrupts = ; @@ -118,13 +165,49 @@ no-loopback-test; }; + uartlite2: uartlite2@d00 { + compatible = "ns16550a"; + reg = <0xd00 0x100>; + + clock-frequency = <50000000>; + + interrupt-parent = <&gic>; + interrupts = ; + + reg-shift = <2>; + reg-io-width = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "disabled"; + }; + + uartlite3: uartlite3@e00 { + compatible = "ns16550a"; + reg = <0xe00 0x100>; + + clock-frequency = <50000000>; + + interrupt-parent = <&gic>; + interrupts = ; + + reg-shift = <2>; + reg-io-width = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + status = "disabled"; + }; + spi0: spi@b00 { - status = "okay"; + status = "disabled"; compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_BUS>; resets = <&rstctrl 18>; reset-names = "spi"; @@ -134,14 +217,40 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_pins>; + }; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0>; - spi-max-frequency = <10000000>; - m25p,chunked-io = <32>; - }; + gdma: gdma@2800 { + compatible = "ralink,rt3883-gdma"; + reg = <0x2800 0x800>; + + resets = <&rstctrl 14>; + reset-names = "dma"; + + interrupt-parent = <&gic>; + interrupts = <0 13 4>; + + #dma-cells = <1>; + #dma-channels = <16>; + #dma-requests = <16>; + + status = "disabled"; + }; + + hsdma: hsdma@7000 { + compatible = "mediatek,mt7621-hsdma"; + reg = <0x7000 0x1000>; + + resets = <&rstctrl 5>; + reset-names = "hsdma"; + + interrupt-parent = <&gic>; + interrupts = <0 11 4>; + + #dma-cells = <1>; + #dma-channels = <1>; + #dma-requests = <1>; + + status = "disabled"; }; }; @@ -153,85 +262,85 @@ state_default: pinctrl0 { }; - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; + i2c_pins: i2c_pins { + i2c_pins { + groups = "i2c"; + function = "i2c"; }; }; - i2c_pins: i2c { - i2c { - ralink,group = "i2c"; - ralink,function = "i2c"; + spi_pins: spi_pins { + spi_pins { + groups = "spi"; + function = "spi"; }; }; uart1_pins: uart1 { uart1 { - ralink,group = "uart1"; - ralink,function = "uart1"; + groups = "uart1"; + function = "uart1"; }; }; uart2_pins: uart2 { uart2 { - ralink,group = "uart2"; - ralink,function = "uart2"; + groups = "uart2"; + function = "uart2"; }; }; uart3_pins: uart3 { uart3 { - ralink,group = "uart3"; - ralink,function = "uart3"; + groups = "uart3"; + function = "uart3"; }; }; rgmii1_pins: rgmii1 { rgmii1 { - ralink,group = "rgmii1"; - ralink,function = "rgmii1"; + groups = "rgmii1"; + function = "rgmii1"; }; }; rgmii2_pins: rgmii2 { rgmii2 { - ralink,group = "rgmii2"; - ralink,function = "rgmii2"; + groups = "rgmii2"; + function = "rgmii2"; }; }; mdio_pins: mdio { mdio { - ralink,group = "mdio"; - ralink,function = "mdio"; + groups = "mdio"; + function = "mdio"; }; }; pcie_pins: pcie { pcie { - ralink,group = "pcie"; - ralink,function = "pcie rst"; + groups = "pcie"; + function = "gpio"; }; }; nand_pins: nand { spi-nand { - ralink,group = "spi"; - ralink,function = "nand1"; + groups = "spi"; + function = "nand1"; }; sdhci-nand { - ralink,group = "sdhci"; - ralink,function = "nand2"; + groups = "sdhci"; + function = "nand2"; }; }; sdhci_pins: sdhci { sdhci { - ralink,group = "sdhci"; - ralink,function = "sdhci"; + groups = "sdhci"; + function = "sdhci"; }; }; }; @@ -241,26 +350,57 @@ #reset-cells = <1>; }; + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + sdhci: sdhci@1E130000 { + status = "disabled"; + compatible = "ralink,mt7620-sdhci"; reg = <0x1E130000 0x4000>; interrupt-parent = <&gic>; interrupts = ; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; }; xhci: xhci@1E1C0000 { - status = "okay"; + #address-cells = <1>; + #size-cells = <0>; compatible = "mediatek,mt8173-xhci"; reg = <0x1e1c0000 0x1000 0x1e1d0700 0x0100>; + reg-names = "mac", "ippc"; clocks = <&sysclock>; clock-names = "sys_ck"; interrupt-parent = <&gic>; interrupts = ; + + /* + * Port 1 of both hubs is one usb slot and referenced here. + * The binding doesn't allow to address individual hubs. + * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci. + */ + xhci_ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + /* + * Only the second usb hub has a second port. That port serves + * ehci and ohci. + */ + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; }; gic: interrupt-controller@1fbc0000 { @@ -275,25 +415,43 @@ timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&pll MT7621_CLK_CPU>; }; }; + nficlock: nficlock { + #clock-cells = <0>; + compatible = "fixed-clock"; + + clock-frequency = <125000000>; + }; + nand: nand@1e003000 { status = "disabled"; - compatible = "mtk,mt7621-nand"; - bank-width = <2>; + compatible = "mediatek,mt7621-nfc"; reg = <0x1e003000 0x800 0x1e003800 0x800>; - #address-cells = <1>; - #size-cells = <1>; + reg-names = "nfi", "ecc"; + + clocks = <&nficlock>; + clock-names = "nfi_clk"; + }; + + ethsys: syscon@1e000000 { + compatible = "mediatek,mt7621-ethsys", + "syscon"; + reg = <0x1e000000 0x1000>; + #clock-cells = <1>; }; ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; + clocks = <&sysclock>; + clock-names = "ethif"; + #address-cells = <1>; #size-cells = <0>; @@ -303,15 +461,87 @@ interrupt-parent = <&gic>; interrupts = ; - mediatek,switch = <&gsw>; + mediatek,ethsys = <ðsys>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + phy-mode = "rgmii-rxid"; + }; - mdio-bus { + mdio: mdio-bus { #address-cells = <1>; #size-cells = <0>; - phy1f: ethernet-phy@1f { + switch0: switch@1f { + compatible = "mediatek,mt7621"; + #address-cells = <1>; + #size-cells = <0>; reg = <0x1f>; - phy-mode = "rgmii"; + mediatek,mcm; + resets = <&rstctrl 2>; + reset-names = "mcm"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + port@0 { + status = "disabled"; + reg = <0>; + label = "lan0"; + }; + + port@1 { + status = "disabled"; + reg = <1>; + label = "lan1"; + }; + + port@2 { + status = "disabled"; + reg = <2>; + label = "lan2"; + }; + + port@3 { + status = "disabled"; + reg = <3>; + label = "lan3"; + }; + + port@4 { + status = "disabled"; + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; }; }; }; @@ -325,9 +555,10 @@ pcie: pcie@1e140000 { compatible = "mediatek,mt7621-pci"; - reg = <0x1e140000 0x100 - 0x1e142000 0x100>; - + reg = <0x1e140000 0x100 /* host-pci bridge registers */ + 0x1e142000 0x100 /* pcie port 0 RC control registers */ + 0x1e143000 0x100 /* pcie port 1 RC control registers */ + 0x1e144000 0x100>; /* pcie port 2 RC control registers */ #address-cells = <3>; #size-cells = <2>; @@ -347,33 +578,51 @@ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; + status = "disabled"; - pcie0 { - reg = <0x0000 0 0 0 0>; + resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; + reset-names = "pcie0", "pcie1", "pcie2"; + clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; + clock-names = "pcie0", "pcie1", "pcie2"; + phys = <&pcie0_phy 1>, <&pcie2_phy 0>; + phy-names = "pcie-phy0", "pcie-phy2"; + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + + pcie0: pcie@0,0 { + reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - - device_type = "pci"; + ranges; + bus-range = <0x00 0xff>; }; - pcie1 { + pcie1: pcie@1,0 { reg = <0x0800 0 0 0 0>; - #address-cells = <3>; #size-cells = <2>; - - device_type = "pci"; + ranges; + bus-range = <0x00 0xff>; }; - pcie2 { + pcie2: pcie@2,0 { reg = <0x1000 0 0 0 0>; - #address-cells = <3>; #size-cells = <2>; - - device_type = "pci"; + ranges; + bus-range = <0x00 0xff>; }; }; + + pcie0_phy: pcie-phy@1e149000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e149000 0x0700>; + #phy-cells = <1>; + }; + + pcie2_phy: pcie-phy@1e14a000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e14a000 0x0700>; + #phy-cells = <1>; + }; };