Compared to the "old" driver:
- Each device must assign a pinctrl setting to the SPI node to allow the
new SPI driver to configure the SPI pins.
While here we are also using separate input and output settings so we
are independent of whether the bootloader configures the pins correctly.
- We use the new "compatible" strings to make the driver choose the
correct number of chip-selects for each SoC.
- The new driver starts counting the chip-selects at 1 (instead of 0, like
the old one did). Thus we have to adjust the devices accordingly.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48293
pinctrl-0 = <&state_default>;
state_default: pinmux {
pinctrl-0 = <&state_default>;
state_default: pinmux {
- spi {
- lantiq,groups = "spi", "spi_cs1";
- lantiq,function = "spi";
- };
asc {
lantiq,groups = "asc";
lantiq,function = "asc";
asc {
lantiq,groups = "asc";
lantiq,function = "asc";
lantiq,open-drain = <1>;
};
};
lantiq,open-drain = <1>;
};
};
+ pins_spi_default: pins_spi_default {
+ spi_in {
+ lantiq,groups = "spi_di";
+ lantiq,function = "spi";
+ };
+ spi_out {
+ lantiq,groups = "spi_do", "spi_clk",
+ "spi_cs1";
+ lantiq,function = "spi";
+ lantiq,output = <1>;
+ };
+ };
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_spi_default>;
+
+ m25p80@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <5000000>;
partition@0 {
spi-max-frequency = <5000000>;
partition@0 {
lantiq,output = <1>;
lantiq,pull = <0>;
};
lantiq,output = <1>;
lantiq,pull = <0>;
};
- spi {
- lantiq,groups = "spi", "spi_cs4";
+ };
+ pins_spi_default: pins_spi_default {
+ spi_in {
+ lantiq,groups = "spi_di";
lantiq,function = "spi";
};
lantiq,function = "spi";
};
+ spi_out {
+ lantiq,groups = "spi_do", "spi_clk",
+ "spi_cs4";
+ lantiq,function = "spi";
+ lantiq,output = <1>;
+ };
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_spi_default>;
+
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <1000000>;
partition@0 {
spi-max-frequency = <1000000>;
partition@0 {
lantiq,groups = "stp";
lantiq,function = "stp";
};
lantiq,groups = "stp";
lantiq,function = "stp";
};
- spi {
- lantiq,groups = "spi", "spi_cs4";
- lantiq,function = "spi";
- };
nand {
lantiq,groups = "nand cle", "nand ale",
"nand rd", "nand rdy";
nand {
lantiq,groups = "nand cle", "nand ale",
"nand rd", "nand rdy";
+ pins_spi_default: pins_spi_default {
+ spi_in {
+ lantiq,groups = "spi_di";
+ lantiq,function = "spi";
+ };
+ spi_out {
+ lantiq,groups = "spi_do", "spi_clk",
+ "spi_cs4";
+ lantiq,function = "spi";
+ lantiq,output = <1>;
+ };
+ };
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_spi_default>;
+
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <1000000>;
partition@0 {
spi-max-frequency = <1000000>;
partition@0 {
pinctrl-0 = <&state_default>;
state_default: pinmux {
pinctrl-0 = <&state_default>;
state_default: pinmux {
- spi {
- lantiq,groups = "spi", "spi_cs4";
- lantiq,function = "spi";
- };
mdio {
lantiq,groups = "mdio";
lantiq,function = "mdio";
mdio {
lantiq,groups = "mdio";
lantiq,function = "mdio";
lantiq,output = <1>;
};
};
lantiq,output = <1>;
};
};
+ pins_spi_default: pins_spi_default {
+ spi_in {
+ lantiq,groups = "spi_di";
+ lantiq,function = "spi";
+ };
+ spi_out {
+ lantiq,groups = "spi_do", "spi_clk",
+ "spi_cs4";
+ lantiq,function = "spi";
+ lantiq,output = <1>;
+ };
+ };
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_spi_default>;
+
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <1000000>;
ath9k_cal: partition@0 {
spi-max-frequency = <1000000>;
ath9k_cal: partition@0 {
lantiq,open-drain = <0>;
lantiq,output = <1>;
};
lantiq,open-drain = <0>;
lantiq,output = <1>;
};
- spi {
- lantiq,groups = "spi", "spi_cs4";
- lantiq,function = "spi";
- };
pcie-rst {
lantiq,pins = "io38";
lantiq,pull = <0>;
lantiq,output = <1>;
};
};
pcie-rst {
lantiq,pins = "io38";
lantiq,pull = <0>;
lantiq,output = <1>;
};
};
+ pins_spi_default: pins_spi_default {
+ spi_in {
+ lantiq,groups = "spi_di";
+ lantiq,function = "spi";
+ };
+ spi_out {
+ lantiq,groups = "spi_do", "spi_clk",
+ "spi_cs4";
+ lantiq,function = "spi";
+ lantiq,output = <1>;
+ };
+ };
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_spi_default>;
+
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <33250000>;
m25p,fast-read;
spi-max-frequency = <33250000>;
m25p,fast-read;
reg = <0x10000000 0xEF00000>;
spi@E100800 {
reg = <0x10000000 0xEF00000>;
spi@E100800 {
- compatible = "lantiq,spi-xway";
+ compatible = "lantiq,ase-spi";
reg = <0xE100800 0x100>;
interrupt-parent = <&icu0>;
interrupts = <24 25 26>;
reg = <0xE100800 0x100>;
interrupt-parent = <&icu0>;
interrupts = <24 25 26>;
+ interrupt-names = "spi_rx", "spi_tx", "spi_err",
+ "spi_frm";
#address-cells = <1>;
#size-cells = <1>;
};
#address-cells = <1>;
#size-cells = <1>;
};
- compatible = "lantiq,spi-xway";
+ compatible = "lantiq,xrx100-spi";
reg = <0xE100800 0x100>;
interrupt-parent = <&icu0>;
interrupts = <22 23 24>;
reg = <0xE100800 0x100>;
interrupt-parent = <&icu0>;
interrupts = <22 23 24>;
+ interrupt-names = "spi_rx", "spi_tx", "spi_err",
+ "spi_frm";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
- compatible = "lantiq,spi-xway";
+ compatible = "lantiq,xrx200-spi";
reg = <0xE100800 0x100>;
interrupt-parent = <&icu0>;
interrupts = <22 23 24>;
reg = <0xE100800 0x100>;
interrupt-parent = <&icu0>;
interrupts = <22 23 24>;
+ interrupt-names = "spi_rx", "spi_tx", "spi_err",
+ "spi_frm";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
CONFIG_RTL8367B_PHY=y
CONFIG_RTL8367_PHY=y
CONFIG_SPI=y
CONFIG_RTL8367B_PHY=y
CONFIG_RTL8367_PHY=y
CONFIG_SPI=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_RTL8367B_PHY=y
CONFIG_RTL8367_PHY=y
CONFIG_SPI=y
CONFIG_RTL8367B_PHY=y
CONFIG_RTL8367_PHY=y
CONFIG_SPI=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y