95672e04 broke booting secondary cores by removing 'qcom,saw' property
from L2 cache node. kpssv2_release_secondary() requires it.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
-diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-index 93647db5d90b..06434fd02d40 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
reg = <0x0>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
reg = <0x0>;
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
reg = <0x1>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
reg = <0x1>;
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
reg = <0x2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
reg = <0x2>;
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
};
acc0: clock-controller@b088000 {
};
acc0: clock-controller@b088000 {
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
+@@ -256,6 +266,12 @@
+ regulator;
+ };
+
++ saw_l2: regulator@b012000 {
++ compatible = "qcom,saw2";
++ reg = <0xb012000 0x1000>;
++ regulator;
++ };
++
+ serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78af000 0x200>;
arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)
arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)
-Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi
-===================================================================
---- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -41,14 +41,7 @@
reg = <0x0>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
@@ -41,14 +41,7 @@
reg = <0x0>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
reg = <0x3>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
+ operating-points-v2 = <&cpu0_opp_table>;
reg = <0x3>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ L2: l2-cache {
+@@ -94,6 +90,28 @@
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-716000000 {
+ opp-hz = /bits/ 64 <716000000>;
+ clock-latency-ns = <256000>;
+ opp-716000000 {
+ opp-hz = /bits/ 64 <716000000>;
+ clock-latency-ns = <256000>;
++ };
++ };
++
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |