++
++ pcie0: pcie-controller@47c00000 {
++ compatible = "plxtech,nas782x-pcie";
++ device_type = "pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ /* flag & space bus address host address size */
++ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
++ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
++ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
++ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
++
++ bus-range = <0x00 0x7f>;
++
++ /* cfg inbound translator */
++ reg = <0x47c00000 0x1000>, <0x47d00000 0x100>;
++
++ phys = <&pcie_phy>;
++ phy-names = "pcie-phy";
++
++ #interrupt-cells = <1>;
++ /* wild card mask, match all bus address & interrupt specifier */
++ /* format: bus address mask, interrupt specifier mask */
++ /* each bit 1 means need match, 0 means ignored when match */
++ interrupt-map-mask = <0 0 0 0>;
++ /* format: a list of: bus address, interrupt specifier,
++ * parent interrupt controller & specifier */
++ interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
++ gpios = <&gpio1 12 0>;
++ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
++ clock-names = "pcie", "busclk";
++ resets = <&reset RESET_PCIEA>;
++ reset-names = "pcie";
++
++ plxtech,pcie-hcsl-bit = <2>;
++ plxtech,pcie-ctrl-offset = <0x120>;
++ plxtech,pcie-outbound-offset = <0x138>;
++ status = "disabled";
++ };
++
++ pcie1: pcie-controller@47e00000 {
++ compatible = "plxtech,nas782x-pcie";
++ device_type = "pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ /* flag & space bus address host address size */
++ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
++ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
++ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
++ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
++
++ bus-range = <0x80 0xff>;
++
++ /* cfg inbound translator */
++ reg = <0x47e00000 0x1000>, <0x47f00000 0x100>;
++
++ phys = <&pcie_phy>;
++ phy-names = "pcie-phy";
++
++ #interrupt-cells = <1>;
++ /* wild card mask, match all bus address & interrupt specifier */
++ /* format: bus address mask, interrupt specifier mask */
++ /* each bit 1 means need match, 0 means ignored when match */
++ interrupt-map-mask = <0 0 0 0>;
++ /* format: a list of: bus address, interrupt specifier,
++ * parent interrupt controller & specifier */
++ interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
++
++ /* gpios = <&gpio1 12 0>; */
++ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
++ clock-names = "pcie", "busclk";
++ resets = <&reset RESET_PCIEB>;
++ reset-names = "pcie";
++
++ plxtech,pcie-hcsl-bit = <3>;
++ plxtech,pcie-ctrl-offset = <0x124>;
++ plxtech,pcie-outbound-offset = <0x174>;
++ status = "disabled";
++ };