+/* common RB SSRs */
+#define RBSPI_SSR_GPIO_BASE 40
+#define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
+
+/* RB 951Ui-2nD gpios */
+#define RB952_SSR_BIT_LED_LAN1 0
+#define RB952_SSR_BIT_LED_LAN2 1
+#define RB952_SSR_BIT_LED_LAN3 2
+#define RB952_SSR_BIT_LED_LAN4 3
+#define RB952_SSR_BIT_LED_LAN5 4
+#define RB952_SSR_BIT_USB_POWER 5
+#define RB952_SSR_BIT_LED_WLAN 6
+#define RB952_GPIO_SSR_CS 11
+#define RB952_GPIO_LED_USER 4
+#define RB952_GPIO_POE_POWER 14
+#define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
+#define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
+#define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
+#define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
+#define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
+#define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
+#define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
+
+static struct gpio_led rb952_leds[] __initdata = {
+ {
+ .name = "rb:green:user",
+ .gpio = RB952_GPIO_LED_USER,
+ .active_low = 0,
+ }, {
+ .name = "rb:blue:wlan",
+ .gpio = RB952_GPIO_LED_WLAN,
+ .active_low = 1,
+ }, {
+ .name = "rb:green:port1",
+ .gpio = RB952_GPIO_LED_LAN1,
+ .active_low = 1,
+ }, {
+ .name = "rb:green:port2",
+ .gpio = RB952_GPIO_LED_LAN2,
+ .active_low = 1,
+ }, {
+ .name = "rb:green:port3",
+ .gpio = RB952_GPIO_LED_LAN3,
+ .active_low = 1,
+ }, {
+ .name = "rb:green:port4",
+ .gpio = RB952_GPIO_LED_LAN4,
+ .active_low = 1,
+ }, {
+ .name = "rb:green:port5",
+ .gpio = RB952_GPIO_LED_LAN5,
+ .active_low = 1,
+ },
+};
+
+static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
+ .base = RBSPI_SSR_GPIO_BASE,
+};
+
+/* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
+static int rbspi_spi_cs_gpios[] = {
+ -ENOENT, /* CS0 is always -ENOENT: natively handled */
+ -ENOENT, /* CS1 can be updated by the code as necessary */
+};
+
+static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
+ .bus_num = 0,
+ .cs_gpios = rbspi_spi_cs_gpios,
+};
+
+/*
+ * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
+ * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
+ */
+static struct spi_board_info rbspi_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "m25p80",
+ .platform_data = &rbspi_spi_flash_data,
+ }, {
+ .bus_num = 0,
+ .chip_select = 1,
+ .max_speed_hz = 25000000,
+ .modalias = "74x164",
+ .platform_data = &rbspi_ssr_data,
+ }
+};
+