DT spec require okay instead of ok in dts files
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
12 files changed:
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
force_gen1 = <1>;
};
nand@1ac00000 {
force_gen1 = <1>;
};
nand@1ac00000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
qcom,id = <1>;
phy-mode = "rgmii";
qcom,id = <1>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
phy-mode = "sgmii";
qcom,id = <2>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
force_gen1 = <1>;
};
pcie2: pci@1b900000 {
force_gen1 = <1>;
};
pcie2: pci@1b900000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
gmac0: ethernet@37000000 {
};
gmac0: ethernet@37000000 {
phy-mode = "rgmii";
qcom,id = <0>;
phy-mode = "rgmii";
qcom,id = <0>;
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
qcom,id = <1>;
mdiobus = <&mdio0>;
phy-mode = "rgmii";
qcom,id = <1>;
mdiobus = <&mdio0>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
mdiobus = <&mdio0>;
phy-mode = "sgmii";
qcom,id = <2>;
mdiobus = <&mdio0>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
};
/*
* The i2c device on gsbi4 should not be enabled.
};
/*
* The i2c device on gsbi4 should not be enabled.
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
pinctrl-0 = <&usb0_pwr_en_pin>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb0_pwr_en_pin>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb1_pwr_en_pin>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
pinctrl-0 = <&usb1_pwr_en_pin>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
qcom,id = <1>;
phy-mode = "rgmii";
qcom,id = <1>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
phy-mode = "sgmii";
qcom,id = <2>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
};
/*
* The i2c device on gsbi4 should not be enabled.
};
/*
* The i2c device on gsbi4 should not be enabled.
};
sata@29000000 {
ports-implemented = <0x1>;
};
sata@29000000 {
ports-implemented = <0x1>;
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
pcie1: pci@1b700000 {
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
pcie1: pci@1b700000 {
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
phy-handle = <&phy4>;
qcom,id = <1>;
phy-mode = "rgmii";
phy-handle = <&phy4>;
qcom,id = <1>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
phy-mode = "sgmii";
qcom,id = <2>;
gsbi2: gsbi@12480000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi2: gsbi@12480000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
};
};
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
};
};
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
gmac0: ethernet@37000000 {
};
gmac0: ethernet@37000000 {
phy-mode = "rgmii";
qcom,id = <0>;
phy-handle = <&phy4>;
phy-mode = "rgmii";
qcom,id = <0>;
phy-handle = <&phy4>;
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "sgmii";
qcom,id = <1>;
phy-mode = "sgmii";
qcom,id = <1>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
phy-handle = <&phy6>;
};
gmac3: ethernet@37600000 {
phy-mode = "sgmii";
qcom,id = <2>;
phy-handle = <&phy6>;
};
gmac3: ethernet@37600000 {
phy-mode = "sgmii";
qcom,id = <3>;
phy-handle = <&phy7>;
phy-mode = "sgmii";
qcom,id = <3>;
phy-handle = <&phy7>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
};
/*
* The i2c device on gsbi4 should not be enabled.
};
/*
* The i2c device on gsbi4 should not be enabled.
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
force_gen1 = <1>;
};
pcie1: pci@1b700000 {
force_gen1 = <1>;
};
pcie1: pci@1b700000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
qcom,id = <1>;
qcom,phy_mdio_addr = <4>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,phy_mdio_addr = <4>;
};
//lan
gmac2: ethernet@37400000 {
};
//lan
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
qcom,phy_mdio_addr = <0>; /* none */
phy-mode = "sgmii";
qcom,id = <2>;
qcom,phy_mdio_addr = <0>; /* none */
};
adm_dma: dma@18300000 {
};
adm_dma: dma@18300000 {
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
};
/*
* The i2c device on gsbi4 should not be enabled.
};
/*
* The i2c device on gsbi4 should not be enabled.
};
phy@100f8800 { /* USB3 port 1 HS phy */
clocks = <&gcc USB30_0_UTMI_CLK>;
};
phy@100f8800 { /* USB3 port 1 HS phy */
clocks = <&gcc USB30_0_UTMI_CLK>;
};
phy@100f8830 { /* USB3 port 1 SS phy */
clocks = <&gcc USB30_0_MASTER_CLK>;
};
phy@100f8830 { /* USB3 port 1 SS phy */
clocks = <&gcc USB30_0_MASTER_CLK>;
};
phy@110f8800 { /* USB3 port 0 HS phy */
clocks = <&gcc USB30_1_UTMI_CLK>;
};
phy@110f8800 { /* USB3 port 0 HS phy */
clocks = <&gcc USB30_1_UTMI_CLK>;
};
phy@110f8830 { /* USB3 port 0 SS phy */
clocks = <&gcc USB30_1_MASTER_CLK>;
};
phy@110f8830 { /* USB3 port 0 SS phy */
clocks = <&gcc USB30_1_MASTER_CLK>;
};
usb30@0 {
clocks = <&gcc USB30_1_MASTER_CLK>;
};
usb30@0 {
clocks = <&gcc USB30_1_MASTER_CLK>;
};
usb30@1 {
clocks = <&gcc USB30_0_MASTER_CLK>;
};
usb30@1 {
clocks = <&gcc USB30_0_MASTER_CLK>;
force_gen1 = <1>;
};
nand@1ac00000 {
force_gen1 = <1>;
};
nand@1ac00000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
qcom,id = <1>;
phy-mode = "rgmii";
qcom,id = <1>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
phy-mode = "sgmii";
qcom,id = <2>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
};
/*
* The i2c device on gsbi4 should not be enabled.
};
/*
* The i2c device on gsbi4 should not be enabled.
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
pcie1: pci@1b700000 {
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
pcie1: pci@1b700000 {
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
qcom,id = <1>;
phy-mode = "rgmii";
qcom,id = <1>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
phy-mode = "sgmii";
qcom,id = <2>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
};
/*
* The i2c device on gsbi4 should not be enabled.
};
/*
* The i2c device on gsbi4 should not be enabled.
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
qcom,id = <1>;
phy-mode = "rgmii";
qcom,id = <1>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
phy-mode = "sgmii";
qcom,id = <2>;
phy-mode = "sgmii";
qcom,id = <2>;
phy-mode = "sgmii";
qcom,id = <2>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
};
/*
* The i2c device on gsbi4 should not be enabled.
};
/*
* The i2c device on gsbi4 should not be enabled.
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
pcie1: pci@1b700000 {
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
pcie1: pci@1b700000 {
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
qcom,id = <1>;
qcom,phy_mdio_addr = <4>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,phy_mdio_addr = <4>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
qcom,phy_mdio_addr = <0>; /* none */
phy-mode = "sgmii";
qcom,id = <2>;
qcom,phy_mdio_addr = <0>; /* none */
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
};
/*
* The i2c device on gsbi4 should not be enabled.
};
/*
* The i2c device on gsbi4 should not be enabled.
};
sata@29000000 {
ports-implemented = <0x1>;
};
sata@29000000 {
ports-implemented = <0x1>;
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8800 { /* USB3 port 1 HS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@100f8830 { /* USB3 port 1 SS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8800 { /* USB3 port 0 HS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
};
phy@110f8830 { /* USB3 port 0 SS phy */
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
usb30@1 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
pcie0: pci@1b500000 {
force_gen1 = <1>;
};
nand@1ac00000 {
force_gen1 = <1>;
};
nand@1ac00000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
gmac1: ethernet@37200000 {
};
gmac1: ethernet@37200000 {
phy-mode = "rgmii";
qcom,id = <1>;
qcom,phy_mdio_addr = <4>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,phy_mdio_addr = <4>;
};
gmac2: ethernet@37400000 {
};
gmac2: ethernet@37400000 {
phy-mode = "sgmii";
qcom,id = <2>;
qcom,phy_mdio_addr = <0>; /* none */
phy-mode = "sgmii";
qcom,id = <2>;
qcom,phy_mdio_addr = <0>; /* none */