-+#include <linux/clk.h>
-+
-+#define REG_SM0CFG0 0x08
-+#define REG_SM0DOUT 0x10
-+#define REG_SM0DIN 0x14
-+#define REG_SM0ST 0x18
-+#define REG_SM0AUTO 0x1C
-+#define REG_SM0CFG1 0x20
-+#define REG_SM0CFG2 0x28
-+#define REG_SM0CTL0 0x40
-+#define REG_SM0CTL1 0x44
-+#define REG_SM0D0 0x50
-+#define REG_SM0D1 0x54
-+#define REG_PINTEN 0x5C
-+#define REG_PINTST 0x60
-+#define REG_PINTCL 0x64
-+
-+/* REG_SM0CFG0 */
-+#define I2C_DEVADDR_MASK 0x7f
-+
-+/* REG_SM0ST */
-+#define I2C_DATARDY BIT(2)
-+#define I2C_SDOEMPTY BIT(1)
-+#define I2C_BUSY BIT(0)
-+
-+/* REG_SM0AUTO */
-+#define READ_CMD BIT(0)
-+
-+/* REG_SM0CFG1 */
-+#define BYTECNT_MAX 64
-+#define SET_BYTECNT(x) (x - 1)
-+
-+/* REG_SM0CFG2 */
-+#define AUTOMODE_EN BIT(0)
-+
-+/* REG_SM0CTL0 */
-+#define ODRAIN_HIGH_SM0 BIT(31)
-+#define VSYNC_SHIFT 28
-+#define VSYNC_MASK 0x3
-+#define VSYNC_PULSE (0x1 << VSYNC_SHIFT)
-+#define VSYNC_RISING (0x2 << VSYNC_SHIFT)
-+#define CLK_DIV_SHIFT 16
-+#define CLK_DIV_MASK 0xfff
-+#define DEG_CNT_SHIFT 8
-+#define DEG_CNT_MASK 0xff
-+#define WAIT_HIGH BIT(6)
-+#define DEG_EN BIT(5)
-+#define CS_STATUA BIT(4)
-+#define SCL_STATUS BIT(3)
-+#define SDA_STATUS BIT(2)
-+#define SM0_EN BIT(1)
-+#define SCL_STRECH BIT(0)
-+
-+/* REG_SM0CTL1 */
-+#define ACK_SHIFT 16
-+#define ACK_MASK 0xff
-+#define PGLEN_SHIFT 8
-+#define PGLEN_MASK 0x7
-+#define SM0_MODE_SHIFT 4
-+#define SM0_MODE_MASK 0x7
-+#define SM0_MODE_START 0x1
-+#define SM0_MODE_WRITE 0x2
-+#define SM0_MODE_STOP 0x3
-+#define SM0_MODE_READ_NACK 0x4
-+#define SM0_MODE_READ_ACK 0x5
-+#define SM0_TRI_BUSY BIT(0)
-+
-+/* timeout waiting for I2C devices to respond (clock streching) */
-+#define TIMEOUT_MS 1000
-+#define DELAY_INTERVAL_US 100
-+
-+struct mtk_i2c {
-+ void __iomem *base;
-+ struct clk *clk;
-+ struct device *dev;
-+ struct i2c_adapter adap;
-+ u32 cur_clk;
-+ u32 clk_div;
-+ u32 flags;
-+};