++static void
++mediatek_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
++{
++ int i;
++
++ for (i = 0; i < MTK_MAX_BANK; i++) {
++ struct mtk_gc *rg = gc_map[i];
++ unsigned long pending;
++ int bit;
++
++ if (!rg)
++ continue;
++
++ pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
++
++ for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
++ u32 map = irq_find_mapping(mediatek_gpio_irq_domain, bit);
++
++ generic_handle_irq(map);
++ mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
++ }
++ }
++}
++
++static void
++mediatek_gpio_irq_unmask(struct irq_data *d)
++{
++ int pin = d->hwirq;
++ int bank = pin / 32;
++ struct mtk_gc *rg = gc_map[bank];
++ unsigned long flags;
++ u32 rise, fall;
++
++ if (!rg)
++ return;
++
++ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
++ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
++
++ spin_lock_irqsave(&rg->lock, flags);
++ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising));
++ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling));
++ spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static void
++mediatek_gpio_irq_mask(struct irq_data *d)
++{
++ int pin = d->hwirq;
++ int bank = pin / 32;
++ struct mtk_gc *rg = gc_map[bank];
++ unsigned long flags;
++ u32 rise, fall;
++
++ if (!rg)
++ return;
++
++ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
++ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
++
++ spin_lock_irqsave(&rg->lock, flags);
++ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq));
++ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq));
++ spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static int
++mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
++{
++ int pin = d->hwirq;
++ int bank = pin / 32;
++ struct mtk_gc *rg = gc_map[bank];
++ u32 mask = BIT(d->hwirq);
++
++ if (!rg)
++ return -1;
++
++ if (type == IRQ_TYPE_PROBE) {
++ if ((rg->rising | rg->falling) & mask)
++ return 0;
++
++ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
++ }
++
++ if (type & IRQ_TYPE_EDGE_RISING)
++ rg->rising |= mask;
++ else
++ rg->rising &= ~mask;
++
++ if (type & IRQ_TYPE_EDGE_FALLING)
++ rg->falling |= mask;
++ else
++ rg->falling &= ~mask;
++
++ return 0;
++}
++
++static struct irq_chip mediatek_gpio_irq_chip = {
++ .name = "GPIO",
++ .irq_unmask = mediatek_gpio_irq_unmask,
++ .irq_mask = mediatek_gpio_irq_mask,
++ .irq_mask_ack = mediatek_gpio_irq_mask,
++ .irq_set_type = mediatek_gpio_irq_type,
++};
++
++static int
++mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq);
++ irq_set_handler_data(irq, d);
++
++ return 0;
++}
++
++static const struct irq_domain_ops irq_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = mediatek_gpio_gpio_map,
++};
++