sifiveu: 6.12: drop upstreamed patches and refresh remaining ones

Drop upstreamed patches from 6.12 and refresh remaining ones.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>

2 files changed, 4 insertions, 120 deletions

diff --git a/target/linux/sifiveu/patches-6.12/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch b/target/linux/sifiveu/patches-6.12/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch
index 9a1c968139..fc74b9ba73 100644
--- a/target/linux/sifiveu/patches-6.12/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch
+++ b/target/linux/sifiveu/patches-6.12/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch
@@ -11,7 +11,7 @@ Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
 
 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
 +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-@@ -39,7 +39,7 @@
+@@ -42,7 +42,7 @@
  			};
  		};
  		cpu1: cpu@1 {
@@ -20,7 +20,7 @@ Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
  			d-cache-block-size = <64>;
  			d-cache-sets = <64>;
  			d-cache-size = <32768>;
-@@ -63,7 +63,7 @@
+@@ -69,7 +69,7 @@
  			};
  		};
  		cpu2: cpu@2 {
@@ -29,7 +29,7 @@ Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
  			d-cache-block-size = <64>;
  			d-cache-sets = <64>;
  			d-cache-size = <32768>;
-@@ -87,7 +87,7 @@
+@@ -96,7 +96,7 @@
  			};
  		};
  		cpu3: cpu@3 {
@@ -38,7 +38,7 @@ Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
  			d-cache-block-size = <64>;
  			d-cache-sets = <64>;
  			d-cache-size = <32768>;
-@@ -111,7 +111,7 @@
+@@ -123,7 +123,7 @@
  			};
  		};
  		cpu4: cpu@4 {
diff --git a/target/linux/sifiveu/patches-6.12/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch b/target/linux/sifiveu/patches-6.12/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch
deleted file mode 100644
index 905e3cccb7..0000000000
--- a/target/linux/sifiveu/patches-6.12/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Fri, 14 May 2021 05:27:51 -0700
-Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
-
-Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/Kconfig                                 |  8 +++++
- arch/riscv/boot/dts/sifive/fu540-c000.dtsi         |  5 ++++
- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
- 3 files changed, 47 insertions(+)
-
---- a/arch/riscv/Kconfig
-+++ b/arch/riscv/Kconfig
-@@ -901,6 +901,14 @@ config PORTABLE
- 	select MMU
- 	select OF
- 
-+menu "CPU Power Management"
-+
-+source "drivers/cpuidle/Kconfig"
-+
-+source "drivers/cpufreq/Kconfig"
-+
-+endmenu
-+
- menu "Power management options"
- 
- source "kernel/power/Kconfig"
---- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-@@ -30,6 +30,7 @@
- 			i-cache-size = <16384>;
- 			reg = <0>;
- 			riscv,isa = "rv64imac";
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			status = "disabled";
- 			cpu0_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
-@@ -54,6 +55,7 @@
- 			reg = <1>;
- 			riscv,isa = "rv64imafdc";
- 			tlb-split;
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			next-level-cache = <&l2cache>;
- 			cpu1_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
-@@ -78,6 +80,7 @@
- 			reg = <2>;
- 			riscv,isa = "rv64imafdc";
- 			tlb-split;
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			next-level-cache = <&l2cache>;
- 			cpu2_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
-@@ -102,6 +105,7 @@
- 			reg = <3>;
- 			riscv,isa = "rv64imafdc";
- 			tlb-split;
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			next-level-cache = <&l2cache>;
- 			cpu3_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
-@@ -126,6 +130,7 @@
- 			reg = <4>;
- 			riscv,isa = "rv64imafdc";
- 			tlb-split;
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			next-level-cache = <&l2cache>;
- 			cpu4_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
---- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-@@ -80,6 +80,40 @@
- 			label = "d4";
- 		};
- 	};
-+
-+	fu540_c000_opp_table: opp-table {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp-350000000 {
-+			opp-hz = /bits/ 64 <350000000>;
-+		};
-+		opp-700000000 {
-+			opp-hz = /bits/ 64 <700000000>;
-+		};
-+		opp-999999999 {
-+			opp-hz = /bits/ 64 <999999999>;
-+		};
-+		opp-1400000000 {
-+			opp-hz = /bits/ 64 <1400000000>;
-+		};
-+	};
-+};
-+
-+&cpu0 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu1 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu2 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu3 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu4 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
- };
- 
- &uart0 {