AArch32: Add support for ARM Cortex-A32 MPCore Processor

This patch adds ARM Cortex-A32 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base FVP port.

Change-Id: If3697b88678df737c29f79cf3fa1ea2cb6fa565d

diff --git a/include/lib/cpus/aarch32/cortex_a32.h b/include/lib/cpus/aarch32/cortex_a32.h
new file mode 100644 (file)
index 0000000..458b41f
--- /dev/null
+++ b/include/lib/cpus/aarch32/cortex_a32.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CORTEX_A32_H__
+#define __CORTEX_A32_H__
+
+/* Cortex-A32 Main ID register for revision 0 */
+#define CORTEX_A32_MIDR                                0x410FD010
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ * CPUECTLR_EL1 is an implementation-specific register.
+ ******************************************************************************/
+#define CORTEX_A32_CPUECTLR_EL1                        p15, 1, c15
+#define CORTEX_A32_CPUECTLR_SMPEN_BIT          (1 << 6)
+
+#endif /* __CORTEX_A32_H__ */

diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S
new file mode 100644 (file)
index 0000000..b51f997
--- /dev/null
+++ b/lib/cpus/aarch32/cortex_a32.S
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+#include <cortex_a32.h>
+#include <cpu_macros.S>
+
+
+       /* ---------------------------------------------
+        * Disable intra-cluster coherency
+        * Clobbers: r0-r1
+        * ---------------------------------------------
+        */
+func cortex_a32_disable_smp
+       ldcopr16        r0, r1, CORTEX_A32_CPUECTLR_EL1
+       bic     r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
+       stcopr16        r0, r1, CORTEX_A32_CPUECTLR_EL1
+       isb
+       dsb     sy
+       bx      lr
+endfunc cortex_a32_disable_smp
+
+       /* -------------------------------------------------
+        * The CPU Ops reset function for Cortex-A32.
+        * Clobbers: r0-r1
+        * -------------------------------------------------
+        */
+func cortex_a32_reset_func
+       /* ---------------------------------------------
+        * Enable the SMP bit.
+        * ---------------------------------------------
+        */
+       ldcopr16        r0, r1, CORTEX_A32_CPUECTLR_EL1
+       orr     r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
+       stcopr16        r0, r1, CORTEX_A32_CPUECTLR_EL1
+       isb
+       bx      lr
+endfunc cortex_a32_reset_func
+
+       /* ----------------------------------------------------
+        * The CPU Ops core power down function for Cortex-A32.
+        * Clobbers: r0-r3
+        * ----------------------------------------------------
+        */
+func cortex_a32_core_pwr_dwn
+       push    {lr}
+
+       /* Assert if cache is enabled */
+#if ASM_ASSERTION
+       ldcopr  r0, SCTLR
+       tst     r0, #SCTLR_C_BIT
+       ASM_ASSERT(eq)
+#endif
+
+       /* ---------------------------------------------
+        * Flush L1 caches.
+        * ---------------------------------------------
+        */
+       mov     r0, #DC_OP_CISW
+       bl      dcsw_op_level1
+
+       /* ---------------------------------------------
+        * Come out of intra cluster coherency
+        * ---------------------------------------------
+        */
+       pop     {lr}
+       b       cortex_a32_disable_smp
+endfunc cortex_a32_core_pwr_dwn
+
+       /* -------------------------------------------------------
+        * The CPU Ops cluster power down function for Cortex-A32.
+        * Clobbers: r0-r3
+        * -------------------------------------------------------
+        */
+func cortex_a32_cluster_pwr_dwn
+       push    {lr}
+
+       /* Assert if cache is enabled */
+#if ASM_ASSERTION
+       ldcopr  r0, SCTLR
+       tst     r0, #SCTLR_C_BIT
+       ASM_ASSERT(eq)
+#endif
+
+       /* ---------------------------------------------
+        * Flush L1 cache.
+        * ---------------------------------------------
+        */
+       mov     r0, #DC_OP_CISW
+       bl      dcsw_op_level1
+
+       /* ---------------------------------------------
+        * Disable the optional ACP.
+        * ---------------------------------------------
+        */
+       bl      plat_disable_acp
+
+       /* ---------------------------------------------
+        * Flush L2 cache.
+        * ---------------------------------------------
+        */
+       mov     r0, #DC_OP_CISW
+       bl      dcsw_op_level2
+
+       /* ---------------------------------------------
+        * Come out of intra cluster coherency
+        * ---------------------------------------------
+        */
+       pop     {lr}
+       b       cortex_a32_disable_smp
+endfunc cortex_a32_cluster_pwr_dwn
+
+declare_cpu_ops cortex_a32, CORTEX_A32_MIDR

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index ca348d1ac9cac6843e31ec8c347247a83e41670c..9b827a6baa8804569dbe9f0f7f96db014a8071e7 100644 (file)
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -109,6 +109,8 @@ FVP_CPU_LIBS                +=      lib/cpus/aarch64/cortex_a35.S                   \
                                lib/cpus/aarch64/cortex_a57.S                   \
                                lib/cpus/aarch64/cortex_a72.S                   \
                                lib/cpus/aarch64/cortex_a73.S
+else
+FVP_CPU_LIBS           +=      lib/cpus/aarch32/cortex_a32.S
 endif
 
 BL1_SOURCES            +=      drivers/io/io_semihosting.c                     \