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| author | INAGAKI Hiroshi | 2024-04-26 14:54:57 +0000 |
|---|---|---|
| committer | Hauke Mehrtens | 2024-07-28 16:47:56 +0000 |
| commit | 09eee2538ee08853b9273df249635409485ac417 (patch) | |
| tree | 148303e068dcaf2557083bbdd0716989d3fa5eef | |
| parent | 98f73552a78e1c6d825dc3ba9845b4c63c3f16c6 (diff) | |
| download | openwrt-09eee2538ee08853b9273df249635409485ac417.tar.gz | |
ath79: add missing reset de-assertion of PCIe endpoint
Fix PCIe initialization by de-assertion of PCIe endpoint reset.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15432
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
| -rw-r--r-- | target/linux/ath79/patches-6.6/318-MIPS-pci-ar724x-deassert-the-reset-of-PCIe-endpoint.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/target/linux/ath79/patches-6.6/318-MIPS-pci-ar724x-deassert-the-reset-of-PCIe-endpoint.patch b/target/linux/ath79/patches-6.6/318-MIPS-pci-ar724x-deassert-the-reset-of-PCIe-endpoint.patch new file mode 100644 index 0000000000..c906bdbbb6 --- /dev/null +++ b/target/linux/ath79/patches-6.6/318-MIPS-pci-ar724x-deassert-the-reset-of-PCIe-endpoint.patch @@ -0,0 +1,41 @@ +From 859c93981a8994ffa69967b44b247d2e7d6a01f1 Mon Sep 17 00:00:00 2001 +From: INAGAKI Hiroshi <musashino.open@gmail.com> +Date: Fri, 26 Apr 2024 23:54:57 +0900 +Subject: [PATCH 2/2] MIPS: pci-ar724x: deassert the reset of PCIe endpoint + +Fix PCIe initialization by de-assertion of PCIe endpoint reset. + +Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> +--- + +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -25,6 +25,7 @@ + + #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) + ++#define AR724X_PCI_RESET_EP_RESET_L BIT(2) + #define AR724X_PCI_RESET_LINK_UP BIT(0) + + #define AR724X_PCI_INT_DEV0 BIT(14) +@@ -340,7 +341,7 @@ static void ar724x_pci_irq_init(struct a + + static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc) + { +- u32 ppl, app; ++ u32 ppl, rst, app; + int wait = 0; + + /* deassert PCIe host controller and PCIe PHY reset */ +@@ -370,6 +371,11 @@ static void ar724x_pci_hw_init(struct ar + ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); + } + ++ /* deassert the reset state of the PCIE endpoint */ ++ rst = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); ++ rst |= AR724X_PCI_RESET_EP_RESET_L; ++ __raw_writel(rst, apc->ctrl_base + AR724X_PCI_REG_RESET); ++ + /* set PCIE Application Control to ready */ + app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); + app |= AR724X_PCI_APP_LTSSM_ENABLE; |