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authorMaxim Anisimov2026-03-23 06:19:30 +0000
committerHauke Mehrtens2026-03-29 15:35:55 +0000
commit0beb242464c587ad32fbc0bfa108f66f55b4ca8e (patch)
tree86110f5dcb82870b8ae14fc77808b712f2357dbb
parent6bd35b670d613475bf6d36a27ecb0b0d121a7350 (diff)
downloadopenwrt-0beb242464c587ad32fbc0bfa108f66f55b4ca8e.tar.gz
mediatek: filogic: kn-1812: fix phy reset deassert
The RTL8261BE 10GbE PHY's `reset-deassert-us` was set to 100ms (100000us), but the **RTL8261N datasheet (Table 108, parameter t7)** specifies a minimum **SMI-ready time of 150ms** after nRESET release before the MDIO (SMI) bus can be used. Note: Essentially, the RTL8261N and RTL8261BE are architecturally identical chips, so their initialization parameters should be consistent. Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com> Link: https://github.com/openwrt/openwrt/pull/22575 (cherry picked from commit 44a52a8769b95cf5f99e31d4acf7443f32a12265) Link: https://github.com/openwrt/openwrt/pull/22626 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-rw-r--r--target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi b/target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi
index 1eb534dbc4..140ae1528b 100644
--- a/target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi
+++ b/target/linux/mediatek/dts/mt7988d-keenetic-kn-1812.dtsi
@@ -400,7 +400,7 @@
reset-gpios = <&pio 4 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
- reset-deassert-us = <100000>;
+ reset-deassert-us = <221000>;
};
};