ath79: rb912: fix pll init issues
authorKoen Vandeputte <koen.vandeputte@ncentric.com>
Wed, 12 Jan 2022 15:11:15 +0000 (16:11 +0100)
committerKoen Vandeputte <koen.vandeputte@ncentric.com>
Thu, 13 Jan 2022 09:04:06 +0000 (10:04 +0100)
It was reported that some rb912 boards (ar934x) have issues with some ethernet speeds.
Investigation shows that the board failed to adapt the ethernet pll values as shown here:

[    5.284359] ag71xx 19000000.eth: failed to read pll-handle property

added custom prints in code and triggering a link switch:

[   62.821446] Atheros AG71xx: fast reset
[   62.826442] Atheros AG71xx: update pll 2
[   62.830494] Atheros AG71xx: no pll regmap!

Comparison with another very similar board (rb922 - QCA955x) showed a missing
reference clock frequency in dts, which seems to cause a pll init issue.
Unfortunately, no errors are printed when this occurs.

Adding the frequency property fixes the pll init as it can be parsed now
by the ethernet driver.

[   55.861407] Atheros AG71xx: fast reset
[   55.866403] Atheros AG71xx: update pll 2
[   55.870462] Atheros AG71xx: ath79_set_pllval: regmap: 0x81548000, pll_reg: 0x2c, pll_val: 0x02000000

Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
(cherry picked from commit 2a000546187122c86143c97337af4d5beacc4908)

target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts

index ee2c12b4e0704cdb21fccae40bf08ed03b110548..14286ae8f784a547d7c7806f2555c77120775412 100644 (file)
        };
 };
 
+&ref {
+       clock-frequency = <25000000>;
+};
+
 &spi {
        status = "okay";