-a 0 -e 0 -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
+ifneq ($(EXT_DTB),)
+u-boot-fit-dtb.bin: u-boot-nodtb.bin $(EXT_DTB)
+ $(call if_changed,cat)
+else
u-boot-fit-dtb.bin: u-boot-nodtb.bin $(FINAL_DTB_CONTAINER)
$(call if_changed,cat)
+endif
u-boot.bin: u-boot-fit-dtb.bin FORCE
$(call if_changed,copy)
select DM_ETH
select DM_GPIO
select DM_KEYBOARD
+ select DM_MMC if MMC
+ select DM_SCSI if SCSI
select DM_SERIAL
select DM_USB if DISTRO_DEFAULTS
select OF_BOARD_SETUP
+++ /dev/null
-/*
- * Support for CompuLab CL-SOM-AM57x System-on-Module
- *
- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include "dra74x.dtsi"
-
-/ {
- model = "CompuLab CL-SOM-AM57x";
- compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_pins_default>;
-
- led0 {
- label = "cl-som-am57x:green";
- gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-
- vdd_3v3: fixedregulator-vdd_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- ads7846reg: fixedregulator-ads7846-reg {
- compatible = "regulator-fixed";
- regulator-name = "ads7846-reg";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- sound0: sound0 {
- compatible = "simple-audio-card";
- simple-audio-card,name = "CL-SOM-AM57x-Sound-Card";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&dailink0_master>;
- simple-audio-card,frame-master = <&dailink0_master>;
- simple-audio-card,widgets =
- "Headphone", "Headphone Jack",
- "Microphone", "Microphone Jack",
- "Line", "Line Jack";
- simple-audio-card,routing =
- "Headphone Jack", "RHPOUT",
- "Headphone Jack", "LHPOUT",
- "LLINEIN", "Line Jack",
- "MICIN", "Mic Bias",
- "Mic Bias", "Microphone Jack";
-
- dailink0_master: simple-audio-card,cpu {
- sound-dai = <&mcasp3>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&wm8731>;
- system-clock-frequency = <12000000>;
- };
- };
-};
-
-&dra7_pmx_core {
- leds_pins_default: leds_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */
- >;
- };
-
- i2c1_pins_default: i2c1_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
- DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
- >;
- };
-
- i2c3_pins_default: i2c3_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
- DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
- >;
- };
-
- i2c4_pins_default: i2c4_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */
- DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */
- >;
- };
-
- tps659038_pins_default: tps659038_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-
- qspi1_pins: pinmux_qspi1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
- DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */
- DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */
- DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
- DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
- DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
- >;
- };
-
- cpsw_pins_default: cpsw_pins_default {
- pinctrl-single,pins = <
- /* Slave at addr 0x0 */
- DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */
- DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */
- DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */
- DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */
- DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */
- DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */
- DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */
- DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */
- DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */
- DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */
- DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */
- DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */
-
- /* Slave at addr 0x1 */
- DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */
- DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
- DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
- DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
- DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
- DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
- DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
- DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
- DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
- DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
- DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
- DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
- >;
- };
-
- cpsw_pins_sleep: cpsw_pins_sleep {
- pinctrl-single,pins = <
- /* Slave 1 */
- DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
-
- /* Slave 2 */
- DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)
- >;
- };
-
- davinci_mdio_pins_default: davinci_mdio_pins_default {
- pinctrl-single,pins = <
- /* MDIO */
- DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */
- DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */
- >;
- };
-
- davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15)
- >;
- };
-
- ads7846_pins: pinmux_ads7846_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */
- >;
- };
-
- mcasp3_pins_default: mcasp3_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
- DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
- DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
- DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
- >;
- };
-
- mcasp3_pins_sleep: mcasp3_pins_sleep {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
- >;
- };
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_default>;
- clock-frequency = <400000>;
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins_default>;
- clock-frequency = <400000>;
-};
-
-&i2c4 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_default>;
- clock-frequency = <400000>;
-
- tps659038: tps659038@58 {
- compatible = "ti,tps659038";
- reg = <0x58>;
- interrupt-parent = <&gpio1>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&tps659038_pins_default>;
-
- #interrupt-cells = <2>;
- interrupt-controller;
-
- ti,system-power-controller;
-
- tps659038_pmic {
- compatible = "ti,tps659038-pmic";
-
- regulators {
- smps12_reg: smps12 {
- /* VDD_MPU */
- regulator-name = "smps12";
- regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps3_reg: smps3 {
- /* VDD_DDR */
- regulator-name = "smps3";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps45_reg: smps45 {
- /* VDD_DSPEVE */
- regulator-name = "smps45";
- regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps6_reg: smps6 {
- /* VDD_GPU */
- regulator-name = "smps6";
- regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps7_reg: smps7 {
- /* VDD_CORE */
- regulator-name = "smps7";
- regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1160000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps8_reg: smps8 {
- /* VDD_IVA */
- regulator-name = "smps8";
- regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps9_reg: smps9 {
- /* PMIC_3V3 */
- regulator-name = "smps9";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
-
- ldo1_reg: ldo1 {
- /* VDD_SD / VDDSHV8 */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2_reg: ldo2 {
- /* VDD_1V8 */
- regulator-name = "ldo2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo3_reg: ldo3 {
- /* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo4_reg: ldo4 {
- /* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */
- regulator-name = "ldo4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo9_reg: ldo9 {
- /* VDD_RTC */
- regulator-name = "ldo9";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldoln_reg: ldoln {
- /* VDDA_1V8_PLL */
- regulator-name = "ldoln";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldousb_reg: ldousb {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldousb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* regen1 not used */
- };
- };
-
- tps659038_pwr_button: tps659038_pwr_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&tps659038>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- wakeup-source;
- ti,palmas-long-press-seconds = <12>;
- };
-
- tps659038_gpio: tps659038_gpio {
- compatible = "ti,palmas-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-
- rtc0: rtc@56 {
- compatible = "emmicro,em3027";
- reg = <0x56>;
- };
-
- eeprom_module: atmel@50 {
- compatible = "atmel,24c08";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- wm8731: wm8731@1a {
- #sound-dai-cells = <0>;
- compatible = "wlf,wm8731";
- reg = <0x1a>;
- status = "okay";
- };
-};
-
-&cpu0 {
- cpu0-supply = <&smps12_reg>;
- voltage-tolerance = <1>;
-};
-
-&sata {
- status = "okay";
-};
-
-&mailbox5 {
- status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
-};
-
-&mailbox6 {
- status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
- status = "okay";
- };
-};
-
-&mmc2 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_default>;
-
- vmmc-supply = <&vdd_3v3>;
- bus-width = <8>;
- ti,non-removable;
- cap-mmc-dual-data-rate;
-};
-
-&qspi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&qspi1_pins>;
-
- spi-max-frequency = <48000000>;
-
- spi_flash: spi_flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spansion,m25p80", "jedec,spi-nor";
- reg = <0>; /* CS0 */
- spi-max-frequency = <48000000>;
-
- partition@0 {
- label = "uboot";
- reg = <0x0 0xc0000>;
- };
-
- partition@c0000 {
- label = "uboot environment";
- reg = <0xc0000 0x40000>;
- };
-
- partition@100000 {
- label = "reserved";
- reg = <0x100000 0x0>;
- };
- };
-
- /* touch controller */
- ads7846@0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ads7846_pins>;
-
- compatible = "ti,ads7846";
- vcc-supply = <&ads7846reg>;
-
- reg = <1>; /* CS1 */
- spi-max-frequency = <1500000>;
-
- interrupt-parent = <&gpio1>;
- interrupts = <31 0>;
- pendown-gpio = <&gpio1 31 0>;
-
-
- ti,x-min = /bits/ 16 <0x0>;
- ti,x-max = /bits/ 16 <0x0fff>;
- ti,y-min = /bits/ 16 <0x0>;
- ti,y-max = /bits/ 16 <0x0fff>;
-
- ti,x-plate-ohms = /bits/ 16 <180>;
- ti,pressure-max = /bits/ 16 <255>;
-
- ti,debounce-max = /bits/ 16 <30>;
- ti,debounce-tol = /bits/ 16 <10>;
- ti,debounce-rep = /bits/ 16 <1>;
-
- wakeup-source;
- };
-};
-
-&mac {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cpsw_pins_default>;
- pinctrl-1 = <&cpsw_pins_sleep>;
- dual_emac;
-};
-
-&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <0>;
- phy-mode = "rgmii-txid";
- dual_emac_res_vlan = <0>;
-};
-
-&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <1>;
- phy-mode = "rgmii-txid";
- dual_emac_res_vlan = <1>;
-};
-
-&davinci_mdio {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&davinci_mdio_pins_default>;
- pinctrl-1 = <&davinci_mdio_pins_sleep>;
-};
-
-&usb2_phy1 {
- phy-supply = <&ldousb_reg>;
-};
-
-&usb2_phy2 {
- phy-supply = <&ldousb_reg>;
-};
-
-&usb1 {
- dr_mode = "host";
-};
-
-&usb2 {
- dr_mode = "host";
-};
-
-&mcasp3 {
- #sound-dai-cells = <0>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&mcasp3_pins_default>;
- pinctrl-1 = <&mcasp3_pins_sleep>;
- status = "okay";
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- /* 4 serializers */
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 2 0 0
- >;
-};
-
-&gpio3 {
- status = "okay";
- ti,no-reset-on-init;
-};
-
-&gpio2 {
- status = "okay";
- ti,no-reset-on-init;
-};
+++ /dev/null
-/*
- * Support for CompuLab SBC-AM57x single board computer
- *
- * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-
-#include "am57xx-cl-som-am57x.dts"
-#include "compulab-sb-som.dtsi"
-
-/ {
- model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x";
- compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
-
- aliases {
- display0 = &lcd0;
- display1 = &hdmi;
- };
-};
-
-&dra7_pmx_core {
- uart3_pins_default: uart3_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
- DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
- >;
- };
-
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */
- DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */
- >;
- };
-
- usb1_pins: pinmux_usb1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
- >;
- };
-
- i2c5_pins_default: i2c5_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
- DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
- >;
- };
-
- lcd_pins_default: lcd_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */
- >;
- };
-
- hdmi_pins: pinmux_hdmi_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
- DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
- >;
- };
-
- hdmi_conn_pins: pinmux_hdmi_conn_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */
- >;
- };
-};
-
-&uart3 {
- status = "okay";
- interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <&dra7_pmx_core 0x3f8>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_default>;
-};
-
-&mmc1 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_default>;
-
- vmmc-supply = <&ldo1_reg>;
- bus-width = <4>;
- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
-};
-
-&usb1 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins>;
-};
-
-&i2c5 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins_default>;
- clock-frequency = <400000>;
-
- eeprom_base: atmel@54 {
- compatible = "atmel,24c08";
- reg = <0x54>;
- pagesize = <16>;
- };
-
- pca9555: pca9555@20 {
- compatible = "nxp,pca9555";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&dss {
- status = "ok";
-
- vdda_video-supply = <&ldoln_reg>;
-
- port {
- dpi_lcd_out: endpoint {
- remote-endpoint = <&lcd_in>;
- data-lines = <24>;
- };
- };
-};
-
-&lcd0 {
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_pins_default>;
-
- enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH
- &gpio4 0 GPIO_ACTIVE_HIGH>;
-
- port {
- lcd_in: endpoint {
- remote-endpoint = <&dpi_lcd_out>;
- data-lines = <24>;
- };
- };
-};
-
-&hdmi {
- status = "ok";
- vdda-supply = <&ldo4_reg>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pins>;
-
- port {
- hdmi_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- lanes = <1 0 3 2 5 4 7 6>;
- };
- };
-};
-
-&hdmi_conn {
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_conn_pins>;
-
- hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_out>;
- };
- };
-};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "orangepi:red:power";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ default-state = "on";
+ };
+
+ status {
+ label = "orangepi:green:status";
+ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <®_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
&r_i2c {
status = "okay";
interrupt-controller;
#interrupt-cells = <1>;
x-powers,self-working-mode;
+ vina-supply = <®_vcc5v>;
+ vinb-supply = <®_vcc5v>;
+ vinc-supply = <®_vcc5v>;
+ vind-supply = <®_vcc5v>;
+ vine-supply = <®_vcc5v>;
+ aldoin-supply = <®_vcc5v>;
+ bldoin-supply = <®_vcc5v>;
+ cldoin-supply = <®_vcc5v>;
regulators {
reg_aldo1: aldo1 {
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usb2otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb2phy {
+ usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */
+ usb0_vbus-supply = <®_vcc5v>;
+ usb3_vbus-supply = <®_vcc5v>;
+ status = "okay";
+};
compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
};
};
+
+ reg_usb_vbus: vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
-&mmc0 {
+&emac {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <®_aldo2>;
+ allwinner,rx-delay-ps = <200>;
+ allwinner,tx-delay-ps = <200>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&mmc0 {
vmmc-supply = <®_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
status = "okay";
};
&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <®_cldo1>;
vqmmc-supply = <®_bldo2>;
non-removable;
cap-mmc-hw-reset;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
status = "okay";
};
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-ac200";
+ regulator-enable-ramp-delay = <100000>;
};
reg_aldo3: aldo3 {
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usb2otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ usb0_vbus-supply = <®_usb_vbus>;
+ usb3_vbus-supply = <®_usb_vbus>;
+ status = "okay";
+};
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
/ {
interrupt-parent = <&gic>;
#size-cells = <0>;
cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
cpu2: cpu@2 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
cpu3: cpu@3 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
};
};
+ de: display-engine {
+ compatible = "allwinner,sun50i-h6-display-engine";
+ allwinner,pipelines = <&mixer0>;
+ status = "disabled";
+ };
+
iosc: internal-osc-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
#size-cells = <1>;
ranges;
+ display-engine@1000000 {
+ compatible = "allwinner,sun50i-h6-de3",
+ "allwinner,sun50i-a64-de2";
+ reg = <0x1000000 0x400000>;
+ allwinner,sram = <&de2_sram 1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000000 0x400000>;
+
+ display_clocks: clock@0 {
+ compatible = "allwinner,sun50i-h6-de3-clk";
+ reg = <0x0 0x10000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@100000 {
+ compatible = "allwinner,sun50i-h6-de3-mixer-0";
+ reg = <0x100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon_top_mixer0: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+ };
+ };
+ };
+ };
+ };
+
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun50i-h6-video-engine";
+ reg = <0x01c0e000 0x2000>;
+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_MBUS_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_VE>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ allwinner,sram = <&ve_sram 1>;
+ };
+
+ syscon: syscon@3000000 {
+ compatible = "allwinner,sun50i-h6-system-control",
+ "allwinner,sun50i-a64-system-control";
+ reg = <0x03000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@28000 {
+ compatible = "mmio-sram";
+ reg = <0x00028000 0x1e000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00028000 0x1e000>;
+
+ de2_sram: sram-section@0 {
+ compatible = "allwinner,sun50i-h6-sram-c",
+ "allwinner,sun50i-a64-sram-c";
+ reg = <0x0000 0x1e000>;
+ };
+ };
+
+ sram_c1: sram@1a00000 {
+ compatible = "mmio-sram";
+ reg = <0x01a00000 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01a00000 0x200000>;
+
+ ve_sram: sram-section@0 {
+ compatible = "allwinner,sun50i-h6-sram-c1",
+ "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x200000>;
+ };
+ };
+ };
+
ccu: clock@3001000 {
compatible = "allwinner,sun50i-h6-ccu";
reg = <0x03001000 0x1000>;
#reset-cells = <1>;
};
- gic: interrupt-controller@3021000 {
- compatible = "arm,gic-400";
- reg = <0x03021000 0x1000>,
- <0x03022000 0x2000>,
- <0x03024000 0x2000>,
- <0x03026000 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- interrupt-controller;
- #interrupt-cells = <3>;
+ sid: sid@3006000 {
+ compatible = "allwinner,sun50i-h6-sid";
+ reg = <0x03006000 0x400>;
};
pio: pinctrl@300b000 {
interrupt-controller;
#interrupt-cells = <3>;
+ ext_rgmii_pins: rgmii-pins {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ "PD5", "PD7", "PD8", "PD9", "PD10",
+ "PD11", "PD12", "PD13", "PD19", "PD20";
+ function = "emac";
+ drive-strength = <40>;
+ };
+
+ hdmi_pins: hdmi-pins {
+ pins = "PH8", "PH9", "PH10";
+ function = "hdmi";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
bias-pull-up;
};
- uart0_ph_pins: uart0-ph {
+ uart0_ph_pins: uart0-ph-pins {
pins = "PH0", "PH1";
function = "uart0";
};
};
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
mmc0: mmc@4020000 {
compatible = "allwinner,sun50i-h6-mmc",
"allwinner,sun50i-a64-mmc";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
+ emac: ethernet@5020000 {
+ compatible = "allwinner,sun50i-h6-emac",
+ "allwinner,sun50i-a64-emac";
+ syscon = <&syscon>;
+ reg = <0x05020000 0x10000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ usb2otg: usb@5100000 {
+ compatible = "allwinner,sun50i-h6-musb",
+ "allwinner,sun8i-a33-musb";
+ reg = <0x05100000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usb2phy 0>;
+ phy-names = "usb";
+ extcon = <&usb2phy 0>;
+ status = "disabled";
+ };
+
+ usb2phy: phy@5100400 {
+ compatible = "allwinner,sun50i-h6-usb-phy";
+ reg = <0x05100400 0x24>,
+ <0x05101800 0x4>,
+ <0x05311800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu3";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY3>;
+ clock-names = "usb0_phy",
+ "usb3_phy";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY3>;
+ reset-names = "usb0_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@5101000 {
+ compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
+ reg = <0x05101000 0x100>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@5101400 {
+ compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
+ reg = <0x05101400 0x100>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
+ ehci3: usb@5311000 {
+ compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
+ reg = <0x05311000 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_BUS_EHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>,
+ <&ccu RST_BUS_EHCI3>;
+ phys = <&usb2phy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb@5311400 {
+ compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
+ reg = <0x05311400 0x100>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>;
+ phys = <&usb2phy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ hdmi: hdmi@6000000 {
+ compatible = "allwinner,sun50i-h6-dw-hdmi";
+ reg = <0x06000000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
+ <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
+ clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
+ "hdcp-bus";
+ resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
+ reset-names = "ctrl", "hdcp";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon_top: endpoint {
+ remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy@6010000 {
+ compatible = "allwinner,sun50i-h6-hdmi-phy";
+ reg = <0x06010000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_HDMI>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
+ tcon_top: tcon-top@6510000 {
+ compatible = "allwinner,sun50i-h6-tcon-top";
+ reg = <0x06510000 0x1000>;
+ clocks = <&ccu CLK_BUS_TCON_TOP>,
+ <&ccu CLK_TCON_TV0>;
+ clock-names = "bus",
+ "tcon-tv0";
+ clock-output-names = "tcon-top-tv0";
+ resets = <&ccu RST_BUS_TCON_TOP>;
+ reset-names = "rst";
+ #clock-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon_top_mixer0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_top_mixer0_out_tcon_tv: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_hdmi_in: port@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ tcon_top_hdmi_in_tcon_tv: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_tv_out_tcon_top>;
+ };
+ };
+
+ tcon_top_hdmi_out: port@5 {
+ reg = <5>;
+
+ tcon_top_hdmi_out_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in_tcon_top>;
+ };
+ };
+ };
+ };
+
+ tcon_tv: lcd-controller@6515000 {
+ compatible = "allwinner,sun50i-h6-tcon-tv",
+ "allwinner,sun8i-r40-tcon-tv";
+ reg = <0x06515000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV0>,
+ <&tcon_top CLK_TCON_TOP_TV0>;
+ clock-names = "ahb",
+ "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV0>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv_in: port@0 {
+ reg = <0>;
+
+ tcon_tv_in_tcon_top_mixer0: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
+ };
+ };
+
+ tcon_tv_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_tv_out_tcon_top: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
+ };
+ };
+ };
+ };
+
r_ccu: clock@7010000 {
compatible = "allwinner,sun50i-h6-r-ccu";
reg = <0x07010000 0x400>;
interrupt-controller;
#interrupt-cells = <3>;
- r_i2c_pins: r-i2c {
+ r_i2c_pins: r-i2c-pins {
pins = "PL0", "PL1";
function = "s_i2c";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_bpi_m1p>;
green {
label = "bananapi-m1-plus:green:usr";
mmc3_pwrseq: mmc3_pwrseq {
compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pwrseq_pin_bpi_m1p>;
reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_power_pin_bpi_m1p>;
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
&mmc3 {
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>;
vmmc-supply = <®_vcc3v3>;
mmc-pwrseq = <&mmc3_pwrseq>;
bus-width = <4>;
};
};
-&mmc3_pins_a {
- /* AP6210 requires pull-up */
- bias-pull-up;
-};
-
&ohci0 {
status = "okay";
};
status = "okay";
};
-&pio {
- gmac_power_pin_bpi_m1p: gmac_power_pin@0 {
- pins = "PH23";
- function = "gpio_out";
- };
-
- led_pins_bpi_m1p: led_pins@0 {
- pins = "PH24", "PH25";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_bpi_m1p: mmc0_cd_pin@0 {
- pins = "PH10";
- function = "gpio_in";
- bias-pull-up;
- };
-
- mmc3_pwrseq_pin_bpi_m1p: mmc3_pwrseq_pin@0 {
- pins = "PH22";
- function = "gpio_out";
- };
-};
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_bananapi>;
green {
label = "bananapi:green:usr";
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_power_pin_bananapi>;
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
};
&pio {
+ vcc-pa-supply = <®_vcc3v3>;
+ vcc-pc-supply = <®_vcc3v3>;
+ vcc-pe-supply = <®_vcc3v3>;
+ vcc-pf-supply = <®_vcc3v3>;
+ vcc-pg-supply = <®_vcc3v3>;
gpio-line-names =
/* PA */
"ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3",
"IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "",
"", "", "", "", "", "", "", "";
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
-
- mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
- pins = "PH10";
- function = "gpio_in";
- bias-pull-up;
- };
-
- gmac_power_pin_bananapi: gmac_power_pin@0 {
- pins = "PH23";
- function = "gpio_out";
- };
-
- led_pins_bananapi: led_pins@0 {
- pins = "PH24";
- function = "gpio_out";
- };
};
#include "axp209.dtsi"
&spi0 {
pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins_a>,
- <&spi0_cs0_pins_a>,
- <&spi0_cs1_pins_a>;
+ pinctrl-0 = <&spi0_pi_pins>,
+ <&spi0_cs0_pi_pin>,
+ <&spi0_cs1_pi_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_b>;
+ pinctrl-0 = <&uart3_ph_pins>;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-0 = <&uart7_pi_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_bananapro>;
blue {
label = "bananapro:blue:usr";
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&vmmc3_pin_bananapro>;
reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>;
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_power_pin_bananapro>;
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
};
&mmc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>;
vmmc-supply = <®_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
status = "okay";
};
-&pio {
- gmac_power_pin_bananapro: gmac_power_pin@0 {
- pins = "PH23";
- function = "gpio_out";
- };
-
- led_pins_bananapro: led_pins@0 {
- pins = "PH24", "PG2";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_bananapro: mmc0_cd_pin@0 {
- pins = "PH10";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
- pins = "PH0";
- function = "gpio_out";
- };
-
- usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
- pins = "PH1";
- function = "gpio_out";
- };
-
- vmmc3_pin_bananapro: vmmc3_pin@0 {
- pins = "PH22";
- function = "gpio_out";
- };
-};
-
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_bananapro>;
gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */
status = "okay";
};
®_usb2_vbus {
- pinctrl-0 = <&usb2_vbus_pin_bananapro>;
gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
status = "okay";
};
&spi0 {
pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins_a>,
- <&spi0_cs0_pins_a>,
- <&spi0_cs1_pins_a>;
+ pinctrl-0 = <&spi0_pi_pins>,
+ <&spi0_cs0_pi_pin>,
+ <&spi0_cs1_pi_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_b>;
+ pinctrl-0 = <&uart4_ph_pins>;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-0 = <&uart7_pi_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_cubieboard2>;
blue {
label = "cubieboard2:blue:usr";
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
+ pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&pio {
- led_pins_cubieboard2: led_pins@0 {
- pins = "PH20", "PH21";
- function = "gpio_out";
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_cubietruck>;
blue {
label = "cubietruck:blue:usr";
mmc3_pwrseq: mmc3_pwrseq {
compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pwrseq_pin_cubietruck>;
reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
+ clocks = <&ccu CLK_OUT_A>;
+ clock-names = "ext_clock";
};
sound {
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&mmc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>;
vmmc-supply = <®_vcc3v3>;
mmc-pwrseq = <&mmc3_pwrseq>;
bus-width = <4>;
};
};
-&mmc3_pins_a {
- /* AP6210 requires pull-up */
- bias-pull-up;
-};
-
&ohci0 {
status = "okay";
};
};
&pio {
- ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
- pins = "PH12";
- function = "gpio_out";
- };
-
- led_pins_cubietruck: led_pins@0 {
- pins = "PH7", "PH11", "PH20", "PH21";
- function = "gpio_out";
- };
-
- mmc3_pwrseq_pin_cubietruck: mmc3_pwrseq_pin@0 {
- pins = "PH9";
- function = "gpio_out";
- };
-
- usb0_vbus_pin_a: usb0_vbus_pin@0 {
- pins = "PH17";
- function = "gpio_out";
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PH19";
- function = "gpio_in";
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- pins = "PH22";
- function = "gpio_in";
- };
+ /* Pin outputs low power clock for WiFi and BT */
+ pinctrl-0 = <&clk_out_a_pin>;
+ pinctrl-names = "default";
};
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>;
+ pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>;
status = "okay";
};
®_ahci_5v {
- pinctrl-0 = <&ahci_pwr_pin_cubietruck>;
gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
®_usb0_vbus {
- pinctrl-0 = <&usb0_vbus_pin_a>;
gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&spdif {
pinctrl-names = "default";
- pinctrl-0 = <&spdif_tx_pins_a>;
+ pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>;
+ uart-has-rtscts;
status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm20702a1";
+ clocks = <&ccu CLK_OUT_A>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
+ host-wakeup-gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
+ shutdown-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */
+ max-speed = <1500000>;
+ };
};
&usb_otg {
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
usb0_vbus_power-supply = <&usb_power_supply>;
reg_mmc3_vdd: mmc3_vdd {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>;
regulator-name = "mmc3_vdd";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
reg_gmac_vdd: gmac_vdd {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>;
regulator-name = "gmac_vdd";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_gmac_vdd>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins_a>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&mmc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>;
vmmc-supply = <®_mmc3_vdd>;
bus-width = <4>;
non-removable;
status = "okay";
};
-&pio {
- ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 {
- pins = "PH15";
- function = "gpio_out";
- };
-
- usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 {
- pins = "PH2";
- function = "gpio_out";
- };
-
- mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 {
- pins = "PH9";
- function = "gpio_out";
- };
-
- gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 {
- pins = "PH16";
- function = "gpio_out";
- };
-};
-
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins_a>;
+ pinctrl-0 = <&pwm0_pin>;
status = "okay";
};
®_ahci_5v {
- pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>;
gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
status = "okay";
};
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>;
gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
status = "okay";
};
&spi2 {
pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_b>,
- <&spi2_cs0_pins_b>;
+ pinctrl-0 = <&spi2_pb_pins>,
+ <&spi2_cs0_pb_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins_a>;
+ pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_a>;
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-0 = <&uart4_pg_pins>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
- pinctrl-0 = <&uart5_pins_a>;
+ pinctrl-0 = <&uart5_pi_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_i12_tvbox>;
red {
label = "i12_tvbox:red:usr";
reg_vmmc3: vmmc3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&vmmc3_pin_i12_tvbox>;
regulator-name = "vmmc3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
reg_vmmc3_io: vmmc3-io {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&vmmc3_io_pin_i12_tvbox>;
regulator-name = "vmmc3-io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_power_pin_i12_tvbox>;
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
+ pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-mode = "mii";
phy-supply = <®_gmac_3v3>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&mmc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>;
vmmc-supply = <®_vmmc3>;
bus-width = <4>;
non-removable;
};
};
-&mmc3_pins_a {
- /* AP6210 / AP6330 requires pull-up */
- bias-pull-up;
-};
-
&ohci0 {
status = "okay";
};
status = "okay";
};
-&pio {
- vmmc3_pin_i12_tvbox: vmmc3_pin@0 {
- pins = "PH2";
- function = "gpio_out";
- };
-
- vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 {
- pins = "PH12";
- function = "gpio_out";
- };
-
- gmac_power_pin_i12_tvbox: gmac_power_pin@0 {
- pins = "PH21";
- function = "gpio_out";
- };
-
- led_pins_i12_tvbox: led_pins@0 {
- pins = "PH9", "PH20";
- function = "gpio_out";
- };
-};
-
®_usb1_vbus {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
+ pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
+ pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&pio {
- led_pins_itead_core: led_pins@0 {
+ led_pins_itead_core: led-pins {
pins = "PH20","PH21";
function = "gpio_out";
drive-strength = <20>;
&spdif {
pinctrl-names = "default";
- pinctrl-0 = <&spdif_tx_pins_a>;
+ pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_lamobo_r1>;
green {
label = "lamobo_r1:green:usr";
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_power_pin_lamobo_r1>;
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
status = "okay";
+ /delete-property/#address-cells;
+ /delete-property/#size-cells;
fixed-link {
speed = <1000>;
switch: ethernet-switch@1e {
compatible = "brcm,bcm53125";
reg = <30>;
- #address-cells = <1>;
- #size-cells = <0>;
ports {
#address-cells = <1>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
};
&pio {
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
-
- mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 {
- pins = "PH10";
- function = "gpio_in";
- bias-pull-up;
- };
-
- gmac_power_pin_lamobo_r1: gmac_power_pin@0 {
- pins = "PH23";
- function = "gpio_out";
- };
-
- led_pins_lamobo_r1: led_pins@0 {
- pins = "PH24";
- function = "gpio_out";
- };
};
#include "axp209.dtsi"
&spi0 {
pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins_a>,
- <&spi0_cs0_pins_a>,
- <&spi0_cs1_pins_a>;
+ pinctrl-0 = <&spi0_pi_pins>,
+ <&spi0_cs0_pi_pin>,
+ <&spi0_cs1_pi_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_b>;
+ pinctrl-0 = <&uart3_ph_pins>;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-0 = <&uart7_pi_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_m3>;
blue {
label = "m3:blue:usr";
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
+ pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
non-removable;
status = "okay";
};
-&pio {
- led_pins_m3: led_pins@0 {
- pins = "PH20";
- function = "gpio_out";
- };
-};
-
®_usb1_vbus {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
};
};
+&ahci {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PH4";
- function = "gpio_in";
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- pins = "PH5";
- function = "gpio_in";
- };
-};
-
®_usb0_vbus {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins_a>;
+ pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>;
status = "okay";
};
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som-evb.dts"
+
+/ {
+
+ model = "Olimex A20-Olimex-SOM-EVB-eMMC";
+ compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
+
+ mmc2_pwrseq: mmc2_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mmc2 {
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc2_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ emmc: emmc@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_olimex_som_evb>;
green {
label = "a20-olimex-som-evb:green:usr";
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
vref-supply = <®_vcc3v0>;
status = "okay";
- button@190 {
+ button-190 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <190000>;
};
- button@390 {
+ button-390 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <390000>;
};
- button@600 {
+ button-600 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <600000>;
};
- button@800 {
+ button-800 {
label = "Search";
linux,code = <KEY_SEARCH>;
channel = <0>;
voltage = <800000>;
};
- button@980 {
+ button-980 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
voltage = <980000>;
};
- button@1180 {
+ button-1180 {
label = "Esc";
linux,code = <KEY_ESC>;
channel = <0>;
voltage = <1180000>;
};
- button@1400 {
+ button-1400 {
label = "Enter";
linux,code = <KEY_ENTER>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&mmc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */
};
&pio {
- ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin@1 {
- pins = "PC3";
- function = "gpio_out";
- };
-
- led_pins_olimex_som_evb: led_pins@0 {
+ led_pins_olimex_som_evb: led-pins {
pins = "PH2";
function = "gpio_out";
drive-strength = <20>;
};
-
- mmc3_cd_pin_olimex_som_evb: mmc3_cd_pin@0 {
- pins = "PH0";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PH4";
- function = "gpio_in";
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- pins = "PH5";
- function = "gpio_in";
- };
};
®_ahci_5v {
- pinctrl-0 = <&ahci_pwr_pin_olimex_som_evb>;
gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>,
- <&spi1_cs0_pins_a>;
+ pinctrl-0 = <&spi1_pi_pins>,
+ <&spi1_cs0_pi_pin>;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>,
- <&spi2_cs0_pins_a>;
+ pinctrl-0 = <&spi2_pc_pins>,
+ <&spi2_cs0_pc_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart6 {
pinctrl-names = "default";
- pinctrl-0 = <&uart6_pins_a>;
+ pinctrl-0 = <&uart6_pi_pins>;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-0 = <&uart7_pi_pins>;
status = "okay";
};
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */
usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */
usb0_vbus-supply = <®_usb0_vbus>;
};
&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_a>;
vmmc-supply = <®_vcc3v3>;
mmc-pwrseq = <&mmc2_pwrseq>;
bus-width = <4>;
&can0 {
pinctrl-names = "default";
- pinctrl-0 = <&can0_pins_a>;
+ pinctrl-0 = <&can_ph_pins>;
status = "okay";
};
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy3>;
phy-mode = "rgmii";
phy-supply = <®_vcc3v3>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
/* Exposed to UEXT1 */
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
eeprom: eeprom@50 {
/* Exposed to UEXT2 */
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>;
};
&mmc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>;
vmmc-supply = <®_vcc3v3>;
mmc-pwrseq = <&rtl_pwrseq>;
bus-width = <4>;
};
&pio {
- bt_uart_pins: bt_uart_pins@0 {
- pins = "PG6", "PG7", "PG8";
+ uart3_rts_pin: uart3-rts-pin {
+ pins = "PG8";
function = "uart3";
};
};
/* Exposed to UEXT1 */
&spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>,
- <&spi1_cs0_pins_a>;
+ pinctrl-0 = <&spi1_pi_pins>,
+ <&spi1_cs0_pi_pin>;
status = "okay";
};
/* Exposed to UEXT2 */
&spi2 {
pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>,
- <&spi2_cs0_pins_a>;
+ pinctrl-0 = <&spi2_pc_pins>,
+ <&spi2_cs0_pc_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
/* Used for RTL8723BS bluetooth */
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&bt_uart_pins>;
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_pin>;
status = "okay";
};
/* Exposed to UEXT1 */
&uart4 {
pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-0 = <&uart4_pg_pins>;
status = "okay";
};
/* Exposed to UEXT2 */
&uart7 {
pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-0 = <&uart7_pi_pins>;
status = "okay";
};
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
+ pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
eeprom: eeprom@50 {
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&pio {
- ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
- pins = "PC3";
- function = "gpio_out";
- };
-
- led_pins_olinuxinolime: led_pins@0 {
+ led_pins_olinuxinolime: led-pins {
pins = "PH2";
function = "gpio_out";
drive-strength = <20>;
};
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
®_ahci_5v {
- pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20";
mmc2_pwrseq: pwrseq {
- pinctrl-0 = <&mmc2_pins_nrst>;
- pinctrl-names = "default";
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
};
};
-&pio {
- mmc2_pins_nrst: mmc2-rst-pin {
- pins = "PC16";
- function = "gpio_out";
- };
-};
-
&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_a>;
vmmc-supply = <®_vcc3v3>;
vqmmc-supply = <®_vcc3v3>;
bus-width = <4>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
eeprom: eeprom@50 {
};
};
+&lradc {
+ vref-supply = <®_vcc3v0>;
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&pio {
- ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
- pins = "PC3";
- function = "gpio_out";
- };
-
- led_pins_olinuxinolime: led_pins@0 {
+ led_pins_olinuxinolime: led-pins {
pins = "PH2";
function = "gpio_out";
drive-strength = <20>;
};
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
-
- usb0_vbus_pin_lime2: usb0_vbus_pin@0 {
- pins = "PC17";
- function = "gpio_out";
- };
};
®_ahci_5v {
- pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vddio-csi0";
+ regulator-soft-start;
+ regulator-ramp-delay = <1600>;
};
®_ldo4 {
};
®_usb0_vbus {
- pinctrl-0 = <&usb0_vbus_pin_lime2>;
gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
};
&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
non-removable;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>, <&gmac_txerr>;
+ pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
eeprom: eeprom@50 {
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
vref-supply = <®_vcc3v0>;
status = "okay";
- button@191 {
+ button-191 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <191274>;
};
- button@392 {
+ button-392 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <392644>;
};
- button@601 {
+ button-601 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <601151>;
};
- button@795 {
+ button-795 {
label = "Search";
linux,code = <KEY_SEARCH>;
channel = <0>;
voltage = <795090>;
};
- button@987 {
+ button-987 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
voltage = <987387>;
};
- button@1184 {
+ button-1184 {
label = "Esc";
linux,code = <KEY_ESC>;
channel = <0>;
voltage = <1184678>;
};
- button@1398 {
+ button-1398 {
label = "Enter";
linux,code = <KEY_ENTER>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&mmc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
};
&pio {
- gmac_txerr: gmac_txerr@0 {
+ gmac_txerr: gmac-txerr-pin {
pins = "PA17";
function = "gmac";
};
- mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
- pins = "PH11";
- function = "gpio_in";
- bias-pull-up;
- };
-
- led_pins_olinuxino: led_pins@0 {
+ led_pins_olinuxino: led-pins {
pins = "PH2";
function = "gpio_out";
drive-strength = <20>;
};
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
&spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins_a>,
- <&spi1_cs0_pins_a>;
+ pinctrl-0 = <&spi1_pi_pins>,
+ <&spi1_cs0_pi_pin>;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>,
- <&spi2_cs0_pins_a>;
+ pinctrl-0 = <&spi2_pc_pins>,
+ <&spi2_cs0_pc_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart6 {
pinctrl-names = "default";
- pinctrl-0 = <&uart6_pins_a>;
+ pinctrl-0 = <&uart6_pi_pins>;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-0 = <&uart7_pi_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_orangepi>;
green {
label = "orangepi:green:usr";
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_power_pin_orangepi>;
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
};
&mmc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
};
&pio {
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
-
- mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
- pins = "PH10";
- function = "gpio_in";
- bias-pull-up;
- };
-
- mmc3_cd_pin_orangepi: mmc3_cd_pin@0 {
- pins = "PH11";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
- pins = "PH22";
- function = "gpio_out";
- };
-
- gmac_power_pin_orangepi: gmac_power_pin@0 {
- pins = "PH23";
- function = "gpio_out";
- };
-
- led_pins_orangepi: led_pins@0 {
- pins = "PH24", "PH25";
- function = "gpio_out";
- };
-
- usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
- pins = "PH26";
- function = "gpio_out";
- };
};
®_dcdc2 {
};
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_bananapro>;
gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */
status = "okay";
};
®_usb2_vbus {
- pinctrl-0 = <&usb2_vbus_pin_bananapro>;
gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_orangepi>;
green {
label = "orangepi:green:usr";
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_power_pin_orangepi>;
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
};
&pio {
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
-
- mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
- pins = "PH10";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
- pins = "PH22";
- function = "gpio_out";
- };
-
- gmac_power_pin_orangepi: gmac_power_pin@0 {
- pins = "PH23";
- function = "gpio_out";
- };
-
- led_pins_orangepi: led_pins@0 {
- pins = "PH24";
- function = "gpio_out";
- };
-
- usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
- pins = "PH26";
- function = "gpio_out";
- };
};
®_dcdc2 {
};
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_bananapro>;
gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */
status = "okay";
};
®_usb2_vbus {
- pinctrl-0 = <&usb2_vbus_pin_bananapro>;
gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_pcduino3_nano>;
/* Marked "LED3" on the PCB. */
usr1 {
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&pio {
- ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 {
- pins = "PH2";
- function = "gpio_out";
- };
-
- led_pins_pcduino3_nano: led_pins@0 {
- pins = "PH16", "PH15";
- function = "gpio_out";
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
-
- usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 {
- pins = "PD2";
- function = "gpio_out";
- };
};
®_ahci_5v {
- pinctrl-0 = <&ahci_pwr_pin_pcduino3_nano>;
gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
status = "okay";
};
/* A single regulator (U24) powers both USB host ports. */
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_pcduino3_nano>;
gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_pcduino3>;
tx {
label = "pcduino3:green:tx";
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&key_pins_pcduino3>;
- #address-cells = <1>;
- #size-cells = <0>;
- button@0 {
+
+ back {
label = "Key Back";
linux,code = <KEY_BACK>;
gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
};
- button@1 {
+
+ home {
label = "Key Home";
linux,code = <KEY_HOME>;
gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
};
- button@2 {
+
+ menu {
label = "Key Menu";
linux,code = <KEY_MENU>;
gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
+ pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pin>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&pio {
- led_pins_pcduino3: led_pins@0 {
- pins = "PH15", "PH16";
- function = "gpio_out";
- };
-
- key_pins_pcduino3: key_pins@0 {
- pins = "PH17", "PH18", "PH19";
- function = "gpio_in";
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
- pinctrl-names = "default";
- pinctrl-0 = <&bl_enable_pin>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
};
};
&codec {
- pinctrl-names = "default";
- pinctrl-0 = <&codec_pa_pin>;
allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
#include "axp209.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
gt911: touchscreen@5d {
reg = <0x5d>;
interrupt-parent = <&pio>;
interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */
- pinctrl-names = "default";
- pinctrl-0 = <&ts_reset_pin>;
irq-gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* INT (PH21) */
reset-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* RST (PB13) */
touchscreen-swapped-x-y;
vref-supply = <®_vcc3v0>;
status = "okay";
- button@571 {
+ button-571 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <571428>;
};
- button@761 {
+ button-761 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&pio {
- bl_enable_pin: bl_enable_pin@0 {
- pins = "PH7";
- function = "gpio_out";
- };
-
- codec_pa_pin: codec_pa_pin@0 {
- pins = "PH15";
- function = "gpio_out";
- };
-
- ts_reset_pin: ts_reset_pin@0 {
- pins = "PB13";
- function = "gpio_out";
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins_a>;
+ pinctrl-0 = <&pwm0_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "sunxi-u-boot.dtsi"
+
+&ahci {
+ status = "okay";
+};
mmc3_pwrseq: mmc3_pwrseq {
compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&vmmc3_pin_ap6xxx_wl_regon>;
reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
};
};
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
#include "axp209.dtsi"
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
};
&mmc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins_a>;
vmmc-supply = <®_vcc3v3>;
mmc-pwrseq = <&mmc3_pwrseq>;
bus-width = <4>;
};
&pio {
- vmmc3_pin_ap6xxx_wl_regon: vmmc3_pin@0 {
- pins = "PH9";
- function = "gpio_out";
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/dma/sun4i-a10.h>
/ {
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
aliases {
ethernet0 = &gmac;
#size-cells = <1>;
ranges;
- framebuffer@0 {
+ framebuffer-lcd0-hdmi {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
status = "disabled";
};
- framebuffer@1 {
+ framebuffer-lcd0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
status = "disabled";
};
- framebuffer@2 {
+ framebuffer-lcd0-tve0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
#cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
+ clocks = <&ccu CLK_CPU>;
+ clock-latency = <244144>; /* 8 32k periods */
+ operating-points = <
+ /* kHz uV */
+ 960000 1400000
+ 912000 1400000
+ 864000 1300000
+ 720000 1200000
+ 528000 1100000
+ 312000 1000000
+ 144000 1000000
+ >;
+ #cooling-cells = <2>;
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
- memory {
- reg = <0x40000000 0x80000000>;
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+ default-pool {
+ compatible = "shared-dma-pool";
+ size = <0x6000000>;
+ alloc-ranges = <0x4a000000 0x6000000>;
+ reusable;
+ linux,cma-default;
+ };
};
timer {
};
pmu {
- compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
};
#size-cells = <1>;
ranges;
- osc24M: clk@1c20050 {
+ osc24M: clk-24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
- osc32k: clk@0 {
+ osc32k: clk-32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
* The actual TX clock rate is not controlled by the
* gmac_tx clock.
*/
- mii_phy_tx_clk: clk@1 {
+ mii_phy_tx_clk: clk-mii-phy-tx {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "mii_phy_tx";
};
- gmac_int_tx_clk: clk@2 {
+ gmac_int_tx_clk: clk-gmac-int-tx {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
status = "disabled";
};
- soc@1c00000 {
+ soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sram-controller@1c00000 {
- compatible = "allwinner,sun4i-a10-sram-controller";
+ system-control@1c00000 {
+ compatible = "allwinner,sun7i-a20-system-control",
+ "allwinner,sun4i-a10-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00000000 0xc000>;
emac_sram: sram-section@8000 {
- compatible = "allwinner,sun4i-a10-sram-a3-a4";
+ compatible = "allwinner,sun7i-a20-sram-a3-a4",
+ "allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
status = "disabled";
};
ranges = <0 0x00010000 0x1000>;
otg_sram: sram-section@0 {
- compatible = "allwinner,sun4i-a10-sram-d";
+ compatible = "allwinner,sun7i-a20-sram-d",
+ "allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
+
+ sram_c: sram@1d00000 {
+ compatible = "mmio-sram";
+ reg = <0x01d00000 0xd0000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01d00000 0xd0000>;
+
+ ve_sram: sram-section@0 {
+ compatible = "allwinner,sun7i-a20-sram-c1",
+ "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x80000>;
+ };
+ };
};
nmi_intc: interrupt-controller@1c00030 {
};
};
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun7i-a20-video-engine";
+ reg = <0x01c0e000 0x1000>;
+ clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_VE>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ allwinner,sram = <&ve_sram 1>;
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
"output",
"sample";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
"output",
"sample";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
"output",
"sample";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
hdmi_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
};
};
#interrupt-cells = <3>;
#gpio-cells = <3>;
- can0_pins_a: can0@0 {
+ can_ph_pins: can-ph-pins {
pins = "PH20", "PH21";
function = "can";
};
- clk_out_a_pins_a: clk_out_a@0 {
+ clk_out_a_pin: clk-out-a-pin {
pins = "PI12";
function = "clk_out_a";
};
- clk_out_b_pins_a: clk_out_b@0 {
+ clk_out_b_pin: clk-out-b-pin {
pins = "PI13";
function = "clk_out_b";
};
- emac_pins_a: emac0@0 {
+ emac_pa_pins: emac-pa-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA9", "PA10",
function = "emac";
};
- gmac_pins_mii_a: gmac_mii@0 {
+ gmac_mii_pins: gmac-mii-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA9", "PA10",
function = "gmac";
};
- gmac_pins_rgmii_a: gmac_rgmii@0 {
+ gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA10",
drive-strength = <40>;
};
- i2c0_pins_a: i2c0@0 {
+ i2c0_pins: i2c0-pins {
pins = "PB0", "PB1";
function = "i2c0";
};
- i2c1_pins_a: i2c1@0 {
+ i2c1_pins: i2c1-pins {
pins = "PB18", "PB19";
function = "i2c1";
};
- i2c2_pins_a: i2c2@0 {
+ i2c2_pins: i2c2-pins {
pins = "PB20", "PB21";
function = "i2c2";
};
- i2c3_pins_a: i2c3@0 {
+ i2c3_pins: i2c3-pins {
pins = "PI0", "PI1";
function = "i2c3";
};
- ir0_rx_pins_a: ir0@0 {
+ ir0_rx_pin: ir0-rx-pin {
pins = "PB4";
function = "ir0";
};
- ir0_tx_pins_a: ir0@1 {
+ ir0_tx_pin: ir0-tx-pin {
pins = "PB3";
function = "ir0";
};
- ir1_rx_pins_a: ir1@0 {
+ ir1_rx_pin: ir1-rx-pin {
pins = "PB23";
function = "ir1";
};
- ir1_tx_pins_a: ir1@1 {
+ ir1_tx_pin: ir1-tx-pin {
pins = "PB22";
function = "ir1";
};
- mmc0_pins_a: mmc0@0 {
+ mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
function = "mmc0";
bias-pull-up;
};
- mmc2_pins_a: mmc2@0 {
+ mmc2_pins: mmc2-pins {
pins = "PC6", "PC7", "PC8",
"PC9", "PC10", "PC11";
function = "mmc2";
bias-pull-up;
};
- mmc3_pins_a: mmc3@0 {
+ mmc3_pins: mmc3-pins {
pins = "PI4", "PI5", "PI6",
"PI7", "PI8", "PI9";
function = "mmc3";
bias-pull-up;
};
- ps20_pins_a: ps20@0 {
+ ps2_0_pins: ps2-0-pins {
pins = "PI20", "PI21";
function = "ps2";
};
- ps21_pins_a: ps21@0 {
+ ps2_1_ph_pins: ps2-1-ph-pins {
pins = "PH12", "PH13";
function = "ps2";
};
- pwm0_pins_a: pwm0@0 {
+ pwm0_pin: pwm0-pin {
pins = "PB2";
function = "pwm";
};
- pwm1_pins_a: pwm1@0 {
+ pwm1_pin: pwm1-pin {
pins = "PI3";
function = "pwm";
};
- spdif_tx_pins_a: spdif@0 {
+ spdif_tx_pin: spdif-tx-pin {
pins = "PB13";
function = "spdif";
bias-pull-up;
};
- spi0_pins_a: spi0@0 {
+ spi0_pi_pins: spi0-pi-pins {
pins = "PI11", "PI12", "PI13";
function = "spi0";
};
- spi0_cs0_pins_a: spi0_cs0@0 {
+ spi0_cs0_pi_pin: spi0-cs0-pi-pin {
pins = "PI10";
function = "spi0";
};
- spi0_cs1_pins_a: spi0_cs1@0 {
+ spi0_cs1_pi_pin: spi0-cs1-pi-pin {
pins = "PI14";
function = "spi0";
};
- spi1_pins_a: spi1@0 {
+ spi1_pi_pins: spi1-pi-pins {
pins = "PI17", "PI18", "PI19";
function = "spi1";
};
- spi1_cs0_pins_a: spi1_cs0@0 {
+ spi1_cs0_pi_pin: spi1-cs0-pi-pin {
pins = "PI16";
function = "spi1";
};
- spi2_pins_a: spi2@0 {
- pins = "PC20", "PC21", "PC22";
+ spi2_pb_pins: spi2-pb-pins {
+ pins = "PB15", "PB16", "PB17";
function = "spi2";
};
- spi2_pins_b: spi2@1 {
- pins = "PB15", "PB16", "PB17";
+ spi2_cs0_pb_pin: spi2-cs0-pb-pin {
+ pins = "PB14";
function = "spi2";
};
- spi2_cs0_pins_a: spi2_cs0@0 {
- pins = "PC19";
+ spi2_pc_pins: spi2-pc-pins {
+ pins = "PC20", "PC21", "PC22";
function = "spi2";
};
- spi2_cs0_pins_b: spi2_cs0@1 {
- pins = "PB14";
+ spi2_cs0_pc_pin: spi2-cs0-pc-pin {
+ pins = "PC19";
function = "spi2";
};
- uart0_pins_a: uart0@0 {
+ uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
};
- uart2_pins_a: uart2@0 {
- pins = "PI16", "PI17", "PI18", "PI19";
+ uart2_pi_pins: uart2-pi-pins {
+ pins = "PI18", "PI19";
function = "uart2";
};
- uart3_pins_a: uart3@0 {
- pins = "PG6", "PG7", "PG8", "PG9";
+ uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
+ pins = "PI16", "PI17";
+ function = "uart2";
+ };
+
+ uart3_pg_pins: uart3-pg-pins {
+ pins = "PG6", "PG7";
+ function = "uart3";
+ };
+
+ uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
+ pins = "PG8", "PG9";
function = "uart3";
};
- uart3_pins_b: uart3@1 {
+ uart3_ph_pins: uart3-ph-pins {
pins = "PH0", "PH1";
function = "uart3";
};
- uart4_pins_a: uart4@0 {
+ uart4_pg_pins: uart4-pg-pins {
pins = "PG10", "PG11";
function = "uart4";
};
- uart4_pins_b: uart4@1 {
+ uart4_ph_pins: uart4-ph-pins {
pins = "PH4", "PH5";
function = "uart4";
};
- uart5_pins_a: uart5@0 {
+ uart5_pi_pins: uart5-pi-pins {
pins = "PI10", "PI11";
function = "uart5";
};
- uart6_pins_a: uart6@0 {
+ uart6_pi_pins: uart6-pi-pins {
pins = "PI12", "PI13";
function = "uart6";
};
- uart7_pins_a: uart7@0 {
+ uart7_pi_pins: uart7-pi-pins {
pins = "PI20", "PI21";
function = "uart7";
};
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01c2b800 0x400>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1_I2C3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+ clocks = <&ccu CLK_OUTA>;
+ clock-names = "ext_clock";
};
};
+&ahci {
+ ahci-supply = <®_dldo4>;
+ phy-supply = <®_eldo3>;
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
status = "okay";
&mmc0 {
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
- cd-inverted;
+ cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
status = "okay";
};
status = "okay";
};
+&pio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_out_a_pin>;
+};
+
®_aldo2 {
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-name = "vcc-wifi-io";
};
+/*
+ * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same
+ * time, with the two being in sync, to be able to meet maximum power
+ * consumption during transmits. Since this is not really supported
+ * right now, just use the two as always on, and we will fix it later.
+ */
+
®_dldo2 {
+ regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+®_dldo4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vdd2v5-sata";
+};
+
+®_eldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd1v2-sata";
+};
+
+&tcon_tv0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&ccu CLK_OUTA>;
+ clock-names = "lpo";
+ vbat-supply = <®_dldo2>;
+ vddio-supply = <®_dldo1>;
+ device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
+ /* TODO host wake line connected to PMIC GPIO pins */
+ shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
+ max-speed = <1500000>;
+ };
+};
+
&usbphy {
usb1_vbus-supply = <®_vcc5v0>;
usb2_vbus-supply = <®_vcc5v0>;
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
/ {
#address-cells = <1>;
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
+ clock-accuracy = <50000>;
clock-output-names = "osc24M";
};
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
- clock-output-names = "osc32k";
+ clock-accuracy = <20000>;
+ clock-output-names = "ext-osc32k";
};
};
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-r40-display-engine";
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ display_clocks: clock@1000000 {
+ compatible = "allwinner,sun8i-r40-de2-clk",
+ "allwinner,sun8i-h3-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@1100000 {
+ compatible = "allwinner,sun8i-r40-de2-mixer-0";
+ reg = <0x01100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+ mixer0_out_tcon_top: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@1200000 {
+ compatible = "allwinner,sun8i-r40-de2-mixer-1";
+ reg = <0x01200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ reg = <1>;
+ mixer1_out_tcon_top: endpoint {
+ remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+ };
+ };
+ };
+ };
+
nmi_intc: interrupt-controller@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&osc32k>;
+ clocks = <&osc24M>, <&rtc 0>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
+ rtc: rtc@1c20400 {
+ compatible = "allwinner,sun8i-r40-rtc",
+ "allwinner,sun8i-h3-rtc";
+ reg = <0x01c20400 0x400>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clock-output-names = "osc32k", "osc32k-out";
+ clocks = <&osc32k>;
+ #clock-cells = <1>;
+ };
+
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-r40-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ clk_out_a_pin: clk-out-a-pin {
+ pins = "PI12";
+ function = "clk_out_a";
+ };
+
gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
pins = "PB22", "PB23";
function = "uart0";
};
+
+ uart3_pg_pins: uart3-pg-pins {
+ pins = "PG6", "PG7";
+ function = "uart3";
+ };
+
+ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
+ pins = "PG8", "PG9";
+ function = "uart3";
+ };
};
wdt: watchdog@1c20c90 {
#size-cells = <0>;
};
+ ahci: sata@1c18000 {
+ compatible = "allwinner,sun8i-r40-ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
+ resets = <&ccu RST_BUS_SATA>;
+ resets-name = "ahci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ };
+
gmac: ethernet@1c50000 {
compatible = "allwinner,sun8i-r40-gmac";
syscon = <&ccu>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_GMAC>;
clock-names = "stmmaceth";
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
gmac_mdio: mdio {
};
};
+ tcon_top: tcon-top@1c70000 {
+ compatible = "allwinner,sun8i-r40-tcon-top";
+ reg = <0x01c70000 0x1000>;
+ clocks = <&ccu CLK_BUS_TCON_TOP>,
+ <&ccu CLK_TCON_TV0>,
+ <&ccu CLK_TVE0>,
+ <&ccu CLK_TCON_TV1>,
+ <&ccu CLK_TVE1>,
+ <&ccu CLK_DSI_DPHY>;
+ clock-names = "bus",
+ "tcon-tv0",
+ "tve0",
+ "tcon-tv1",
+ "tve1",
+ "dsi";
+ clock-output-names = "tcon-top-tv0",
+ "tcon-top-tv1",
+ "tcon-top-dsi";
+ resets = <&ccu RST_BUS_TCON_TOP>;
+ #clock-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon_top_mixer0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon_top>;
+ };
+ };
+
+ tcon_top_mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+ reg = <0>;
+ };
+
+ tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
+ reg = <1>;
+ };
+
+ tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+ };
+
+ tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer1_in: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ tcon_top_mixer1_in_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mixer1_out_tcon_top>;
+ };
+ };
+
+ tcon_top_mixer1_out: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+ reg = <0>;
+ };
+
+ tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
+ reg = <1>;
+ };
+
+ tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+ };
+
+ tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
+ };
+ };
+
+ tcon_top_hdmi_in: port@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_tv0_out_tcon_top>;
+ };
+
+ tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_tv1_out_tcon_top>;
+ };
+ };
+
+ tcon_top_hdmi_out: port@5 {
+ reg = <5>;
+
+ tcon_top_hdmi_out_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in_tcon_top>;
+ };
+ };
+ };
+ };
+
+ tcon_tv0: lcd-controller@1c73000 {
+ compatible = "allwinner,sun8i-r40-tcon-tv";
+ reg = <0x01c73000 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV0>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+ };
+
+ tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+ };
+ };
+
+ tcon_tv0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_tv0_out_tcon_top: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+ };
+ };
+ };
+ };
+
+ tcon_tv1: lcd-controller@1c74000 {
+ compatible = "allwinner,sun8i-r40-tcon-tv";
+ reg = <0x01c74000 0x1000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV1>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
+ };
+
+ tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
+ };
+ };
+
+ tcon_tv1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_tv1_out_tcon_top: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+
+ hdmi: hdmi@1ee0000 {
+ compatible = "allwinner,sun8i-r40-dw-hdmi",
+ "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI1>;
+ reset-names = "ctrl";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon_top: endpoint {
+ remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy@1ef0000 {
+ compatible = "allwinner,sun8i-r40-hdmi-phy";
+ reg = <0x01ef0000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu 7>, <&ccu 16>;
+ clock-names = "bus", "mod", "pll-0", "pll-1";
+ resets = <&ccu RST_BUS_HDMI0>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
};
timer {
};
};
+&ahci {
+ phy-supply = <®_eldo3>; /* VDD12-SATA */
+ ahci-supply = <®_dldo4>; /* VDD25-SATA */
+ status = "okay";
+};
+
&ehci1 {
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
&i2c0 {
status = "okay";
- axp22x: pmic@68 {
+ axp22x: pmic@34 {
compatible = "x-powers,axp221";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
regulator-name = "vcc-wifi";
};
+®_dldo4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vdd2v5-sata";
+};
+
+®_eldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd1v2-sata";
+};
+
&mmc0 {
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
cpu0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
cpu1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
cpu0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
+ compatible = "arm,cortex-a72";
reg = <0 0x000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
cpu1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
+ compatible = "arm,cortex-a72";
reg = <0 0x001>;
clocks = <&sys_clk 32>;
enable-method = "psci";
cpu2: cpu@100 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0 0x100>;
clocks = <&sys_clk 33>;
enable-method = "psci";
cpu3: cpu@101 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0 0x101>;
clocks = <&sys_clk 33>;
enable-method = "psci";
cooling-maps {
map0 {
trip = <&cpu_alert>;
- cooling-device = <&cpu0
- THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu_alert>;
- cooling-device = <&cpu2
- THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
};
+ pcie: pcie@66000000 {
+ compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+ status = "disabled";
+ reg-names = "dbi", "link", "config";
+ reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
+ <0x2fff0000 0x10000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&sys_clk 24>;
+ resets = <&sys_rst 24>;
+ num-lanes = <1>;
+ num-viewport = <1>;
+ bus-range = <0x0 0xff>;
+ device_type = "pci";
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
+ /* non-prefetchable memory */
+ <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
+ #interrupt-cells = <1>;
+ interrupt-names = "dma", "msi";
+ interrupts = <0 224 4>, <0 225 4>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
+ <0 0 0 2 &pcie_intc 1>, /* INTB */
+ <0 0 0 3 &pcie_intc 2>, /* INTC */
+ <0 0 0 4 &pcie_intc 3>; /* INTD */
+ phy-names = "pcie-phy";
+ phys = <&pcie_phy>;
+
+ pcie_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 226 4>;
+ };
+ };
+
+ pcie_phy: phy@66038000 {
+ compatible = "socionext,uniphier-ld20-pcie-phy";
+ reg = <0x66038000 0x4000>;
+ #phy-cells = <0>;
+ clocks = <&sys_clk 24>;
+ resets = <&sys_rst 24>;
+ socionext,syscon = <&soc_glue>;
+ };
+
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
};
};
+ dmac: dma-controller@5a000000 {
+ compatible = "socionext,uniphier-mio-dmac";
+ reg = <0x5a000000 0x1000>;
+ interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+ <0 71 4>, <0 72 4>, <0 73 4>;
+ clocks = <&mio_clk 7>;
+ resets = <&mio_rst 7>;
+ #dma-cells = <1>;
+ };
+
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 4>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 6>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
};
};
+ dmac: dma-controller@5a000000 {
+ compatible = "socionext,uniphier-mio-dmac";
+ reg = <0x5a000000 0x1000>;
+ interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+ <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
+ clocks = <&mio_clk 7>;
+ resets = <&mio_rst 7>;
+ #dma-cells = <1>;
+ };
+
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 4>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 5>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
clocks = <&mio_clk 2>;
reset-names = "host", "bridge";
resets = <&mio_rst 2>, <&mio_rst 5>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 6>;
bus-width = <4>;
cap-sd-highspeed;
};
cooling-maps {
map {
trip = <&cpu_alert>;
- cooling-device = <&cpu0
- THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
status = "okay";
};
+&pcie {
+ status = "okay";
+};
+
&nand {
status = "okay";
};
cpu0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
cpu1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
cpu2: cpu@2 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0 0x002>;
clocks = <&sys_clk 33>;
enable-method = "psci";
cpu3: cpu@3 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0 0x003>;
clocks = <&sys_clk 33>;
enable-method = "psci";
};
};
+ pcie: pcie@66000000 {
+ compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+ status = "disabled";
+ reg-names = "dbi", "link", "config";
+ reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
+ <0x2fff0000 0x10000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&sys_clk 24>;
+ resets = <&sys_rst 24>;
+ num-lanes = <1>;
+ num-viewport = <1>;
+ bus-range = <0x0 0xff>;
+ device_type = "pci";
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
+ /* non-prefetchable memory */
+ <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
+ #interrupt-cells = <1>;
+ interrupt-names = "dma", "msi";
+ interrupts = <0 224 4>, <0 225 4>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
+ <0 0 0 2 &pcie_intc 1>, /* INTB */
+ <0 0 0 3 &pcie_intc 2>, /* INTC */
+ <0 0 0 4 &pcie_intc 3>; /* INTD */
+ phy-names = "pcie-phy";
+ phys = <&pcie_phy>;
+
+ pcie_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 226 4>;
+ };
+ };
+
+ pcie_phy: phy@66038000 {
+ compatible = "socionext,uniphier-pxs3-pcie-phy";
+ reg = <0x66038000 0x4000>;
+ #phy-cells = <0>;
+ clocks = <&sys_clk 24>;
+ resets = <&sys_rst 24>;
+ socionext,syscon = <&soc_glue>;
+ };
+
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
};
};
+ dmac: dma-controller@5a000000 {
+ compatible = "socionext,uniphier-mio-dmac";
+ reg = <0x5a000000 0x1000>;
+ interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+ <0 71 4>, <0 72 4>, <0 73 4>;
+ clocks = <&mio_clk 7>;
+ resets = <&mio_rst 7>;
+ #dma-cells = <1>;
+ };
+
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 4>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 6>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
&qspi {
status = "okay";
- flash@0 {
- compatible = "n25q512a11";
+ flash0: flash@0 {
+ compatible = "n25q512a11", "spi-flash";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
prompt "OMAP5 board select"
optional
-config TARGET_CL_SOM_AM57X
- bool "CompuLab CL-SOM-AM57x"
- select DRA7XX
-
config TARGET_CM_T54
bool "CompuLab CM-T54"
endmenu
endif
-source "board/compulab/cl-som-am57x/Kconfig"
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
bool "sun4i (Allwinner A10)"
select CPU_V7A
select ARM_CORTEX_CPU_IS_UP
- select DM_MMC if MMC
- select DM_SCSI if SCSI
select PHY_SUN4I_USB
select DRAM_SUN4I
select SUNXI_GEN_SUN4I
bool "sun5i (Allwinner A13)"
select CPU_V7A
select ARM_CORTEX_CPU_IS_UP
- select DM_MMC if MMC
select DRAM_SUN4I
select PHY_SUN4I_USB
select SUNXI_GEN_SUN4I
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
- select DM_MMC if MMC
select DRAM_SUN6I
select PHY_SUN4I_USB
select SUN6I_P2WI
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
- select DM_MMC if MMC
select DRAM_SUN8I_A23
select PHY_SUN4I_USB
select SUNXI_GEN_SUN6I
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
- select DM_MMC if MMC
select DRAM_SUN8I_A33
select PHY_SUN4I_USB
select SUNXI_GEN_SUN6I
config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
select CPU_V7A
- select DM_MMC if MMC
select DRAM_SUN8I_A83T
select PHY_SUN4I_USB
select SUNXI_GEN_SUN6I
select ARCH_SUPPORT_PSCI
select MACH_SUNXI_H3_H5
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
- select DM_MMC if MMC
config MACH_SUN8I_R40
bool "sun8i (Allwinner R40)"
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
- select DM_MMC if MMC
select SUNXI_GEN_SUN6I
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_16BIT
select SUNXI_GEN_SUN6I
select SUN8I_RSB
select SUPPORT_SPL
- select DM_MMC if MMC
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
select DM_I2C
- select DM_MMC if MMC
select PHY_SUN4I_USB
select SUN6I_PRCM
select SUNXI_DE2
bool "sun50i (Allwinner H5)"
select ARM64
select MACH_SUNXI_H3_H5
- select DM_MMC if MMC
select FIT
select SPL_LOAD_FIT
bool "sun50i (Allwinner H6)"
select ARM64
select SUPPORT_SPL
- select DM_MMC if MMC
select FIT
select SPL_LOAD_FIT
select DRAM_SUN50I_H6
/* Delay is required for clocks to be propagated */
udelay(1000000);
+ debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
/* if both controllers enabled, then these two are the second controller */
-#if defined(SPL_ZYNQMP_TWO_SDHCI)
+#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
return BOOT_DEVICE_MMC2;
/* else, fall through, the one SDHCI controller that is enabled is number 1 */
#endif
+++ /dev/null
-if TARGET_CL_SOM_AM57X
-
-config SYS_BOARD
- default "cl-som-am57x"
-
-config SYS_VENDOR
- default "compulab"
-
-config SYS_CONFIG_NAME
- default "cl-som-am57x"
-
-endif
+++ /dev/null
-CL-SOM-AM57x BOARD
-M: Uri Mashiach <uri.mashiach@compulab.co.il>
-S: Maintained
-F: board/compulab/cl-som-am57x/
-F: include/configs/cl-som-am57x.h
-F: configs/cl-som-am57x_defconfig
+++ /dev/null
-#
-# Makefile
-#
-# (C) Copyright 2016 CompuLab, Ltd. <www.compulab.co.il>
-#
-# Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o mux.o
-else
-obj-y += cl-som-am57x.o mux.o
-endif
-
-obj-$(CONFIG_DRIVER_TI_CPSW) += eth.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board functions for CompuLab cl_som_am57x board
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- */
-
-#include <common.h>
-#include <palmas.h>
-#include <usb.h>
-#include <asm/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include "../common/common.h"
-#include "../common/eeprom.h"
-#include <asm/omap_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
- "Board: CL-SOM-AM57x\n"
-};
-
-int board_init(void)
-{
- /* Disable PMIC Powerhold feature, DEV_CTRL.DEV_ON = 1 */
- palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_MMC
-#define SB_SOM_CD_GPIO 187
-#define SB_SOM_WP_GPIO 188
-
-int board_mmc_init(bd_t *bis)
-{
- int ret0, ret1;
-
- ret0 = omap_mmc_init(0, 0, 0, SB_SOM_CD_GPIO, SB_SOM_WP_GPIO);
- if (ret0)
- printf("cl-som-am57x: failed to initialize mmc0\n");
-
- ret1 = omap_mmc_init(1, 0, 0, -1, -1);
- if (ret1)
- printf("cl-som-am57x: failed to initialize mmc1\n");
-
- return ret0 && ret1;
-}
-#endif /* CONFIG_MMC */
-
-int misc_init_r(void)
-{
- cl_print_pcb_info();
-
- return 0;
-}
-
-u32 get_board_rev(void)
-{
- return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
-}
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- enable_usb_clocks(index);
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- disable_usb_clocks(index);
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Ethernet specific code for CompuLab CL-SOM-AM57x module
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#include <common.h>
-#include <cpsw.h>
-#include <environment.h>
-#include <miiphy.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include "../common/eeprom.h"
-
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-}
-
-static struct cpsw_slave_data cl_som_am57x_cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- .phy_if = PHY_INTERFACE_MODE_RMII,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- .phy_if = PHY_INTERFACE_MODE_RMII,
-
- },
-};
-
-static struct cpsw_platform_data cl_som_am57_cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 2,
- .slave_data = cl_som_am57x_cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-/*
- * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address.
- * The information is retrieved from the SOC's registers.
- * @buff: read buffer.
- * @port_num: port number.
- */
-static void cl_som_am57x_efuse_read_mac_addr(uchar *buff, uint port_num)
-{
- uint32_t mac_hi, mac_lo;
-
- if (port_num) {
- mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
- } else {
- mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
- }
-
- buff[0] = (mac_hi & 0xFF0000) >> 16;
- buff[1] = (mac_hi & 0xFF00) >> 8;
- buff[2] = mac_hi & 0xFF;
- buff[3] = (mac_lo & 0xFF0000) >> 16;
- buff[4] = (mac_lo & 0xFF00) >> 8;
- buff[5] = mac_lo & 0xFF;
-}
-
-/*
- * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot
- * environment.
- * The address is retrieved retrieved from an EEPROM field or from the
- * SOC's registers.
- * @env_name: U-Boot environment name.
- * @field_name: EEPROM field name.
- * @port_num: SOC's port number.
- */
-static int cl_som_am57x_handle_mac_address(char *env_name, uint port_num)
-{
- int ret;
- uint8_t enetaddr[6];
-
- ret = eth_env_get_enetaddr(env_name, enetaddr);
- if (ret)
- return 0;
-
- ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
-
- if (ret || !is_valid_ethaddr(enetaddr))
- cl_som_am57x_efuse_read_mac_addr(enetaddr, port_num);
-
- if (!is_valid_ethaddr(enetaddr))
- return -1;
-
- ret = eth_env_set_enetaddr(env_name, enetaddr);
- if (ret)
- printf("cl-som-am57x: Failed to set Eth port %d MAC address\n",
- port_num);
-
- return ret;
-}
-
-#define CL_SOM_AM57X_PHY_ADDR2 0x01
-#define AR8033_PHY_DEBUG_ADDR_REG 0x1d
-#define AR8033_PHY_DEBUG_DATA_REG 0x1e
-#define AR8033_DEBUG_RGMII_RX_CLK_DLY_REG 0x00
-#define AR8033_DEBUG_RGMII_TX_CLK_DLY_REG 0x05
-#define AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK (1 << 15)
-#define AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK (1 << 8)
-
-/*
- * cl_som_am57x_rgmii_clk_delay() - Set RGMII clock delay.
- * Enable RX delay, disable TX delay.
- */
-static void cl_som_am57x_rgmii_clk_delay(void)
-{
- uint16_t mii_reg_val;
- const char *devname;
-
- devname = miiphy_get_current_dev();
- /* PHY 2 */
- miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG,
- AR8033_DEBUG_RGMII_RX_CLK_DLY_REG);
- miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
- &mii_reg_val);
- mii_reg_val |= AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK;
- miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
- mii_reg_val);
-
- miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG,
- AR8033_DEBUG_RGMII_TX_CLK_DLY_REG);
- miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
- &mii_reg_val);
- mii_reg_val &= ~AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK;
- miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
- mii_reg_val);
-}
-
-#define CL_SOM_AM57X_GPIO_PHY1_RST 92 /* GPIO3_28 */
-#define CL_SOM_AM57X_RGMII_PORT1 1
-
-int board_eth_init(bd_t *bis)
-{
- int ret;
- uint32_t ctrl_val;
- char *cpsw_phy_envval;
- int cpsw_act_phy = 1;
-
- /* SB-SOM-AM57x primary Eth (P21) is routed to RGMII1 */
- ret = cl_som_am57x_handle_mac_address("ethaddr",
- CL_SOM_AM57X_RGMII_PORT1);
-
- if (ret)
- return -1;
-
- /* Select RGMII for GMII1_SEL */
- ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
- ctrl_val |= 0x22;
- writel(ctrl_val, (*ctrl)->control_core_control_io1);
- mdelay(10);
-
- gpio_request(CL_SOM_AM57X_GPIO_PHY1_RST, "phy1_rst");
- gpio_direction_output(CL_SOM_AM57X_GPIO_PHY1_RST, 0);
- mdelay(20);
-
- gpio_set_value(CL_SOM_AM57X_GPIO_PHY1_RST, 1);
- mdelay(20);
-
- cpsw_phy_envval = env_get("cpsw_phy");
- if (cpsw_phy_envval != NULL)
- cpsw_act_phy = simple_strtoul(cpsw_phy_envval, NULL, 0);
-
- cl_som_am57_cpsw_data.active_slave = cpsw_act_phy;
-
- ret = cpsw_register(&cl_som_am57_cpsw_data);
- if (ret < 0)
- printf("Error %d registering CPSW switch\n", ret);
-
- /* Set RGMII clock delay */
- cl_som_am57x_rgmii_clk_delay();
-
- return ret;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Pinmux configuration for CompuLab CL-SOM-AM57x board
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- */
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mux_dra7xx.h>
-
-/* Serial console */
-static const struct pad_conf_entry cl_som_am57x_padconf_console[] = {
- {UART3_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_RXD */
- {UART3_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_TXD */
-};
-
-/* PMIC I2C */
-static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = {
- {MCASP1_ACLKR, (M10 | PIN_INPUT)}, /* MCASP1_ACLKR.I2C4_SDA */
- {MCASP1_FSR, (M10 | PIN_INPUT)}, /* MCASP1_FSR.I2C4_SCL */
-};
-
-/* Green GPIO led */
-static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = {
- {GPMC_A15, (M14 | PIN_OUTPUT_PULLDOWN)}, /* GPMC_A15.GPIO2_5 */
-};
-
-/* MMC/SD Card */
-static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = {
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CLK */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CMD */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT3 */
- {MMC1_SDCD, (M14 | PIN_INPUT) }, /* MMC1_SDCD */
- {MMC1_SDWP, (M14 | PIN_INPUT) }, /* MMC1_SDWP */
-};
-
-/* WiFi - must be in the safe mode on boot */
-static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = {
- {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_CTSN */
- {UART1_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_RTSN */
- {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RXD */
- {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_TXD */
- {UART2_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_CTSN */
- {UART2_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RTSN */
-};
-
-/* QSPI */
-static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = {
- {GPMC_A13, (M1 | PIN_INPUT) }, /* GPMC_A13.QSPI1_RTCLK */
- {GPMC_A18, (M1 | PIN_INPUT) }, /* GPMC_A18.QSPI1_SCLK */
- {GPMC_A16, (M1 | PIN_INPUT) }, /* GPMC_A16.QSPI1_D0 */
- {GPMC_A17, (M1 | PIN_INPUT) }, /* GPMC_A17.QSPI1_D1 */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */
-};
-
-/* GPIO Expander I2C */
-static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = {
- {MCASP1_AXR0, (M10 | PIN_INPUT)}, /* MCASP1_AXR0.I2C5_SDA */
- {MCASP1_AXR1, (M10 | PIN_INPUT)}, /* MCASP1_AXR1.I2C5_SCL */
-};
-
-/* eMMC internal storage */
-static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = {
- {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */
- {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */
- {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */
- {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */
- {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */
- {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A24.MMC2_DAT0 */
- {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A25.MMC2_DAT1 */
- {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A26.MMC2_DAT2 */
- {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A27.MMC2_DAT3 */
- {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS1.MMC2_CMD */
-};
-
-/* usb1_drvvbus */
-static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = {
- /* USB1_DRVVBUS.USB1_DRVVBUS */
- {USB1_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL) },
-};
-
-/* Ethernet */
-static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = {
- /* MDIO bus */
- {VIN2A_D10, (M3 | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK */
- {VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* VIN2A_D11.MDIO_D */
- /* EMAC Slave 1 at addr 0x1 - Default interface */
- {VIN2A_D12, (M3 | PIN_OUTPUT) }, /* VIN2A_D12.RGMII1_TXC */
- {VIN2A_D13, (M3 | PIN_OUTPUT) }, /* VIN2A_D13.RGMII1_TXCTL */
- {VIN2A_D14, (M3 | PIN_OUTPUT) }, /* VIN2A_D14.RGMII1_TXD3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT) }, /* VIN2A_D15.RGMII1_TXD2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT) }, /* VIN2A_D16.RGMII1_TXD1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT) }, /* VIN2A_D17.RGMII1_TXD0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D20.RGMII1_RXD3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D21.RGMII1_RXD2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D22.RGMII1_RXD1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D23.RGMII1_RXD0 */
- /* Eth PHY1 reset GPIOs*/
- {VIN2A_CLK0, (M14 | PIN_OUTPUT_PULLDOWN)}, /* VIN2A_CLK0.GPIO3_28 */
-};
-
-#define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \
- mux_array, ARRAY_SIZE(mux_array))
-
-void set_muxconf_regs(void)
-{
- SET_MUX(cl_som_am57x_padconf_console);
- SET_MUX(cl_som_am57x_padconf_pmic);
- SET_MUX(cl_som_am57x_padconf_green_led);
- SET_MUX(cl_som_am57x_padconf_sd_card);
- SET_MUX(cl_som_am57x_padconf_wifi);
- SET_MUX(cl_som_am57x_padconf_qspi);
- SET_MUX(cl_som_am57x_padconf_i2c_gpio);
- SET_MUX(cl_som_am57x_padconf_emmc);
- SET_MUX(cl_som_am57x_padconf_usb);
- SET_MUX(cl_som_am57x_padconf_ethernet);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPL data and initialization for CompuLab CL-SOM-AM57x board
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
- */
-
-#include <asm/emif.h>
-#include <asm/omap_common.h>
-#include <asm/arch/sys_proto.h>
-
-static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = {
- .dmm_lisa_map_3 = 0x80740300,
- .is_ma_present = 0x1
-};
-
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
-{
- /* Disable SDRAM controller EMIF2 for single core SOC */
- *dmm_lisa_regs = &cl_som_am57x_lisa_regs;
- if (omap_revision() == DRA722_ES1_0) {
- ((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 =
- 0x80640100;
- }
-}
-
-static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61852332,
- .sdram_config = 0x61852332,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x000040f1,
- .ref_ctrl_final = 0x00001040,
- .sdram_tim1 = 0xeeef36f3,
- .sdram_tim2 = 0x348f7fda,
- .sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x1007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0034400b,
- .emif_ddr_phy_ctlr_1 = 0x0e34400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
- .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
- .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
- .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-/* Ext phy ctrl regs 1-35 */
-static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = {
- 0x10040100,
- 0x00740074,
- 0x00780078,
- 0x007c007c,
- 0x007b007b,
- 0x00800080,
- 0x00360036,
- 0x00340034,
- 0x00360036,
- 0x00350035,
- 0x00350035,
-
- 0x01ff01ff,
- 0x01ff01ff,
- 0x01ff01ff,
- 0x01ff01ff,
- 0x01ff01ff,
-
- 0x00430043,
- 0x003e003e,
- 0x004a004a,
- 0x00470047,
- 0x00400040,
-
- 0x00000000,
- 0x00600020,
- 0x40011080,
- 0x08102040,
-
- 0x00400040,
- 0x00400040,
- 0x00400040,
- 0x00400040,
- 0x00400040,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0
-};
-
-static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61852332,
- .sdram_config = 0x61852332,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x000040f1,
- .ref_ctrl_final = 0x00001040,
- .sdram_tim1 = 0xeeef36f3,
- .sdram_tim2 = 0x348f7fda,
- .sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x1007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0034400b,
- .emif_ddr_phy_ctlr_1 = 0x0e34400b,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
- .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
- .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
- .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = {
- 0x10040100,
- 0x00820082,
- 0x008b008b,
- 0x00800080,
- 0x007e007e,
- 0x00800080,
- 0x00370037,
- 0x00390039,
- 0x00360036,
- 0x00370037,
- 0x00350035,
- 0x01ff01ff,
- 0x01ff01ff,
- 0x01ff01ff,
- 0x01ff01ff,
- 0x01ff01ff,
- 0x00540054,
- 0x00540054,
- 0x004e004e,
- 0x004c004c,
- 0x00400040,
-
- 0x00000000,
- 0x00600020,
- 0x40011080,
- 0x08102040,
-
- 0x00400040,
- 0x00400040,
- 0x00400040,
- 0x00400040,
- 0x00400040,
- 0x0,
- 0x0,
- 0x0,
- 0x0,
- 0x0
-};
-
-static struct vcores_data cl_som_am57x_volts = {
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12,
- .mpu.pmic = &tps659038,
-
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45,
- .eve.pmic = &tps659038,
-
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
- .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
- .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6,
- .gpu.pmic = &tps659038,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7,
- .core.pmic = &tps659038,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS8,
- .iva.pmic = &tps659038,
-};
-
-void hw_data_init(void)
-{
- *prcm = &dra7xx_prcm;
- *dplls_data = &dra7xx_dplls;
- *omap_vcores = &cl_som_am57x_volts;
- *ctrl = &dra7xx_ctrl;
-}
-
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
-{
- switch (emif_nr) {
- case 1:
- *regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs;
- break;
- case 2:
- *regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs;
- break;
- }
-}
-
-void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
-{
- switch (emif_nr) {
- case 1:
- *regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs;
- *size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs);
- break;
- case 2:
- *regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs;
- *size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs);
- break;
- }
-}
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += board.o
obj-$(CONFIG_SUN7I_GMAC) += gmac.o
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SUNXI_AHCI) += ahci.o
-endif
obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o
+++ /dev/null
-#include <common.h>
-#include <ahci.h>
-#include <dm.h>
-#include <scsi.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-
-#define AHCI_PHYCS0R 0x00c0
-#define AHCI_PHYCS1R 0x00c4
-#define AHCI_PHYCS2R 0x00c8
-#define AHCI_RWCR 0x00fc
-
-/* This magic PHY initialisation was taken from the Allwinner releases
- * and Linux driver, but is completely undocumented.
- */
-static int sunxi_ahci_phy_init(u8 *reg_base)
-{
- u32 reg_val;
- int timeout;
-
- writel(0, reg_base + AHCI_RWCR);
- mdelay(5);
-
- setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
- clrsetbits_le32(reg_base + AHCI_PHYCS0R,
- (0x7 << 24),
- (0x5 << 24) | (0x1 << 23) | (0x1 << 18));
- clrsetbits_le32(reg_base + AHCI_PHYCS1R,
- (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
- (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
- setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
- clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
- clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
- clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
- mdelay(5);
-
- setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
-
- timeout = 250; /* Power up takes approx 50 us */
- for (;;) {
- reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
- if (reg_val == (0x2 << 28))
- break;
- if (--timeout == 0) {
- printf("AHCI PHY power up failed.\n");
- return -EIO;
- }
- udelay(1);
- };
-
- setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
-
- timeout = 100; /* Calibration takes approx 10 us */
- for (;;) {
- reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
- if (reg_val == 0x0)
- break;
- if (--timeout == 0) {
- printf("AHCI PHY calibration failed.\n");
- return -EIO;
- }
- udelay(1);
- }
-
- mdelay(15);
-
- writel(0x7, reg_base + AHCI_RWCR);
-
- return 0;
-}
-
-#ifndef CONFIG_DM_SCSI
-void scsi_init(void)
-{
- if (sunxi_ahci_phy_init((u8 *)SUNXI_SATA_BASE) < 0)
- return;
-
- ahci_init((void __iomem *)SUNXI_SATA_BASE);
-}
-#else
-static int sunxi_sata_probe(struct udevice *dev)
-{
- ulong base;
- u8 *reg;
- int ret;
-
- base = dev_read_addr(dev);
- if (base == FDT_ADDR_T_NONE) {
- debug("%s: Failed to find address (err=%d\n)", __func__, ret);
- return -EINVAL;
- }
- reg = (u8 *)base;
- ret = sunxi_ahci_phy_init(reg);
- if (ret) {
- debug("%s: Failed to init phy (err=%d\n)", __func__, ret);
- return ret;
- }
- ret = ahci_probe_scsi(dev, base);
- if (ret) {
- debug("%s: Failed to probe (err=%d\n)", __func__, ret);
- return ret;
- }
-
- return 0;
-}
-
-static int sunxi_sata_bind(struct udevice *dev)
-{
- struct udevice *scsi_dev;
- int ret;
-
- ret = ahci_bind_scsi(dev, &scsi_dev);
- if (ret) {
- debug("%s: Failed to bind (err=%d\n)", __func__, ret);
- return ret;
- }
-
- return 0;
-}
-
-static const struct udevice_id sunxi_ahci_ids[] = {
- { .compatible = "allwinner,sun4i-a10-ahci" },
- { }
-};
-
-U_BOOT_DRIVER(ahci_sunxi_drv) = {
- .name = "ahci_sunxi",
- .id = UCLASS_AHCI,
- .of_match = sunxi_ahci_ids,
- .bind = sunxi_sata_bind,
- .probe = sunxi_sata_probe,
-};
-#endif
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- /* Set up clock gating */
-#ifdef CONFIG_SUNXI_GEN_SUN6I
- setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
-#else
- setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-#endif
-
/* Set MII clock */
#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
u32 src_ptr;
char *endp;
+ if (argc != cmdtp->maxargs)
+ return CMD_RET_FAILURE;
+
src_ptr = simple_strtoul(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
return CMD_RET_USAGE;
+
if (zynq_verify_image(src_ptr))
return CMD_RET_FAILURE;
u32 srcaddr, srclen, dstaddr, dstlen;
int status;
+ if (argc < 5 && argc > cmdtp->maxargs)
+ return CMD_RET_USAGE;
+
srcaddr = simple_strtoul(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
return CMD_RET_USAGE;
return CMD_RET_USAGE;
zynq_cmd = find_cmd_tbl(argv[1], zynq_commands,
ARRAY_SIZE(zynq_commands));
- if (!zynq_cmd || argc != zynq_cmd->maxargs)
+ if (!zynq_cmd)
return CMD_RET_USAGE;
ret = zynq_cmd->cmd(zynq_cmd, flag, argc, argv);
.id = 0x62,
.name = "29dr",
},
+ {
+ .id = 0x66,
+ .name = "39dr",
+ },
};
#endif
{}
};
-static u32 reset_reason(void)
+static int reset_reason(void)
{
- u32 ret;
- int i;
+ u32 reg;
+ int i, ret;
const char *reason = NULL;
- ret = readl(&crlapb_base->reset_reason);
+ ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
+ if (ret)
+ return -EINVAL;
puts("Reset reason:\t");
for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
- if (ret & reset_reasons[i].bit) {
+ if (reg & reset_reasons[i].bit) {
reason = reset_reasons[i].name;
printf("%s ", reset_reasons[i].name);
break;
env_set("reset_reason", reason);
- writel(~0, &crlapb_base->reset_reason);
+ ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
+ if (ret)
+ return -EINVAL;
return ret;
}
return CMD_RET_FAILURE;
}
- /* get fpga subimage data address and length */
- if (fit_image_get_data(fit_hdr, noffset, &fit_data,
- &data_size)) {
+ /* get fpga subimage/external data address and length */
+ if (fit_image_get_data_and_size(fit_hdr, noffset,
+ &fit_data, &data_size)) {
puts("Fpga subimage data not found\n");
return CMD_RET_FAILURE;
}
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_CL_SOM_AM57X=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_SPL_FS_EXT4 is not set
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_EEPROM_LAYOUT=y
-CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_SCSI_AHCI=y
-CONFIG_CMD_PCA953X=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=37
-CONFIG_LED_STATUS_STATE=2
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=48000000
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_MCS7830=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_NO_DDR=y
+# CONFIG_PSCI_RESET is not set
# CONFIG_CMD_ZYNQMP is not set
CONFIG_NR_DRAM_BANKS=1
+# CONFIG_EXPERT is not set
# CONFIG_IMAGE_FORMAT_LEGACY is not set
# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_USB_ETH_CDC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
-CONFIG_WDT=y
-CONFIG_WDT_CDNS=y
CONFIG_SPL_GZIP=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
drivers/spi/kirkwood_spi.c
drivers/spi/mxc_spi.c
drivers/spi/omap3_spi.c
- drivers/spi/ti_qspi.c
Status: In progress
Deadline: 2019.07
help
Enable this driver to support the SIL3114 SATA controllers.
+config SUNXI_AHCI
+ bool "Enable Allwinner SATA driver support"
+ depends on AHCI
+ default y if ARCH_SUNXI
+ help
+ Enable this driver to support the SATA controllers found in the
+ Allwinner A10, A20 and R40 SoCs.
+
config AHCI_MVEBU
bool "Marvell EBU AHCI SATA support"
depends on ARCH_MVEBU
obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_SANDBOX) += sata_sandbox.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
+obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
--- /dev/null
+#include <common.h>
+#include <ahci.h>
+#include <dm.h>
+#include <scsi.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define AHCI_PHYCS0R 0x00c0
+#define AHCI_PHYCS1R 0x00c4
+#define AHCI_PHYCS2R 0x00c8
+#define AHCI_RWCR 0x00fc
+
+/* This magic PHY initialisation was taken from the Allwinner releases
+ * and Linux driver, but is completely undocumented.
+ */
+static int sunxi_ahci_phy_init(u8 *reg_base)
+{
+ u32 reg_val;
+ int timeout;
+
+ writel(0, reg_base + AHCI_RWCR);
+ mdelay(5);
+
+ setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R,
+ (0x7 << 24),
+ (0x5 << 24) | (0x1 << 23) | (0x1 << 18));
+ clrsetbits_le32(reg_base + AHCI_PHYCS1R,
+ (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
+ (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
+ setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
+ clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
+ clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
+ mdelay(5);
+
+ setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+
+ timeout = 250; /* Power up takes approx 50 us */
+ for (;;) {
+ reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
+ if (reg_val == (0x2 << 28))
+ break;
+ if (--timeout == 0) {
+ printf("AHCI PHY power up failed.\n");
+ return -EIO;
+ }
+ udelay(1);
+ };
+
+ setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+
+ timeout = 100; /* Calibration takes approx 10 us */
+ for (;;) {
+ reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
+ if (reg_val == 0x0)
+ break;
+ if (--timeout == 0) {
+ printf("AHCI PHY calibration failed.\n");
+ return -EIO;
+ }
+ udelay(1);
+ }
+
+ mdelay(15);
+
+ writel(0x7, reg_base + AHCI_RWCR);
+
+ return 0;
+}
+
+static int sunxi_sata_probe(struct udevice *dev)
+{
+ ulong base;
+ u8 *reg;
+ int ret;
+
+ base = dev_read_addr(dev);
+ if (base == FDT_ADDR_T_NONE) {
+ debug("%s: Failed to find address (err=%d\n)", __func__, ret);
+ return -EINVAL;
+ }
+ reg = (u8 *)base;
+ ret = sunxi_ahci_phy_init(reg);
+ if (ret) {
+ debug("%s: Failed to init phy (err=%d\n)", __func__, ret);
+ return ret;
+ }
+ ret = ahci_probe_scsi(dev, base);
+ if (ret) {
+ debug("%s: Failed to probe (err=%d\n)", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sunxi_sata_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+ int ret;
+
+ ret = ahci_bind_scsi(dev, &scsi_dev);
+ if (ret) {
+ debug("%s: Failed to bind (err=%d\n)", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id sunxi_ahci_ids[] = {
+ { .compatible = "allwinner,sun4i-a10-ahci" },
+ { .compatible = "allwinner,sun8i-r40-ahci" },
+ { }
+};
+
+U_BOOT_DRIVER(ahci_sunxi_drv) = {
+ .name = "ahci_sunxi",
+ .id = UCLASS_AHCI,
+ .of_match = sunxi_ahci_ids,
+ .bind = sunxi_sata_bind,
+ .probe = sunxi_sata_probe,
+};
case lqspi_clk ... pcap_clk:
case sdio0_clk ... spi1_clk:
return zynq_clk_get_peripheral_rate(priv, id, 0);
+ case i2c0_aper_clk ... i2c1_aper_clk:
+ return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
default:
return -ENXIO;
}
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
- [RST_BUS_GMAC] = RESET(0x2c0, BIT(17)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),
[RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)),
[RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)),
+ [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
+
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
if (bstype != BIT_PARTIAL)
zynq_slcr_devcfg_enable();
+ puts("INFO:post config was not run, please run manually if needed\n");
+
return FPGA_SUCCESS;
}
loff_t blocksize, actread;
loff_t pos = 0;
int fstype;
- char *interface, *dev_part, *filename;
+ char *interface, *dev_part;
+ const char *filename;
blocksize = fsinfo->blocksize;
interface = fsinfo->interface;
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <fdt_support.h>
#include <linux/err.h>
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
+#include <reset.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#ifdef CONFIG_DM_GPIO
#include <asm-generic/gpio.h>
phys_addr_t sysctl_reg;
struct phy_device *phydev;
struct mii_dev *bus;
+ struct clk tx_clk;
+ struct reset_ctl tx_rst;
#ifdef CONFIG_DM_GPIO
struct gpio_desc reset_gpio;
#endif
int ret;
u32 reg;
- reg = readl(priv->sysctl_reg + 0x30);
+ if (priv->variant == R40_GMAC) {
+ /* Select RGMII for R40 */
+ reg = readl(priv->sysctl_reg + 0x164);
+ reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+ CCM_GMAC_CTRL_GPIT_RGMII |
+ CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
- if (priv->variant == R40_GMAC)
+ writel(reg, priv->sysctl_reg + 0x164);
return 0;
+ }
+
+ reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == H3_EMAC) {
ret = sun8i_emac_set_syscon_ephy(priv, ®);
return _sun8i_write_hwaddr(priv, pdata->enetaddr);
}
-static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
+static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int ret;
+
+ ret = clk_enable(&priv->tx_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable TX clock\n");
+ return ret;
+ }
+
+ if (reset_valid(&priv->tx_rst)) {
+ ret = reset_deassert(&priv->tx_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert TX reset\n");
+ goto err_tx_clk;
+ }
+ }
if (priv->variant == H3_EMAC) {
/* Only H3/H5 have clock controls for internal EPHY */
}
}
- if (priv->variant == R40_GMAC) {
- /* Set clock gating for emac */
- setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
-
- /* De-assert EMAC */
- setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
+ return 0;
- /* Select RGMII for R40 */
- setbits_le32(&ccm->gmac_clk_cfg,
- CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
- CCM_GMAC_CTRL_GPIT_RGMII);
- setbits_le32(&ccm->gmac_clk_cfg,
- CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
- } else {
- /* Set clock gating for emac */
- setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
-
- /* De-assert EMAC */
- setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
- }
+err_tx_clk:
+ clk_disable(&priv->tx_clk);
+ return ret;
}
#if defined(CONFIG_DM_GPIO)
struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
+ int ret;
priv->mac_reg = (void *)pdata->iobase;
- sun8i_emac_board_setup(priv);
+ ret = sun8i_emac_board_setup(priv);
+ if (ret)
+ return ret;
+
sun8i_emac_set_syscon(sun8i_pdata, priv);
sun8i_mdio_init(dev->name, dev);
int offset = 0;
#ifdef CONFIG_DM_GPIO
int reset_flags = GPIOD_IS_OUT;
- int ret = 0;
#endif
+ int ret;
pdata->iobase = devfdt_get_addr(dev);
if (pdata->iobase == FDT_ADDR_T_NONE) {
return -EINVAL;
}
- if (priv->variant != R40_GMAC) {
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
- if (offset < 0) {
- debug("%s: cannot find syscon node\n", __func__);
- return -EINVAL;
- }
- reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
- if (!reg) {
- debug("%s: cannot find reg property in syscon node\n",
- __func__);
- return -EINVAL;
- }
- priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
- offset, reg);
- if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
- debug("%s: Cannot find syscon base address\n",
- __func__);
- return -EINVAL;
- }
+ ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
+ if (ret) {
+ dev_err(dev, "failed to get TX clock\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "failed to get TX reset\n");
+ return ret;
+ }
+
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+ if (offset < 0) {
+ debug("%s: cannot find syscon node\n", __func__);
+ return -EINVAL;
+ }
+
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+ if (!reg) {
+ debug("%s: cannot find reg property in syscon node\n",
+ __func__);
+ return -EINVAL;
+ }
+ priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+ offset, reg);
+ if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find syscon base address\n", __func__);
+ return -EINVAL;
}
pdata->phy_interface = -1;
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <linux/err.h>
#include <malloc.h>
struct emac_eth_dev {
struct emac_regs *regs;
+ struct clk clk;
struct mii_dev *bus;
struct phy_device *phydev;
int link_printed;
return 0;
}
-static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
+static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_sramc_regs *sram =
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
struct emac_regs *regs = priv->regs;
- int pin;
+ int pin, ret;
/* Map SRAM to EMAC */
setbits_le32(&sram->ctrl1, 0x5 << 2);
sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
/* Set up clock gating */
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+ ret = clk_enable(&priv->clk);
+ if (ret) {
+ dev_err(dev, "failed to enable emac clock\n");
+ return ret;
+ }
/* Set MII clock */
clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
+
+ return 0;
}
static int sunxi_emac_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct emac_eth_dev *priv = dev_get_priv(dev);
+ int ret;
priv->regs = (struct emac_regs *)pdata->iobase;
- sunxi_emac_board_setup(priv);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret) {
+ dev_err(dev, "failed to get emac clock\n");
+ return ret;
+ }
+
+ ret = sunxi_emac_board_setup(priv);
+ if (ret)
+ return ret;
return sunxi_emac_init_phy(priv, dev);
}
ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
}
-static int phy_detection(struct udevice *dev)
-{
- int i;
- u16 phyreg = 0;
- struct zynq_gem_priv *priv = dev->priv;
-
- if (priv->phyaddr != -1) {
- phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
- if ((phyreg != 0xFFFF) &&
- ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
- /* Found a valid PHY address */
- debug("Default phy address %d is valid\n",
- priv->phyaddr);
- return 0;
- } else {
- debug("PHY address is not setup correctly %d\n",
- priv->phyaddr);
- priv->phyaddr = -1;
- }
- }
-
- debug("detecting phy address\n");
- if (priv->phyaddr == -1) {
- /* detect the PHY address */
- for (i = 31; i >= 0; i--) {
- phyread(priv, i, PHY_DETECT_REG, &phyreg);
- if ((phyreg != 0xFFFF) &&
- ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
- /* Found a valid PHY address */
- priv->phyaddr = i;
- debug("Found valid phy address, %d\n", i);
- return 0;
- }
- }
- }
- printf("PHY is not detected\n");
- return -1;
-}
-
static int zynq_gem_setup_mac(struct udevice *dev)
{
u32 i, macaddrlow, macaddrhigh;
/* Enable only MDIO bus */
writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
- if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
- (priv->interface != PHY_INTERFACE_MODE_GMII)) {
- ret = phy_detection(dev);
- if (ret) {
- printf("GEM PHY init failed\n");
- return ret;
- }
- }
-
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
if (!priv->phydev)
return -ENODEV;
- priv->phydev->supported &= supported | ADVERTISED_Pause |
- ADVERTISED_Asym_Pause;
if (priv->max_speed) {
ret = phy_set_supported(priv->phydev, priv->max_speed);
if (ret)
return ret;
}
+ priv->phydev->supported &= supported | ADVERTISED_Pause |
+ ADVERTISED_Asym_Pause;
+
priv->phydev->advertising = priv->phydev->supported;
priv->phydev->node = priv->phy_of_node;
be used to access SPI chips on platforms embedding this
NVIDIA Tegra210 IP core.
+config TI_QSPI
+ bool "TI QSPI driver"
+ imply TI_EDMA3
+ help
+ Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
+ This driver support spi flash single, quad and memory reads.
+
config XILINX_SPI
bool "Xilinx SPI driver"
help
Enable the Renesas Quad SPI controller driver. This driver can be
used on Renesas SoCs.
-config TI_QSPI
- bool "TI QSPI driver"
- help
- Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
- This driver support spi flash single, quad and memory reads.
-
config KIRKWOOD_SPI
bool "Marvell Kirkwood SPI Driver"
help
obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o
+obj-$(CONFIG_TI_QSPI) += ti_qspi.o
else
obj-y += spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
-obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
+#include <spi-mem.h>
#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#define QSPI_INVAL (4 << 16)
#define QSPI_RD_QUAD (7 << 16)
/* device control */
-#define QSPI_DD(m, n) (m << (3 + n*8))
#define QSPI_CKPHA(n) (1 << (2 + n*8))
#define QSPI_CSPOL(n) (1 << (1 + n*8))
#define QSPI_CKPOL(n) (1 << (n*8))
#define MM_SWITCH 0x01
#define MEM_CS(cs) ((cs + 1) << 8)
#define MEM_CS_UNSELECT 0xfffff8ff
-#define MMAP_START_ADDR_DRA 0x5c000000
-#define MMAP_START_ADDR_AM43x 0x30000000
-#define CORE_CTRL_IO 0x4a002558
-
-#define QSPI_CMD_READ (0x3 << 0)
-#define QSPI_CMD_READ_DUAL (0x6b << 0)
-#define QSPI_CMD_READ_QUAD (0x6c << 0)
-#define QSPI_CMD_READ_FAST (0x0b << 0)
-#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
-#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
-#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
+
#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
-#define QSPI_CMD_WRITE (0x12 << 16)
-#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
+#define QSPI_SETUP0_ADDR_SHIFT (8)
+#define QSPI_SETUP0_DBITS_SHIFT (10)
/* ti qspi register set */
struct ti_qspi_regs {
/* ti qspi priv */
struct ti_qspi_priv {
-#ifndef CONFIG_DM_SPI
- struct spi_slave slave;
-#else
void *memory_map;
+ size_t mmap_size;
uint max_hz;
u32 num_cs;
-#endif
struct ti_qspi_regs *base;
void *ctrl_mod_mmap;
ulong fclk;
u32 dc;
};
-static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
+static int ti_qspi_set_speed(struct udevice *bus, uint hz)
{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
uint clk_div;
if (!hz)
&priv->base->clk_ctrl);
/* enable SCLK and program the clk divider */
writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
+
+ return 0;
}
static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
readl(&priv->base->cmd);
}
-static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
-{
- priv->dc = 0;
- if (mode & SPI_CPHA)
- priv->dc |= QSPI_CKPHA(0);
- if (mode & SPI_CPOL)
- priv->dc |= QSPI_CKPOL(0);
- if (mode & SPI_CS_HIGH)
- priv->dc |= QSPI_CSPOL(0);
-
- return 0;
-}
-
-static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
-{
- writel(priv->dc, &priv->base->dc);
- writel(0, &priv->base->cmd);
- writel(0, &priv->base->data);
-
- priv->dc <<= cs * 8;
- writel(priv->dc, &priv->base->dc);
-
- return 0;
-}
-
-static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
-{
- writel(0, &priv->base->dc);
- writel(0, &priv->base->cmd);
- writel(0, &priv->base->data);
-}
-
static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
{
u32 val;
writel(val, ctrl_mod_mmap);
}
-static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags,
- u32 cs)
+static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
uint words = bitlen >> 3; /* fixed 8-bit word length */
const uchar *txp = dout;
uchar *rxp = din;
uint status;
int timeout;
+ unsigned int cs = slave->cs;
- /* Setup mmap flags */
- if (flags & SPI_XFER_MMAP) {
- writel(MM_SWITCH, &priv->base->memswitch);
- if (priv->ctrl_mod_mmap)
- ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
- return 0;
- } else if (flags & SPI_XFER_MMAP_END) {
- writel(~MM_SWITCH, &priv->base->memswitch);
- if (priv->ctrl_mod_mmap)
- ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
- return 0;
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
}
if (bitlen == 0)
}
/* TODO: control from sf layer to here through dm-spi */
-#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
-void spi_flash_copy_mmap(void *data, void *offset, size_t len)
+static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
{
+#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
unsigned int addr = (unsigned int) (data);
unsigned int edma_slot_num = 1;
/* disable edma3 clocks */
disable_edma3_clocks();
-
- *((unsigned int *)offset) += len;
-}
-#endif
-
-#ifndef CONFIG_DM_SPI
-
-static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
-{
- return container_of(slave, struct ti_qspi_priv, slave);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* CS handled in xfer */
- return;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
- ti_qspi_cs_deactivate(priv);
-}
-
-void spi_init(void)
-{
- /* nothing to do */
-}
-
-static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
-{
- u32 memval = 0;
-
-#ifdef CONFIG_QSPI_QUAD_SUPPORT
- struct spi_slave *slave = &priv->slave;
- memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_8_BITS |
- QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS);
- slave->mode |= SPI_RX_QUAD;
#else
- memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
- QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS;
+ memcpy_fromio(data, offset, len);
#endif
- writel(memval, &priv->base->setup0);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct ti_qspi_priv *priv;
-
-#ifdef CONFIG_AM43XX
- gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
- gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
-#endif
-
- priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
- if (!priv) {
- printf("SPI_error: Fail to allocate ti_qspi_priv\n");
- return NULL;
- }
-
- priv->base = (struct ti_qspi_regs *)QSPI_BASE;
- priv->mode = mode;
-#if defined(CONFIG_DRA7XX)
- priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
- priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
- priv->fclk = QSPI_DRA7XX_FCLK;
-#else
- priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
- priv->fclk = QSPI_FCLK;
-#endif
-
- ti_spi_set_speed(priv, max_hz);
-
-#ifdef CONFIG_TI_SPI_MMAP
- ti_spi_setup_spi_register(priv);
-#endif
-
- return &priv->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
- free(priv);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
- __ti_qspi_set_mode(priv, priv->mode);
- return __ti_qspi_claim_bus(priv, priv->slave.cs);
-}
-void spi_release_bus(struct spi_slave *slave)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
- __ti_qspi_release_bus(priv);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
- debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
- priv->slave.bus, priv->slave.cs, bitlen, flags);
- return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
+ *((unsigned int *)offset) += len;
}
-#else /* CONFIG_DM_SPI */
-
-static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
- struct spi_slave *slave,
- bool enable)
+static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
+ u8 data_nbits, u8 addr_width,
+ u8 dummy_bytes)
{
- u32 memval;
- u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
-
- if (!enable) {
- writel(0, &priv->base->setup0);
- return;
- }
-
- memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
+ u32 memval = opcode;
- switch (mode) {
- case SPI_RX_QUAD:
- memval |= QSPI_CMD_READ_QUAD;
- memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ switch (data_nbits) {
+ case 4:
memval |= QSPI_SETUP0_READ_QUAD;
- slave->mode |= SPI_RX_QUAD;
break;
- case SPI_RX_DUAL:
- memval |= QSPI_CMD_READ_DUAL;
- memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ case 2:
memval |= QSPI_SETUP0_READ_DUAL;
break;
default:
- memval |= QSPI_CMD_READ;
- memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
memval |= QSPI_SETUP0_READ_NORMAL;
break;
}
+ memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
+ dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
+
writel(memval, &priv->base->setup0);
}
-
-static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
+static int ti_qspi_set_mode(struct udevice *bus, uint mode)
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
- ti_spi_set_speed(priv, max_hz);
+ priv->dc = 0;
+ if (mode & SPI_CPHA)
+ priv->dc |= QSPI_CKPHA(0);
+ if (mode & SPI_CPOL)
+ priv->dc |= QSPI_CKPOL(0);
+ if (mode & SPI_CS_HIGH)
+ priv->dc |= QSPI_CSPOL(0);
return 0;
}
-static int ti_qspi_set_mode(struct udevice *bus, uint mode)
+static int ti_qspi_exec_mem_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
{
- struct ti_qspi_priv *priv = dev_get_priv(bus);
- return __ti_qspi_set_mode(priv, mode);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = slave->dev->parent;
+ priv = dev_get_priv(bus);
+ u32 from = 0;
+ int ret = 0;
+
+ /* Only optimize read path. */
+ if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
+ !op->addr.nbytes || op->addr.nbytes > 4)
+ return -ENOTSUPP;
+
+ /* Address exceeds MMIO window size, fall back to regular mode. */
+ from = op->addr.val;
+ if (from + op->data.nbytes > priv->mmap_size)
+ return -ENOTSUPP;
+
+ ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth,
+ op->addr.nbytes, op->dummy.nbytes);
+
+ ti_qspi_copy_mmap((void *)op->data.buf.in,
+ (void *)priv->memory_map + from, op->data.nbytes);
+
+ return ret;
}
static int ti_qspi_claim_bus(struct udevice *dev)
{
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
- struct spi_slave *slave = dev_get_parent_priv(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
return -EINVAL;
}
- __ti_qspi_setup_memorymap(priv, slave, true);
-
- return __ti_qspi_claim_bus(priv, slave_plat->cs);
-}
-
-static int ti_qspi_release_bus(struct udevice *dev)
-{
- struct spi_slave *slave = dev_get_parent_priv(dev);
- struct ti_qspi_priv *priv;
- struct udevice *bus;
+ writel(MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
+ slave_plat->cs, true);
- bus = dev->parent;
- priv = dev_get_priv(bus);
+ writel(priv->dc, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
- __ti_qspi_setup_memorymap(priv, slave, false);
- __ti_qspi_release_bus(priv);
+ priv->dc <<= slave_plat->cs * 8;
+ writel(priv->dc, &priv->base->dc);
return 0;
}
-static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int ti_qspi_release_bus(struct udevice *dev)
{
- struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
struct ti_qspi_priv *priv;
struct udevice *bus;
bus = dev->parent;
priv = dev_get_priv(bus);
- if (slave->cs > priv->num_cs) {
- debug("invalid qspi chip select\n");
- return -EINVAL;
- }
+ writel(~MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
+ slave_plat->cs, false);
- return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
+ writel(0, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
+ writel(0, &priv->base->setup0);
+
+ return 0;
}
static int ti_qspi_probe(struct udevice *bus)
struct ti_qspi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
+ fdt_addr_t mmap_addr;
+ fdt_addr_t mmap_size;
priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
priv->base = map_physmem(devfdt_get_addr(bus),
sizeof(struct ti_qspi_regs), MAP_NOCACHE);
- priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
- MAP_NOCACHE);
+ mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
+ priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
+ priv->mmap_size = mmap_size;
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
if (priv->max_hz < 0) {
return 0;
}
-static int ti_qspi_child_pre_probe(struct udevice *dev)
-{
- struct spi_slave *slave = dev_get_parent_priv(dev);
- struct udevice *bus = dev_get_parent(dev);
- struct ti_qspi_priv *priv = dev_get_priv(bus);
-
- slave->memory_map = priv->memory_map;
- return 0;
-}
+static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
+ .exec_op = ti_qspi_exec_mem_op,
+};
static const struct dm_spi_ops ti_qspi_ops = {
.claim_bus = ti_qspi_claim_bus,
.xfer = ti_qspi_xfer,
.set_speed = ti_qspi_set_speed,
.set_mode = ti_qspi_set_mode,
+ .mem_ops = &ti_qspi_mem_ops,
};
static const struct udevice_id ti_qspi_ids[] = {
.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
.probe = ti_qspi_probe,
- .child_pre_probe = ti_qspi_child_pre_probe,
};
-#endif /* CONFIG_DM_SPI */
zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
- } else if (reqhz < GQSPI_FREQ_100MHZ) {
+ } else if (reqhz <= GQSPI_FREQ_100MHZ) {
zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
| (GQSPI_DATA_DLY_ADJ_VALUE <<
GQSPI_DATA_DLY_ADJ_SHIFT));
- } else if (reqhz < GQSPI_FREQ_150MHZ) {
+ } else if (reqhz <= GQSPI_FREQ_150MHZ) {
lpbkdlyadj = readl(®s->lpbkdly);
lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
GQSPI_LPBK_DLY_ADJ_DLY_0);
#define CONFIG_ENV_OFFSET_REDUND 0x120000
#endif
-/* SPI */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_QSPI_SEL_GPIO 48
-#define CONFIG_QSPI_QUAD_SUPPORT
-#define CONFIG_TI_EDMA3
-
#ifndef CONFIG_SPL_BUILD
#include <environment/ti/dfu.h>
#include <environment/ti/mmc.h>
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */
-#define CONFIG_TI_EDMA3
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
-/* SPI */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_QSPI_QUAD_SUPPORT
-
#endif /* __CONFIG_AM57XX_EVM_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration settings for CompuLab CL-SOM-AM57x board
- *
- * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
- *
- * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
- */
-
-#ifndef __CONFIG_CL_SOM_AM57X_H
-#define __CONFIG_CL_SOM_AM57X_H
-
-#define CONSOLEDEV "ttyO2"
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
-
-#define CONFIG_SYS_OMAP_ABE_SYSCK
-
-#define PARTS_DEFAULT
-
-#include <configs/ti_omap5_common.h>
-
-/* misc */
-#define CONFIG_REVISION_TAG
-
-/* PMIC I2C bus number */
-#define CONFIG_SYS_SPD_BUS_NUM 3
-
-/* SPI Flash support */
-#define CONFIG_TI_SPI_MMAP
-
-/* SPI SPL defines */
-/* Offsets: 0K - SPL1, 64K - SPL2, 128K - SPL3, 192K - SPL4, 256K - U-Boot */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
-#define CONFIG_SPL_SPI_SUPPORT
-
-/* SD/MMC RAW/FS boot */
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-
-/* Environment */
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB env size */
-
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_OFFSET (768 * 1024)
-
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS 3
-
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_EEPROM_SIZE 256
-
-#ifndef CONFIG_SPL_BUILD
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-/* PCA9555 GPIO expander support */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
-
-#endif /* !CONFIG_SPL_BUILD */
-
-/* USB xHCI HOST */
-#define CONFIG_USB_XHCI_OMAP
-
-#define CONFIG_OMAP_USB3PHY1_HOST
-
-/* USB Networking options */
-
-/* CPSW Ethernet */
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_PHY_ATHEROS
-#define CONFIG_SYS_RX_ETH_BUFFER 64
-#define PHY_ANEG_TIMEOUT 8000
-
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* Default environment */
-#undef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
- "autoload=no\0" \
- "baudrate=115200\0" \
- "console=ttyO2,115200n8\0" \
- "bootdelay=3\0" \
- "fdtfile=am57xx-sbc-am57x.dtb\0" \
- "kernel=zImage-cl-som-am57x\0" \
- "bootscr=bootscr.img\0" \
- "displaytype=hdmi\0" \
- "bootkernel=bootz ${loadaddr} - ${fdtaddr}\0" \
- "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
- "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
- "emmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
- "emmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
- "load_mmc=mmc dev ${mmcdev} && mmc rescan && " \
- "run mmcloadkernel && run mmcloadfdt\0" \
- "mmcroot=/dev/mmcblk1p2\0" \
- "mmcrootfstype=ext4 rw rootwait\0" \
- "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "mmcbootscript=setenv mmcdev 0; mmc dev ${mmcdev} && mmc rescan && " \
- "load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \
- "echo Running bootscript from MMC/SD Card ... && " \
- "source ${loadaddr}\0" \
- "mmcboot=setenv mmcdev 0 && run load_mmc && " \
- "run mmcargs && echo Booting from MMC/SD Card ... && " \
- "run bootkernel\0" \
- "emmcroot=/dev/mmcblk0p2\0" \
- "emmcrootfstype=ext4 rw rootwait\0" \
- "emmcargs=setenv bootargs console=${console} " \
- "root=${emmcroot} " \
- "rootfstype=${emmcrootfstype}\0" \
- "emmcbootscript=setenv mmcdev 1; mmc dev ${mmcdev} && mmc rescan && " \
- "load mmc ${mmcdev} ${loadaddr} ${bootscr} && " \
- "echo Running bootscript from eMMC ... && " \
- "source ${loadaddr}\0" \
- "emmcboot=setenv mmcdev 1 && run load_mmc && " \
- "run emmcargs && echo Booting from eMMC ... && " \
- "run bootkernel\0" \
- "sataroot=/dev/sda2\0" \
- "satarootfstype=ext4 rw rootwait\0" \
- "load_sata=load scsi 0 ${loadaddr} ${kernel} && " \
- "load scsi 0 ${fdtaddr} ${fdtfile}\0" \
- "sataargs=setenv bootargs console=${console} " \
- "root=${sataroot} " \
- "rootfstype=${satarootfstype}\0" \
- "satabootscript=load scsi 0 ${loadaddr} ${bootscr} && " \
- "echo Running bootscript from SATA ... && " \
- "source ${loadaddr}\0" \
- "sataboot=run load_sata && run sataargs && " \
- "echo Booting from SATA ... && " \
- "run bootkernel\0"
-
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "run mmcbootscript || run mmcboot || " \
- "run satabootscript || run sataboot || " \
- "run emmcbootscript || run emmcboot"
-
-
-#endif /* __CONFIG_CL_SOM_AM57X_H */
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_AM437X_USB2PHY2_HOST
-/* SPI Flash support */
-#define CONFIG_TI_SPI_MMAP
-
/* Power */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_PHY_TI
-/* SPI */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_QSPI_QUAD_SUPPORT
-
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x040000 : QSPI.SPL (256KiB)
#endif
/* SPI SPL */
-#define CONFIG_TI_EDMA3
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#define CONFIG_SUPPORT_EMMC_BOOT
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
#ifdef CONFIG_AHCI
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SUNXI_AHCI
#define CONFIG_SYS_64BIT_LBA
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#endif
#define CONFIG_SETUP_MEMORY_TAGS
# define PHY_ANEG_TIMEOUT 20000
#endif
-/* EEPROM */
-#ifdef CONFIG_ZYNQMP_EEPROM
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-# define CONFIG_SYS_EEPROM_SIZE (64 * 1024)
-#endif
-
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
#define CONFIG_CLOCKS
# define CONFIG_THOR_RESET_OFF
# define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
- "set dfu_alt_info " \
+ "setenv dfu_alt_info " \
"${kernel_image} ram 0x3000000 0x500000\\\\;" \
"${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
"${ramdisk_image} ram 0x2000000 0x600000\0" \
# if defined(CONFIG_MMC_SDHCI_ZYNQ)
# define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
- "set dfu_alt_info " \
+ "setenv dfu_alt_info " \
"${kernel_image} fat 0 1\\\\;" \
"${devicetree_image} fat 0 1\\\\;" \
"${ramdisk_image} fat 0 1\0" \
"env run importbootenv; " \
"fi; " \
"fi; \0" \
- "sd_loadbootenv=set bootenv_dev mmc && " \
+ "sd_loadbootenv=setenv bootenv_dev mmc && " \
"run setbootenv \0" \
- "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \
+ "usb_loadbootenv=setenv bootenv_dev usb && usb start && run setbootenv \0" \
"preboot=if test $modeboot = sdboot; then " \
"run sd_loadbootenv; " \
"echo Checking if uenvcmd is set ...; " \
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+
+#define CLK_TCON_TOP_TV0 0
+#define CLK_TCON_TOP_TV1 1
+#define CLK_TCON_TOP_DSI 2
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
unsigned int blocksize;
char *interface;
char *dev_part;
- char *filename;
+ const char *filename;
int fstype;
} fpga_fs_info;
CONFIG_QEMU_MIPS
CONFIG_QIXIS_I2C_ACCESS
CONFIG_QSPI
-CONFIG_QSPI_QUAD_SUPPORT
-CONFIG_QSPI_SEL_GPIO
CONFIG_QUOTA
CONFIG_R7780MP
CONFIG_R8A66597_BASE_ADDR
CONFIG_STV0991_HZ
CONFIG_STV0991_HZ_CLOCK
CONFIG_ST_SMI
-CONFIG_SUNXI_AHCI
CONFIG_SUNXI_GPIO
CONFIG_SUNXI_MAX_FB_SIZE
CONFIG_SUPERH_ON_CHIP_R8A66597
CONFIG_TIMESTAMP
CONFIG_TIZEN
CONFIG_TI_KSNAV
-CONFIG_TI_SPI_MMAP
CONFIG_TMU_TIMER
CONFIG_TPL_PAD_TO
CONFIG_TPM_TIS_BASE_ADDRESS
output = u_boot_console.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
assert expected_text in output
+@pytest.mark.buildconfigspec('cmd_fpga')
+@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
+@pytest.mark.buildconfigspec('fit')
+@pytest.mark.buildconfigspec('cmd_echo')
+def test_fpga_loadmk_fit_external(u_boot_console):
+ f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit_external')
+
+ u_boot_console.run_command('imi %x' % (addr))
+
+ expected_text = 'FPGA loaded successfully'
+ output = u_boot_console.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
+ assert expected_text in output
+
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('fit')
projects / project / bcm63xx / u-boot.git / commitdiff