* linker symbol __BL32_END__. Use these addresses to compute the TSP image
* size.
******************************************************************************/
-#define BL32_TOTAL_LIMIT (unsigned long)(&__BL32_END__)
+#define BL32_TOTAL_LIMIT BL32_END
#define BL32_TOTAL_SIZE (BL32_TOTAL_LIMIT - (unsigned long) BL32_BASE)
static tsp_args_t *set_smc_args(uint64_t arg0,
return value;
}
-/******************************************************************************
- * Determine whether the memory region delimited by 'addr' and 'size' is free,
- * given the extents of free memory.
- * Return 1 if it is free, 0 if it is not free or if the input values are
- * invalid.
- *****************************************************************************/
-int is_mem_free(uintptr_t free_base, size_t free_size,
- uintptr_t addr, size_t size)
-{
- uintptr_t free_end, requested_end;
-
- /*
- * Handle corner cases first.
- *
- * The order of the 2 tests is important, because if there's no space
- * left (i.e. free_size == 0) but we don't ask for any memory
- * (i.e. size == 0) then we should report that the memory is free.
- */
- if (size == 0)
- return 1; /* A zero-byte region is always free */
- if (free_size == 0)
- return 0;
-
- /*
- * Check that the end addresses don't overflow.
- * If they do, consider that this memory region is not free, as this
- * is an invalid scenario.
- */
- if (check_uptr_overflow(free_base, free_size - 1))
- return 0;
- free_end = free_base + (free_size - 1);
-
- if (check_uptr_overflow(addr, size - 1))
- return 0;
- requested_end = addr + (size - 1);
-
- /*
- * Finally, check that the requested memory region lies within the free
- * region.
- */
- return (addr >= free_base) && (requested_end <= free_end);
-}
-
-/* Generic function to return the size of an image */
-size_t get_image_size(unsigned int image_id)
-{
- uintptr_t dev_handle;
- uintptr_t image_handle;
- uintptr_t image_spec;
- size_t image_size = 0U;
- int io_result;
-
- /* Obtain a reference to the image by querying the platform layer */
- io_result = plat_get_image_source(image_id, &dev_handle, &image_spec);
- if (io_result != 0) {
- WARN("Failed to obtain reference to image id=%u (%i)\n",
- image_id, io_result);
- return 0;
- }
-
- /* Attempt to access the image */
- io_result = io_open(dev_handle, image_spec, &image_handle);
- if (io_result != 0) {
- WARN("Failed to access image id=%u (%i)\n",
- image_id, io_result);
- return 0;
- }
-
- /* Find the size of the image */
- io_result = io_size(image_handle, &image_size);
- if ((io_result != 0) || (image_size == 0U)) {
- WARN("Failed to determine the size of the image id=%u (%i)\n",
- image_id, io_result);
- }
- io_result = io_close(image_handle);
- /* Ignore improbable/unrecoverable error in 'close' */
-
- /* TODO: Consider maintaining open device connection from this
- * bootloader stage
- */
- io_result = io_dev_close(dev_handle);
- /* Ignore improbable/unrecoverable error in 'dev_close' */
-
- return image_size;
-}
-
/*******************************************************************************
* Internal function to load an image at a specific address given
* an image ID and extents of free memory.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Each platform must ensure that a header file of this name is in the system
-include path with the following constants defined. This may require updating the
-list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the Arm development
-platforms, this file is found in ``plat/arm/board/<plat_name>/include/``.
+include path with the following constants defined. This will require updating
+the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Platform ports may optionally use the file `include/plat/common/common\_def.h`_,
which provides typical values for some of the constants below. These values are
likely to be suitable for all platform ports.
-Platform ports that want to be aligned with standard Arm platforms (for example
-FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides
-standard values for some of the constants below. However, this requires the
-platform port to define additional platform porting constants in
-``platform_def.h``. These additional constants are not documented here.
-
- **#define : PLATFORM\_LINKER\_FORMAT**
Defines the linker format used by the platform, for example
meminfo.total_base = Base address of secure RAM visible to BL1
meminfo.total_size = Size of secure RAM visible to BL1
- meminfo.free_base = Base address of secure RAM available for allocation
- to BL1
- meminfo.free_size = Size of secure RAM available for allocation to BL1
This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
populates a similar structure to tell BL2 the extents of memory available for
compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
*Armv8 Architecture Extensions* in `Firmware Design`_.
-- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
- cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
- is set, the functions which deal with MPIDR assume that the ``MT`` bit in
- MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
- this flag is 0. Note that this option is not used on FVP platforms.
-
- ``BL2``: This is an optional build option which specifies the path to BL2
image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
built.
Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
option.
+- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
+ cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
+ is set, the functions which deal with MPIDR assume that the ``MT`` bit in
+ MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
+ this flag is 0. Note that this option is not used on FVP platforms.
+
- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
for the construction of composite state-ID in the power-state parameter.
The existing PSCI clients currently do not support this encoding of
proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) &
TYPER_PROC_NUM_MASK;
}
- assert(proc_num < rdistif_num);
- rdistif_base_addrs[proc_num] = rdistif_base;
+
+ if (proc_num < rdistif_num)
+ rdistif_base_addrs[proc_num] = rdistif_base;
+
rdistif_base += (1U << GICR_PCPUBASE_SHIFT);
} while ((typer_val & TYPER_LAST_BIT) == 0U);
}
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
void generic_delay_timer_init(void)
{
+ assert(is_armv7_gentimer_present());
+
/* Value in ticks */
unsigned int mult = MHZ_TICKS_PER_SEC;
--- /dev/null
+/*
+ * Copyright (c) 2019, Linaro Limited
+ * Copyright (c) 2019, Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <drivers/delay_timer.h>
+#include <drivers/rpi3/sdhost/rpi3_sdhost.h>
+#include <drivers/mmc.h>
+#include <drivers/rpi3/gpio/rpi3_gpio.h>
+#include <errno.h>
+#include <string.h>
+
+static void rpi3_sdhost_initialize(void);
+static int rpi3_sdhost_send_cmd(struct mmc_cmd *cmd);
+static int rpi3_sdhost_set_ios(unsigned int clk, unsigned int width);
+static int rpi3_sdhost_prepare(int lba, uintptr_t buf, size_t size);
+static int rpi3_sdhost_read(int lba, uintptr_t buf, size_t size);
+static int rpi3_sdhost_write(int lba, uintptr_t buf, size_t size);
+
+static const struct mmc_ops rpi3_sdhost_ops = {
+ .init = rpi3_sdhost_initialize,
+ .send_cmd = rpi3_sdhost_send_cmd,
+ .set_ios = rpi3_sdhost_set_ios,
+ .prepare = rpi3_sdhost_prepare,
+ .read = rpi3_sdhost_read,
+ .write = rpi3_sdhost_write,
+};
+
+static struct rpi3_sdhost_params rpi3_sdhost_params;
+
+/**
+ * Wait for command being processed.
+ *
+ * This function waits the command being processed. It compares
+ * the ENABLE flag of the HC_COMMAND register. When ENABLE flag disappeared
+ * it means the command is processed by the SDHOST.
+ * The timeout is currently 1000*100 us = 100 ms.
+ *
+ * @return 0: command finished. 1: command timed out.
+ */
+static int rpi3_sdhost_waitcommand(void)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+
+ volatile int timeout = 1000;
+
+ while ((mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_ENABLE)
+ && (--timeout > 0)) {
+ udelay(100);
+ }
+
+ return ((timeout > 0) ? 0 : (-(ETIMEDOUT)));
+}
+
+/**
+ * Send the command and argument to the SDHOST
+ *
+ * This function will wait for the previous command finished. And then
+ * clear any error status of previous command. And then
+ * send out the command and args. The command will be turned on the ENABLE
+ * flag before sending out.
+ */
+static void send_command_raw(unsigned int cmd, unsigned int arg)
+{
+ unsigned int status;
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+
+ /* wait for previous command finish */
+ rpi3_sdhost_waitcommand();
+
+ /* clean error status */
+ status = mmio_read_32(reg_base + HC_HOSTSTATUS);
+ if (status & HC_HSTST_MASK_ERROR_ALL)
+ mmio_write_32(reg_base + HC_HOSTSTATUS, status);
+
+ /* recording the command */
+ rpi3_sdhost_params.current_cmd = cmd & HC_CMD_COMMAND_MASK;
+
+ /* send the argument and command */
+ mmio_write_32(reg_base + HC_ARGUMENT, arg);
+ mmio_write_32(reg_base + HC_COMMAND, cmd | HC_CMD_ENABLE);
+}
+
+/**
+ * Send the command and argument to the SDHOST, decorated with control
+ * flags.
+ *
+ * This function will use send_command_raw to send the commands to SDHOST.
+ * But before sending it will decorate the command with control flags specific
+ * to SDHOST.
+ */
+static void send_command_decorated(unsigned int cmd, unsigned int arg)
+{
+ unsigned int cmd_flags = 0;
+
+ switch (cmd & HC_CMD_COMMAND_MASK) {
+ case MMC_CMD(0):
+ cmd_flags |= HC_CMD_RESPONSE_NONE;
+ break;
+ case MMC_ACMD(51):
+ cmd_flags |= HC_CMD_READ;
+ break;
+ case MMC_CMD(8):
+ case MMC_CMD(11):
+ case MMC_CMD(17):
+ case MMC_CMD(18):
+ cmd_flags |= HC_CMD_READ;
+ break;
+ case MMC_CMD(20):
+ case MMC_CMD(24):
+ case MMC_CMD(25):
+ cmd_flags |= HC_CMD_WRITE;
+ break;
+ case MMC_CMD(12):
+ cmd_flags |= HC_CMD_BUSY;
+ break;
+ default:
+ break;
+ }
+ send_command_raw(cmd | cmd_flags, arg);
+}
+
+/**
+ * drains the FIFO on DATA port
+ *
+ * This function drains any data left in the DATA port.
+ */
+static void rpi3_drain_fifo(void)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+ volatile int timeout = 100000;
+
+ rpi3_sdhost_waitcommand();
+
+ while (mmio_read_32(reg_base + HC_HOSTSTATUS) & HC_HSTST_HAVEDATA) {
+ mmio_read_32(reg_base + HC_DATAPORT);
+ udelay(100);
+ }
+
+ while (1) {
+ uint32_t edm, fsm;
+
+ edm = mmio_read_32(reg_base + HC_DEBUG);
+ fsm = edm & HC_DBG_FSM_MASK;
+
+ if ((fsm == HC_DBG_FSM_IDENTMODE) ||
+ (fsm == HC_DBG_FSM_DATAMODE))
+ break;
+
+ if ((fsm == HC_DBG_FSM_READWAIT) ||
+ (fsm == HC_DBG_FSM_WRITESTART1) ||
+ (fsm == HC_DBG_FSM_READDATA)) {
+ mmio_write_32(reg_base + HC_DEBUG,
+ edm | HC_DBG_FORCE_DATA_MODE);
+ break;
+ }
+
+ if (--timeout <= 0) {
+ ERROR("rpi3_sdhost: %s cannot recover stat\n",
+ __func__);
+ return;
+ }
+ }
+}
+
+/**
+ * Dump SDHOST registers
+ */
+static void rpi3_sdhost_print_regs(void)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+
+ INFO("rpi3_sdhost: HC_COMMAND: 0x%08x\n",
+ mmio_read_32(reg_base + HC_COMMAND));
+ INFO("rpi3_sdhost: HC_ARGUMENT: 0x%08x\n",
+ mmio_read_32(reg_base + HC_ARGUMENT));
+ INFO("rpi3_sdhost: HC_TIMEOUTCOUNTER: 0x%08x\n",
+ mmio_read_32(reg_base + HC_TIMEOUTCOUNTER));
+ INFO("rpi3_sdhost: HC_CLOCKDIVISOR: 0x%08x\n",
+ mmio_read_32(reg_base + HC_CLOCKDIVISOR));
+ INFO("rpi3_sdhost: HC_RESPONSE_0: 0x%08x\n",
+ mmio_read_32(reg_base + HC_RESPONSE_0));
+ INFO("rpi3_sdhost: HC_RESPONSE_1: 0x%08x\n",
+ mmio_read_32(reg_base + HC_RESPONSE_1));
+ INFO("rpi3_sdhost: HC_RESPONSE_2: 0x%08x\n",
+ mmio_read_32(reg_base + HC_RESPONSE_2));
+ INFO("rpi3_sdhost: HC_RESPONSE_3: 0x%08x\n",
+ mmio_read_32(reg_base + HC_RESPONSE_3));
+ INFO("rpi3_sdhost: HC_HOSTSTATUS: 0x%08x\n",
+ mmio_read_32(reg_base + HC_HOSTSTATUS));
+ INFO("rpi3_sdhost: HC_POWER: 0x%08x\n",
+ mmio_read_32(reg_base + HC_POWER));
+ INFO("rpi3_sdhost: HC_DEBUG: 0x%08x\n",
+ mmio_read_32(reg_base + HC_DEBUG));
+ INFO("rpi3_sdhost: HC_HOSTCONFIG: 0x%08x\n",
+ mmio_read_32(reg_base + HC_HOSTCONFIG));
+ INFO("rpi3_sdhost: HC_BLOCKSIZE: 0x%08x\n",
+ mmio_read_32(reg_base + HC_BLOCKSIZE));
+ INFO("rpi3_sdhost: HC_BLOCKCOUNT: 0x%08x\n",
+ mmio_read_32(reg_base + HC_BLOCKCOUNT));
+}
+
+/**
+ * Reset SDHOST
+ */
+static void rpi3_sdhost_reset(void)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+ unsigned int dbg;
+ uint32_t tmp1;
+
+ mmio_write_32(reg_base + HC_POWER, 0);
+ mmio_write_32(reg_base + HC_COMMAND, 0);
+ mmio_write_32(reg_base + HC_ARGUMENT, 0);
+
+ mmio_write_32(reg_base + HC_TIMEOUTCOUNTER, HC_TIMEOUT_DEFAULT);
+ mmio_write_32(reg_base + HC_CLOCKDIVISOR, 0);
+ mmio_write_32(reg_base + HC_HOSTSTATUS, HC_HSTST_RESET);
+ mmio_write_32(reg_base + HC_HOSTCONFIG, 0);
+ mmio_write_32(reg_base + HC_BLOCKSIZE, 0);
+ mmio_write_32(reg_base + HC_BLOCKCOUNT, 0);
+
+ dbg = mmio_read_32(reg_base + HC_DEBUG);
+ dbg &= ~((HC_DBG_FIFO_THRESH_MASK << HC_DBG_FIFO_THRESH_READ_SHIFT) |
+ (HC_DBG_FIFO_THRESH_MASK << HC_DBG_FIFO_THRESH_WRITE_SHIFT));
+ dbg |= (HC_FIFO_THRESH_READ << HC_DBG_FIFO_THRESH_READ_SHIFT) |
+ (HC_FIFO_THRESH_WRITE << HC_DBG_FIFO_THRESH_WRITE_SHIFT);
+ mmio_write_32(reg_base + HC_DEBUG, dbg);
+ mdelay(250);
+ mmio_write_32(reg_base + HC_POWER, 1);
+ mdelay(250);
+ rpi3_sdhost_params.clk_rate = 0;
+
+ mmio_write_32(reg_base + HC_CLOCKDIVISOR, HC_CLOCKDIVISOR_MAXVAL);
+ tmp1 = mmio_read_32(reg_base + HC_HOSTCONFIG);
+ mmio_write_32(reg_base + HC_HOSTCONFIG, tmp1 | HC_HSTCF_INT_BUSY);
+}
+
+static void rpi3_sdhost_initialize(void)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+
+ assert((rpi3_sdhost_params.reg_base & MMC_BLOCK_MASK) == 0);
+
+ rpi3_sdhost_reset();
+
+ mmio_write_32(reg_base + HC_CLOCKDIVISOR, HC_CLOCKDIVISOR_PREFERVAL);
+ udelay(300);
+}
+
+static int rpi3_sdhost_send_cmd(struct mmc_cmd *cmd)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+ int err = 0;
+ uint32_t cmd_idx;
+ uint32_t cmd_arg;
+ uint32_t cmd_flags = 0;
+ uint32_t intmask;
+
+ /* Wait for the command done */
+ err = rpi3_sdhost_waitcommand();
+ if (err != 0) {
+ WARN("previous command not done yet\n");
+ return err;
+ }
+
+ cmd_idx = cmd->cmd_idx & HC_CMD_COMMAND_MASK;
+ if (cmd_idx == MMC_CMD(17))
+ cmd_idx = MMC_CMD(18);
+
+ cmd_arg = cmd->cmd_arg;
+ if (cmd_idx == MMC_ACMD(51)) {
+ /* if previous cmd send to SDHOST is not MMC_CMD(55).
+ * It means this MMC_ACMD(51) is a resend.
+ * And we must also resend MMC_CMD(55) in this case
+ */
+ if (rpi3_sdhost_params.current_cmd != MMC_CMD(55)) {
+ send_command_decorated(
+ MMC_CMD(55),
+ rpi3_sdhost_params.sdcard_rca <<
+ RCA_SHIFT_OFFSET);
+ rpi3_sdhost_params.mmc_app_cmd = 1;
+ rpi3_sdhost_waitcommand();
+
+ /* Also we need to call prepare to clean the buffer */
+ rpi3_sdhost_prepare(0, (uintptr_t)NULL, 8);
+ }
+ }
+
+ /* We ignore MMC_CMD(12) sending from the TF-A's MMC driver
+ * because we send MMC_CMD(12) by ourselves.
+ */
+ if (cmd_idx == MMC_CMD(12))
+ return 0;
+
+ if ((cmd->resp_type & MMC_RSP_136) &&
+ (cmd->resp_type & MMC_RSP_BUSY)) {
+ ERROR("rpi3_sdhost: unsupported response type!\n");
+ return -(EOPNOTSUPP);
+ }
+
+ if (cmd->resp_type & MMC_RSP_48 && cmd->resp_type != MMC_RESPONSE_R2) {
+ /* 48-bit command
+ * We don't need to set any flags here because it is default.
+ */
+ } else if (cmd->resp_type & MMC_RSP_136) {
+ /* 136-bit command */
+ cmd_flags |= HC_CMD_RESPONSE_LONG;
+ } else {
+ /* no respond command */
+ cmd_flags |= HC_CMD_RESPONSE_NONE;
+ }
+
+ rpi3_sdhost_params.cmdbusy = 0;
+ if (cmd->resp_type & MMC_RSP_BUSY) {
+ cmd_flags |= HC_CMD_BUSY;
+ rpi3_sdhost_params.cmdbusy = 1;
+ }
+
+ if (rpi3_sdhost_params.mmc_app_cmd) {
+ switch (cmd_idx) {
+ case MMC_ACMD(41):
+ if (cmd_arg == OCR_HCS)
+ cmd_arg |= OCR_3_3_3_4;
+ break;
+ default:
+ break;
+ }
+ rpi3_sdhost_params.mmc_app_cmd = 0;
+ }
+
+ if (cmd_idx == MMC_CMD(55))
+ rpi3_sdhost_params.mmc_app_cmd = 1;
+
+ send_command_decorated(cmd_idx | cmd_flags, cmd_arg);
+
+ intmask = mmio_read_32(reg_base + HC_HOSTSTATUS);
+ if (rpi3_sdhost_params.cmdbusy && (intmask & HC_HSTST_INT_BUSY)) {
+ mmio_write_32(reg_base + HC_HOSTSTATUS, HC_HSTST_INT_BUSY);
+ rpi3_sdhost_params.cmdbusy = 0;
+ }
+
+ if (!(cmd_flags & HC_CMD_RESPONSE_NONE)) {
+ err = rpi3_sdhost_waitcommand();
+ if (err != 0)
+ ERROR("rpi3_sdhost: cmd cannot be finished\n");
+ }
+
+ cmd->resp_data[0] = mmio_read_32(reg_base + HC_RESPONSE_0);
+ cmd->resp_data[1] = mmio_read_32(reg_base + HC_RESPONSE_1);
+ cmd->resp_data[2] = mmio_read_32(reg_base + HC_RESPONSE_2);
+ cmd->resp_data[3] = mmio_read_32(reg_base + HC_RESPONSE_3);
+
+ if (mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_FAILED) {
+ uint32_t sdhsts = mmio_read_32(reg_base + HC_HOSTSTATUS);
+
+ mmio_write_32(reg_base + HC_HOSTSTATUS,
+ HC_HSTST_MASK_ERROR_ALL);
+
+ if (!(sdhsts & HC_HSTST_ERROR_CRC7)
+ || (cmd_idx != MMC_ACMD(51))) {
+ if (sdhsts & HC_HSTST_TIMEOUT_CMD) {
+ ERROR("rpi3_sdhost: timeout status 0x%x\n",
+ sdhsts);
+ err = -(ETIMEDOUT);
+ } else {
+ ERROR("rpi3_sdhost: unknown err, cmd = 0x%x\n",
+ mmio_read_32(reg_base + HC_COMMAND));
+ ERROR("rpi3_sdhost status: 0x%x\n", sdhsts);
+ err = -(EILSEQ);
+ }
+ }
+ }
+
+ if ((!err) && (cmd_idx == MMC_CMD(3))) {
+ /* we keep the RCA in case to send MMC_CMD(55) ourselves */
+ rpi3_sdhost_params.sdcard_rca = (cmd->resp_data[0]
+ & 0xFFFF0000U) >> 16;
+ }
+
+ return err;
+}
+
+static int rpi3_sdhost_set_clock(unsigned int clk)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+ uint32_t max_clk = 250000000;
+ uint32_t div;
+
+ if (clk < 100000) {
+ mmio_write_32(reg_base + HC_CLOCKDIVISOR,
+ HC_CLOCKDIVISOR_MAXVAL);
+ return 0;
+ }
+
+ div = max_clk / clk;
+ if (div < 2)
+ div = 2;
+
+ if ((max_clk / div) > clk)
+ div++;
+
+ div -= 2;
+ if (div > HC_CLOCKDIVISOR_MAXVAL)
+ div = HC_CLOCKDIVISOR_MAXVAL;
+
+ rpi3_sdhost_params.clk_rate = max_clk / (div + 2);
+ rpi3_sdhost_params.ns_per_fifo_word = (1000000000 /
+ rpi3_sdhost_params.clk_rate)
+ * 8;
+
+ mmio_write_32(reg_base + HC_CLOCKDIVISOR, div);
+ return 0;
+}
+
+static int rpi3_sdhost_set_ios(unsigned int clk, unsigned int width)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+ uint32_t tmp1;
+
+ rpi3_sdhost_set_clock(clk);
+ VERBOSE("rpi3_sdhost: Changing clock to %dHz for data mode\n", clk);
+
+ if (width != MMC_BUS_WIDTH_4 && width != MMC_BUS_WIDTH_1) {
+ ERROR("rpi3_sdhost: width %d not supported\n", width);
+ return -(EOPNOTSUPP);
+ }
+ rpi3_sdhost_params.bus_width = width;
+
+ tmp1 = mmio_read_32(reg_base + HC_HOSTCONFIG);
+ tmp1 &= ~(HC_HSTCF_EXTBUS_4BIT);
+ if (rpi3_sdhost_params.bus_width == MMC_BUS_WIDTH_4)
+ tmp1 |= HC_HSTCF_EXTBUS_4BIT;
+
+ mmio_write_32(reg_base + HC_HOSTCONFIG, tmp1);
+ tmp1 = mmio_read_32(reg_base + HC_HOSTCONFIG);
+ mmio_write_32(reg_base + HC_HOSTCONFIG, tmp1 |
+ HC_HSTCF_SLOW_CARD | HC_HSTCF_INTBUS_WIDE);
+
+ return 0;
+}
+
+static int rpi3_sdhost_prepare(int lba, uintptr_t buf, size_t size)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+ size_t blocks;
+ size_t blocksize;
+
+ if (size < 512) {
+ blocksize = size;
+ blocks = 1;
+ } else {
+ blocksize = 512;
+ blocks = size / blocksize;
+ if (size % blocksize != 0)
+ blocks++;
+ }
+
+ rpi3_drain_fifo();
+
+ mmio_write_32(reg_base + HC_BLOCKSIZE, blocksize);
+ mmio_write_32(reg_base + HC_BLOCKCOUNT, blocks);
+ udelay(100);
+ return 0;
+}
+
+static int rpi3_sdhost_read(int lba, uintptr_t buf, size_t size)
+{
+ int err = 0;
+ uint32_t *buf1 = ((uint32_t *) buf);
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+ int timeout = 100000;
+ int remaining_words = 0;
+
+ for (int i = 0; i < size / 4; i++) {
+ volatile int t = timeout;
+ uint32_t hsts_err;
+
+ while ((mmio_read_32(reg_base + HC_HOSTSTATUS)
+ & HC_HSTST_HAVEDATA) == 0) {
+ if (t == 0) {
+ ERROR("rpi3_sdhost: fifo timeout after %dus\n",
+ timeout);
+ err = -(ETIMEDOUT);
+ break;
+ }
+ t--;
+ udelay(10);
+ }
+ if (t == 0)
+ break;
+
+ uint32_t data = mmio_read_32(reg_base + HC_DATAPORT);
+
+ hsts_err = mmio_read_32(reg_base + HC_HOSTSTATUS)
+ & HC_HSTST_MASK_ERROR_ALL;
+ if (hsts_err) {
+ ERROR("rpi3_sdhost: transfer FIFO word %d: 0x%x\n",
+ i,
+ mmio_read_32(reg_base + HC_HOSTSTATUS));
+ rpi3_sdhost_print_regs();
+
+ err = -(EILSEQ);
+
+ /* clean the error status */
+ mmio_write_32(reg_base + HC_HOSTSTATUS, hsts_err);
+ }
+
+ if (buf1)
+ buf1[i] = data;
+
+ /* speeding up if the remaining words are still a lot */
+ remaining_words = (mmio_read_32(reg_base + HC_DEBUG) >> 4)
+ & HC_DBG_FIFO_THRESH_MASK;
+ if (remaining_words >= 7)
+ continue;
+
+ /* delay. slowing down the read process */
+ udelay(100);
+ }
+
+ /* We decide to stop by ourselves.
+ * It is because MMC_CMD(18) -> MMC_CMD(13) -> MMC_CMD(12)
+ * doesn't work for RPi3 SDHost.
+ */
+ if (rpi3_sdhost_params.current_cmd == MMC_CMD(18))
+ send_command_decorated(MMC_CMD(12), 0);
+
+ if (err == -(EILSEQ)) {
+ const int max_retries = 20;
+ int r;
+
+ rpi3_sdhost_params.crc_err_retries++;
+ if (rpi3_sdhost_params.crc_err_retries < max_retries) {
+ /* retries if there's an CRC error */
+ r = rpi3_sdhost_prepare(lba, buf, size);
+ send_command_decorated(MMC_CMD(18), lba);
+ r = rpi3_sdhost_read(lba, buf, size);
+ if (r == 0)
+ err = 0;
+ }
+ }
+
+ return err;
+}
+
+static int rpi3_sdhost_write(int lba, uintptr_t buf, size_t size)
+{
+ uint32_t *buf1 = ((uint32_t *) buf);
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+ int err = 0;
+ int remaining_words = 0;
+
+ for (int i = 0; i < size / 4; i++) {
+ uint32_t hsts_err;
+ uint32_t data = buf1[i];
+ uint32_t dbg;
+ uint32_t fsm_state;
+
+ mmio_write_32(reg_base + HC_DATAPORT, data);
+
+ dbg = mmio_read_32(reg_base + HC_DEBUG);
+ fsm_state = dbg & HC_DBG_FSM_MASK;
+ if (fsm_state != HC_DBG_FSM_WRITEDATA
+ && fsm_state != HC_DBG_FSM_WRITESTART1
+ && fsm_state != HC_DBG_FSM_WRITESTART2
+ && fsm_state != HC_DBG_FSM_WRITECRC
+ && fsm_state != HC_DBG_FSM_WRITEWAIT1
+ && fsm_state != HC_DBG_FSM_WRITEWAIT2) {
+ hsts_err = mmio_read_32(reg_base + HC_HOSTSTATUS)
+ & HC_HSTST_MASK_ERROR_ALL;
+ if (hsts_err)
+ err = -(EILSEQ);
+ }
+
+ /* speeding up if the remaining words are not many */
+ remaining_words = (mmio_read_32(reg_base + HC_DEBUG) >> 4)
+ & HC_DBG_FIFO_THRESH_MASK;
+ if (remaining_words <= 4)
+ continue;
+
+ udelay(100);
+ }
+
+ /* We decide to stop by ourselves.
+ * It is because MMC_CMD(25) -> MMC_CMD(13) -> MMC_CMD(12)
+ * doesn't work for RPi3 SDHost.
+ */
+ if (rpi3_sdhost_params.current_cmd == MMC_CMD(25))
+ send_command_decorated(MMC_CMD(12), 0);
+
+ return err;
+}
+
+void rpi3_sdhost_init(struct rpi3_sdhost_params *params,
+ struct mmc_device_info *mmc_dev_info)
+{
+ assert((params != 0) &&
+ ((params->reg_base & MMC_BLOCK_MASK) == 0));
+
+ memcpy(&rpi3_sdhost_params, params, sizeof(struct rpi3_sdhost_params));
+
+ /* backup GPIO 48 to 53 configurations */
+ for (int i = 48; i <= 53; i++) {
+ rpi3_sdhost_params.gpio48_pinselect[i - 48]
+ = rpi3_gpio_get_select(i);
+ VERBOSE("rpi3_sdhost: Original GPIO state %d: %d\n",
+ i,
+ rpi3_sdhost_params.gpio48_pinselect[i - 48]);
+ }
+
+ /* setting pull resistors for 48 to 53.
+ * GPIO 48 (SD_CLK) to GPIO_PULL_UP
+ * GPIO 49 (SD_CMD) to GPIO_PULL_NONE
+ * GPIO 50 (SD_D0) to GPIO_PULL_NONE
+ * GPIO 51 (SD_D1) to GPIO_PULL_NONE
+ * GPIO 52 (SD_D2) to GPIO_PULL_NONE
+ * GPIO 53 (SD_D3) to GPIO_PULL_NONE
+ */
+ gpio_set_pull(48, GPIO_PULL_UP);
+ for (int i = 49; i <= 53; i++)
+ gpio_set_pull(i, GPIO_PULL_NONE);
+
+ /* Set pin 48-53 to alt-0. It means route SDHOST to card slot */
+ for (int i = 48; i <= 53; i++)
+ rpi3_gpio_set_select(i, RPI3_GPIO_FUNC_ALT0);
+
+ mmc_init(&rpi3_sdhost_ops, params->clk_rate, params->bus_width,
+ params->flags, mmc_dev_info);
+}
+
+void rpi3_sdhost_stop(void)
+{
+ uintptr_t reg_base = rpi3_sdhost_params.reg_base;
+
+ VERBOSE("rpi3_sdhost: Shutting down: drain FIFO out\n");
+ rpi3_drain_fifo();
+
+ VERBOSE("rpi3_sdhost: Shutting down: slowing down the clock\n");
+ mmio_write_32(reg_base+HC_CLOCKDIVISOR, HC_CLOCKDIVISOR_SLOWVAL);
+ udelay(500);
+
+ VERBOSE("rpi3_sdhost: Shutting down: put SDHost into idle state\n");
+ send_command_decorated(MMC_CMD(0), 0);
+ udelay(500);
+
+ mmio_write_32(reg_base + HC_COMMAND, 0);
+ mmio_write_32(reg_base + HC_ARGUMENT, 0);
+ mmio_write_32(reg_base + HC_TIMEOUTCOUNTER, HC_TIMEOUT_IDLE);
+ mmio_write_32(reg_base + HC_CLOCKDIVISOR, HC_CLOCKDIVISOR_STOPVAL);
+
+ udelay(100);
+
+ mmio_write_32(reg_base + HC_POWER, 0);
+ mmio_write_32(reg_base + HC_HOSTCONFIG, 0);
+ mmio_write_32(reg_base + HC_BLOCKSIZE, 0x400);
+ mmio_write_32(reg_base + HC_BLOCKCOUNT, 0);
+ mmio_write_32(reg_base + HC_HOSTSTATUS, 0x7f8);
+
+ mmio_write_32(reg_base + HC_COMMAND, 0);
+ mmio_write_32(reg_base + HC_ARGUMENT, 0);
+
+ udelay(100);
+
+ /* Restore the pinmux to original state */
+ for (int i = 48; i <= 53; i++) {
+ rpi3_gpio_set_select(i,
+ rpi3_sdhost_params.gpio48_pinselect[i-48]);
+ }
+
+ /* Must reset the pull resistors for u-boot to work.
+ * GPIO 48 (SD_CLK) to GPIO_PULL_NONE
+ * GPIO 49 (SD_CMD) to GPIO_PULL_UP
+ * GPIO 50 (SD_D0) to GPIO_PULL_UP
+ * GPIO 51 (SD_D1) to GPIO_PULL_UP
+ * GPIO 52 (SD_D2) to GPIO_PULL_UP
+ * GPIO 53 (SD_D3) to GPIO_PULL_UP
+ */
+ gpio_set_pull(48, GPIO_PULL_NONE);
+ for (int i = 49; i <= 53; i++)
+ gpio_set_pull(i, GPIO_PULL_UP);
+}
#define ID_PFR1_VIRTEXT_MASK U(0xf)
#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
& ID_PFR1_VIRTEXT_MASK)
+#define ID_PFR1_GENTIMER_SHIFT U(16)
+#define ID_PFR1_GENTIMER_MASK U(0xf)
#define ID_PFR1_GIC_SHIFT U(28)
#define ID_PFR1_GIC_MASK U(0xf)
#include <arch_helpers.h>
+static inline bool is_armv7_gentimer_present(void)
+{
+ return ((read_id_pfr1() >> ID_PFR1_GENTIMER_SHIFT) &
+ ID_PFR1_GENTIMER_MASK) != 0U;
+}
+
static inline bool is_armv8_2_ttcnp_present(void)
{
return ((read_id_mmfr4() >> ID_MMFR4_CNP_SHIFT) &
#include <arch_helpers.h>
+static inline bool is_armv7_gentimer_present(void)
+{
+ /* The Generic Timer is always present in an ARMv8-A implementation */
+ return true;
+}
+
static inline bool is_armv8_2_ttcnp_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
* BL images
*/
#if SEPARATE_CODE_AND_RODATA
-IMPORT_SYM(unsigned long, __TEXT_START__, BL_CODE_BASE);
-IMPORT_SYM(unsigned long, __TEXT_END__, BL_CODE_END);
-IMPORT_SYM(unsigned long, __RODATA_START__, BL_RO_DATA_BASE);
-IMPORT_SYM(unsigned long, __RODATA_END__, BL_RO_DATA_END);
+IMPORT_SYM(uintptr_t, __TEXT_START__, BL_CODE_BASE);
+IMPORT_SYM(uintptr_t, __TEXT_END__, BL_CODE_END);
+IMPORT_SYM(uintptr_t, __RODATA_START__, BL_RO_DATA_BASE);
+IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END);
#else
-IMPORT_SYM(unsigned long, __RO_START__, BL_CODE_BASE);
-IMPORT_SYM(unsigned long, __RO_END__, BL_CODE_END);
+IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
+IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END);
#endif
#if defined(IMAGE_BL1)
-IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END);
+IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END);
-IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE);
-IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT);
+IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE);
+IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT);
#elif defined(IMAGE_BL2)
-IMPORT_SYM(unsigned long, __BL2_END__, BL2_END);
+IMPORT_SYM(uintptr_t, __BL2_END__, BL2_END);
#elif defined(IMAGE_BL2U)
-IMPORT_SYM(unsigned long, __BL2U_END__, BL2U_END);
+IMPORT_SYM(uintptr_t, __BL2U_END__, BL2U_END);
#elif defined(IMAGE_BL31)
-IMPORT_SYM(unsigned long, __BL31_START__, BL31_START);
-IMPORT_SYM(unsigned long, __BL31_END__, BL31_END);
+IMPORT_SYM(uintptr_t, __BL31_START__, BL31_START);
+IMPORT_SYM(uintptr_t, __BL31_END__, BL31_END);
#elif defined(IMAGE_BL32)
-IMPORT_SYM(unsigned long, __BL32_END__, BL32_END);
+IMPORT_SYM(uintptr_t, __BL32_END__, BL32_END);
#endif /* IMAGE_BLX */
/* The following symbols are only exported from the BL2 at EL3 linker script. */
#if BL2_IN_XIP_MEM && defined(IMAGE_BL2)
-extern uintptr_t __BL2_ROM_END__;
-#define BL2_ROM_END (uintptr_t)(&__BL2_ROM_END__)
+IMPORT_SYM(uintptr_t, __BL2_ROM_END__, BL2_ROM_END);
-extern uintptr_t __BL2_RAM_START__;
-extern uintptr_t __BL2_RAM_END__;
-#define BL2_RAM_BASE (uintptr_t)(&__BL2_RAM_START__)
-#define BL2_RAM_LIMIT (uintptr_t)(&__BL2_RAM_END__)
+IMPORT_SYM(uintptr_t, __BL2_RAM_START__, BL2_RAM_BASE);
+IMPORT_SYM(uintptr_t, __BL2_RAM_END__, BL2_RAM_END);
#endif /* BL2_IN_XIP_MEM */
/*
* page-aligned addresses.
*/
#if USE_COHERENT_MEM
-IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE);
-IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL_COHERENT_RAM_END);
+IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE);
+IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, BL_COHERENT_RAM_END);
#endif
/*******************************************************************************
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
-size_t get_image_size(unsigned int image_id);
-
-int is_mem_free(uintptr_t free_base, size_t free_size,
- uintptr_t addr, size_t size);
-
int load_auth_image(unsigned int image_id, image_info_t *image_data);
#if TRUSTED_BOARD_BOOT && defined(DYN_DISABLE_AUTH)
--- /dev/null
+/*
+ * Copyright (c) 2019, Linaro Limited
+ * Copyright (c) 2019, Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPI3_SDHOST_H
+#define RPI3_SDHOST_H
+
+#include <drivers/mmc.h>
+#include <stdint.h>
+#include <platform_def.h>
+
+struct rpi3_sdhost_params {
+ uintptr_t reg_base;
+ uint32_t clk_rate;
+ uint32_t bus_width;
+ uint32_t flags;
+ uint32_t current_cmd;
+ uint8_t cmdbusy;
+ uint8_t mmc_app_cmd;
+ uint32_t ns_per_fifo_word;
+ uint32_t crc_err_retries;
+
+ uint32_t sdcard_rca;
+ uint32_t gpio48_pinselect[6];
+};
+
+void rpi3_sdhost_init(struct rpi3_sdhost_params *params,
+ struct mmc_device_info *mmc_dev_info);
+void rpi3_sdhost_stop(void);
+
+/* Registers */
+#define HC_COMMAND 0x00 /* Command and flags */
+#define HC_ARGUMENT 0x04
+#define HC_TIMEOUTCOUNTER 0x08
+#define HC_CLOCKDIVISOR 0x0c
+#define HC_RESPONSE_0 0x10
+#define HC_RESPONSE_1 0x14
+#define HC_RESPONSE_2 0x18
+#define HC_RESPONSE_3 0x1c
+#define HC_HOSTSTATUS 0x20
+#define HC_POWER 0x30
+#define HC_DEBUG 0x34
+#define HC_HOSTCONFIG 0x38
+#define HC_BLOCKSIZE 0x3c
+#define HC_DATAPORT 0x40
+#define HC_BLOCKCOUNT 0x50
+
+/* Flags for HC_COMMAND register */
+#define HC_CMD_ENABLE 0x8000
+#define HC_CMD_FAILED 0x4000
+#define HC_CMD_BUSY 0x0800
+#define HC_CMD_RESPONSE_NONE 0x0400
+#define HC_CMD_RESPONSE_LONG 0x0200
+#define HC_CMD_WRITE 0x0080
+#define HC_CMD_READ 0x0040
+#define HC_CMD_COMMAND_MASK 0x003f
+
+#define HC_CLOCKDIVISOR_MAXVAL 0x07ff
+#define HC_CLOCKDIVISOR_PREFERVAL 0x027b
+#define HC_CLOCKDIVISOR_SLOWVAL 0x0148
+#define HC_CLOCKDIVISOR_STOPVAL 0x01fb
+
+/* Flags for HC_HOSTSTATUS register */
+#define HC_HSTST_HAVEDATA 0x0001
+#define HC_HSTST_ERROR_FIFO 0x0008
+#define HC_HSTST_ERROR_CRC7 0x0010
+#define HC_HSTST_ERROR_CRC16 0x0020
+#define HC_HSTST_TIMEOUT_CMD 0x0040
+#define HC_HSTST_TIMEOUT_DATA 0x0080
+#define HC_HSTST_INT_BLOCK 0x0200
+#define HC_HSTST_INT_BUSY 0x0400
+
+#define HC_HSTST_RESET 0xffff
+
+#define HC_HSTST_MASK_ERROR_DATA (HC_HSTST_ERROR_FIFO | \
+ HC_HSTST_ERROR_CRC7 | \
+ HC_HSTST_ERROR_CRC16 | \
+ HC_HSTST_TIMEOUT_DATA)
+
+#define HC_HSTST_MASK_ERROR_ALL (HC_HSTST_MASK_ERROR_DATA | \
+ HC_HSTST_TIMEOUT_CMD)
+
+/* Flags for HC_HOSTCONFIG register */
+#define HC_HSTCF_INTBUS_WIDE 0x0002
+#define HC_HSTCF_EXTBUS_4BIT 0x0004
+#define HC_HSTCF_SLOW_CARD 0x0008
+#define HC_HSTCF_INT_DATA 0x0010
+#define HC_HSTCF_INT_BLOCK 0x0100
+#define HC_HSTCF_INT_BUSY 0x0400
+
+/* Flags for HC_DEBUG register */
+#define HC_DBG_FIFO_THRESH_WRITE_SHIFT 9
+#define HC_DBG_FIFO_THRESH_READ_SHIFT 14
+#define HC_DBG_FIFO_THRESH_MASK 0x001f
+#define HC_DBG_FSM_MASK 0xf
+#define HC_DBG_FSM_IDENTMODE 0x0
+#define HC_DBG_FSM_DATAMODE 0x1
+#define HC_DBG_FSM_READDATA 0x2
+#define HC_DBG_FSM_WRITEDATA 0x3
+#define HC_DBG_FSM_READWAIT 0x4
+#define HC_DBG_FSM_READCRC 0x5
+#define HC_DBG_FSM_WRITECRC 0x6
+#define HC_DBG_FSM_WRITEWAIT1 0x7
+#define HC_DBG_FSM_POWERDOWN 0x8
+#define HC_DBG_FSM_POWERUP 0x9
+#define HC_DBG_FSM_WRITESTART1 0xa
+#define HC_DBG_FSM_WRITESTART2 0xb
+#define HC_DBG_FSM_GENPULSES 0xc
+#define HC_DBG_FSM_WRITEWAIT2 0xd
+#define HC_DBG_FSM_STARTPOWDOWN 0xf
+#define HC_DBG_FORCE_DATA_MODE 0x40000
+
+/* Settings */
+#define HC_FIFO_SIZE 16
+#define HC_FIFO_THRESH_READ 4
+#define HC_FIFO_THRESH_WRITE 4
+
+#define HC_TIMEOUT_DEFAULT 0x00f00000
+#define HC_TIMEOUT_IDLE 0x00a00000
+
+#endif /* RPI3_SDHOST_H */
#endif /* CSS_LOAD_SCP_IMAGES */
/* Load address of Non-Secure Image for CSS platform ports */
-#define PLAT_ARM_NS_IMAGE_OFFSET U(0xE0000000)
+#define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000)
/* TZC related constants */
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
.endm
/*
- * Define MMU-enabling functions for EL1 and EL3:
+ * Define MMU-enabling functions for EL1, EL2 and EL3:
*
* enable_mmu_direct_el1
+ * enable_mmu_direct_el2
* enable_mmu_direct_el3
*/
define_mmu_enable_func 1
-------------------------------------------------------------
:M: Nariman Poushin <nariman.poushin@linaro.org>
:G: `npoushin`_
+:M: Thomas Abraham <thomas.abraham@arm.com>
+:G: `thomas-arm`_
:F: plat/arm/css/sgi/
:F: plat/arm/css/sgm/
:F: plat/arm/board/sgi575/
:F: docs/plat/poplar.rst
:F: plat/hisilicon/poplar/
+Intel SocFPGA platform ports
+----------------------------
+:M: Tien Hock Loh <tien.hock.loh@intel.com>
+:G: `thloh85-intel`
+:F: plat/intel/soc
+
MediaTek platform ports
-----------------------
:M: Yidi Lin (林以廸) <yidi.lin@mediatek.com>
----------------------------
:M: Antonio Niño Díaz <antonio.ninodiaz@arm.com>
:G: `antonio-nino-diaz-arm`_
+:M: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+:G: `grandpaul`_
:F: docs/plat/rpi3.rst
:F: plat/rpi3/
+:F: drivers/rpi3/
+:F: include/drivers/rpi3/
Renesas rcar-gen3 platform port
-------------------------------
.. _sivadur: https://github.com/sivadur
.. _smaeul: https://github.com/smaeul
.. _soby-mathew: https://github.com/soby-mathew
+.. _thomas-arm: https://github.com/thomas-arm
.. _TonyXie06: https://github.com/TonyXie06
.. _vwadekar: https://github.com/vwadekar
.. _Yann-lms: https://github.com/Yann-lms
/*
* Load address of BL33 for this platform port
*/
-#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000))
+#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000))
/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
#else
- .ep_info.pc = PLAT_ARM_NS_IMAGE_OFFSET,
+ .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
- .image_info.image_base = PLAT_ARM_NS_IMAGE_OFFSET,
- .image_info.image_max_size = ARM_DRAM1_SIZE,
+ .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
+ .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
+ - PLAT_ARM_NS_IMAGE_BASE,
#endif /* PRELOADED_BL33_BASE */
.next_handoff_image_id = INVALID_IMAGE_ID,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
# else
- .ep_info.pc = PLAT_ARM_NS_IMAGE_OFFSET,
+ .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
- .image_info.image_base = PLAT_ARM_NS_IMAGE_OFFSET,
- .image_info.image_max_size = ARM_DRAM1_SIZE,
+ .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
+ .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
+ - PLAT_ARM_NS_IMAGE_BASE,
# endif /* PRELOADED_BL33_BASE */
.next_handoff_image_id = INVALID_IMAGE_ID,
#ifdef PRELOADED_BL33_BASE
return PRELOADED_BL33_BASE;
#else
- return PLAT_ARM_NS_IMAGE_OFFSET;
+ return PLAT_ARM_NS_IMAGE_BASE;
#endif
}
* until the end of DRAM1.
* We limit the size of DRAM2 to 1 GB to avoid big delays while booting
*/
-#define DRAM1_NS_IMAGE_LIMIT (PLAT_ARM_NS_IMAGE_OFFSET + (32 << TWO_MB_SHIFT))
+#define DRAM1_NS_IMAGE_LIMIT (PLAT_ARM_NS_IMAGE_BASE + (32 << TWO_MB_SHIFT))
#define DRAM1_PROTECTED_SIZE (ARM_NS_DRAM1_END+1u - DRAM1_NS_IMAGE_LIMIT)
static mem_region_t arm_ram_ranges[] = {
#include <drivers/console.h>
#include <plat/arm/common/plat_arm.h>
-#define BL32_END (unsigned long)(&__BL32_END__)
-
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak tsp_early_platform_setup
#pragma weak tsp_platform_setup
#include <plat/common/platform.h>
#include <services/secure_partition.h>
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
-#define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
-#endif
-
#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE)
#include <hisi_sram_map.h>
#include "hikey_private.h"
-/*
- * The next 2 constants identify the extents of the code & RO data region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
- */
-#define BL2_RO_BASE (unsigned long)(&__RO_START__)
-#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
-
-#define BL2_RW_BASE (BL2_RO_LIMIT)
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
+#define BL2_RW_BASE (BL_CODE_END)
static meminfo_t bl2_el3_tzram_layout;
static console_pl011_t console;
{
hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base,
bl2_el3_tzram_layout.total_size,
- BL2_RO_BASE,
- BL2_RO_LIMIT,
- BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT);
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
void bl2_platform_setup(void)
#include "hikey_private.h"
-/*
- * The next 2 constants identify the extents of the code & RO data region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
- */
-#define BL31_RO_BASE (unsigned long)(&__RO_START__)
-#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static console_pl011_t console;
{
hikey_init_mmu_el3(BL31_BASE,
BL31_LIMIT - BL31_BASE,
- BL31_RO_BASE,
- BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
/* Initialize EDMAC controller with non-secure mode. */
USE_COHERENT_MEM := 1
-PLAT_INCLUDES := -Iinclude/common/tbbr \
- -Iplat/hisilicon/hikey/include
+PLAT_INCLUDES := -Iplat/hisilicon/hikey/include
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
lib/xlat_tables/aarch64/xlat_tables.c \
#include "hikey960_def.h"
#include "hikey960_private.h"
-/*
- * The next 2 constants identify the extents of the code & RO data region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
- */
-#define BL2_RO_BASE (unsigned long)(&__RO_START__)
-#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
-
-#define BL2_RW_BASE (BL2_RO_LIMIT)
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
+#define BL2_RW_BASE (BL_CODE_END)
static meminfo_t bl2_el3_tzram_layout;
static console_pl011_t console;
{
hikey960_init_mmu_el3(bl2_el3_tzram_layout.total_base,
bl2_el3_tzram_layout.total_size,
- BL2_RO_BASE,
- BL2_RO_LIMIT,
- BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT);
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
void bl2_platform_setup(void)
#include "hikey960_def.h"
#include "hikey960_private.h"
-/*
- * The next 2 constants identify the extents of the code & RO data region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
- */
-#define BL31_RO_BASE (unsigned long)(&__RO_START__)
-#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static console_pl011_t console;
{
hikey960_init_mmu_el3(BL31_BASE,
BL31_LIMIT - BL31_BASE,
- BL31_RO_BASE,
- BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
static void hikey960_edma_init(void)
non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC;
mmio_write_32(EDMAC_SEC_CTRL, non_secure);
- for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) {
+ /* Channel 0 is reserved for LPM3, keep secure */
+ for (i = 1; i < EDMAC_CHANNEL_NUMS; i++) {
mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
}
}
USE_COHERENT_MEM := 1
-PLAT_INCLUDES := -Iinclude/common/tbbr \
- -Iplat/hisilicon/hikey960/include
+PLAT_INCLUDES := -Iplat/hisilicon/hikey960/include
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
drivers/delay_timer/delay_timer.c \
#include "hi3798cv200.h"
#include "plat_private.h"
-/* Memory ranges for code and read only data sections */
-#define BL2_RO_BASE (unsigned long)(&__RO_START__)
-#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
-
-/* Memory ranges for coherent memory section */
-#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
static console_pl011_t console;
{
plat_configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
- BL2_RO_BASE,
- BL2_RO_LIMIT,
- BL2_COHERENT_RAM_BASE,
- BL2_COHERENT_RAM_LIMIT);
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
void bl2_platform_setup(void)
#include "hi3798cv200.h"
#include "plat_private.h"
-/* Memory ranges for code and RO data sections */
-#define BL31_RO_BASE (unsigned long)(&__RO_START__)
-#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-
-/* Memory ranges for coherent memory section */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
#define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45)
static entry_point_info_t bl32_image_ep_info;
{
plat_configure_mmu_el3(BL31_BASE,
(BL31_LIMIT - BL31_BASE),
- BL31_RO_BASE,
- BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
INFO("Boot BL33 from 0x%lx for %lu Bytes\n",
bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);
$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
PLAT_INCLUDES := -Iplat/hisilicon/poplar/include \
- -Iplat/hisilicon/poplar \
- -Iinclude/common/tbbr
+ -Iplat/hisilicon/poplar
PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/aarch64/xlat_tables.c \
# Platform
PLAT_INCLUDES := -Idrivers/imx/uart \
- -Iinclude/common/tbbr \
-Iplat/imx/common/include/ \
-Iplat/imx/imx7/warp7/include \
-Idrivers/imx/timer \
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <platform_def.h>
+
+ .globl plat_secondary_cold_boot_setup
+ .globl platform_is_primary_cpu
+ .globl plat_is_my_cpu_primary
+ .globl plat_my_core_pos
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+ .globl plat_crash_console_flush
+ .globl platform_mem_init
+
+ .globl plat_get_my_entrypoint
+ .globl stratix10_sec_entry
+ .globl cpuid_release
+
+ /* -----------------------------------------------------
+ * void plat_secondary_cold_boot_setup (void);
+ *
+ * This function performs any platform specific actions
+ * needed for a secondary cpu after a cold reset e.g
+ * mark the cpu's presence, mechanism to place it in a
+ * holding pen etc.
+ * -----------------------------------------------------
+ */
+func plat_secondary_cold_boot_setup
+ /* Wait until the it gets reset signal from rstmgr gets populated */
+poll_mailbox:
+ wfi
+
+ adr x0, stratix10_sec_entry
+ ldr x1, [x0]
+ adr x2, cpuid_release
+ ldr x3, [x2]
+ mrs x4, mpidr_el1
+ and x4, x4, #0xff
+ cmp x3, x4
+ b.ne poll_mailbox
+ br x1
+endfunc plat_secondary_cold_boot_setup
+
+func platform_is_primary_cpu
+ and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+ cmp x0, #PLAT_PRIMARY_CPU
+ cset x0, eq
+ ret
+endfunc platform_is_primary_cpu
+
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ b platform_is_primary_cpu
+endfunc plat_is_my_cpu_primary
+
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+endfunc plat_my_core_pos
+
+func plat_get_my_entrypoint
+ adr x1,stratix10_sec_entry
+ ldr x0, [x1]
+ ret
+endfunc plat_get_my_entrypoint
+
+ /* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ * Function to initialize the crash console
+ * without a C Runtime to print crash report.
+ * Clobber list : x0, x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+ mov_imm x0, PLAT_UART0_BASE
+ mov_imm x1, PLAT_UART_CLOCK
+ mov_imm x2, PLAT_BAUDRATE
+ b console_16550_core_init
+endfunc plat_crash_console_init
+
+ /* ---------------------------------------------
+ * int plat_crash_console_putc(void)
+ * Function to print a character on the crash
+ * console without a C Runtime.
+ * Clobber list : x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_putc
+ mov_imm x1, PLAT_UART0_BASE
+ b console_16550_core_putc
+endfunc plat_crash_console_putc
+
+func plat_crash_console_flush
+ mov_imm x0, CRASH_CONSOLE_BASE
+ b console_16550_core_flush
+endfunc plat_crash_console_flush
+
+
+ /* --------------------------------------------------------
+ * void platform_mem_init (void);
+ *
+ * Any memory init, relocation to be done before the
+ * platform boots. Called very early in the boot process.
+ * --------------------------------------------------------
+ */
+func platform_mem_init
+ mov x0, #0
+ ret
+endfunc platform_mem_init
+
+
+ .data
+ .align 3
+
+stratix10_sec_entry:
+ .quad 0
+
+cpuid_release:
+ .quad 0
+
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
+}
+
+unsigned long plat_get_ns_image_entrypoint(void)
+{
+ return PLAT_NS_IMAGE_OFFSET;
+}
+
+/******************************************************************************
+ * Gets SPSR for BL32 entry
+ *****************************************************************************/
+uint32_t plat_get_spsr_for_bl32_entry(void)
+{
+ /*
+ * The Secure Payload Dispatcher service is responsible for
+ * setting the SPSR prior to entry into the BL32 image.
+ */
+ return 0;
+}
+
+/******************************************************************************
+ * Gets SPSR for BL33 entry
+ *****************************************************************************/
+uint32_t plat_get_spsr_for_bl33_entry(void)
+{
+ unsigned long el_status;
+ unsigned int mode;
+ uint32_t spsr;
+
+ /* Figure out what mode we enter the non-secure world in */
+ el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
+ el_status &= ID_AA64PFR0_ELX_MASK;
+
+ mode = (el_status) ? MODE_EL2 : MODE_EL1;
+
+ /*
+ * TODO: Consider the possibility of specifying the SPSR in
+ * the FIP ToC and allowing the platform to have a say as
+ * well.
+ */
+ spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+ return spsr;
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __S10_PRIVATE_H__
+#define __S10_PRIVATE_H__
+
+#define S10_MMC_REG_BASE 0xff808000
+
+#define EMMC_DESC_SIZE (1<<20)
+#define EMMC_INIT_PARAMS(base) \
+ { .bus_width = MMC_BUS_WIDTH_4, \
+ .clk_rate = 50000000, \
+ .desc_base = (base), \
+ .desc_size = EMMC_DESC_SIZE, \
+ .flags = 0, \
+ .reg_base = S10_MMC_REG_BASE, \
+ \
+ }
+
+typedef enum {
+ BOOT_SOURCE_FPGA = 0,
+ BOOT_SOURCE_SDMMC,
+ BOOT_SOURCE_NAND,
+ BOOT_SOURCE_RSVD,
+ BOOT_SOURCE_QSPI,
+} boot_source_type;
+
+void enable_nonsecure_access(void);
+void stratix10_io_setup(void);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+#include <platform_def.h>
+#include <plat/common/platform.h>
+
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+#ifdef SCP_BL2_BASE
+ /* Fill SCP_BL2 related information if it exists */
+ {
+ .image_id = SCP_BL2_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = SCP_BL2_BASE,
+ .image_info.image_max_size = SCP_BL2_SIZE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+#endif /* SCP_BL2_BASE */
+
+#ifdef EL3_PAYLOAD_BASE
+ /* Fill EL3 payload related information (BL31 is EL3 payload)*/
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = EL3_PAYLOAD_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+#else /* EL3_PAYLOAD_BASE */
+
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL31_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+ .image_info.image_base = BL31_BASE,
+ .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+#endif /* EL3_PAYLOAD_BASE */
+
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+ .ep_info.pc = PLAT_NS_IMAGE_OFFSET,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = PLAT_NS_IMAGE_OFFSET,
+ .image_info.image_max_size =
+ 0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <drivers/arm/gicv2.h>
+
+#include <drivers/generic_delay_timer.h>
+#include <drivers/console.h>
+#include <drivers/ti/uart/uart_16550.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <errno.h>
+#include <drivers/io/io_storage.h>
+#include <common/image_decompress.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <platform_private.h>
+#include <drivers/synopsys/dw_mmc.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables.h>
+
+#include "s10_memory_controller.h"
+#include "s10_reset_manager.h"
+#include "s10_clock_manager.h"
+#include "s10_handoff.h"
+#include "s10_pinmux.h"
+#include "aarch64/stratix10_private.h"
+
+const mmap_region_t plat_stratix10_mmap[] = {
+ MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
+ MT_NON_CACHEABLE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ {0},
+};
+
+boot_source_type boot_source;
+
+void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
+ u_register_t x2, u_register_t x4)
+{
+ static console_16550_t console;
+ handoff reverse_handoff_ptr;
+
+ generic_delay_timer_init();
+
+ if (s10_get_handoff(&reverse_handoff_ptr))
+ return;
+ config_pinmux(&reverse_handoff_ptr);
+ boot_source = reverse_handoff_ptr.boot_source;
+
+ config_clkmgr_handoff(&reverse_handoff_ptr);
+ enable_nonsecure_access();
+ deassert_peripheral_reset();
+ config_hps_hs_before_warm_reset();
+
+ console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
+ &console);
+
+ plat_delay_timer_init();
+ init_hard_memory_controller();
+}
+
+
+void bl2_el3_plat_arch_setup(void)
+{
+
+ struct mmc_device_info info;
+ const mmap_region_t bl_regions[] = {
+ MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
+ MT_MEMORY | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
+ MT_CODE | MT_SECURE),
+ MAP_REGION_FLAT(BL_RO_DATA_BASE,
+ BL_RO_DATA_END - BL_RO_DATA_BASE,
+ MT_RO_DATA | MT_SECURE),
+#if USE_COHERENT_MEM_BAR
+ MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+#endif
+ {0},
+ };
+
+ setup_page_tables(bl_regions, plat_stratix10_mmap);
+
+ enable_mmu_el3(0);
+
+ /* ECC Scrubbing */
+ memset(0, DRAM_BASE, DRAM_SIZE);
+
+ dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
+
+ info.mmc_dev_type = MMC_IS_SD;
+
+ switch (boot_source) {
+ case BOOT_SOURCE_SDMMC:
+ dw_mmc_init(¶ms, &info);
+ stratix10_io_setup();
+ break;
+ default:
+ ERROR("Unsupported boot source\n");
+ panic();
+ break;
+ }
+}
+
+uint32_t get_spsr_for_bl33_entry(void)
+{
+ unsigned long el_status;
+ unsigned int mode;
+ uint32_t spsr;
+
+ /* Figure out what mode we enter the non-secure world in */
+ el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
+ el_status &= ID_AA64PFR0_ELX_MASK;
+
+ mode = (el_status) ? MODE_EL2 : MODE_EL1;
+
+ /*
+ * TODO: Consider the possibility of specifying the SPSR in
+ * the FIP ToC and allowing the platform to have a say as
+ * well.
+ */
+ spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+ return spsr;
+}
+
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+ bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+
+ switch (image_id) {
+ case BL33_IMAGE_ID:
+ bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
+ bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+/*******************************************************************************
+ * Perform any BL3-1 platform setup code
+ ******************************************************************************/
+void bl2_platform_setup(void)
+{
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_MACROS_S__
+#define __PLAT_MACROS_S__
+
+#include <platform_def.h>
+
+ /* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ mov_imm x17, PLAT_GICC_BASE
+ mov_imm x16, PLAT_GICD_BASE
+ arm_print_gic_regs
+ .endm
+
+#endif /* __PLAT_MACROS_S__ */
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLATFORM_PRIVATE_H__
+#define __PLATFORM_PRIVATE_H__
+#include <common/bl_common.h>
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_configure_mmu_el3(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long ro_start,
+ unsigned long ro_limit,
+ unsigned long coh_start,
+ unsigned long coh_limit);
+
+
+void plat_configure_mmu_el1(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long ro_start,
+ unsigned long ro_limit,
+ unsigned long coh_start,
+ unsigned long coh_limit);
+
+void plat_gic_driver_init(void);
+
+void plat_arm_gic_init(void);
+
+void plat_delay_timer_init(void);
+
+unsigned long plat_get_ns_image_entrypoint(void);
+
+uint32_t plat_get_spsr_for_bl32_entry(void);
+
+uint32_t plat_get_spsr_for_bl33_entry(void);
+
+#endif /* __PLATFORM_PRIVATE_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __CLOCKMANAGER_H__
+#define __CLOCKMANAGER_H__
+
+#include "s10_handoff.h"
+
+#define ALT_CLKMGR 0xffd10000
+
+#define ALT_CLKMGR_CTRL 0x0
+#define ALT_CLKMGR_STAT 0x4
+#define ALT_CLKMGR_INTRCLR 0x14
+#define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004
+#define ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008
+
+#define ALT_CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001
+#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1
+#define ALT_CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0)
+#define ALT_CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8)
+#define ALT_CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00000200) >> 9)
+
+#define ALT_CLKMGR_MAINPLL 0xffd10030
+#define ALT_CLKMGR_MAINPLL_EN 0x0
+#define ALT_CLKMGR_MAINPLL_BYPASS 0xc
+#define ALT_CLKMGR_MAINPLL_MPUCLK 0x18
+#define ALT_CLKMGR_MAINPLL_NOCCLK 0x1c
+#define ALT_CLKMGR_MAINPLL_CNTR2CLK 0x20
+#define ALT_CLKMGR_MAINPLL_CNTR3CLK 0x24
+#define ALT_CLKMGR_MAINPLL_CNTR4CLK 0x28
+#define ALT_CLKMGR_MAINPLL_CNTR5CLK 0x2c
+#define ALT_CLKMGR_MAINPLL_CNTR6CLK 0x30
+#define ALT_CLKMGR_MAINPLL_CNTR7CLK 0x34
+#define ALT_CLKMGR_MAINPLL_CNTR8CLK 0x38
+#define ALT_CLKMGR_MAINPLL_CNTR9CLK 0x3c
+#define ALT_CLKMGR_MAINPLL_NOCDIV 0x40
+#define ALT_CLKMGR_MAINPLL_PLLGLOB 0x44
+#define ALT_CLKMGR_MAINPLL_FDBCK 0x48
+#define ALT_CLKMGR_MAINPLL_PLLC0 0x54
+#define ALT_CLKMGR_MAINPLL_PLLC1 0x58
+#define ALT_CLKMGR_MAINPLL_VCOCALIB 0x5c
+#define ALT_CLKMGR_MAINPLL_EN_RESET 0x000000ff
+#define ALT_CLKMGR_MAINPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24)
+#define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK 0x00000001
+#define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
+#define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK 0x00000002
+#define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff)
+#define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00)
+
+#define ALT_CLKMGR_PERPLL 0xffd100a4
+#define ALT_CLKMGR_PERPLL_EN 0x0
+#define ALT_CLKMGR_PERPLL_BYPASS 0xc
+#define ALT_CLKMGR_PERPLL_CNTR2CLK 0x18
+#define ALT_CLKMGR_PERPLL_CNTR3CLK 0x1c
+#define ALT_CLKMGR_PERPLL_CNTR4CLK 0x20
+#define ALT_CLKMGR_PERPLL_CNTR5CLK 0x24
+#define ALT_CLKMGR_PERPLL_CNTR6CLK 0x28
+#define ALT_CLKMGR_PERPLL_CNTR7CLK 0x2c
+#define ALT_CLKMGR_PERPLL_CNTR8CLK 0x30
+#define ALT_CLKMGR_PERPLL_CNTR9CLK 0x34
+#define ALT_CLKMGR_PERPLL_GPIODIV 0x3c
+#define ALT_CLKMGR_PERPLL_EMACCTL 0x38
+#define ALT_CLKMGR_PERPLL_PLLGLOB 0x40
+#define ALT_CLKMGR_PERPLL_FDBCK 0x44
+#define ALT_CLKMGR_PERPLL_PLLC0 0x50
+#define ALT_CLKMGR_PERPLL_PLLC1 0x54
+#define ALT_CLKMGR_PERPLL_EN_RESET 0x00000fff
+#define ALT_CLKMGR_PERPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24)
+#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff)
+#define ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001
+#define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
+#define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_SET(x) (((x) << 8) & 0x00003f00)
+#define ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002
+#define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff)
+#define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00)
+#define ALT_CLKMGR_PERPLL_VCOCALIB 0x58
+
+void config_clkmgr_handoff(handoff *hoff_ptr);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HANDOFF_H_
+#define _HANDOFF_H_
+
+#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
+#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
+#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
+#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
+#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
+#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
+#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
+
+typedef struct handoff_t {
+ /* header */
+ uint32_t header_magic;
+ uint32_t header_device;
+ uint32_t _pad_0x08_0x10[2];
+
+ /* pinmux configuration - select */
+ uint32_t pinmux_sel_magic;
+ uint32_t pinmux_sel_length;
+ uint32_t _pad_0x18_0x20[2];
+ uint32_t pinmux_sel_array[96]; /* offset, value */
+
+ /* pinmux configuration - io control */
+ uint32_t pinmux_io_magic;
+ uint32_t pinmux_io_length;
+ uint32_t _pad_0x1a8_0x1b0[2];
+ uint32_t pinmux_io_array[96]; /* offset, value */
+
+ /* pinmux configuration - use fpga switch */
+ uint32_t pinmux_fpga_magic;
+ uint32_t pinmux_fpga_length;
+ uint32_t _pad_0x338_0x340[2];
+ uint32_t pinmux_fpga_array[42]; /* offset, value */
+ uint32_t _pad_0x3e8_0x3f0[2];
+
+ /* pinmux configuration - io delay */
+ uint32_t pinmux_delay_magic;
+ uint32_t pinmux_delay_length;
+ uint32_t _pad_0x3f8_0x400[2];
+ uint32_t pinmux_iodelay_array[96]; /* offset, value */
+
+ /* clock configuration */
+ uint32_t clock_magic;
+ uint32_t clock_length;
+ uint32_t _pad_0x588_0x590[2];
+ uint32_t main_pll_mpuclk;
+ uint32_t main_pll_nocclk;
+ uint32_t main_pll_cntr2clk;
+ uint32_t main_pll_cntr3clk;
+ uint32_t main_pll_cntr4clk;
+ uint32_t main_pll_cntr5clk;
+ uint32_t main_pll_cntr6clk;
+ uint32_t main_pll_cntr7clk;
+ uint32_t main_pll_cntr8clk;
+ uint32_t main_pll_cntr9clk;
+ uint32_t main_pll_nocdiv;
+ uint32_t main_pll_pllglob;
+ uint32_t main_pll_fdbck;
+ uint32_t main_pll_pllc0;
+ uint32_t main_pll_pllc1;
+ uint32_t _pad_0x5cc_0x5d0[1];
+ uint32_t per_pll_cntr2clk;
+ uint32_t per_pll_cntr3clk;
+ uint32_t per_pll_cntr4clk;
+ uint32_t per_pll_cntr5clk;
+ uint32_t per_pll_cntr6clk;
+ uint32_t per_pll_cntr7clk;
+ uint32_t per_pll_cntr8clk;
+ uint32_t per_pll_cntr9clk;
+ uint32_t per_pll_emacctl;
+ uint32_t per_pll_gpiodiv;
+ uint32_t per_pll_pllglob;
+ uint32_t per_pll_fdbck;
+ uint32_t per_pll_pllc0;
+ uint32_t per_pll_pllc1;
+ uint32_t hps_osc_clk_h;
+ uint32_t fpga_clk_hz;
+
+ /* misc configuration */
+ uint32_t misc_magic;
+ uint32_t misc_length;
+ uint32_t _pad_0x618_0x620[2];
+ uint32_t boot_source;
+} handoff;
+
+int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
+int s10_get_handoff(handoff *hoff_ptr);
+
+#endif
+
+
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __S10_MEMORYCONTROLLER_H__
+#define __S10_MEMORYCONTROLLER_H__
+
+#define S10_MPFE_IOHMC_REG_DRAMADDRW 0xf80100a8
+#define S10_MPFE_IOHMC_CTRLCFG0 0xf8010028
+#define S10_MPFE_IOHMC_CTRLCFG1 0xf801002c
+#define S10_MPFE_IOHMC_DRAMADDRW 0xf80100a8
+#define S10_MPFE_IOHMC_DRAMTIMING0 0xf8010050
+#define S10_MPFE_IOHMC_CALTIMING0 0xf801007c
+#define S10_MPFE_IOHMC_CALTIMING1 0xf8010080
+#define S10_MPFE_IOHMC_CALTIMING2 0xf8010084
+#define S10_MPFE_IOHMC_CALTIMING3 0xf8010088
+#define S10_MPFE_IOHMC_CALTIMING4 0xf801008c
+#define S10_MPFE_IOHMC_CALTIMING9 0xf80100a0
+#define S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0)
+#define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \
+ (((value) & 0x00000060) >> 5)
+
+#define S10_RSTMGR_BRGMODRST 0xffd1102c
+#define S10_RSTMGR_BRGMODRST_DDRSCH 0x00000040
+
+#define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
+#define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
+#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218
+#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff
+#define S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214
+
+
+#define S10_MPFE_IOHMC_REG_CTRLCFG1 0xf801002c
+
+#define S10_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0xf8010110
+
+#define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0)
+#define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5)
+#define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16)
+#define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14)
+#define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10)
+
+#define S10_MPFE_DDR(x) (0xf8000000 + x)
+#define S10_MPFE_HMC_ADP_DDRCALSTAT 0xf801100c
+#define S10_MPFE_DDR_MAIN_SCHED 0xf8000400
+#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF 0xf8000408
+#define S10_MPFE_DDR_MAIN_SCHED_DDRTIMING 0xf800040c
+#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f
+#define S10_MPFE_DDR_MAIN_SCHED_DDRMODE 0xf8000410
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV 0xf800043c
+#define S10_MPFE_DDR_MAIN_SCHED_READLATENCY 0xf8000414
+#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE 0xf8000438
+#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10
+#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST 4
+#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST 0
+#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f)
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST 0
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST 2
+#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST 4
+
+#define S10_MPFE_HMC_ADP(x) (0xf8011000 + (x))
+#define S10_MPFE_HMC_ADP_HPSINTFCSEL 0xf8011210
+#define S10_MPFE_HMC_ADP_DDRIOCTRL 0xf8011008
+#define HMC_ADP_DDRIOCTRL 0x8
+#define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
+#define HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(x) (((x) & 0x00003e00) >> 9)
+#define ADP_DRAMADDRWIDTH 0xe0
+
+#define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18)
+#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12)
+#define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0)
+#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12)
+
+/* timing 2 */
+#define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6)
+#define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24)
+#define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18)
+#define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6)
+
+/* timing 3 */
+#define CALTIMING3_WR_TO_RD_DIFF_CHIP(value) (((value) & 0x0003f000) >> 12)
+#define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6)
+
+/* timing 4 */
+#define PCH_TO_VALID(value) (((value) & 0x00000fc0) >> 6)
+
+#define DDRTIMING_BWRATIO_OFST 31
+#define DDRTIMING_WRTORD_OFST 26
+#define DDRTIMING_RDTOWR_OFST 21
+#define DDRTIMING_BURSTLEN_OFST 18
+#define DDRTIMING_WRTOMISS_OFST 12
+#define DDRTIMING_RDTOMISS_OFST 6
+#define DDRTIMING_ACTTOACT_OFST 0
+
+#define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
+
+#define DDRMODE_AUTOPRECHARGE_OFST 1
+#define DDRMODE_BWRATIOEXTENDED_OFST 0
+
+
+#define S10_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x0000007f) >> 0)
+#define S10_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(x) (((x) & 0x0000000f) >> 0)
+
+#define S10_CCU_CPU0_MPRT_DDR 0xf7004400
+#define S10_CCU_CPU0_MPRT_MEM0 0xf70045c0
+#define S10_CCU_CPU0_MPRT_MEM1A 0xf70045e0
+#define S10_CCU_CPU0_MPRT_MEM1B 0xf7004600
+#define S10_CCU_CPU0_MPRT_MEM1C 0xf7004620
+#define S10_CCU_CPU0_MPRT_MEM1D 0xf7004640
+#define S10_CCU_CPU0_MPRT_MEM1E 0xf7004660
+#define S10_CCU_IOM_MPRT_MEM0 0xf7018560
+#define S10_CCU_IOM_MPRT_MEM1A 0xf7018580
+#define S10_CCU_IOM_MPRT_MEM1B 0xf70185a0
+#define S10_CCU_IOM_MPRT_MEM1C 0xf70185c0
+#define S10_CCU_IOM_MPRT_MEM1D 0xf70185e0
+#define S10_CCU_IOM_MPRT_MEM1E 0xf7018600
+
+#define S10_NOC_FW_DDR_SCR 0xf8020100
+#define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0xf802011c
+#define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT 0xf8020118
+#define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0xf802019c
+#define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0xf8020198
+
+#define S10_SOC_NOC_FW_DDR_SCR_ENABLE 0xf8020100
+#define S10_CCU_NOC_DI_SET_MSK 0x10
+
+#define S10_SYSMGR_CORE_HMC_CLK 0xffd120b4
+#define S10_SYSMGR_CORE_HMC_CLK_STATUS 0x00000001
+
+#define S10_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(x) (((x) & 0x0000ffff) >> 0)
+#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK 0x00000003
+#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST 0
+#define S10_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE 0x001f1f1f
+#define S10_IOHMC_CTRLCFG1_ENABLE_ECC_OFST 7
+
+#define S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000
+#define S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100
+#define S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001
+
+#define S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001
+#define S10_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000
+#define S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100
+#define S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(value) (((value) & 0x00000001) >> 0)
+
+
+#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
+#define IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10)
+#define IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14)
+#define IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0)
+#define IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16)
+#define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5)
+
+#define S10_SDRAM_0_LB_ADDR 0x0
+
+int init_hard_memory_controller(void);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define AXI_AP (1<<0)
+#define FPGA2SOC (1<<16)
+#define MPU (1<<24)
+#define S10_NOC_PER_SCR_NAND 0xffd21000
+#define S10_NOC_PER_SCR_NAND_DATA 0xffd21004
+#define S10_NOC_PER_SCR_USB0 0xffd2100c
+#define S10_NOC_PER_SCR_USB1 0xffd21010
+#define S10_NOC_PER_SCR_SPI_M0 0xffd2101c
+#define S10_NOC_PER_SCR_SPI_M1 0xffd21020
+#define S10_NOC_PER_SCR_SPI_S0 0xffd21024
+#define S10_NOC_PER_SCR_SPI_S1 0xffd21028
+#define S10_NOC_PER_SCR_EMAC0 0xffd2102c
+#define S10_NOC_PER_SCR_EMAC1 0xffd21030
+#define S10_NOC_PER_SCR_EMAC2 0xffd21034
+#define S10_NOC_PER_SCR_SDMMC 0xffd21040
+#define S10_NOC_PER_SCR_GPIO0 0xffd21044
+#define S10_NOC_PER_SCR_GPIO1 0xffd21048
+#define S10_NOC_PER_SCR_I2C0 0xffd21050
+#define S10_NOC_PER_SCR_I2C1 0xffd21058
+#define S10_NOC_PER_SCR_I2C2 0xffd2105c
+#define S10_NOC_PER_SCR_I2C3 0xffd21060
+#define S10_NOC_PER_SCR_SP_TIMER0 0xffd21064
+#define S10_NOC_PER_SCR_SP_TIMER1 0xffd21068
+#define S10_NOC_PER_SCR_UART0 0xffd2106c
+#define S10_NOC_PER_SCR_UART1 0xffd21070
+
+
+#define S10_NOC_SYS_SCR_DMA_ECC 0xffd21108
+#define S10_NOC_SYS_SCR_EMAC0RX_ECC 0xffd2110c
+#define S10_NOC_SYS_SCR_EMAC0TX_ECC 0xffd21110
+#define S10_NOC_SYS_SCR_EMAC1RX_ECC 0xffd21114
+#define S10_NOC_SYS_SCR_EMAC1TX_ECC 0xffd21118
+#define S10_NOC_SYS_SCR_EMAC2RX_ECC 0xffd2111c
+#define S10_NOC_SYS_SCR_EMAC2TX_ECC 0xffd21120
+#define S10_NOC_SYS_SCR_NAND_ECC 0xffd2112c
+#define S10_NOC_SYS_SCR_NAND_READ_ECC 0xffd21130
+#define S10_NOC_SYS_SCR_NAND_WRITE_ECC 0xffd21134
+#define S10_NOC_SYS_SCR_OCRAM_ECC 0xffd21138
+#define S10_NOC_SYS_SCR_SDMMC_ECC 0xffd21140
+#define S10_NOC_SYS_SCR_USB0_ECC 0xffd21144
+#define S10_NOC_SYS_SCR_USB1_ECC 0xffd21148
+#define S10_NOC_SYS_SCR_CLK_MGR 0xffd2114c
+#define S10_NOC_SYS_SCR_IO_MGR 0xffd21154
+#define S10_NOC_SYS_SCR_RST_MGR 0xffd21158
+#define S10_NOC_SYS_SCR_SYS_MGR 0xffd2115c
+#define S10_NOC_SYS_SCR_OSC0_TIMER 0xffd21160
+#define S10_NOC_SYS_SCR_OSC1_TIMER 0xffd21164
+#define S10_NOC_SYS_SCR_WATCHDOG0 0xffd21168
+#define S10_NOC_SYS_SCR_WATCHDOG1 0xffd2116c
+#define S10_NOC_SYS_SCR_WATCHDOG2 0xffd21170
+#define S10_NOC_SYS_SCR_WATCHDOG3 0xffd21174
+#define S10_NOC_SYS_SCR_DAP 0xffd21178
+#define S10_NOC_SYS_SCR_L4_NOC_PROBES 0xffd21190
+#define S10_NOC_SYS_SCR_L4_NOC_QOS 0xffd21194
+
+#define S10_CCU_NOC_BRIDGE_CPU0_RAM 0xf7004688
+#define S10_CCU_NOC_BRIDGE_IOM_RAM 0xf7004688
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __S10_PINMUX_H__
+#define __S10_PINMUX_H__
+
+#define S10_PINMUX_PIN0SEL 0xffd13000
+#define S10_PINMUX_IO0CTRL 0xffd13130
+#define S10_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300
+#define S10_PINMUX_IO0_DELAY 0xffd13400
+
+#include "s10_handoff.h"
+
+void config_pinmux(handoff *handoff);
+
+#endif
+
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __S10_RESETMANAGER_H__
+#define __S10_RESETMANAGER_H__
+
+#define S10_RSTMGR_PER0MODRST 0xffd11024
+#define S10_RSTMGR_PER1MODRST 0xffd11028
+#define S10_RSTMGR_HDSKEN 0xffd11010
+
+#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
+#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
+#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
+#define S10_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
+#define S10_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
+#define S10_RSTMGR_PER0MODRST_DMAOCP 0x00200000
+#define S10_RSTMGR_PER0MODRST_DMA 0x00010000
+#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
+#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
+#define S10_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
+#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
+#define S10_RSTMGR_PER0MODRST_EMACPTP 0x00400000
+#define S10_RSTMGR_PER0MODRST_NANDOCP 0x00002000
+#define S10_RSTMGR_PER0MODRST_NAND 0x00000020
+#define S10_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
+#define S10_RSTMGR_PER0MODRST_SDMMC 0x00000080
+#define S10_RSTMGR_PER0MODRST_SPIM0 0x00020000
+#define S10_RSTMGR_PER0MODRST_SPIM1 0x00040000
+#define S10_RSTMGR_PER0MODRST_SPIS0 0x00080000
+#define S10_RSTMGR_PER0MODRST_SPIS1 0x00100000
+#define S10_RSTMGR_PER0MODRST_USB0OCP 0x00000800
+#define S10_RSTMGR_PER0MODRST_USB0 0x00000008
+#define S10_RSTMGR_PER0MODRST_USB1OCP 0x00001000
+#define S10_RSTMGR_PER0MODRST_USB1 0x00000010
+
+#define S10_RSTMGR_PER1MODRST_WATCHDOG0 0x1
+#define S10_RSTMGR_PER1MODRST_WATCHDOG1 0x2
+#define S10_RSTMGR_PER1MODRST_WATCHDOG2 0x4
+#define S10_RSTMGR_PER1MODRST_WATCHDOG3 0x8
+#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
+#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
+#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
+#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
+#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
+#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
+#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
+#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
+#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
+#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
+#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
+#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
+#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
+#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
+#define S10_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
+#define S10_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
+#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
+#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
+#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
+#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
+#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
+#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
+#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
+#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
+#define S10_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
+#define S10_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
+#define S10_RSTMGR_HDSKEN_FPGAHSEN 0x00000004
+#define S10_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
+#define S10_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
+
+#define S10_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
+#define S10_RSTMGR_PER0MODRST_DMAIF0 0x01000000
+#define S10_RSTMGR_PER0MODRST_DMAIF1 0x02000000
+#define S10_RSTMGR_PER0MODRST_DMAIF2 0x04000000
+#define S10_RSTMGR_PER0MODRST_DMAIF3 0x08000000
+#define S10_RSTMGR_PER0MODRST_DMAIF4 0x10000000
+#define S10_RSTMGR_PER0MODRST_DMAIF5 0x20000000
+#define S10_RSTMGR_PER0MODRST_DMAIF6 0x40000000
+#define S10_RSTMGR_PER0MODRST_DMAIF7 0x80000000
+
+void deassert_peripheral_reset(void);
+void config_hps_hs_before_warm_reset(void);
+
+#endif
+
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
+#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
+#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
+#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010
+#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c
+#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020
+#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024
+#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028
+#define S10_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c
+#define S10_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030
+#define S10_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034
+#define S10_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040
+#define S10_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044
+#define S10_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048
+#define S10_NOC_FW_L4_PER_SCR_I2C0 0xffd21050
+#define S10_NOC_FW_L4_PER_SCR_I2C1 0xffd21054
+#define S10_NOC_FW_L4_PER_SCR_I2C2 0xffd21058
+#define S10_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c
+#define S10_NOC_FW_L4_PER_SCR_I2C4 0xffd21060
+#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064
+#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068
+#define S10_NOC_FW_L4_PER_SCR_UART0 0xffd2106c
+#define S10_NOC_FW_L4_PER_SCR_UART1 0xffd21070
+
+#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108
+#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c
+#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110
+#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114
+#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118
+#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c
+#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120
+#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c
+#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130
+#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134
+#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138
+#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140
+#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144
+#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148
+#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c
+#define S10_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154
+#define S10_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158
+#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c
+#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160
+#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164
+#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168
+#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c
+#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170
+#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174
+#define S10_NOC_FW_L4_SYS_SCR_DAP 0xffd21178
+#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190
+#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194
+
+#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
+#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
+
+#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
+
+void enable_nonsecure_access(void);
+
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <arch_helpers.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#define S10_GLOBAL_TIMER 0xffd01000
+#define S10_GLOBAL_TIMER_EN 0x3
+
+/********************************************************************
+ * The timer delay function
+ ********************************************************************/
+static uint32_t plat_get_timer_value(void)
+{
+ /*
+ * Generic delay timer implementation expects the timer to be a down
+ * counter. We apply bitwise NOT operator to the tick values returned
+ * by read_cntpct_el0() to simulate the down counter. The value is
+ * clipped from 64 to 32 bits.
+ */
+ return (uint32_t)(~read_cntpct_el0());
+}
+
+static const timer_ops_t plat_timer_ops = {
+ .get_timer_value = plat_get_timer_value,
+ .clk_mult = 1,
+ .clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ,
+};
+
+void plat_delay_timer_init(void)
+{
+ timer_init(&plat_timer_ops);
+ mmio_write_32(S10_GLOBAL_TIMER, S10_GLOBAL_TIMER_EN);
+}
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/mmc.h>
+#include <tools_share/firmware_image_package.h>
+#include <drivers/io/io_block.h>
+#include <drivers/io/io_driver.h>
+#include <drivers/io/io_fip.h>
+#include <drivers/io/io_memmap.h>
+#include <drivers/io/io_storage.h>
+#include <lib/mmio.h>
+#include <drivers/partition/partition.h>
+#include <lib/semihosting.h>
+#include <string.h>
+#include <lib/utils.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include "platform_def.h"
+
+#define STRATIX10_FIP_BASE (0)
+#define STRATIX10_FIP_MAX_SIZE (0x1000000)
+#define STRATIX10_MMC_DATA_BASE (0xffe3c000)
+#define STRATIX10_MMC_DATA_SIZE (0x2000)
+
+static const io_dev_connector_t *mmc_dev_con;
+static const io_dev_connector_t *fip_dev_con;
+
+static uintptr_t fip_dev_handle;
+static uintptr_t mmc_dev_handle;
+
+static const io_uuid_spec_t bl2_uuid_spec = {
+ .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
+};
+
+static const io_uuid_spec_t bl31_uuid_spec = {
+ .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
+};
+
+static const io_uuid_spec_t bl33_uuid_spec = {
+ .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
+};
+
+uintptr_t a2_lba_offset;
+
+static const io_block_spec_t gpt_block_spec = {
+ .offset = 0,
+ .length = MMC_BLOCK_SIZE
+};
+
+static int check_mmc(const uintptr_t spec);
+static int check_fip(const uintptr_t spec);
+
+static io_block_spec_t mmc_fip_spec = {
+ .offset = STRATIX10_FIP_BASE,
+ .length = STRATIX10_FIP_MAX_SIZE,
+};
+
+const char a2[] = {0xa2, 0x0};
+
+static const io_block_dev_spec_t mmc_dev_spec = {
+ .buffer = {
+ .offset = STRATIX10_MMC_DATA_BASE,
+ .length = MMC_BLOCK_SIZE,
+ },
+
+ .ops = {
+ .read = mmc_read_blocks,
+ .write = mmc_write_blocks,
+ },
+
+ .block_size = MMC_BLOCK_SIZE,
+};
+
+struct plat_io_policy {
+ uintptr_t *dev_handle;
+ uintptr_t image_spec;
+ int (*check)(const uintptr_t spec);
+};
+
+static const struct plat_io_policy policies[] = {
+ [FIP_IMAGE_ID] = {
+ &mmc_dev_handle,
+ (uintptr_t)&mmc_fip_spec,
+ check_mmc
+ },
+ [BL2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl2_uuid_spec,
+ check_fip
+ },
+ [BL31_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl31_uuid_spec,
+ check_fip
+ },
+ [BL33_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t) &bl33_uuid_spec,
+ check_fip
+ },
+ [GPT_IMAGE_ID] = {
+ &mmc_dev_handle,
+ (uintptr_t) &gpt_block_spec,
+ check_mmc
+ },
+};
+
+static int check_mmc(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_handle;
+
+ result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
+ if (result == 0) {
+ result = io_open(mmc_dev_handle, spec, &local_handle);
+ if (result == 0)
+ io_close(local_handle);
+ }
+ return result;
+}
+
+static int check_fip(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_image_handle;
+
+ result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
+ if (result == 0) {
+ result = io_open(fip_dev_handle, spec, &local_image_handle);
+ if (result == 0)
+ io_close(local_image_handle);
+ }
+ return result;
+}
+
+void stratix10_io_setup(void)
+{
+ int result;
+
+ result = register_io_dev_block(&mmc_dev_con);
+ assert(result == 0);
+
+ result = register_io_dev_fip(&fip_dev_con);
+ assert(result == 0);
+
+ result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
+ &mmc_dev_handle);
+ assert(result == 0);
+
+ result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle);
+ assert(result == 0);
+
+ partition_init(GPT_IMAGE_ID);
+
+ mmc_fip_spec.offset = get_partition_entry(a2)->start;
+
+ (void)result;
+}
+
+int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
+ uintptr_t *image_spec)
+{
+ int result;
+ const struct plat_io_policy *policy;
+
+ assert(image_id < ARRAY_SIZE(policies));
+
+ policy = &policies[image_id];
+ result = policy->check(policy->image_spec);
+ assert(result == 0);
+
+ *image_spec = policy->image_spec;
+ *dev_handle = *(policy->dev_handle);
+
+ return result;
+}
--- /dev/null
+#
+# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PLAT_INCLUDES := \
+ -Iplat/intel/soc/stratix10/ \
+ -Iplat/intel/soc/stratix10/include/ \
+
+PLAT_BL_COMMON_SOURCES := \
+ lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
+ drivers/arm/gic/common/gic_common.c \
+ drivers/arm/gic/v2/gicv2_main.c \
+ drivers/arm/gic/v2/gicv2_helpers.c \
+ plat/common/plat_gicv2.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/ti/uart/aarch64/16550_console.S \
+ plat/intel/soc/stratix10/aarch64/platform_common.c \
+ plat/intel/soc/stratix10/aarch64/plat_helpers.S \
+
+BL2_SOURCES += \
+ drivers/partition/partition.c \
+ drivers/partition/gpt.c \
+ drivers/arm/pl061/pl061_gpio.c \
+ drivers/mmc/mmc.c \
+ drivers/synopsys/emmc/dw_mmc.c \
+ drivers/io/io_storage.c \
+ drivers/io/io_block.c \
+ drivers/io/io_fip.c \
+ drivers/gpio/gpio.c \
+ drivers/io/io_memmap.c \
+ plat/intel/soc/stratix10/bl2_plat_setup.c \
+ plat/intel/soc/stratix10/plat_storage.c \
+ plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c \
+ plat/intel/soc/stratix10/soc/s10_reset_manager.c \
+ plat/intel/soc/stratix10/soc/s10_handoff.c \
+ plat/intel/soc/stratix10/soc/s10_clock_manager.c \
+ plat/intel/soc/stratix10/soc/s10_pinmux.c \
+ plat/intel/soc/stratix10/soc/s10_memory_controller.c \
+ plat/intel/soc/stratix10/plat_delay_timer.c \
+ lib/cpus/aarch64/cortex_a53.S \
+ plat/intel/soc/stratix10/stratix10_image_load.c \
+ plat/intel/soc/stratix10/soc/s10_system_manager.c \
+ common/desc_image_load.c
+
+# plat/intel/soc/stratix10/plat_topology.c \
+
+PROGRAMMABLE_RESET_ADDRESS := 0
+BL2_AT_EL3 := 1
+MULTI_CONSOLE_API := 1
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <arch.h>
+#include <common/bl_common.h>
+#include <common/interrupt_props.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <drivers/arm/gic_common.h>
+#include <plat/common/common_def.h>
+
+
+/* Define next boot image name and offset */
+#define PLAT_NS_IMAGE_OFFSET 0x50000
+#define PLAT_HANDOFF_OFFSET 0xFFE3F000
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+/* Stratix 10 supports up to 124GB RAM */
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
+
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+#define PLAT_PRIMARY_CPU 0
+#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0
+
+/* Size of cacheable stacks */
+#define PLATFORM_STACK_SIZE 0x2000
+
+/* PSCI related constant */
+#define PLAT_NUM_POWER_DOMAINS 5
+#define PLAT_MAX_PWR_LVL 1
+#define PLAT_MAX_RET_STATE 1
+#define PLAT_MAX_OFF_STATE 2
+#define PLATFORM_SYSTEM_COUNT 1
+#define PLATFORM_CLUSTER_COUNT 1
+#define PLATFORM_CLUSTER0_CORE_COUNT 4
+#define PLATFORM_CLUSTER1_CORE_COUNT 0
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
+ PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
+
+/* Interrupt related constant */
+
+#define INTEL_S10_IRQ_SEC_PHY_TIMER 29
+
+#define INTEL_S10_IRQ_SEC_SGI_0 8
+#define INTEL_S10_IRQ_SEC_SGI_1 9
+#define INTEL_S10_IRQ_SEC_SGI_2 10
+#define INTEL_S10_IRQ_SEC_SGI_3 11
+#define INTEL_S10_IRQ_SEC_SGI_4 12
+#define INTEL_S10_IRQ_SEC_SGI_5 13
+#define INTEL_S10_IRQ_SEC_SGI_6 14
+#define INTEL_S10_IRQ_SEC_SGI_7 15
+
+#define TSP_IRQ_SEC_PHY_TIMER INTEL_S10_IRQ_SEC_PHY_TIMER
+#define TSP_SEC_MEM_BASE BL32_BASE
+#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define DRAM_BASE (0x0)
+#define DRAM_SIZE (0x80000000)
+
+#define OCRAM_BASE (0xFFE00000)
+#define OCRAM_SIZE (0x00100000)
+
+#define MEM64_BASE (0x0100000000)
+#define MEM64_SIZE (0x1F00000000)
+
+#define DEVICE1_BASE (0x80000000)
+#define DEVICE1_SIZE (0x60000000)
+
+#define DEVICE2_BASE (0xF7000000)
+#define DEVICE2_SIZE (0x08E00000)
+
+#define DEVICE3_BASE (0xFFFC0000)
+#define DEVICE3_SIZE (0x00008000)
+
+#define DEVICE4_BASE (0x2000000000)
+#define DEVICE4_SIZE (0x0100000000)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
+ * little space for growth.
+ */
+
+
+#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
+
+#define BL1_RO_BASE (0xffe00000)
+#define BL1_RO_LIMIT (0xffe0f000)
+#define BL1_RW_BASE (0xffe10000)
+#define BL1_RW_LIMIT (0xffe1ffff)
+#define BL1_RW_SIZE (0x14000)
+
+#define BL2_BASE (0xffe00000)
+#define BL2_LIMIT (0xffe1c000)
+
+#define BL31_BASE (0xffe1c000)
+#define BL31_LIMIT (0xffe3ffff)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define MAX_XLAT_TABLES 8
+#define MAX_MMAP_REGIONS 16
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT 6
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+#define PLAT_GIC_BASE (0xFFFC0000)
+#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
+#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
+#define PLAT_GICR_BASE 0
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define PLAT_UART0_BASE (0xFFC02000)
+#define PLAT_UART1_BASE (0xFFC02100)
+
+#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
+
+#define PLAT_BAUDRATE (115200)
+#define PLAT_UART_CLOCK (100000000)
+
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
+
+#define PLAT_INTEL_S10_GICD_BASE PLAT_GICD_BASE
+#define PLAT_INTEL_S10_GICC_BASE PLAT_GICC_BASE
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_INTEL_S10_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(INTEL_S10_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE)
+
+#define PLAT_INTEL_S10_G0_IRQ_PROPS(grp)
+
+#define MAX_IO_HANDLES 4
+#define MAX_IO_DEVICES 4
+#define MAX_IO_BLOCK_DEVICES 2
+
+
+#endif /* __PLATFORM_DEF_H__ */
+
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+#include <platform_private.h>
+
+#include "s10_clock_manager.h"
+#include "s10_handoff.h"
+
+
+void wait_pll_lock(void)
+{
+ uint32_t data;
+
+ do {
+ data = mmio_read_32(ALT_CLKMGR + ALT_CLKMGR_STAT);
+ } while ((ALT_CLKMGR_STAT_MAINPLLLOCKED(data) == 0) ||
+ (ALT_CLKMGR_STAT_PERPLLLOCKED(data) == 0));
+}
+
+void wait_fsm(void)
+{
+ uint32_t data;
+
+ do {
+ data = mmio_read_32(ALT_CLKMGR + ALT_CLKMGR_STAT);
+ } while (ALT_CLKMGR_STAT_BUSY(data) == ALT_CLKMGR_STAT_BUSY_E_BUSY);
+}
+
+void config_clkmgr_handoff(handoff *hoff_ptr)
+{
+ uint32_t m_div, refclk_div, mscnt, hscnt;
+
+ /* Bypass all mainpllgrp's clocks */
+ mmio_write_32(ALT_CLKMGR_MAINPLL +
+ ALT_CLKMGR_MAINPLL_BYPASS,
+ 0x7);
+ wait_fsm();
+ /* Bypass all perpllgrp's clocks */
+ mmio_write_32(ALT_CLKMGR_PERPLL +
+ ALT_CLKMGR_PERPLL_BYPASS,
+ 0x7f);
+ wait_fsm();
+
+ /* Setup main PLL dividers */
+ m_div = ALT_CLKMGR_MAINPLL_FDBCK_MDIV(hoff_ptr->main_pll_fdbck);
+ refclk_div = ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(
+ hoff_ptr->main_pll_pllglob);
+ mscnt = 200 / ((6 + m_div) / refclk_div);
+ hscnt = (m_div + 6) * mscnt / refclk_div - 9;
+
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB,
+ hoff_ptr->main_pll_pllglob);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_FDBCK,
+ hoff_ptr->main_pll_fdbck);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_VCOCALIB,
+ ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(hscnt) |
+ ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(mscnt));
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC0,
+ hoff_ptr->main_pll_pllc0);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC1,
+ hoff_ptr->main_pll_pllc1);
+
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCDIV,
+ hoff_ptr->main_pll_nocdiv);
+
+ /* Setup peripheral PLL dividers */
+ m_div = ALT_CLKMGR_PERPLL_FDBCK_MDIV(hoff_ptr->per_pll_fdbck);
+ refclk_div = ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(
+ hoff_ptr->per_pll_pllglob);
+ mscnt = 200 / ((6 + m_div) / refclk_div);
+ hscnt = (m_div + 6) * mscnt / refclk_div - 9;
+
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB,
+ hoff_ptr->per_pll_pllglob);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_FDBCK,
+ hoff_ptr->per_pll_fdbck);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_VCOCALIB,
+ ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(hscnt) |
+ ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(mscnt));
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLC0,
+ hoff_ptr->per_pll_pllc0);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLC1,
+ hoff_ptr->per_pll_pllc1);
+
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_GPIODIV,
+ ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(
+ hoff_ptr->per_pll_gpiodiv));
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_EMACCTL,
+ hoff_ptr->per_pll_emacctl);
+
+
+ /* Take both PLL out of reset and power up */
+ mmio_setbits_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB,
+ ALT_CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
+ ALT_CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
+ mmio_setbits_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB,
+ ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
+ ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
+
+ wait_pll_lock();
+
+ /* Dividers for C2 to C9 only init after PLLs are lock. */
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_MPUCLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCCLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR2CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR3CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR4CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR5CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR6CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR7CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR8CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR9CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR2CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR3CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR4CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR5CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR6CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR7CLK, 0xff);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR8CLK, 0xff);
+
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_MPUCLK,
+ hoff_ptr->main_pll_mpuclk);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCCLK,
+ hoff_ptr->main_pll_nocclk);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR2CLK,
+ hoff_ptr->main_pll_cntr2clk);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR3CLK,
+ hoff_ptr->main_pll_cntr3clk);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR4CLK,
+ hoff_ptr->main_pll_cntr4clk);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR5CLK,
+ hoff_ptr->main_pll_cntr5clk);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR6CLK,
+ hoff_ptr->main_pll_cntr6clk);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR7CLK,
+ hoff_ptr->main_pll_cntr7clk);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR8CLK,
+ hoff_ptr->main_pll_cntr8clk);
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR9CLK,
+ hoff_ptr->main_pll_cntr9clk);
+
+ /* Peripheral PLL Clock Source and Counters/Divider */
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR2CLK,
+ hoff_ptr->per_pll_cntr2clk);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR3CLK,
+ hoff_ptr->per_pll_cntr3clk);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR4CLK,
+ hoff_ptr->per_pll_cntr4clk);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR5CLK,
+ hoff_ptr->per_pll_cntr5clk);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR6CLK,
+ hoff_ptr->per_pll_cntr6clk);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR7CLK,
+ hoff_ptr->per_pll_cntr7clk);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR8CLK,
+ hoff_ptr->per_pll_cntr8clk);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR9CLK,
+ hoff_ptr->per_pll_cntr9clk);
+
+ /* Take all PLLs out of bypass */
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_BYPASS, 0);
+ wait_fsm();
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_BYPASS, 0);
+ wait_fsm();
+
+ /* Set safe mode/ out of boot mode */
+ mmio_clrbits_32(ALT_CLKMGR + ALT_CLKMGR_CTRL,
+ ALT_CLKMGR_CTRL_BOOTMODE_SET_MSK);
+ wait_fsm();
+
+ /* 10 Enable mainpllgrp's software-managed clock */
+ mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_EN,
+ ALT_CLKMGR_MAINPLL_EN_RESET);
+ mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_EN,
+ ALT_CLKMGR_PERPLL_EN_RESET);
+
+ /* Clear loss lock interrupt status register that */
+ /* might be set during configuration */
+ mmio_write_32(ALT_CLKMGR + ALT_CLKMGR_INTRCLR,
+ ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK |
+ ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <drivers/arm/gicv2.h>
+#include <assert.h>
+#include <common/bl_common.h>
+#include <lib/mmio.h>
+#include <string.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <platform_private.h>
+
+#include "s10_handoff.h"
+
+#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \
+ (((x) & 0x0000FF00) << 8) | ((x) << 24))
+
+int s10_get_handoff(handoff *reverse_hoff_ptr)
+{
+ int i;
+ uint32_t *buffer;
+ handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET;
+
+ memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff));
+ buffer = (uint32_t *)reverse_hoff_ptr;
+
+ /* convert big indian to little indian */
+ for (i = 0; i < sizeof(handoff) / 4; i++)
+ buffer[i] = SWAP_UINT32(buffer[i]);
+
+ if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER)
+ return -1;
+ if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL)
+ return -1;
+ if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR)
+ return -1;
+ if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA)
+ return -1;
+ if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY)
+ return -1;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <errno.h>
+#include <lib/mmio.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <string.h>
+
+#include "s10_memory_controller.h"
+
+#define ALT_CCU_NOC_DI_SET_MSK 0x10
+
+#define DDR_READ_LATENCY_DELAY 40
+#define MAX_MEM_CAL_RETRY 3
+#define PRE_CALIBRATION_DELAY 1
+#define POST_CALIBRATION_DELAY 1
+#define TIMEOUT_EMIF_CALIBRATION 100
+#define CLEAR_EMIF_DELAY 50000
+#define CLEAR_EMIF_TIMEOUT 0x100000
+#define TIMEOUT_INT_RESP 10000
+
+#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
+
+/* tWR = Min. 15ns constant, see JEDEC standard eg. DDR4 is JESD79-4.pdf */
+#define tWR_IN_NS 15
+
+void configure_hmc_adaptor_regs(void);
+void configure_ddr_sched_ctrl_regs(void);
+
+/* The followring are the supported configurations */
+uint32_t ddr_config[] = {
+ /* DDR_CONFIG(Address order,Bank,Column,Row) */
+ /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
+ DDR_CONFIG(0, 3, 10, 12),
+ DDR_CONFIG(0, 3, 9, 13),
+ DDR_CONFIG(0, 3, 10, 13),
+ DDR_CONFIG(0, 3, 9, 14),
+ DDR_CONFIG(0, 3, 10, 14),
+ DDR_CONFIG(0, 3, 10, 15),
+ DDR_CONFIG(0, 3, 11, 14),
+ DDR_CONFIG(0, 3, 11, 15),
+ DDR_CONFIG(0, 3, 10, 16),
+ DDR_CONFIG(0, 3, 11, 16),
+ DDR_CONFIG(0, 3, 12, 15), /* 0xa */
+ /* List for DDR4 only (pinout order > chip, bank, row, column) */
+ DDR_CONFIG(1, 3, 10, 14),
+ DDR_CONFIG(1, 4, 10, 14),
+ DDR_CONFIG(1, 3, 10, 15),
+ DDR_CONFIG(1, 4, 10, 15),
+ DDR_CONFIG(1, 3, 10, 16),
+ DDR_CONFIG(1, 4, 10, 16),
+ DDR_CONFIG(1, 3, 10, 17),
+ DDR_CONFIG(1, 4, 10, 17),
+};
+
+static int match_ddr_conf(uint32_t ddr_conf)
+{
+ int i;
+
+ for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+ if (ddr_conf == ddr_config[i])
+ return i;
+ }
+ return 0;
+}
+
+static int check_hmc_clk(void)
+{
+ unsigned long timeout = 0;
+ uint32_t hmc_clk;
+
+ do {
+ hmc_clk = mmio_read_32(S10_SYSMGR_CORE_HMC_CLK);
+ if (hmc_clk & S10_SYSMGR_CORE_HMC_CLK_STATUS)
+ break;
+ udelay(1);
+ } while (++timeout < 1000);
+ if (timeout >= 1000)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int clear_emif(void)
+{
+ uint32_t data;
+ unsigned long timeout;
+
+ mmio_write_32(S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL, 0);
+
+ timeout = 0;
+ do {
+ data = mmio_read_32(S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT);
+ if ((data & S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE) == 0)
+ break;
+ udelay(CLEAR_EMIF_DELAY);
+ } while (++timeout < CLEAR_EMIF_TIMEOUT);
+ if (timeout >= CLEAR_EMIF_TIMEOUT)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int mem_calibration(void)
+{
+ int status = 0;
+ uint32_t data;
+ unsigned long timeout;
+ unsigned long retry = 0;
+
+ udelay(PRE_CALIBRATION_DELAY);
+
+ do {
+ if (retry != 0)
+ INFO("DDR: Retrying DRAM calibration\n");
+
+ timeout = 0;
+ do {
+ data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT);
+ if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1)
+ break;
+ udelay(1);
+ } while (++timeout < TIMEOUT_EMIF_CALIBRATION);
+
+ if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
+ status = clear_emif();
+ if (status)
+ ERROR("Failed to clear Emif\n");
+ } else {
+ break;
+ }
+ } while (++retry < MAX_MEM_CAL_RETRY);
+
+ if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
+ ERROR("DDR: DRAM calibration failed.\n");
+ status = -EIO;
+ } else {
+ INFO("DDR: DRAM calibration success.\n");
+ status = 0;
+ }
+
+ udelay(POST_CALIBRATION_DELAY);
+
+ return status;
+}
+
+int init_hard_memory_controller(void)
+{
+ int status;
+
+ mmio_clrbits_32(S10_CCU_CPU0_MPRT_DDR, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1E, S10_CCU_NOC_DI_SET_MSK);
+
+ mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK);
+ mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1E, S10_CCU_NOC_DI_SET_MSK);
+
+ mmio_write_32(S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, 0xFFFF0000);
+ mmio_write_32(S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1F);
+
+ mmio_write_32(S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, 0xFFFF0000);
+ mmio_write_32(S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT, 0x1F);
+ mmio_write_32(S10_SOC_NOC_FW_DDR_SCR_ENABLE, BIT(0) | BIT(8));
+
+ status = check_hmc_clk();
+ if (status) {
+ ERROR("DDR: Error, HMC clock not running\n");
+ return status;
+ }
+
+ mmio_clrbits_32(S10_RSTMGR_BRGMODRST, S10_RSTMGR_BRGMODRST_DDRSCH);
+
+ status = mem_calibration();
+ if (status) {
+ ERROR("DDR: Memory Calibration Failed\n");
+ return status;
+ }
+
+ configure_hmc_adaptor_regs();
+ configure_ddr_sched_ctrl_regs();
+
+ return 0;
+}
+
+void configure_ddr_sched_ctrl_regs(void)
+{
+ uint32_t data, dram_addr_order, ddr_conf, bank, row, col,
+ rd_to_miss, wr_to_miss, burst_len, burst_len_ddr_clk,
+ burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio,
+ t_rtp, t_rp, t_rcd, rd_latency, tw_rin_clk_cycles,
+ bw_ratio_extended, auto_precharge = 0, act_to_act_bank, faw,
+ faw_bank, bus_rd_to_rd, bus_rd_to_wr, bus_wr_to_rd;
+
+ INFO("Init HPS NOC's DDR Scheduler.\n");
+
+ data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG1);
+ dram_addr_order = S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(data);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_DRAMADDRW);
+
+ col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data);
+ row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data);
+ bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) +
+ IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(data);
+
+ ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row));
+
+ if (ddr_conf) {
+ mmio_clrsetbits_32(
+ S10_MPFE_DDR_MAIN_SCHED_DDRCONF,
+ S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK,
+ S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(ddr_conf));
+ } else {
+ ERROR("DDR: Cannot find predefined ddrConf configuration.\n");
+ }
+
+ mmio_write_32(S10_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_DRAMTIMING0);
+ rd_latency = S10_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(data);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING0);
+ act_to_act = ACT_TO_ACT(data);
+ t_rcd = ACT_TO_RDWR(data);
+ act_to_act_bank = ACT_TO_ACT_DIFF_BANK(data);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING1);
+ rd_to_wr = RD_TO_WR(data);
+ bus_rd_to_rd = RD_TO_RD_DIFF_CHIP(data);
+ bus_rd_to_wr = RD_TO_WR_DIFF_CHIP(data);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING2);
+ t_rtp = RD_TO_PCH(data);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING3);
+ wr_to_rd = CALTIMING3_WR_TO_RD(data);
+ bus_wr_to_rd = CALTIMING3_WR_TO_RD_DIFF_CHIP(data);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING4);
+ t_rp = PCH_TO_VALID(data);
+
+ data = mmio_read_32(S10_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL));
+ bw_ratio = ((HMC_ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 0 : 1);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG0);
+ burst_len = HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(data);
+ burst_len_ddr_clk = burst_len / 2;
+ burst_len_sched_clk = ((burst_len/2) / 2);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG0);
+ switch (S10_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(data)) {
+ case 1:
+ /* DDR4 - 1333MHz */
+ /* 20 (19.995) clock cycles = 15ns */
+ /* Calculate with rounding */
+ tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ?
+ ((tWR_IN_NS * 1333) / 1000) + 1 :
+ ((tWR_IN_NS * 1333) / 1000);
+ break;
+ default:
+ /* Others - 1066MHz or slower */
+ /* 16 (15.990) clock cycles = 15ns */
+ /* Calculate with rounding */
+ tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ?
+ ((tWR_IN_NS * 1066) / 1000) + 1 :
+ ((tWR_IN_NS * 1066) / 1000);
+ break;
+ }
+
+ rd_to_miss = t_rtp + t_rp + t_rcd - burst_len_sched_clk;
+ wr_to_miss = ((rd_latency + burst_len_ddr_clk + 2 + tw_rin_clk_cycles)
+ / 2) - rd_to_wr + t_rp + t_rcd;
+
+ mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DDRTIMING,
+ bw_ratio << DDRTIMING_BWRATIO_OFST |
+ wr_to_rd << DDRTIMING_WRTORD_OFST|
+ rd_to_wr << DDRTIMING_RDTOWR_OFST |
+ burst_len_sched_clk << DDRTIMING_BURSTLEN_OFST |
+ wr_to_miss << DDRTIMING_WRTOMISS_OFST |
+ rd_to_miss << DDRTIMING_RDTOMISS_OFST |
+ act_to_act << DDRTIMING_ACTTOACT_OFST);
+
+ data = mmio_read_32(S10_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL));
+ bw_ratio_extended = ((ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 1 : 0);
+
+ mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DDRMODE,
+ bw_ratio_extended << DDRMODE_BWRATIOEXTENDED_OFST |
+ auto_precharge << DDRMODE_AUTOPRECHARGE_OFST);
+
+ mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_READLATENCY,
+ (rd_latency / 2) + DDR_READ_LATENCY_DELAY);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING9);
+ faw = S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(data);
+
+ faw_bank = 1; // always 1 because we always have 4 bank DDR.
+
+ mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_ACTIVATE,
+ faw_bank << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST |
+ faw << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST |
+ act_to_act_bank << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST);
+
+ mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DEVTODEV,
+ bus_rd_to_rd << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST |
+ bus_rd_to_wr << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST |
+ bus_wr_to_rd << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST);
+
+}
+
+unsigned long get_physical_dram_size(void)
+{
+ uint32_t data;
+ unsigned long ram_addr_width, ram_ext_if_io_width;
+
+ data = mmio_read_32(S10_MPFE_HMC_ADP_DDRIOCTRL);
+ switch (S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(data)) {
+ case 0:
+ ram_ext_if_io_width = 16;
+ break;
+ case 1:
+ ram_ext_if_io_width = 32;
+ break;
+ case 2:
+ ram_ext_if_io_width = 64;
+ break;
+ default:
+ ram_ext_if_io_width = 0;
+ break;
+ }
+
+ data = mmio_read_32(S10_MPFE_IOHMC_REG_DRAMADDRW);
+ ram_addr_width = IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(data) +
+ IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(data) +
+ IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(data) +
+ IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(data) +
+ IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(data);
+
+ return (1 << ram_addr_width) * (ram_ext_if_io_width / 8);
+}
+
+
+
+void configure_hmc_adaptor_regs(void)
+{
+ uint32_t data;
+ uint32_t dram_io_width;
+
+ dram_io_width = S10_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(
+ mmio_read_32(S10_MPFE_IOHMC_REG_NIOSRESERVE0_OFST));
+
+ dram_io_width = (dram_io_width & 0xFF) >> 5;
+
+ mmio_clrsetbits_32(S10_MPFE_HMC_ADP_DDRIOCTRL,
+ S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK,
+ dram_io_width << S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST);
+
+ mmio_write_32(S10_MPFE_HMC_ADP_HPSINTFCSEL,
+ S10_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE);
+
+ data = mmio_read_32(S10_MPFE_IOHMC_REG_CTRLCFG1);
+ if (data & (1 << S10_IOHMC_CTRLCFG1_ENABLE_ECC_OFST)) {
+ mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1,
+ S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK |
+ S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK |
+ S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK,
+ S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK |
+ S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK);
+
+ mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL2,
+ S10_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK |
+ S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK |
+ S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK,
+ S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK |
+ S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK);
+
+ mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1,
+ S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK |
+ S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK |
+ S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK,
+ S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK);
+
+ } else {
+ INFO("ECC is disabled.\n");
+ }
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+
+#include "s10_pinmux.h"
+
+const uint32_t sysmgr_pinmux_array_sel[] = {
+ 0x00000000, 0x00000001, /* usb */
+ 0x00000004, 0x00000001,
+ 0x00000008, 0x00000001,
+ 0x0000000c, 0x00000001,
+ 0x00000010, 0x00000001,
+ 0x00000014, 0x00000001,
+ 0x00000018, 0x00000001,
+ 0x0000001c, 0x00000001,
+ 0x00000020, 0x00000001,
+ 0x00000024, 0x00000001,
+ 0x00000028, 0x00000001,
+ 0x0000002c, 0x00000001,
+ 0x00000030, 0x00000000, /* emac0 */
+ 0x00000034, 0x00000000,
+ 0x00000038, 0x00000000,
+ 0x0000003c, 0x00000000,
+ 0x00000040, 0x00000000,
+ 0x00000044, 0x00000000,
+ 0x00000048, 0x00000000,
+ 0x0000004c, 0x00000000,
+ 0x00000050, 0x00000000,
+ 0x00000054, 0x00000000,
+ 0x00000058, 0x00000000,
+ 0x0000005c, 0x00000000,
+ 0x00000060, 0x00000008, /* gpio1 */
+ 0x00000064, 0x00000008,
+ 0x00000068, 0x00000005, /* uart0 tx */
+ 0x0000006c, 0x00000005, /* uart 0 rx */
+ 0x00000070, 0x00000008, /* gpio */
+ 0x00000074, 0x00000008,
+ 0x00000078, 0x00000004, /* i2c1 */
+ 0x0000007c, 0x00000004,
+ 0x00000080, 0x00000007, /* jtag */
+ 0x00000084, 0x00000007,
+ 0x00000088, 0x00000007,
+ 0x0000008c, 0x00000007,
+ 0x00000090, 0x00000001, /* sdmmc data0 */
+ 0x00000094, 0x00000001,
+ 0x00000098, 0x00000001,
+ 0x0000009c, 0x00000001,
+ 0x00000100, 0x00000001,
+ 0x00000104, 0x00000001, /* sdmmc.data3 */
+ 0x00000108, 0x00000008, /* loan */
+ 0x0000010c, 0x00000008, /* gpio */
+ 0x00000110, 0x00000008,
+ 0x00000114, 0x00000008, /* gpio1.io21 */
+ 0x00000118, 0x00000005, /* mdio0.mdio */
+ 0x0000011c, 0x00000005 /* mdio0.mdc */
+};
+
+const uint32_t sysmgr_pinmux_array_ctrl[] = {
+ 0x00000000, 0x00502c38, /* Q1_1 */
+ 0x00000004, 0x00102c38,
+ 0x00000008, 0x00502c38,
+ 0x0000000c, 0x00502c38,
+ 0x00000010, 0x00502c38,
+ 0x00000014, 0x00502c38,
+ 0x00000018, 0x00502c38,
+ 0x0000001c, 0x00502c38,
+ 0x00000020, 0x00502c38,
+ 0x00000024, 0x00502c38,
+ 0x00000028, 0x00502c38,
+ 0x0000002c, 0x00502c38,
+ 0x00000030, 0x00102c38, /* Q2_1 */
+ 0x00000034, 0x00102c38,
+ 0x00000038, 0x00502c38,
+ 0x0000003c, 0x00502c38,
+ 0x00000040, 0x00102c38,
+ 0x00000044, 0x00102c38,
+ 0x00000048, 0x00502c38,
+ 0x0000004c, 0x00502c38,
+ 0x00000050, 0x00102c38,
+ 0x00000054, 0x00102c38,
+ 0x00000058, 0x00502c38,
+ 0x0000005c, 0x00502c38,
+ 0x00000060, 0x00502c38, /* Q3_1 */
+ 0x00000064, 0x00502c38,
+ 0x00000068, 0x00102c38,
+ 0x0000006c, 0x00502c38,
+ 0x000000d0, 0x00502c38,
+ 0x000000d4, 0x00502c38,
+ 0x000000d8, 0x00542c38,
+ 0x000000dc, 0x00542c38,
+ 0x000000e0, 0x00502c38,
+ 0x000000e4, 0x00502c38,
+ 0x000000e8, 0x00102c38,
+ 0x000000ec, 0x00502c38,
+ 0x000000f0, 0x00502c38, /* Q4_1 */
+ 0x000000f4, 0x00502c38,
+ 0x000000f8, 0x00102c38,
+ 0x000000fc, 0x00502c38,
+ 0x00000100, 0x00502c38,
+ 0x00000104, 0x00502c38,
+ 0x00000108, 0x00102c38,
+ 0x0000010c, 0x00502c38,
+ 0x00000110, 0x00502c38,
+ 0x00000114, 0x00502c38,
+ 0x00000118, 0x00542c38,
+ 0x0000011c, 0x00102c38
+};
+
+const uint32_t sysmgr_pinmux_array_fpga[] = {
+ 0x00000000, 0x00000000,
+ 0x00000004, 0x00000000,
+ 0x00000008, 0x00000000,
+ 0x0000000c, 0x00000000,
+ 0x00000010, 0x00000000,
+ 0x00000014, 0x00000000,
+ 0x00000018, 0x00000000,
+ 0x0000001c, 0x00000000,
+ 0x00000020, 0x00000000,
+ 0x00000028, 0x00000000,
+ 0x0000002c, 0x00000000,
+ 0x00000030, 0x00000000,
+ 0x00000034, 0x00000000,
+ 0x00000038, 0x00000000,
+ 0x0000003c, 0x00000000,
+ 0x00000040, 0x00000000,
+ 0x00000044, 0x00000000,
+ 0x00000048, 0x00000000,
+ 0x00000050, 0x00000000,
+ 0x00000054, 0x00000000,
+ 0x00000058, 0x0000002a
+};
+
+const uint32_t sysmgr_pinmux_array_iodelay[] = {
+ 0x00000000, 0x00000000,
+ 0x00000004, 0x00000000,
+ 0x00000008, 0x00000000,
+ 0x0000000c, 0x00000000,
+ 0x00000010, 0x00000000,
+ 0x00000014, 0x00000000,
+ 0x00000018, 0x00000000,
+ 0x0000001c, 0x00000000,
+ 0x00000020, 0x00000000,
+ 0x00000024, 0x00000000,
+ 0x00000028, 0x00000000,
+ 0x0000002c, 0x00000000,
+ 0x00000030, 0x00000000,
+ 0x00000034, 0x00000000,
+ 0x00000038, 0x00000000,
+ 0x0000003c, 0x00000000,
+ 0x00000040, 0x00000000,
+ 0x00000044, 0x00000000,
+ 0x00000048, 0x00000000,
+ 0x0000004c, 0x00000000,
+ 0x00000050, 0x00000000,
+ 0x00000054, 0x00000000,
+ 0x00000058, 0x00000000,
+ 0x0000005c, 0x00000000,
+ 0x00000060, 0x00000000,
+ 0x00000064, 0x00000000,
+ 0x00000068, 0x00000000,
+ 0x0000006c, 0x00000000,
+ 0x00000070, 0x00000000,
+ 0x00000074, 0x00000000,
+ 0x00000078, 0x00000000,
+ 0x0000007c, 0x00000000,
+ 0x00000080, 0x00000000,
+ 0x00000084, 0x00000000,
+ 0x00000088, 0x00000000,
+ 0x0000008c, 0x00000000,
+ 0x00000090, 0x00000000,
+ 0x00000094, 0x00000000,
+ 0x00000098, 0x00000000,
+ 0x0000009c, 0x00000000,
+ 0x00000100, 0x00000000,
+ 0x00000104, 0x00000000,
+ 0x00000108, 0x00000000,
+ 0x0000010c, 0x00000000,
+ 0x00000110, 0x00000000,
+ 0x00000114, 0x00000000,
+ 0x00000118, 0x00000000,
+ 0x0000011c, 0x00000000
+};
+
+void config_pinmux(handoff *hoff_ptr)
+{
+ unsigned int i;
+
+ for (i = 0; i < 96; i += 2) {
+ mmio_write_32(S10_PINMUX_PIN0SEL +
+ hoff_ptr->pinmux_sel_array[i],
+ hoff_ptr->pinmux_sel_array[i+1]);
+ }
+
+ for (i = 0; i < 96; i += 2) {
+ mmio_write_32(S10_PINMUX_IO0CTRL +
+ hoff_ptr->pinmux_io_array[i],
+ hoff_ptr->pinmux_io_array[i+1]);
+ }
+
+ for (i = 0; i < 42; i += 2) {
+ mmio_write_32(S10_PINMUX_PINMUX_EMAC0_USEFPGA +
+ hoff_ptr->pinmux_fpga_array[i],
+ hoff_ptr->pinmux_fpga_array[i+1]);
+ }
+
+ for (i = 0; i < 96; i += 2) {
+ mmio_write_32(S10_PINMUX_IO0_DELAY +
+ hoff_ptr->pinmux_iodelay_array[i],
+ hoff_ptr->pinmux_iodelay_array[i+1]);
+ }
+
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <platform_private.h>
+#include "s10_reset_manager.h"
+
+void deassert_peripheral_reset(void)
+{
+ mmio_clrbits_32(S10_RSTMGR_PER1MODRST,
+ S10_RSTMGR_PER1MODRST_WATCHDOG0 |
+ S10_RSTMGR_PER1MODRST_WATCHDOG1 |
+ S10_RSTMGR_PER1MODRST_WATCHDOG2 |
+ S10_RSTMGR_PER1MODRST_WATCHDOG3 |
+ S10_RSTMGR_PER1MODRST_L4SYSTIMER0 |
+ S10_RSTMGR_PER1MODRST_L4SYSTIMER1 |
+ S10_RSTMGR_PER1MODRST_SPTIMER0 |
+ S10_RSTMGR_PER1MODRST_SPTIMER1 |
+ S10_RSTMGR_PER1MODRST_I2C0 |
+ S10_RSTMGR_PER1MODRST_I2C1 |
+ S10_RSTMGR_PER1MODRST_I2C2 |
+ S10_RSTMGR_PER1MODRST_I2C3 |
+ S10_RSTMGR_PER1MODRST_I2C4 |
+ S10_RSTMGR_PER1MODRST_UART0 |
+ S10_RSTMGR_PER1MODRST_UART1 |
+ S10_RSTMGR_PER1MODRST_GPIO0 |
+ S10_RSTMGR_PER1MODRST_GPIO1);
+
+ mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
+ S10_RSTMGR_PER0MODRST_EMAC0OCP |
+ S10_RSTMGR_PER0MODRST_EMAC1OCP |
+ S10_RSTMGR_PER0MODRST_EMAC2OCP |
+ S10_RSTMGR_PER0MODRST_USB0OCP |
+ S10_RSTMGR_PER0MODRST_USB1OCP |
+ S10_RSTMGR_PER0MODRST_NANDOCP |
+ S10_RSTMGR_PER0MODRST_SDMMCOCP |
+ S10_RSTMGR_PER0MODRST_DMAOCP);
+
+ mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
+ S10_RSTMGR_PER0MODRST_EMAC0 |
+ S10_RSTMGR_PER0MODRST_EMAC1 |
+ S10_RSTMGR_PER0MODRST_EMAC2 |
+ S10_RSTMGR_PER0MODRST_USB0 |
+ S10_RSTMGR_PER0MODRST_USB1 |
+ S10_RSTMGR_PER0MODRST_NAND |
+ S10_RSTMGR_PER0MODRST_SDMMC |
+ S10_RSTMGR_PER0MODRST_DMA |
+ S10_RSTMGR_PER0MODRST_SPIM0 |
+ S10_RSTMGR_PER0MODRST_SPIM1 |
+ S10_RSTMGR_PER0MODRST_SPIS0 |
+ S10_RSTMGR_PER0MODRST_SPIS1 |
+ S10_RSTMGR_PER0MODRST_EMACPTP |
+ S10_RSTMGR_PER0MODRST_DMAIF0 |
+ S10_RSTMGR_PER0MODRST_DMAIF1 |
+ S10_RSTMGR_PER0MODRST_DMAIF2 |
+ S10_RSTMGR_PER0MODRST_DMAIF3 |
+ S10_RSTMGR_PER0MODRST_DMAIF4 |
+ S10_RSTMGR_PER0MODRST_DMAIF5 |
+ S10_RSTMGR_PER0MODRST_DMAIF6 |
+ S10_RSTMGR_PER0MODRST_DMAIF7);
+
+}
+
+void config_hps_hs_before_warm_reset(void)
+{
+ uint32_t or_mask = 0;
+
+ or_mask |= S10_RSTMGR_HDSKEN_SDRSELFREFEN;
+ or_mask |= S10_RSTMGR_HDSKEN_FPGAHSEN;
+ or_mask |= S10_RSTMGR_HDSKEN_ETRSTALLEN;
+ or_mask |= S10_RSTMGR_HDSKEN_L2FLUSHEN;
+ or_mask |= S10_RSTMGR_HDSKEN_L3NOC_DBG;
+ or_mask |= S10_RSTMGR_HDSKEN_DEBUG_L3NOC;
+
+ mmio_setbits_32(S10_RSTMGR_HDSKEN, or_mask);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include "s10_system_manager.h"
+
+void enable_nonsecure_access(void)
+{
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC,
+ DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL);
+
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL);
+
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL);
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL);
+
+ mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL);
+
+ mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
+ mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/desc_image_load.h>
+
+/*******************************************************************************
+ * This function flushes the data structures so that they are visible
+ * in memory for the next BL image.
+ ******************************************************************************/
+void plat_flush_next_bl_params(void)
+{
+ flush_bl_params_desc();
+}
+
+/*******************************************************************************
+ * This function returns the list of loadable images.
+ ******************************************************************************/
+bl_load_info_t *plat_get_bl_image_load_info(void)
+{
+ return get_bl_load_info_from_mem_params_desc();
+}
+
+/*******************************************************************************
+ * This function returns the list of executable images.
+ ******************************************************************************/
+bl_params_t *plat_get_next_bl_params(void)
+{
+ return get_next_bl_params_from_mem_params_desc();
+}
PLAT_INCLUDES := -Iplat/layerscape/board/ls1043/include \
-Iplat/layerscape/common/include \
- -Iinclude/lib
-
PLAT_BL_COMMON_SOURCES := plat/layerscape/common/aarch64/ls_console.S
COLD_BOOT_SINGLE_CPU := 1
-PLAT_INCLUDES += -Iinclude/common/tbbr
-
PLAT_BL_COMMON_SOURCES += plat/layerscape/common/${ARCH}/ls_helpers.S \
plat/layerscape/common/ls_common.c
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <common/bl_common.h>
#include <common/debug.h>
#include <common/interrupt_props.h>
#include <drivers/arm/gicv2.h>
#include "plat_ls.h"
#include "soc.h"
-#define BL32_END (unsigned long)(&__BL32_END__)
-
static const interrupt_prop_t g0_interrupt_props[] = {
INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
plat/common/plat_gicv3.c \
drivers/arm/gic/v3/gic500.c
-ATF_INCLUDES := -Iinclude/common/tbbr
-
PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \
-I$(PLAT_COMMON_BASE)/include \
-I$(PLAT_INCLUDE_BASE)/common \
-I$(MARVELL_DRV_BASE) \
- -I$/drivers/arm/gic/common/ \
- $(ATF_INCLUDES)
+ -I$/drivers/arm/gic/common/
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
$(MARVELL_COMMON_BASE)/marvell_cci.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c
-ATF_INCLUDES := -Iinclude/common/tbbr
-
PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \
-I$(PLAT_COMMON_BASE)/include \
- -I$(PLAT_INCLUDE_BASE)/common \
- $(ATF_INCLUDES)
+ -I$(PLAT_INCLUDE_BASE)/common
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a8k_common.c \
drivers/ti/uart/aarch64/16550_console.S
$(PLAT_MARVELL)/common/plat_delay_timer.c \
$(PLAT_MARVELL)/common/marvell_console.c
-PLAT_INCLUDES += -I$(MV_DDR_PATH) \
- -I$(CURDIR)/include/ \
- -I$(CURDIR)/include/lib \
- -I$(CURDIR)/include/lib/libc \
- -I$(CURDIR)/include/lib/libc/aarch64 \
+PLAT_INCLUDES += -I$(MV_DDR_PATH) \
+ -I$(CURDIR)/include \
+ -I$(CURDIR)/include/lib/libc \
+ -I$(CURDIR)/include/lib/libc/aarch64 \
-I$(CURDIR)/drivers/marvell
BLE_LINKERFILE := $(BLE_PATH)/ble.ld.S
#include <assert.h>
#include <arch.h>
+#include <common/bl_common.h>
#include <common/debug.h>
#ifdef USE_CCI
#include <drivers/arm/cci.h>
#include <marvell_plat_priv.h>
#include <plat_marvell.h>
-/*
- * The next 3 constants identify the extents of the code, RO data region and the
- * limit of the BL31 image. These addresses are used by the MMU setup code and
- * therefore they must be page-aligned. It is the responsibility of the linker
- * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_END (unsigned long)(&__BL31_END__)
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
LLC_ENABLE := 1
$(eval $(call add_define,LLC_ENABLE))
-PLAT_INCLUDES += -I. -Iinclude/common -Iinclude/common/tbbr \
- -I$(MARVELL_PLAT_INCLUDE_BASE)/common \
+PLAT_INCLUDES += -I$(MARVELL_PLAT_INCLUDE_BASE)/common \
-I$(MARVELL_PLAT_INCLUDE_BASE)/common/aarch64
-I${MTK_PLAT_SOC}/drivers/timer/ \
-I${MTK_PLAT_SOC}/include/ \
-Iinclude/plat/arm/common/ \
- -Iinclude/common/tbbr/ \
${OEMS_INCLUDES}
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \
endif
PLAT_PATH := plat/qemu/
-PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
- -Iplat/qemu/include \
- -Iinclude/common/tbbr
+PLAT_INCLUDES := -Iplat/qemu/include
ifeq (${ARM_ARCH_MAJOR},8)
PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
drivers/auth/img_parser_mod.c \
drivers/auth/tbbr/tbbr_cot.c
- PLAT_INCLUDES += -Iinclude/bl1/tbbr
-
BL1_SOURCES += ${AUTH_SOURCES} \
bl1/tbbr/tbbr_img_desc.c \
plat/common/tbbr/plat_tbbr.c \
#include "qemu_private.h"
-/*
- * The next 3 constants identify the extents of the code, RO data region and the
- * limit of the BL3-1 image. These addresses are used by the MMU setup code and
- * therefore they must be page-aligned. It is the responsibility of the linker
- * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_END (unsigned long)(&__BL31_END__)
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
static entry_point_info_t bl33_image_ep_info;
-/*
- * The next 3 constants identify the extents of the code, RO data region and the
- * limit of the BL3-1 image. These addresses are used by the MMU setup code and
- * therefore they must be page-aligned. It is the responsibility of the linker
- * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL32_RO_BASE (unsigned long)(&__RO_START__)
-#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
-#define BL32_END (unsigned long)(&__BL32_END__)
-
-#if USE_COHERENT_MEM
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-#endif
-
/******************************************************************************
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
void sp_min_plat_arch_setup(void)
{
qemu_configure_mmu_svc_mon(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
- BL32_RO_BASE, BL32_RO_LIMIT,
+ BL_CODE_BASE, BL_CODE_END,
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
include drivers/staging/renesas/rcar/pfc/pfc.mk
include lib/libfdt/libfdt.mk
-PLAT_INCLUDES := -Iinclude/common/tbbr \
- -Idrivers/staging/renesas/rcar/ddr \
+PLAT_INCLUDES := -Idrivers/staging/renesas/rcar/ddr \
-Idrivers/staging/renesas/rcar/qos \
-Idrivers/renesas/rcar/iic_dvfs \
-Idrivers/renesas/rcar/board \
PLAT_INCLUDES := -Idrivers/arm/gic/common/ \
-Idrivers/arm/gic/v2/ \
- -Iinclude/plat/common/ \
-I${RK_PLAT_COMMON}/ \
-I${RK_PLAT_COMMON}/include/ \
-I${RK_PLAT_COMMON}/pmusram \
#define MAX_IO_DEVICES U(3)
#define MAX_IO_HANDLES U(4)
+#define MAX_IO_BLOCK_DEVICES U(1)
+
/*
* Serial-related constants.
*/
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/rpi3/gpio/rpi3_gpio.c \
+ drivers/io/io_block.c \
+ drivers/mmc/mmc.c \
+ drivers/rpi3/sdhost/rpi3_sdhost.c \
plat/common/aarch64/platform_mp_stack.S \
plat/rpi3/aarch64/plat_helpers.S \
plat/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/rpi3/gpio/rpi3_gpio.h>
+#include <drivers/rpi3/sdhost/rpi3_sdhost.h>
#include "rpi3_private.h"
rpi3_gpio_init(¶ms);
}
+/* Data structure which holds the MMC info */
+static struct mmc_device_info mmc_info;
+
+static void rpi3_sdhost_setup(void)
+{
+ struct rpi3_sdhost_params params;
+
+ memset(¶ms, 0, sizeof(struct rpi3_sdhost_params));
+ params.reg_base = RPI3_SDHOST_BASE;
+ params.bus_width = MMC_BUS_WIDTH_4;
+ params.clk_rate = 392464;
+ mmc_info.mmc_dev_type = MMC_IS_SD_HC;
+ rpi3_sdhost_init(¶ms, &mmc_info);
+}
+
/*******************************************************************************
* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
+ /* Setup SDHost driver */
+ rpi3_sdhost_setup();
+
plat_rpi3_io_setup();
}
/* BL33 expects to receive the primary CPU MPID (through r0) */
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
+
+ /* Shutting down the SDHost driver to let BL33 drives SDHost.*/
+ rpi3_sdhost_stop();
break;
default:
#include "rpi3_private.h"
-#define BL31_END (uintptr_t)(&__BL31_END__)
-
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
#define RPI3_IO_GPIO_OFFSET ULL(0x00200000)
#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET)
+/*
+ * SDHost controller
+ */
+#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000)
+#define RPI3_SDHOST_BASE (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET)
+
/*
* Local interrupt controller
*/
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-PLAT_INCLUDES += -Iinclude/common/tbbr
-
BL2_SOURCES += drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \
#include <platform_def.h>
+#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include "../uniphier.h"
-#define BL32_END (unsigned long)(&__BL32_END__)
#define BL32_SIZE ((BL32_END) - (BL32_BASE))
void tsp_early_platform_setup(void)
#include "uniphier.h"
-#define BL2_END (unsigned long)(&__BL2_END__)
#define BL2_SIZE ((BL2_END) - (BL2_BASE))
static int uniphier_bl2_kick_scp;
#include <plat_private.h>
-#define BL31_END (unsigned long)(&__BL31_END__)
-
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
* BL33 specific defines.
******************************************************************************/
#ifndef PRELOADED_BL33_BASE
-# define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000
+# define PLAT_ARM_NS_IMAGE_BASE 0x8000000
#else
-# define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
+# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
#endif
/*******************************************************************************
#include <plat_private.h>
#include <platform_tsp.h>
-
-#define BL32_END (unsigned long)(&__BL32_END__)
-
/*******************************************************************************
* Initialize the UART
******************************************************************************/
projects / project / bcm63xx / atf.git / commitdiff