Add GICv3 ITS to FDTs

- The interrupt addresses need to be updated to work.

Change-Id: Icdd00177095ae9e4eb7b13718762f92e29b1465c

diff --git a/fdts/fvp-base-gicv3-psci.dtb b/fdts/fvp-base-gicv3-psci.dtb
index 678b45bb7588d63e37cf8e8e2a44265f28a21b21..5198cc7ea75ff7b6c0bf78a95f8311da3d247d22 100644 (file)
Binary files a/fdts/fvp-base-gicv3-psci.dtb and b/fdts/fvp-base-gicv3-psci.dtb differ

diff --git a/fdts/fvp-base-gicv3-psci.dts b/fdts/fvp-base-gicv3-psci.dts
index 98c74870405d27cc2aef56ee1f01355b9b25fcaf..8bafe2675ac561ac88b4dd53c7aae2127a781d0d 100644 (file)
--- a/fdts/fvp-base-gicv3-psci.dts
+++ b/fdts/fvp-base-gicv3-psci.dts
@@ -121,16 +121,25 @@
                */
        };
 
-       gic: interrupt-controller@2cf00000 {
+       gic: interrupt-controller@2f000000 {
                compatible = "arm,gic-v3";
                #interrupt-cells = <3>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
                interrupt-controller;
                reg = <0x0 0x2f000000 0 0x10000>,       // GICD
                      <0x0 0x2f100000 0 0x200000>,      // GICR
                      <0x0 0x2c000000 0 0x2000>,        // GICC
                      <0x0 0x2c010000 0 0x2000>,        // GICH
-                     <0x0 0x2c02F000 0 0x2000>;        // GICV
+                     <0x0 0x2c02f000 0 0x2000>;        // GICV
                interrupts = <1 9 4>;
+
+               its: its@2f020000 {
+                       compatible = "arm,gic-v3-its";
+                       msi-controller;
+                       reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
+               };
        };
 
        timer {
@@ -178,49 +187,49 @@
 
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 63>;
-               interrupt-map = <0 0  0 &gic 0  0 4>,
-                               <0 0  1 &gic 0  1 4>,
-                               <0 0  2 &gic 0  2 4>,
-                               <0 0  3 &gic 0  3 4>,
-                               <0 0  4 &gic 0  4 4>,
-                               <0 0  5 &gic 0  5 4>,
-                               <0 0  6 &gic 0  6 4>,
-                               <0 0  7 &gic 0  7 4>,
-                               <0 0  8 &gic 0  8 4>,
-                               <0 0  9 &gic 0  9 4>,
-                               <0 0 10 &gic 0 10 4>,
-                               <0 0 11 &gic 0 11 4>,
-                               <0 0 12 &gic 0 12 4>,
-                               <0 0 13 &gic 0 13 4>,
-                               <0 0 14 &gic 0 14 4>,
-                               <0 0 15 &gic 0 15 4>,
-                               <0 0 16 &gic 0 16 4>,
-                               <0 0 17 &gic 0 17 4>,
-                               <0 0 18 &gic 0 18 4>,
-                               <0 0 19 &gic 0 19 4>,
-                               <0 0 20 &gic 0 20 4>,
-                               <0 0 21 &gic 0 21 4>,
-                               <0 0 22 &gic 0 22 4>,
-                               <0 0 23 &gic 0 23 4>,
-                               <0 0 24 &gic 0 24 4>,
-                               <0 0 25 &gic 0 25 4>,
-                               <0 0 26 &gic 0 26 4>,
-                               <0 0 27 &gic 0 27 4>,
-                               <0 0 28 &gic 0 28 4>,
-                               <0 0 29 &gic 0 29 4>,
-                               <0 0 30 &gic 0 30 4>,
-                               <0 0 31 &gic 0 31 4>,
-                               <0 0 32 &gic 0 32 4>,
-                               <0 0 33 &gic 0 33 4>,
-                               <0 0 34 &gic 0 34 4>,
-                               <0 0 35 &gic 0 35 4>,
-                               <0 0 36 &gic 0 36 4>,
-                               <0 0 37 &gic 0 37 4>,
-                               <0 0 38 &gic 0 38 4>,
-                               <0 0 39 &gic 0 39 4>,
-                               <0 0 40 &gic 0 40 4>,
-                               <0 0 41 &gic 0 41 4>,
-                               <0 0 42 &gic 0 42 4>;
+               interrupt-map = <0 0  0 &gic 0 0 0  0 4>,
+                               <0 0  1 &gic 0 0 0  1 4>,
+                               <0 0  2 &gic 0 0 0  2 4>,
+                               <0 0  3 &gic 0 0 0  3 4>,
+                               <0 0  4 &gic 0 0 0  4 4>,
+                               <0 0  5 &gic 0 0 0  5 4>,
+                               <0 0  6 &gic 0 0 0  6 4>,
+                               <0 0  7 &gic 0 0 0  7 4>,
+                               <0 0  8 &gic 0 0 0  8 4>,
+                               <0 0  9 &gic 0 0 0  9 4>,
+                               <0 0 10 &gic 0 0 0 10 4>,
+                               <0 0 11 &gic 0 0 0 11 4>,
+                               <0 0 12 &gic 0 0 0 12 4>,
+                               <0 0 13 &gic 0 0 0 13 4>,
+                               <0 0 14 &gic 0 0 0 14 4>,
+                               <0 0 15 &gic 0 0 0 15 4>,
+                               <0 0 16 &gic 0 0 0 16 4>,
+                               <0 0 17 &gic 0 0 0 17 4>,
+                               <0 0 18 &gic 0 0 0 18 4>,
+                               <0 0 19 &gic 0 0 0 19 4>,
+                               <0 0 20 &gic 0 0 0 20 4>,
+                               <0 0 21 &gic 0 0 0 21 4>,
+                               <0 0 22 &gic 0 0 0 22 4>,
+                               <0 0 23 &gic 0 0 0 23 4>,
+                               <0 0 24 &gic 0 0 0 24 4>,
+                               <0 0 25 &gic 0 0 0 25 4>,
+                               <0 0 26 &gic 0 0 0 26 4>,
+                               <0 0 27 &gic 0 0 0 27 4>,
+                               <0 0 28 &gic 0 0 0 28 4>,
+                               <0 0 29 &gic 0 0 0 29 4>,
+                               <0 0 30 &gic 0 0 0 30 4>,
+                               <0 0 31 &gic 0 0 0 31 4>,
+                               <0 0 32 &gic 0 0 0 32 4>,
+                               <0 0 33 &gic 0 0 0 33 4>,
+                               <0 0 34 &gic 0 0 0 34 4>,
+                               <0 0 35 &gic 0 0 0 35 4>,
+                               <0 0 36 &gic 0 0 0 36 4>,
+                               <0 0 37 &gic 0 0 0 37 4>,
+                               <0 0 38 &gic 0 0 0 38 4>,
+                               <0 0 39 &gic 0 0 0 39 4>,
+                               <0 0 40 &gic 0 0 0 40 4>,
+                               <0 0 41 &gic 0 0 0 41 4>,
+                               <0 0 42 &gic 0 0 0 42 4>;
 
                /include/ "rtsm_ve-motherboard.dtsi"
        };

diff --git a/fdts/fvp-foundation-gicv3-psci.dtb b/fdts/fvp-foundation-gicv3-psci.dtb
index 29a7c742975feb9f239e87529fec1e4824f4eaea..c6472e000fd0bdb6c7e39c3038e875ab8d037c2f 100644 (file)
Binary files a/fdts/fvp-foundation-gicv3-psci.dtb and b/fdts/fvp-foundation-gicv3-psci.dtb differ

diff --git a/fdts/fvp-foundation-gicv3-psci.dts b/fdts/fvp-foundation-gicv3-psci.dts
index 3243c900e544d30e1d5a3ffad787fac8b9f25c2a..87ee3c01619fa57089ebc9877a593fc4edce162c 100644 (file)
--- a/fdts/fvp-foundation-gicv3-psci.dts
+++ b/fdts/fvp-foundation-gicv3-psci.dts
@@ -11,7 +11,7 @@
  * this list of conditions and the following disclaimer in the documentation
  * and/or other materials provided with the distribution.
  *
- * Neither the name of the ARM nor the names of its contributors may be used
+ * Neither the name of ARM nor the names of its contributors may be used
  * to endorse or promote products derived from this software without specific
  * prior written permission.
  *
@@ -95,16 +95,25 @@
                      <0x00000008 0x80000000 0 0x80000000>;
        };
 
-       gic: interrupt-controller@2cf00000 {
+       gic: interrupt-controller@2f000000 {
                compatible = "arm,gic-v3";
                #interrupt-cells = <3>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
                interrupt-controller;
                reg = <0x0 0x2f000000 0 0x10000>,       // GICD
                      <0x0 0x2f100000 0 0x200000>,      // GICR
                      <0x0 0x2c000000 0 0x2000>,        // GICC
                      <0x0 0x2c010000 0 0x2000>,        // GICH
-                     <0x0 0x2c02F000 0 0x2000>;        // GICV
+                     <0x0 0x2c02f000 0 0x2000>;        // GICV
                interrupts = <1 9 4>;
+
+               its: its@2f020000 {
+                       compatible = "arm,gic-v3-its";
+                       msi-controller;
+                       reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
+               };
        };
 
        timer {
@@ -152,49 +161,49 @@
 
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 63>;
-               interrupt-map = <0 0  0 &gic 0  0 4>,
-                               <0 0  1 &gic 0  1 4>,
-                               <0 0  2 &gic 0  2 4>,
-                               <0 0  3 &gic 0  3 4>,
-                               <0 0  4 &gic 0  4 4>,
-                               <0 0  5 &gic 0  5 4>,
-                               <0 0  6 &gic 0  6 4>,
-                               <0 0  7 &gic 0  7 4>,
-                               <0 0  8 &gic 0  8 4>,
-                               <0 0  9 &gic 0  9 4>,
-                               <0 0 10 &gic 0 10 4>,
-                               <0 0 11 &gic 0 11 4>,
-                               <0 0 12 &gic 0 12 4>,
-                               <0 0 13 &gic 0 13 4>,
-                               <0 0 14 &gic 0 14 4>,
-                               <0 0 15 &gic 0 15 4>,
-                               <0 0 16 &gic 0 16 4>,
-                               <0 0 17 &gic 0 17 4>,
-                               <0 0 18 &gic 0 18 4>,
-                               <0 0 19 &gic 0 19 4>,
-                               <0 0 20 &gic 0 20 4>,
-                               <0 0 21 &gic 0 21 4>,
-                               <0 0 22 &gic 0 22 4>,
-                               <0 0 23 &gic 0 23 4>,
-                               <0 0 24 &gic 0 24 4>,
-                               <0 0 25 &gic 0 25 4>,
-                               <0 0 26 &gic 0 26 4>,
-                               <0 0 27 &gic 0 27 4>,
-                               <0 0 28 &gic 0 28 4>,
-                               <0 0 29 &gic 0 29 4>,
-                               <0 0 30 &gic 0 30 4>,
-                               <0 0 31 &gic 0 31 4>,
-                               <0 0 32 &gic 0 32 4>,
-                               <0 0 33 &gic 0 33 4>,
-                               <0 0 34 &gic 0 34 4>,
-                               <0 0 35 &gic 0 35 4>,
-                               <0 0 36 &gic 0 36 4>,
-                               <0 0 37 &gic 0 37 4>,
-                               <0 0 38 &gic 0 38 4>,
-                               <0 0 39 &gic 0 39 4>,
-                               <0 0 40 &gic 0 40 4>,
-                               <0 0 41 &gic 0 41 4>,
-                               <0 0 42 &gic 0 42 4>;
+               interrupt-map = <0 0  0 &gic 0 0 0  0 4>,
+                               <0 0  1 &gic 0 0 0  1 4>,
+                               <0 0  2 &gic 0 0 0  2 4>,
+                               <0 0  3 &gic 0 0 0  3 4>,
+                               <0 0  4 &gic 0 0 0  4 4>,
+                               <0 0  5 &gic 0 0 0  5 4>,
+                               <0 0  6 &gic 0 0 0  6 4>,
+                               <0 0  7 &gic 0 0 0  7 4>,
+                               <0 0  8 &gic 0 0 0  8 4>,
+                               <0 0  9 &gic 0 0 0  9 4>,
+                               <0 0 10 &gic 0 0 0 10 4>,
+                               <0 0 11 &gic 0 0 0 11 4>,
+                               <0 0 12 &gic 0 0 0 12 4>,
+                               <0 0 13 &gic 0 0 0 13 4>,
+                               <0 0 14 &gic 0 0 0 14 4>,
+                               <0 0 15 &gic 0 0 0 15 4>,
+                               <0 0 16 &gic 0 0 0 16 4>,
+                               <0 0 17 &gic 0 0 0 17 4>,
+                               <0 0 18 &gic 0 0 0 18 4>,
+                               <0 0 19 &gic 0 0 0 19 4>,
+                               <0 0 20 &gic 0 0 0 20 4>,
+                               <0 0 21 &gic 0 0 0 21 4>,
+                               <0 0 22 &gic 0 0 0 22 4>,
+                               <0 0 23 &gic 0 0 0 23 4>,
+                               <0 0 24 &gic 0 0 0 24 4>,
+                               <0 0 25 &gic 0 0 0 25 4>,
+                               <0 0 26 &gic 0 0 0 26 4>,
+                               <0 0 27 &gic 0 0 0 27 4>,
+                               <0 0 28 &gic 0 0 0 28 4>,
+                               <0 0 29 &gic 0 0 0 29 4>,
+                               <0 0 30 &gic 0 0 0 30 4>,
+                               <0 0 31 &gic 0 0 0 31 4>,
+                               <0 0 32 &gic 0 0 0 32 4>,
+                               <0 0 33 &gic 0 0 0 33 4>,
+                               <0 0 34 &gic 0 0 0 34 4>,
+                               <0 0 35 &gic 0 0 0 35 4>,
+                               <0 0 36 &gic 0 0 0 36 4>,
+                               <0 0 37 &gic 0 0 0 37 4>,
+                               <0 0 38 &gic 0 0 0 38 4>,
+                               <0 0 39 &gic 0 0 0 39 4>,
+                               <0 0 40 &gic 0 0 0 40 4>,
+                               <0 0 41 &gic 0 0 0 41 4>,
+                               <0 0 42 &gic 0 0 0 42 4>;
 
                /include/ "fvp-foundation-motherboard.dtsi"
        };