arm: sync armada-xp dts files from Linux 5.0
authorChris Packham <judge.packham@gmail.com>
Fri, 15 Feb 2019 22:48:58 +0000 (11:48 +1300)
committerStefan Roese <sr@denx.de>
Fri, 12 Apr 2019 05:04:18 +0000 (07:04 +0200)
Bring in the Armada 370/XP dts/dtsi files from Linux. As U-Boot hasn't
got the new NAND driver the updating binding has not been included.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
arch/arm/dts/armada-370-xp.dtsi
arch/arm/dts/armada-xp-gp.dts
arch/arm/dts/armada-xp-maxbcm.dts
arch/arm/dts/armada-xp-mv78230.dtsi
arch/arm/dts/armada-xp-mv78260.dtsi
arch/arm/dts/armada-xp-mv78460.dtsi
arch/arm/dts/armada-xp-synology-ds414.dts
arch/arm/dts/armada-xp-theadorable.dts
arch/arm/dts/armada-xp.dtsi

index 0b2a78d393010fbdbfb400ddad63a4dba2d9ff18..e4c35d4e98f4d3078fd2266c1332cbfeae44030b 100644 (file)
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
  *
@@ -8,50 +9,10 @@
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  * Ben Dooks <ben.dooks@codethink.co.uk>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- *
  * This file contains the definitions that are common to the Armada
  * 370 and Armada XP SoC.
  */
 
-/include/ "skeleton64.dtsi"
-
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
 / {
@@ -86,7 +47,7 @@
                pcie-mem-aperture = <0xf8000000 0x7e00000>;
                pcie-io-aperture  = <0xffe00000 0x100000>;
 
-               devbus-bootcs {
+               devbus_bootcs: devbus-bootcs {
                        compatible = "marvell,mvebu-devbus";
                        reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
                        ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -96,7 +57,7 @@
                        status = "disabled";
                };
 
-               devbus-cs0 {
+               devbus_cs0: devbus-cs0 {
                        compatible = "marvell,mvebu-devbus";
                        reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
                        ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
                        status = "disabled";
                };
 
-               devbus-cs1 {
+               devbus_cs1: devbus-cs1 {
                        compatible = "marvell,mvebu-devbus";
                        reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
                        ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
                        status = "disabled";
                };
 
-               devbus-cs2 {
+               devbus_cs2: devbus-cs2 {
                        compatible = "marvell,mvebu-devbus";
                        reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
                        ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
                        status = "disabled";
                };
 
-               devbus-cs3 {
+               devbus_cs3: devbus-cs3 {
                        compatible = "marvell,mvebu-devbus";
                        reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
                        ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
-                       u-boot,dm-pre-reloc;
 
-                       rtc@10300 {
+                       rtc: rtc@10300 {
                                compatible = "marvell,orion-rtc";
                                reg = <0x10300 0x20>;
                                interrupts = <50>;
                        };
 
-                       spi0: spi@10600 {
-                               reg = <0x10600 0x28>;
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               cell-index = <0>;
-                               interrupts = <30>;
-                               clocks = <&coreclk 0>;
-                               status = "disabled";
-                       };
-
-                       spi1: spi@10680 {
-                               reg = <0x10680 0x28>;
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               cell-index = <1>;
-                               interrupts = <92>;
-                               clocks = <&coreclk 0>;
-                               status = "disabled";
-                       };
-
                        i2c0: i2c@11000 {
                                compatible = "marvell,mv64xxx-i2c";
                                #address-cells = <1>;
                                msi-controller;
                        };
 
-                       coherency-fabric@20200 {
+                       coherencyfab: coherency-fabric@20200 {
                                compatible = "marvell,coherency-fabric";
                                reg = <0x20200 0xb0>, <0x21010 0x1c>;
                        };
 
-                       timer@20300 {
+                       timer: timer@20300 {
                                reg = <0x20300 0x30>, <0x21040 0x30>;
                                interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
                        };
 
-                       watchdog@20300 {
+                       watchdog: watchdog@20300 {
                                reg = <0x20300 0x34>, <0x20704 0x4>;
                        };
 
-                       pmsu@22000 {
+                       cpurst: cpurst@20800 {
+                               compatible = "marvell,armada-370-cpu-reset";
+                               reg = <0x20800 0x8>;
+                       };
+
+                       pmsu: pmsu@22000 {
                                compatible = "marvell,armada-370-pmsu";
                                reg = <0x22000 0x1000>;
                        };
 
-                       usb@50000 {
+                       usb0: usb@50000 {
                                compatible = "marvell,orion-ehci";
                                reg = <0x50000 0x500>;
                                interrupts = <45>;
                                status = "disabled";
                        };
 
-                       usb@51000 {
+                       usb1: usb@51000 {
                                compatible = "marvell,orion-ehci";
                                reg = <0x51000 0x500>;
                                interrupts = <46>;
                                status = "disabled";
                        };
 
-                       mdio: mdio {
+                       mdio: mdio@72004 {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "marvell,orion-mdio";
                                status = "disabled";
                        };
 
-                       sata@a0000 {
+                       sata: sata@a0000 {
                                compatible = "marvell,armada-370-sata";
                                reg = <0xa0000 0x5000>;
                                interrupts = <55>;
                                status = "disabled";
                        };
 
-                       mvsdio@d4000 {
+                       sdio: mvsdio@d4000 {
                                compatible = "marvell,orion-sdio";
                                reg = <0xd4000 0x200>;
                                interrupts = <54>;
                                status = "disabled";
                        };
                };
+
+               spi0: spi@10600 {
+                       reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
+                             <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
+                             <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
+                             <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
+                             <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
+                             <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
+                             <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
+                             <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
+                             <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       interrupts = <30>;
+                       clocks = <&coreclk 0>;
+                       status = "disabled";
+               };
+
+               spi1: spi@10680 {
+                       reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
+                             <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
+                             <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
+                             <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
+                             <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
+                             <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
+                             <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
+                             <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
+                             <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       interrupts = <92>;
+                       clocks = <&coreclk 0>;
+                       status = "disabled";
+               };
        };
 
        clocks {
index 27799d1254eadc1f9056a17184195449c5cd8624..1139e9469a83792efc102ff2c8dd375d1c5591b3 100644 (file)
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree file for Marvell Armada XP development board
  * (DB-MV784MP-GP)
@@ -8,44 +9,6 @@
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- *
  * Note: this Device Tree assumes that the bootloader has remapped the
  * internal registers to 0xf1000000 (instead of the default
  * 0xd0000000). The 0xf1000000 is the default used by the recent,
                stdout-path = "serial0:115200n8";
        };
 
-       aliases {
-               spi0 = &spi0;
-       };
-
-       memory {
+       memory@0 {
                device_type = "memory";
                /*
                  * 8 GB of plug-in RAM modules by default.The amount
        soc {
                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-                         MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+                         MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
+                         MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+                         MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
+                         MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
 
                devbus-bootcs {
                        status = "okay";
                        };
                };
 
-               pcie-controller {
-                       status = "okay";
-
-                       /*
-                        * The 3 slots are physically present as
-                        * standard PCIe slots on the board.
-                        */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-                       pcie@9,0 {
-                               /* Port 2, Lane 0 */
-                               status = "okay";
-                       };
-                       pcie@10,0 {
-                               /* Port 3, Lane 0 */
-                               status = "okay";
-                       };
-               };
-
                internal-regs {
                        serial@12000 {
                                status = "okay";
-                               u-boot,dm-pre-reloc;
                        };
                        serial@12100 {
                                status = "okay";
                                status = "okay";
                        };
 
-                       mdio {
-                               phy0: ethernet-phy@0 {
-                                       reg = <16>;
-                               };
-
-                               phy1: ethernet-phy@1 {
-                                       reg = <17>;
-                               };
-
-                               phy2: ethernet-phy@2 {
-                                       reg = <18>;
-                               };
-
-                               phy3: ethernet-phy@3 {
-                                       reg = <19>;
-                               };
-                       };
-
                        ethernet@70000 {
                                status = "okay";
                                phy = <&phy0>;
                                phy-mode = "qsgmii";
+                               buffer-manager = <&bm>;
+                               bm,pool-long = <0>;
                        };
                        ethernet@74000 {
                                status = "okay";
                                phy = <&phy1>;
                                phy-mode = "qsgmii";
+                               buffer-manager = <&bm>;
+                               bm,pool-long = <1>;
                        };
                        ethernet@30000 {
                                status = "okay";
                                phy = <&phy2>;
                                phy-mode = "qsgmii";
+                               buffer-manager = <&bm>;
+                               bm,pool-long = <2>;
                        };
                        ethernet@34000 {
                                status = "okay";
                                phy = <&phy3>;
                                phy-mode = "qsgmii";
+                               buffer-manager = <&bm>;
+                               bm,pool-long = <3>;
                        };
 
                        /* Front-side USB slot */
                                status = "okay";
                        };
 
-                       spi0: spi@10600 {
+                       bm@c0000 {
                                status = "okay";
-                               u-boot,dm-pre-reloc;
-
-                               spi-flash@0 {
-                                       u-boot,dm-pre-reloc;
-                                       #address-cells = <1>;
-                                       #size-cells = <1>;
-                                       compatible = "n25q128a13", "jedec,spi-nor";
-                                       reg = <0>; /* Chip select 0 */
-                                       spi-max-frequency = <108000000>;
-                               };
                        };
 
                        nand@d0000 {
                                status = "okay";
+                               label = "pxa3xx_nand-0";
                                num-cs = <1>;
                                marvell,nand-keep-config;
-                               marvell,nand-enable-arbiter;
                                nand-on-flash-bbt;
                        };
                };
+
+               bm-bppi {
+                       status = "okay";
+               };
+       };
+};
+
+&pciec {
+       status = "okay";
+
+       /*
+        * The 3 slots are physically present as
+        * standard PCIe slots on the board.
+        */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+       pcie@9,0 {
+               /* Port 2, Lane 0 */
+               status = "okay";
+       };
+       pcie@a,0 {
+               /* Port 3, Lane 0 */
+               status = "okay";
+       };
+};
+
+&mdio {
+       phy0: ethernet-phy@0 {
+               reg = <16>;
+       };
+
+       phy1: ethernet-phy@1 {
+               reg = <17>;
+       };
+
+       phy2: ethernet-phy@2 {
+               reg = <18>;
+       };
+
+       phy3: ethernet-phy@3 {
+               reg = <19>;
+       };
+};
+
+&spi0 {
+       status = "okay";
+
+       spi-flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "n25q128a13", "jedec,spi-nor";
+               reg = <0>; /* Chip select 0 */
+               spi-max-frequency = <108000000>;
        };
 };
index d7d7f65c85fec623f7a66fcd4efdc12fa0216d47..921eb708625433ca6f3d471c67d67f9c02ae392d 100644 (file)
                                status = "okay";
                        };
 
-                       spi0: spi@10600 {
-                               status = "okay";
-
-                               spi-flash@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <1>;
-                                       compatible = "n25q128a13", "jedec,spi-nor";
-                                       reg = <0>; /* Chip select 0 */
-                                       spi-max-frequency = <108000000>;
-                               };
-                       };
-
                        nand@d0000 {
                                status = "okay";
                                num-cs = <1>;
                };
        };
 };
+
+&spi0 {
+       status = "okay";
+
+       spi-flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "n25q128a13", "jedec,spi-nor";
+               reg = <0>; /* Chip select 0 */
+               spi-max-frequency = <108000000>;
+       };
+};
index f6bab9fb20a908e305e5c84ca296c9ed22e37dc6..8558bf6bb54c603c16b8a5a987c991413e3297c8 100644 (file)
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada XP family SoC
  *
@@ -5,44 +6,6 @@
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- *
  * Contains definitions specific to the Armada XP MV78230 SoC that are not
  * common to all Armada XP SoCs.
  */
 
                internal-regs {
                        gpio0: gpio@18100 {
-                               compatible = "marvell,orion-gpio";
-                               reg = <0x18100 0x40>;
+                               compatible = "marvell,armada-370-gpio",
+                                            "marvell,orion-gpio";
+                               reg = <0x18100 0x40>, <0x181c0 0x08>;
+                               reg-names = "gpio", "pwm";
                                ngpios = <32>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                               #pwm-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                interrupts = <82>, <83>, <84>, <85>;
+                               clocks = <&coreclk 0>;
                        };
 
                        gpio1: gpio@18140 {
-                               compatible = "marvell,orion-gpio";
-                               reg = <0x18140 0x40>;
+                               compatible = "marvell,armada-370-gpio",
+                                            "marvell,orion-gpio";
+                               reg = <0x18140 0x40>, <0x181c8 0x08>;
+                               reg-names = "gpio", "pwm";
                                ngpios = <17>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                               #pwm-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                interrupts = <87>, <88>, <89>;
+                               clocks = <&coreclk 0>;
                        };
                };
        };
index d39231f69d9a960f011e27f44974d2afe2f270c3..2d85fe8ac327296420e1050228e88fa0df48d79a 100644 (file)
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada XP family SoC
  *
@@ -5,44 +6,6 @@
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- *
  * Contains definitions specific to the Armada XP MV78260 SoC that are not
  * common to all Armada XP SoCs.
  */
 
                internal-regs {
                        gpio0: gpio@18100 {
-                               compatible = "marvell,orion-gpio";
-                               reg = <0x18100 0x40>;
+                               compatible = "marvell,armada-370-gpio",
+                                            "marvell,orion-gpio";
+                               reg = <0x18100 0x40>, <0x181c0 0x08>;
+                               reg-names = "gpio", "pwm";
                                ngpios = <32>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                               #pwm-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                interrupts = <82>, <83>, <84>, <85>;
+                               clocks = <&coreclk 0>;
                        };
 
                        gpio1: gpio@18140 {
-                               compatible = "marvell,orion-gpio";
-                               reg = <0x18140 0x40>;
+                               compatible = "marvell,armada-370-gpio",
+                                            "marvell,orion-gpio";
+                               reg = <0x18140 0x40>, <0x181c8 0x08>;
+                               reg-names = "gpio", "pwm";
                                ngpios = <32>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                               #pwm-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                interrupts = <87>, <88>, <89>, <90>;
+                               clocks = <&coreclk 0>;
                        };
 
                        gpio2: gpio@18180 {
-                               compatible = "marvell,orion-gpio";
+                               compatible = "marvell,armada-370-gpio",
+                                            "marvell,orion-gpio";
                                reg = <0x18180 0x40>;
                                ngpios = <3>;
                                gpio-controller;
index c642565d1bc68119dfa5c470fdc7e4d0c63865b0..230a3fd36b3048937c760784ec2fd619f49f9bdb 100644 (file)
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada XP family SoC
  *
@@ -5,44 +6,6 @@
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- *
  * Contains definitions specific to the Armada XP MV78460 SoC that are not
  * common to all Armada XP SoCs.
  */
 
                internal-regs {
                        gpio0: gpio@18100 {
-                               compatible = "marvell,orion-gpio";
-                               reg = <0x18100 0x40>;
+                               compatible = "marvell,armada-370-gpio",
+                                            "marvell,orion-gpio";
+                               reg = <0x18100 0x40>, <0x181c0 0x08>;
+                               reg-names = "gpio", "pwm";
                                ngpios = <32>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                               #pwm-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                interrupts = <82>, <83>, <84>, <85>;
+                               clocks = <&coreclk 0>;
                        };
 
                        gpio1: gpio@18140 {
-                               compatible = "marvell,orion-gpio";
-                               reg = <0x18140 0x40>;
+                               compatible = "marvell,armada-370-gpio",
+                                            "marvell,orion-gpio";
+                               reg = <0x18140 0x40>, <0x181c8 0x08>;
+                               reg-names = "gpio", "pwm";
                                ngpios = <32>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                               #pwm-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                interrupts = <87>, <88>, <89>, <90>;
+                               clocks = <&coreclk 0>;
                        };
 
                        gpio2: gpio@18180 {
-                               compatible = "marvell,orion-gpio";
+                               compatible = "marvell,armada-370-gpio",
+                                            "marvell,orion-gpio";
                                reg = <0x18180 0x40>;
                                ngpios = <3>;
                                gpio-controller;
index 0a60ddfa4149ee75da08ef732bf5699544c7131c..861967cd7e8728124f0e336819bf4c034b930a56 100644 (file)
@@ -1,13 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree file for Synology DS414
  *
  * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
  * Note: this Device Tree assumes that the bootloader has remapped the
  * internal registers to 0xf1000000 (instead of the old 0xd0000000).
  * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
                spi0 = &spi0;
        };
 
-       memory {
+       memory@0 {
                device_type = "memory";
                reg = <0 0x00000000 0 0x40000000>; /* 1GB */
        };
 
        soc {
                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
-                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
-
-               pcie-controller {
-                       status = "okay";
-
-                       /*
-                        * Connected to Marvell 88SX7042 SATA-II controller
-                        * handling the four disks.
-                        */
-                       pcie@1,0 {
-                               /* Port 0, Lane 0 */
-                               status = "okay";
-                       };
-
-                       /*
-                        * Connected to EtronTech EJ168A XHCI controller
-                        * providing the two rear USB 3.0 ports.
-                        */
-                       pcie@5,0 {
-                               /* Port 1, Lane 0 */
-                               status = "okay";
-                       };
-               };
+                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                         MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+                         MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
                internal-regs {
 
                                status = "disabled";
                        };
 
-                       spi0: spi@10600 {
-                               status = "okay";
-                               u-boot,dm-pre-reloc;
-
-                               spi-flash@0 {
-                                       u-boot,dm-pre-reloc;
-                                       #address-cells = <1>;
-                                       #size-cells = <1>;
-                                       compatible = "micron,n25q064";
-                                       reg = <0>; /* Chip select 0 */
-                                       spi-max-frequency = <20000000>;
-
-                                       /*
-                                        * Warning!
-                                        *
-                                        * Synology u-boot uses its compiled-in environment
-                                        * and it seems Synology did not care to change u-boot
-                                        * default configuration in order to allow saving a
-                                        * modified environment at a sensible location. So,
-                                        * if you do a 'saveenv' under u-boot, your modified
-                                        * environment will be saved at 1MB after the start
-                                        * of the flash, i.e. in the middle of the uImage.
-                                        * For that reason, it is strongly advised not to
-                                        * change the default environment, unless you know
-                                        * what you are doing.
-                                        */
-                                       partition@00000000 { /* u-boot */
-                                               label = "RedBoot";
-                                               reg = <0x00000000 0x000d0000>; /* 832KB */
-                                       };
-
-                                       partition@000c0000 { /* uImage */
-                                               label = "zImage";
-                                               reg = <0x000d0000 0x002d0000>; /* 2880KB */
-                                       };
-
-                                       partition@003a0000 { /* uInitramfs */
-                                               label = "rd.gz";
-                                               reg = <0x003a0000 0x00430000>; /* 4250KB */
-                                       };
-
-                                       partition@007d0000 { /* MAC address and serial number */
-                                               label = "vendor";
-                                               reg = <0x007d0000 0x00010000>; /* 64KB */
-                                       };
-
-                                       partition@007e0000 {
-                                               label = "RedBoot config";
-                                               reg = <0x007e0000 0x00010000>; /* 64KB */
-                                       };
-
-                                       partition@007f0000 {
-                                               label = "FIS directory";
-                                               reg = <0x007f0000 0x00010000>; /* 64KB */
-                                       };
-                               };
-                       };
-
                        i2c@11000 {
                                clock-frequency = <400000>;
                                status = "okay";
                                status = "okay";
                        };
 
-                       mdio {
-                               phy0: ethernet-phy@0 { /* Marvell 88E1512 */
-                                       reg = <0>;
-                               };
-
-                               phy1: ethernet-phy@1 { /* Marvell 88E1512 */
-                                       reg = <1>;
-                               };
-                       };
-
                        ethernet@70000 {
                                status = "okay";
                                pinctrl-0 = <&ge0_rgmii_pins>;
                             &sata3_pwr_pin &sata4_pwr_pin>;
                pinctrl-names = "default";
 
-               sata1_regulator: sata1-regulator {
+               sata1_regulator: sata1-regulator@1 {
                        compatible = "regulator-fixed";
                        reg = <1>;
                        regulator-name = "SATA1 Power";
                        gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
                };
 
-               sata2_regulator: sata2-regulator {
+               sata2_regulator: sata2-regulator@2 {
                        compatible = "regulator-fixed";
                        reg = <2>;
                        regulator-name = "SATA2 Power";
                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
                };
 
-               sata3_regulator: sata3-regulator {
+               sata3_regulator: sata3-regulator@3 {
                        compatible = "regulator-fixed";
                        reg = <3>;
                        regulator-name = "SATA3 Power";
                        gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
                };
 
-               sata4_regulator: sata4-regulator {
+               sata4_regulator: sata4-regulator@4 {
                        compatible = "regulator-fixed";
                        reg = <4>;
                        regulator-name = "SATA4 Power";
        };
 };
 
+&pciec {
+       status = "okay";
+
+       /*
+        * Connected to Marvell 88SX7042 SATA-II controller
+        * handling the four disks.
+        */
+       pcie@1,0 {
+               /* Port 0, Lane 0 */
+               status = "okay";
+       };
+
+       /*
+        * Connected to EtronTech EJ168A XHCI controller
+        * providing the two rear USB 3.0 ports.
+        */
+       pcie@5,0 {
+               /* Port 1, Lane 0 */
+               status = "okay";
+       };
+};
+
+
+&mdio {
+       phy0: ethernet-phy@0 { /* Marvell 88E1512 */
+               reg = <0>;
+       };
+
+       phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+               reg = <1>;
+       };
+};
+
 &pinctrl {
        sata1_pwr_pin: sata1-pwr-pin {
                marvell,pins = "mpp42";
                marvell,function = "gpio";
        };
 };
+
+&spi0 {
+       status = "okay";
+
+       spi-flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "micron,n25q064", "jedec,spi-nor";
+               reg = <0>; /* Chip select 0 */
+               spi-max-frequency = <20000000>;
+
+               /*
+                * Warning!
+                *
+                * Synology u-boot uses its compiled-in environment
+                * and it seems Synology did not care to change u-boot
+                * default configuration in order to allow saving a
+                * modified environment at a sensible location. So,
+                * if you do a 'saveenv' under u-boot, your modified
+                * environment will be saved at 1MB after the start
+                * of the flash, i.e. in the middle of the uImage.
+                * For that reason, it is strongly advised not to
+                * change the default environment, unless you know
+                * what you are doing.
+                */
+               partition@0 { /* u-boot */
+                       label = "RedBoot";
+                       reg = <0x00000000 0x000d0000>; /* 832KB */
+               };
+
+               partition@c0000 { /* uImage */
+                       label = "zImage";
+                       reg = <0x000d0000 0x002d0000>; /* 2880KB */
+               };
+
+               partition@3a0000 { /* uInitramfs */
+                       label = "rd.gz";
+                       reg = <0x003a0000 0x00430000>; /* 4250KB */
+               };
+
+               partition@7d0000 { /* MAC address and serial number */
+                       label = "vendor";
+                       reg = <0x007d0000 0x00010000>; /* 64KB */
+               };
+
+               partition@7e0000 {
+                       label = "RedBoot config";
+                       reg = <0x007e0000 0x00010000>; /* 64KB */
+               };
+
+               partition@7f0000 {
+                       label = "FIS directory";
+                       reg = <0x007f0000 0x00010000>; /* 64KB */
+               };
+       };
+};
index 5695e9b758569234dd4dcb6ffeb7e0af39583f65..bcb4bfdd5c198cdc809a808ce2317cfecb0cb9c7 100644 (file)
                                status = "okay";
                        };
 
-                       spi0: spi@10600 {
-                               status = "okay";
-                               u-boot,dm-pre-reloc;
-
-                               spi-flash@0 {
-                                       u-boot,dm-pre-reloc;
-                                       #address-cells = <1>;
-                                       #size-cells = <1>;
-                                       compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
-                                       reg = <0>; /* Chip select 0 */
-                                       spi-max-frequency = <27777777>;
-                               };
-
-                               fpga@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <1>;
-                                       compatible = "spi-generic-device";
-                                       reg = <1>; /* Chip select 1 */
-                                       spi-max-frequency = <27777777>;
-                               };
-                       };
-
-                       spi1: spi@10680 {
-                               status = "okay";
-
-                               fpga@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <1>;
-                                       compatible = "spi-generic-device";
-                                       reg = <0>; /* Chip select 0 */
-                                       spi-max-frequency = <27777777>;
-                               };
-                       };
-
                        /* The LCD controller is only used on this board */
                        lcd0: lcd-controller@e0000 {
                                compatible = "marvell,armada-xp-lcd";
        };
 };
 
+&spi0 {
+       status = "okay";
+       u-boot,dm-pre-reloc;
+
+       spi-flash@0 {
+               u-boot,dm-pre-reloc;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
+               reg = <0>; /* Chip select 0 */
+               spi-max-frequency = <27777777>;
+       };
+
+       fpga@1 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-generic-device";
+               reg = <1>; /* Chip select 1 */
+               spi-max-frequency = <27777777>;
+       };
+};
+
+&spi1 {
+       status = "okay";
+
+       fpga@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-generic-device";
+               reg = <0>; /* Chip select 0 */
+               spi-max-frequency = <27777777>;
+       };
+};
+
+
 &pciec {
        status = "okay";
 
index 3fac39e41d789199947a3927bf7c4630ea14c275..d856d96022727a7802fcd71c5b526a309d0a0bda 100644 (file)
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada XP family SoC
  *
@@ -8,44 +9,6 @@
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  * Ben Dooks <ben.dooks@codethink.co.uk>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- *
  * Contains definitions specific to the Armada XP SoC that are not
  * common to all Armada SoCs.
  */
@@ -53,6 +16,9 @@
 #include "armada-370-xp.dtsi"
 
 / {
+       #address-cells = <2>;
+       #size-cells = <2>;
+
        model = "Marvell Armada XP family SoC";
        compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
                };
 
                internal-regs {
-                       sdramc@1400 {
+                       sdramc: sdramc@1400 {
                                compatible = "marvell,armada-xp-sdram-controller";
                                reg = <0x1400 0x500>;
                        };
 
-                       L2: l2-cache {
+                       L2: l2-cache@8000 {
                                compatible = "marvell,aurora-system-cache";
                                reg = <0x08000 0x1000>;
                                cache-id-part = <0x100>;
                                wt-override;
                        };
 
-                       spi0: spi@10600 {
-                               compatible = "marvell,armada-xp-spi",
-                                               "marvell,orion-spi";
-                               pinctrl-0 = <&spi0_pins>;
-                               pinctrl-names = "default";
-                       };
-
-                       spi1: spi@10680 {
-                               compatible = "marvell,armada-xp-spi",
-                                               "marvell,orion-spi";
-                       };
-
-
-                       i2c0: i2c@11000 {
-                               compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
-                               reg = <0x11000 0x100>;
-                       };
-
-                       i2c1: i2c@11100 {
-                               compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
-                               reg = <0x11100 0x100>;
-                       };
-
                        uart2: serial@12200 {
                                compatible = "snps,dw-apb-uart";
                                pinctrl-0 = <&uart2_pins>;
                                status = "disabled";
                        };
 
-                       system-controller@18200 {
+                       systemc: system-controller@18200 {
                                compatible = "marvell,armada-370-xp-system-controller";
                                reg = <0x18200 0x500>;
                        };
                                #clock-cells = <1>;
                        };
 
-                       thermal@182b0 {
+                       thermal: thermal@182b0 {
                                compatible = "marvell,armadaxp-thermal";
                                reg = <0x182b0 0x4
                                        0x184d0 0x4>;
                                clocks = <&coreclk 1>;
                        };
 
-                       interrupt-controller@20a00 {
-                             reg = <0x20a00 0x2d0>, <0x21070 0x58>;
-                       };
-
-                       timer@20300 {
-                               compatible = "marvell,armada-xp-timer";
-                               clocks = <&coreclk 2>, <&refclk>;
-                               clock-names = "nbclk", "fixed";
-                       };
-
-                       watchdog@20300 {
-                               compatible = "marvell,armada-xp-wdt";
-                               clocks = <&coreclk 2>, <&refclk>;
-                               clock-names = "nbclk", "fixed";
-                       };
-
-                       cpurst@20800 {
-                               compatible = "marvell,armada-370-cpu-reset";
-                               reg = <0x20800 0x20>;
+                       cpu-config@21000 {
+                               compatible = "marvell,armada-xp-cpu-config";
+                               reg = <0x21000 0x8>;
                        };
 
                        eth2: ethernet@30000 {
                                status = "disabled";
                        };
 
-                       usb@50000 {
-                               clocks = <&gateclk 18>;
-                       };
-
-                       usb@51000 {
-                               clocks = <&gateclk 19>;
-                       };
-
-                       usb@52000 {
+                       usb2: usb@52000 {
                                compatible = "marvell,orion-ehci";
                                reg = <0x52000 0x500>;
                                interrupts = <47>;
                                status = "disabled";
                        };
 
-                       xor@60900 {
+                       xor1: xor@60900 {
                                compatible = "marvell,orion-xor";
                                reg = <0x60900 0x100
                                       0x60b00 0x100>;
                                compatible = "marvell,armada-xp-neta";
                        };
 
-                       xor@f0900 {
+                       cesa: crypto@90000 {
+                               compatible = "marvell,armada-xp-crypto";
+                               reg = <0x90000 0x10000>;
+                               reg-names = "regs";
+                               interrupts = <48>, <49>;
+                               clocks = <&gateclk 23>, <&gateclk 23>;
+                               clock-names = "cesa0", "cesa1";
+                               marvell,crypto-srams = <&crypto_sram0>,
+                                                      <&crypto_sram1>;
+                               marvell,crypto-sram-size = <0x800>;
+                       };
+
+                       bm: bm@c0000 {
+                               compatible = "marvell,armada-380-neta-bm";
+                               reg = <0xc0000 0xac>;
+                               clocks = <&gateclk 13>;
+                               internal-mem = <&bm_bppi>;
+                               status = "disabled";
+                       };
+
+                       xor0: xor@f0900 {
                                compatible = "marvell,orion-xor";
                                reg = <0xF0900 0x100
                                       0xF0B00 0x100>;
                                };
                        };
                };
+
+               crypto_sram0: sa-sram0 {
+                       compatible = "mmio-sram";
+                       reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
+                       clocks = <&gateclk 23>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
+               };
+
+               crypto_sram1: sa-sram1 {
+                       compatible = "mmio-sram";
+                       reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
+                       clocks = <&gateclk 23>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
+               };
+
+               bm_bppi: bm-bppi {
+                       compatible = "mmio-sram";
+                       reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
+                       ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       clocks = <&gateclk 13>;
+                       no-memory-wc;
+                       status = "disabled";
+               };
        };
 
        clocks {
        };
 };
 
+&i2c0 {
+       compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+       reg = <0x11000 0x100>;
+};
+
+&i2c1 {
+       compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+       reg = <0x11100 0x100>;
+};
+
+&mpic {
+       reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+};
+
+&timer {
+       compatible = "marvell,armada-xp-timer";
+       clocks = <&coreclk 2>, <&refclk>;
+       clock-names = "nbclk", "fixed";
+};
+
+&watchdog {
+       compatible = "marvell,armada-xp-wdt";
+       clocks = <&coreclk 2>, <&refclk>;
+       clock-names = "nbclk", "fixed";
+};
+
+&cpurst {
+       reg = <0x20800 0x20>;
+};
+
+&usb0 {
+       clocks = <&gateclk 18>;
+};
+
+&usb1 {
+       clocks = <&gateclk 19>;
+};
+
 &pinctrl {
        ge0_gmii_pins: ge0-gmii-pins {
                marvell,pins =
                marvell,function = "spi0";
        };
 
+       spi1_pins: spi1-pins {
+               marvell,pins = "mpp13", "mpp14",
+                              "mpp16", "mpp17";
+               marvell,function = "spi1";
+       };
+
        uart2_pins: uart2-pins {
                marvell,pins = "mpp42", "mpp43";
                marvell,function = "uart2";
                marvell,function = "uart3";
        };
 };
+
+&spi0 {
+       compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+       pinctrl-0 = <&spi0_pins>;
+       pinctrl-names = "default";
+};
+
+&spi1 {
+       compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+       pinctrl-0 = <&spi1_pins>;
+       pinctrl-names = "default";
+};