+++ /dev/null
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Defines a simple and generic interface to access eMMC device.
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <debug.h>
-#include <emmc.h>
-#include <errno.h>
-#include <string.h>
-#include <utils.h>
-
-static const emmc_ops_t *ops;
-static unsigned int emmc_ocr_value;
-static emmc_csd_t emmc_csd;
-static unsigned int emmc_flags;
-
-static int is_cmd23_enabled(void)
-{
- return (!!(emmc_flags & EMMC_FLAG_CMD23));
-}
-
-static int emmc_device_state(void)
-{
- emmc_cmd_t cmd;
- int ret;
-
- do {
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD13;
- cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
- cmd.resp_type = EMMC_RESPONSE_R1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
- assert((cmd.resp_data[0] & STATUS_SWITCH_ERROR) == 0);
- /* Ignore improbable errors in release builds */
- (void)ret;
- } while ((cmd.resp_data[0] & STATUS_READY_FOR_DATA) == 0);
- return EMMC_GET_STATE(cmd.resp_data[0]);
-}
-
-static void emmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
-{
- emmc_cmd_t cmd;
- int ret, state;
-
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD6;
- cmd.cmd_arg = EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
- EXTCSD_VALUE(value) | 1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- /* wait to exit PRG state */
- do {
- state = emmc_device_state();
- } while (state == EMMC_STATE_PRG);
- /* Ignore improbable errors in release builds */
- (void)ret;
-}
-
-static void emmc_set_ios(int clk, int bus_width)
-{
- int ret;
-
- /* set IO speed & IO bus width */
- if (emmc_csd.spec_vers == 4)
- emmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH, bus_width);
- ret = ops->set_ios(clk, bus_width);
- assert(ret == 0);
- /* Ignore improbable errors in release builds */
- (void)ret;
-}
-
-static int emmc_enumerate(int clk, int bus_width)
-{
- emmc_cmd_t cmd;
- int ret, state;
-
- ops->init();
-
- /* CMD0: reset to IDLE */
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD0;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- while (1) {
- /* CMD1: get OCR register */
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD1;
- cmd.cmd_arg = OCR_SECTOR_MODE | OCR_VDD_MIN_2V7 |
- OCR_VDD_MIN_1V7;
- cmd.resp_type = EMMC_RESPONSE_R3;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
- emmc_ocr_value = cmd.resp_data[0];
- if (emmc_ocr_value & OCR_POWERUP)
- break;
- }
-
- /* CMD2: Card Identification */
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD2;
- cmd.resp_type = EMMC_RESPONSE_R2;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- /* CMD3: Set Relative Address */
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD3;
- cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
- cmd.resp_type = EMMC_RESPONSE_R1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- /* CMD9: CSD Register */
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD9;
- cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
- cmd.resp_type = EMMC_RESPONSE_R2;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
- memcpy(&emmc_csd, &cmd.resp_data, sizeof(cmd.resp_data));
-
- /* CMD7: Select Card */
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD7;
- cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET;
- cmd.resp_type = EMMC_RESPONSE_R1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
- /* wait to TRAN state */
- do {
- state = emmc_device_state();
- } while (state != EMMC_STATE_TRAN);
-
- emmc_set_ios(clk, bus_width);
- return ret;
-}
-
-size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size)
-{
- emmc_cmd_t cmd;
- int ret;
-
- assert((ops != 0) &&
- (ops->read != 0) &&
- ((buf & EMMC_BLOCK_MASK) == 0) &&
- ((size & EMMC_BLOCK_MASK) == 0));
-
- inv_dcache_range(buf, size);
- ret = ops->prepare(lba, buf, size);
- assert(ret == 0);
-
- if (is_cmd23_enabled()) {
- zeromem(&cmd, sizeof(emmc_cmd_t));
- /* set block count */
- cmd.cmd_idx = EMMC_CMD23;
- cmd.cmd_arg = size / EMMC_BLOCK_SIZE;
- cmd.resp_type = EMMC_RESPONSE_R1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD18;
- } else {
- if (size > EMMC_BLOCK_SIZE)
- cmd.cmd_idx = EMMC_CMD18;
- else
- cmd.cmd_idx = EMMC_CMD17;
- }
- if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
- cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
- else
- cmd.cmd_arg = lba;
- cmd.resp_type = EMMC_RESPONSE_R1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- ret = ops->read(lba, buf, size);
- assert(ret == 0);
-
- /* wait buffer empty */
- emmc_device_state();
-
- if (is_cmd23_enabled() == 0) {
- if (size > EMMC_BLOCK_SIZE) {
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD12;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
- }
- }
- /* Ignore improbable errors in release builds */
- (void)ret;
- return size;
-}
-
-size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size)
-{
- emmc_cmd_t cmd;
- int ret;
-
- assert((ops != 0) &&
- (ops->write != 0) &&
- ((buf & EMMC_BLOCK_MASK) == 0) &&
- ((size & EMMC_BLOCK_MASK) == 0));
-
- clean_dcache_range(buf, size);
- ret = ops->prepare(lba, buf, size);
- assert(ret == 0);
-
- if (is_cmd23_enabled()) {
- /* set block count */
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD23;
- cmd.cmd_arg = size / EMMC_BLOCK_SIZE;
- cmd.resp_type = EMMC_RESPONSE_R1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD25;
- } else {
- zeromem(&cmd, sizeof(emmc_cmd_t));
- if (size > EMMC_BLOCK_SIZE)
- cmd.cmd_idx = EMMC_CMD25;
- else
- cmd.cmd_idx = EMMC_CMD24;
- }
- if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE)
- cmd.cmd_arg = lba * EMMC_BLOCK_SIZE;
- else
- cmd.cmd_arg = lba;
- cmd.resp_type = EMMC_RESPONSE_R1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- ret = ops->write(lba, buf, size);
- assert(ret == 0);
-
- /* wait buffer empty */
- emmc_device_state();
-
- if (is_cmd23_enabled() == 0) {
- if (size > EMMC_BLOCK_SIZE) {
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD12;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
- }
- }
- /* Ignore improbable errors in release builds */
- (void)ret;
- return size;
-}
-
-size_t emmc_erase_blocks(int lba, size_t size)
-{
- emmc_cmd_t cmd;
- int ret, state;
-
- assert(ops != 0);
- assert((size != 0) && ((size % EMMC_BLOCK_SIZE) == 0));
-
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD35;
- cmd.cmd_arg = lba;
- cmd.resp_type = EMMC_RESPONSE_R1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD36;
- cmd.cmd_arg = lba + (size / EMMC_BLOCK_SIZE) - 1;
- cmd.resp_type = EMMC_RESPONSE_R1;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- zeromem(&cmd, sizeof(emmc_cmd_t));
- cmd.cmd_idx = EMMC_CMD38;
- cmd.resp_type = EMMC_RESPONSE_R1B;
- ret = ops->send_cmd(&cmd);
- assert(ret == 0);
-
- /* wait to TRAN state */
- do {
- state = emmc_device_state();
- } while (state != EMMC_STATE_TRAN);
- /* Ignore improbable errors in release builds */
- (void)ret;
- return size;
-}
-
-static inline void emmc_rpmb_enable(void)
-{
- emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
- PART_CFG_BOOT_PARTITION1_ENABLE |
- PART_CFG_PARTITION1_ACCESS);
-}
-
-static inline void emmc_rpmb_disable(void)
-{
- emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
- PART_CFG_BOOT_PARTITION1_ENABLE);
-}
-
-size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size)
-{
- size_t size_read;
-
- emmc_rpmb_enable();
- size_read = emmc_read_blocks(lba, buf, size);
- emmc_rpmb_disable();
- return size_read;
-}
-
-size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size)
-{
- size_t size_written;
-
- emmc_rpmb_enable();
- size_written = emmc_write_blocks(lba, buf, size);
- emmc_rpmb_disable();
- return size_written;
-}
-
-size_t emmc_rpmb_erase_blocks(int lba, size_t size)
-{
- size_t size_erased;
-
- emmc_rpmb_enable();
- size_erased = emmc_erase_blocks(lba, size);
- emmc_rpmb_disable();
- return size_erased;
-}
-
-void emmc_init(const emmc_ops_t *ops_ptr, int clk, int width,
- unsigned int flags)
-{
- assert((ops_ptr != 0) &&
- (ops_ptr->init != 0) &&
- (ops_ptr->send_cmd != 0) &&
- (ops_ptr->set_ios != 0) &&
- (ops_ptr->prepare != 0) &&
- (ops_ptr->read != 0) &&
- (ops_ptr->write != 0) &&
- (clk != 0) &&
- ((width == EMMC_BUS_WIDTH_1) ||
- (width == EMMC_BUS_WIDTH_4) ||
- (width == EMMC_BUS_WIDTH_8) ||
- (width == EMMC_BUS_WIDTH_DDR_4) ||
- (width == EMMC_BUS_WIDTH_DDR_8)));
- ops = ops_ptr;
- emmc_flags = flags;
-
- emmc_enumerate(clk, width);
-}
+++ /dev/null
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __EMMC_H__
-#define __EMMC_H__
-
-#include <stdint.h>
-
-#define EMMC_BLOCK_SIZE 512
-#define EMMC_BLOCK_MASK (EMMC_BLOCK_SIZE - 1)
-#define EMMC_BOOT_CLK_RATE (400 * 1000)
-
-#define EMMC_CMD0 0
-#define EMMC_CMD1 1
-#define EMMC_CMD2 2
-#define EMMC_CMD3 3
-#define EMMC_CMD6 6
-#define EMMC_CMD7 7
-#define EMMC_CMD8 8
-#define EMMC_CMD9 9
-#define EMMC_CMD12 12
-#define EMMC_CMD13 13
-#define EMMC_CMD17 17
-#define EMMC_CMD18 18
-#define EMMC_CMD21 21
-#define EMMC_CMD23 23
-#define EMMC_CMD24 24
-#define EMMC_CMD25 25
-#define EMMC_CMD35 35
-#define EMMC_CMD36 36
-#define EMMC_CMD38 38
-
-#define OCR_POWERUP (1 << 31)
-#define OCR_BYTE_MODE (0 << 29)
-#define OCR_SECTOR_MODE (2 << 29)
-#define OCR_ACCESS_MODE_MASK (3 << 29)
-#define OCR_VDD_MIN_2V7 (0x1ff << 15)
-#define OCR_VDD_MIN_2V0 (0x7f << 8)
-#define OCR_VDD_MIN_1V7 (1 << 7)
-
-#define EMMC_RESPONSE_R1 1
-#define EMMC_RESPONSE_R1B 1
-#define EMMC_RESPONSE_R2 4
-#define EMMC_RESPONSE_R3 1
-#define EMMC_RESPONSE_R4 1
-#define EMMC_RESPONSE_R5 1
-
-#define EMMC_FIX_RCA 6 /* > 1 */
-#define RCA_SHIFT_OFFSET 16
-
-#define CMD_EXTCSD_PARTITION_CONFIG 179
-#define CMD_EXTCSD_BUS_WIDTH 183
-#define CMD_EXTCSD_HS_TIMING 185
-
-#define PART_CFG_BOOT_PARTITION1_ENABLE (1 << 3)
-#define PART_CFG_PARTITION1_ACCESS (1 << 0)
-
-/* values in EXT CSD register */
-#define EMMC_BUS_WIDTH_1 0
-#define EMMC_BUS_WIDTH_4 1
-#define EMMC_BUS_WIDTH_8 2
-#define EMMC_BUS_WIDTH_DDR_4 5
-#define EMMC_BUS_WIDTH_DDR_8 6
-#define EMMC_BOOT_MODE_BACKWARD (0 << 3)
-#define EMMC_BOOT_MODE_HS_TIMING (1 << 3)
-#define EMMC_BOOT_MODE_DDR (2 << 3)
-
-#define EXTCSD_SET_CMD (0 << 24)
-#define EXTCSD_SET_BITS (1 << 24)
-#define EXTCSD_CLR_BITS (2 << 24)
-#define EXTCSD_WRITE_BYTES (3 << 24)
-#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
-#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
-
-#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
-#define STATUS_READY_FOR_DATA (1 << 8)
-#define STATUS_SWITCH_ERROR (1 << 7)
-#define EMMC_GET_STATE(x) (((x) >> 9) & 0xf)
-#define EMMC_STATE_IDLE 0
-#define EMMC_STATE_READY 1
-#define EMMC_STATE_IDENT 2
-#define EMMC_STATE_STBY 3
-#define EMMC_STATE_TRAN 4
-#define EMMC_STATE_DATA 5
-#define EMMC_STATE_RCV 6
-#define EMMC_STATE_PRG 7
-#define EMMC_STATE_DIS 8
-#define EMMC_STATE_BTST 9
-#define EMMC_STATE_SLP 10
-
-#define EMMC_FLAG_CMD23 (1 << 0)
-
-typedef struct emmc_cmd {
- unsigned int cmd_idx;
- unsigned int cmd_arg;
- unsigned int resp_type;
- unsigned int resp_data[4];
-} emmc_cmd_t;
-
-typedef struct emmc_ops {
- void (*init)(void);
- int (*send_cmd)(emmc_cmd_t *cmd);
- int (*set_ios)(int clk, int width);
- int (*prepare)(int lba, uintptr_t buf, size_t size);
- int (*read)(int lba, uintptr_t buf, size_t size);
- int (*write)(int lba, const uintptr_t buf, size_t size);
-} emmc_ops_t;
-
-typedef struct emmc_csd {
- unsigned int not_used: 1;
- unsigned int crc: 7;
- unsigned int ecc: 2;
- unsigned int file_format: 2;
- unsigned int tmp_write_protect: 1;
- unsigned int perm_write_protect: 1;
- unsigned int copy: 1;
- unsigned int file_format_grp: 1;
-
- unsigned int reserved_1: 5;
- unsigned int write_bl_partial: 1;
- unsigned int write_bl_len: 4;
- unsigned int r2w_factor: 3;
- unsigned int default_ecc: 2;
- unsigned int wp_grp_enable: 1;
-
- unsigned int wp_grp_size: 5;
- unsigned int erase_grp_mult: 5;
- unsigned int erase_grp_size: 5;
- unsigned int c_size_mult: 3;
- unsigned int vdd_w_curr_max: 3;
- unsigned int vdd_w_curr_min: 3;
- unsigned int vdd_r_curr_max: 3;
- unsigned int vdd_r_curr_min: 3;
- unsigned int c_size_low: 2;
-
- unsigned int c_size_high: 10;
- unsigned int reserved_2: 2;
- unsigned int dsr_imp: 1;
- unsigned int read_blk_misalign: 1;
- unsigned int write_blk_misalign: 1;
- unsigned int read_bl_partial: 1;
- unsigned int read_bl_len: 4;
- unsigned int ccc: 12;
-
- unsigned int tran_speed: 8;
- unsigned int nsac: 8;
- unsigned int taac: 8;
- unsigned int reserved_3: 2;
- unsigned int spec_vers: 4;
- unsigned int csd_structure: 2;
-} emmc_csd_t;
-
-size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size);
-size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size);
-size_t emmc_erase_blocks(int lba, size_t size);
-size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
-size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
-size_t emmc_rpmb_erase_blocks(int lba, size_t size);
-void emmc_init(const emmc_ops_t *ops, int clk, int bus_width,
- unsigned int flags);
-
-#endif /* __EMMC_H__ */
projects / project / bcm63xx / atf.git / commitdiff