Merge "plat: imx8m: Add the aipstz init to config peripheral access" into integration

diff --combined plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index ea60466f7ebbdf2a3be9c6e9f8e024115932afeb,47eae86df3edbbbcd2d0ba48538e6a087718361b..ce55d7f3134061f0581f824f284976c855010e80
--- 1/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
--- 2/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@@ -22,59 -22,28 +22,68 @@@
  #include <plat/common/platform.h>
  
  #include <gpc.h>
+ #include <imx_aipstz.h>
  #include <imx_uart.h>
  #include <plat_imx8.h>
  
  static const mmap_region_t imx_mmap[] = {
        MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */
 +      MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */
        MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
        MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
        {0},
  };
  
+ static const struct aipstz_cfg aipstz[] = {
+       {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+       {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+       {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+       {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+       {0},
+ };
+ 
  static entry_point_info_t bl32_image_ep_info;
  static entry_point_info_t bl33_image_ep_info;
  
 +static uint32_t imx_soc_revision;
 +
 +int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
 +                              u_register_t x3)
 +{
 +      return imx_soc_revision;
 +}
 +
 +#define ANAMIX_DIGPROG                0x6c
 +#define ROM_SOC_INFO_A0               0x800
 +#define ROM_SOC_INFO_B0               0x83C
 +#define OCOTP_SOC_INFO_B1     0x40
 +
 +static void imx8mq_soc_info_init(void)
 +{
 +      uint32_t rom_version;
 +      uint32_t ocotp_val;
 +
 +      imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG);
 +      rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_A0);
 +      if (rom_version == 0x10)
 +              return;
 +
 +      rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_B0);
 +      if (rom_version == 0x20) {
 +              imx_soc_revision &= ~0xff;
 +              imx_soc_revision |= rom_version;
 +              return;
 +      }
 +
 +      /* 0xff0055aa is magic number for B1 */
 +      ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1);
 +      if (ocotp_val == 0xff0055aa) {
 +              imx_soc_revision &= ~0xff;
 +              imx_soc_revision |= 0x21;
 +              return;
 +      }
 +}
 +
  /* get SPSR for BL33 entry */
  static uint32_t get_spsr_for_bl33_entry(void)
  {
@@@ -118,6 -87,8 +127,8 @@@ void bl31_early_platform_setup2(u_regis
                mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
        }
  
+       imx_aipstz_init(aipstz);
+ 
        /* config CAAM JRaMID set MID to Cortex A */
        mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
        mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
@@@ -168,9 -139,6 +179,9 @@@ void bl31_platform_setup(void
        plat_gic_driver_init();
        plat_gic_init();
  
 +      /* determine SOC revision for erratas */
 +      imx8mq_soc_info_init();
 +
        /* gpc init */
        imx_gpc_init();
  }