This is the PR for SPI-NAND changes along with few spi changes.
[trini: Re-sync changes for ls1012afrwy_qspi*_defconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
- wget
- device-tree-compiler
- lzop
+ - liblz4-tool
before_install:
- sudo add-apt-repository ppa:ubuntu-toolchain-r/test -y
--- /dev/null
+gdsys Gazerbeam board driver
+
+This driver provides capabilities to access the gdsys Gazerbeam board's device
+information. Furthermore, phandles to some internal devices are provided for
+the board files.
+
+Required properties:
+- compatible: should be "gdsys,board_gazerbeam"
+- csb: phandle to the board's coherent system bus (CSB) device node
+- rxaui[0-3]: phandles to the rxaui control device nodes
+- fpga[0-1]: phandles to the board's gdsys FPGA device nodes
+- ioep[0-1]: phandles to the board's IO endpoint device nodes
+- ver-gpios: GPIO list to read the hardware version from
+- var-gpios: GPIO list to read the hardware variant information from
+- reset-gpios: GPIO list for the board's reset GPIOs
+
+Example:
+
+
+board {
+ compatible = "gdsys,board_gazerbeam";
+ csb = <&board_soc>;
+ serdes = <&SERDES>;
+ rxaui0 = <&RXAUI0>;
+ rxaui1 = <&RXAUI1>;
+ rxaui2 = <&RXAUI2>;
+ rxaui3 = <&RXAUI3>;
+ fpga0 = <&FPGA0>;
+ fpga1 = <&FPGA1>;
+ ioep0 = <&IOEP0>;
+ ioep1 = <&IOEP1>;
+
+ ver-gpios = <&PPCPCA 12 0
+ &PPCPCA 13 0
+ &PPCPCA 14 0
+ &PPCPCA 15 0>;
+
+ /* MC2/SC-Board */
+ var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */
+ &GPIO_VB0 11 0>; /* VAR-CON */
+ /* MC4-Board */
+ var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */
+ &GPIO_VB1 11 0>; /* VAR-CON */
+
+ reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
+};
F: arch/arm/mach-snapdragon/
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
+F: drivers/phy/msm8916-usbh-phy.c
F: drivers/serial/serial_msm.c
F: drivers/smem/msm_smem.c
F: drivers/usb/host/ehci-msm.c
F: doc/README.uefi
F: doc/README.iscsi
F: Documentation/efi.rst
+F: include/capitalization.h
+F: include/cp1250.h
+F: include/cp437.h
F: include/efi*
F: include/pe.h
F: include/asm-generic/pe.h
F: lib/charset.c
F: lib/efi*/
F: test/py/tests/test_efi*
+F: test/unicode_ut.c
F: cmd/bootefi.c
F: tools/file2include.c
F: test/log/log_test.c
F: test/py/tests/test_log.py
+MALI DISPLAY PROCESSORS
+M: Liviu Dudau <liviu.dudau@foss.arm.com>
+S: Supported
+T: git git://github.com/ARM-software/u-boot.git
+F: drivers/video/mali_dp.c
+
MICROBLAZE
M: Michal Simek <monstr@monstr.eu>
S: Maintained
F: drivers/spmi/
F: include/spmi/
+TDA19988 HDMI ENCODER
+M: Liviu Dudau <liviu.dudau@foss.arm.com>
+S: Maintained
+F: drivers/video/tda19988.c
+
TI SYSTEM SECURITY
M: Andrew F. Davis <afd@ti.com>
S: Supported
F: drivers/video/
F: common/lcd*.c
F: include/lcd*.h
+F: include/video*.h
X86
M: Simon Glass <sjg@chromium.org>
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2018
-PATCHLEVEL = 09
+PATCHLEVEL = 11
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
KBUILD_CFLAGS := -Wall -Wstrict-prototypes \
-Wno-format-security \
-fno-builtin -ffreestanding $(CSTD_FLAG)
-KBUILD_CFLAGS += -fshort-wchar
+KBUILD_CFLAGS += -fshort-wchar -fno-strict-aliasing
KBUILD_AFLAGS := -D__ASSEMBLY__
# Don't generate position independent code
ALL-y += init_sp_bss_offset_check
endif
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+ALL-y += u-boot-with-dtb.bin
+endif
+
LDFLAGS_u-boot += $(LDFLAGS_FINAL)
# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
$(call if_changed,objcopy)
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
- $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)
+ $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
+ $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
$(call if_changed,socboot)
endif
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+u-boot-with-dtb.bin: u-boot.bin u-boot.dtb \
+ $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR), u-boot-br.bin) FORCE
+ $(call if_changed,binman)
+
+ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR),y)
+OBJCOPYFLAGS_u-boot-br.bin := -O binary -j .bootpg -j .resetvec
+u-boot-br.bin: u-boot FORCE
+ $(call if_changed,objcopy)
+endif
+endif
+
# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
# the middle. This is handled by binman based on an image description in the
ifeq ($(ARCH),arm)
UBOOT_BINLOAD := u-boot.img
else
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+UBOOT_BINLOAD := u-boot-with-dtb.bin
+else
UBOOT_BINLOAD := u-boot.bin
endif
+endif
OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
--gap-fill=0xff
pointer. This is needed for the temporary stack before
relocation.
- CONFIG_SYS_MIPS_CACHE_MODE
-
- Cache operation mode for the MIPS CPU.
- See also arch/mips/include/asm/mipsregs.h.
- Possible values are:
- CONF_CM_CACHABLE_NO_WA
- CONF_CM_CACHABLE_WA
- CONF_CM_UNCACHED
- CONF_CM_CACHABLE_NONCOHERENT
- CONF_CM_CACHABLE_CE
- CONF_CM_CACHABLE_COW
- CONF_CM_CACHABLE_CUW
- CONF_CM_CACHABLE_ACCELERATED
-
- CONFIG_SYS_XWAY_EBU_BOOTCFG
-
- Special option for Lantiq XWAY SoCs for booting from NOR flash.
- See also arch/mips/cpu/mips32/start.S.
-
CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq
imply CMD_SF_TEST
imply CRC32_VERIFY
imply FAT_WRITE
+ imply FIRMWARE
imply HASH_VERIFY
imply LZMA
imply SCSI
select OF_CONTROL
select PL01X_SERIAL
imply CMD_DM
+ imply DM_RTC
+ imply RTC_PL031
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
config ARCH_ZYNQ
bool "Xilinx Zynq based platform"
select BOARD_EARLY_INIT_F if WDT
- select BOARD_LATE_INIT
select CLK
select CLK_ZYNQ
select CPU_V7A
select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL
imply ARCH_EARLY_INIT_R
+ imply BOARD_LATE_INIT
imply CMD_CLK
imply CMD_DM
imply CMD_SPL
config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform"
select ARM64
- select BOARD_LATE_INIT
select CLK
select DM
select DM_SERIAL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
select SUPPORT_SPL
+ imply BOARD_LATE_INIT
imply CMD_DM
imply FAT_WRITE
#if defined(CONFIG_SPEAR_GPIO)
periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB;
#endif
+#if defined(CONFIG_PL022_SPI)
+ periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB;
+#endif
writel(periph1_clken, &misc_p->periph1_clken);
obj-y += fsl_epu.o
obj-y += soc.o
-obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
* read, that is why we don't read it from register ippdexpcr1 itself.
*/
ippdexpcr1 = in_le32(&scfg->sparecr[7]);
+ out_be32(&rcpm->ippdexpcr1, ippdexpcr1);
if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
+ /* Disable QE */
+ setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE);
+
ls1_deepsleep_irq_cfg();
psci_v7_flush_dcache_all();
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/immap_ls102xa.h>
-#include <ahci.h>
-#include <scsi.h>
-
-/* port register default value */
-#define AHCI_PORT_PHY_1_CFG 0xa003fffe
-#define AHCI_PORT_PHY_2_CFG 0x28183414
-#define AHCI_PORT_PHY_3_CFG 0x0e080e06
-#define AHCI_PORT_PHY_4_CFG 0x064a080b
-#define AHCI_PORT_PHY_5_CFG 0x2aa86470
-#define AHCI_PORT_TRANS_CFG 0x08000029
-
-#define SATA_ECC_REG_ADDR 0x20220520
-#define SATA_ECC_DISABLE 0x00020000
-
-int ls1021a_sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
- out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
-#endif
-
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
- out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
- out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-
- ahci_init((void __iomem *)AHCI_BASE_ADDR);
- scsi_scan(false);
-
- return 0;
-}
ifneq ($(CONFIG_ARCH_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
+obj-y += icid.o ls1043_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1012A),)
return 0;
}
-#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(EFI_LOADER)
void efi_add_known_memory(void)
{
int i;
fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
*boot_code_size);
-#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(EFI_LOADER)
efi_add_memory_map((uintptr_t)&secondary_boot_code,
ALIGN(*boot_code_size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
EFI_RESERVED_MEMORY_TYPE, false);
return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
}
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+ if (!gd->arch.sdhc_clk)
+ get_clocks();
+
+ return gd->arch.sdhc_clk;
+}
+#endif
+
int get_serial_clock(void)
{
return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
switch (clk) {
case MXC_I2C_CLK:
return get_i2c_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+ case MXC_ESDHC_CLK:
+ return get_sdhc_freq(0);
+#endif
case MXC_DSPI_CLK:
return get_dspi_freq(0);
default:
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+#include <fsl_sec.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+};
+#endif
+
+struct icid_id_table icid_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
+ SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1),
+#endif
+
+ SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
+
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
+
+ SET_SATA_ICID("fsl,ls1043a-ahci", FSL_SATA_STREAM_ID),
+ SET_QDMA_ICID("fsl,ls1043a-qdma", FSL_QDMA_STREAM_ID),
+ SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
+ SET_ETR_ICID(FSL_ETR_STREAM_ID),
+ SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
+ SET_QE_ICID(FSL_QE_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct fman_icid_id_table fman_icid_tbl[] = {
+ /* port id, icid */
+ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END),
+};
+
+int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl);
+#endif
cnt = DIV_ROUND_UP(fdt_header_len, 512);
debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
__func__, dev, blk, cnt);
- ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp);
+ ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, fitp);
if (ret != cnt) {
free(fitp);
printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
blk = CONFIG_SYS_LS_PPA_ESBC_ADDR >> 9;
cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512);
- ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, ppa_hdr_ddr);
+ ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_hdr_ddr);
if (ret != cnt) {
free(ppa_hdr_ddr);
printf("MMC/SD read of PPA header failed\n");
cnt = DIV_ROUND_UP(fw_length, 512);
debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
__func__, dev, blk, cnt);
- ret = mmc->block_dev.block_read(&mmc->block_dev,
- blk, cnt, ppa_fit_addr);
+ ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_fit_addr);
if (ret != cnt) {
free(ppa_fit_addr);
printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n",
erratum_a008997();
erratum_a009007();
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_icids();
#endif
}
return regs.regs[0];
}
-#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001
-
-#define ZYNQMP_PM_VERSION_MAJOR 1
-#define ZYNQMP_PM_VERSION_MINOR 0
-#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
-#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
-
-#define ZYNQMP_PM_VERSION \
- ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
- ZYNQMP_PM_VERSION_MINOR)
-
#if defined(CONFIG_CLK_ZYNQMP)
-void zynqmp_pmufw_version(void)
+unsigned int zynqmp_pmufw_version(void)
{
int ret;
u32 ret_payload[PAYLOAD_ARG_CNT];
- u32 pm_api_version;
-
- ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
- ret_payload);
- pm_api_version = ret_payload[1];
+ static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID;
- if (ret)
- panic("PMUFW is not found - Please load it!\n");
+ /*
+ * Get PMU version only once and later
+ * just return stored values instead of
+ * asking PMUFW again.
+ */
+ if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) {
+ ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
+ ret_payload);
+ pm_api_version = ret_payload[1];
- printf("PMUFW:\tv%d.%d\n",
- pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
- pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
+ if (ret)
+ panic("PMUFW is not found - Please load it!\n");
+ }
- if (pm_api_version < ZYNQMP_PM_VERSION)
- panic("PMUFW version error. Expected: v%d.%d\n",
- ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
+ return pm_api_version;
}
#endif
};
};
-&mmc1 {
- cd-inverted;
-};
-
&uart1 {
reg-shift = <2>;
};
stdout-path = &uart1;
};
+ onewire_tm: onewire {
+ gpios = <&pioA 17 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_onewire_tm_default>;
+ status = "okay";
+
+ w1_eeprom: w1_eeprom@0 {
+ compatible = "maxim,ds24b33";
+ status = "okay";
+ };
+ };
+
ahb {
usb1: ohci@00400000 {
num-ports = <3>;
pinmux = <PIN_PA31__GPIO>;
bias-disable;
};
+
+ pinctrl_onewire_tm_default: onewire_tm_default {
+ pinmux = <PIN_PA17__GPIO>;
+ bias-pull-up;
+ };
};
};
};
stdout-path = &uart0;
};
+ onewire_tm: onewire {
+ gpios = <&pioA PIN_PB31 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_onewire_tm_default>;
+ status = "okay";
+
+ w1_eeprom: w1_eeprom@0 {
+ compatible = "maxim,ds24b33";
+ status = "okay";
+ };
+ };
+
ahb {
usb0: gadget@00300000 {
atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
pinmux = <PIN_PB11__GPIO>;
bias-disable;
};
+
+ pinctrl_onewire_tm_default: onewire_tm_default {
+ pinmux = <PIN_PB31__GPIO>;
+ bias-pull-up;
+ };
};
};
};
stdout-path = &uart1;
};
+ onewire_tm: onewire {
+ gpios = <&pioA PIN_PB0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_onewire_tm_default>;
+ status = "okay";
+
+ w1_eeprom: w1_eeprom@0 {
+ compatible = "maxim,ds24b33";
+ status = "okay";
+ };
+ };
+
ahb {
usb1: ohci@00400000 {
num-ports = <3>;
pinmux = <PIN_PA31__GPIO>;
bias-disable;
};
+
+ pinctrl_onewire_tm_default: onewire_tm_default {
+ pinmux = <PIN_PB0__GPIO>;
+ bias-pull-up;
+ };
};
};
};
};
};
+ onewire_tm: onewire {
+ gpios = <&pioE 23 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_onewire_tm_default>;
+ status = "okay";
+
+ w1_eeprom: w1_eeprom@0 {
+ compatible = "maxim,ds24b33";
+ status = "okay";
+ };
+ };
+
ahb {
apb {
mmc0: mmc@f0000000 {
atmel,pins =
<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */
};
+
+ pinctrl_onewire_tm_default: onewire_tm_default {
+ atmel,pins =
+ <AT91_PIOE 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
};
};
};
stdout-path = &usart3;
};
+ onewire_tm: onewire {
+ gpios = <&pioE 15 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_onewire_tm_default>;
+ status = "okay";
+
+ w1_eeprom: w1_eeprom@0 {
+ compatible = "maxim,ds24b33";
+ status = "okay";
+ };
+ };
+
memory {
reg = <0x20000000 0x20000000>;
};
atmel,pins =
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
+ pinctrl_onewire_tm_default: onewire_tm_default {
+ atmel,pins =
+ <AT91_PIOE 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
};
};
};
interrupt-controller;
#interrupt-cells = <1>;
+ ac_power_supply: ac-power-supply {
+ compatible = "x-powers,axp202-ac-power-supply";
+ status = "disabled";
+ };
+
+ axp_adc: adc {
+ compatible = "x-powers,axp209-adc";
+ #io-channel-cells = <1>;
+ };
+
axp_gpio: gpio {
compatible = "x-powers,axp209-gpio";
gpio-controller;
#gpio-cells = <2>;
};
+ battery_power_supply: battery-power-supply {
+ compatible = "x-powers,axp209-battery-power-supply";
+ status = "disabled";
+ };
+
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <1500>;
};
};
- usb_power_supply: usb_power_supply {
+ usb_power_supply: usb-power-supply {
compatible = "x-powers,axp202-usb-power-supply";
status = "disabled";
};
#address-cells = <0x2>;
#size-cells = <0x2>;
+ aliases {
+ usb0 = "/soc/ehci@78d9000";
+ };
+
memory {
device_type = "memory";
reg = <0 0x80000000 0 0x3da00000>;
ehci@78d9000 {
compatible = "qcom,ehci-host";
reg = <0x78d9000 0x400>;
+ phys = <&ehci_phy>;
+ };
+
+ ehci_phy: ehci_phy@78d9000 {
+ compatible = "qcom,apq8016-usbphy";
+ reg = <0x78d9000 0x400>;
+ #phy-cells = <0>;
};
sdhci@07824000 {
&lpuart0 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
status = "disabled";
};
+ esdhc: esdhc@1560000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <0 62 0x4>;
+ big-endian;
+ bus-width = <4>;
+ };
+
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1043a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 69 4>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
};
};
status = "disabled";
};
+ esdhc: esdhc@1560000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <0 62 0x4>;
+ big-endian;
+ bus-width = <4>;
+ };
+
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
};
+
+ esdhc: esdhc@2140000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ little-endian;
+ bus-width = <4>;
+ };
+
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x2240000 0x0 0x20000>;
num-cs = <4>;
};
+ esdhc: esdhc@0 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ little-endian;
+ bus-width = <4>;
+ };
+
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
&uart1 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
&uart1 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
- status = "disabled";
};
scfg: scfg@1570000 {
ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
};
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1021a-ahci";
+ reg = <0x3200000 0x10000>;
+ interrupts = <0 101 4>;
+ status = "disabled";
+ };
};
};
};
};
-&mmc1 {
- cd-inverted;
-};
-
&uart1 {
reg-shift = <2>;
};
};
};
-&mmc1 {
- cd-inverted;
-};
-
&uart1 {
reg-shift = <2>;
};
};
};
-&mmc1 {
- cd-inverted;
-};
-
&uart1 {
reg-shift = <2>;
};
};
};
-&mmc1 {
- cd-inverted;
-};
-
&uart1 {
reg-shift = <2>;
};
};
};
-&mmc1 {
- cd-inverted;
-};
-
&uart1 {
reg-shift = <2>;
};
};
};
};
+
+ onewire_tm: onewire {
+ compatible = "w1-gpio";
+ status = "disabled";
+ };
};
};
};
};
+
+ onewire_tm: onewire {
+ compatible = "w1-gpio";
+ status = "disabled";
+ };
};
};
};
};
+
+ onewire_tm: onewire {
+ compatible = "w1-gpio";
+ status = "disabled";
+ };
};
bias-disable;
};
};
+
+ usbotg_hs_pins_a: usbotg_hs-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
+ };
+ };
};
pinctrl_z: pin-controller-z@54004000 {
regulator-always-on;
};
+&usbotg_hs {
+ g-tx-fifo-size = <576>;
+};
+
/* SPL part **************************************/
&qspi {
u-boot,dm-spl;
&flash0 {
u-boot,dm-spl;
};
+
};
};
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ phy-names = "usb";
+ vbus-supply = <&vbus_sw>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
&usbphyc {
status = "okay";
};
};
};
+ pm_domain {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp157c-pd";
+
+ pd_core_ret: core-ret-power-domain@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ #power-domain-cells = <0>;
+ label = "CORE-RETENTION";
+
+ pd_core: core-power-domain@2 {
+ reg = <2>;
+ #power-domain-cells = <0>;
+ label = "CORE";
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
status = "disabled";
};
+ usbotg_hs: usb-otg@49000000 {
+ compatible = "st,stm32mp1-hsotg", "snps,dwc2";
+ reg = <0x49000000 0x10000>;
+ clocks = <&rcc USBO_K>;
+ clock-names = "otg";
+ resets = <&rcc USBO_R>;
+ reset-names = "dwc2";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+ dr_mode = "otg";
+ power-domains = <&pd_core>;
+ status = "disabled";
+ };
+
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Mele A1000";
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_a1000>;
red {
label = "a1000:red:usr";
reg_emac_3v3: emac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&emac_power_pin_a1000>;
regulator-name = "emac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
status = "okay";
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&ehci0 {
status = "okay";
};
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pins>;
status = "okay";
};
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
status = "okay";
};
-&pio {
- emac_power_pin_a1000: emac_power_pin@0 {
- allwinner,pins = "PH15";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
+#include "axp209.dtsi"
- led_pins_a1000: led_pins@0 {
- allwinner,pins = "PH10", "PH20";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
};
®_usb1_vbus {
&spdif {
pinctrl-names = "default";
- pinctrl-0 = <&spdif_tx_pins_a>;
+ pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pins>;
status = "okay";
};
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
status = "okay";
};
-&ohci1 {
- status = "okay";
-};
-
&otg_sram {
status = "okay";
};
-&pio {
- usb2_vbus_pin_a: usb2_vbus_pin@0 {
- allwinner,pins = "PH12";
- };
-};
-
®_usb0_vbus {
regulator-boot-on;
status = "okay";
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
ft5306de4: touchscreen@38 {
vref-supply = <®_vcc3v0>;
status = "okay";
- button@800 {
+ button-800 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <800000>;
};
- button@1000 {
+ button-1000 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <1000000>;
};
- button@1200 {
+ button-1200 {
label = "Back";
linux,code = <KEY_BACK>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Cubietech Cubieboard";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
cpu-supply = <®_dcdc2>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pins>;
status = "okay";
};
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- led_pins_cubieboard: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ led_pins_cubieboard: led-pins {
+ pins = "PH20", "PH21";
+ function = "gpio_out";
+ drive-strength = <20>;
};
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
&spi0 {
pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins_a>,
- <&spi0_cs0_pins_a>;
+ pinctrl-0 = <&spi0_pi_pins>,
+ <&spi0_cs0_pi_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/pwm/pwm.h>
/ {
backlight: backlight {
compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&bl_en_pin_dsrv9703c>;
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
max-microvolt = <3000000>;
};
- reg_motor: reg_motor {
+ reg_motor: reg-motor {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&motor_pins>;
regulator-name = "vcc-motor";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
&codec {
- pinctrl-names = "default";
- pinctrl-0 = <&codec_pa_pin>;
allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
#include "axp209.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
/* pull-ups and devices require AXP209 LDO3 */
status = "failed";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
ft5406ee8: touchscreen@38 {
reg = <0x38>;
interrupt-parent = <&pio>;
interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&touchscreen_pins>;
reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <1024>;
touchscreen-size-y = <768>;
vref-supply = <®_ldo2>;
status = "okay";
- button@400 {
+ button-400 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <400000>;
};
- button@800 {
+ button-800 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- bl_en_pin_dsrv9703c: bl_en_pin@0 {
- allwinner,pins = "PH7";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- codec_pa_pin: codec_pa_pin@0 {
- allwinner,pins = "PH15";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- motor_pins: motor_pins@0 {
- allwinner,pins = "PB3";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- touchscreen_pins: touchscreen_pins@0 {
- allwinner,pins = "PB13";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins_a>;
+ pinctrl-0 = <&pwm0_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
*/
&codec {
/* PH15 controls power to external amplifier (ft2012q) */
- pinctrl-names = "default";
- pinctrl-0 = <&codec_pa_pin>;
allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
#include "axp209.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
/* Accelerometer */
status = "okay";
- button@158 {
+ button-158 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <158730>;
};
- button@349 {
+ button-349 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <349206>;
};
- button@1142 {
+ button-1142 {
label = "Esc";
linux,code = <KEY_ESC>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */
status = "okay";
};
-&pio {
- codec_pa_pin: codec_pa_pin@0 {
- allwinner,pins = "PH15";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Miniand Hackberry";
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
phy = <&phy0>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pins>;
status = "okay";
};
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
status = "okay";
};
-&pio {
- pinctrl-names = "default";
- pinctrl-0 = <&hackberry_hogs>;
-
- hackberry_hogs: hogs@0 {
- allwinner,pins = "PH19";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb2_vbus_pin_hackberry: usb2_vbus_pin@0 {
- allwinner,pins = "PH12";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
®_usb1_vbus {
status = "okay";
};
®_usb2_vbus {
- pinctrl-0 = <&usb2_vbus_pin_hackberry>;
gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
-&usb2_vbus_pin_a {
- allwinner,pins = "PH6";
-};
-
&usb_otg {
dr_mode = "otg";
status = "okay";
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/pwm/pwm.h>
/ {
backlight: backlight {
compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&bl_en_pin_inet>;
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
#include "axp209.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
/* Accelerometer */
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
ft5x: touchscreen@38 {
reg = <0x38>;
interrupt-parent = <&pio>;
interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&touchscreen_wake_pin>;
wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */
touchscreen-size-x = <600>;
touchscreen-size-y = <1024>;
vref-supply = <®_ldo2>;
status = "okay";
- button@200 {
+ button-200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <200000>;
};
- button@1000 {
+ button-1000 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <1000000>;
};
- button@1200 {
+ button-1200 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- bl_en_pin_inet: bl_en_pin@0 {
- allwinner,pins = "PH7";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- touchscreen_wake_pin: touchscreen_wake_pin@0 {
- allwinner,pins = "PB13";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins_a>;
+ pinctrl-0 = <&pwm0_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
#include "axp209.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
ft5406ee8: touchscreen@38 {
vref-supply = <®_ldo2>;
status = "okay";
- button@200 {
+ button-200 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <200000>;
};
- button@600 {
+ button-600 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <600000>;
};
- button@800 {
+ button-800 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <800000>;
};
- button@1000 {
+ button-1000 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
voltage = <1000000>;
};
- button@1200 {
+ button-1200 {
label = "Esc";
linux,code = <KEY_ESC>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "iNet-9F Rev 03";
stdout-path = "serial0:115200n8";
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys-polled";
pinctrl-names = "default";
pinctrl-0 = <&key_pins_inet9f>;
#size-cells = <0>;
poll-interval = <20>;
- button@0 {
+ left-joystick-left {
label = "Left Joystick Left";
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
};
- button@1 {
+ left-joystick-right {
label = "Left Joystick Right";
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
};
- button@2 {
+ left-joystick-up {
label = "Left Joystick Up";
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
};
- button@3 {
+ left-joystick-down {
label = "Left Joystick Down";
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
};
- button@4 {
+ right-joystick-left {
label = "Right Joystick Left";
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
};
- button@5 {
+ right-joystick-right {
label = "Right Joystick Right";
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
};
- button@6 {
+ right-joystick-up {
label = "Right Joystick Up";
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
};
- button@7 {
+ right-joystick-down {
label = "Right Joystick Down";
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
};
- button@8 {
+ dpad-left {
label = "DPad Left";
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */
};
- button@9 {
+ dpad-right {
label = "DPad Right";
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
};
- button@10 {
+ dpad-up {
label = "DPad Up";
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
};
- button@11 {
+ dpad-down {
label = "DPad Down";
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
};
- button@12 {
+ x {
label = "Button X";
linux,code = <BTN_X>;
gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */
};
- button@13 {
+ y {
label = "Button Y";
linux,code = <BTN_Y>;
gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */
};
- button@14 {
+ a {
label = "Button A";
linux,code = <BTN_A>;
gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
};
- button@15 {
+ b {
label = "Button B";
linux,code = <BTN_B>;
gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */
};
- button@16 {
+ select {
label = "Select Button";
linux,code = <BTN_SELECT>;
gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
};
- button@17 {
+ start {
label = "Start Button";
linux,code = <BTN_START>;
gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
};
- button@18 {
+ top-left {
label = "Top Left Button";
linux,code = <BTN_TL>;
gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
};
- button@19 {
+ top-right {
label = "Top Right Button";
linux,code = <BTN_TR>;
gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
#include "axp209.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
/* Accelerometer */
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
ft5406ee8: touchscreen@38 {
vref-supply = <®_ldo2>;
status = "okay";
- button@200 {
+ button-200 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <200000>;
};
- button@600 {
+ button-600 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <600000>;
};
- button@800 {
+ button-800 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <800000>;
};
- button@1000 {
+ button-1000 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
voltage = <1000000>;
};
- button@1200 {
+ button-1200 {
label = "Esc";
linux,code = <KEY_ESC>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- key_pins_inet9f: key_pins@0 {
- allwinner,pins = "PA0", "PA1", "PA3", "PA4",
- "PA5", "PA6", "PA8", "PA9",
- "PA11", "PA12", "PA13",
- "PA14", "PA15", "PA16", "PA17",
- "PH22", "PH23", "PH24", "PH25", "PH26";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ key_pins_inet9f: key-pins {
+ pins = "PA0", "PA1", "PA3", "PA4",
+ "PA5", "PA6", "PA8", "PA9",
+ "PA11", "PA12", "PA13",
+ "PA14", "PA15", "PA16", "PA17",
+ "PH22", "PH23", "PH24", "PH25", "PH26";
+ function = "gpio_in";
+ bias-pull-up;
};
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&emac {
pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
+ pinctrl-0 = <&emac_pins>;
phy = <&phy1>;
status = "okay";
};
};
&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
axp209: pmic@34 {
interrupts = <0>;
};
&i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
+ pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&spi0 {
pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins_a>,
- <&spi0_cs0_pins_a>;
+ pinctrl-0 = <&spi0_pi_pins>,
+ <&spi0_cs0_pi_pin>;
status = "okay";
};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb_pins>;
+};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Jesurun Q5";
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_q5>;
green {
label = "q5:green:usr";
reg_emac_3v3: emac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&emac_power_pin_q5>;
regulator-name = "emac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pins>;
status = "okay";
};
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
status = "okay";
};
-&pio {
- emac_power_pin_q5: emac_power_pin@0 {
- allwinner,pins = "PH19";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- led_pins_q5: led_pins@0 {
- allwinner,pins = "PH20";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
®_usb0_vbus {
regulator-boot-on;
status = "okay";
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "HAOYU Electronics Marsboard A10";
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_marsboard>;
red1 {
label = "marsboard:red1:usr";
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- led_pins_marsboard: led_pins@0 {
- allwinner,pins = "PB5", "PB6", "PB7", "PB8";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
&spi0 {
pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins_a>,
- <&spi0_cs0_pins_a>;
+ pinctrl-0 = <&spi0_pi_pins>,
+ <&spi0_cs0_pi_pin>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "PineRiver Mini X-Plus";
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
&ir0 {
pinctrl-names = "default";
- pinctrl-0 = <&ir0_rx_pins_a>;
+ pinctrl-0 = <&ir0_rx_pins>;
status = "okay";
};
-&ir0_rx_pins_a {
+&ir0_rx_pins {
/* The ir receiver is not always populated */
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include "sun4i-a10.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "MK802";
chosen {
stdout-path = "serial0:115200n8";
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
};
&codec {
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb2_vbus_pin_mk802: usb2_vbus_pin@0 {
- allwinner,pins = "PH12";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
®_usb0_vbus {
status = "okay";
};
};
®_usb2_vbus {
- pinctrl-0 = <&usb2_vbus_pin_mk802>;
gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Olimex A10-OLinuXino-LIME";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
864000 1300000
624000 1250000
>;
- cooling-max-level = <2>;
+};
+
+&de {
+ status = "okay";
};
&ehci0 {
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
eeprom: eeprom@50 {
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
- allwinner,pins = "PC3";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- led_pins_olinuxinolime: led_pins@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ led_pins_olinuxinolime: led-pin {
+ pins = "PH2";
+ function = "gpio_out";
+ drive-strength = <20>;
};
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
®_ahci_5v {
- pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "LinkSprite pcDuino";
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_pcduino>;
tx {
label = "pcduino:green:tx";
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&key_pins_pcduino>;
#address-cells = <1>;
#size-cells = <0>;
- button@0 {
+ back {
label = "Key Back";
linux,code = <KEY_BACK>;
gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
};
- button@1 {
+ home {
label = "Key Home";
linux,code = <KEY_HOME>;
gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
};
- button@2 {
+ menu {
label = "Key Menu";
linux,code = <KEY_MENU>;
gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
};
&emac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- led_pins_pcduino: led_pins@0 {
- allwinner,pins = "PH15", "PH16";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- key_pins_pcduino: key_pins@0 {
- allwinner,pins = "PH17", "PH18", "PH19";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10";
};
-&pio {
- usb2_vbus_pin_pcduino2: usb2_vbus_pin@0 {
- allwinner,pins = "PD2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
®_usb2_vbus {
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_vbus_pin_pcduino2>;
gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/pwm/pwm.h>
/ {
backlight: backlight {
compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&bl_en_pin_protab>;
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
};
&codec {
- pinctrl-names = "default";
- pinctrl-0 = <&codec_pa_pin>;
allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
status = "okay";
};
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
#include "axp209.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- status = "okay";
-
- /* Accelerometer */
- bma250@18 {
- compatible = "bosch,bma250";
- reg = <0x18>;
- interrupt-parent = <&pio>;
- interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */
- };
+ /* pull-ups and devices require AXP209 LDO3 */
+ status = "failed";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
- pixcir_ts@5c {
- pinctrl-names = "default";
- pinctrl-0 = <&touchscreen_pins>;
+ touchscreen@5c {
compatible = "pixcir,pixcir_tangoc";
reg = <0x5c>;
interrupt-parent = <&pio>;
vref-supply = <®_ldo2>;
status = "okay";
- button@400 {
+ button-400 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <400000>;
};
- button@800 {
+ button-800 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
};
&pio {
- bl_en_pin_protab: bl_en_pin@0 {
- allwinner,pins = "PH7";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ usb0_id_detect_pin: usb0-id-detect-pin {
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
- codec_pa_pin: codec_pa_pin@0 {
- allwinner,pins = "PH15";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- touchscreen_pins: touchscreen_pins@0 {
- allwinner,pins = "PA5", "PB13";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ usb0_vbus_detect_pin: usb0-vbus-detect-pin {
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins_a>;
+ pinctrl-0 = <&pwm0_pin>;
status = "okay";
};
regulator-name = "avcc";
};
-®_ldo3 {
- /*
- * We need to always power the camera sensor, otherwhise all access
- * to i2c1 is blocked.
- */
- regulator-always-on;
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-name = "vdd-csi";
-};
-
®_usb0_vbus {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
#include <dt-bindings/thermal/thermal.h>
-
-#include <dt-bindings/clock/sun4i-a10-pll2.h>
#include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+#include <dt-bindings/reset/sun4i-a10-ccu.h>
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-parent = <&intc>;
aliases {
#size-cells = <1>;
ranges;
- framebuffer@0 {
+ framebuffer-lcd0-hdmi {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
- clocks = <&ahb_gates 36>, <&ahb_gates 43>,
- <&ahb_gates 44>, <&de_be0_clk>,
- <&tcon0_ch1_clk>, <&dram_gates 26>;
+ clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
+ <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
+ <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
status = "disabled";
};
- framebuffer@1 {
+ framebuffer-fe0-lcd0-hdmi {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
- clocks = <&ahb_gates 36>, <&ahb_gates 43>,
- <&ahb_gates 44>, <&ahb_gates 46>,
- <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>,
- <&dram_gates 25>, <&dram_gates 26>;
+ clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
+ <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
+ <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
+ <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
+ <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
status = "disabled";
};
- framebuffer@2 {
+ framebuffer-fe0-lcd0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0";
- clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
- <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
- <&dram_gates 25>, <&dram_gates 26>;
+ clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
+ <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
+ <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
+ <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
status = "disabled";
};
- framebuffer@3 {
+ framebuffer-fe0-lcd0-tve0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
- clocks = <&ahb_gates 34>, <&ahb_gates 36>,
- <&ahb_gates 44>, <&ahb_gates 46>,
- <&de_be0_clk>, <&de_fe0_clk>,
- <&tcon0_ch1_clk>, <&dram_gates 5>,
- <&dram_gates 25>, <&dram_gates 26>;
+ clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
+ <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
+ <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
+ <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
+ <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
status = "disabled";
};
};
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0x0>;
- clocks = <&cpu>;
+ clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
624000 1250000
>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <3>;
};
};
thermal-zones {
- cpu_thermal {
+ cpu-thermal {
/* milliseconds */
polling-delay-passive = <250>;
polling-delay = <1000>;
};
trips {
- cpu_alert0: cpu_alert0 {
+ cpu_alert0: cpu-alert0 {
/* milliCelsius */
temperature = <850000>;
hysteresis = <2000>;
type = "passive";
};
- cpu_crit: cpu_crit {
+ cpu_crit: cpu-crit {
/* milliCelsius */
temperature = <100000>;
hysteresis = <2000>;
};
};
- memory {
- reg = <0x40000000 0x80000000>;
- };
-
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- /*
- * This is a dummy clock, to be used as placeholder on
- * other mux clocks when a specific parent clock is not
- * yet implemented. It should be dropped when the driver
- * is complete.
- */
- dummy: dummy {
+ osc24M: clk-24M {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-osc-clk";
- reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
- osc3M: osc3M_clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <8>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "osc3M";
- };
-
- osc32k: clk@0 {
+ osc32k: clk-32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
+ };
- pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll1";
- };
-
- pll2: clk@01c20008 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll2-clk";
- reg = <0x01c20008 0x8>;
- clocks = <&osc24M>;
- clock-output-names = "pll2-1x", "pll2-2x",
- "pll2-4x", "pll2-8x";
- };
-
- pll3: clk@01c20010 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll3-clk";
- reg = <0x01c20010 0x4>;
- clocks = <&osc3M>;
- clock-output-names = "pll3";
- };
-
- pll3x2: pll3x2_clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <2>;
- clocks = <&pll3>;
- clock-output-names = "pll3-2x";
- };
-
- pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll4";
- };
-
- pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll5-clk";
- reg = <0x01c20020 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
- pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll6-clk";
- reg = <0x01c20028 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll6_sata", "pll6_other", "pll6";
- };
-
- pll7: clk@01c20030 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll3-clk";
- reg = <0x01c20030 0x4>;
- clocks = <&osc3M>;
- clock-output-names = "pll7";
- };
-
- pll7x2: pll7x2_clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <2>;
- clocks = <&pll7>;
- clock-output-names = "pll7-2x";
- };
-
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
- clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
- clock-output-names = "axi";
- };
-
- axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
- clocks = <&axi>;
- clock-indices = <0>;
- clock-output-names = "axi_dram";
- };
-
- ahb: ahb@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
- clock-output-names = "ahb";
- };
-
- ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
- clocks = <&ahb>;
- clock-indices = <0>, <1>,
- <2>, <3>,
- <4>, <5>, <6>,
- <7>, <8>, <9>,
- <10>, <11>, <12>,
- <13>, <14>, <16>,
- <17>, <18>, <20>,
- <21>, <22>, <23>,
- <24>, <25>, <26>,
- <32>, <33>, <34>,
- <35>, <36>, <37>,
- <40>, <41>, <43>,
- <44>, <45>,
- <46>, <47>,
- <50>, <52>;
- clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1",
- "ahb_ohci1", "ahb_ss", "ahb_dma",
- "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms",
- "ahb_nand", "ahb_sdram", "ahb_ace",
- "ahb_emac", "ahb_ts", "ahb_spi0",
- "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps",
- "ahb_ve", "ahb_tvd", "ahb_tve0",
- "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
- "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1",
- "ahb_de_fe0", "ahb_de_fe1",
- "ahb_mp", "ahb_mali400";
- };
-
- apb0: apb0@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
- clock-output-names = "apb0";
- };
-
- apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
- clocks = <&apb0>;
- clock-indices = <0>, <1>,
- <2>, <3>,
- <5>, <6>,
- <7>, <10>;
- clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis",
- "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
- };
-
- apb1: clk@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- clock-output-names = "apb1";
- };
-
- apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
- clocks = <&apb1>;
- clock-indices = <0>, <1>,
- <2>, <4>,
- <5>, <6>,
- <7>, <16>,
- <17>, <18>,
- <19>, <20>,
- <21>, <22>,
- <23>;
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can",
- "apb1_scr", "apb1_ps20",
- "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2",
- "apb1_uart3", "apb1_uart4",
- "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
- };
-
- nand_clk: clk@01c20080 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20080 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "nand";
- };
-
- ms_clk: clk@01c20084 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20084 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ms";
- };
-
- mmc0_clk: clk@01c20088 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0",
- "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk@01c2008c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc1",
- "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk@01c20090 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc2",
- "mmc2_output",
- "mmc2_sample";
- };
-
- mmc3_clk: clk@01c20094 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20094 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc3",
- "mmc3_output",
- "mmc3_sample";
- };
-
- ts_clk: clk@01c20098 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20098 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ts";
- };
-
- ss_clk: clk@01c2009c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c2009c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ss";
- };
-
- spi0_clk: clk@01c200a0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi0";
- };
-
- spi1_clk: clk@01c200a4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi1";
- };
-
- spi2_clk: clk@01c200a8 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a8 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi2";
- };
-
- pata_clk: clk@01c200ac {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200ac 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "pata";
- };
-
- ir0_clk: clk@01c200b0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200b0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir0";
- };
-
- ir1_clk: clk@01c200b4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200b4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir1";
- };
-
- spdif_clk: clk@01c200c0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod1-clk";
- reg = <0x01c200c0 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_8X>,
- <&pll2 SUN4I_A10_PLL2_4X>,
- <&pll2 SUN4I_A10_PLL2_2X>,
- <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "spdif";
- };
-
- usb_clk: clk@01c200cc {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun4i-a10-usb-clk";
- reg = <0x01c200cc 0x4>;
- clocks = <&pll6 1>;
- clock-output-names = "usb_ohci0", "usb_ohci1",
- "usb_phy";
- };
-
- spi3_clk: clk@01c200d4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200d4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi3";
- };
-
- dram_gates: clk@01c20100 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-dram-gates-clk";
- reg = <0x01c20100 0x4>;
- clocks = <&pll5 0>;
- clock-indices = <0>,
- <1>, <2>,
- <3>,
- <4>,
- <5>, <6>,
- <15>,
- <24>, <25>,
- <26>, <27>,
- <28>, <29>;
- clock-output-names = "dram_ve",
- "dram_csi0", "dram_csi1",
- "dram_ts",
- "dram_tvd",
- "dram_tve0", "dram_tve1",
- "dram_output",
- "dram_de_fe1", "dram_de_fe0",
- "dram_de_be0", "dram_de_be1",
- "dram_de_mp", "dram_ace";
- };
-
- de_be0_clk: clk@01c20104 {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c20104 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-be0";
- };
-
- de_be1_clk: clk@01c20108 {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c20108 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-be1";
- };
-
- de_fe0_clk: clk@01c2010c {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c2010c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-fe0";
- };
-
- de_fe1_clk: clk@01c20110 {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c20110 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-fe1";
- };
-
-
- tcon0_ch0_clk: clk@01c20118 {
- #clock-cells = <0>;
- #reset-cells = <1>;
- compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
- reg = <0x01c20118 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon0-ch0-sclk";
-
- };
-
- tcon1_ch0_clk: clk@01c2011c {
- #clock-cells = <0>;
- #reset-cells = <1>;
- compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
- reg = <0x01c2011c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon1-ch0-sclk";
-
- };
-
- tcon0_ch1_clk: clk@01c2012c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
- reg = <0x01c2012c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon0-ch1-sclk";
-
- };
-
- tcon1_ch1_clk: clk@01c20130 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
- reg = <0x01c20130 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon1-ch1-sclk";
-
- };
-
- ve_clk: clk@01c2013c {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-ve-clk";
- reg = <0x01c2013c 0x4>;
- clocks = <&pll4>;
- clock-output-names = "ve";
- };
-
- codec_clk: clk@01c20140 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-codec-clk";
- reg = <0x01c20140 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "codec";
- };
+ de: display-engine {
+ compatible = "allwinner,sun4i-a10-display-engine";
+ allwinner,pipelines = <&fe0>, <&fe1>;
+ status = "disabled";
};
- soc@01c00000 {
+ soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sram-controller@01c00000 {
+ sram-controller@1c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sram_a: sram@00000000 {
+ sram_a: sram@0 {
compatible = "mmio-sram";
reg = <0x00000000 0xc000>;
#address-cells = <1>;
};
};
- sram_d: sram@00010000 {
+ sram_d: sram@10000 {
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00010000 0x1000>;
- otg_sram: sram-section@0000 {
+ otg_sram: sram-section@0 {
compatible = "allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
- dma: dma-controller@01c02000 {
+ dma: dma-controller@1c02000 {
compatible = "allwinner,sun4i-a10-dma";
reg = <0x01c02000 0x1000>;
interrupts = <27>;
- clocks = <&ahb_gates 6>;
+ clocks = <&ccu CLK_AHB_DMA>;
#dma-cells = <2>;
};
- nfc: nand@01c03000 {
+ nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
- clocks = <&ahb_gates 13>, <&nand_clk>;
+ clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 3>;
dma-names = "rxtx";
#size-cells = <0>;
};
- spi0: spi@01c05000 {
+ spi0: spi@1c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
interrupts = <10>;
- clocks = <&ahb_gates 20>, <&spi0_clk>;
+ clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
<&dma SUN4I_DMA_DEDICATED 26>;
#size-cells = <0>;
};
- spi1: spi@01c06000 {
+ spi1: spi@1c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
- clocks = <&ahb_gates 21>, <&spi1_clk>;
+ clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
<&dma SUN4I_DMA_DEDICATED 8>;
dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- emac: ethernet@01c0b000 {
+ emac: ethernet@1c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
interrupts = <55>;
- clocks = <&ahb_gates 17>;
+ clocks = <&ccu CLK_AHB_EMAC>;
allwinner,sram = <&emac_sram 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins>;
status = "disabled";
};
- mdio: mdio@01c0b080 {
+ mdio: mdio@1c0b080 {
compatible = "allwinner,sun4i-a10-mdio";
reg = <0x01c0b080 0x14>;
status = "disabled";
#size-cells = <0>;
};
- mmc0: mmc@01c0f000 {
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun4i-a10-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <44>;
+ resets = <&ccu RST_TCON0>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB_LCD0>,
+ <&ccu CLK_TCON0_CH0>,
+ <&ccu CLK_TCON0_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon0-pixel-clock";
+ dmas = <&dma SUN4I_DMA_DEDICATED 14>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon0>;
+ };
+
+ tcon0_in_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon0_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon0>;
+ allwinner,tcon-channel = <1>;
+ };
+ };
+ };
+ };
+
+ tcon1: lcd-controller@1c0d000 {
+ compatible = "allwinner,sun4i-a10-tcon";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <45>;
+ resets = <&ccu RST_TCON1>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB_LCD1>,
+ <&ccu CLK_TCON1_CH0>,
+ <&ccu CLK_TCON1_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon1-pixel-clock";
+ dmas = <&dma SUN4I_DMA_DEDICATED 15>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon1>;
+ };
+
+ tcon1_in_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon1_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon1>;
+ allwinner,tcon-channel = <1>;
+ };
+ };
+ };
+ };
+
+ mmc0: mmc@1c0f000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ahb_gates 8>,
- <&mmc0_clk 0>,
- <&mmc0_clk 1>,
- <&mmc0_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
interrupts = <32>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- mmc1: mmc@01c10000 {
+ mmc1: mmc@1c10000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ahb_gates 9>,
- <&mmc1_clk 0>,
- <&mmc1_clk 1>,
- <&mmc1_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
interrupts = <33>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- mmc2: mmc@01c11000 {
+ mmc2: mmc@1c11000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ahb_gates 10>,
- <&mmc2_clk 0>,
- <&mmc2_clk 1>,
- <&mmc2_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
interrupts = <34>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- mmc3: mmc@01c12000 {
+ mmc3: mmc@1c12000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c12000 0x1000>;
- clocks = <&ahb_gates 11>,
- <&mmc3_clk 0>,
- <&mmc3_clk 1>,
- <&mmc3_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
+ clock-names = "ahb", "mmc";
interrupts = <35>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- usb_otg: usb@01c13000 {
+ usb_otg: usb@1c13000 {
compatible = "allwinner,sun4i-a10-musb";
reg = <0x01c13000 0x0400>;
- clocks = <&ahb_gates 0>;
+ clocks = <&ccu CLK_AHB_OTG>;
interrupts = <38>;
interrupt-names = "mc";
phys = <&usbphy 0>;
status = "disabled";
};
- usbphy: phy@01c13400 {
+ usbphy: phy@1c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun4i-a10-usb-phy";
reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
reg-names = "phy_ctrl", "pmu1", "pmu2";
- clocks = <&usb_clk 8>;
+ clocks = <&ccu CLK_USB_PHY>;
clock-names = "usb_phy";
- resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>;
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
status = "disabled";
};
- ehci0: usb@01c14000 {
+ ehci0: usb@1c14000 {
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
reg = <0x01c14000 0x100>;
interrupts = <39>;
- clocks = <&ahb_gates 1>;
+ clocks = <&ccu CLK_AHB_EHCI0>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
- ohci0: usb@01c14400 {
+ ohci0: usb@1c14400 {
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
reg = <0x01c14400 0x100>;
interrupts = <64>;
- clocks = <&usb_clk 6>, <&ahb_gates 2>;
+ clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
- crypto: crypto-engine@01c15000 {
+ crypto: crypto-engine@1c15000 {
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <86>;
- clocks = <&ahb_gates 5>, <&ss_clk>;
+ clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
clock-names = "ahb", "mod";
};
- spi2: spi@01c17000 {
+ hdmi: hdmi@1c16000 {
+ compatible = "allwinner,sun4i-a10-hdmi";
+ reg = <0x01c16000 0x1000>;
+ interrupts = <58>;
+ clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
+ <&ccu CLK_PLL_VIDEO0_2X>,
+ <&ccu CLK_PLL_VIDEO1_2X>;
+ clock-names = "ahb", "mod", "pll-0", "pll-1";
+ dmas = <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_DEDICATED 24>;
+ dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_hdmi>;
+ };
+
+ hdmi_in_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+ spi2: spi@1c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
interrupts = <12>;
- clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
<&dma SUN4I_DMA_DEDICATED 28>;
#size-cells = <0>;
};
- ahci: sata@01c18000 {
+ ahci: sata@1c18000 {
compatible = "allwinner,sun4i-a10-ahci";
reg = <0x01c18000 0x1000>;
interrupts = <56>;
- clocks = <&pll6 0>, <&ahb_gates 25>;
+ clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
status = "disabled";
};
- ehci1: usb@01c1c000 {
+ ehci1: usb@1c1c000 {
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
reg = <0x01c1c000 0x100>;
interrupts = <40>;
- clocks = <&ahb_gates 3>;
+ clocks = <&ccu CLK_AHB_EHCI1>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
- ohci1: usb@01c1c400 {
+ ohci1: usb@1c1c400 {
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
reg = <0x01c1c400 0x100>;
interrupts = <65>;
- clocks = <&usb_clk 7>, <&ahb_gates 4>;
+ clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
- spi3: spi@01c1f000 {
+ spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
interrupts = <50>;
- clocks = <&ahb_gates 23>, <&spi3_clk>;
+ clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 31>,
<&dma SUN4I_DMA_DEDICATED 30>;
#size-cells = <0>;
};
- intc: interrupt-controller@01c20400 {
+ ccu: clock@1c20000 {
+ compatible = "allwinner,sun4i-a10-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ intc: interrupt-controller@1c20400 {
compatible = "allwinner,sun4i-a10-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
- pio: pinctrl@01c20800 {
+ pio: pinctrl@1c20800 {
compatible = "allwinner,sun4i-a10-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <28>;
- clocks = <&apb0_gates 5>;
+ clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
- emac_pins_a: emac0@0 {
- allwinner,pins = "PA0", "PA1", "PA2",
- "PA3", "PA4", "PA5", "PA6",
- "PA7", "PA8", "PA9", "PA10",
- "PA11", "PA12", "PA13", "PA14",
- "PA15", "PA16";
- allwinner,function = "emac";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ can0_ph_pins: can0-ph-pins {
+ pins = "PH20", "PH21";
+ function = "can";
};
- i2c0_pins_a: i2c0@0 {
- allwinner,pins = "PB0", "PB1";
- allwinner,function = "i2c0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ emac_pins: emac0-pins {
+ pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ function = "emac";
};
- i2c1_pins_a: i2c1@0 {
- allwinner,pins = "PB18", "PB19";
- allwinner,function = "i2c1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ i2c0_pins: i2c0-pins {
+ pins = "PB0", "PB1";
+ function = "i2c0";
};
- i2c2_pins_a: i2c2@0 {
- allwinner,pins = "PB20", "PB21";
- allwinner,function = "i2c2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ i2c1_pins: i2c1-pins {
+ pins = "PB18", "PB19";
+ function = "i2c1";
};
- ir0_rx_pins_a: ir0@0 {
- allwinner,pins = "PB4";
- allwinner,function = "ir0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ i2c2_pins: i2c2-pins {
+ pins = "PB20", "PB21";
+ function = "i2c2";
};
- ir0_tx_pins_a: ir0@1 {
- allwinner,pins = "PB3";
- allwinner,function = "ir0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ ir0_rx_pins: ir0-rx-pin {
+ pins = "PB4";
+ function = "ir0";
};
- ir1_rx_pins_a: ir1@0 {
- allwinner,pins = "PB23";
- allwinner,function = "ir1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ ir0_tx_pins: ir0-tx-pin {
+ pins = "PB3";
+ function = "ir0";
};
- ir1_tx_pins_a: ir1@1 {
- allwinner,pins = "PB22";
- allwinner,function = "ir1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ ir1_rx_pins: ir1-rx-pin {
+ pins = "PB23";
+ function = "ir1";
};
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0", "PF1", "PF2",
- "PF3", "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ ir1_tx_pins: ir1-tx-pin {
+ pins = "PB22";
+ function = "ir1";
};
- mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
- allwinner,pins = "PH1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2",
+ "PF3", "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
};
- ps20_pins_a: ps20@0 {
- allwinner,pins = "PI20", "PI21";
- allwinner,function = "ps2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ ps2_ch0_pins: ps2-ch0-pins {
+ pins = "PI20", "PI21";
+ function = "ps2";
};
- ps21_pins_a: ps21@0 {
- allwinner,pins = "PH12", "PH13";
- allwinner,function = "ps2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ ps2_ch1_ph_pins: ps2-ch1-ph-pins {
+ pins = "PH12", "PH13";
+ function = "ps2";
};
- pwm0_pins_a: pwm0@0 {
- allwinner,pins = "PB2";
- allwinner,function = "pwm";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pwm0_pin: pwm0-pin {
+ pins = "PB2";
+ function = "pwm";
};
- pwm1_pins_a: pwm1@0 {
- allwinner,pins = "PI3";
- allwinner,function = "pwm";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pwm1_pin: pwm1-pin {
+ pins = "PI3";
+ function = "pwm";
};
- spdif_tx_pins_a: spdif@0 {
- allwinner,pins = "PB13";
- allwinner,function = "spdif";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ spdif_tx_pin: spdif-tx-pin {
+ pins = "PB13";
+ function = "spdif";
+ bias-pull-up;
};
- spi0_pins_a: spi0@0 {
- allwinner,pins = "PI11", "PI12", "PI13";
- allwinner,function = "spi0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi0_pi_pins: spi0-pi-pins {
+ pins = "PI11", "PI12", "PI13";
+ function = "spi0";
};
- spi0_cs0_pins_a: spi0_cs0@0 {
- allwinner,pins = "PI10";
- allwinner,function = "spi0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi0_cs0_pi_pin: spi0-cs0-pi-pin {
+ pins = "PI10";
+ function = "spi0";
};
- spi1_pins_a: spi1@0 {
- allwinner,pins = "PI17", "PI18", "PI19";
- allwinner,function = "spi1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi1_pins: spi1-pins {
+ pins = "PI17", "PI18", "PI19";
+ function = "spi1";
};
- spi1_cs0_pins_a: spi1_cs0@0 {
- allwinner,pins = "PI16";
- allwinner,function = "spi1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi1_cs0_pin: spi1-cs0-pin {
+ pins = "PI16";
+ function = "spi1";
};
- spi2_pins_a: spi2@0 {
- allwinner,pins = "PC20", "PC21", "PC22";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi2_pb_pins: spi2-pb-pins {
+ pins = "PB15", "PB16", "PB17";
+ function = "spi2";
};
- spi2_pins_b: spi2@1 {
- allwinner,pins = "PB15", "PB16", "PB17";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi2_pc_pins: spi2-pc-pins {
+ pins = "PC20", "PC21", "PC22";
+ function = "spi2";
};
- spi2_cs0_pins_a: spi2_cs0@0 {
- allwinner,pins = "PC19";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi2_cs0_pb_pin: spi2-cs0-pb-pin {
+ pins = "PB14";
+ function = "spi2";
};
- spi2_cs0_pins_b: spi2_cs0@1 {
- allwinner,pins = "PB14";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi2_cs0_pc_pins: spi2-cs0-pc-pin {
+ pins = "PC19";
+ function = "spi2";
};
- uart0_pins_a: uart0@0 {
- allwinner,pins = "PB22", "PB23";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart0_pb_pins: uart0-pb-pins {
+ pins = "PB22", "PB23";
+ function = "uart0";
};
- uart0_pins_b: uart0@1 {
- allwinner,pins = "PF2", "PF4";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart0_pf_pins: uart0-pf-pins {
+ pins = "PF2", "PF4";
+ function = "uart0";
};
- uart1_pins_a: uart1@0 {
- allwinner,pins = "PA10", "PA11";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart1_pins: uart1-pins {
+ pins = "PA10", "PA11";
+ function = "uart1";
};
};
- timer@01c20c00 {
+ timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
clocks = <&osc24M>;
};
- wdt: watchdog@01c20c90 {
+ wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
};
- rtc: rtc@01c20d00 {
+ rtc: rtc@1c20d00 {
compatible = "allwinner,sun4i-a10-rtc";
reg = <0x01c20d00 0x20>;
interrupts = <24>;
};
- pwm: pwm@01c20e00 {
+ pwm: pwm@1c20e00 {
compatible = "allwinner,sun4i-a10-pwm";
reg = <0x01c20e00 0xc>;
clocks = <&osc24M>;
status = "disabled";
};
- spdif: spdif@01c21000 {
+ spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-spdif";
reg = <0x01c21000 0x400>;
interrupts = <13>;
- clocks = <&apb0_gates 1>, <&spdif_clk>;
+ clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
clock-names = "apb", "spdif";
dmas = <&dma SUN4I_DMA_NORMAL 2>,
<&dma SUN4I_DMA_NORMAL 2>;
status = "disabled";
};
- ir0: ir@01c21800 {
+ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
- clocks = <&apb0_gates 6>, <&ir0_clk>;
+ clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
clock-names = "apb", "ir";
interrupts = <5>;
reg = <0x01c21800 0x40>;
status = "disabled";
};
- ir1: ir@01c21c00 {
+ ir1: ir@1c21c00 {
compatible = "allwinner,sun4i-a10-ir";
- clocks = <&apb0_gates 7>, <&ir1_clk>;
+ clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
clock-names = "apb", "ir";
interrupts = <6>;
reg = <0x01c21c00 0x40>;
status = "disabled";
};
- lradc: lradc@01c22800 {
+ i2s0: i2s@1c22400 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-i2s";
+ reg = <0x01c22400 0x400>;
+ interrupts = <16>;
+ clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ dmas = <&dma SUN4I_DMA_NORMAL 3>,
+ <&dma SUN4I_DMA_NORMAL 3>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <31>;
status = "disabled";
};
- codec: codec@01c22c00 {
+ codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-codec";
reg = <0x01c22c00 0x40>;
interrupts = <30>;
- clocks = <&apb0_gates 0>, <&codec_clk>;
+ clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
clock-names = "apb", "codec";
dmas = <&dma SUN4I_DMA_NORMAL 19>,
<&dma SUN4I_DMA_NORMAL 19>;
status = "disabled";
};
- sid: eeprom@01c23800 {
+ sid: eeprom@1c23800 {
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>;
};
- rtp: rtp@01c25000 {
+ rtp: rtp@1c25000 {
compatible = "allwinner,sun4i-a10-ts";
reg = <0x01c25000 0x100>;
interrupts = <29>;
#thermal-sensor-cells = <0>;
};
- uart0: serial@01c28000 {
+ uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 16>;
+ clocks = <&ccu CLK_APB1_UART0>;
status = "disabled";
};
- uart1: serial@01c28400 {
+ uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 17>;
+ clocks = <&ccu CLK_APB1_UART1>;
status = "disabled";
};
- uart2: serial@01c28800 {
+ uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <3>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 18>;
+ clocks = <&ccu CLK_APB1_UART2>;
status = "disabled";
};
- uart3: serial@01c28c00 {
+ uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <4>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 19>;
+ clocks = <&ccu CLK_APB1_UART3>;
status = "disabled";
};
- uart4: serial@01c29000 {
+ uart4: serial@1c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <17>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 20>;
+ clocks = <&ccu CLK_APB1_UART4>;
status = "disabled";
};
- uart5: serial@01c29400 {
+ uart5: serial@1c29400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29400 0x400>;
interrupts = <18>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 21>;
+ clocks = <&ccu CLK_APB1_UART5>;
status = "disabled";
};
- uart6: serial@01c29800 {
+ uart6: serial@1c29800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29800 0x400>;
interrupts = <19>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 22>;
+ clocks = <&ccu CLK_APB1_UART6>;
status = "disabled";
};
- uart7: serial@01c29c00 {
+ uart7: serial@1c29c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29c00 0x400>;
interrupts = <20>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 23>;
+ clocks = <&ccu CLK_APB1_UART7>;
status = "disabled";
};
- i2c0: i2c@01c2ac00 {
+ ps20: ps2@1c2a000 {
+ compatible = "allwinner,sun4i-a10-ps2";
+ reg = <0x01c2a000 0x400>;
+ interrupts = <62>;
+ clocks = <&ccu CLK_APB1_PS20>;
+ status = "disabled";
+ };
+
+ ps21: ps2@1c2a400 {
+ compatible = "allwinner,sun4i-a10-ps2";
+ reg = <0x01c2a400 0x400>;
+ interrupts = <63>;
+ clocks = <&ccu CLK_APB1_PS21>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <7>;
- clocks = <&apb1_gates 0>;
+ clocks = <&ccu CLK_APB1_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c1: i2c@01c2b000 {
+ i2c1: i2c@1c2b000 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <8>;
- clocks = <&apb1_gates 1>;
+ clocks = <&ccu CLK_APB1_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c2: i2c@01c2b400 {
+ i2c2: i2c@1c2b400 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <9>;
- clocks = <&apb1_gates 2>;
+ clocks = <&ccu CLK_APB1_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- ps20: ps2@01c2a000 {
- compatible = "allwinner,sun4i-a10-ps2";
- reg = <0x01c2a000 0x400>;
- interrupts = <62>;
- clocks = <&apb1_gates 6>;
+ can0: can@1c2bc00 {
+ compatible = "allwinner,sun4i-a10-can";
+ reg = <0x01c2bc00 0x400>;
+ interrupts = <26>;
+ clocks = <&ccu CLK_APB1_CAN>;
status = "disabled";
};
- ps21: ps2@01c2a400 {
- compatible = "allwinner,sun4i-a10-ps2";
- reg = <0x01c2a400 0x400>;
- interrupts = <63>;
- clocks = <&apb1_gates 7>;
- status = "disabled";
+ fe0: display-frontend@1e00000 {
+ compatible = "allwinner,sun4i-a10-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <47>;
+ clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
+ <&ccu CLK_DRAM_DE_FE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_FE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+
+ fe0_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_fe0>;
+ };
+ };
+ };
+ };
+
+ fe1: display-frontend@1e20000 {
+ compatible = "allwinner,sun4i-a10-display-frontend";
+ reg = <0x01e20000 0x20000>;
+ interrupts = <48>;
+ clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
+ <&ccu CLK_DRAM_DE_FE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_FE1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe1_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe1>;
+ };
+
+ fe1_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_fe1>;
+ };
+ };
+ };
+ };
+
+ be1: display-backend@1e40000 {
+ compatible = "allwinner,sun4i-a10-display-backend";
+ reg = <0x01e40000 0x10000>;
+ interrupts = <48>;
+ clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
+ <&ccu CLK_DRAM_DE_BE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_BE1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be1_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be1>;
+ };
+
+ be1_in_fe1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&fe1_out_be1>;
+ };
+ };
+
+ be1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be1_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be1>;
+ };
+
+ be1_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_be1>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@1e60000 {
+ compatible = "allwinner,sun4i-a10-display-backend";
+ reg = <0x01e60000 0x10000>;
+ interrupts = <47>;
+ clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
+ <&ccu CLK_DRAM_DE_BE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_BE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+
+ be0_in_fe1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&fe1_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be0>;
+ };
+
+ be0_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_be0>;
+ };
+ };
+ };
};
};
};
#include "sun5i-a10s.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Auxtek t003 A10s hdmi tv-stick";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
&pio {
mmc0_cd_pin_t003: mmc0_cd_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG1";
+ function = "gpio_in";
+ bias-pull-up;
};
led_pins_t003: led_pins@0 {
- allwinner,pins = "PB2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB2";
+ function = "gpio_out";
+ drive-strength = <20>;
};
};
status = "okay";
};
-&usb0_vbus_pin_a {
- allwinner,pins = "PG13";
-};
-
-&usb1_vbus_pin_a {
- allwinner,pins = "PB10";
-};
-
&usb_otg {
dr_mode = "host";
status = "okay";
#include "sun5i-a10s.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Auxtek t004 A10s hdmi tv-stick";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
status = "okay";
};
+&otg_sram {
+ status = "okay";
+};
+
&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ pins = "PG12";
+ function = "gpio_in";
+ bias-pull-up;
+ };
+
mmc0_cd_pin_t004: mmc0_cd_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG1";
+ function = "gpio_in";
+ bias-pull-up;
};
mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin@0 {
- allwinner,pins = "PB18";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB18";
+ function = "gpio_out";
};
led_pins_t004: led_pins@0 {
- allwinner,pins = "PB2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB2";
+ function = "gpio_out";
+ drive-strength = <20>;
};
};
status = "okay";
};
-&usb1_vbus_pin_a {
- allwinner,pins = "PG13";
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
};
&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
};
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
&pio {
led_pins_mk802: led_pins@0 {
- allwinner,pins = "PB2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB2";
+ function = "gpio_out";
};
mmc0_cd_pin_mk802: mmc0_cd_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG1";
+ function = "gpio_in";
+ bias-pull-up;
};
usb1_vbus_pin_mk802: usb1_vbus_pin@0 {
- allwinner,pins = "PB10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB10";
+ function = "gpio_out";
};
};
};
&usb_otg {
- dr_mode = "otg";
+ dr_mode = "peripheral";
status = "okay";
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Olimex A10s-Olinuxino Micro";
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
};
};
+&be0 {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
&emac {
pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
+ pinctrl-0 = <&emac_pins_b>;
phy = <&phy1>;
status = "okay";
};
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
- cd-inverted;
+ cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
status = "okay";
};
&pio {
mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG1";
+ function = "gpio_in";
+ bias-pull-up;
};
mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
- allwinner,pins = "PG13";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG13";
+ function = "gpio_in";
+ bias-pull-up;
};
led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PE3";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PE3";
+ function = "gpio_out";
+ drive-strength = <20>;
};
usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 {
- allwinner,pins = "PB10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB10";
+ function = "gpio_out";
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PG12";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG12";
+ function = "gpio_in";
+ bias-pull-up;
};
};
&spi2 {
pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>,
- <&spi2_cs0_pins_a>;
+ pinctrl-0 = <&spi2_pins_b>,
+ <&spi2_cs0_pins_b>;
+ status = "okay";
+};
+
+&tcon0 {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins_a>;
+ pinctrl-0 = <&uart2_pins_b>;
status = "okay";
};
status = "okay";
};
-&usb0_vbus_pin_a {
- allwinner,pins = "PG11";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "R7 A10s hdmi tv-stick";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- cd-inverted;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
status = "okay";
};
&pio {
mmc0_cd_pin_r7: mmc0_cd_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG1";
+ function = "gpio_in";
+ bias-pull-up;
};
led_pins_r7: led_pins@0 {
- allwinner,pins = "PB2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB2";
+ function = "gpio_out";
+ drive-strength = <20>;
};
usb1_vbus_pin_r7: usb1_vbus_pin@0 {
- allwinner,pins = "PG13";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG13";
+ function = "gpio_out";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "A10s-Wobo i5";
&emac {
pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_b>;
+ pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
- cd-inverted;
+ cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */
status = "okay";
};
&pio {
led_pins_wobo_i5: led_pins@0 {
- allwinner,pins = "PB2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB2";
+ function = "gpio_out";
};
mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 {
- allwinner,pins = "PB3";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PB3";
+ function = "gpio_in";
+ bias-pull-up;
};
emac_power_pin_wobo: emac_power_pin@0 {
- allwinner,pins = "PA02";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PA02";
+ function = "gpio_out";
};
};
status = "okay";
};
-&usb1_vbus_pin_a {
- allwinner,pins = "PG12";
-};
-
&usbphy {
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
#include "sun5i.dtsi"
#include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
interrupt-parent = <&intc>;
#size-cells = <1>;
ranges;
- framebuffer@0 {
+ framebuffer@2 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
- clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
- <&ahb_gates 43>, <&ahb_gates 44>;
- status = "disabled";
- };
-
- framebuffer@1 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0";
- clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
- <&ahb_gates 44>;
+ clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
+ <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
+ <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
status = "disabled";
};
+ };
- framebuffer@2 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0-tve0";
- clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
- <&ahb_gates 36>, <&ahb_gates 44>;
- status = "disabled";
- };
+ display-engine {
+ compatible = "allwinner,sun5i-a10s-display-engine";
+ allwinner,pipelines = <&fe0>;
};
- clocks {
- ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
- clocks = <&ahb>;
- clock-indices = <0>, <1>,
- <2>, <5>, <6>,
- <7>, <8>, <9>,
- <10>, <13>,
- <14>, <17>, <18>,
- <20>, <21>, <22>,
- <26>, <28>, <32>,
- <34>, <36>, <40>,
- <43>, <44>,
- <46>, <51>,
- <52>;
- clock-output-names = "ahb_usbotg", "ahb_ehci",
- "ahb_ohci", "ahb_ss", "ahb_dma",
- "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_nand",
- "ahb_sdram", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2",
- "ahb_gps", "ahb_stimer", "ahb_ve",
- "ahb_tve", "ahb_lcd", "ahb_csi",
- "ahb_hdmi", "ahb_de_be",
- "ahb_de_fe", "ahb_iep",
- "ahb_mali400";
- };
+ soc@1c00000 {
+ hdmi: hdmi@1c16000 {
+ compatible = "allwinner,sun5i-a10s-hdmi";
+ reg = <0x01c16000 0x1000>;
+ interrupts = <58>;
+ clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
+ <&ccu CLK_PLL_VIDEO0_2X>,
+ <&ccu CLK_PLL_VIDEO1_2X>;
+ clock-names = "ahb", "mod", "pll-0", "pll-1";
+ dmas = <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_DEDICATED 24>;
+ dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+ status = "disabled";
- apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
- clocks = <&apb0>;
- clock-indices = <0>, <3>,
- <5>, <6>,
- <10>;
- clock-output-names = "apb0_codec", "apb0_iis",
- "apb0_pio", "apb0_ir",
- "apb0_keypad";
- };
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
- clocks = <&apb1>;
- clock-indices = <0>, <1>,
- <2>, <16>,
- <17>, <18>,
- <19>;
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart0",
- "apb1_uart1", "apb1_uart2",
- "apb1_uart3";
- };
- };
+ hdmi_in: port@0 {
+ reg = <0>;
- soc@01c00000 {
- emac: ethernet@01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ahb_gates 17>;
- allwinner,sram = <&emac_sram 1>;
- status = "disabled";
- };
+ hdmi_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_hdmi>;
+ };
+ };
- mdio: mdio@01c0b080 {
- compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
+ hdmi_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
};
- pwm: pwm@01c20e00 {
+ pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
- clocks = <&osc24M>;
+ clocks = <&ccu CLK_HOSC>;
#pwm-cells = <3>;
status = "disabled";
};
-
- uart0: serial@01c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <1>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb1_gates 16>;
- status = "disabled";
- };
-
- uart2: serial@01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <3>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb1_gates 18>;
- status = "disabled";
- };
};
};
+&ccu {
+ compatible = "allwinner,sun5i-a10s-ccu";
+};
+
&pio {
compatible = "allwinner,sun5i-a10s-pinctrl";
uart0_pins_a: uart0@0 {
- allwinner,pins = "PB19", "PB20";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB19", "PB20";
+ function = "uart0";
};
- uart2_pins_a: uart2@0 {
- allwinner,pins = "PC18", "PC19";
- allwinner,function = "uart2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart2_pins_b: uart2@1 {
+ pins = "PC18", "PC19";
+ function = "uart2";
};
- emac_pins_a: emac0@0 {
- allwinner,pins = "PA0", "PA1", "PA2",
+ emac_pins_b: emac0@1 {
+ pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA9", "PA10",
"PA11", "PA12", "PA13", "PA14",
"PA15", "PA16";
- allwinner,function = "emac";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- emac_pins_b: emac0@1 {
- allwinner,pins = "PD6", "PD7", "PD10",
- "PD11", "PD12", "PD13", "PD14",
- "PD15", "PD18", "PD19", "PD20",
- "PD21", "PD22", "PD23", "PD24",
- "PD25", "PD26", "PD27";
- allwinner,function = "emac";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ function = "emac";
};
mmc1_pins_a: mmc1@0 {
- allwinner,pins = "PG3", "PG4", "PG5",
+ pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";
- allwinner,function = "mmc1";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ function = "mmc1";
+ drive-strength = <30>;
};
- spi2_pins_a: spi2@0 {
- allwinner,pins = "PB12", "PB13", "PB14";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi2_pins_b: spi2@1 {
+ pins = "PB12", "PB13", "PB14";
+ function = "spi2";
};
- spi2_cs0_pins_a: spi2_cs0@0 {
- allwinner,pins = "PB11";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spi2_cs0_pins_b: spi2_cs0@1 {
+ pins = "PB11";
+ function = "spi2";
};
};
&sram_a {
- emac_sram: sram-section@8000 {
- compatible = "allwinner,sun4i-a10-sram-a3-a4";
- reg = <0x8000 0x4000>;
- status = "disabled";
+};
+
+&tcon0_out {
+ tcon0_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi_in_tcon0>;
+ allwinner,tcon-channel = <1>;
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/pwm/pwm.h>
/ {
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
&pio {
mmc0_cd_pin_d709: mmc0_cd_pin@0 {
- allwinner,pins = "PG0";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG0";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ pins = "PG1";
+ function = "gpio_in";
+ bias-pull-down;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PG2";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG2";
+ function = "gpio_in";
+ bias-pull-up;
};
};
status = "okay";
};
-&usb0_vbus_pin_a {
- allwinner,pins = "PG12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "HSG H702";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
&pio {
mmc0_cd_pin_h702: mmc0_cd_pin@0 {
- allwinner,pins = "PG0";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG0";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PG2";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG2";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG1";
+ function = "gpio_in";
};
};
};
®_usb0_vbus {
- pinctrl-0 = <&usb0_vbus_pin_a>;
gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
status = "okay";
};
status = "okay";
};
-&usb0_vbus_pin_a {
- allwinner,pins = "PG12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
/dts-v1/;
#include "sun5i-a13.dtsi"
-#include "sunxi-common-regulators.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sun5i-reference-design-tablet.dtsi"
/ {
model = "INet-98V Rev 02";
compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13";
-
- aliases {
- serial0 = &uart1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
-
- axp209: pmic@34 {
- reg = <0x34>;
- interrupts = <0>;
- };
-};
-
-#include "axp209.dtsi"
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- status = "okay";
-
- pcf8563: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-};
-
-&lradc {
- vref-supply = <®_ldo2>;
- status = "okay";
-
- button@200 {
- label = "Volume Up";
- linux,code = <KEY_VOLUMEUP>;
- channel = <0>;
- voltage = <200000>;
- };
-
- button@400 {
- label = "Volume Down";
- linux,code = <KEY_VOLUMEDOWN>;
- channel = <0>;
- voltage = <400000>;
- };
-};
-
-&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
- status = "okay";
-};
-
-&otg_sram {
- status = "okay";
-};
-
-&pio {
- mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 {
- allwinner,pins = "PG0";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PG2";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1400000>;
- regulator-name = "vdd-cpu";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1250000>;
- regulator-max-microvolt = <1250000>;
- regulator-name = "vdd-int-pll";
-};
-
-®_ldo1 {
- regulator-name = "vdd-rtc";
-};
-
-®_ldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "avcc";
-};
-
-®_ldo3 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-wifi";
-};
-
-®_usb0_vbus {
- gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
- status = "okay";
-};
-
-&usb_otg {
- dr_mode = "otg";
- status = "okay";
-};
-
-&usb0_vbus_pin_a {
- allwinner,pins = "PG12";
-};
-
-&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
- usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- usb0_vbus-supply = <®_usb0_vbus>;
- usb1_vbus-supply = <®_ldo3>;
- status = "okay";
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Olimex A13-Olinuxino Micro";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
&pio {
mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
- allwinner,pins = "PG0";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG0";
+ function = "gpio_in";
+ bias-pull-up;
};
led_pins_olinuxinom: led_pins@0 {
- allwinner,pins = "PG9";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG9";
+ function = "gpio_out";
+ drive-strength = <20>;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PG2";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG2";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ pins = "PG1";
+ function = "gpio_in";
+ bias-pull-down;
};
usb0_vbus_pin_olinuxinom: usb0_vbus_pin@0 {
- allwinner,pins = "PG12";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG12";
+ function = "gpio_out";
};
usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 {
- allwinner,pins = "PG11";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG11";
+ function = "gpio_out";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Olimex A13-Olinuxino";
default-state = "on";
};
};
+
+ bridge {
+ compatible = "dumb-vga-dac";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&tcon0_out_vga>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+};
+
+&be0 {
+ status = "okay";
+};
+
+&codec {
+ status = "okay";
};
&ehci0 {
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
&pio {
mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
- allwinner,pins = "PG0";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG0";
+ function = "gpio_in";
+ bias-pull-up;
};
led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PG9";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG9";
+ function = "gpio_out";
+ drive-strength = <20>;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PG2";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG2";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ pins = "PG1";
+ function = "gpio_in";
+ bias-pull-down;
};
usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
- allwinner,pins = "PG11";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG11";
+ function = "gpio_out";
};
};
status = "okay";
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rgb666_pins>;
+ status = "okay";
+};
+
+&tcon0_out {
+ tcon0_out_vga: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vga_bridge_in>;
+ };
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
status = "okay";
};
-&usb0_vbus_pin_a {
- allwinner,pins = "PG12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
};
&codec_pa_pin {
- allwinner,pins = "PG3";
-};
-
-&i2c1 {
- icn8318: touchscreen@40 {
- compatible = "chipone,icn8318";
- reg = <0x40>;
- interrupt-parent = <&pio>;
- interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
- pinctrl-names = "default";
- pinctrl-0 = <&ts_wake_pin_p66>;
- wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
- touchscreen-size-x = <800>;
- touchscreen-size-y = <480>;
- touchscreen-inverted-x;
- touchscreen-swapped-x-y;
- };
+ pins = "PG3";
};
&mmc2 {
&pio {
i2c_lcd_pins: i2c_lcd_pin@0 {
- allwinner,pins = "PG10", "PG12";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-
- ts_wake_pin_p66: ts_wake_pin@0 {
- allwinner,pins = "PB3";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG10", "PG12";
+ function = "gpio_out";
+ bias-pull-up;
};
-
};
®_usb0_vbus {
gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
};
+&touchscreen {
+ compatible = "chipone,icn8318";
+ reg = <0x40>;
+ /* The P66 uses a different EINT then the reference design */
+ interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
+ /* The icn8318 binding expects wake-gpios instead of power-gpios */
+ wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-inverted-x;
+ touchscreen-swapped-x-y;
+ status = "okay";
+};
+
&uart1 {
/* The P66 uses the uart pins as gpios */
status = "disabled";
};
&usb0_vbus_pin_a {
- allwinner,pins = "PB4";
+ pins = "PB4";
};
#include "sun5i.dtsi"
-#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
- chosen {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- framebuffer@0 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0";
- clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
- <&tcon_ch0_clk>, <&dram_gates 26>;
- status = "disabled";
- };
- };
-
thermal-zones {
cpu_thermal {
/* milliseconds */
trips {
cpu_alert0: cpu_alert0 {
/* milliCelsius */
- temperature = <850000>;
+ temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
};
};
- clocks {
- ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
- clocks = <&ahb>;
- clock-indices = <0>, <1>,
- <2>, <5>, <6>,
- <7>, <8>, <9>,
- <10>, <13>,
- <14>, <20>,
- <21>, <22>,
- <28>, <32>, <34>,
- <36>, <40>, <44>,
- <46>, <51>,
- <52>;
- clock-output-names = "ahb_usbotg", "ahb_ehci",
- "ahb_ohci", "ahb_ss", "ahb_dma",
- "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_nand",
- "ahb_sdram", "ahb_spi0",
- "ahb_spi1", "ahb_spi2",
- "ahb_stimer", "ahb_ve", "ahb_tve",
- "ahb_lcd", "ahb_csi", "ahb_de_be",
- "ahb_de_fe", "ahb_iep",
- "ahb_mali400";
- };
-
- apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
- clocks = <&apb0>;
- clock-indices = <0>, <5>,
- <6>;
- clock-output-names = "apb0_codec", "apb0_pio",
- "apb0_ir";
- };
-
- apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
- clocks = <&apb1>;
- clock-indices = <0>, <1>,
- <2>, <17>,
- <19>;
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart1",
- "apb1_uart3";
- };
-
- dram_gates: clk@01c20100 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-dram-gates-clk",
- "allwinner,sun4i-a10-gates-clk";
- reg = <0x01c20100 0x4>;
- clocks = <&pll5 0>;
- clock-indices = <0>,
- <1>,
- <25>,
- <26>,
- <29>,
- <31>;
- clock-output-names = "dram_ve",
- "dram_csi",
- "dram_de_fe",
- "dram_de_be",
- "dram_ace",
- "dram_iep";
- };
-
- de_be_clk: clk@01c20104 {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c20104 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-be";
- };
-
- de_fe_clk: clk@01c2010c {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c2010c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-fe";
- };
-
- tcon_ch0_clk: clk@01c20118 {
- #clock-cells = <0>;
- #reset-cells = <1>;
- compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
- reg = <0x01c20118 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon-ch0-sclk";
- };
-
- tcon_ch1_clk: clk@01c2012c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
- reg = <0x01c2012c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon-ch1-sclk";
- };
- };
-
display-engine {
compatible = "allwinner,sun5i-a13-display-engine";
allwinner,pipelines = <&fe0>;
};
- soc@01c00000 {
- tcon0: lcd-controller@01c0c000 {
- compatible = "allwinner,sun5i-a13-tcon";
- reg = <0x01c0c000 0x1000>;
- interrupts = <44>;
- resets = <&tcon_ch0_clk 1>;
- reset-names = "lcd";
- clocks = <&ahb_gates 36>,
- <&tcon_ch0_clk>,
- <&tcon_ch1_clk>;
- clock-names = "ahb",
- "tcon-ch0",
- "tcon-ch1";
- clock-output-names = "tcon-pixel-clock";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tcon0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tcon0_in_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_out_tcon0>;
- };
- };
-
- tcon0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
- };
- };
-
- pwm: pwm@01c20e00 {
+ soc@1c00000 {
+ pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a13-pwm";
reg = <0x01c20e00 0xc>;
- clocks = <&osc24M>;
+ clocks = <&ccu CLK_HOSC>;
#pwm-cells = <3>;
status = "disabled";
};
- fe0: display-frontend@01e00000 {
- compatible = "allwinner,sun5i-a13-display-frontend";
- reg = <0x01e00000 0x20000>;
- interrupts = <47>;
- clocks = <&ahb_gates 46>, <&de_fe_clk>,
- <&dram_gates 25>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&de_fe_clk>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fe0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- fe0_out_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_in_fe0>;
- };
- };
- };
- };
-
- be0: display-backend@01e60000 {
- compatible = "allwinner,sun5i-a13-display-backend";
- reg = <0x01e60000 0x10000>;
- clocks = <&ahb_gates 44>, <&de_be_clk>,
- <&dram_gates 26>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&de_be_clk>;
- status = "disabled";
-
- assigned-clocks = <&de_be_clk>;
- assigned-clock-rates = <300000000>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- be0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- be0_in_fe0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&fe0_out_be0>;
- };
- };
-
- be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- be0_out_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_in_be0>;
- };
- };
- };
- };
};
};
+&ccu {
+ compatible = "allwinner,sun5i-a13-ccu";
+};
+
&cpu0 {
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
432000 1200000
>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <5>;
};
&pio {
compatible = "allwinner,sun5i-a13-pinctrl";
-
- lcd_rgb666_pins: lcd_rgb666@0 {
- allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
- "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
- "PD24", "PD25", "PD26", "PD27";
- allwinner,function = "lcd0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart1_pins_a: uart1@0 {
- allwinner,pins = "PE10", "PE11";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart1_pins_b: uart1@1 {
- allwinner,pins = "PG3", "PG4";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
};
&pio {
usb0_id_pin_chip_pro: usb0-id-pin@0 {
- allwinner,pins = "PG2";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG2";
+ function = "gpio_in";
};
wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 {
- allwinner,pins = "PB10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB10";
+ function = "gpio_out";
};
};
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins>;
+ pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+ pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
status = "okay";
};
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <dt-bindings/clock/sun4i-a10-pll2.h>
+#include "sun5i.dtsi"
+
+#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/reset/sun5i-ccu.h>
/ {
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a8";
- reg = <0x0>;
- clocks = <&cpu>;
- };
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- /*
- * This is a dummy clock, to be used as placeholder on
- * other mux clocks when a specific parent clock is not
- * yet implemented. It should be dropped when the driver
- * is complete.
- */
- dummy: dummy {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- osc3M: osc3M-clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <8>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "osc3M";
- };
-
- osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
- };
-
- pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll1";
- };
-
- pll2: clk@01c20008 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-pll2-clk";
- reg = <0x01c20008 0x8>;
- clocks = <&osc24M>;
- clock-output-names = "pll2-1x", "pll2-2x",
- "pll2-4x", "pll2-8x";
- };
-
- pll3: clk@01c20010 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll3-clk";
- reg = <0x01c20010 0x4>;
- clocks = <&osc3M>;
- clock-output-names = "pll3";
- };
-
- pll3x2: pll3x2-clk {
- compatible = "allwinner,sun4i-a10-pll3-2x-clk";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <2>;
- clocks = <&pll3>;
- clock-output-names = "pll3-2x";
- };
-
- pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll4";
- };
-
- pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll5-clk";
- reg = <0x01c20020 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
- pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll6-clk";
- reg = <0x01c20028 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll6_sata", "pll6_other", "pll6";
- };
-
- pll7: clk@01c20030 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll3-clk";
- reg = <0x01c20030 0x4>;
- clocks = <&osc3M>;
- clock-output-names = "pll7";
- };
-
- pll7x2: pll7x2-clk {
- compatible = "allwinner,sun4i-a10-pll3-2x-clk";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <2>;
- clocks = <&pll7>;
- clock-output-names = "pll7-2x";
- };
-
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
- clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
- clock-output-names = "axi";
- };
-
- ahb: ahb@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun5i-a13-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>, <&cpu>, <&pll6 1>;
- clock-output-names = "ahb";
- /*
- * Use PLL6 as parent, instead of CPU/AXI
- * which has rate changes due to cpufreq
- */
- assigned-clocks = <&ahb>;
- assigned-clock-parents = <&pll6 1>;
- };
-
- apb0: apb0@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
- clock-output-names = "apb0";
- };
-
- apb1: clk@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- clock-output-names = "apb1";
- };
-
- axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-gates-clk";
- reg = <0x01c2005c 0x4>;
- clocks = <&axi>;
- clock-indices = <0>;
- clock-output-names = "axi_dram";
- };
-
- ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
- clocks = <&ahb>;
- clock-indices = <0>, <1>,
- <2>, <5>, <6>,
- <7>, <8>, <9>,
- <10>, <13>,
- <14>, <17>, <20>,
- <21>, <22>,
- <28>, <32>, <34>,
- <36>, <40>, <44>,
- <46>, <51>,
- <52>;
- clock-output-names = "ahb_usbotg", "ahb_ehci",
- "ahb_ohci", "ahb_ss", "ahb_dma",
- "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_nand",
- "ahb_sdram", "ahb_emac", "ahb_spi0",
- "ahb_spi1", "ahb_spi2",
- "ahb_hstimer", "ahb_ve", "ahb_tve",
- "ahb_lcd", "ahb_csi", "ahb_de_be",
- "ahb_de_fe", "ahb_iep",
- "ahb_mali400";
- };
-
- apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-gates-clk";
- reg = <0x01c20068 0x4>;
- clocks = <&apb0>;
- clock-indices = <0>, <3>,
- <5>, <6>;
- clock-output-names = "apb0_codec", "apb0_i2s0",
- "apb0_pio", "apb0_ir";
- };
-
- apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-gates-clk";
- reg = <0x01c2006c 0x4>;
- clocks = <&apb1>;
- clock-indices = <0>, <1>,
- <2>, <17>,
- <18>, <19>;
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart1",
- "apb1_uart2", "apb1_uart3";
- };
-
- nand_clk: clk@01c20080 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20080 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "nand";
- };
-
- ms_clk: clk@01c20084 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20084 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ms";
- };
-
- mmc0_clk: clk@01c20088 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0",
- "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk@01c2008c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc1",
- "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk@01c20090 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc2",
- "mmc2_output",
- "mmc2_sample";
- };
-
- ts_clk: clk@01c20098 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20098 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ts";
- };
-
- ss_clk: clk@01c2009c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c2009c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ss";
- };
-
- spi0_clk: clk@01c200a0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi0";
- };
-
- spi1_clk: clk@01c200a4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi1";
- };
-
- spi2_clk: clk@01c200a8 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a8 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi2";
- };
-
- ir0_clk: clk@01c200b0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200b0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir0";
- };
-
- i2s0_clk: clk@01c200b8 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod1-clk";
- reg = <0x01c200b8 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_8X>,
- <&pll2 SUN4I_A10_PLL2_4X>,
- <&pll2 SUN4I_A10_PLL2_2X>,
- <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "i2s0";
- };
-
- spdif_clk: clk@01c200c0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod1-clk";
- reg = <0x01c200c0 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_8X>,
- <&pll2 SUN4I_A10_PLL2_4X>,
- <&pll2 SUN4I_A10_PLL2_2X>,
- <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "spdif";
- };
-
- usb_clk: clk@01c200cc {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun5i-a13-usb-clk";
- reg = <0x01c200cc 0x4>;
- clocks = <&pll6 1>;
- clock-output-names = "usb_ohci0", "usb_phy";
- };
-
- dram_gates: clk@01c20100 {
- #clock-cells = <1>;
- compatible = "nextthing,gr8-dram-gates-clk",
- "allwinner,sun4i-a10-gates-clk";
- reg = <0x01c20100 0x4>;
- clocks = <&pll5 0>;
- clock-indices = <0>,
- <1>,
- <25>,
- <26>,
- <29>,
- <31>;
- clock-output-names = "dram_ve",
- "dram_csi",
- "dram_de_fe",
- "dram_de_be",
- "dram_ace",
- "dram_iep";
- };
-
- de_be_clk: clk@01c20104 {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c20104 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-be";
- };
-
- de_fe_clk: clk@01c2010c {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c2010c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-fe";
- };
-
- tcon_ch0_clk: clk@01c20118 {
- #clock-cells = <0>;
- #reset-cells = <1>;
- compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
- reg = <0x01c20118 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon-ch0-sclk";
- };
-
- tcon_ch1_clk: clk@01c2012c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
- reg = <0x01c2012c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon-ch1-sclk";
- };
-
- codec_clk: clk@01c20140 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-codec-clk";
- reg = <0x01c20140 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "codec";
- };
-
- mbus_clk: clk@01c2015c {
- #clock-cells = <0>;
- compatible = "allwinner,sun5i-a13-mbus-clk";
- reg = <0x01c2015c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mbus";
- };
- };
-
display-engine {
compatible = "allwinner,sun5i-a13-display-engine";
allwinner,pipelines = <&fe0>;
};
- soc@01c00000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sram-controller@01c00000 {
- compatible = "allwinner,sun4i-a10-sram-controller";
- reg = <0x01c00000 0x30>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- sram_a: sram@00000000 {
- compatible = "mmio-sram";
- reg = <0x00000000 0xc000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x00000000 0xc000>;
- };
-
- sram_d: sram@00010000 {
- compatible = "mmio-sram";
- reg = <0x00010000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x00010000 0x1000>;
-
- otg_sram: sram-section@0000 {
- compatible = "allwinner,sun4i-a10-sram-d";
- reg = <0x0000 0x1000>;
- status = "disabled";
- };
- };
- };
-
- dma: dma-controller@01c02000 {
- compatible = "allwinner,sun4i-a10-dma";
- reg = <0x01c02000 0x1000>;
- interrupts = <27>;
- clocks = <&ahb_gates 6>;
- #dma-cells = <2>;
- };
-
- nfc: nand@01c03000 {
- compatible = "allwinner,sun4i-a10-nand";
- reg = <0x01c03000 0x1000>;
- interrupts = <37>;
- clocks = <&ahb_gates 13>, <&nand_clk>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 3>;
- dma-names = "rxtx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi0: spi@01c05000 {
- compatible = "allwinner,sun4i-a10-spi";
- reg = <0x01c05000 0x1000>;
- interrupts = <10>;
- clocks = <&ahb_gates 20>, <&spi0_clk>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 27>,
- <&dma SUN4I_DMA_DEDICATED 26>;
- dma-names = "rx", "tx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi1: spi@01c06000 {
- compatible = "allwinner,sun4i-a10-spi";
- reg = <0x01c06000 0x1000>;
- interrupts = <11>;
- clocks = <&ahb_gates 21>, <&spi1_clk>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 9>,
- <&dma SUN4I_DMA_DEDICATED 8>;
- dma-names = "rx", "tx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- tve0: tv-encoder@01c0a000 {
- compatible = "allwinner,sun4i-a10-tv-encoder";
- reg = <0x01c0a000 0x1000>;
- clocks = <&ahb_gates 34>;
- resets = <&tcon_ch0_clk 0>;
- status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tve0_in_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_out_tve0>;
- };
- };
- };
-
- tcon0: lcd-controller@01c0c000 {
- compatible = "allwinner,sun5i-a13-tcon";
- reg = <0x01c0c000 0x1000>;
- interrupts = <44>;
- resets = <&tcon_ch0_clk 1>;
- reset-names = "lcd";
- clocks = <&ahb_gates 36>,
- <&tcon_ch0_clk>,
- <&tcon_ch1_clk>;
- clock-names = "ahb",
- "tcon-ch0",
- "tcon-ch1";
- clock-output-names = "tcon-pixel-clock";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tcon0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tcon0_in_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_out_tcon0>;
- };
- };
-
- tcon0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tcon0_out_tve0: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&tve0_in_tcon0>;
- };
- };
- };
- };
-
- mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c0f000 0x1000>;
- clocks = <&ahb_gates 8>,
- <&mmc0_clk 0>,
- <&mmc0_clk 1>,
- <&mmc0_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
- interrupts = <32>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc1: mmc@01c10000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c10000 0x1000>;
- clocks = <&ahb_gates 9>,
- <&mmc1_clk 0>,
- <&mmc1_clk 1>,
- <&mmc1_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
- interrupts = <33>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc2: mmc@01c11000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c11000 0x1000>;
- clocks = <&ahb_gates 10>,
- <&mmc2_clk 0>,
- <&mmc2_clk 1>,
- <&mmc2_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
- interrupts = <34>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usb_otg: usb@01c13000 {
- compatible = "allwinner,sun4i-a10-musb";
- reg = <0x01c13000 0x0400>;
- clocks = <&ahb_gates 0>;
- interrupts = <38>;
- interrupt-names = "mc";
- phys = <&usbphy 0>;
- phy-names = "usb";
- extcon = <&usbphy 0>;
- allwinner,sram = <&otg_sram 1>;
- status = "disabled";
-
- dr_mode = "otg";
- };
-
- usbphy: phy@01c13400 {
- #phy-cells = <1>;
- compatible = "allwinner,sun5i-a13-usb-phy";
- reg = <0x01c13400 0x10 0x01c14800 0x4>;
- reg-names = "phy_ctrl", "pmu1";
- clocks = <&usb_clk 8>;
- clock-names = "usb_phy";
- resets = <&usb_clk 0>, <&usb_clk 1>;
- reset-names = "usb0_reset", "usb1_reset";
- status = "disabled";
- };
-
- ehci0: usb@01c14000 {
- compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
- reg = <0x01c14000 0x100>;
- interrupts = <39>;
- clocks = <&ahb_gates 1>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci0: usb@01c14400 {
- compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
- reg = <0x01c14400 0x100>;
- interrupts = <40>;
- clocks = <&usb_clk 6>, <&ahb_gates 2>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- spi2: spi@01c17000 {
- compatible = "allwinner,sun4i-a10-spi";
- reg = <0x01c17000 0x1000>;
- interrupts = <12>;
- clocks = <&ahb_gates 22>, <&spi2_clk>;
- clock-names = "ahb", "mod";
- dmas = <&dma SUN4I_DMA_DEDICATED 29>,
- <&dma SUN4I_DMA_DEDICATED 28>;
- dma-names = "rx", "tx";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-a10-ic";
- reg = <0x01c20400 0x400>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- pio: pinctrl@01c20800 {
- compatible = "nextthing,gr8-pinctrl";
- reg = <0x01c20800 0x400>;
- interrupts = <28>;
- clocks = <&apb0_gates 5>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <3>;
- #gpio-cells = <3>;
-
- i2c0_pins_a: i2c0@0 {
- allwinner,pins = "PB0", "PB1";
- allwinner,function = "i2c0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- i2c1_pins_a: i2c1@0 {
- allwinner,pins = "PB15", "PB16";
- allwinner,function = "i2c1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- i2c2_pins_a: i2c2@0 {
- allwinner,pins = "PB17", "PB18";
- allwinner,function = "i2c2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- i2s0_data_pins_a: i2s0-data@0 {
- allwinner,pins = "PB6", "PB7", "PB8", "PB9";
- allwinner,function = "i2s0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- i2s0_mclk_pins_a: i2s0-mclk@0 {
- allwinner,pins = "PB5";
- allwinner,function = "i2s0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- ir0_rx_pins_a: ir0@0 {
- allwinner,pins = "PB4";
- allwinner,function = "ir0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- lcd_rgb666_pins: lcd-rgb666@0 {
- allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
- "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
- "PD24", "PD25", "PD26", "PD27";
- allwinner,function = "lcd0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0", "PF1", "PF2", "PF3",
- "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- nand_pins_a: nand-base0@0 {
- allwinner,pins = "PC0", "PC1", "PC2",
- "PC5", "PC8", "PC9", "PC10",
- "PC11", "PC12", "PC13", "PC14",
- "PC15";
- allwinner,function = "nand0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- nand_cs0_pins_a: nand-cs@0 {
- allwinner,pins = "PC4";
- allwinner,function = "nand0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- nand_rb0_pins_a: nand-rb@0 {
- allwinner,pins = "PC6";
- allwinner,function = "nand0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- pwm0_pins_a: pwm0@0 {
- allwinner,pins = "PB2";
- allwinner,function = "pwm0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- pwm1_pins: pwm1 {
- allwinner,pins = "PG13";
- allwinner,function = "pwm1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- spdif_tx_pins_a: spdif@0 {
- allwinner,pins = "PB10";
- allwinner,function = "spdif";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-
- uart1_pins_a: uart1@1 {
- allwinner,pins = "PG3", "PG4";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart1_cts_rts_pins_a: uart1-cts-rts@0 {
- allwinner,pins = "PG5", "PG6";
- allwinner,function = "uart1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart2_pins_a: uart2@1 {
- allwinner,pins = "PD2", "PD3";
- allwinner,function = "uart2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart2_cts_rts_pins_a: uart2-cts-rts@0 {
- allwinner,pins = "PD4", "PD5";
- allwinner,function = "uart2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart3_pins_a: uart3@1 {
- allwinner,pins = "PG9", "PG10";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- uart3_cts_rts_pins_a: uart3-cts-rts@0 {
- allwinner,pins = "PG11", "PG12";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
- };
-
- pwm: pwm@01c20e00 {
+ soc@1c00000 {
+ pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
- clocks = <&osc24M>;
+ clocks = <&ccu CLK_HOSC>;
#pwm-cells = <3>;
status = "disabled";
};
- timer@01c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
- reg = <0x01c20c00 0x90>;
- interrupts = <22>;
- clocks = <&osc24M>;
- };
-
- wdt: watchdog@01c20c90 {
- compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
- spdif: spdif@01c21000 {
+ spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-spdif";
reg = <0x01c21000 0x400>;
interrupts = <13>;
- clocks = <&apb0_gates 1>, <&spdif_clk>;
+ clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
clock-names = "apb", "spdif";
dmas = <&dma SUN4I_DMA_NORMAL 2>,
<&dma SUN4I_DMA_NORMAL 2>;
status = "disabled";
};
- ir0: ir@01c21800 {
- compatible = "allwinner,sun4i-a10-ir";
- clocks = <&apb0_gates 6>, <&ir0_clk>;
- clock-names = "apb", "ir";
- interrupts = <5>;
- reg = <0x01c21800 0x40>;
- status = "disabled";
- };
-
- i2s0: i2s@01c22400 {
+ i2s0: i2s@1c22400 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-i2s";
reg = <0x01c22400 0x400>;
interrupts = <16>;
- clocks = <&apb0_gates 3>, <&i2s0_clk>;
+ clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>;
clock-names = "apb", "mod";
dmas = <&dma SUN4I_DMA_NORMAL 3>,
<&dma SUN4I_DMA_NORMAL 3>;
dma-names = "rx", "tx";
status = "disabled";
};
+ };
+};
- lradc: lradc@01c22800 {
- compatible = "allwinner,sun4i-a10-lradc-keys";
- reg = <0x01c22800 0x100>;
- interrupts = <31>;
- status = "disabled";
- };
-
- codec: codec@01c22c00 {
- #sound-dai-cells = <0>;
- compatible = "allwinner,sun4i-a10-codec";
- reg = <0x01c22c00 0x40>;
- interrupts = <30>;
- clocks = <&apb0_gates 0>, <&codec_clk>;
- clock-names = "apb", "codec";
- dmas = <&dma SUN4I_DMA_NORMAL 19>,
- <&dma SUN4I_DMA_NORMAL 19>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- rtp: rtp@01c25000 {
- compatible = "allwinner,sun5i-a13-ts";
- reg = <0x01c25000 0x100>;
- interrupts = <29>;
- #thermal-sensor-cells = <0>;
- };
-
- uart1: serial@01c28400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28400 0x400>;
- interrupts = <2>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb1_gates 17>;
- status = "disabled";
- };
-
- uart2: serial@01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <3>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb1_gates 18>;
- status = "disabled";
- };
-
- uart3: serial@01c28c00 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28c00 0x400>;
- interrupts = <4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb1_gates 19>;
- status = "disabled";
- };
-
- i2c0: i2c@01c2ac00 {
- compatible = "allwinner,sun4i-a10-i2c";
- reg = <0x01c2ac00 0x400>;
- interrupts = <7>;
- clocks = <&apb1_gates 0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c@01c2b000 {
- compatible = "allwinner,sun4i-a10-i2c";
- reg = <0x01c2b000 0x400>;
- interrupts = <8>;
- clocks = <&apb1_gates 1>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c@01c2b400 {
- compatible = "allwinner,sun4i-a10-i2c";
- reg = <0x01c2b400 0x400>;
- interrupts = <9>;
- clocks = <&apb1_gates 2>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- timer@01c60000 {
- compatible = "allwinner,sun5i-a13-hstimer";
- reg = <0x01c60000 0x1000>;
- interrupts = <82>, <83>;
- clocks = <&ahb_gates 28>;
- };
-
- fe0: display-frontend@01e00000 {
- compatible = "allwinner,sun5i-a13-display-frontend";
- reg = <0x01e00000 0x20000>;
- interrupts = <47>;
- clocks = <&ahb_gates 46>, <&de_fe_clk>,
- <&dram_gates 25>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&de_fe_clk>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fe0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- fe0_out_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_in_fe0>;
- };
- };
- };
- };
-
- be0: display-backend@01e60000 {
- compatible = "allwinner,sun5i-a13-display-backend";
- reg = <0x01e60000 0x10000>;
- clocks = <&ahb_gates 44>, <&de_be_clk>,
- <&dram_gates 26>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&de_be_clk>;
- status = "disabled";
+&ccu {
+ compatible = "nextthing,gr8-ccu";
+};
- assigned-clocks = <&de_be_clk>;
- assigned-clock-rates = <300000000>;
+&pio {
+ compatible = "nextthing,gr8-pinctrl";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ i2s0_data_pins_a: i2s0-data@0 {
+ pins = "PB6", "PB7", "PB8", "PB9";
+ function = "i2s0";
+ };
- be0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
+ i2s0_mclk_pins_a: i2s0-mclk@0 {
+ pins = "PB5";
+ function = "i2s0";
+ };
- be0_in_fe0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&fe0_out_be0>;
- };
- };
+ pwm1_pins: pwm1 {
+ pins = "PG13";
+ function = "pwm1";
+ };
- be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
+ spdif_tx_pins_a: spdif@0 {
+ pins = "PB10";
+ function = "spdif";
+ bias-pull-up;
+ };
- be0_out_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_in_be0>;
- };
- };
- };
- };
+ uart1_cts_rts_pins_a: uart1-cts-rts@0 {
+ pins = "PG5", "PG6";
+ function = "uart1";
};
};
aliases {
i2c0 = &i2c0;
+ i2c1 = &i2c1;
i2c2 = &i2c2;
serial0 = &uart1;
serial1 = &uart3;
+ spi0 = &spi2;
};
chosen {
stdout-path = "serial0:115200n8";
};
- wifi_reg_on: wifi_reg_on {
- compatible = "regulator-fixed";
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "chip:white:status";
+ gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ mmc0_pwrseq: mmc0_pwrseq {
+ compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&chip_wifi_reg_on_pin>;
+ reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
+ };
- regulator-name = "wifi-reg-on";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&pio 2 19 GPIO_ACTIVE_HIGH>; /* PC19 */
- enable-active-high;
+ onewire {
+ compatible = "w1-gpio";
+ gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_w1_pin>;
};
};
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "disabled";
+};
+
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
};
&mmc0_pins_a {
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
- vmmc-supply = <&wifi_reg_on>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc0_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
&pio {
chip_vbus_pin: chip_vbus_pin@0 {
- allwinner,pins = "PB10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB10";
+ function = "gpio_out";
};
chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 {
- allwinner,pins = "PC19";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC19";
+ function = "gpio_out";
};
chip_id_det_pin: chip_id_det_pin@0 {
- allwinner,pins = "PG2";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG2";
+ function = "gpio_in";
+ };
+
+ chip_w1_pin: chip_w1_pin@0 {
+ pins = "PD2";
+ function = "gpio_in";
+ bias-pull-up;
};
};
regulator-always-on;
};
+/*
+ * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT
+ * Chip.
+ *
+ * If those are not enabled, the SDIO part will not enumerate, and
+ * since there's no way currently to pass DT infos to an SDIO device,
+ * we cannot really do better than this ugly hack for now.
+ */
®_ldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vdd-wifi1";
+ regulator-name = "vcc-wifi-1";
regulator-always-on;
};
®_ldo4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vdd-wifi2";
+ regulator-name = "vcc-wifi-2";
regulator-always-on;
};
status = "okay";
};
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "disabled";
+};
+
&tcon0 {
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_a>,
- <&uart3_pins_cts_rts_a>;
+ <&uart3_cts_rts_pins_a>;
status = "okay";
};
#include "sun5i-a13.dtsi"
-/ {
- chosen {
- framebuffer@1 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0-tve0";
- clocks = <&ahb_gates 34>, <&ahb_gates 36>,
- <&ahb_gates 44>, <&de_be_clk>,
- <&tcon_ch1_clk>, <&dram_gates 26>;
- status = "disabled";
- };
- };
-
- soc@01c00000 {
- tve0: tv-encoder@01c0a000 {
- compatible = "allwinner,sun4i-a10-tv-encoder";
- reg = <0x01c0a000 0x1000>;
- clocks = <&ahb_gates 34>;
- resets = <&tcon_ch0_clk 0>;
- status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tve0_in_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_out_tve0>;
- };
- };
- };
- };
-};
-
-&tcon0_out {
- tcon0_out_tve0: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&tve0_in_tcon0>;
- };
-};
*/
#include "sunxi-reference-design-tablet.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
/ {
};
&i2c1 {
+ /*
+ * The gsl1680 is rated at 400KHz and it will not work reliable at
+ * 100KHz, this has been confirmed on multiple different q8 tablets.
+ * All other devices on this bus are also rated for 400KHz.
+ */
+ clock-frequency = <400000>;
+
+ touchscreen: touchscreen {
+ interrupt-parent = <&pio>;
+ interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_power_pin>;
+ power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ /* Tablet dts must provide reg and compatible */
+ status = "disabled";
+ };
+
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
&lradc {
vref-supply = <®_ldo2>;
};
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
status = "okay";
};
&pio {
codec_pa_pin: codec_pa_pin@0 {
- allwinner,pins = "PG10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG10";
+ function = "gpio_out";
};
mmc0_cd_pin: mmc0_cd_pin@0 {
- allwinner,pins = "PG0";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG0";
+ function = "gpio_in";
+ bias-pull-up;
+ };
+
+ ts_power_pin: ts_power_pin {
+ pins = "PB3";
+ function = "gpio_out";
+ drive-strength = <10>;
+ bias-disable;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ pins = "PG1";
+ function = "gpio_in";
+ bias-pull-down;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PG2";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PG2";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_vbus_pin_a: usb0_vbus_pin@0 {
- allwinner,pins = "PG12";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG12";
+ function = "gpio_out";
};
};
#include "skeleton.dtsi"
-#include <dt-bindings/clock/sun4i-a10-pll2.h>
+#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/reset/sun5i-ccu.h>
/ {
interrupt-parent = <&intc>;
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0x0>;
- clocks = <&cpu>;
+ clocks = <&ccu CLK_CPU>;
};
};
- clocks {
+ chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- /*
- * This is a dummy clock, to be used as placeholder on
- * other mux clocks when a specific parent clock is not
- * yet implemented. It should be dropped when the driver
- * is complete.
- */
- dummy: dummy {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
+ status = "disabled";
};
- osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
+ framebuffer@1 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-tve0";
+ clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
+ <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
+ status = "disabled";
};
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
- osc3M: osc3M_clk {
- compatible = "fixed-factor-clock";
+ osc24M: clk@1c20050 {
#clock-cells = <0>;
- clock-div = <8>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "osc3M";
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
};
osc32k: clk@0 {
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
-
- pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll1";
- };
-
- pll2: clk@01c20008 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-pll2-clk";
- reg = <0x01c20008 0x8>;
- clocks = <&osc24M>;
- clock-output-names = "pll2-1x", "pll2-2x",
- "pll2-4x", "pll2-8x";
- };
-
- pll3: clk@01c20010 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll3-clk";
- reg = <0x01c20010 0x4>;
- clocks = <&osc3M>;
- clock-output-names = "pll3";
- };
-
- pll3x2: pll3x2_clk {
- compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <2>;
- clocks = <&pll3>;
- clock-output-names = "pll3-2x";
- };
-
- pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll4";
- };
-
- pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll5-clk";
- reg = <0x01c20020 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
- pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll6-clk";
- reg = <0x01c20028 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll6_sata", "pll6_other", "pll6";
- };
-
- pll7: clk@01c20030 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll3-clk";
- reg = <0x01c20030 0x4>;
- clocks = <&osc3M>;
- clock-output-names = "pll7";
- };
-
- pll7x2: pll7x2_clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <2>;
- clocks = <&pll7>;
- clock-output-names = "pll7-2x";
- };
-
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
- clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
- clock-output-names = "axi";
- };
-
- ahb: ahb@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun5i-a13-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>, <&cpu>, <&pll6 1>;
- clock-output-names = "ahb";
- /*
- * Use PLL6 as parent, instead of CPU/AXI
- * which has rate changes due to cpufreq
- */
- assigned-clocks = <&ahb>;
- assigned-clock-parents = <&pll6 1>;
- };
-
- apb0: apb0@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
- clock-output-names = "apb0";
- };
-
- apb1: clk@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- clock-output-names = "apb1";
- };
-
- axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
- clocks = <&axi>;
- clock-indices = <0>;
- clock-output-names = "axi_dram";
- };
-
- nand_clk: clk@01c20080 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20080 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "nand";
- };
-
- ms_clk: clk@01c20084 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20084 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ms";
- };
-
- mmc0_clk: clk@01c20088 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0",
- "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk@01c2008c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc1",
- "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk@01c20090 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc2",
- "mmc2_output",
- "mmc2_sample";
- };
-
- ts_clk: clk@01c20098 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20098 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ts";
- };
-
- ss_clk: clk@01c2009c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c2009c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ss";
- };
-
- spi0_clk: clk@01c200a0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi0";
- };
-
- spi1_clk: clk@01c200a4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi1";
- };
-
- spi2_clk: clk@01c200a8 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a8 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi2";
- };
-
- ir0_clk: clk@01c200b0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200b0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir0";
- };
-
- usb_clk: clk@01c200cc {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun5i-a13-usb-clk";
- reg = <0x01c200cc 0x4>;
- clocks = <&pll6 1>;
- clock-output-names = "usb_ohci0", "usb_phy";
- };
-
- codec_clk: clk@01c20140 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-codec-clk";
- reg = <0x01c20140 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "codec";
- };
-
- mbus_clk: clk@01c2015c {
- #clock-cells = <0>;
- compatible = "allwinner,sun5i-a13-mbus-clk";
- reg = <0x01c2015c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mbus";
- };
};
- soc@01c00000 {
+ soc@1c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sram-controller@01c00000 {
+ sram-controller@1c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sram_a: sram@00000000 {
+ sram_a: sram@0 {
compatible = "mmio-sram";
reg = <0x00000000 0xc000>;
#address-cells = <1>;
ranges = <0 0x00000000 0xc000>;
};
- sram_d: sram@00010000 {
+ emac_sram: sram-section@8000 {
+ compatible = "allwinner,sun4i-a10-sram-a3-a4";
+ reg = <0x8000 0x4000>;
+ status = "disabled";
+ };
+
+ sram_d: sram@10000 {
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00010000 0x1000>;
- otg_sram: sram-section@0000 {
+ otg_sram: sram-section@0 {
compatible = "allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
- dma: dma-controller@01c02000 {
+ dma: dma-controller@1c02000 {
compatible = "allwinner,sun4i-a10-dma";
reg = <0x01c02000 0x1000>;
interrupts = <27>;
- clocks = <&ahb_gates 6>;
+ clocks = <&ccu CLK_AHB_DMA>;
#dma-cells = <2>;
};
- spi0: spi@01c05000 {
+ nfc: nand@1c03000 {
+ compatible = "allwinner,sun4i-a10-nand";
+ reg = <0x01c03000 0x1000>;
+ interrupts = <37>;
+ clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+ dma-names = "rxtx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi0: spi@1c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
interrupts = <10>;
- clocks = <&ahb_gates 20>, <&spi0_clk>;
+ clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
<&dma SUN4I_DMA_DEDICATED 26>;
#size-cells = <0>;
};
- spi1: spi@01c06000 {
+ spi1: spi@1c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
- clocks = <&ahb_gates 21>, <&spi1_clk>;
+ clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
<&dma SUN4I_DMA_DEDICATED 8>;
#size-cells = <0>;
};
- mmc0: mmc@01c0f000 {
+ tve0: tv-encoder@1c0a000 {
+ compatible = "allwinner,sun4i-a10-tv-encoder";
+ reg = <0x01c0a000 0x1000>;
+ clocks = <&ccu CLK_AHB_TVE>;
+ resets = <&ccu RST_TVE>;
+ status = "disabled";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tve0_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_tve0>;
+ };
+ };
+ };
+
+ emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <55>;
+ clocks = <&ccu CLK_AHB_EMAC>;
+ allwinner,sram = <&emac_sram 1>;
+ status = "disabled";
+ };
+
+ mdio: mdio@1c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun5i-a13-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <44>;
+ resets = <&ccu RST_LCD>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB_LCD>,
+ <&ccu CLK_TCON_CH0>,
+ <&ccu CLK_TCON_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon-pixel-clock";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon0_out_tve0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tve0_in_tcon0>;
+ allwinner,tcon-channel = <1>;
+ };
+ };
+ };
+ };
+
+ mmc0: mmc@1c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ahb_gates 8>,
- <&mmc0_clk 0>,
- <&mmc0_clk 1>,
- <&mmc0_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
interrupts = <32>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- mmc1: mmc@01c10000 {
+ mmc1: mmc@1c10000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ahb_gates 9>,
- <&mmc1_clk 0>,
- <&mmc1_clk 1>,
- <&mmc1_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
interrupts = <33>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- mmc2: mmc@01c11000 {
+ mmc2: mmc@1c11000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ahb_gates 10>,
- <&mmc2_clk 0>,
- <&mmc2_clk 1>,
- <&mmc2_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
+ clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
interrupts = <34>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- usb_otg: usb@01c13000 {
+ usb_otg: usb@1c13000 {
compatible = "allwinner,sun4i-a10-musb";
reg = <0x01c13000 0x0400>;
- clocks = <&ahb_gates 0>;
+ clocks = <&ccu CLK_AHB_OTG>;
interrupts = <38>;
interrupt-names = "mc";
phys = <&usbphy 0>;
status = "disabled";
};
- usbphy: phy@01c13400 {
+ usbphy: phy@1c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun5i-a13-usb-phy";
reg = <0x01c13400 0x10 0x01c14800 0x4>;
reg-names = "phy_ctrl", "pmu1";
- clocks = <&usb_clk 8>;
+ clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb_phy";
- resets = <&usb_clk 0>, <&usb_clk 1>;
+ resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
reset-names = "usb0_reset", "usb1_reset";
status = "disabled";
};
- ehci0: usb@01c14000 {
+ ehci0: usb@1c14000 {
compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
reg = <0x01c14000 0x100>;
interrupts = <39>;
- clocks = <&ahb_gates 1>;
+ clocks = <&ccu CLK_AHB_EHCI>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
- ohci0: usb@01c14400 {
+ ohci0: usb@1c14400 {
compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
reg = <0x01c14400 0x100>;
interrupts = <40>;
- clocks = <&usb_clk 6>, <&ahb_gates 2>;
+ clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
- spi2: spi@01c17000 {
+ crypto: crypto-engine@1c15000 {
+ compatible = "allwinner,sun5i-a13-crypto",
+ "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <54>;
+ clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
+ clock-names = "ahb", "mod";
+ };
+
+ spi2: spi@1c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
interrupts = <12>;
- clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
<&dma SUN4I_DMA_DEDICATED 28>;
#size-cells = <0>;
};
- intc: interrupt-controller@01c20400 {
+ ccu: clock@1c20000 {
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ intc: interrupt-controller@1c20400 {
compatible = "allwinner,sun4i-a10-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
- pio: pinctrl@01c20800 {
+ pio: pinctrl@1c20800 {
reg = <0x01c20800 0x400>;
interrupts = <28>;
- clocks = <&apb0_gates 5>;
+ clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ emac_pins_a: emac0@0 {
+ pins = "PD6", "PD7", "PD10",
+ "PD11", "PD12", "PD13", "PD14",
+ "PD15", "PD18", "PD19", "PD20",
+ "PD21", "PD22", "PD23", "PD24",
+ "PD25", "PD26", "PD27";
+ function = "emac";
+ };
+
i2c0_pins_a: i2c0@0 {
- allwinner,pins = "PB0", "PB1";
- allwinner,function = "i2c0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB0", "PB1";
+ function = "i2c0";
};
i2c1_pins_a: i2c1@0 {
- allwinner,pins = "PB15", "PB16";
- allwinner,function = "i2c1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB15", "PB16";
+ function = "i2c1";
};
i2c2_pins_a: i2c2@0 {
- allwinner,pins = "PB17", "PB18";
- allwinner,function = "i2c2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB17", "PB18";
+ function = "i2c2";
+ };
+
+ ir0_rx_pins_a: ir0@0 {
+ pins = "PB4";
+ function = "ir0";
+ };
+
+ lcd_rgb565_pins: lcd_rgb565@0 {
+ pins = "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+ "PD19", "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ function = "lcd0";
+ };
+
+ lcd_rgb666_pins: lcd_rgb666@0 {
+ pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+ "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ function = "lcd0";
};
mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0", "PF1", "PF2", "PF3",
- "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
};
mmc2_pins_a: mmc2@0 {
- allwinner,pins = "PC6", "PC7", "PC8", "PC9",
- "PC10", "PC11", "PC12", "PC13",
- "PC14", "PC15";
- allwinner,function = "mmc2";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PC6", "PC7", "PC8", "PC9",
+ "PC10", "PC11", "PC12", "PC13",
+ "PC14", "PC15";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_4bit_pins_a: mmc2-4bit@0 {
+ pins = "PC6", "PC7", "PC8", "PC9",
+ "PC10", "PC11";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ nand_pins_a: nand-base0@0 {
+ pins = "PC0", "PC1", "PC2",
+ "PC5", "PC8", "PC9", "PC10",
+ "PC11", "PC12", "PC13", "PC14",
+ "PC15";
+ function = "nand0";
+ };
+
+ nand_cs0_pins_a: nand-cs@0 {
+ pins = "PC4";
+ function = "nand0";
+ };
+
+ nand_rb0_pins_a: nand-rb@0 {
+ pins = "PC6";
+ function = "nand0";
+ };
+
+ spi2_pins_a: spi2@0 {
+ pins = "PE1", "PE2", "PE3";
+ function = "spi2";
+ };
+
+ spi2_cs0_pins_a: spi2-cs0@0 {
+ pins = "PE0";
+ function = "spi2";
+ };
+
+ uart1_pins_a: uart1@0 {
+ pins = "PE10", "PE11";
+ function = "uart1";
+ };
+
+ uart1_pins_b: uart1@1 {
+ pins = "PG3", "PG4";
+ function = "uart1";
+ };
+
+ uart2_pins_a: uart2@0 {
+ pins = "PD2", "PD3";
+ function = "uart2";
+ };
+
+ uart2_cts_rts_pins_a: uart2-cts-rts@0 {
+ pins = "PD4", "PD5";
+ function = "uart2";
};
uart3_pins_a: uart3@0 {
- allwinner,pins = "PG9", "PG10";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG9", "PG10";
+ function = "uart3";
};
- uart3_pins_cts_rts_a: uart3-cts-rts@0 {
- allwinner,pins = "PG11", "PG12";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart3_cts_rts_pins_a: uart3-cts-rts@0 {
+ pins = "PG11", "PG12";
+ function = "uart3";
};
pwm0_pins: pwm0 {
- allwinner,pins = "PB2";
- allwinner,function = "pwm";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB2";
+ function = "pwm";
};
};
- timer@01c20c00 {
+ timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
- clocks = <&osc24M>;
+ clocks = <&ccu CLK_HOSC>;
};
- wdt: watchdog@01c20c90 {
+ wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
};
- lradc: lradc@01c22800 {
+ ir0: ir@1c21800 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ interrupts = <5>;
+ reg = <0x01c21800 0x40>;
+ status = "disabled";
+ };
+
+ lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <31>;
status = "disabled";
};
- codec: codec@01c22c00 {
+ codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-codec";
reg = <0x01c22c00 0x40>;
interrupts = <30>;
- clocks = <&apb0_gates 0>, <&codec_clk>;
+ clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
clock-names = "apb", "codec";
dmas = <&dma SUN4I_DMA_NORMAL 19>,
<&dma SUN4I_DMA_NORMAL 19>;
status = "disabled";
};
- sid: eeprom@01c23800 {
+ sid: eeprom@1c23800 {
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>;
};
- rtp: rtp@01c25000 {
+ rtp: rtp@1c25000 {
compatible = "allwinner,sun5i-a13-ts";
reg = <0x01c25000 0x100>;
interrupts = <29>;
#thermal-sensor-cells = <0>;
};
- uart1: serial@01c28400 {
+ uart0: serial@1c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_APB1_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 17>;
+ clocks = <&ccu CLK_APB1_UART1>;
status = "disabled";
};
- uart3: serial@01c28c00 {
+ uart2: serial@1c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_APB1_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <4>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 19>;
+ clocks = <&ccu CLK_APB1_UART3>;
status = "disabled";
};
- i2c0: i2c@01c2ac00 {
+ i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <7>;
- clocks = <&apb1_gates 0>;
+ clocks = <&ccu CLK_APB1_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c1: i2c@01c2b000 {
+ i2c1: i2c@1c2b000 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <8>;
- clocks = <&apb1_gates 1>;
+ clocks = <&ccu CLK_APB1_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c2: i2c@01c2b400 {
+ i2c2: i2c@1c2b400 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <9>;
- clocks = <&apb1_gates 2>;
+ clocks = <&ccu CLK_APB1_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- timer@01c60000 {
+ timer@1c60000 {
compatible = "allwinner,sun5i-a13-hstimer";
reg = <0x01c60000 0x1000>;
interrupts = <82>, <83>;
- clocks = <&ahb_gates 28>;
+ clocks = <&ccu CLK_AHB_HSTIMER>;
+ };
+
+ fe0: display-frontend@1e00000 {
+ compatible = "allwinner,sun5i-a13-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <47>;
+ clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
+ <&ccu CLK_DRAM_DE_FE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_FE>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@1e60000 {
+ compatible = "allwinner,sun5i-a13-display-backend";
+ reg = <0x01e60000 0x10000>;
+ interrupts = <47>;
+ clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_DRAM_DE_BE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_BE>;
+ status = "disabled";
+
+ assigned-clocks = <&ccu CLK_DE_BE>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be0>;
+ };
+ };
+ };
};
};
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Allwinner A31 APP4 EVB1 Evaluation Board";
&pio {
usb1_vbus_pin_a: usb1_vbus_pin@0 {
- allwinner,pins = "PH27";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH27";
+ function = "gpio_out";
};
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "WITS A31 Colombus Evaluation Board";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
&mmc0_pins_a {
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&pio {
mmc0_cd_pin_colombus: mmc0_cd_pin@0 {
- allwinner,pins = "PA8";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA8";
+ function = "gpio_in";
+ bias-pull-up;
};
usb2_vbus_pin_colombus: usb2_vbus_pin@0 {
- allwinner,pins = "PH24";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH24";
+ function = "gpio_out";
};
i2c_lcd_pins: i2c_lcd_pin@0 {
- allwinner,pins = "PA23", "PA24";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA23", "PA24";
+ function = "gpio_out";
+ bias-pull-up;
};
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Merrii A31 Hummingbird";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ vga-connector {
+ compatible = "vga-connector";
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_dac_out>;
+ };
+ };
+ };
+
+ vga-dac {
+ compatible = "dumb-vga-dac";
+ vdd-supply = <®_vga_3v3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ vga_dac_in: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_vga>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ vga_dac_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ reg_vga_3v3: vga_3v3_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vga-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */
};
};
+&codec {
+ allwinner,audio-routing =
+ "Headphone", "HP",
+ "Speaker", "LINEOUT",
+ "LINEIN", "Line In",
+ "MIC1", "Mic",
+ "MIC2", "Headset Mic",
+ "Mic", "MBIAS",
+ "Headset Mic", "HBIAS";
+ allwinner,pa-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <®_dcdc3>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
&mmc0_pins_a {
/* external pull-ups missing for some pins */
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&mmc1 {
&pio {
gmac_phy_reset_pin_hummingbird: gmac_phy_reset_pin@0 {
- allwinner,pins = "PA21";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PA21";
+ function = "gpio_out";
};
mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
- allwinner,pins = "PA8";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA8";
+ function = "gpio_in";
+ bias-pull-up;
};
wifi_reset_pin_hummingbird: wifi_reset_pin@0 {
- allwinner,pins = "PG10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG10";
+ function = "gpio_out";
};
};
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ x-powers,drive-vbus-en;
};
};
#include "axp22x.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
®_aldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-dram";
};
+®_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
®_usb1_vbus {
gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
status = "okay";
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd0_rgb888_pins>;
+};
+
+&tcon0_out {
+ tcon0_out_vga: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vga_dac_in>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
-&usb1_vbus_pin_a {
- /* different pin from sunxi-common-regulators */
- allwinner,pins = "PH24";
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
};
&usbphy {
+ usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+ usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_drivevbus>;
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Mele I7 Quad top set box";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
};
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Headphone", "HP";
+ status = "okay";
+};
+
+&de {
+ status = "okay";
};
&ehci0 {
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
- cd-inverted;
+ cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
status = "okay";
};
&pio {
led_pins_i7: led_pins@0 {
- allwinner,pins = "PH13";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH13";
+ function = "gpio_out";
};
mmc0_cd_pin_i7: mmc0_cd_pin@0 {
- allwinner,pins = "PH22";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH22";
+ function = "gpio_in";
+ bias-pull-up;
};
usb1_vbus_pin_i7: usb1_vbus_pin@0 {
- allwinner,pins = "PC27";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC27";
+ function = "gpio_out";
};
};
status = "okay";
};
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_pins_a>;
+ spdif-out = "okay";
+ status = "okay";
+};
+
+&tcon0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Mele M9 top set box";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
- cd-inverted;
+ cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
status = "okay";
};
&pio {
led_pins_m9: led_pins@0 {
- allwinner,pins = "PH13";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH13";
+ function = "gpio_out";
};
mmc0_cd_pin_m9: mmc0_cd_pin@0 {
- allwinner,pins = "PH22";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH22";
+ function = "gpio_in";
+ bias-pull-up;
};
usb1_vbus_pin_m9: usb1_vbus_pin@0 {
- allwinner,pins = "PC27";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC27";
+ function = "gpio_out";
};
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Mele A1000G Quad top set box";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
- cd-inverted;
+ cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
status = "okay";
};
&pio {
led_pins_m9: led_pins@0 {
- allwinner,pins = "PH13";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH13";
+ function = "gpio_out";
};
mmc0_cd_pin_m9: mmc0_cd_pin@0 {
- allwinner,pins = "PH22";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH22";
+ function = "gpio_in";
+ bias-pull-up;
};
usb1_vbus_pin_m9: usb1_vbus_pin@0 {
- allwinner,pins = "PC27";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC27";
+ function = "gpio_out";
};
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/clock/sun6i-a31-ccu.h>
+#include <dt-bindings/reset/sun6i-a31-ccu.h>
/ {
interrupt-parent = <&gic>;
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
- clocks = <&pll6 0>;
+ clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
+ <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
+ <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
+ <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
status = "disabled";
};
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
- clocks = <&pll6 0>;
+ clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
+ <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
+ <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
status = "disabled";
};
};
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
- clocks = <&cpu>;
+ clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
480000 1000000
>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <3>;
};
cpu@1 {
clock-output-names = "osc32k";
};
- pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun6i-a31-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll1";
- };
-
- pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-pll6-clk";
- reg = <0x01c20028 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll6", "pll6x2";
- };
-
- cpu: cpu@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-cpu-clk";
- reg = <0x01c20050 0x4>;
-
- /*
- * PLL1 is listed twice here.
- * While it looks suspicious, it's actually documented
- * that way both in the datasheet and in the code from
- * Allwinner.
- */
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
- clock-output-names = "cpu";
- };
-
- axi: axi@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-axi-clk";
- reg = <0x01c20050 0x4>;
- clocks = <&cpu>;
- clock-output-names = "axi";
- };
-
- ahb1: ahb1@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun6i-a31-ahb1-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
- clock-output-names = "ahb1";
-
- /*
- * Clock AHB1 from PLL6, instead of CPU/AXI which
- * has rate changes due to cpufreq. Also the DMA
- * controller requires AHB1 clocked from PLL6.
- */
- assigned-clocks = <&ahb1>;
- assigned-clock-parents = <&pll6 0>;
- };
-
- ahb1_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
- reg = <0x01c20060 0x8>;
- clocks = <&ahb1>;
- clock-indices = <1>, <5>,
- <6>, <8>, <9>,
- <10>, <11>, <12>,
- <13>, <14>,
- <17>, <18>, <19>,
- <20>, <21>, <22>,
- <23>, <24>, <26>,
- <27>, <29>,
- <30>, <31>, <32>,
- <36>, <37>, <40>,
- <43>, <44>, <45>,
- <46>, <47>, <50>,
- <52>, <55>, <56>,
- <57>, <58>;
- clock-output-names = "ahb1_mipidsi", "ahb1_ss",
- "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
- "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
- "ahb1_nand0", "ahb1_sdram",
- "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
- "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
- "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
- "ahb1_ehci1", "ahb1_ohci0",
- "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
- "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
- "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
- "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
- "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
- "ahb1_drc0", "ahb1_drc1";
- };
-
- apb1: apb1@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb1>;
- clock-output-names = "apb1";
- };
-
- apb1_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-apb1-gates-clk";
- reg = <0x01c20068 0x4>;
- clocks = <&apb1>;
- clock-indices = <0>, <4>,
- <5>, <12>,
- <13>;
- clock-output-names = "apb1_codec", "apb1_digital_mic",
- "apb1_pio", "apb1_daudio0",
- "apb1_daudio1";
- };
-
- apb2: clk@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
- clock-output-names = "apb2";
- };
-
- apb2_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-apb2-gates-clk";
- reg = <0x01c2006c 0x4>;
- clocks = <&apb2>;
- clock-indices = <0>, <1>,
- <2>, <3>, <16>,
- <17>, <18>, <19>,
- <20>, <21>;
- clock-output-names = "apb2_i2c0", "apb2_i2c1",
- "apb2_i2c2", "apb2_i2c3",
- "apb2_uart0", "apb2_uart1",
- "apb2_uart2", "apb2_uart3",
- "apb2_uart4", "apb2_uart5";
- };
-
- mmc0_clk: clk@01c20088 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "mmc0",
- "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk@01c2008c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "mmc1",
- "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk@01c20090 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "mmc2",
- "mmc2_output",
- "mmc2_sample";
- };
-
- mmc3_clk: clk@01c20094 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20094 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "mmc3",
- "mmc3_output",
- "mmc3_sample";
- };
-
- ss_clk: clk@01c2009c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c2009c 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "ss";
- };
-
- spi0_clk: clk@01c200a0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a0 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "spi0";
- };
-
- spi1_clk: clk@01c200a4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a4 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "spi1";
- };
-
- spi2_clk: clk@01c200a8 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a8 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "spi2";
- };
-
- spi3_clk: clk@01c200ac {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200ac 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "spi3";
- };
-
- usb_clk: clk@01c200cc {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-usb-clk";
- reg = <0x01c200cc 0x4>;
- clocks = <&osc24M>;
- clock-indices = <8>, <9>, <10>,
- <16>, <17>,
- <18>;
- clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
- "usb_ohci0", "usb_ohci1",
- "usb_ohci2";
- };
-
/*
* The following two are dummy clocks, placeholders
* used in the gmac_tx clock. The gmac driver will
clock-output-names = "gmac_int_tx";
};
- gmac_tx_clk: clk@01c200d0 {
+ gmac_tx_clk: clk@1c200d0 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-gmac-clk";
reg = <0x01c200d0 0x4>;
};
};
- soc@01c00000 {
+ de: display-engine {
+ compatible = "allwinner,sun6i-a31-display-engine";
+ allwinner,pipelines = <&fe0>, <&fe1>;
+ status = "disabled";
+ };
+
+ soc@1c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- dma: dma-controller@01c02000 {
+ dma: dma-controller@1c02000 {
compatible = "allwinner,sun6i-a31-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 6>;
- resets = <&ahb1_rst 6>;
+ clocks = <&ccu CLK_AHB1_DMA>;
+ resets = <&ccu RST_AHB1_DMA>;
#dma-cells = <1>;
};
- mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun6i-a31-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_AHB1_LCD0>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB1_LCD0>,
+ <&ccu CLK_LCD0_CH0>,
+ <&ccu CLK_LCD0_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon0-pixel-clock";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_out_tcon0>;
+ };
+
+ tcon0_in_drc1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&drc1_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon0_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon0>;
+ allwinner,tcon-channel = <1>;
+ };
+ };
+ };
+ };
+
+ tcon1: lcd-controller@1c0d000 {
+ compatible = "allwinner,sun6i-a31-tcon";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_AHB1_LCD1>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB1_LCD1>,
+ <&ccu CLK_LCD1_CH0>,
+ <&ccu CLK_LCD1_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon1-pixel-clock";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_out_tcon1>;
+ };
+
+ tcon1_in_drc1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&drc1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon1_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon1>;
+ allwinner,tcon-channel = <1>;
+ };
+ };
+ };
+ };
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ahb1_gates 8>,
- <&mmc0_clk 0>,
- <&mmc0_clk 1>,
- <&mmc0_clk 2>;
+ clocks = <&ccu CLK_AHB1_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ahb1_rst 8>;
+ resets = <&ccu RST_AHB1_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#size-cells = <0>;
};
- mmc1: mmc@01c10000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ahb1_gates 9>,
- <&mmc1_clk 0>,
- <&mmc1_clk 1>,
- <&mmc1_clk 2>;
+ clocks = <&ccu CLK_AHB1_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ahb1_rst 9>;
+ resets = <&ccu RST_AHB1_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#size-cells = <0>;
};
- mmc2: mmc@01c11000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc2: mmc@1c11000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ahb1_gates 10>,
- <&mmc2_clk 0>,
- <&mmc2_clk 1>,
- <&mmc2_clk 2>;
+ clocks = <&ccu CLK_AHB1_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ahb1_rst 10>;
+ resets = <&ccu RST_AHB1_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#size-cells = <0>;
};
- mmc3: mmc@01c12000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc3: mmc@1c12000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c12000 0x1000>;
- clocks = <&ahb1_gates 11>,
- <&mmc3_clk 0>,
- <&mmc3_clk 1>,
- <&mmc3_clk 2>;
+ clocks = <&ccu CLK_AHB1_MMC3>,
+ <&ccu CLK_MMC3>,
+ <&ccu CLK_MMC3_OUTPUT>,
+ <&ccu CLK_MMC3_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
- resets = <&ahb1_rst 11>;
+ resets = <&ccu RST_AHB1_MMC3>;
reset-names = "ahb";
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#size-cells = <0>;
};
- usb_otg: usb@01c19000 {
+ hdmi: hdmi@1c16000 {
+ compatible = "allwinner,sun6i-a31-hdmi";
+ reg = <0x01c16000 0x1000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
+ <&ccu CLK_HDMI_DDC>,
+ <&ccu CLK_PLL_VIDEO0_2X>,
+ <&ccu CLK_PLL_VIDEO1_2X>;
+ clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
+ resets = <&ccu RST_AHB1_HDMI>;
+ reset-names = "ahb";
+ dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+ dmas = <&dma 13>, <&dma 13>, <&dma 14>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_hdmi>;
+ };
+
+ hdmi_in_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+ usb_otg: usb@1c19000 {
compatible = "allwinner,sun6i-a31-musb";
reg = <0x01c19000 0x0400>;
- clocks = <&ahb1_gates 24>;
- resets = <&ahb1_rst 24>;
+ clocks = <&ccu CLK_AHB1_OTG>;
+ resets = <&ccu RST_AHB1_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
status = "disabled";
};
- usbphy: phy@01c19400 {
+ usbphy: phy@1c19400 {
compatible = "allwinner,sun6i-a31-usb-phy";
reg = <0x01c19400 0x10>,
<0x01c1a800 0x4>,
reg-names = "phy_ctrl",
"pmu1",
"pmu2";
- clocks = <&usb_clk 8>,
- <&usb_clk 9>,
- <&usb_clk 10>;
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_PHY2>;
clock-names = "usb0_phy",
"usb1_phy",
"usb2_phy";
- resets = <&usb_clk 0>,
- <&usb_clk 1>,
- <&usb_clk 2>;
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>;
reset-names = "usb0_reset",
"usb1_reset",
"usb2_reset";
#phy-cells = <1>;
};
- ehci0: usb@01c1a000 {
+ ehci0: usb@1c1a000 {
compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 26>;
- resets = <&ahb1_rst 26>;
+ clocks = <&ccu CLK_AHB1_EHCI0>;
+ resets = <&ccu RST_AHB1_EHCI0>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
- ohci0: usb@01c1a400 {
+ ohci0: usb@1c1a400 {
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 29>, <&usb_clk 16>;
- resets = <&ahb1_rst 29>;
+ clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_AHB1_OHCI0>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
- ehci1: usb@01c1b000 {
+ ehci1: usb@1c1b000 {
compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 27>;
- resets = <&ahb1_rst 27>;
+ clocks = <&ccu CLK_AHB1_EHCI1>;
+ resets = <&ccu RST_AHB1_EHCI1>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
- ohci1: usb@01c1b400 {
+ ohci1: usb@1c1b400 {
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
reg = <0x01c1b400 0x100>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 30>, <&usb_clk 17>;
- resets = <&ahb1_rst 30>;
+ clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_AHB1_OHCI1>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
- ohci2: usb@01c1c400 {
+ ohci2: usb@1c1c400 {
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
reg = <0x01c1c400 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 31>, <&usb_clk 18>;
- resets = <&ahb1_rst 31>;
+ clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_AHB1_OHCI2>;
status = "disabled";
};
- pio: pinctrl@01c20800 {
+ ccu: clock@1c20000 {
+ compatible = "allwinner,sun6i-a31-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pio: pinctrl@1c20800 {
compatible = "allwinner,sun6i-a31-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 5>;
+ clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
- uart0_pins_a: uart0@0 {
- allwinner,pins = "PH20", "PH21";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ gmac_pins_gmii_a: gmac_gmii@0 {
+ pins = "PA0", "PA1", "PA2", "PA3",
+ "PA4", "PA5", "PA6", "PA7",
+ "PA8", "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA15",
+ "PA16", "PA17", "PA18", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA25", "PA26", "PA27";
+ function = "gmac";
+ /*
+ * data lines in GMII mode run at 125MHz and
+ * might need a higher signal drive strength
+ */
+ drive-strength = <30>;
+ };
+
+ gmac_pins_mii_a: gmac_mii@0 {
+ pins = "PA0", "PA1", "PA2", "PA3",
+ "PA8", "PA9", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA26", "PA27";
+ function = "gmac";
+ };
+
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ pins = "PA0", "PA1", "PA2", "PA3",
+ "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA25", "PA26", "PA27";
+ function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ drive-strength = <40>;
};
i2c0_pins_a: i2c0@0 {
- allwinner,pins = "PH14", "PH15";
- allwinner,function = "i2c0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH14", "PH15";
+ function = "i2c0";
};
i2c1_pins_a: i2c1@0 {
- allwinner,pins = "PH16", "PH17";
- allwinner,function = "i2c1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH16", "PH17";
+ function = "i2c1";
};
i2c2_pins_a: i2c2@0 {
- allwinner,pins = "PH18", "PH19";
- allwinner,function = "i2c2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH18", "PH19";
+ function = "i2c2";
+ };
+
+ lcd0_rgb888_pins: lcd0_rgb888 {
+ pins = "PD0", "PD1", "PD2", "PD3",
+ "PD4", "PD5", "PD6", "PD7",
+ "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD14", "PD15",
+ "PD16", "PD17", "PD18", "PD19",
+ "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ function = "lcd0";
};
mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0", "PF1", "PF2",
+ pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
};
mmc1_pins_a: mmc1@0 {
- allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+ pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
- allwinner,function = "mmc1";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
};
mmc2_pins_a: mmc2@0 {
- allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+ pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11";
- allwinner,function = "mmc2";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
};
mmc2_8bit_emmc_pins: mmc2@1 {
- allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+ pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12",
"PC13", "PC14", "PC15",
"PC24";
- allwinner,function = "mmc2";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
};
mmc3_8bit_emmc_pins: mmc3@1 {
- allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+ pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12",
"PC13", "PC14", "PC15",
"PC24";
- allwinner,function = "mmc3";
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ function = "mmc3";
+ drive-strength = <40>;
+ bias-pull-up;
};
- gmac_pins_mii_a: gmac_mii@0 {
- allwinner,pins = "PA0", "PA1", "PA2", "PA3",
- "PA8", "PA9", "PA11",
- "PA12", "PA13", "PA14", "PA19",
- "PA20", "PA21", "PA22", "PA23",
- "PA24", "PA26", "PA27";
- allwinner,function = "gmac";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- gmac_pins_gmii_a: gmac_gmii@0 {
- allwinner,pins = "PA0", "PA1", "PA2", "PA3",
- "PA4", "PA5", "PA6", "PA7",
- "PA8", "PA9", "PA10", "PA11",
- "PA12", "PA13", "PA14", "PA15",
- "PA16", "PA17", "PA18", "PA19",
- "PA20", "PA21", "PA22", "PA23",
- "PA24", "PA25", "PA26", "PA27";
- allwinner,function = "gmac";
- /*
- * data lines in GMII mode run at 125MHz and
- * might need a higher signal drive strength
- */
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ spdif_pins_a: spdif@0 {
+ pins = "PH28";
+ function = "spdif";
};
- gmac_pins_rgmii_a: gmac_rgmii@0 {
- allwinner,pins = "PA0", "PA1", "PA2", "PA3",
- "PA9", "PA10", "PA11",
- "PA12", "PA13", "PA14", "PA19",
- "PA20", "PA25", "PA26", "PA27";
- allwinner,function = "gmac";
- /*
- * data lines in RGMII mode use DDR mode
- * and need a higher signal drive strength
- */
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ uart0_pins_a: uart0@0 {
+ pins = "PH20", "PH21";
+ function = "uart0";
};
};
- ahb1_rst: reset@01c202c0 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-ahb1-reset";
- reg = <0x01c202c0 0xc>;
- };
-
- apb1_rst: reset@01c202d0 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x01c202d0 0x4>;
- };
-
- apb2_rst: reset@01c202d8 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x01c202d8 0x4>;
- };
-
- timer@01c20c00 {
+ timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
clocks = <&osc24M>;
};
- wdt1: watchdog@01c20ca0 {
+ wdt1: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
};
- lradc: lradc@01c22800 {
+ spdif: spdif@1c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun6i-a31-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
+ resets = <&ccu RST_APB1_SPDIF>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma 2>, <&dma 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s0: i2s@1c22000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun6i-a31-i2s";
+ reg = <0x01c22000 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
+ resets = <&ccu RST_APB1_DAUDIO0>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 3>, <&dma 3>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2s1: i2s@1c22400 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun6i-a31-i2s";
+ reg = <0x01c22400 0x400>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
+ resets = <&ccu RST_APB1_DAUDIO1>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 4>, <&dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- rtp: rtp@01c25000 {
+ rtp: rtp@1c25000 {
compatible = "allwinner,sun6i-a31-ts";
reg = <0x01c25000 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
};
- uart0: serial@01c28000 {
+ uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb2_gates 16>;
- resets = <&apb2_rst 16>;
+ clocks = <&ccu CLK_APB2_UART0>;
+ resets = <&ccu RST_APB2_UART0>;
dmas = <&dma 6>, <&dma 6>;
dma-names = "rx", "tx";
status = "disabled";
};
- uart1: serial@01c28400 {
+ uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb2_gates 17>;
- resets = <&apb2_rst 17>;
+ clocks = <&ccu CLK_APB2_UART1>;
+ resets = <&ccu RST_APB2_UART1>;
dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx";
status = "disabled";
};
- uart2: serial@01c28800 {
+ uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb2_gates 18>;
- resets = <&apb2_rst 18>;
+ clocks = <&ccu CLK_APB2_UART2>;
+ resets = <&ccu RST_APB2_UART2>;
dmas = <&dma 8>, <&dma 8>;
dma-names = "rx", "tx";
status = "disabled";
};
- uart3: serial@01c28c00 {
+ uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb2_gates 19>;
- resets = <&apb2_rst 19>;
+ clocks = <&ccu CLK_APB2_UART3>;
+ resets = <&ccu RST_APB2_UART3>;
dmas = <&dma 9>, <&dma 9>;
dma-names = "rx", "tx";
status = "disabled";
};
- uart4: serial@01c29000 {
+ uart4: serial@1c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb2_gates 20>;
- resets = <&apb2_rst 20>;
+ clocks = <&ccu CLK_APB2_UART4>;
+ resets = <&ccu RST_APB2_UART4>;
dmas = <&dma 10>, <&dma 10>;
dma-names = "rx", "tx";
status = "disabled";
};
- uart5: serial@01c29400 {
+ uart5: serial@1c29400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29400 0x400>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb2_gates 21>;
- resets = <&apb2_rst 21>;
+ clocks = <&ccu CLK_APB2_UART5>;
+ resets = <&ccu RST_APB2_UART5>;
dmas = <&dma 22>, <&dma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
- i2c0: i2c@01c2ac00 {
+ i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb2_gates 0>;
- resets = <&apb2_rst 0>;
+ clocks = <&ccu CLK_APB2_I2C0>;
+ resets = <&ccu RST_APB2_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c1: i2c@01c2b000 {
+ i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb2_gates 1>;
- resets = <&apb2_rst 1>;
+ clocks = <&ccu CLK_APB2_I2C1>;
+ resets = <&ccu RST_APB2_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c2: i2c@01c2b400 {
+ i2c2: i2c@1c2b400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb2_gates 2>;
- resets = <&apb2_rst 2>;
+ clocks = <&ccu CLK_APB2_I2C2>;
+ resets = <&ccu RST_APB2_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c3: i2c@01c2b800 {
+ i2c3: i2c@1c2b800 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b800 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb2_gates 3>;
- resets = <&apb2_rst 3>;
+ clocks = <&ccu CLK_APB2_I2C3>;
+ resets = <&ccu RST_APB2_I2C3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- gmac: ethernet@01c30000 {
+ gmac: ethernet@1c30000 {
compatible = "allwinner,sun7i-a20-gmac";
reg = <0x01c30000 0x1054>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
- clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+ clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
clock-names = "stmmaceth", "allwinner_gmac_tx";
- resets = <&ahb1_rst 17>;
+ resets = <&ccu RST_AHB1_EMAC>;
reset-names = "stmmaceth";
snps,pbl = <2>;
snps,fixed-burst;
#size-cells = <0>;
};
- crypto: crypto-engine@01c15000 {
- compatible = "allwinner,sun4i-a10-crypto";
+ crypto: crypto-engine@1c15000 {
+ compatible = "allwinner,sun6i-a31-crypto",
+ "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 5>, <&ss_clk>;
+ clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
clock-names = "ahb", "mod";
- resets = <&ahb1_rst 5>;
+ resets = <&ccu RST_AHB1_SS>;
reset-names = "ahb";
};
- timer@01c60000 {
+ codec: codec@1c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun6i-a31-codec";
+ reg = <0x01c22c00 0x400>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
+ clock-names = "apb", "codec";
+ resets = <&ccu RST_APB1_CODEC>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ timer@1c60000 {
compatible = "allwinner,sun6i-a31-hstimer",
"allwinner,sun7i-a20-hstimer";
reg = <0x01c60000 0x1000>;
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 19>;
- resets = <&ahb1_rst 19>;
+ clocks = <&ccu CLK_AHB1_HSTIMER>;
+ resets = <&ccu RST_AHB1_HSTIMER>;
};
- spi0: spi@01c68000 {
+ spi0: spi@1c68000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c68000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 20>, <&spi0_clk>;
+ clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
- resets = <&ahb1_rst 20>;
+ resets = <&ccu RST_AHB1_SPI0>;
status = "disabled";
};
- spi1: spi@01c69000 {
+ spi1: spi@1c69000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c69000 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 21>, <&spi1_clk>;
+ clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
dmas = <&dma 24>, <&dma 24>;
dma-names = "rx", "tx";
- resets = <&ahb1_rst 21>;
+ resets = <&ccu RST_AHB1_SPI1>;
status = "disabled";
};
- spi2: spi@01c6a000 {
+ spi2: spi@1c6a000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c6a000 0x1000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 22>, <&spi2_clk>;
+ clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
clock-names = "ahb", "mod";
dmas = <&dma 25>, <&dma 25>;
dma-names = "rx", "tx";
- resets = <&ahb1_rst 22>;
+ resets = <&ccu RST_AHB1_SPI2>;
status = "disabled";
};
- spi3: spi@01c6b000 {
+ spi3: spi@1c6b000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c6b000 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb1_gates 23>, <&spi3_clk>;
+ clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
clock-names = "ahb", "mod";
dmas = <&dma 26>, <&dma 26>;
dma-names = "rx", "tx";
- resets = <&ahb1_rst 23>;
+ resets = <&ccu RST_AHB1_SPI3>;
status = "disabled";
};
- gic: interrupt-controller@01c81000 {
+ gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- rtc: rtc@01f00000 {
+ fe0: display-frontend@1e00000 {
+ compatible = "allwinner,sun6i-a31-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
+ <&ccu CLK_DRAM_FE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_FE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+
+ fe0_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_fe0>;
+ };
+ };
+ };
+ };
+
+ fe1: display-frontend@1e20000 {
+ compatible = "allwinner,sun6i-a31-display-frontend";
+ reg = <0x01e20000 0x20000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
+ <&ccu CLK_DRAM_FE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_FE1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe1_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe1>;
+ };
+
+ fe1_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_fe1>;
+ };
+ };
+ };
+ };
+
+ be1: display-backend@1e40000 {
+ compatible = "allwinner,sun6i-a31-display-backend";
+ reg = <0x01e40000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
+ <&ccu CLK_DRAM_BE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_BE1>;
+
+ assigned-clocks = <&ccu CLK_BE1>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be1_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be1>;
+ };
+
+ be1_in_fe1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&fe1_out_be1>;
+ };
+ };
+
+ be1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be1_out_drc1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&drc1_in_be1>;
+ };
+ };
+ };
+ };
+
+ drc1: drc@1e50000 {
+ compatible = "allwinner,sun6i-a31-drc";
+ reg = <0x01e50000 0x10000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
+ <&ccu CLK_DRAM_DRC1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_DRC1>;
+
+ assigned-clocks = <&ccu CLK_IEP_DRC1>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ drc1_in_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_out_drc1>;
+ };
+ };
+
+ drc1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ drc1_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_drc1>;
+ };
+
+ drc1_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_drc1>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@1e60000 {
+ compatible = "allwinner,sun6i-a31-display-backend";
+ reg = <0x01e60000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
+ <&ccu CLK_DRAM_BE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_BE0>;
+
+ assigned-clocks = <&ccu CLK_BE0>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+
+ be0_in_fe1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&fe1_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_drc0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&drc0_in_be0>;
+ };
+ };
+ };
+ };
+
+ drc0: drc@1e70000 {
+ compatible = "allwinner,sun6i-a31-drc";
+ reg = <0x01e70000 0x10000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
+ <&ccu CLK_DRAM_DRC0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_AHB1_DRC0>;
+
+ assigned-clocks = <&ccu CLK_IEP_DRC0>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ drc0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_drc0>;
+ };
+ };
+
+ drc0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ drc0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_drc0>;
+ };
+
+ drc0_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_drc0>;
+ };
+ };
+ };
+ };
+
+ rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
- nmi_intc: interrupt-controller@01f00c0c {
- compatible = "allwinner,sun6i-a31-sc-nmi";
+ nmi_intc: interrupt-controller@1f00c00 {
+ compatible = "allwinner,sun6i-a31-r-intc";
interrupt-controller;
#interrupt-cells = <2>;
- reg = <0x01f00c0c 0x38>;
+ reg = <0x01f00c00 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
- prcm@01f01400 {
+ prcm@1f01400 {
compatible = "allwinner,sun6i-a31-prcm";
reg = <0x01f01400 0x200>;
ar100: ar100_clk {
compatible = "allwinner,sun6i-a31-ar100-clk";
#clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
- <&pll6 0>;
+ clocks = <&osc32k>, <&osc24M>,
+ <&ccu CLK_PLL_PERIPH>,
+ <&ccu CLK_PLL_PERIPH>;
clock-output-names = "ar100";
};
};
};
- cpucfg@01f01c00 {
+ cpucfg@1f01c00 {
compatible = "allwinner,sun6i-a31-cpuconfig";
reg = <0x01f01c00 0x300>;
};
- ir: ir@01f02000 {
+ ir: ir@1f02000 {
compatible = "allwinner,sun5i-a13-ir";
clocks = <&apb0_gates 1>, <&ir_clk>;
clock-names = "apb", "ir";
status = "disabled";
};
- r_pio: pinctrl@01f02c00 {
+ r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun6i-a31-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>;
+ clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#gpio-cells = <3>;
ir_pins_a: ir@0 {
- allwinner,pins = "PL4";
- allwinner,function = "s_ir";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PL4";
+ function = "s_ir";
};
p2wi_pins: p2wi {
- allwinner,pins = "PL0", "PL1";
- allwinner,function = "s_p2wi";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PL0", "PL1";
+ function = "s_p2wi";
};
};
- p2wi: i2c@01f03400 {
+ p2wi: i2c@1f03400 {
compatible = "allwinner,sun6i-a31-p2wi";
reg = <0x01f03400 0x400>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
/dts-v1/;
#include "sun6i-a31s.dtsi"
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
/ {
model = "CSQ CS908 top set box";
compatible = "csq,cs908", "allwinner,sun6i-a31s";
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "MSI Primo81 tablet";
compatible = "msi,primo81", "allwinner,sun6i-a31s";
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "c";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
};
&cpu0 {
cpu-supply = <®_dcdc3>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
/* rtl8188etv wifi is connected here */
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
/* pull-ups and device VDDIO use AXP221 DLDO3 */
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
&pio {
gt911_int_primo81: gt911_int_pin@0 {
- allwinner,pins = "PA3";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PA3";
+ function = "gpio_in";
};
mma8452_int_primo81: mma8452_int_pin@0 {
- allwinner,pins = "PA9";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA9";
+ function = "gpio_in";
+ bias-pull-up;
};
mmc0_cd_pin_primo81: mmc0_cd_pin@0 {
- allwinner,pins = "PA8";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA8";
+ function = "gpio_in";
+ bias-pull-up;
};
};
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ x-powers,drive-vbus-en;
};
};
#include "axp22x.dtsi"
+&battery_power_supply {
+ status = "okay";
+};
+
®_aldo3 {
regulator-always-on;
regulator-min-microvolt = <2700000>;
regulator-name = "vddio-csi";
};
+®_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
®_eldo3 {
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
};
&usb_otg {
- /* otg support requires support for AXP221 usb-power-supply and GPIO */
- dr_mode = "host";
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
status = "okay";
};
&usbphy {
+ usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_drivevbus>;
usb1_vbus-supply = <®_dldo1>;
status = "okay";
};
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Sinlinx SinA31s Core Board";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
};
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&de {
+ status = "okay";
};
&ehci0 {
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
- cd-inverted;
+ cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
status = "okay";
};
&pio {
led_pin_sina31s: led_pin@0 {
- allwinner,pins = "PH13";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH13";
+ function = "gpio_out";
};
mmc0_cd_pin_sina31s: mmc0_cd_pin@0 {
- allwinner,pins = "PA4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
regulator-name = "vcc-gmac-phy";
};
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
&usbphy {
status = "okay";
};
/dts-v1/;
#include "sun6i-a31s.dtsi"
-#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
};
};
+&cpu0 {
+ cpu-supply = <®_dcdc3>;
+};
+
&ehci0 {
status = "okay";
};
pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>;
phy = <&phy1>;
phy-mode = "rgmii";
+ phy-supply = <®_dldo1>;
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>;
- vmmc-supply = <®_vcc3v0>;
+ vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
- cd-inverted;
+ cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
status = "okay";
};
&mmc0_pins_a {
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_a>;
- vmmc-supply = <®_vcc3v0>;
+ vmmc-supply = <®_aldo1>;
mmc-pwrseq = <&mmc2_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&r_pio>;
};
&mmc2_pins_a {
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&ohci0 {
status = "okay";
};
+&p2wi {
+ status = "okay";
+
+ axp22x: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <®_dcdc1>;
+ x-powers,drive-vbus-en;
+ };
+};
+
&pio {
gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 {
- allwinner,pins = "PA21";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PA21";
+ function = "gpio_out";
};
led_pins_bpi_m2: led_pins@0 {
- allwinner,pins = "PG5", "PG10", "PG11";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG5", "PG10", "PG11";
+ function = "gpio_out";
};
mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 {
- allwinner,pins = "PA4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
&r_pio {
mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin@0 {
- allwinner,pins = "PL8";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PL8";
+ function = "gpio_out";
};
};
+#include "axp22x.dtsi"
+
+®_aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-gmac";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_dc5ldo {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vdd-3v0";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-sys-dll";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-mac";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "avdd-csi";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pb";
+};
+
+®_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vdd-csi";
+ status = "okay";
+};
+
+®_ldo_io1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pm-cpus";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Yones TopTech BS1078 v2 Tablet";
&pio {
mmc0_cd_pin_bs1078v2: mmc0_cd_pin@0 {
- allwinner,pins = "PA8";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA8";
+ function = "gpio_in";
+ bias-pull-up;
};
};
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
&mmc0_pins_a {
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&p2wi {
#include "sun6i-a31.dtsi"
+&de {
+ compatible = "allwinner,sun6i-a31s-display-engine";
+};
+
&pio {
compatible = "allwinner,sun6i-a31s-pinctrl";
};
+
+&tcon0 {
+ compatible = "allwinner,sun6i-a31s-tcon";
+};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
aliases {
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
- cd-inverted;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
&pio {
mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 {
- allwinner,pins = "PA8";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA8";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PA15";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PA15";
+ function = "gpio_in";
+ bias-pull-up;
};
};
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
cpu-supply = <®_dcdc2>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
&ir0 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_rx_pins_a>;
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "LeMaker Banana Pi";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
};
&pio {
+ gpio-line-names =
+ /* PA */
+ "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3",
+ "ETXD2", "ETXD1", "ETXD0",
+ "ERXCK", "ERXERR", "ERXDV", "EMDC", "EMDIO",
+ "ETXEN", "ETXCK", "ECRS",
+ "ECOL", "ETXERR", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PB */
+ "PMU-SCK", "PMU-SDA", "", "", "", "", "", "",
+ "", "USB0-DRV", "", "", "", "", "", "",
+ "", "", "", "", "SCL", "SDA", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PC */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PD */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PE */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PF */
+ "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3",
+ "SD0-D2", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PG */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ /* PH */
+ "TXD0", "RXD0", "IO-1", "PH3", "USB0-IDDET", "PH5", "", "",
+ "", "", "SD0-DET", "", "", "", "", "",
+ "", "", "", "", "IO-4", "IO-5", "", "EMAC-PWR-EN",
+ "LED1", "", "", "", "", "", "", "",
+ /* PI */
+ "", "", "", "IO-GCLK", "", "", "", "",
+ "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
+ "SPI-MISO", "SPI-CE1", "",
+ "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
- allwinner,pins = "PH10";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH10";
+ function = "gpio_in";
+ bias-pull-up;
};
gmac_power_pin_bananapi: gmac_power_pin@0 {
- allwinner,pins = "PH23";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH23";
+ function = "gpio_out";
};
led_pins_bananapi: led_pins@0 {
- allwinner,pins = "PH24";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH24";
+ function = "gpio_out";
};
};
};
};
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vmmc3_pin_bananapro>;
+ reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>;
+ };
+
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
enable-active-high;
gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>;
};
-
- reg_vmmc3: vmmc3 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&vmmc3_pin_bananapro>;
- regulator-name = "vmmc3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>;
- };
};
&ahci {
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
&mmc3 {
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins_a>;
- vmmc-supply = <®_vmmc3>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
};
&ohci0 {
&pio {
gmac_power_pin_bananapro: gmac_power_pin@0 {
- allwinner,pins = "PH23";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH23";
+ function = "gpio_out";
};
led_pins_bananapro: led_pins@0 {
- allwinner,pins = "PH24", "PG2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH24", "PG2";
+ function = "gpio_out";
};
mmc0_cd_pin_bananapro: mmc0_cd_pin@0 {
- allwinner,pins = "PH10";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH10";
+ function = "gpio_in";
+ bias-pull-up;
};
usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
- allwinner,pins = "PH0";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH0";
+ function = "gpio_out";
};
usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
- allwinner,pins = "PH1";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH1";
+ function = "gpio_out";
};
vmmc3_pin_bananapro: vmmc3_pin@0 {
- allwinner,pins = "PH22";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH22";
+ function = "gpio_out";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Cubietech Cubieboard2";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
cpu-supply = <®_dcdc2>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&pio {
led_pins_cubieboard2: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH20", "PH21";
+ function = "gpio_out";
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
status = "okay";
};
-&usb_otg {
- dr_mode = "otg";
+#include "axp209.dtsi"
+
+&ac_power_supply {
status = "okay";
};
-#include "axp209.dtsi"
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Cubietech Cubietruck";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
cpu-supply = <®_dcdc2>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
&mmc3_pins_a {
/* AP6210 requires pull-up */
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&ohci0 {
&pio {
ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
- allwinner,pins = "PH12";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH12";
+ function = "gpio_out";
};
led_pins_cubietruck: led_pins@0 {
- allwinner,pins = "PH7", "PH11", "PH20", "PH21";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH7", "PH11", "PH20", "PH21";
+ function = "gpio_out";
};
mmc3_pwrseq_pin_cubietruck: mmc3_pwrseq_pin@0 {
- allwinner,pins = "PH9";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH9";
+ function = "gpio_out";
};
usb0_vbus_pin_a: usb0_vbus_pin@0 {
- allwinner,pins = "PH17";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH17";
+ function = "gpio_out";
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH19";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH19";
+ function = "gpio_in";
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH22";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH22";
+ function = "gpio_in";
};
};
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
status = "okay";
};
+&usb_power_supply {
+ status = "okay";
+};
+
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Merrii A20 Hummingbird";
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&pio {
ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 {
- allwinner,pins = "PH15";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH15";
+ function = "gpio_out";
};
usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH2";
+ function = "gpio_out";
};
mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 {
- allwinner,pins = "PH9";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH9";
+ function = "gpio_out";
};
gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 {
- allwinner,pins = "PH16";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH16";
+ function = "gpio_out";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "I12 / Q5 / QT840A A20 tvbox";
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
&mmc3_pins_a {
/* AP6210 / AP6330 requires pull-up */
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&ohci0 {
&pio {
vmmc3_pin_i12_tvbox: vmmc3_pin@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH2";
+ function = "gpio_out";
};
vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 {
- allwinner,pins = "PH12";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH12";
+ function = "gpio_out";
};
gmac_power_pin_i12_tvbox: gmac_power_pin@0 {
- allwinner,pins = "PH21";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH21";
+ function = "gpio_out";
};
led_pins_i12_tvbox: led_pins@0 {
- allwinner,pins = "PH9", "PH20";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH9", "PH20";
+ function = "gpio_out";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "ICnova-A20 SWAC";
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */
- cd-inverted;
+ cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&pio {
led_pins_itead_core: led_pins@0 {
- allwinner,pins = "PH20","PH21";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH20","PH21";
+ function = "gpio_out";
+ drive-strength = <20>;
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Lamobo R1";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
};
};
-&ahci_pwr_pin_a {
- allwinner,pins = "PB3";
-};
-
&ahci {
target-supply = <®_ahci_5v>;
status = "okay";
cpu-supply = <®_dcdc2>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
reg = <8>;
label = "cpu";
ethernet = <&gmac>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-txid";
fixed-link {
speed = <1000>;
full-duplex;
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 {
- allwinner,pins = "PH10";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH10";
+ function = "gpio_in";
+ bias-pull-up;
};
gmac_power_pin_lamobo_r1: gmac_power_pin@0 {
- allwinner,pins = "PH23";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH23";
+ function = "gpio_out";
};
led_pins_lamobo_r1: led_pins@0 {
- allwinner,pins = "PH24";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH24";
+ function = "gpio_out";
};
};
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
®_ahci_5v {
gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
status = "okay";
status = "okay";
};
-&usb2_vbus_pin_a {
- allwinner,pins = "PH12";
-};
-
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Mele M3";
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&pio {
led_pins_m3: led_pins@0 {
- allwinner,pins = "PH20";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH20";
+ function = "gpio_out";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "mk808c";
chosen {
stdout-path = "serial0:115200n8";
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
};
&codec {
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH4";
+ function = "gpio_in";
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH5";
+ function = "gpio_in";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Olimex A20-Olimex-SOM-EVB";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
status = "okay";
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&codec {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
&lradc {
vref-supply = <®_vcc3v0>;
status = "okay";
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */
- cd-inverted;
+ cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */
status = "okay";
};
&pio {
ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin@1 {
- allwinner,pins = "PC3";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC3";
+ function = "gpio_out";
};
led_pins_olimex_som_evb: led_pins@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH2";
+ function = "gpio_out";
+ drive-strength = <20>;
};
mmc3_cd_pin_olimex_som_evb: mmc3_cd_pin@0 {
- allwinner,pins = "PH0";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH0";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH4";
+ function = "gpio_in";
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH5";
+ function = "gpio_in";
};
};
status = "okay";
};
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>,
+ <&spi1_cs0_pins_a>;
+ status = "okay";
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>,
+ <&spi2_cs0_pins_a>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pins_a>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
+
&usb_otg {
dr_mode = "otg";
status = "okay";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
status = "okay";
};
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins_a>;
+ status = "okay";
+};
+
&codec {
status = "okay";
};
cpu-supply = <®_dcdc2>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
®_ahci_5v {
gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
status = "okay";
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Olimex A20-OLinuXino-LIME";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&pio {
ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
- allwinner,pins = "PC3";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC3";
+ function = "gpio_out";
};
led_pins_olinuxinolime: led_pins@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH2";
+ function = "gpio_out";
+ drive-strength = <20>;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
&pio {
mmc2_pins_nrst: mmc2-rst-pin {
- allwinner,pins = "PC16";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC16";
+ function = "gpio_out";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Olimex A20-OLinuXino-LIME2";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- acin-supply = <®_axp_ipsout>;
- vin2-supply = <®_axp_ipsout>;
- vin3-supply = <®_axp_ipsout>;
- ldo24in-supply = <®_axp_ipsout>;
- ldo3in-supply = <®_axp_ipsout>;
-
- regulators {
- vdd_rtc: ldo1 {
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- };
-
- avcc: ldo2 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vcc_csi0: ldo3 {
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <3500000>;
- regulator-always-on;
- };
-
- vcc_csi1: ldo4 {
- regulator-min-microvolt = <1250000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vdd_cpu: dcdc2 {
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <2275000>;
- regulator-always-on;
- };
-
- vdd_int: dcdc3 {
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <3500000>;
- regulator-always-on;
- };
- };
};
};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&pio {
ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
- allwinner,pins = "PC3";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC3";
+ function = "gpio_out";
};
led_pins_olinuxinolime: led_pins@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH2";
+ function = "gpio_out";
+ drive-strength = <20>;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
usb0_vbus_pin_lime2: usb0_vbus_pin@0 {
- allwinner,pins = "PC17";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC17";
+ function = "gpio_out";
};
};
status = "okay";
};
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vddio-csi0";
+};
+
+®_ldo4 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vddio-csi1";
+};
+
®_usb0_vbus {
pinctrl-0 = <&usb0_vbus_pin_lime2>;
gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Olimex A20-Olinuxino Micro";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
status = "okay";
};
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
+ pinctrl-0 = <&gmac_pins_mii_a>, <&gmac_txerr>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
- cd-inverted;
+ cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
status = "okay";
};
};
&pio {
+ gmac_txerr: gmac_txerr@0 {
+ pins = "PA17";
+ function = "gmac";
+ };
+
mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
- allwinner,pins = "PH11";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH11";
+ function = "gpio_in";
+ bias-pull-up;
};
led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH2";
+ function = "gpio_out";
+ drive-strength = <20>;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PH5";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ pins = "PH5";
+ function = "gpio_in";
+ bias-pull-down;
};
};
+#include "axp209.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
®_ahci_5v {
status = "okay";
};
status = "okay";
};
+&usb_power_supply {
+ status = "okay";
+};
+
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Orange Pi Mini";
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
status = "okay";
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
- cd-inverted;
+ cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
- allwinner,pins = "PH10";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH10";
+ function = "gpio_in";
+ bias-pull-up;
};
mmc3_cd_pin_orangepi: mmc3_cd_pin@0 {
- allwinner,pins = "PH11";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH11";
+ function = "gpio_in";
+ bias-pull-up;
};
usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
- allwinner,pins = "PH22";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH22";
+ function = "gpio_out";
};
gmac_power_pin_orangepi: gmac_power_pin@0 {
- allwinner,pins = "PH23";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH23";
+ function = "gpio_out";
};
led_pins_orangepi: led_pins@0 {
- allwinner,pins = "PH24", "PH25";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH24", "PH25";
+ function = "gpio_out";
};
usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
- allwinner,pins = "PH26";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH26";
+ function = "gpio_out";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Orange Pi";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
- cd-inverted;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
- allwinner,pins = "PH10";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH10";
+ function = "gpio_in";
+ bias-pull-up;
};
usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
- allwinner,pins = "PH22";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH22";
+ function = "gpio_out";
};
gmac_power_pin_orangepi: gmac_power_pin@0 {
- allwinner,pins = "PH23";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH23";
+ function = "gpio_out";
};
led_pins_orangepi: led_pins@0 {
- allwinner,pins = "PH24";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH24";
+ function = "gpio_out";
};
usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
- allwinner,pins = "PH26";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH26";
+ function = "gpio_out";
};
};
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
cpu-supply = <®_dcdc2>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&pio {
ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH2";
+ function = "gpio_out";
};
led_pins_pcduino3_nano: led_pins@0 {
- allwinner,pins = "PH16", "PH15";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH16", "PH15";
+ function = "gpio_out";
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 {
- allwinner,pins = "PD2";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PD2";
+ function = "gpio_out";
};
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "LinkSprite pcDuino3";
status = "okay";
};
-&ahci_pwr_pin_a {
- allwinner,pins = "PH2";
-};
-
&codec {
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
&pio {
led_pins_pcduino3: led_pins@0 {
- allwinner,pins = "PH15", "PH16";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH15", "PH16";
+ function = "gpio_out";
};
key_pins_pcduino3: key_pins@0 {
- allwinner,pins = "PH17", "PH18", "PH19";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH17", "PH18", "PH19";
+ function = "gpio_in";
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
chosen {
stdout-path = "serial0:115200n8";
};
+};
- soc@01c00000 {
- mmc0: mmc@01c0f000 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 7 1 0>; /* PH1 */
- cd-inverted;
- status = "okay";
- };
-
- usbphy: phy@01c13400 {
- usb2_vbus-supply = <®_usb2_vbus>;
- status = "okay";
- };
+&ehci1 {
+ status = "okay";
+};
- ehci1: usb@01c1c000 {
- /* rtl8188etv wifi is connected here */
- status = "okay";
- };
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
+ status = "okay";
+};
- pinctrl@01c20800 {
- usb2_vbus_pin_a: usb2_vbus_pin@0 {
- allwinner,pins = "PH12";
- };
- };
+®_usb2_vbus {
+ gpio = <&pio 7 12 0>; /* PH12 */
+ status = "okay";
+};
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
- };
- };
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
- reg_usb2_vbus: usb2-vbus {
- gpio = <&pio 7 12 0>; /* PH12 */
- status = "okay";
- };
+&usbphy {
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&pio {
bl_enable_pin: bl_enable_pin@0 {
- allwinner,pins = "PH7";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH7";
+ function = "gpio_out";
};
codec_pa_pin: codec_pa_pin@0 {
- allwinner,pins = "PH15";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH15";
+ function = "gpio_out";
};
ts_reset_pin: ts_reset_pin@0 {
- allwinner,pins = "PB13";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB13";
+ function = "gpio_out";
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
- cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- cd-inverted;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
non-removable;
status = "okay";
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
&pio {
vmmc3_pin_ap6xxx_wl_regon: vmmc3_pin@0 {
- allwinner,pins = "PH9";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH9";
+ function = "gpio_out";
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
-
-#include <dt-bindings/clock/sun4i-a10-pll2.h>
#include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/clock/sun7i-a20-ccu.h>
+#include <dt-bindings/reset/sun4i-a10-ccu.h>
/ {
interrupt-parent = <&gic>;
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
- clocks = <&ahb_gates 36>, <&ahb_gates 43>,
- <&ahb_gates 44>, <&de_be0_clk>,
- <&tcon0_ch1_clk>, <&dram_gates 26>;
+ clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
+ <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
+ <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
+ <&ccu CLK_HDMI>;
status = "disabled";
};
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
- clocks = <&ahb_gates 36>, <&ahb_gates 44>,
- <&de_be0_clk>, <&tcon0_ch0_clk>,
- <&dram_gates 26>;
+ clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
+ <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
+ <&ccu CLK_DRAM_DE_BE0>;
status = "disabled";
};
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
- clocks = <&ahb_gates 34>, <&ahb_gates 36>,
- <&ahb_gates 44>,
- <&de_be0_clk>, <&tcon0_ch1_clk>,
- <&dram_gates 5>, <&dram_gates 26>;
+ clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
+ <&ccu CLK_AHB_DE_BE0>,
+ <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
+ <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
status = "disabled";
};
};
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
- clocks = <&cpu>;
+ clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
144000 1000000
>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <6>;
};
cpu@1 {
#size-cells = <1>;
ranges;
- osc24M: clk@01c20050 {
+ osc24M: clk@1c20050 {
#clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-osc-clk";
- reg = <0x01c20050 0x4>;
+ compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
- osc3M: osc3M_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <8>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "osc3M";
- };
-
osc32k: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-output-names = "osc32k";
};
- pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll1";
- };
-
- pll2: clk@01c20008 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll2-clk";
- reg = <0x01c20008 0x8>;
- clocks = <&osc24M>;
- clock-output-names = "pll2-1x", "pll2-2x",
- "pll2-4x", "pll2-8x";
- };
-
- pll3: clk@01c20010 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll3-clk";
- reg = <0x01c20010 0x4>;
- clocks = <&osc3M>;
- clock-output-names = "pll3";
- };
-
- pll3x2: pll3x2_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&pll3>;
- clock-div = <1>;
- clock-mult = <2>;
- clock-output-names = "pll3-2x";
- };
-
- pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun7i-a20-pll4-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll4";
- };
-
- pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll5-clk";
- reg = <0x01c20020 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
- pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-pll6-clk";
- reg = <0x01c20028 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll6_sata", "pll6_other", "pll6",
- "pll6_div_4";
- };
-
- pll7: clk@01c20030 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-pll3-clk";
- reg = <0x01c20030 0x4>;
- clocks = <&osc3M>;
- clock-output-names = "pll7";
- };
-
- pll7x2: pll7x2_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&pll7>;
- clock-div = <1>;
- clock-mult = <2>;
- clock-output-names = "pll7-2x";
- };
-
- pll8: clk@01c20040 {
- #clock-cells = <0>;
- compatible = "allwinner,sun7i-a20-pll4-clk";
- reg = <0x01c20040 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll8";
- };
-
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
- clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
- clock-output-names = "axi";
- };
-
- ahb: ahb@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun5i-a13-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>, <&pll6 3>, <&pll6 1>;
- clock-output-names = "ahb";
- /*
- * Use PLL6 as parent, instead of CPU/AXI
- * which has rate changes due to cpufreq
- */
- assigned-clocks = <&ahb>;
- assigned-clock-parents = <&pll6 3>;
- };
-
- ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun7i-a20-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
- clocks = <&ahb>;
- clock-indices = <0>, <1>,
- <2>, <3>, <4>,
- <5>, <6>, <7>, <8>,
- <9>, <10>, <11>, <12>,
- <13>, <14>, <16>,
- <17>, <18>, <20>, <21>,
- <22>, <23>, <25>,
- <28>, <32>, <33>, <34>,
- <35>, <36>, <37>, <40>,
- <41>, <42>, <43>,
- <44>, <45>, <46>,
- <47>, <49>, <50>,
- <52>;
- clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
- "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
- "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
- "ahb_nand", "ahb_sdram", "ahb_ace",
- "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
- "ahb_spi2", "ahb_spi3", "ahb_sata",
- "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
- "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
- "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_gmac", "ahb_mp",
- "ahb_mali";
- };
-
- apb0: apb0@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
- clock-output-names = "apb0";
- };
-
- apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun7i-a20-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
- clocks = <&apb0>;
- clock-indices = <0>, <1>,
- <2>, <3>, <4>,
- <5>, <6>, <7>,
- <8>, <10>;
- clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
- "apb0_pio", "apb0_ir0", "apb0_ir1",
- "apb0_i2s2", "apb0_keypad";
- };
-
- apb1: clk@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- clock-output-names = "apb1";
- };
-
- apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun7i-a20-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
- clocks = <&apb1>;
- clock-indices = <0>, <1>,
- <2>, <3>, <4>,
- <5>, <6>, <7>,
- <15>, <16>, <17>,
- <18>, <19>, <20>,
- <21>, <22>, <23>;
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_i2c3", "apb1_can",
- "apb1_scr", "apb1_ps20", "apb1_ps21",
- "apb1_i2c4", "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3", "apb1_uart4",
- "apb1_uart5", "apb1_uart6", "apb1_uart7";
- };
-
- nand_clk: clk@01c20080 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20080 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "nand";
- };
-
- ms_clk: clk@01c20084 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20084 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ms";
- };
-
- mmc0_clk: clk@01c20088 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0",
- "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk@01c2008c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc1",
- "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk@01c20090 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc2",
- "mmc2_output",
- "mmc2_sample";
- };
-
- mmc3_clk: clk@01c20094 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20094 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc3",
- "mmc3_output",
- "mmc3_sample";
- };
-
- ts_clk: clk@01c20098 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20098 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ts";
- };
-
- ss_clk: clk@01c2009c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c2009c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ss";
- };
-
- spi0_clk: clk@01c200a0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi0";
- };
-
- spi1_clk: clk@01c200a4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi1";
- };
-
- spi2_clk: clk@01c200a8 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200a8 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi2";
- };
-
- pata_clk: clk@01c200ac {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200ac 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "pata";
- };
-
- ir0_clk: clk@01c200b0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200b0 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir0";
- };
-
- ir1_clk: clk@01c200b4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200b4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir1";
- };
-
- i2s0_clk: clk@01c200b8 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod1-clk";
- reg = <0x01c200b8 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_8X>,
- <&pll2 SUN4I_A10_PLL2_4X>,
- <&pll2 SUN4I_A10_PLL2_2X>,
- <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "i2s0";
- };
-
- ac97_clk: clk@01c200bc {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod1-clk";
- reg = <0x01c200bc 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_8X>,
- <&pll2 SUN4I_A10_PLL2_4X>,
- <&pll2 SUN4I_A10_PLL2_2X>,
- <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "ac97";
- };
-
- spdif_clk: clk@01c200c0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod1-clk";
- reg = <0x01c200c0 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_8X>,
- <&pll2 SUN4I_A10_PLL2_4X>,
- <&pll2 SUN4I_A10_PLL2_2X>,
- <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "spdif";
- };
-
- keypad_clk: clk@01c200c4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200c4 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "keypad";
- };
-
- usb_clk: clk@01c200cc {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun4i-a10-usb-clk";
- reg = <0x01c200cc 0x4>;
- clocks = <&pll6 1>;
- clock-output-names = "usb_ohci0", "usb_ohci1",
- "usb_phy";
- };
-
- spi3_clk: clk@01c200d4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c200d4 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi3";
- };
-
- i2s1_clk: clk@01c200d8 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod1-clk";
- reg = <0x01c200d8 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_8X>,
- <&pll2 SUN4I_A10_PLL2_4X>,
- <&pll2 SUN4I_A10_PLL2_2X>,
- <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "i2s1";
- };
-
- i2s2_clk: clk@01c200dc {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod1-clk";
- reg = <0x01c200dc 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_8X>,
- <&pll2 SUN4I_A10_PLL2_4X>,
- <&pll2 SUN4I_A10_PLL2_2X>,
- <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "i2s2";
- };
-
- dram_gates: clk@01c20100 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-dram-gates-clk";
- reg = <0x01c20100 0x4>;
- clocks = <&pll5 0>;
- clock-indices = <0>,
- <1>, <2>,
- <3>,
- <4>,
- <5>, <6>,
- <15>,
- <24>, <25>,
- <26>, <27>,
- <28>, <29>;
- clock-output-names = "dram_ve",
- "dram_csi0", "dram_csi1",
- "dram_ts",
- "dram_tvd",
- "dram_tve0", "dram_tve1",
- "dram_output",
- "dram_de_fe1", "dram_de_fe0",
- "dram_de_be0", "dram_de_be1",
- "dram_de_mp", "dram_ace";
- };
-
- de_be0_clk: clk@01c20104 {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c20104 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-be0";
- };
-
- de_be1_clk: clk@01c20108 {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c20108 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-be1";
- };
-
- de_fe0_clk: clk@01c2010c {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c2010c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-fe0";
- };
-
- de_fe1_clk: clk@01c20110 {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-display-clk";
- reg = <0x01c20110 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll5 1>;
- clock-output-names = "de-fe1";
- };
-
- tcon0_ch0_clk: clk@01c20118 {
- #clock-cells = <0>;
- #reset-cells = <1>;
- compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
- reg = <0x01c20118 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon0-ch0-sclk";
-
- };
-
- tcon1_ch0_clk: clk@01c2011c {
- #clock-cells = <0>;
- #reset-cells = <1>;
- compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
- reg = <0x01c2011c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon1-ch0-sclk";
-
- };
-
- tcon0_ch1_clk: clk@01c2012c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
- reg = <0x01c2012c 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon0-ch1-sclk";
-
- };
-
- tcon1_ch1_clk: clk@01c20130 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
- reg = <0x01c20130 0x4>;
- clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
- clock-output-names = "tcon1-ch1-sclk";
-
- };
-
- ve_clk: clk@01c2013c {
- #clock-cells = <0>;
- #reset-cells = <0>;
- compatible = "allwinner,sun4i-a10-ve-clk";
- reg = <0x01c2013c 0x4>;
- clocks = <&pll4>;
- clock-output-names = "ve";
- };
-
- codec_clk: clk@01c20140 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-codec-clk";
- reg = <0x01c20140 0x4>;
- clocks = <&pll2 SUN4I_A10_PLL2_1X>;
- clock-output-names = "codec";
- };
-
- mbus_clk: clk@01c2015c {
- #clock-cells = <0>;
- compatible = "allwinner,sun5i-a13-mbus-clk";
- reg = <0x01c2015c 0x4>;
- clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
- clock-output-names = "mbus";
- };
-
/*
* The following two are dummy clocks, placeholders
* used in the gmac_tx clock. The gmac driver will
* The actual TX clock rate is not controlled by the
* gmac_tx clock.
*/
- mii_phy_tx_clk: clk@2 {
+ mii_phy_tx_clk: clk@1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "mii_phy_tx";
};
- gmac_int_tx_clk: clk@3 {
+ gmac_int_tx_clk: clk@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_int_tx";
};
- gmac_tx_clk: clk@01c20164 {
+ gmac_tx_clk: clk@1c20164 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-gmac-clk";
reg = <0x01c20164 0x4>;
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
clock-output-names = "gmac_tx";
};
+ };
- /*
- * Dummy clock used by output clocks
- */
- osc24M_32k: clk@1 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <750>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "osc24M_32k";
- };
-
- clk_out_a: clk@01c201f0 {
- #clock-cells = <0>;
- compatible = "allwinner,sun7i-a20-out-clk";
- reg = <0x01c201f0 0x4>;
- clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
- clock-output-names = "clk_out_a";
- };
- clk_out_b: clk@01c201f4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun7i-a20-out-clk";
- reg = <0x01c201f4 0x4>;
- clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
- clock-output-names = "clk_out_b";
- };
+ de: display-engine {
+ compatible = "allwinner,sun7i-a20-display-engine";
+ allwinner,pipelines = <&fe0>, <&fe1>;
+ status = "disabled";
};
- soc@01c00000 {
+ soc@1c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sram-controller@01c00000 {
+ sram-controller@1c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sram_a: sram@00000000 {
+ sram_a: sram@0 {
compatible = "mmio-sram";
reg = <0x00000000 0xc000>;
#address-cells = <1>;
};
};
- sram_d: sram@00010000 {
+ sram_d: sram@10000 {
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00010000 0x1000>;
- otg_sram: sram-section@0000 {
+ otg_sram: sram-section@0 {
compatible = "allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
- nmi_intc: interrupt-controller@01c00030 {
+ nmi_intc: interrupt-controller@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
- dma: dma-controller@01c02000 {
+ dma: dma-controller@1c02000 {
compatible = "allwinner,sun4i-a10-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 6>;
+ clocks = <&ccu CLK_AHB_DMA>;
#dma-cells = <2>;
};
- nfc: nand@01c03000 {
+ nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 13>, <&nand_clk>;
+ clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 3>;
dma-names = "rxtx";
#size-cells = <0>;
};
- spi0: spi@01c05000 {
+ spi0: spi@1c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 20>, <&spi0_clk>;
+ clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
<&dma SUN4I_DMA_DEDICATED 26>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ num-cs = <4>;
};
- spi1: spi@01c06000 {
+ spi1: spi@1c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 21>, <&spi1_clk>;
+ clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
<&dma SUN4I_DMA_DEDICATED 8>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ num-cs = <1>;
};
- emac: ethernet@01c0b000 {
+ emac: ethernet@1c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 17>;
+ clocks = <&ccu CLK_AHB_EMAC>;
allwinner,sram = <&emac_sram 1>;
status = "disabled";
};
- mdio: mdio@01c0b080 {
+ mdio: mdio@1c0b080 {
compatible = "allwinner,sun4i-a10-mdio";
reg = <0x01c0b080 0x14>;
status = "disabled";
#size-cells = <0>;
};
- mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun7i-a20-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_TCON0>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB_LCD0>,
+ <&ccu CLK_TCON0_CH0>,
+ <&ccu CLK_TCON0_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon0-pixel-clock";
+ dmas = <&dma SUN4I_DMA_DEDICATED 14>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon0>;
+ };
+
+ tcon0_in_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon0_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon0>;
+ allwinner,tcon-channel = <1>;
+ };
+ };
+ };
+ };
+
+ tcon1: lcd-controller@1c0d000 {
+ compatible = "allwinner,sun7i-a20-tcon";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_TCON1>;
+ reset-names = "lcd";
+ clocks = <&ccu CLK_AHB_LCD1>,
+ <&ccu CLK_TCON1_CH0>,
+ <&ccu CLK_TCON1_CH1>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon1-pixel-clock";
+ dmas = <&dma SUN4I_DMA_DEDICATED 15>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon1>;
+ };
+
+ tcon1_in_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon1_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon1>;
+ allwinner,tcon-channel = <1>;
+ };
+ };
+ };
+ };
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ahb_gates 8>,
- <&mmc0_clk 0>,
- <&mmc0_clk 1>,
- <&mmc0_clk 2>;
+ clocks = <&ccu CLK_AHB_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
#size-cells = <0>;
};
- mmc1: mmc@01c10000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ahb_gates 9>,
- <&mmc1_clk 0>,
- <&mmc1_clk 1>,
- <&mmc1_clk 2>;
+ clocks = <&ccu CLK_AHB_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
#size-cells = <0>;
};
- mmc2: mmc@01c11000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc2: mmc@1c11000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ahb_gates 10>,
- <&mmc2_clk 0>,
- <&mmc2_clk 1>,
- <&mmc2_clk 2>;
+ clocks = <&ccu CLK_AHB_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
#size-cells = <0>;
};
- mmc3: mmc@01c12000 {
- compatible = "allwinner,sun7i-a20-mmc",
- "allwinner,sun5i-a13-mmc";
+ mmc3: mmc@1c12000 {
+ compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c12000 0x1000>;
- clocks = <&ahb_gates 11>,
- <&mmc3_clk 0>,
- <&mmc3_clk 1>,
- <&mmc3_clk 2>;
+ clocks = <&ccu CLK_AHB_MMC3>,
+ <&ccu CLK_MMC3>,
+ <&ccu CLK_MMC3_OUTPUT>,
+ <&ccu CLK_MMC3_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
#size-cells = <0>;
};
- usb_otg: usb@01c13000 {
+ usb_otg: usb@1c13000 {
compatible = "allwinner,sun4i-a10-musb";
reg = <0x01c13000 0x0400>;
- clocks = <&ahb_gates 0>;
+ clocks = <&ccu CLK_AHB_OTG>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
status = "disabled";
};
- usbphy: phy@01c13400 {
+ usbphy: phy@1c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun7i-a20-usb-phy";
reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
reg-names = "phy_ctrl", "pmu1", "pmu2";
- clocks = <&usb_clk 8>;
+ clocks = <&ccu CLK_USB_PHY>;
clock-names = "usb_phy";
- resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>;
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
status = "disabled";
};
- ehci0: usb@01c14000 {
+ ehci0: usb@1c14000 {
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
reg = <0x01c14000 0x100>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 1>;
+ clocks = <&ccu CLK_AHB_EHCI0>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
- ohci0: usb@01c14400 {
+ ohci0: usb@1c14400 {
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
reg = <0x01c14400 0x100>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_clk 6>, <&ahb_gates 2>;
+ clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
- crypto: crypto-engine@01c15000 {
- compatible = "allwinner,sun4i-a10-crypto";
+ crypto: crypto-engine@1c15000 {
+ compatible = "allwinner,sun7i-a20-crypto",
+ "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 5>, <&ss_clk>;
+ clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
clock-names = "ahb", "mod";
};
- spi2: spi@01c17000 {
+ hdmi: hdmi@1c16000 {
+ compatible = "allwinner,sun7i-a20-hdmi",
+ "allwinner,sun5i-a10s-hdmi";
+ reg = <0x01c16000 0x1000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
+ <&ccu CLK_PLL_VIDEO0_2X>,
+ <&ccu CLK_PLL_VIDEO1_2X>;
+ clock-names = "ahb", "mod", "pll-0", "pll-1";
+ dmas = <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_DEDICATED 24>;
+ dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_hdmi>;
+ };
+
+ hdmi_in_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+ spi2: spi@1c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
<&dma SUN4I_DMA_DEDICATED 28>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ num-cs = <1>;
};
- ahci: sata@01c18000 {
+ ahci: sata@1c18000 {
compatible = "allwinner,sun4i-a10-ahci";
reg = <0x01c18000 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pll6 0>, <&ahb_gates 25>;
+ clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
status = "disabled";
};
- ehci1: usb@01c1c000 {
+ ehci1: usb@1c1c000 {
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
reg = <0x01c1c000 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 3>;
+ clocks = <&ccu CLK_AHB_EHCI1>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
- ohci1: usb@01c1c400 {
+ ohci1: usb@1c1c400 {
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
reg = <0x01c1c400 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_clk 7>, <&ahb_gates 4>;
+ clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
- spi3: spi@01c1f000 {
+ spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 23>, <&spi3_clk>;
+ clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 31>,
<&dma SUN4I_DMA_DEDICATED 30>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ num-cs = <1>;
};
- pio: pinctrl@01c20800 {
+ ccu: clock@1c20000 {
+ compatible = "allwinner,sun7i-a20-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pio: pinctrl@1c20800 {
compatible = "allwinner,sun7i-a20-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 5>;
+ clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ can0_pins_a: can0@0 {
+ pins = "PH20", "PH21";
+ function = "can";
+ };
+
clk_out_a_pins_a: clk_out_a@0 {
- allwinner,pins = "PI12";
- allwinner,function = "clk_out_a";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI12";
+ function = "clk_out_a";
};
clk_out_b_pins_a: clk_out_b@0 {
- allwinner,pins = "PI13";
- allwinner,function = "clk_out_b";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI13";
+ function = "clk_out_b";
};
emac_pins_a: emac0@0 {
- allwinner,pins = "PA0", "PA1", "PA2",
- "PA3", "PA4", "PA5", "PA6",
- "PA7", "PA8", "PA9", "PA10",
- "PA11", "PA12", "PA13", "PA14",
- "PA15", "PA16";
- allwinner,function = "emac";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ function = "emac";
};
gmac_pins_mii_a: gmac_mii@0 {
- allwinner,pins = "PA0", "PA1", "PA2",
- "PA3", "PA4", "PA5", "PA6",
- "PA7", "PA8", "PA9", "PA10",
- "PA11", "PA12", "PA13", "PA14",
- "PA15", "PA16";
- allwinner,function = "gmac";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ function = "gmac";
};
gmac_pins_rgmii_a: gmac_rgmii@0 {
- allwinner,pins = "PA0", "PA1", "PA2",
- "PA3", "PA4", "PA5", "PA6",
- "PA7", "PA8", "PA10",
- "PA11", "PA12", "PA13",
- "PA15", "PA16";
- allwinner,function = "gmac";
+ pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA10",
+ "PA11", "PA12", "PA13",
+ "PA15", "PA16";
+ function = "gmac";
/*
* data lines in RGMII mode use DDR mode
* and need a higher signal drive strength
*/
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ drive-strength = <40>;
};
i2c0_pins_a: i2c0@0 {
- allwinner,pins = "PB0", "PB1";
- allwinner,function = "i2c0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB0", "PB1";
+ function = "i2c0";
};
i2c1_pins_a: i2c1@0 {
- allwinner,pins = "PB18", "PB19";
- allwinner,function = "i2c1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB18", "PB19";
+ function = "i2c1";
};
i2c2_pins_a: i2c2@0 {
- allwinner,pins = "PB20", "PB21";
- allwinner,function = "i2c2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB20", "PB21";
+ function = "i2c2";
};
i2c3_pins_a: i2c3@0 {
- allwinner,pins = "PI0", "PI1";
- allwinner,function = "i2c3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI0", "PI1";
+ function = "i2c3";
};
ir0_rx_pins_a: ir0@0 {
- allwinner,pins = "PB4";
- allwinner,function = "ir0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB4";
+ function = "ir0";
};
ir0_tx_pins_a: ir0@1 {
- allwinner,pins = "PB3";
- allwinner,function = "ir0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB3";
+ function = "ir0";
};
ir1_rx_pins_a: ir1@0 {
- allwinner,pins = "PB23";
- allwinner,function = "ir1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB23";
+ function = "ir1";
};
ir1_tx_pins_a: ir1@1 {
- allwinner,pins = "PB22";
- allwinner,function = "ir1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB22";
+ function = "ir1";
};
mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0", "PF1", "PF2",
- "PF3", "PF4", "PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
- allwinner,pins = "PH1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PF0", "PF1", "PF2",
+ "PF3", "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
};
mmc2_pins_a: mmc2@0 {
- allwinner,pins = "PC6", "PC7", "PC8",
- "PC9", "PC10", "PC11";
- allwinner,function = "mmc2";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PC6", "PC7", "PC8",
+ "PC9", "PC10", "PC11";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
};
mmc3_pins_a: mmc3@0 {
- allwinner,pins = "PI4", "PI5", "PI6",
- "PI7", "PI8", "PI9";
- allwinner,function = "mmc3";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI4", "PI5", "PI6",
+ "PI7", "PI8", "PI9";
+ function = "mmc3";
+ drive-strength = <30>;
+ bias-pull-up;
};
ps20_pins_a: ps20@0 {
- allwinner,pins = "PI20", "PI21";
- allwinner,function = "ps2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI20", "PI21";
+ function = "ps2";
};
ps21_pins_a: ps21@0 {
- allwinner,pins = "PH12", "PH13";
- allwinner,function = "ps2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH12", "PH13";
+ function = "ps2";
};
pwm0_pins_a: pwm0@0 {
- allwinner,pins = "PB2";
- allwinner,function = "pwm";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB2";
+ function = "pwm";
};
pwm1_pins_a: pwm1@0 {
- allwinner,pins = "PI3";
- allwinner,function = "pwm";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI3";
+ function = "pwm";
};
spdif_tx_pins_a: spdif@0 {
- allwinner,pins = "PB13";
- allwinner,function = "spdif";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PB13";
+ function = "spdif";
+ bias-pull-up;
};
spi0_pins_a: spi0@0 {
- allwinner,pins = "PI11", "PI12", "PI13";
- allwinner,function = "spi0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI11", "PI12", "PI13";
+ function = "spi0";
};
spi0_cs0_pins_a: spi0_cs0@0 {
- allwinner,pins = "PI10";
- allwinner,function = "spi0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI10";
+ function = "spi0";
};
spi0_cs1_pins_a: spi0_cs1@0 {
- allwinner,pins = "PI14";
- allwinner,function = "spi0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI14";
+ function = "spi0";
};
spi1_pins_a: spi1@0 {
- allwinner,pins = "PI17", "PI18", "PI19";
- allwinner,function = "spi1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI17", "PI18", "PI19";
+ function = "spi1";
};
spi1_cs0_pins_a: spi1_cs0@0 {
- allwinner,pins = "PI16";
- allwinner,function = "spi1";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI16";
+ function = "spi1";
};
spi2_pins_a: spi2@0 {
- allwinner,pins = "PC20", "PC21", "PC22";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC20", "PC21", "PC22";
+ function = "spi2";
};
spi2_pins_b: spi2@1 {
- allwinner,pins = "PB15", "PB16", "PB17";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB15", "PB16", "PB17";
+ function = "spi2";
};
spi2_cs0_pins_a: spi2_cs0@0 {
- allwinner,pins = "PC19";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PC19";
+ function = "spi2";
};
spi2_cs0_pins_b: spi2_cs0@1 {
- allwinner,pins = "PB14";
- allwinner,function = "spi2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB14";
+ function = "spi2";
};
uart0_pins_a: uart0@0 {
- allwinner,pins = "PB22", "PB23";
- allwinner,function = "uart0";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PB22", "PB23";
+ function = "uart0";
};
uart2_pins_a: uart2@0 {
- allwinner,pins = "PI16", "PI17", "PI18", "PI19";
- allwinner,function = "uart2";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI16", "PI17", "PI18", "PI19";
+ function = "uart2";
};
uart3_pins_a: uart3@0 {
- allwinner,pins = "PG6", "PG7", "PG8", "PG9";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG6", "PG7", "PG8", "PG9";
+ function = "uart3";
};
uart3_pins_b: uart3@1 {
- allwinner,pins = "PH0", "PH1";
- allwinner,function = "uart3";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH0", "PH1";
+ function = "uart3";
};
uart4_pins_a: uart4@0 {
- allwinner,pins = "PG10", "PG11";
- allwinner,function = "uart4";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PG10", "PG11";
+ function = "uart4";
};
uart4_pins_b: uart4@1 {
- allwinner,pins = "PH4", "PH5";
- allwinner,function = "uart4";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH4", "PH5";
+ function = "uart4";
};
uart5_pins_a: uart5@0 {
- allwinner,pins = "PI10", "PI11";
- allwinner,function = "uart5";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI10", "PI11";
+ function = "uart5";
};
uart6_pins_a: uart6@0 {
- allwinner,pins = "PI12", "PI13";
- allwinner,function = "uart6";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI12", "PI13";
+ function = "uart6";
};
uart7_pins_a: uart7@0 {
- allwinner,pins = "PI20", "PI21";
- allwinner,function = "uart7";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PI20", "PI21";
+ function = "uart7";
};
};
- timer@01c20c00 {
+ timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
clocks = <&osc24M>;
};
- wdt: watchdog@01c20c90 {
+ wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
};
- rtc: rtc@01c20d00 {
+ rtc: rtc@1c20d00 {
compatible = "allwinner,sun7i-a20-rtc";
reg = <0x01c20d00 0x20>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
};
- pwm: pwm@01c20e00 {
+ pwm: pwm@1c20e00 {
compatible = "allwinner,sun7i-a20-pwm";
reg = <0x01c20e00 0xc>;
clocks = <&osc24M>;
status = "disabled";
};
- spdif: spdif@01c21000 {
+ spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-spdif";
reg = <0x01c21000 0x400>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 1>, <&spdif_clk>;
+ clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
clock-names = "apb", "spdif";
dmas = <&dma SUN4I_DMA_NORMAL 2>,
<&dma SUN4I_DMA_NORMAL 2>;
status = "disabled";
};
- ir0: ir@01c21800 {
+ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
- clocks = <&apb0_gates 6>, <&ir0_clk>;
+ clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
clock-names = "apb", "ir";
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01c21800 0x40>;
status = "disabled";
};
- ir1: ir@01c21c00 {
+ ir1: ir@1c21c00 {
compatible = "allwinner,sun4i-a10-ir";
- clocks = <&apb0_gates 7>, <&ir1_clk>;
+ clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
clock-names = "apb", "ir";
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01c21c00 0x40>;
status = "disabled";
};
- i2s1: i2s@01c22000 {
+ i2s1: i2s@1c22000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-i2s";
reg = <0x01c22000 0x400>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 4>, <&i2s1_clk>;
+ clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
clock-names = "apb", "mod";
dmas = <&dma SUN4I_DMA_NORMAL 4>,
<&dma SUN4I_DMA_NORMAL 4>;
status = "disabled";
};
- i2s0: i2s@01c22400 {
+ i2s0: i2s@1c22400 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-i2s";
reg = <0x01c22400 0x400>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 3>, <&i2s0_clk>;
+ clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
clock-names = "apb", "mod";
dmas = <&dma SUN4I_DMA_NORMAL 3>,
<&dma SUN4I_DMA_NORMAL 3>;
status = "disabled";
};
- lradc: lradc@01c22800 {
+ lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- codec: codec@01c22c00 {
+ codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun7i-a20-codec";
reg = <0x01c22c00 0x40>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>, <&codec_clk>;
+ clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
clock-names = "apb", "codec";
dmas = <&dma SUN4I_DMA_NORMAL 19>,
<&dma SUN4I_DMA_NORMAL 19>;
status = "disabled";
};
- sid: eeprom@01c23800 {
+ sid: eeprom@1c23800 {
compatible = "allwinner,sun7i-a20-sid";
reg = <0x01c23800 0x200>;
};
- i2s2: i2s@01c24400 {
+ i2s2: i2s@1c24400 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun4i-a10-i2s";
reg = <0x01c24400 0x400>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 8>, <&i2s2_clk>;
+ clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
clock-names = "apb", "mod";
dmas = <&dma SUN4I_DMA_NORMAL 6>,
<&dma SUN4I_DMA_NORMAL 6>;
status = "disabled";
};
- rtp: rtp@01c25000 {
+ rtp: rtp@1c25000 {
compatible = "allwinner,sun5i-a13-ts";
reg = <0x01c25000 0x100>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
};
- uart0: serial@01c28000 {
+ uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 16>;
+ clocks = <&ccu CLK_APB1_UART0>;
status = "disabled";
};
- uart1: serial@01c28400 {
+ uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 17>;
+ clocks = <&ccu CLK_APB1_UART1>;
status = "disabled";
};
- uart2: serial@01c28800 {
+ uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 18>;
+ clocks = <&ccu CLK_APB1_UART2>;
status = "disabled";
};
- uart3: serial@01c28c00 {
+ uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 19>;
+ clocks = <&ccu CLK_APB1_UART3>;
status = "disabled";
};
- uart4: serial@01c29000 {
+ uart4: serial@1c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 20>;
+ clocks = <&ccu CLK_APB1_UART4>;
status = "disabled";
};
- uart5: serial@01c29400 {
+ uart5: serial@1c29400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29400 0x400>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 21>;
+ clocks = <&ccu CLK_APB1_UART5>;
status = "disabled";
};
- uart6: serial@01c29800 {
+ uart6: serial@1c29800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29800 0x400>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 22>;
+ clocks = <&ccu CLK_APB1_UART6>;
status = "disabled";
};
- uart7: serial@01c29c00 {
+ uart7: serial@1c29c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29c00 0x400>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 23>;
+ clocks = <&ccu CLK_APB1_UART7>;
status = "disabled";
};
- i2c0: i2c@01c2ac00 {
+ ps20: ps2@1c2a000 {
+ compatible = "allwinner,sun4i-a10-ps2";
+ reg = <0x01c2a000 0x400>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1_PS20>;
+ status = "disabled";
+ };
+
+ ps21: ps2@1c2a400 {
+ compatible = "allwinner,sun4i-a10-ps2";
+ reg = <0x01c2a400 0x400>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1_PS21>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun7i-a20-i2c",
"allwinner,sun4i-a10-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 0>;
+ clocks = <&ccu CLK_APB1_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c1: i2c@01c2b000 {
+ i2c1: i2c@1c2b000 {
compatible = "allwinner,sun7i-a20-i2c",
"allwinner,sun4i-a10-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 1>;
+ clocks = <&ccu CLK_APB1_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c2: i2c@01c2b400 {
+ i2c2: i2c@1c2b400 {
compatible = "allwinner,sun7i-a20-i2c",
"allwinner,sun4i-a10-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 2>;
+ clocks = <&ccu CLK_APB1_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c3: i2c@01c2b800 {
+ i2c3: i2c@1c2b800 {
compatible = "allwinner,sun7i-a20-i2c",
"allwinner,sun4i-a10-i2c";
reg = <0x01c2b800 0x400>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 3>;
+ clocks = <&ccu CLK_APB1_I2C3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- i2c4: i2c@01c2c000 {
+ can0: can@1c2bc00 {
+ compatible = "allwinner,sun7i-a20-can",
+ "allwinner,sun4i-a10-can";
+ reg = <0x01c2bc00 0x400>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1_CAN>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@1c2c000 {
compatible = "allwinner,sun7i-a20-i2c",
"allwinner,sun4i-a10-i2c";
reg = <0x01c2c000 0x400>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 15>;
+ clocks = <&ccu CLK_APB1_I2C4>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- gmac: ethernet@01c50000 {
+ mali: gpu@1c40000 {
+ compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_GPU>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <384000000>;
+ };
+
+ gmac: ethernet@1c50000 {
compatible = "allwinner,sun7i-a20-gmac";
reg = <0x01c50000 0x10000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
- clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
+ clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
clock-names = "stmmaceth", "allwinner_gmac_tx";
snps,pbl = <2>;
snps,fixed-burst;
#size-cells = <0>;
};
- hstimer@01c60000 {
+ hstimer@1c60000 {
compatible = "allwinner,sun7i-a20-hstimer";
reg = <0x01c60000 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ahb_gates 28>;
+ clocks = <&ccu CLK_AHB_HSTIMER>;
};
- gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- ps20: ps2@01c2a000 {
- compatible = "allwinner,sun4i-a10-ps2";
- reg = <0x01c2a000 0x400>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 6>;
- status = "disabled";
+ fe0: display-frontend@1e00000 {
+ compatible = "allwinner,sun7i-a20-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
+ <&ccu CLK_DRAM_DE_FE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_FE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+
+ fe0_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_fe0>;
+ };
+ };
+ };
};
- ps21: ps2@01c2a400 {
- compatible = "allwinner,sun4i-a10-ps2";
- reg = <0x01c2a400 0x400>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 7>;
- status = "disabled";
+ fe1: display-frontend@1e20000 {
+ compatible = "allwinner,sun7i-a20-display-frontend";
+ reg = <0x01e20000 0x20000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
+ <&ccu CLK_DRAM_DE_FE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_FE1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe1_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe1>;
+ };
+
+ fe1_out_be1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&be1_in_fe1>;
+ };
+ };
+ };
+ };
+
+ be1: display-backend@1e40000 {
+ compatible = "allwinner,sun7i-a20-display-backend";
+ reg = <0x01e40000 0x10000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
+ <&ccu CLK_DRAM_DE_BE1>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_BE1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be1_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be1>;
+ };
+
+ be1_in_fe1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&fe1_out_be1>;
+ };
+ };
+
+ be1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be1_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be1>;
+ };
+
+ be1_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_be1>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@1e60000 {
+ compatible = "allwinner,sun7i-a20-display-backend";
+ reg = <0x01e60000 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
+ <&ccu CLK_DRAM_DE_BE0>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_DE_BE0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+
+ be0_in_fe1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&fe1_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be0>;
+ };
+
+ be0_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_be0>;
+ };
+ };
+ };
};
};
};
};
};
- soc@01c00000 {
+ soc@1c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- dma: dma-controller@01c02000 {
+ dma: dma-controller@1c02000 {
compatible = "allwinner,sun8i-a23-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
};
- mmc0: mmc@01c0f000 {
+ mmc0: mmc@1c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_BUS_MMC0>,
#size-cells = <0>;
};
- mmc1: mmc@01c10000 {
+ mmc1: mmc@1c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>,
#size-cells = <0>;
};
- mmc2: mmc@01c11000 {
+ mmc2: mmc@1c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>,
#size-cells = <0>;
};
- nfc: nand@01c03000 {
+ nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
- usb_otg: usb@01c19000 {
+ usb_otg: usb@1c19000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
status = "disabled";
};
- usbphy: phy@01c19400 {
+ usbphy: phy@1c19400 {
/*
* compatible and address regions get set in
* SoC specific dtsi file
#phy-cells = <1>;
};
- ehci0: usb@01c1a000 {
+ ehci0: usb@1c1a000 {
compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- ohci0: usb@01c1a400 {
+ ohci0: usb@1c1a400 {
compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- ccu: clock@01c20000 {
+ ccu: clock@1c20000 {
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clock-names = "hosc", "losc";
#reset-cells = <1>;
};
- pio: pinctrl@01c20800 {
+ pio: pinctrl@1c20800 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c20800 0x400>;
/* interrupts get set in SoC specific dtsi file */
function = "uart1";
};
- nand_pins_a: nand-base0@0 {
- pins = "PC0", "PC1", "PC2", "PC5",
- "PC8", "PC9", "PC10", "PC11",
- "PC12", "PC13", "PC14", "PC15";
- function = "nand0";
- };
-
- nand_cs0_pins_a: nand-cs@0 {
- pins = "PC4";
- function = "nand0";
- };
-
- nand_rb0_pins_a: nand-rb@0 {
- pins = "PC6";
- function = "nand0";
- };
-
mmc0_pins_a: mmc0@0 {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
bias-pull-up;
};
+ nand_pins: nand-pins {
+ pins = "PC0", "PC1", "PC2", "PC5",
+ "PC8", "PC9", "PC10", "PC11",
+ "PC12", "PC13", "PC14", "PC15";
+ function = "nand0";
+ };
+
+ nand_pins_cs0: nand-pins-cs0 {
+ pins = "PC4";
+ function = "nand0";
+ bias-pull-up;
+ };
+
+ nand_pins_cs1: nand-pins-cs1 {
+ pins = "PC3";
+ function = "nand0";
+ bias-pull-up;
+ };
+
+ nand_pins_rb0: nand-pins-rb0 {
+ pins = "PC6";
+ function = "nand0";
+ bias-pull-up;
+ };
+
+ nand_pins_rb1: nand-pins-rb1 {
+ pins = "PC7";
+ function = "nand0";
+ bias-pull-up;
+ };
+
pwm0_pins: pwm0 {
pins = "PH0";
function = "pwm0";
};
};
- timer@01c20c00 {
+ timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
clocks = <&osc24M>;
};
- wdt0: watchdog@01c20ca0 {
+ wdt0: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
- pwm: pwm@01c21400 {
+ pwm: pwm@1c21400 {
compatible = "allwinner,sun7i-a20-pwm";
reg = <0x01c21400 0xc>;
clocks = <&osc24M>;
status = "disabled";
};
- lradc: lradc@01c22800 {
+ lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- uart0: serial@01c28000 {
+ uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- uart1: serial@01c28400 {
+ uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- uart2: serial@01c28800 {
+ uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- uart3: serial@01c28c00 {
+ uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- uart4: serial@01c29000 {
+ uart4: serial@1c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- i2c0: i2c@01c2ac00 {
+ i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#size-cells = <0>;
};
- i2c1: i2c@01c2b000 {
+ i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#size-cells = <0>;
};
- i2c2: i2c@01c2b400 {
+ i2c2: i2c@1c2b400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
assigned-clock-rates = <384000000>;
};
- gic: interrupt-controller@01c81000 {
+ gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- rtc: rtc@01f00000 {
+ rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
- prcm@01f01400 {
+ prcm@1f01400 {
compatible = "allwinner,sun8i-a23-prcm";
reg = <0x01f01400 0x200>;
};
};
- cpucfg@01f01c00 {
+ cpucfg@1f01c00 {
compatible = "allwinner,sun8i-a23-cpuconfig";
reg = <0x01f01c00 0x300>;
};
- r_uart: serial@01f02800 {
+ r_uart: serial@1f02800 {
compatible = "snps,dw-apb-uart";
reg = <0x01f02800 0x400>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- r_pio: pinctrl@01f02c00 {
+ r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a23-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
};
};
- r_rsb: rsb@01f03400 {
+ r_rsb: rsb@1f03400 {
compatible = "allwinner,sun8i-a23-rsb";
reg = <0x01f03400 0x400>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Allwinner A23 Evaluation Board";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_evb>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
&pio {
mmc0_cd_pin_evb: mmc0_cd_pin@0 {
- allwinner,pins = "PB4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PB4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
status = "okay";
};
-&gsl1680 {
+&touchscreen {
+ reg = <0x40>;
compatible = "silead,gsl3675";
- touchscreen-fw-name = "silead/gsl3675-gt90h.fw";
+ firmware-name = "gsl3675-gt90h.fw";
touchscreen-size-x = <1792>;
touchscreen-size-y = <1024>;
status = "okay";
status = "okay";
};
-&gsl1680 {
+&touchscreen {
+ reg = <0x40>;
+ compatible = "silead,gsl1680";
+ firmware-name = "gsl1680-inet86dz.fw";
touchscreen-size-x = <960>;
touchscreen-size-y = <640>;
- touchscreen-fw-name = "silead/gsl1680-inet86dz.fw";
status = "okay";
};
};
};
-&gsl1680 {
- vddio-supply = <®_ldo_io1>;
- touchscreen-size-x = <960>;
- touchscreen-size-y = <640>;
- touchscreen-inverted-x;
- touchscreen-inverted-y;
- touchscreen-fw-name = "silead/gsl1680-polaroid-mid2407pxe03.fw";
- status = "okay";
+&i2c1 {
+ mma7660: accelerometer@4c {
+ reg = <0x4c>;
+ compatible = "fsl,mma7660";
+ };
};
&mmc1 {
};
&mmc1_pins_a {
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&r_pio {
wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin@0 {
- allwinner,pins = "PL6";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PL6";
+ function = "gpio_out";
};
};
-®_ldo_io1 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-touchscreen";
+&touchscreen {
+ reg = <0x40>;
+ compatible = "silead,gsl1680";
+ firmware-name = "gsl1680-polaroid-mid2407pxe03.fw";
+ touchscreen-size-x = <960>;
+ touchscreen-size-y = <640>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ vddio-supply = <®_ldo_io1>;
status = "okay";
};
};
};
-&gsl1680 {
- compatible = "silead,gsl3670";
- touchscreen-fw-name = "silead/gsl3670-polaroid-mid2809pxe04.fw";
- touchscreen-size-x = <1660>;
- touchscreen-size-y = <890>;
- status = "okay";
-};
-
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
};
&mmc1_pins_a {
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&r_pio {
wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin@0 {
- allwinner,pins = "PL6";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PL6";
+ function = "gpio_out";
};
};
+
+&touchscreen {
+ reg = <0x40>;
+ compatible = "silead,gsl3670";
+ firmware-name = "gsl3670-polaroid-mid2809pxe04.fw";
+ touchscreen-size-x = <1660>;
+ touchscreen-size-y = <890>;
+ status = "okay";
+};
model = "Q8 A23 Tablet";
compatible = "allwinner,q8-a23", "allwinner,sun8i-a23";
};
+
+&codec {
+ allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+ allwinner,audio-routing =
+ "Headphone", "HP",
+ "Headphone", "HPCOM",
+ "Speaker", "HP",
+ "MIC1", "Mic",
+ "MIC2", "Headset Mic",
+ "Mic", "MBIAS",
+ "Headset Mic", "HBIAS";
+ status = "okay";
+};
reg = <0x40000000 0x40000000>;
};
- soc@01c00000 {
- codec: codec@01c22c00 {
+ soc@1c00000 {
+ codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-a23-codec";
reg = <0x01c22c00 0x400>;
status = "okay";
};
-&gsl1680 {
+&touchscreen {
+ reg = <0x40>;
compatible = "silead,gsl3675";
- touchscreen-fw-name = "silead/gsl3675-ga10h.fw";
+ firmware-name = "gsl3675-ga10h.fw";
touchscreen-size-x = <1630>;
touchscreen-size-y = <990>;
touchscreen-inverted-y;
model = "INet-D978 Rev 02";
compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33";
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ /* Delete debug UART as serial0 is the UART for bluetooth */
+ /delete-property/stdout-path;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
};
&mmc1_pins_a {
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&mmc1 {
&r_pio {
led_pin_d978: led_pin_d978@0 {
- allwinner,pins = "PL5";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PL5";
+ function = "gpio_out";
+ drive-strength = <20>;
};
};
+
+&r_uart {
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>,
+ <&uart1_pins_cts_rts_a>;
+ status = "okay";
+};
/dts-v1/;
#include "sun8i-a33.dtsi"
-#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pin_olinuxino>;
green {
label = "a33-olinuxino:green:usr";
};
};
+&codec {
+ status = "okay";
+};
+
+&dai {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
+ pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
status = "okay";
};
-&pio {
- led_pin_olinuxino: led_pins@0 {
- allwinner,pins = "PB7";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
- allwinner,pins = "PB4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PB3";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
&r_rsb {
status = "okay";
};
};
-#include "axp22x.dtsi"
+#include "axp223.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
®_aldo1 {
regulator-always-on;
vcc-lcd-supply = <®_dc1sw>;
};
+&sound {
+ /* Board level jack widgets */
+ simple-audio-card,widgets = "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack";
+ /* Board level routing. First 2 routes copied from SoC level */
+ simple-audio-card,routing =
+ "Left DAC", "AIF1 Slot 0 Left",
+ "Right DAC", "AIF1 Slot 0 Right",
+ "HP", "HPCOM",
+ "Headphone Jack", "HP",
+ "MIC1", "Microphone Jack",
+ "Microphone Jack", "MBIAS";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_drivevbus>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Sinlinx SinA33";
};
};
-&de {
+&codec {
status = "okay";
};
cpu-supply = <®_dcdc3>;
};
+&cpu0_opp_table {
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+};
+
+&de {
+ status = "okay";
+};
+
+&dai {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
&mmc2_8bit_pins {
/* Increase drive strength for DDR modes */
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ drive-strength = <40>;
/* eMMC is missing pull-ups */
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&ohci0 {
&pio {
mmc0_cd_pin_sina33: mmc0_cd_pin@0 {
- allwinner,pins = "PB4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PB4";
+ function = "gpio_in";
+ bias-pull-up;
};
};
};
};
-#include "axp22x.dtsi"
+#include "axp223.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
®_aldo1 {
regulator-always-on;
regulator-name = "vcc-rtc";
};
+&sound {
+ status = "okay";
+};
+
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
};
};
- soc@01c00000 {
- tcon0: lcd-controller@01c0c000 {
+ soc@1c00000 {
+ tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun8i-a33-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ tcon0_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_tcon0>;
+ };
};
};
};
- crypto: crypto-engine@01c15000 {
+ crypto: crypto-engine@1c15000 {
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
reset-names = "ahb";
};
- dai: dai@01c22c00 {
+ dai: dai@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun6i-a31-i2s";
reg = <0x01c22c00 0x200>;
status = "disabled";
};
- codec: codec@01c22e00 {
+ codec: codec@1c22e00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x400>;
status = "disabled";
};
- ths: ths@01c25000 {
+ ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
#thermal-sensor-cells = <0>;
#io-channel-cells = <0>;
};
- fe0: display-frontend@01e00000 {
+ dsi: dsi@1ca0000 {
+ compatible = "allwinner,sun6i-a31-mipi-dsi";
+ reg = <0x01ca0000 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ <&ccu CLK_DSI_SCLK>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ phys = <&dphy>;
+ phy-names = "dphy";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dsi_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_dsi>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1ca1000 {
+ compatible = "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01ca1000 0x1000>;
+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
+ <&ccu CLK_DSI_DPHY>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_MIPI_DSI>;
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ fe0: display-frontend@1e00000 {
compatible = "allwinner,sun8i-a33-display-frontend";
reg = <0x01e00000 0x20000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_BUS_DE_FE>;
- status = "disabled";
ports {
#address-cells = <1>;
};
};
- be0: display-backend@01e60000 {
+ be0: display-backend@1e60000 {
compatible = "allwinner,sun8i-a33-display-backend";
reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
reg-names = "be", "sat";
};
};
- drc0: drc@01e70000 {
+ drc0: drc@1e70000 {
compatible = "allwinner,sun8i-a33-drc";
reg = <0x01e70000 0x10000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ethernet0 = &sdio_wifi;
};
- q8_hardwaremgr {
- compatible = "allwinner,sunxi-q8-hardwaremgr";
- touchscreen-i2c-bus = <&i2c0>;
- touchscreen-supply = <®_ldo_io1>;
- touchscreen-power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- };
-
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
/*
};
&mmc1_pins_a {
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ bias-pull-up;
};
&r_pio {
wifi_pwrseq_pin_q8: wifi_pwrseq_pin@0 {
- allwinner,pins = "PL6", "PL7", "PL11";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PL6", "PL7", "PL11";
+ function = "gpio_in";
+ bias-pull-up;
};
};
&usbphy {
usb1_vbus-supply = <®_dldo1>;
};
-
-&gsl1680 {
- touchscreen-size-x = <1024>;
- touchscreen-size-y = <600>;
- touchscreen-fw-name = "silead/gsl1680-q8-700.fw";
- status = "okay";
-};
-
-®_ldo_io1 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-touchscreen";
- status = "okay";
-};
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
};
&nfc {
- pinctrl-names = "default";
- pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
status = "okay";
nand@0 {
};
+&codec {
+ status = "okay";
+};
+
+&dai {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
};
&mmc2_8bit_pins {
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ drive-strength = <40>;
+ bias-pull-up;
};
&ohci0 {
&pio {
mmc0_cd_pin_parrot: mmc0_cd_pin@0 {
- allwinner,pins = "PD14";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PD14";
+ function = "gpio_in";
+ bias-pull-up;
};
led_pins_parrot: led_pins@0 {
- allwinner,pins = "PE16", "PE17";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PE16", "PE17";
+ function = "gpio_out";
};
usb0_id_det: usb0_id_detect_pin@0 {
- allwinner,pins = "PD10";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PD10";
+ function = "gpio_in";
+ bias-pull-up;
};
usb1_vbus_pin_parrot: usb1_vbus_pin@0 {
- allwinner,pins = "PD12";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PD12";
+ function = "gpio_out";
};
};
&r_pio {
wifi_reset_pin_parrot: wifi_reset_pin@0 {
- allwinner,pins = "PL6";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PL6";
+ function = "gpio_out";
};
};
};
};
-#include "axp22x.dtsi"
+#include "axp223.dtsi"
®_aldo1 {
regulator-always-on;
status = "okay";
};
+&sound {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
backlight: backlight {
compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&bl_en_pin>;
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
*/
clock-frequency = <400000>;
- gsl1680: touchscreen@40 {
- compatible = "silead,gsl1680";
- reg = <0x40>;
+ touchscreen: touchscreen@0 {
interrupt-parent = <&pio>;
interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */
pinctrl-names = "default";
pinctrl-0 = <&ts_power_pin>;
power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
- /* Most tablets use this touchscreen, but not all */
+ /* Tablet dts must provide reg and compatible */
status = "disabled";
};
};
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
- cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
- cd-inverted;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
&pio {
- bl_en_pin: bl_en_pin@0 {
- allwinner,pins = "PH6";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
mmc0_cd_pin: mmc0_cd_pin@0 {
- allwinner,pins = "PB4";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PB4";
+ function = "gpio_in";
+ bias-pull-up;
};
ts_power_pin: ts_power_pin@0 {
- allwinner,pins = "PH1";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ pins = "PH1";
+ function = "gpio_out";
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PH8";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ pins = "PH8";
+ function = "gpio_in";
+ bias-pull-up;
};
};
};
};
-#include "axp22x.dtsi"
+#include "axp223.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
®_aldo1 {
regulator-always-on;
status = "okay";
};
+®_ldo_io1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-touchscreen";
+ status = "okay";
+};
+
®_rtc_ldo {
regulator-name = "vcc-rtc";
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
&r_uart {
pinctrl-names = "default";
pinctrl-0 = <&r_uart_pins_a>;
/* SoC related */
#ifdef CONFIG_ARCH_LS1043A
#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_QMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define SET_DEBUG_ICID(streamid) \
SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
+#define SET_QE_ICID(streamid) \
+ SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
+ QE_BASE_ADDR)
+
#define SET_QMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000)
#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000)
+#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000)
+
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000)
* -DPAA2
* -u-boot will allocate a range of stream IDs to be used by the Management
* Complex for containers and will set these values in the MC DPC image.
+ * -u-boot will fixup the iommu-map property in the fsl-mc node in the
+ * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
+ * for more info on the msi-map definition)
* -the MC is responsible for allocating and setting up 'isolation context
* IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
*
unsigned long freq_localbus;
};
+#define CCSR_DEVDISR1_QE 0x00000001
+
/* Device Configuration and Pin Control */
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
};
-
-
-/* AHCI (sata) register map */
-struct ccsr_ahci {
- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
- u32 pcfg; /* port config */
- u32 ppcfg; /* port phy1 config */
- u32 pp2c; /* port phy2 config */
- u32 pp3c; /* port phy3 config */
- u32 pp4c; /* port phy4 config */
- u32 pp5c; /* port phy5 config */
- u32 paxic; /* port AXI config */
- u32 axicc; /* AXI cache control */
- u32 axipc; /* AXI PROT control */
- u32 ptc; /* port Trans Config */
- u32 pts; /* port Trans Status */
- u32 plc; /* port link config */
- u32 plc1; /* port link config1 */
- u32 plc2; /* port link config2 */
- u32 pls; /* port link status */
- u32 pls1; /* port link status1 */
- u32 pcmdc; /* port CMD config */
- u32 ppcs; /* port phy control status */
- u32 pberr; /* port 0/1 BIST error */
- u32 cmds; /* port 0/1 CMD status error */
-};
-
#define RCPM_POWMGTCSR 0x130
#define RCPM_POWMGTCSR_SERDES_PW 0x80000000
#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_SATA_H_
-#define __FSL_SATA_H_
-
-int ls1021a_sata_init(void);
-#endif
#define PBIASLITEPWRDNZ0 (1 << 1)
#define PBIASSPEEDCTRL0 (1 << 2)
#define PBIASLITEPWRDNZ1 (1 << 9)
+#define PBIASLITEVMODE1 (1 << 8)
#define PBIASLITEVMODE0 (1 << 0)
#define CTLPROGIO1SPEEDCTRL (1 << 20)
#define MISC_SMIENB 0x00200000
#define MISC_GPIO3ENB 0x00040000
#define MISC_GPT3ENB 0x00010000
+#define MISC_SSP3ENB 0x00004000
#define MISC_GPIO4ENB 0x00002000
#define MISC_GPT2ENB 0x00000800
#define MISC_FSMCENB 0x00000200
#define MISC_I2CENB 0x00000080
-#define MISC_SSP2ENB 0x00000070
+#define MISC_SSP2ENB 0x00000040
+#define MISC_SSP1ENB 0x00000020
#define MISC_UART0ENB 0x00000008
/* PERIPH_CLK_CFG */
#define ZYNQMP_FPGA_AUTH_DDR 1
+#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001
+
+#define ZYNQMP_PM_VERSION_MAJOR 1
+#define ZYNQMP_PM_VERSION_MINOR 0
+#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
+#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
+
+#define ZYNQMP_PM_VERSION \
+ ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
+ ZYNQMP_PM_VERSION_MINOR)
+
+#define ZYNQMP_PM_VERSION_INVALID ~0
+
+#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
+
enum {
IDCODE,
VERSION,
void handoff_setup(void);
-void zynqmp_pmufw_version(void);
+unsigned int zynqmp_pmufw_version(void);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_mmio_read(const u32 address, u32 *value);
int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
#error SMP not supported
#endif
-typedef struct { volatile int counter; } atomic_t;
-#if BITS_PER_LONG == 32
-typedef struct { volatile long long counter; } atomic64_t;
-#else /* BIT_PER_LONG == 32 */
-typedef struct { volatile long counter; } atomic64_t;
-#endif
-
-#define ATOMIC_INIT(i) { (i) }
-
-#ifdef __KERNEL__
#include <asm/proc-armv/system.h>
-
-#define atomic_read(v) ((v)->counter)
-#define atomic_set(v, i) (((v)->counter) = (i))
-#define atomic64_read(v) atomic_read(v)
-#define atomic64_set(v, i) atomic_set(v, i)
-
-static inline void atomic_add(int i, volatile atomic_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_sub(int i, volatile atomic_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_inc(volatile atomic_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += 1;
- local_irq_restore(flags);
-}
-
-static inline void atomic_dec(volatile atomic_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= 1;
- local_irq_restore(flags);
-}
-
-static inline int atomic_dec_and_test(volatile atomic_t *v)
-{
- unsigned long flags = 0;
- int val;
-
- local_irq_save(flags);
- val = v->counter;
- v->counter = val -= 1;
- local_irq_restore(flags);
-
- return val == 0;
-}
-
-static inline int atomic_add_negative(int i, volatile atomic_t *v)
-{
- unsigned long flags = 0;
- int val;
-
- local_irq_save(flags);
- val = v->counter;
- v->counter = val += i;
- local_irq_restore(flags);
-
- return val < 0;
-}
-
-static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- *addr &= ~mask;
- local_irq_restore(flags);
-}
-
-#if BITS_PER_LONG == 32
-
-static inline void atomic64_add(long long i, volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += i;
- local_irq_restore(flags);
-}
-
-static inline void atomic64_sub(long long i, volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= i;
- local_irq_restore(flags);
-}
-
-#else /* BIT_PER_LONG == 32 */
-
-static inline void atomic64_add(long i, volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += i;
- local_irq_restore(flags);
-}
-
-static inline void atomic64_sub(long i, volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= i;
- local_irq_restore(flags);
-}
-#endif
-
-static inline void atomic64_inc(volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter += 1;
- local_irq_restore(flags);
-}
-
-static inline void atomic64_dec(volatile atomic64_t *v)
-{
- unsigned long flags = 0;
-
- local_irq_save(flags);
- v->counter -= 1;
- local_irq_restore(flags);
-}
+#include <asm-generic/atomic.h>
/* Atomic operations are already serializing on ARM */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_inc() barrier()
#endif
-#endif
struct mmc_config cfg;
struct hsmmc *base_addr;
struct mmc *mmc;
- bool cd_inverted;
u32 controller_flags;
const char *hw_rev;
};
bool "SAMA5D2 PTC EK board"
select BOARD_EARLY_INIT_F
select SAMA5D2
+ select BOARD_LATE_INIT
config TARGET_SAMA5D2_XPLAINED
bool "SAMA5D2 Xplained board"
select BOARD_EARLY_INIT_F
select SAMA5D3
select SUPPORT_SPL
+ select BOARD_LATE_INIT
config TARGET_SAMA5D3XEK
bool "SAMA5D3X-EK board"
/* GPIO setup */
board_gpio_init();
-
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
+#endif
/*
* Fix Power and Emulation Management Register
* see sprufw3a.pdf page 37 Table 24
config TARGET_DRAGONBOARD410C
bool "96Boards Dragonboard 410C"
+ select BOARD_LATE_INIT
help
Support for 96Boards Dragonboard 410C. This board complies with
96Board Open Platform Specifications. Features:
#include <common.h>
#include <dm.h>
+#include <efi_loader.h>
#include <errno.h>
#include <ns16550.h>
#include <usb.h>
int board_late_init(void)
{
+#if CONFIG_IS_ENABLED(EFI_LOADER)
+ if (gd->bd->bi_dram[1].start) {
+ /*
+ * Only bank 0 is below board_get_usable_ram_top(), so all of
+ * bank 1 is not mapped by the U-Boot MMU configuration, and so
+ * we must prevent EFI from using it.
+ */
+ efi_add_memory_map(gd->bd->bi_dram[1].start,
+ gd->bd->bi_dram[1].size >> EFI_PAGE_SHIFT,
+ EFI_BOOT_SERVICES_DATA, false);
+ }
+#endif
+
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (tegra_cpu_is_non_secure()) {
printf("CPU is in NS mode\n");
select DM_SERIAL
select DYNAMIC_IO_PORT_BASE
select MIPS_CM
+ select MIPS_INSERT_BOOT_CONFIG
select MIPS_L1_CACHE_SHIFT_6
select MIPS_L2_CACHE
select OF_CONTROL
select SYSRESET
imply CMD_DM
+config ARCH_MT7620
+ bool "Support MT7620/7688 SoCs"
+ imply CMD_DM
+ select DISPLAY_CPUINFO
+ select DM
+ select DM_SERIAL
+ imply DM_SPI
+ imply DM_SPI_FLASH
+ select MIPS_TUNE_24KC
+ select OF_CONTROL
+ select ROM_EXCEPTION_VECTORS
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_LITTLE_ENDIAN
+ select SYSRESET
+
config MACH_PIC32
bool "Support Microchip PIC32"
select DM
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-bmips/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
+source "arch/mips/mach-mt7620/Kconfig"
if MIPS
the GCRs occupy a region of the physical address space which is
otherwise unused, or at minimum that software doesn't need to access.
+config MIPS_CACHE_INDEX_BASE
+ hex "Index base address for cache initialisation"
+ default 0x80000000 if CPU_MIPS32
+ default 0xffffffff80000000 if CPU_MIPS64
+ help
+ This is the base address for a memory block, which is used for
+ initialising the cache lines. This is also the base address of a memory
+ block which is used for loading and filling cache lines when
+ SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
+ Normally this is CKSEG0. If the MIPS system needs to move this block
+ to some SRAM or ScratchPad RAM, adapt this option accordingly.
+
endmenu
menu "OS boot interface"
wish U-Boot to configure it or make use of it to retrieve system
information such as cache configuration.
+config MIPS_INSERT_BOOT_CONFIG
+ bool
+ default n
+ help
+ Enable this to insert some board-specific boot configuration in
+ the U-Boot binary at offset 0x10.
+
+config MIPS_BOOT_CONFIG_WORD0
+ hex
+ depends on MIPS_INSERT_BOOT_CONFIG
+ default 0x420 if TARGET_MALTA
+ default 0x0
+ help
+ Value which is inserted as boot config word 0.
+
+config MIPS_BOOT_CONFIG_WORD1
+ hex
+ depends on MIPS_INSERT_BOOT_CONFIG
+ default 0x0
+ help
+ Value which is inserted as boot config word 1.
+
endif
endmenu
machine-$(CONFIG_ARCH_ATH79) += ath79
machine-$(CONFIG_ARCH_BMIPS) += bmips
machine-$(CONFIG_MACH_PIC32) += pic32
+machine-$(CONFIG_ARCH_MT7620) += mt7620
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
libs-y += $(machdirs)
b reset
mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
-#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
+#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
/*
- * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
- * access external NOR flashes. If the board boots from NOR flash the
- * internal BootROM does a blind read at address 0xB0000010 to read the
- * initial configuration for that EBU in order to access the flash
- * device with correct parameters. This config option is board-specific.
+ * Store some board-specific boot configuration. This is used by some
+ * MIPS systems like Malta.
*/
.org 0x10
- .word CONFIG_SYS_XWAY_EBU_BOOTCFG
- .word 0x0
-#endif
-#if defined(CONFIG_MALTA)
- /*
- * Linux expects the Board ID here.
- */
- .org 0x10
- .word 0x00000420 # 0x420 (Malta Board with CoreLV)
- .word 0x00000000
+ .word CONFIG_MIPS_BOOT_CONFIG_WORD0
+ .word CONFIG_MIPS_BOOT_CONFIG_WORD1
#endif
#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
u-boot,dm-pre-reloc;
};
+ gpio_test_port: syscon@14e00294 {
+ compatible = "syscon";
+ reg = <0x14e00294 0x1c>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "brcm,bcm6838-pinctrl";
+ regmap = <&gpio_test_port>;
+ brcm,pins-count = <74>;
+ brcm,functions-count = <8>;
+ };
+
uart0: serial@14e00500 {
compatible = "brcm,bcm6345-uart";
reg = <0x14e00500 0x18>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc";
+ model = "Gardena smart-Gateway-MT7688";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ stdout-path = &uart0;
+ };
+};
+
+&uart0 {
+ status = "okay";
+ clock-frequency = <40000000>;
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+ };
+
+ spi-nand@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <40000000>;
+ reg = <1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "seeed,linkit-smart-7688", "ralink,mt7628a-soc";
+ model = "LinkIt-Smart-7688";
+
+ aliases {
+ serial0 = &uart2;
+ spi0 = &spi0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ stdout-path = &uart2;
+ };
+};
+
+&uart2 {
+ status = "okay";
+ clock-frequency = <40000000>;
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mt7628a-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mti,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ resetc: reset-controller {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@10000000 {
+ compatible = "palmbus", "simple-bus";
+ reg = <0x10000000 0x200000>;
+ ranges = <0x0 0x10000000 0x1FFFFF>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc: system-controller@0 {
+ compatible = "ralink,mt7620a-sysc", "syscon";
+ reg = <0x0 0x100>;
+ };
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&sysc>;
+ offset = <0x34>;
+ mask = <0x1>;
+ };
+
+ intc: interrupt-controller@200 {
+ compatible = "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ resets = <&resetc 9>;
+ reset-names = "intc";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ ralink,intc-registers = <0x9c 0xa0
+ 0x6c 0xa4
+ 0x80 0x78>;
+ };
+
+ memory-controller@300 {
+ compatible = "ralink,mt7620a-memc";
+ reg = <0x300 0x100>;
+ };
+
+ spi0: spi@b00 {
+ compatible = "ralink,mt7621-spi";
+ reg = <0xb00 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-frequency = <200000000>;
+ };
+
+ uart0: uartlite@c00 {
+ compatible = "ns16550a";
+ reg = <0xc00 0x100>;
+
+ resets = <&resetc 12>;
+ reset-names = "uart0";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+
+ reg-shift = <2>;
+ };
+
+ uart1: uart1@d00 {
+ compatible = "ns16550a";
+ reg = <0xd00 0x100>;
+
+ resets = <&resetc 19>;
+ reset-names = "uart1";
+
+ interrupt-parent = <&intc>;
+ interrupts = <21>;
+
+ reg-shift = <2>;
+ };
+
+ uart2: uart2@e00 {
+ compatible = "ns16550a";
+ reg = <0xe00 0x100>;
+
+ resets = <&resetc 20>;
+ reset-names = "uart2";
+
+ interrupt-parent = <&intc>;
+ interrupts = <22>;
+
+ reg-shift = <2>;
+ };
+ };
+
+ usb_phy: usb-phy@10120000 {
+ compatible = "mediatek,mt7628-usbphy";
+ reg = <0x10120000 0x1000>;
+
+ #phy-cells = <0>;
+
+ ralink,sysctl = <&sysc>;
+ resets = <&resetc 22 &resetc 25>;
+ reset-names = "host", "device";
+ };
+
+ ehci@101c0000 {
+ compatible = "generic-ehci";
+ reg = <0x101c0000 0x1000>;
+
+ phys = <&usb_phy>;
+ phy-names = "usb";
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+ };
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _MIPS_ATOMIC_H
+#define _MIPS_ATOMIC_H
+
+#include <asm/system.h>
+#include <asm-generic/atomic.h>
+
+#endif
/* ensure cache ops complete before any further memory accesses */
sync();
}
+
+int dcache_status(void)
+{
+ unsigned int cca = read_c0_config() & CONF_CM_CMASK;
+ return cca != CONF_CM_UNCACHED;
+}
+
+void dcache_enable(void)
+{
+ puts("Not supported!\n");
+}
+
+void dcache_disable(void)
+{
+ /* change CCA to uncached */
+ change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+
+ /* ensure the pipeline doesn't contain now-invalid instructions */
+ instruction_hazard_barrier();
+}
#include <asm/cacheops.h>
#include <asm/cm.h>
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-#endif
-
-#define INDEX_BASE CKSEG0
-
.macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
10:
.set pop
.endm
+
/*
* mips_cache_reset - low level initialisation of the primary caches
*
/*
* Now clear that much memory starting from zero.
*/
- PTR_LI a0, CKSEG1
+ PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
PTR_ADDU a1, a0, v0
2: PTR_ADDIU a0, 64
f_fill64 a0, -64, zero
bnez R_L2_BYPASSED, l1_init
l2_init:
- PTR_LI t0, INDEX_BASE
+ PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
PTR_ADDU t1, t0, R_L2_SIZE
1: cache INDEX_STORE_TAG_SD, 0(t0)
PTR_ADDU t0, t0, R_L2_LINE
* Initialize the I-cache first,
*/
blez R_IC_SIZE, 1f
- PTR_LI t0, INDEX_BASE
+ PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
PTR_ADDU t1, t0, R_IC_SIZE
/* clear tag to invalidate */
cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* fill once, so data field parity is correct */
- PTR_LI t0, INDEX_BASE
+ PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
cache_loop t0, t1, R_IC_LINE, FILL
/* invalidate again - prudent but not strictly neccessary */
- PTR_LI t0, INDEX_BASE
+ PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
#endif
-
- /* Enable use of the I-cache by setting Config.K0 */
sync
- mfc0 t0, CP0_CONFIG
- li t1, CONFIG_SYS_MIPS_CACHE_MODE
-#if __mips_isa_rev >= 2
- ins t0, t1, 0, 3
-#else
- ori t0, t0, CONF_CM_CMASK
- xori t0, t0, CONF_CM_CMASK
+
+ /*
+ * Enable use of the I-cache by setting Config.K0. The code for this
+ * must be executed from KSEG1. Jump from KSEG0 to KSEG1 to do this.
+ * Jump back to KSEG0 after caches are enabled and insert an
+ * instruction hazard barrier.
+ */
+ PTR_LA t0, change_k0_cca
+ li t1, CPHYSADDR(~0)
+ and t0, t0, t1
+ PTR_LI t1, CKSEG1
or t0, t0, t1
-#endif
- mtc0 t0, CP0_CONFIG
+ li a0, CONF_CM_CACHABLE_NONCOHERENT
+ jalr.hb t0
/*
* then initialize D-cache.
*/
1: blez R_DC_SIZE, 3f
- PTR_LI t0, INDEX_BASE
+ PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
PTR_ADDU t1, t0, R_DC_SIZE
/* clear all tags */
cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* load from each line (in cached space) */
- PTR_LI t0, INDEX_BASE
+ PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
2: LONG_L zero, 0(t0)
PTR_ADDU t0, R_DC_LINE
bne t0, t1, 2b
/* clear all tags */
- PTR_LI t0, INDEX_BASE
+ PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
#endif
3:
beqz t0, 2f
/* Change Config.K0 to a coherent CCA */
- mfc0 t0, CP0_CONFIG
- li t1, CONF_CM_CACHABLE_COW
-#if __mips_isa_rev >= 2
- ins t0, t1, 0, 3
-#else
- ori t0, t0, CONF_CM_CMASK
- xori t0, t0, CONF_CM_CMASK
- or t0, t0, t1
-#endif
- mtc0 t0, CP0_CONFIG
+ PTR_LA t0, change_k0_cca
+ li a0, CONF_CM_CACHABLE_COW
+ jalr t0
/*
* Join the coherent domain such that the caches of this core are kept
return:
/* Ensure all cache operations complete before returning */
sync
- jr ra
+ jr R_RETURN
END(mips_cache_reset)
-/*
- * dcache_status - get cache status
- *
- * RETURNS: 0 - cache disabled; 1 - cache enabled
- *
- */
-LEAF(dcache_status)
- mfc0 t0, CP0_CONFIG
- li t1, CONF_CM_UNCACHED
- andi t0, t0, CONF_CM_CMASK
- move v0, zero
- beq t0, t1, 2f
- li v0, 1
-2: jr ra
- END(dcache_status)
-
-/*
- * dcache_disable - disable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_disable)
- mfc0 t0, CP0_CONFIG
- li t1, -8
- and t0, t0, t1
- ori t0, t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
- jr ra
- END(dcache_disable)
+LEAF(change_k0_cca)
+ mfc0 t0, CP0_CONFIG
+#if __mips_isa_rev >= 2
+ ins t0, a0, 0, 3
+#else
+ xor a0, a0, t0
+ andi a0, a0, CONF_CM_CMASK
+ xor a0, a0, t0
+#endif
+ mtc0 a0, CP0_CONFIG
-/*
- * dcache_enable - enable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_enable)
- mfc0 t0, CP0_CONFIG
- ori t0, CONF_CM_CMASK
- xori t0, CONF_CM_CMASK
- ori t0, CONFIG_SYS_MIPS_CACHE_MODE
- mtc0 t0, CP0_CONFIG
- jr ra
- END(dcache_enable)
+ jr.hb ra
+ END(change_k0_cca)
--- /dev/null
+menu "MediaTek MIPS platforms"
+ depends on ARCH_MT7620
+
+config SYS_MALLOC_F_LEN
+ default 0x1000
+
+config SYS_SOC
+ default "mt7620" if SOC_MT7620
+
+choice
+ prompt "MediaTek MIPS SoC select"
+
+config SOC_MT7620
+ bool "MT7620/8"
+ select MIPS_L1_CACHE_SHIFT_5
+ help
+ This supports MediaTek MIPS MT7620 family.
+
+endchoice
+
+choice
+ prompt "Board select"
+
+config BOARD_GARDENA_SMART_GATEWAY_MT7688
+ bool "Gardena Smart Gateway"
+ depends on SOC_MT7620
+ select SUPPORTS_BOOT_RAM
+ help
+ Gardena Smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
+ and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.
+
+config BOARD_LINKIT_SMART_7688
+ bool "LinkIt Smart 7688"
+ depends on SOC_MT7620
+ select SUPPORTS_BOOT_RAM
+ help
+ Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM
+ and 32 MiB of flash (SPI).
+ Between its different peripherals there's an integrated switch with 4
+ ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
+ a MT7688 (PCIe).
+
+endchoice
+
+choice
+ prompt "Boot mode"
+
+config BOOT_RAM
+ bool "RAM boot"
+ depends on SUPPORTS_BOOT_RAM
+ help
+ This builds an image that is linked to a RAM address. It can be used
+ for booting from CFE via TFTP using an ELF image, but it can also be
+ booted from RAM by other bootloaders using a BIN image.
+
+config BOOT_ROM
+ bool "ROM boot"
+ depends on SUPPORTS_BOOT_RAM
+ help
+ This builds an image that is linked to a ROM address. It can be
+ used as main bootloader image which is programmed onto the onboard
+ flash storage (SPI NOR).
+
+endchoice
+
+choice
+ prompt "DDR2 size"
+
+config ONBOARD_DDR2_SIZE_256MBIT
+ bool "256MBit (32MByte) total size"
+ depends on BOOT_ROM
+ help
+ Use 256MBit (32MByte) of DDR total size
+
+config ONBOARD_DDR2_SIZE_512MBIT
+ bool "512MBit (64MByte) total size"
+ depends on BOOT_ROM
+ help
+ Use 512MBit (64MByte) of DDR total size
+
+config ONBOARD_DDR2_SIZE_1024MBIT
+ bool "1024MBit (128MByte) total size"
+ depends on BOOT_ROM
+ help
+ Use 1024MBit (128MByte) of DDR total size
+
+config ONBOARD_DDR2_SIZE_2048MBIT
+ bool "2048MBit (256MByte) total size"
+ depends on BOOT_ROM
+ help
+ Use 2048MBit (256MByte) of DDR total size
+
+endchoice
+
+choice
+ prompt "DDR2 chip width"
+
+config ONBOARD_DDR2_CHIP_WIDTH_8BIT
+ bool "8bit DDR chip width"
+ depends on BOOT_ROM
+ help
+ Use DDR chips with 8bit width
+
+config ONBOARD_DDR2_CHIP_WIDTH_16BIT
+ bool "16bit DDR chip width"
+ depends on BOOT_ROM
+ help
+ Use DDR chips with 16bit width
+
+endchoice
+
+choice
+ prompt "DDR2 bus width"
+
+config ONBOARD_DDR2_BUS_WIDTH_16BIT
+ bool "16bit DDR bus width"
+ depends on BOOT_ROM
+ help
+ Use 16bit DDR bus width
+
+config ONBOARD_DDR2_BUS_WIDTH_32BIT
+ bool "32bit DDR bus width"
+ depends on BOOT_ROM
+ help
+ Use 32bit DDR bus width
+
+endchoice
+
+config SUPPORTS_BOOT_RAM
+ bool
+
+source "board/gardena/smart-gateway-mt7688/Kconfig"
+source "board/seeed/linkit-smart-7688/Kconfig"
+
+endmenu
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += cpu.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+obj-y += ddr_calibrate.o
+obj-y += lowlevel_init.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include "mt76xx.h"
+
+#define STR_LEN 6
+
+#ifdef CONFIG_BOOT_ROM
+int mach_cpu_init(void)
+{
+ ddr_calibrate();
+
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)",
+ "PLL (4-Byte SPI Addr)",
+ "XTAL (3-Byte SPI Addr)",
+ "XTAL (4-Byte SPI Addr)" };
+ const void *blob = gd->fdt_blob;
+ void __iomem *sysc_base;
+ char buf[STR_LEN + 1];
+ fdt_addr_t base;
+ fdt_size_t size;
+ char *str;
+ int node;
+ u32 val;
+
+ /* Get system controller base address */
+ node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc");
+ if (node < 0)
+ return -FDT_ERR_NOTFOUND;
+
+ base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg",
+ 0, &size, true);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ sysc_base = ioremap_nocache(base, size);
+
+ str = (char *)sysc_base + MT76XX_CHIPID_OFFS;
+ snprintf(buf, STR_LEN + 1, "%s", str);
+ val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS);
+ printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf,
+ (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0));
+
+ val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1;
+ printf("Boot from %s\n", boot_str[val]);
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ *
+ * This code is mostly based on the code extracted from this MediaTek
+ * github repository:
+ *
+ * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
+ *
+ * I was not able to find a specific license or other developers
+ * copyrights here, so I can't add them here.
+ *
+ * Most functions in this file are copied from the MediaTek U-Boot
+ * repository. Without any documentation, it was impossible to really
+ * implement this differently. So its mostly a cleaned-up version of
+ * the original code, with only support for the MT7628 / MT7688 SoC.
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <asm/cacheops.h>
+#include <asm/io.h>
+#include "mt76xx.h"
+
+#define NUM_OF_CACHELINE 128
+#define MIN_START 6
+#define MIN_FINE_START 0xf
+#define MAX_START 7
+#define MAX_FINE_START 0x0
+
+#define CPU_FRAC_DIV 1
+
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
+#define DRAM_BUTTOM 0x02000000
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
+#define DRAM_BUTTOM 0x04000000
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
+#define DRAM_BUTTOM 0x08000000
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
+#define DRAM_BUTTOM 0x10000000
+#endif
+
+static inline void cal_memcpy(void *src, void *dst, u32 size)
+{
+ u8 *psrc = (u8 *)src;
+ u8 *pdst = (u8 *)dst;
+ int i;
+
+ for (i = 0; i < size; i++, psrc++, pdst++)
+ *pdst = *psrc;
+}
+
+static inline void cal_memset(void *src, u8 pat, u32 size)
+{
+ u8 *psrc = (u8 *)src;
+ int i;
+
+ for (i = 0; i < size; i++, psrc++)
+ *psrc = pat;
+}
+
+#define pref_op(hint, addr) \
+ __asm__ __volatile__( \
+ ".set push\n" \
+ ".set noreorder\n" \
+ "pref %0, %1\n" \
+ ".set pop\n" \
+ : \
+ : "i" (hint), "R" (*(u8 *)(addr)))
+
+static inline void cal_patgen(u32 start_addr, u32 size, u32 bias)
+{
+ u32 *addr = (u32 *)start_addr;
+ int i;
+
+ for (i = 0; i < size; i++)
+ addr[i] = start_addr + i + bias;
+}
+
+static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs,
+ u32 offs, u32 pat, u32 val)
+{
+ u32 nc_addr;
+ u32 *c_addr;
+ int i;
+
+ for (nc_addr = 0xa0000000;
+ nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32);
+ nc_addr += (DRAM_BUTTOM >> 6) + offs) {
+ writel(0x00007474, (void *)MT76XX_MEMCTRL_BASE + 0x64);
+ wmb(); /* Make sure store if finished */
+
+ c_addr = (u32 *)(nc_addr & 0xdfffffff);
+ cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32);
+ cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat);
+
+ if (dqs > 0)
+ writel(0x00000074 |
+ (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) |
+ (((k == 0) ? val : test_dqs) << 8),
+ (void *)MT76XX_MEMCTRL_BASE + 0x64);
+ else
+ writel(0x00007400 |
+ (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) |
+ (((k == 0) ? val : test_dqs) << 0),
+ (void *)MT76XX_MEMCTRL_BASE + 0x64);
+ wmb(); /* Make sure store if finished */
+
+ invalidate_dcache_range((u32)c_addr,
+ (u32)c_addr +
+ NUM_OF_CACHELINE * 32);
+ wmb(); /* Make sure store if finished */
+
+ for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
+ if (i % 8 == 0)
+ pref_op(0, &c_addr[i]);
+ }
+
+ for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
+ if (c_addr[i] != nc_addr + i + pat)
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+void ddr_calibrate(void)
+{
+ u32 min_coarse_dqs[2];
+ u32 max_coarse_dqs[2];
+ u32 min_fine_dqs[2];
+ u32 max_fine_dqs[2];
+ u32 coarse_dqs[2];
+ u32 fine_dqs[2];
+ int reg = 0, ddr_cfg2_reg;
+ int flag;
+ int i, k;
+ int dqs = 0;
+ u32 min_coarse_dqs_bnd, min_fine_dqs_bnd, coarse_dqs_dll, fine_dqs_dll;
+ u32 val;
+ u32 fdiv = 0, frac = 0;
+
+ /* Setup clock to run at full speed */
+ val = readl((void *)MT76XX_DYN_CFG0_REG);
+ fdiv = (u32)((val >> 8) & 0x0F);
+ if (CPU_FRAC_DIV < 1 || CPU_FRAC_DIV > 10)
+ frac = val & 0x0f;
+ else
+ frac = CPU_FRAC_DIV;
+
+ while (frac < fdiv) {
+ val = readl((void *)MT76XX_DYN_CFG0_REG);
+ fdiv = (val >> 8) & 0x0f;
+ fdiv--;
+ val &= ~(0x0f << 8);
+ val |= (fdiv << 8);
+ writel(val, (void *)MT76XX_DYN_CFG0_REG);
+ udelay(500);
+ val = readl((void *)MT76XX_DYN_CFG0_REG);
+ fdiv = (val >> 8) & 0x0f;
+ }
+
+ clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
+ ddr_cfg2_reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x48);
+ clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x48,
+ (0x3 << 28) | (0x3 << 26));
+
+ min_coarse_dqs[0] = MIN_START;
+ min_coarse_dqs[1] = MIN_START;
+ min_fine_dqs[0] = MIN_FINE_START;
+ min_fine_dqs[1] = MIN_FINE_START;
+ max_coarse_dqs[0] = MAX_START;
+ max_coarse_dqs[1] = MAX_START;
+ max_fine_dqs[0] = MAX_FINE_START;
+ max_fine_dqs[1] = MAX_FINE_START;
+ dqs = 0;
+
+ /* Add by KP, DQS MIN boundary */
+ reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x20);
+ coarse_dqs_dll = (reg & 0xf00) >> 8;
+ fine_dqs_dll = (reg & 0xf0) >> 4;
+ if (coarse_dqs_dll <= 8)
+ min_coarse_dqs_bnd = 8 - coarse_dqs_dll;
+ else
+ min_coarse_dqs_bnd = 0;
+
+ if (fine_dqs_dll <= 8)
+ min_fine_dqs_bnd = 8 - fine_dqs_dll;
+ else
+ min_fine_dqs_bnd = 0;
+ /* DQS MIN boundary */
+
+DQS_CAL:
+
+ for (k = 0; k < 2; k++) {
+ u32 test_dqs;
+
+ if (k == 0)
+ test_dqs = MAX_START;
+ else
+ test_dqs = MAX_FINE_START;
+
+ do {
+ flag = test_loop(k, dqs, test_dqs, max_coarse_dqs,
+ 0x400, 0x3, 0xf);
+ if (flag == -1)
+ break;
+
+ test_dqs++;
+ } while (test_dqs <= 0xf);
+
+ if (k == 0) {
+ max_coarse_dqs[dqs] = test_dqs;
+ } else {
+ test_dqs--;
+
+ if (test_dqs == MAX_FINE_START - 1) {
+ max_coarse_dqs[dqs]--;
+ max_fine_dqs[dqs] = 0xf;
+ } else {
+ max_fine_dqs[dqs] = test_dqs;
+ }
+ }
+ }
+
+ for (k = 0; k < 2; k++) {
+ u32 test_dqs;
+
+ if (k == 0)
+ test_dqs = MIN_START;
+ else
+ test_dqs = MIN_FINE_START;
+
+ do {
+ flag = test_loop(k, dqs, test_dqs, min_coarse_dqs,
+ 0x480, 0x1, 0x0);
+ if (k == 0) {
+ if (flag == -1 ||
+ test_dqs == min_coarse_dqs_bnd)
+ break;
+
+ test_dqs--;
+
+ if (test_dqs < min_coarse_dqs_bnd)
+ break;
+ } else {
+ if (flag == -1) {
+ test_dqs++;
+ break;
+ } else if (test_dqs == min_fine_dqs_bnd) {
+ break;
+ }
+
+ test_dqs--;
+
+ if (test_dqs < min_fine_dqs_bnd)
+ break;
+ }
+ } while (test_dqs >= 0);
+
+ if (k == 0) {
+ min_coarse_dqs[dqs] = test_dqs;
+ } else {
+ if (test_dqs == MIN_FINE_START + 1) {
+ min_coarse_dqs[dqs]++;
+ min_fine_dqs[dqs] = 0x0;
+ } else {
+ min_fine_dqs[dqs] = test_dqs;
+ }
+ }
+ }
+
+ if (dqs == 0) {
+ dqs = 1;
+ goto DQS_CAL;
+ }
+
+ for (i = 0; i < 2; i++) {
+ u32 temp;
+
+ coarse_dqs[i] = (max_coarse_dqs[i] + min_coarse_dqs[i]) >> 1;
+ temp =
+ (((max_coarse_dqs[i] + min_coarse_dqs[i]) % 2) * 4) +
+ ((max_fine_dqs[i] + min_fine_dqs[i]) >> 1);
+ if (temp >= 0x10) {
+ coarse_dqs[i]++;
+ fine_dqs[i] = (temp - 0x10) + 0x8;
+ } else {
+ fine_dqs[i] = temp;
+ }
+ }
+ reg = (coarse_dqs[1] << 12) | (fine_dqs[1] << 8) |
+ (coarse_dqs[0] << 4) | fine_dqs[0];
+
+ clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
+ writel(reg, (void *)MT76XX_MEMCTRL_BASE + 0x64);
+ writel(ddr_cfg2_reg, (void *)MT76XX_MEMCTRL_BASE + 0x48);
+ setbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
+
+ for (i = 0; i < 2; i++)
+ debug("[%02X%02X%02X%02X]", min_coarse_dqs[i],
+ min_fine_dqs[i], max_coarse_dqs[i], max_fine_dqs[i]);
+ debug("\nDDR Calibration DQS reg = %08X\n", reg);
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) 2018 Stefan Roese <sr@denx.de>
+ *
+ * This code is mostly based on the code extracted from this MediaTek
+ * github repository:
+ *
+ * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
+ *
+ * I was not able to find a specific license or other developers
+ * copyrights here, so I can't add them here.
+ */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include "mt76xx.h"
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define DELAY_USEC(us) ((us) / 100)
+
+#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
+#define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12)
+
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
+#define DDR_CFG1_SIZE_VAL 0x222e2323
+#define DDR_CFG4_SIZE_VAL 7
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
+#define DDR_CFG1_SIZE_VAL 0x22322323
+#define DDR_CFG4_SIZE_VAL 9
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
+#define DDR_CFG1_SIZE_VAL 0x22362323
+#define DDR_CFG4_SIZE_VAL 9
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
+#define DDR_CFG1_SIZE_VAL 0x223a2323
+#define DDR_CFG4_SIZE_VAL 9
+#endif
+
+#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT)
+#define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16)
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT)
+#define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16)
+#endif
+
+#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT)
+#define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12)
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT)
+#define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12)
+#endif
+
+ .set noreorder
+
+LEAF(lowlevel_init)
+
+ /* Load base addresses as physical addresses for later usage */
+ li s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE)
+ li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)
+ li s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE)
+
+ /* polling CPLL is ready */
+ li t1, DELAY_USEC(1000000)
+ la t5, MT76XX_ROM_STATUS_REG
+1:
+ lw t2, 0(t5)
+ andi t2, t2, 0x1
+ bnez t2, CPLL_READY
+ subu t1, t1, 1
+ bgtz t1, 1b
+ nop
+ la t0, MT76XX_CLKCFG0_REG
+ lw t3, 0(t0)
+ ori t3, t3, 0x1
+ sw t3, 0(t0)
+ b CPLL_DONE
+ nop
+CPLL_READY:
+ la t0, MT76XX_CLKCFG0_REG
+ lw t1, 0(t0)
+ li t2, ~0x0c
+ and t1, t1, t2
+ ori t1, t1, 0xc
+ sw t1, 0(t0)
+ la t0, MT76XX_DYN_CFG0_REG
+ lw t3, 0(t0)
+ li t5, ~((0x0f << 8) | (0x0f << 0))
+ and t3, t3, t5
+ li t5, (10 << 8) | (1 << 0)
+ or t3, t3, t5
+ sw t3, 0(t0)
+ la t0, MT76XX_CLKCFG0_REG
+ lw t3, 0(t0)
+ li t4, ~0x0F
+ and t3, t3, t4
+ ori t3, t3, 0xc
+ sw t3, 0(t0)
+ lw t3, 0(t0)
+ ori t3, t3, 0x08
+ sw t3, 0(t0)
+
+CPLL_DONE:
+ /*
+ * SDR and DDR initialization: delay 200us
+ */
+ li t0, DELAY_USEC(200 + 40)
+ li t1, 0x1
+1:
+ sub t0, t0, t1
+ bnez t0, 1b
+ nop
+
+ /* set DRAM IO PAD for MT7628IC */
+ /* DDR LDO Enable */
+ lw t4, 0x100(s2)
+ li t2, BIT(31)
+ or t4, t4, t2
+ sw t4, 0x100(s2)
+ lw t4, 0x10c(s2)
+ j LDO_1P8V
+ nop
+LDO_1P8V:
+ li t2, ~BIT(6)
+ and t4, t4, t2
+ sw t4, 0x10c(s2)
+ j DDRLDO_SOFT_START
+LDO_2P5V:
+ /* suppose external DDR1 LDO 2.5V */
+ li t2, BIT(6)
+ or t4, t4, t2
+ sw t4, 0x10c(s2)
+
+DDRLDO_SOFT_START:
+ lw t2, 0x10c(s2)
+ li t3, BIT(16)
+ or t2, t2, t3
+ sw t2, 0x10c(s2)
+ li t3, DELAY_USEC(250*50)
+LDO_DELAY:
+ subu t3, t3, 1
+ bnez t3, LDO_DELAY
+ nop
+
+ lw t2, 0x10c(s2)
+ li t3, BIT(18)
+ or t2, t2, t3
+ sw t2, 0x10c(s2)
+
+SET_RG_BUCK_FPWM:
+ lw t2, 0x104(s2)
+ ori t2, t2, BIT(10)
+ sw t2, 0x104(s2)
+
+DDR_PAD_CFG:
+ /* clean CLK PAD */
+ lw t2, 0x704(s2)
+ li t8, 0xfffff0f0
+ and t2, t2, t8
+ /* clean CMD PAD */
+ lw t3, 0x70c(s2)
+ li t8, 0xfffff0f0
+ and t3, t3, t8
+ /* clean DQ IPAD */
+ lw t4, 0x710(s2)
+ li t8, 0xfffff8ff
+ and t4, t4, t8
+ /* clean DQ OPAD */
+ lw t5, 0x714(s2)
+ li t8, 0xfffff0f0
+ and t5, t5, t8
+ /* clean DQS IPAD */
+ lw t6, 0x718(s2)
+ li t8, 0xfffff8ff
+ and t6, t6, t8
+ /* clean DQS OPAD */
+ lw t7, 0x71c(s2)
+ li t8, 0xfffff0f0
+ and t7, t7, t8
+
+ lw t9, 0xc(s0)
+ srl t9, t9, 16
+ andi t9, t9, 0x1
+ bnez t9, MT7628_AN_DDR1_PAD
+MT7628_KN_PAD:
+ li t8, 0x00000303
+ or t2, t2, t8
+ or t3, t3, t8
+ or t5, t5, t8
+ or t7, t7, t8
+ li t8, 0x00000000
+ or t4, t4, t8
+ or t6, t6, t8
+ j SET_PAD_CFG
+MT7628_AN_DDR1_PAD:
+ lw t1, 0x10(s0)
+ andi t1, t1, 0x1
+ beqz t1, MT7628_AN_DDR2_PAD
+ li t8, 0x00000c0c
+ or t2, t2, t8
+ li t8, 0x00000202
+ or t3, t3, t8
+ li t8, 0x00000707
+ or t5, t5, t8
+ li t8, 0x00000c0c
+ or t7, t7, t8
+ li t8, 0x00000000
+ or t4, t4, t8
+ or t6, t6, t8
+ j SET_PAD_CFG
+MT7628_AN_DDR2_PAD:
+ li t8, 0x00000c0c
+ or t2, t2, t8
+ li t8, 0x00000202
+ or t3, t3, t8
+ li t8, 0x00000404
+ or t5, t5, t8
+ li t8, 0x00000c0c
+ or t7, t7, t8
+ li t8, 0x00000000 /* ODT off */
+ or t4, t4, t8
+ or t6, t6, t8
+
+SET_PAD_CFG:
+ sw t2, 0x704(s2)
+ sw t3, 0x70c(s2)
+ sw t4, 0x710(s2)
+ sw t5, 0x714(s2)
+ sw t6, 0x718(s2)
+ sw t7, 0x71c(s2)
+
+ /*
+ * DDR initialization: reset pin to 0
+ */
+ lw t2, 0x34(s0)
+ and t2, ~BIT(10)
+ sw t2, 0x34(s0)
+ nop
+
+ /*
+ * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
+ */
+DDR_READY:
+ li t1, DDR_CFG1_REG
+ lw t0, 0(t1)
+ nop
+ and t2, t0, BIT(21)
+ beqz t2, DDR_READY
+ nop
+
+ /*
+ * DDR initialization
+ *
+ * Only DDR2 supported right now. DDR2 support can be added, once
+ * boards using it will get added to mainline U-Boot.
+ */
+ li t1, DDR_CFG2_REG
+ lw t0, 0(t1)
+ nop
+ and t0, ~BIT(30)
+ and t0, ~(7 << 4)
+ or t0, (4 << 4)
+ or t0, BIT(30)
+ or t0, BIT(11)
+ sw t0, 0(t1)
+ nop
+
+ li t1, DDR_CFG3_REG
+ lw t2, 0(t1)
+ /* Disable ODT; reference board ok, ev board fail */
+ and t2, ~BIT(6)
+ or t2, BIT(2)
+ li t0, DDR_CFG4_REG
+ lw t1, 0(t0)
+ li t2, ~(0x01f | 0x0f0)
+ and t1, t1, t2
+ ori t1, t1, DDR_CFG4_SIZE_VAL
+ sw t1, 0(t0)
+ nop
+
+ /*
+ * DDR initialization: config size and width on reg DDR_CFG1
+ */
+ li t6, DDR_CFG1_SIZE_VAL
+
+ and t6, ~DDR_CFG1_CHIP_WIDTH_MASK
+ or t6, DDR_CFG1_CHIP_WIDTH_VAL
+
+ /* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
+ and t6, ~DDR_CFG1_BUS_WIDTH_MASK
+ or t6, DDR_CFG1_BUS_WIDTH_VAL
+
+ li t5, DDR_CFG1_REG
+ sw t6, 0(t5)
+ nop
+
+ /*
+ * DDR: enable self auto refresh for power saving
+ * enable it by default for both RAM and ROM version (for CoC)
+ */
+ lw t1, 0x14(s1)
+ nop
+ and t1, 0xff000000
+ or t1, 0x01
+ sw t1, 0x14(s1)
+ nop
+ lw t1, 0x10(s1)
+ nop
+ or t1, 0x10
+ sw t1, 0x10(s1)
+ nop
+
+ jr ra
+ nop
+ END(lowlevel_init)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __MT76XX_H
+#define __MT76XX_H
+
+#define MT76XX_SYSCTL_BASE 0x10000000
+
+#define MT76XX_CHIPID_OFFS 0x00
+#define MT76XX_CHIP_REV_ID_OFFS 0x0c
+#define MT76XX_SYSCFG0_OFFS 0x10
+
+#define MT76XX_MEMCTRL_BASE (MT76XX_SYSCTL_BASE + 0x0300)
+#define MT76XX_RGCTRL_BASE (MT76XX_SYSCTL_BASE + 0x1000)
+
+#define MT76XX_ROM_STATUS_REG (MT76XX_SYSCTL_BASE + 0x0028)
+#define MT76XX_CLKCFG0_REG (MT76XX_SYSCTL_BASE + 0x002c)
+#define MT76XX_DYN_CFG0_REG (MT76XX_SYSCTL_BASE + 0x0440)
+
+#define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44)
+#define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48)
+#define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c)
+#define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50)
+
+#ifndef __ASSEMBLY__
+/* Prototypes */
+void ddr_calibrate(void);
+#endif
+
+#endif
CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \
-T $(srctree)/examples/standalone/nds32.lds
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax
+PLATFORM_RELFLAGS += -fno-common -mrelax
PLATFORM_RELFLAGS += -gdwarf-2
PLATFORM_CPPFLAGS += -D__nds32__ -G0 -ffixed-10 -fpie
select CREATE_ARCH_SYMLINK
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
+ select BINMAN
imply CMD_HASH
imply CMD_IRQ
imply USB_EHCI_HCD if USB
imply CMD_REGINFO
imply FSL_SATA
+config MPC85XX_HAVE_RESET_VECTOR
+ bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
+ depends on MPC85xx
+
config BOOKE
bool
default y
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
+ _end = .;
.bootpg ADDR(.text) - 0x1000 :
{
. = ALIGN(8);
__init_begin = .;
__init_end = .;
+ _end = .;
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
. = ALIGN(8);
__init_begin = .;
__init_end = .;
+ _end = .;
#ifdef CONFIG_SPL_SKIP_RELOCATE
. = ALIGN(4);
__bss_start = .;
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
+ _end = .;
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
.bootpg ADDR(.text) - 0x1000 :
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e6500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2018 NXP
+ */
+
+/ {
+ cpus {
+ power-isa-version = "2.06";
+ power-isa-b; // Base
+ power-isa-e; // Embedded
+ power-isa-atb; // Alternate Time Base
+ power-isa-cs; // Cache Specification
+ power-isa-ds; // Decorated Storage
+ power-isa-e.ed; // Embedded.Enhanced Debug
+ power-isa-e.pd; // Embedded.External PID
+ power-isa-e.hv; // Embedded.Hypervisor
+ power-isa-e.le; // Embedded.Little-Endian
+ power-isa-e.pm; // Embedded.Performance Monitor
+ power-isa-e.pc; // Embedded.Processor Control
+ power-isa-ecl; // Embedded Cache Locking
+ power-isa-exp; // External Proxy
+ power-isa-fp; // Floating Point
+ power-isa-fp.r; // Floating Point.Record
+ power-isa-mmc; // Memory Coherence
+ power-isa-scpm; // Store Conditional Page Mobility
+ power-isa-wt; // Wait
+ power-isa-64; // 64-bit
+ power-isa-e.pt; // Embedded.Page Table
+ power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT
+ power-isa-e.em; // Embedded Multi-Threading
+ power-isa-v; // Vector (AltiVec)
+ fsl,eref-er; // Enhanced Reservations
+ fsl,eref-deo; // Data Cache Extended Operations
+ mmu-type = "power-embedded";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T2080/T2081 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2018 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e6500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e6500@0 {
+ device_type = "cpu";
+ reg = <0 1>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu1: PowerPC,e6500@2 {
+ device_type = "cpu";
+ reg = <2 3>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu2: PowerPC,e6500@4 {
+ device_type = "cpu";
+ reg = <4 5>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ cpu3: PowerPC,e6500@6 {
+ device_type = "cpu";
+ reg = <6 7>;
+ fsl,portid-mapping = <0x80000000>;
+ };
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2018 NXP
+ */
+
+/include/ "t2080.dtsi"
+
+/ {
+ model = "fsl,T2080QDS";
+ compatible = "fsl,T2080QDS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <config.h>
+
+/ {
+ binman {
+ filename = "u-boot-with-dtb.bin";
+ skip-at-start = <CONFIG_SYS_TEXT_BASE>;
+ sort-by-offset;
+ pad-byte = <0xff>;
+ size = <CONFIG_SYS_MONITOR_LEN>;
+
+ u-boot-with-ucode-ptr {
+ offset = <CONFIG_SYS_TEXT_BASE>;
+ optional-ucode;
+ };
+
+ u-boot-dtb-with-ucode {
+#ifdef CONFIG_MPC85xx
+ align = <256>;
+#endif
+ };
+#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR
+ powerpc-mpc85xx-bootpg-resetvec {
+ offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+ };
+#endif
+ };
+};
-T $(srctree)/examples/standalone/riscv.lds
PLATFORM_CPPFLAGS += -ffixed-gp -fpic
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2 -ffunction-sections
+PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections
LDFLAGS_u-boot += --gc-sections -static -pie
EFI_CRT0 := crt0_riscv_efi.o
return 0;
}
+/**
+ * is_in_sandbox_mem() - Checks if a pointer is within sandbox's emulated DRAM
+ *
+ * This provides a way to check if a pointer is owned by sandbox (and is within
+ * its RAM) or not. Sometimes pointers come from a test which conceptually runs
+ * output sandbox, potentially with direct access to the C-library malloc()
+ * function, or the sandbox stack (which is not actually within the emulated
+ * DRAM.
+ *
+ * Such pointers obviously cannot be mapped into sandbox's DRAM, so we must
+ * detect them an process them separately, by recording a mapping to a tag,
+ * which we can use to map back to the pointer later.
+ *
+ * @ptr: Pointer to check
+ * @return true if this is within sandbox emulated DRAM, false if not
+ */
+static bool is_in_sandbox_mem(const void *ptr)
+{
+ return (const uint8_t *)ptr >= gd->arch.ram_buf &&
+ (const uint8_t *)ptr < gd->arch.ram_buf + gd->ram_size;
+}
+
+/**
+ * phys_to_virt() - Converts a sandbox RAM address to a pointer
+ *
+ * Sandbox uses U-Boot addresses from 0 to the size of DRAM. These index into
+ * the emulated DRAM buffer used by sandbox. This function converts such an
+ * address to a pointer into this buffer, which can be used to access the
+ * memory.
+ *
+ * If the address is outside this range, it is assumed to be a tag
+ */
void *phys_to_virt(phys_addr_t paddr)
{
- return (void *)(gd->arch.ram_buf + paddr);
+ struct sandbox_mapmem_entry *mentry;
+ struct sandbox_state *state;
+
+ /* If the address is within emulated DRAM, calculate the value */
+ if (paddr < gd->ram_size)
+ return (void *)(gd->arch.ram_buf + paddr);
+
+ /*
+ * Otherwise search out list of tags for the correct pointer previously
+ * created by map_to_sysmem()
+ */
+ state = state_get_current();
+ list_for_each_entry(mentry, &state->mapmem_head, sibling_node) {
+ if (mentry->tag == paddr) {
+ printf("%s: Used map from %lx to %p\n", __func__,
+ (ulong)paddr, mentry->ptr);
+ return mentry->ptr;
+ }
+ }
+
+ printf("%s: Cannot map sandbox address %lx (SDRAM from 0 to %lx)\n",
+ __func__, (ulong)paddr, (ulong)gd->ram_size);
+ os_abort();
+
+ /* Not reached */
+ return NULL;
+}
+
+struct sandbox_mapmem_entry *find_tag(const void *ptr)
+{
+ struct sandbox_mapmem_entry *mentry;
+ struct sandbox_state *state = state_get_current();
+
+ list_for_each_entry(mentry, &state->mapmem_head, sibling_node) {
+ if (mentry->ptr == ptr) {
+ debug("%s: Used map from %p to %lx\n", __func__, ptr,
+ mentry->tag);
+ return mentry;
+ }
+ }
+ return NULL;
}
-phys_addr_t virt_to_phys(void *vaddr)
+phys_addr_t virt_to_phys(void *ptr)
{
- return (phys_addr_t)((uint8_t *)vaddr - gd->arch.ram_buf);
+ struct sandbox_mapmem_entry *mentry;
+
+ /*
+ * If it is in emulated RAM, don't bother looking for a tag. Just
+ * calculate the pointer using the provides offset into the RAM buffer.
+ */
+ if (is_in_sandbox_mem(ptr))
+ return (phys_addr_t)((uint8_t *)ptr - gd->arch.ram_buf);
+
+ mentry = find_tag(ptr);
+ if (!mentry) {
+ /* Abort so that gdb can be used here */
+ printf("%s: Cannot map sandbox address %p (SDRAM from 0 to %lx)\n",
+ __func__, ptr, (ulong)gd->ram_size);
+ os_abort();
+ }
+ printf("%s: Used map from %p to %lx\n", __func__, ptr, mentry->tag);
+
+ return mentry->tag;
}
void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
return phys_to_virt(paddr);
}
-void unmap_physmem(const void *vaddr, unsigned long flags)
+void unmap_physmem(const void *ptr, unsigned long flags)
{
#ifdef CONFIG_PCI
if (map_dev) {
- pci_unmap_physmem(vaddr, map_len, map_dev);
+ pci_unmap_physmem(ptr, map_len, map_dev);
map_dev = NULL;
}
#endif
}
-void sandbox_set_enable_pci_map(int enable)
+phys_addr_t map_to_sysmem(const void *ptr)
{
- enable_pci_map = enable;
+ struct sandbox_mapmem_entry *mentry;
+
+ /*
+ * If it is in emulated RAM, don't bother creating a tag. Just return
+ * the offset into the RAM buffer.
+ */
+ if (is_in_sandbox_mem(ptr))
+ return (u8 *)ptr - gd->arch.ram_buf;
+
+ /*
+ * See if there is an existing tag with this pointer. If not, set up a
+ * new one.
+ */
+ mentry = find_tag(ptr);
+ if (!mentry) {
+ struct sandbox_state *state = state_get_current();
+
+ mentry = malloc(sizeof(*mentry));
+ if (!mentry) {
+ printf("%s: Error: Out of memory\n", __func__);
+ os_exit(ENOMEM);
+ }
+ mentry->tag = state->next_tag++;
+ mentry->ptr = (void *)ptr;
+ list_add_tail(&mentry->sibling_node, &state->mapmem_head);
+ debug("%s: Added map from %p to %lx\n", __func__, ptr,
+ (ulong)mentry->tag);
+ }
+
+ /*
+ * Return the tag as the address to use. A later call to map_sysmem()
+ * will return ptr
+ */
+ return mentry->tag;
}
-phys_addr_t map_to_sysmem(const void *ptr)
+void sandbox_set_enable_pci_map(int enable)
{
- return (u8 *)ptr - gd->arch.ram_buf;
+ enable_pci_map = enable;
}
void flush_dcache_range(unsigned long start, unsigned long stop)
return (count - base_count) / 1000;
}
-
-int setjmp(jmp_buf jmp)
-{
- return os_setjmp((ulong *)jmp, sizeof(*jmp));
-}
-
-void longjmp(jmp_buf jmp, int ret)
-{
- os_longjmp((ulong *)jmp, ret);
- while (1)
- ;
-}
void *os_malloc(size_t length)
{
struct os_mem_hdr *hdr;
+ int page_size = getpagesize();
- hdr = mmap(NULL, length + sizeof(*hdr), PROT_READ | PROT_WRITE,
+ hdr = mmap(NULL, length + page_size,
+ PROT_READ | PROT_WRITE | PROT_EXEC,
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
if (hdr == MAP_FAILED)
return NULL;
hdr->length = length;
- return hdr + 1;
+ return (void *)hdr + page_size;
}
void os_free(void *ptr)
rt->tm_isdst = tm->tm_isdst;
}
-int os_setjmp(ulong *jmp, int size)
+void os_abort(void)
{
- jmp_buf dummy;
-
- /*
- * We cannot rely on the struct name that jmp_buf uses, so use a
- * local variable here
- */
- if (size < sizeof(dummy)) {
- printf("setjmp: jmpbuf is too small (%d bytes, need %d)\n",
- size, sizeof(jmp_buf));
- return -ENOSPC;
- }
-
- return setjmp((struct __jmp_buf_tag *)jmp);
-}
-
-void os_longjmp(ulong *jmp, int ret)
-{
- longjmp((struct __jmp_buf_tag *)jmp, ret);
+ abort();
}
memset(&state->wdt, '\0', sizeof(state->wdt));
memset(state->spi, '\0', sizeof(state->spi));
+
+ /*
+ * Set up the memory tag list. Use the top of emulated SDRAM for the
+ * first tag number, since that address offset is outside the legal
+ * range, and can be assumed to be a tag.
+ */
+ INIT_LIST_HEAD(&state->mapmem_head);
+ state->next_tag = state->ram_size;
}
int state_init(void)
pinctrl {
compatible = "sandbox,pinctrl";
+ status = "okay";
pinctrl_i2c0: i2c0 {
groups = "i2c";
groups = "serial_a";
function = "serial";
};
+
+ pinctrl_onewire0: onewire0 {
+ groups = "w1";
+ function = "w1";
+ bias-pull-up;
+ };
};
reset@1 {
reg = <0x0 0x400>;
};
};
+
+ onewire0: onewire {
+ compatible = "w1-gpio";
+ gpios = <&gpio_a 8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_onewire0>;
+ status = "okay";
+
+ sandbox_eeprom0: sandbox_eeprom@0 {
+ compatible = "sandbox,w1-eeprom";
+ status = "okay";
+ };
+ };
};
#include "cros-ec-keyboard.dtsi"
usb1 = &usb_1;
usb2 = &usb_2;
axi0 = &axi;
+ osd0 = "/osd";
};
a-test {
fake-host-hwaddr = [00 00 66 44 22 22];
};
+ firmware {
+ sandbox_firmware: sandbox-firmware {
+ compatible = "sandbox,firmware";
+ };
+ };
+
gpio_a: base-gpios {
compatible = "sandbox,gpio";
gpio-controller;
};
};
};
+
+ osd {
+ compatible = "sandbox,sandbox_osd";
+ };
+
+ board {
+ compatible = "sandbox,board_sandbox";
+ };
};
#include "sandbox_pmic.dtsi"
typedef struct jmp_buf_data jmp_buf[1];
+/*
+ * We have to directly link with the system versions of
+ * setjmp/longjmp, because setjmp must not return as otherwise
+ * the stack may become invalid.
+ */
int setjmp(jmp_buf jmp);
__noreturn void longjmp(jmp_buf jmp, int ret);
#include <config.h>
#include <sysreset.h>
#include <stdbool.h>
+#include <linux/list.h>
#include <linux/stringify.h>
/**
bool running;
};
+/**
+ * struct sandbox_mapmem_entry - maps pointers to/from U-Boot addresses
+ *
+ * When map_to_sysmem() is called with an address outside sandbox's emulated
+ * RAM, a record is created with a tag that can be used to reference that
+ * pointer. When map_sysmem() is called later with that tag, the pointer will
+ * be returned, just as it would for a normal sandbox address.
+ *
+ * @tag: Address tag (a value which U-Boot uses to refer to the address)
+ * @ptr: Associated pointer for that tag
+ */
+struct sandbox_mapmem_entry {
+ ulong tag;
+ void *ptr;
+ struct list_head sibling_node;
+};
+
/* The complete state of the test system */
struct sandbox_state {
const char *cmd; /* Command to execute */
/* Information about Watchdog */
struct sandbox_wdt_info wdt;
+
+ ulong next_tag; /* Next address tag to allocate */
+ struct list_head mapmem_head; /* struct sandbox_mapmem_entry */
};
/* Minimum space we guarantee in the state FDT when calling read/write*/
int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str);
+/**
+ * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD
+ *
+ * @dev: OSD device for which to access the internal memory for
+ * @buf: pointer to buffer to receive the OSD memory data
+ * @buflen: length of buffer in bytes
+ */
+int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen);
#endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
-PLATFORM_CPPFLAGS += -fno-strict-aliasing
PLATFORM_CPPFLAGS += -fomit-frame-pointer
PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \
$(call cc-option, -fno-unit-at-a-time))
return 4;
}
-#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(EFI_LOADER)
void efi_add_known_memory(void)
{
struct e820_entry e820[E820MAX];
efi_add_memory_map(start, pages, type, false);
}
}
-#endif /* defined(EFI_LOADER) && !defined(CONFIG_SPL_BUILD) */
+#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
#define _XTENSA_ATOMIC_H
#include <asm/system.h>
-
-typedef struct { volatile int counter; } atomic_t;
-
-#define ATOMIC_INIT(i) { (i) }
-
-#define atomic_read(v) ((v)->counter)
-#define atomic_set(v, i) ((v)->counter = (i))
-
-static inline void atomic_add(int i, atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- v->counter += i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_sub(int i, atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- v->counter -= i;
- local_irq_restore(flags);
-}
-
-static inline void atomic_inc(atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- ++v->counter;
- local_irq_restore(flags);
-}
-
-static inline void atomic_dec(atomic_t *v)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- --v->counter;
- local_irq_restore(flags);
-}
+#include <asm-generic/atomic.h>
#endif
AT91SAM9M10G45EK BOARD
-M: Bo Shen <voice.shen@atmel.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/at91sam9m10g45ek/
F: include/configs/at91sam9m10g45ek.h
AT91SAM9N12EK BOARD
-M: Josh Wu <josh.wu@atmel.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/at91sam9n12ek/
F: include/configs/at91sam9n12ek.h
AT91SAM9X5EK BOARD
-M: Bo Shen <voice.shen@atmel.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/at91sam9x5ek/
F: include/configs/at91sam9x5ek.h
*/
#include <common.h>
+#include <w1.h>
+#include <w1-eeprom.h>
+#include <dm/device-internal.h>
+
+#define AT91_PDA_EEPROM_ID_OFFSET 15
+#define AT91_PDA_EEPROM_ID_LENGTH 5
+#define AT91_PDA_EEPROM_DEFAULT_BUS 0
void dummy(void)
{
}
+
+#if defined CONFIG_W1
+void at91_pda_detect(void)
+{
+ struct udevice *bus, *dev;
+ u8 buf[AT91_PDA_EEPROM_ID_LENGTH + 1] = {0};
+ int ret;
+ int pda = 0;
+
+ ret = w1_get_bus(AT91_PDA_EEPROM_DEFAULT_BUS, &bus);
+ if (ret)
+ return;
+
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ ret = device_probe(dev);
+ if (ret) {
+ continue;
+ } else {
+ ret = w1_eeprom_read_buf(dev, AT91_PDA_EEPROM_ID_OFFSET,
+ (u8 *)buf, AT91_PDA_EEPROM_ID_LENGTH);
+ if (ret)
+ return;
+ break;
+ }
+ }
+ pda = simple_strtoul((const char *)buf, NULL, 10);
+
+ switch (pda) {
+ case 7000:
+ if (buf[4] == 'B')
+ printf("PDA TM7000B detected\n");
+ else
+ printf("PDA TM7000 detected\n");
+ break;
+ case 4300:
+ printf("PDA TM4300 detected\n");
+ break;
+ case 5000:
+ printf("PDA TM5000 detected\n");
+ break;
+ }
+ env_set("pda", (const char *)buf);
+}
+#else
+void at91_pda_detect(void)
+{
+}
+#endif
SAMA5D27 SOM1 EK BOARD
-M: Wenyou Yang <wenyou.yang@microchip.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sama5d27_som1_ek/
F: include/configs/sama5d27_som1_ek.h
F: configs/sama5d27_som1_ek_mmc_defconfig
+F: configs/sama5d27_som1_ek_mmc1_defconfig
#include <asm/arch/gpio.h>
#include <asm/arch/sama5d2.h>
+extern void at91_pda_detect(void);
+
DECLARE_GLOBAL_DATA_PTR;
static void board_usb_hw_init(void)
#ifdef CONFIG_DM_VIDEO
at91_video_show_board_info();
#endif
+ at91_pda_detect();
return 0;
}
#endif
SAMA5D2 PTC EK BOARD
-M: Wenyou Yang <wenyou.yang@microchip.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
M: Ludovic Desroches <ludovic.desroches@microchip.com>
S: Maintained
F: board/atmel/sama5d2_ptc_ek/
#include <asm/arch/sama5d2.h>
#include <asm/arch/sama5d2_smc.h>
+extern void at91_pda_detect(void);
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_NAND_ATMEL
}
#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ at91_pda_detect();
+ return 0;
+}
+#endif
+
static void board_usb_hw_init(void)
{
atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK);
SAMA5D2 XPLAINED BOARD
-M: Wenyou Yang <wenyou.yang@atmel.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sama5d2_xplained/
F: include/configs/sama5d2_xplained.h
F: configs/sama5d2_xplained_mmc_defconfig
F: configs/sama5d2_xplained_spiflash_defconfig
+F: configs/sama5d2_xplained_emmc_defconfig
#include <asm/arch/gpio.h>
#include <asm/arch/sama5d2.h>
+extern void at91_pda_detect(void);
+
DECLARE_GLOBAL_DATA_PTR;
static void board_usb_hw_init(void)
#ifdef CONFIG_DM_VIDEO
at91_video_show_board_info();
#endif
+ at91_pda_detect();
return 0;
}
#endif
SAMA5D3_XPLAINED BOARD
-M: Bo Shen <voice.shen@atmel.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sama5d3_xplained/
F: include/configs/sama5d3_xplained.h
DECLARE_GLOBAL_DATA_PTR;
+extern void at91_pda_detect(void);
+
#ifdef CONFIG_NAND_ATMEL
void sama5d3_xplained_nand_hw_init(void)
{
}
#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ at91_pda_detect();
+ return 0;
+}
+#endif
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
SAMA5D3XEK BOARD
-M: Bo Shen <voice.shen@atmel.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sama5d3xek/
F: include/configs/sama5d3xek.h
SAMA5D4 XPLAINED ULTRA BOARD
-M: Bo Shen <voice.shen@atmel.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sama5d4_xplained/
F: include/configs/sama5d4_xplained.h
DECLARE_GLOBAL_DATA_PTR;
+extern void at91_pda_detect(void);
+
#ifdef CONFIG_NAND_ATMEL
static void sama5d4_xplained_nand_hw_init(void)
{
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+ at91_pda_detect();
#ifdef CONFIG_DM_VIDEO
at91_video_show_board_info();
#endif
SAMA5D4EK BOARD
-M: Bo Shen <voice.shen@atmel.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sama5d4ek/
F: include/configs/sama5d4ek.h
static inline int get_board_version(void)
{
- struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
- int val;
+ uint32_t val;
+#ifdef CONFIG_TARGET_LS1012AFRDM
+ val = 0;
+#else
+ struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
- val = in_be32(&pgpio->gpdat);
+ val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
+#endif
return val;
}
puts("Version");
switch (rev) {
- case BOARD_REV_A:
- puts(": RevA ");
+ case BOARD_REV_A_B:
+ puts(": RevA/B ");
break;
- case BOARD_REV_B:
- puts(": RevB ");
+ case BOARD_REV_C:
+ puts(": RevC ");
break;
default:
puts(": unknown");
#ifdef CONFIG_TARGET_LS1012AFRWY
board_rev = get_board_version();
- if (board_rev & BOARD_REV_B) {
+ if (board_rev == BOARD_REV_C) {
mparam.mdctl = 0x05180000;
gd->ram_size = SYS_SDRAM_SIZE_1024;
} else {
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
-#include <asm/arch/ls102xa_sata.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_immap.h>
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- ls1021a_sata_init();
-#endif
-
return 0;
}
#endif
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
-#include <asm/arch/ls102xa_sata.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- ls1021a_sata_init();
-#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_soc.h>
-#include <asm/arch/ls102xa_sata.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- ls1021a_sata_init();
-#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
+
reg = QIXIS_READ(brdcfg[0]);
reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <fdt_support.h>
#include <hwconfig.h>
#include <ahci.h>
fdt_fixup_fman_ethernet(blob);
#endif
+ fdt_fixup_icid(blob);
+
/*
* qe-hdlc and usb multi-use the pins,
* when set hwconfig to qe-hdlc, delete usb node.
fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
fsl_fdt_fixup_flash(blob);
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_memory_banks(blob, base, size, 2);
+ fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_memory_banks(blob, base, size, 2);
+ fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
fsl_fdt_fixup_dr_usb(blob, bd);
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_memory_banks(blob, base, size, 2);
+ fdt_fsl_mc_fixup_iommu_map_entry(blob);
+
fsl_fdt_fixup_dr_usb(blob, bd);
fsl_fdt_fixup_flash(blob);
For more details, please refer to T2080QDS User Guide and access
website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+
+Device tree support and how to enable it for different configs
+--------------------------------------------------------------
+Device tree support is available for t2080qds for below mentioned boot,
+1. NOR Boot
+2. NAND Boot
+3. SD Boot
+4. SPIFLASH Boot
+
+To enable device tree support for other boot, below configs need to be
+enabled in relative defconfig file,
+1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
+2. CONFIG_OF_CONTROL
+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
+ CONFIG_RESET_VECTOR_ADDRESS - 0xffc
+
+If device tree support is enabled in defconfig,
+1. use 'u-boot-with-dtb.bin' for NOR boot.
+2. use 'u-boot-with-spl-pbl.bin' for other boot.
--- /dev/null
+if BOARD_GARDENA_SMART_GATEWAY_MT7688
+
+config SYS_BOARD
+ default "smart-gateway-mt7688"
+
+config SYS_VENDOR
+ default "gardena"
+
+config SYS_CONFIG_NAME
+ default "gardena-smart-gateway-mt7688"
+
+endif
--- /dev/null
+GARDENA_SMART_GATEWAY_MT7688 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/gardena/smart-gateway-mt7688
+F: include/configs/gardena-smart-gateway-mt7688.h
+F: configs/gardena-smart-gateway-mt7688_defconfig
+F: configs/gardena-smart-gateway-mt7688-ram_defconfig
+F: arch/mips/dts/gardena-smart-gateway-mt7688.dts
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+int board_early_init_f(void)
+{
+ /*
+ * Nothing to be done here for this board (no UART setup etc)
+ * right now. We might need some pin muxing, so lets keep this
+ * function for now.
+ */
+ return 0;
+}
obj-$(CONFIG_STRIDER) += fanctrl.o
obj-$(CONFIG_STRIDER_CON) += osd.o
obj-$(CONFIG_STRIDER_CON_DP) += osd.o
+
+ifdef CONFIG_OSD
+obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * based on the gdsys osd driver, which is
+ *
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <hexdump.h>
+#include <video_osd.h>
+#include <malloc.h>
+
+static int do_osd_write(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dev;
+ uint x, y;
+ uint count;
+ char *hexstr;
+ u8 *buffer;
+ size_t buflen;
+ int res;
+
+ if (argc < 4 || (strlen(argv[3])) % 2)
+ return CMD_RET_USAGE;
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ hexstr = argv[3];
+ count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
+
+ buflen = strlen(hexstr) / 2;
+
+ buffer = malloc(buflen);
+ if (!buffer) {
+ puts("Memory allocation failure\n");
+ return CMD_RET_FAILURE;
+ }
+
+ res = hex2bin(buffer, hexstr, buflen);
+ if (res) {
+ free(buffer);
+ puts("Hexadecimal input contained invalid characters\n");
+ return CMD_RET_FAILURE;
+ }
+
+ for (uclass_first_device(UCLASS_VIDEO_OSD, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ int res;
+
+ res = video_osd_set_mem(dev, x, y, buffer, buflen, count);
+ if (res) {
+ free(buffer);
+ printf("Could not write to video mem on osd %s\n",
+ dev->name);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ free(buffer);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_osd_print(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dev;
+ uint x, y;
+ u8 color;
+ char *text;
+
+ if (argc < 5)
+ return CMD_RET_USAGE;
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ color = simple_strtoul(argv[3], NULL, 16);
+ text = argv[4];
+
+ for (uclass_first_device(UCLASS_VIDEO_OSD, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ int res;
+
+ res = video_osd_print(dev, x, y, color, text);
+ if (res) {
+ printf("Could not print string to osd %s\n", dev->name);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_osd_size(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dev;
+ uint x, y;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+
+ for (uclass_first_device(UCLASS_VIDEO_OSD, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ int res;
+
+ res = video_osd_set_size(dev, x, y);
+
+ if (res) {
+ printf("Could not set size on osd %s\n", dev->name);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ osdw, 5, 0, do_osd_write,
+ "write 16-bit hex encoded buffer to osd memory",
+ "osdw [pos_x] [pos_y] [buffer] [count] - write 8-bit hex encoded buffer to osd memory\n"
+);
+
+U_BOOT_CMD(
+ osdp, 5, 0, do_osd_print,
+ "write ASCII buffer to osd memory",
+ "osdp [pos_x] [pos_y] [color] [text] - write ASCII buffer to osd memory\n"
+);
+
+U_BOOT_CMD(
+ osdsize, 3, 0, do_osd_size,
+ "set OSD XY size in characters",
+ "osdsize [size_x] [size_y] - set OSD XY size in characters\n"
+);
+config GDSYS_LEGACY_OSD_CMDS
+ bool
+ help
+ Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
+ gdsys devices.
+
if TARGET_HRCON
config SYS_BOARD
config SYS_CONFIG_NAME
default "hrcon"
+config GDSYS_LEGACY_OSD_CMDS
+ default y
+
endif
if TARGET_STRIDER
config SYS_CONFIG_NAME
default "strider"
+config GDSYS_LEGACY_OSD_CMDS
+ default y
endif
config CMD_IOLOOP
}
#endif
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
#if defined(CONFIG_MMC)
void board_mmc_power_init(void)
{
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /*CAM_HS */
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /*CAM_VS */
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /*CAM_XCLKA*/
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /*CAM_PCLK*/
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); /*GPIO_98*/
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /*CAM_D0*/
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /*CAM_D1*/
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /*CAM_D2*/
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /*CAM_D3*/
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /*CAM_D4*/
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /*CAM_D5*/
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /*CAM_D6*/
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /*CAM_D7*/
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /*CAM_D8*/
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /*CAM_D9*/
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /*CAM_D10*/
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /*CAM_D11*/
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /*CAM_XCLKB*/
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /*GPIO_167*/
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /*CAM_STROBE*/
-
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /*CSI2_DX0*/
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /*CSI2_DY0*/
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /*CSI2_DX1*/
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /*CSI2_DY1*/
-
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /*McBSP2_FSX*/
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); /*McBSP2_CLKX*/
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /*McBSP2_DR*/
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /*McBSP2_DX*/
-
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
-
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /*MMC2_CLK*/
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /*MMC2_CMD*/
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /*MMC2_DAT0*/
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /*MMC2_DAT1*/
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /*MMC2_DAT2*/
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /*MMC2_DAT3*/
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)); /*MMC2_DAT4*/
- MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)); /*MMC2_DAT5*/
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)); /*MMC2_DAT6 */
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)); /*MMC2_DAT7*/
-
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); /*McBSP3_DX*/
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); /*McBSP3_DR*/
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); /*McBSP3_CLKX*/
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); /*McBSP3_FSX*/
-
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /*UART2_CTS*/
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /*UART2_RTS*/
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /*UART2_TX*/
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /*UART2_RX*/
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
- MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)); /*GPIO_153*/
-
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKR*/
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)); /*MCBSP1_FSR*/
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); /*MCBSP1_DX*/
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /*MCBSP1_DR*/
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); /*MCBSP_CLKS*/
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); /*MCBSP1_FSX*/
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); /*MCBSP1_CLKX*/
-
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); /*UART3_CTS_*/
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); /*UART3_RTS_SD */
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX_IRRX*/
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX_IRTX*/
-
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
-
- MUX_VAL(CP(I2C1_SCL), (IEN | EN | M0)); /*I2C1_SCL*/
- MUX_VAL(CP(I2C1_SDA), (IEN | EN | M0)); /*I2C1_SDA*/
-
- MUX_VAL(CP(I2C2_SCL), (IEN | EN | M0)); /*I2C2_SCL*/
- MUX_VAL(CP(I2C2_SDA), (IEN | EN | M0)); /*I2C2_SDA*/
-
- MUX_VAL(CP(I2C3_SCL), (IEN | EN | M0)); /*I2C3_SCL*/
- MUX_VAL(CP(I2C3_SDA), (IEN | EN | M0)); /*I2C3_SDA*/
-
- MUX_VAL(CP(I2C4_SCL), (IEN | EN | M0)); /*I2C4_SCL*/
- MUX_VAL(CP(I2C4_SDA), (IEN | EN | M0)); /*I2C4_SDA*/
-
- MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /*HDQ_SIO*/
-
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); /*McSPI1_CLK*/
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); /*McSPI1_SIMO */
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); /*McSPI1_SOMI */
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); /*McSPI1_CS0*/
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)); /*GPIO_175*/
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)); /*GPIO_176*/
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*McSPI1_CS3*/
-
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*McSPI2_CLK*/
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*McSPI2_SIMO*/
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*McSPI2_SOMI*/
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*McSPI2_CS0*/
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*McSPI2_CS1*/
-
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /*GPIO_2*/
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /*GPIO_3 */
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /*GPIO_4*/
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /*GPIO_5*/
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /*GPIO_6*/
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /*GPIO_7*/
-
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*SYS_OFF_MODE*/
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*SYS_CLKOUT1*/
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); /*SYS_CLKOUT2*/
-
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
return 0;
}
-int board_prepare_usb(enum usb_init_type type)
+int board_usb_init(int index, enum usb_init_type init)
{
static struct udevice *pmic_gpio;
static struct gpio_desc hub_reset, usb_sel;
}
}
- if (type == USB_INIT_HOST) {
+ if (init == USB_INIT_HOST) {
/* Start USB Hub */
dm_gpio_set_dir_flags(&hub_reset,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (dm_gpio_get_value(&resin)) {
env_set("bootdelay", "-1");
- printf("Power button pressed - dropping to console.\n");
+ env_set("bootcmd", "fastboot 0");
+ printf("key_vol_down pressed - Starting fastboot.\n");
}
return 0;
return 0;
}
+int board_late_init(void)
+{
+ char serial[16];
+
+ memset(serial, 0, 16);
+ snprintf(serial, 13, "%x", msm_board_serial());
+ env_set("serial#", serial);
+ return 0;
+}
+
/* Fixup of DTB for Linux Kernel
* 1. Fixup installed DRAM.
* 2. Fixup WLAN/BT Mac address:
Also sandbox supports driver model (CONFIG_DM) and associated commands.
+Sandbox Variants
+----------------
+
+There are unfortunately quite a few variants at present:
+
+sandbox - should be used for most tests
+sandbox64 - special build that forces a 64-bit host
+sandbox_flattree - builds with dev_read_...() functions defined as inline.
+ We need this build so that we can test those inline functions, and we
+ cannot build with both the inline functions and the non-inline functions
+ since they are named the same.
+sandbox_noblk - builds without CONFIG_BLK, which means the legacy block
+ drivers are used. We cannot use both the legacy and driver-model block
+ drivers since they implement the same functions
+sandbox_spl - builds sandbox with SPL support, so you can run spl/u-boot-spl
+ and it will start up and then load ./u-boot. It is also possible to
+ run ./u-boot directly.
+
+Of these sandbox_noblk can be removed once CONFIG_BLK is used everwhere, and
+sandbox_spl can probably be removed since it is a superset of sandbox.
+
+Most of the config options should be identical between these variants.
+
+
Linux RAW Networking Bridge
---------------------------
--- /dev/null
+if BOARD_LINKIT_SMART_7688
+
+config SYS_BOARD
+ default "linkit-smart-7688"
+
+config SYS_VENDOR
+ default "seeed"
+
+config SYS_CONFIG_NAME
+ default "linkit-smart-7688"
+
+endif
--- /dev/null
+LINKIT_SMART_7688 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/seeed/linkit-smart-7688
+F: include/configs/linkit-smart-7688.h
+F: configs/linkit-smart-7688_defconfig
+F: configs/linkit-smart-7688-ram_defconfig
+F: arch/mips/dts/linkit-smart-7688.dts
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MT76XX_GPIO1_MODE 0xb0000060
+
+void board_debug_uart_init(void)
+{
+ /* Select UART2 mode instead of GPIO mode (default) */
+ clrbits_le32((void __iomem *)MT76XX_GPIO1_MODE, GENMASK(27, 26));
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * The pin muxing of UART2 also needs to be done, if debug uart
+ * is not enabled. So we need to call this function here as well.
+ */
+ board_debug_uart_init();
+
+ return 0;
+}
#include <config.h>
#include <common.h>
#include <led.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <phy.h>
+#include <reset.h>
+#include <usb.h>
#include <asm/arch/stm32.h>
+#include <asm/io.h>
+#include <power/regulator.h>
+#include <usb/dwc2_udc.h>
/*
* Get a global data pointer
*/
DECLARE_GLOBAL_DATA_PTR;
+#define STM32MP_GUSBCFG 0x40002407
+
+#define STM32MP_GGPIO 0x38
+#define STM32MP_GGPIO_VBUS_SENSING BIT(21)
+
+static struct dwc2_plat_otg_data stm32mp_otg_data = {
+ .usb_gusbcfg = STM32MP_GUSBCFG,
+};
+
+static struct reset_ctl usbotg_reset;
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ struct fdtdec_phandle_args args;
+ struct udevice *dev;
+ const void *blob = gd->fdt_blob;
+ struct clk clk;
+ struct phy phy;
+ int node;
+ int phy_provider;
+ int ret;
+
+ /* find the usb otg node */
+ node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
+ if (node < 0) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+
+ if (!fdtdec_get_is_enabled(blob, node)) {
+ debug("stm32 usbotg is disabled in the device tree\n");
+ return -ENODEV;
+ }
+
+ /* Enable clock */
+ ret = fdtdec_parse_phandle_with_args(blob, node, "clocks",
+ "#clock-cells", 0, 0, &args);
+ if (ret) {
+ debug("usbotg has no clocks defined in the device tree\n");
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev);
+ if (ret)
+ return ret;
+
+ if (args.args_count != 1) {
+ debug("Can't find clock ID in the device tree\n");
+ return -ENODATA;
+ }
+
+ clk.dev = dev;
+ clk.id = args.args[0];
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ debug("Failed to enable usbotg clock\n");
+ return ret;
+ }
+
+ /* Reset */
+ ret = fdtdec_parse_phandle_with_args(blob, node, "resets",
+ "#reset-cells", 0, 0, &args);
+ if (ret) {
+ debug("usbotg has no resets defined in the device tree\n");
+ goto clk_err;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node, &dev);
+ if (ret || args.args_count != 1)
+ goto clk_err;
+
+ usbotg_reset.dev = dev;
+ usbotg_reset.id = args.args[0];
+
+ reset_assert(&usbotg_reset);
+ udelay(2);
+ reset_deassert(&usbotg_reset);
+
+ /* Get USB PHY */
+ ret = fdtdec_parse_phandle_with_args(blob, node, "phys",
+ "#phy-cells", 0, 0, &args);
+ if (!ret) {
+ phy_provider = fdt_parent_offset(blob, args.node);
+ ret = uclass_get_device_by_of_offset(UCLASS_PHY,
+ phy_provider, &dev);
+ if (ret)
+ goto clk_err;
+
+ phy.dev = dev;
+ phy.id = fdtdec_get_uint(blob, args.node, "reg", -1);
+
+ ret = generic_phy_power_on(&phy);
+ if (ret) {
+ debug("unable to power on the phy\n");
+ goto clk_err;
+ }
+
+ ret = generic_phy_init(&phy);
+ if (ret) {
+ debug("failed to init usb phy\n");
+ goto phy_power_err;
+ }
+ }
+
+ /* Parse and store data needed for gadget */
+ stm32mp_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+ if (stm32mp_otg_data.regs_otg == FDT_ADDR_T_NONE) {
+ debug("usbotg: can't get base address\n");
+ ret = -ENODATA;
+ goto phy_init_err;
+ }
+
+ stm32mp_otg_data.rx_fifo_sz = fdtdec_get_int(blob, node,
+ "g-rx-fifo-size", 0);
+ stm32mp_otg_data.np_tx_fifo_sz = fdtdec_get_int(blob, node,
+ "g-np-tx-fifo-size", 0);
+ stm32mp_otg_data.tx_fifo_sz = fdtdec_get_int(blob, node,
+ "g-tx-fifo-size", 0);
+ /* Enable voltage level detector */
+ if (!(fdtdec_parse_phandle_with_args(blob, node, "usb33d-supply",
+ NULL, 0, 0, &args))) {
+ if (!uclass_get_device_by_of_offset(UCLASS_REGULATOR,
+ args.node, &dev)) {
+ ret = regulator_set_enable(dev, true);
+ if (ret) {
+ debug("Failed to enable usb33d\n");
+ goto phy_init_err;
+ }
+ }
+ }
+ /* Enable vbus sensing */
+ setbits_le32(stm32mp_otg_data.regs_otg + STM32MP_GGPIO,
+ STM32MP_GGPIO_VBUS_SENSING);
+
+ return dwc2_udc_probe(&stm32mp_otg_data);
+
+phy_init_err:
+ generic_phy_exit(&phy);
+
+phy_power_err:
+ generic_phy_power_off(&phy);
+
+clk_err:
+ clk_disable(&clk);
+
+ return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ /* Reset usbotg */
+ reset_assert(&usbotg_reset);
+ udelay(2);
+ reset_deassert(&usbotg_reset);
+
+ return 0;
+}
+
int board_late_init(void)
{
return 0;
};
#endif
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
+ defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
+
+#define MAX_CPSW_SLAVES 2
+
+/* At the moment, we do not want to stop booting for any failures here */
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ const char *slave_path, *enet_name;
+ int enetnode, slavenode, phynode;
+ struct udevice *ethdev;
+ char alias[16];
+ u32 phy_id[2];
+ int phy_addr;
+ int i, ret;
+
+ /* phy address fixup needed only on beagle bone family */
+ if (!board_is_beaglebonex())
+ goto done;
+
+ for (i = 0; i < MAX_CPSW_SLAVES; i++) {
+ sprintf(alias, "ethernet%d", i);
+
+ slave_path = fdt_get_alias(fdt, alias);
+ if (!slave_path)
+ continue;
+
+ slavenode = fdt_path_offset(fdt, slave_path);
+ if (slavenode < 0)
+ continue;
+
+ enetnode = fdt_parent_offset(fdt, slavenode);
+ enet_name = fdt_get_name(fdt, enetnode, NULL);
+
+ ethdev = eth_get_dev_by_name(enet_name);
+ if (!ethdev)
+ continue;
+
+ phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
+
+ /* check for phy_id as well as phy-handle properties */
+ ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
+ phy_id, 2);
+ if (ret == 2) {
+ if (phy_id[1] != phy_addr) {
+ printf("fixing up phy_id for %s, old: %d, new: %d\n",
+ alias, phy_id[1], phy_addr);
+
+ phy_id[0] = cpu_to_fdt32(phy_id[0]);
+ phy_id[1] = cpu_to_fdt32(phy_addr);
+ do_fixup_by_path(fdt, slave_path, "phy_id",
+ phy_id, sizeof(phy_id), 0);
+ }
+ } else {
+ phynode = fdtdec_lookup_phandle(fdt, slavenode,
+ "phy-handle");
+ if (phynode < 0)
+ continue;
+
+ ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
+ if (ret < 0)
+ continue;
+
+ if (ret != phy_addr) {
+ printf("fixing up phy-handle for %s, old: %d, new: %d\n",
+ alias, ret, phy_addr);
+
+ fdt_setprop_u32(fdt, phynode, "reg",
+ cpu_to_fdt32(phy_addr));
+ }
+ }
+ }
+
+done:
+ return 0;
+}
+#endif
+
/*
* Basic board specific setup. Pinmux has been handled already.
*/
{
int ret = 0;
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
- zynqmp_pmufw_version();
+ u32 pm_api_version;
+
+ pm_api_version = zynqmp_pmufw_version();
+ printf("PMUFW:\tv%d.%d\n",
+ pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
+ pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
+
+ if (pm_api_version < ZYNQMP_PM_VERSION)
+ panic("PMUFW version error. Expected: v%d.%d\n",
+ ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
#endif
#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
help
Extract a part of a multi-image.
-config CMD_POWEROFF
- bool "poweroff"
- help
- Poweroff/Shutdown the system
-
config CMD_SPL
bool "spl export - Export boot information for Falcon boot"
depends on SPL
help
I2C support.
+config CMD_W1
+ depends on W1
+ default y if W1
+ bool "w1 - Support for Dallas 1-Wire protocol"
+ help
+ Dallas 1-wire protocol support
+
config CMD_LOADB
bool "loadb"
default y
and erasing blocks. It allso provides a way to show and change
bad blocks, and test the device.
+config CMD_OSD
+ bool "osd"
+ help
+ Enable the 'osd' command which allows to query information from and
+ write text data to a on-screen display (OSD) device; a virtual device
+ associated with a display capable of displaying a text overlay on the
+ display it's associated with..
+
config CMD_PART
bool "part"
select HAVE_BLOCK_DEVICE
about 1990. These devices are typically removable memory or network
cards using a standard 68-pin connector.
+config CMD_POWEROFF
+ bool "poweroff"
+ help
+ Poweroff/Shutdown the system
+
config CMD_READ
bool "read - Read binary data from a partition"
help
help
Enable the "icache" and "dcache" commands
+config CMD_CONITRACE
+ bool "conitrace - trace console input codes"
+ help
+ Enable the 'conitrace' command which displays the codes received
+ from the console input as hexadecimal numbers.
+
config CMD_DISPLAY
bool "Enable the 'display' command, for character displays"
help
obj-$(CONFIG_CMD_CBFS) += cbfs.o
obj-$(CONFIG_CMD_CLK) += clk.o
obj-$(CONFIG_CMD_CONFIG) += config.o
+obj-$(CONFIG_CMD_CONITRACE) += conitrace.o
obj-$(CONFIG_CMD_CONSOLE) += console.o
obj-$(CONFIG_CMD_CPU) += cpu.o
obj-$(CONFIG_DATAFLASH_MMC_SELECT) += dataflash_mmc_mux.o
obj-$(CONFIG_CMD_NAND) += nand.o
obj-$(CONFIG_CMD_NET) += net.o
obj-$(CONFIG_CMD_ONENAND) += onenand.o
+obj-$(CONFIG_CMD_OSD) += osd.o
obj-$(CONFIG_CMD_PART) += part.o
ifdef CONFIG_PCI
obj-$(CONFIG_CMD_PCI) += pci.o
obj-$(CONFIG_CMD_XIMG) += ximg.o
obj-$(CONFIG_CMD_YAFFS2) += yaffs2.o
obj-$(CONFIG_CMD_SPL) += spl.o
+obj-$(CONFIG_CMD_W1) += w1.o
obj-$(CONFIG_CMD_ZIP) += zip.o
obj-$(CONFIG_CMD_ZFS) += zfs.o
if (ret != EFI_SUCCESS)
goto out;
+ /* Initialize root node */
+ ret = efi_root_node_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
+
/* Initialize EFI driver uclass */
ret = efi_driver_init();
if (ret != EFI_SUCCESS)
{
size_t size;
const char *env = env_get(env_var);
+ u16 *pos;
loaded_image_info->load_options = NULL;
loaded_image_info->load_options_size = 0;
if (!env)
return;
- size = strlen(env) + 1;
+ size = utf8_utf16_strlen(env) + 1;
loaded_image_info->load_options = calloc(size, sizeof(u16));
if (!loaded_image_info->load_options) {
printf("ERROR: Out of memory\n");
return;
}
- utf8_to_utf16(loaded_image_info->load_options, (u8 *)env, size);
+ pos = loaded_image_info->load_options;
+ utf8_utf16_strcpy(&pos, env);
loaded_image_info->load_options_size = size * 2;
}
-static void *copy_fdt(void *fdt)
+/**
+ * copy_fdt() - Copy the device tree to a new location available to EFI
+ *
+ * The FDT is relocated into a suitable location within the EFI memory map.
+ * An additional 12KB is added to the space in case the device tree needs to be
+ * expanded later with fdt_open_into().
+ *
+ * @fdt_addr: On entry, address of start of FDT. On exit, address of relocated
+ * FDT start
+ * @fdt_sizep: Returns new size of FDT, including
+ * @return new relocated address of FDT
+ */
+static efi_status_t copy_fdt(ulong *fdt_addrp, ulong *fdt_sizep)
{
- u64 fdt_size = fdt_totalsize(fdt);
unsigned long fdt_ram_start = -1L, fdt_pages;
+ efi_status_t ret = 0;
+ void *fdt, *new_fdt;
u64 new_fdt_addr;
- void *new_fdt;
+ uint fdt_size;
int i;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- u64 ram_start = gd->bd->bi_dram[i].start;
- u64 ram_size = gd->bd->bi_dram[i].size;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ u64 ram_start = gd->bd->bi_dram[i].start;
+ u64 ram_size = gd->bd->bi_dram[i].size;
if (!ram_size)
continue;
* Give us at least 4KB of breathing room in case the device tree needs
* to be expanded later. Round up to the nearest EFI page boundary.
*/
- fdt_size += 4096;
+ fdt = map_sysmem(*fdt_addrp, 0);
+ fdt_size = fdt_totalsize(fdt);
+ fdt_size += 4096 * 3;
fdt_size = ALIGN(fdt_size + EFI_PAGE_SIZE - 1, EFI_PAGE_SIZE);
fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
- /* Safe fdt location is at 128MB */
- new_fdt_addr = fdt_ram_start + (128 * 1024 * 1024) + fdt_size;
- if (efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
- EFI_RUNTIME_SERVICES_DATA, fdt_pages,
- &new_fdt_addr) != EFI_SUCCESS) {
+ /* Safe fdt location is at 127MB */
+ new_fdt_addr = fdt_ram_start + (127 * 1024 * 1024) + fdt_size;
+ ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+ EFI_RUNTIME_SERVICES_DATA, fdt_pages,
+ &new_fdt_addr);
+ if (ret != EFI_SUCCESS) {
/* If we can't put it there, put it somewhere */
new_fdt_addr = (ulong)memalign(EFI_PAGE_SIZE, fdt_size);
- if (efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
- EFI_RUNTIME_SERVICES_DATA, fdt_pages,
- &new_fdt_addr) != EFI_SUCCESS) {
+ ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+ EFI_RUNTIME_SERVICES_DATA, fdt_pages,
+ &new_fdt_addr);
+ if (ret != EFI_SUCCESS) {
printf("ERROR: Failed to reserve space for FDT\n");
- return NULL;
+ goto done;
}
}
- new_fdt = (void*)(ulong)new_fdt_addr;
+ new_fdt = map_sysmem(new_fdt_addr, fdt_size);
memcpy(new_fdt, fdt, fdt_totalsize(fdt));
fdt_set_totalsize(new_fdt, fdt_size);
- return new_fdt;
+ *fdt_addrp = new_fdt_addr;
+ *fdt_sizep = fdt_size;
+done:
+ return ret;
}
static efi_status_t efi_do_enter(
}
}
-static efi_status_t efi_install_fdt(void *fdt)
+static efi_status_t efi_install_fdt(ulong fdt_addr)
{
bootm_headers_t img = { 0 };
- ulong fdt_pages, fdt_size, fdt_start, fdt_end;
+ ulong fdt_pages, fdt_size, fdt_start;
efi_status_t ret;
+ void *fdt;
+ fdt = map_sysmem(fdt_addr, 0);
if (fdt_check_header(fdt)) {
printf("ERROR: invalid device tree\n");
return EFI_INVALID_PARAMETER;
}
/* Prepare fdt for payload */
- fdt = copy_fdt(fdt);
- if (!fdt)
- return EFI_OUT_OF_RESOURCES;
+ ret = copy_fdt(&fdt_addr, &fdt_size);
+ if (ret)
+ return ret;
+ unmap_sysmem(fdt);
+ fdt = map_sysmem(fdt_addr, 0);
+ fdt_size = fdt_totalsize(fdt);
if (image_setup_libfdt(&img, fdt, 0, NULL)) {
printf("ERROR: failed to process device tree\n");
return EFI_LOAD_ERROR;
return EFI_OUT_OF_RESOURCES;
/* And reserve the space in the memory map */
- fdt_start = ((ulong)fdt) & ~EFI_PAGE_MASK;
- fdt_end = ((ulong)fdt) + fdt_totalsize(fdt);
- fdt_size = (fdt_end - fdt_start) + EFI_PAGE_MASK;
+ fdt_start = fdt_addr;
fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
- /* Give a bootloader the chance to modify the device tree */
- fdt_pages += 2;
+
ret = efi_add_memory_map(fdt_start, fdt_pages,
EFI_BOOT_SERVICES_DATA, true);
+
return ret;
}
-/*
- * Load an EFI payload into a newly allocated piece of memory, register all
- * EFI objects it would want to access and jump to it.
+/**
+ * do_bootefi_exec() - execute EFI binary
+ *
+ * @efi: address of the binary
+ * @device_path: path of the device from which the binary was loaded
+ * @image_path: device path of the binary
+ * Return: status code
+ *
+ * Load the EFI binary into a newly assigned memory unwinding the relocation
+ * information, install the loaded image protocol, and call the binary.
*/
static efi_status_t do_bootefi_exec(void *efi,
struct efi_device_path *device_path,
struct efi_device_path *image_path)
{
- struct efi_loaded_image loaded_image_info = {};
- struct efi_object loaded_image_info_obj = {};
- struct efi_object mem_obj = {};
+ efi_handle_t mem_handle = NULL;
struct efi_device_path *memdp = NULL;
efi_status_t ret;
+ struct efi_loaded_image_obj *image_handle = NULL;
+ struct efi_loaded_image *loaded_image_info = NULL;
EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
struct efi_system_table *st);
/*
* Special case for efi payload not loaded from disk, such as
* 'bootefi hello' or for example payload loaded directly into
- * memory via jtag/etc:
+ * memory via jtag, etc:
*/
if (!device_path && !image_path) {
printf("WARNING: using memory device/image path, this may confuse some payloads!\n");
/* actual addresses filled in after efi_load_pe() */
memdp = efi_dp_from_mem(0, 0, 0);
device_path = image_path = memdp;
- efi_add_handle(&mem_obj);
-
- ret = efi_add_protocol(mem_obj.handle, &efi_guid_device_path,
+ /*
+ * Grub expects that the device path of the loaded image is
+ * installed on a handle.
+ */
+ ret = efi_create_handle(&mem_handle);
+ if (ret != EFI_SUCCESS)
+ goto exit;
+ ret = efi_add_protocol(mem_handle, &efi_guid_device_path,
device_path);
if (ret != EFI_SUCCESS)
goto exit;
assert(device_path && image_path);
}
- efi_setup_loaded_image(&loaded_image_info, &loaded_image_info_obj,
- device_path, image_path);
+ ret = efi_setup_loaded_image(device_path, image_path, &image_handle,
+ &loaded_image_info);
+ if (ret != EFI_SUCCESS)
+ goto exit;
/*
* gd lives in a fixed register which may get clobbered while we execute
efi_save_gd();
/* Transfer environment variable bootargs as load options */
- set_load_options(&loaded_image_info, "bootargs");
+ set_load_options(loaded_image_info, "bootargs");
/* Load the EFI payload */
- entry = efi_load_pe(efi, &loaded_image_info);
+ entry = efi_load_pe(image_handle, efi, loaded_image_info);
if (!entry) {
ret = EFI_LOAD_ERROR;
goto exit;
if (memdp) {
struct efi_device_path_memory *mdp = (void *)memdp;
- mdp->memory_type = loaded_image_info.image_code_type;
- mdp->start_address = (uintptr_t)loaded_image_info.image_base;
+ mdp->memory_type = loaded_image_info->image_code_type;
+ mdp->start_address = (uintptr_t)loaded_image_info->image_base;
mdp->end_address = mdp->start_address +
- loaded_image_info.image_size;
+ loaded_image_info->image_size;
}
/* we don't support much: */
/* Call our payload! */
debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
- if (setjmp(&loaded_image_info.exit_jmp)) {
- ret = loaded_image_info.exit_status;
+ if (setjmp(&image_handle->exit_jmp)) {
+ ret = image_handle->exit_status;
goto exit;
}
/* Move into EL2 and keep running there */
armv8_switch_to_el2((ulong)entry,
- (ulong)&loaded_image_info_obj.handle,
+ (ulong)image_handle,
(ulong)&systab, 0, (ulong)efi_run_in_el2,
ES_TO_AARCH64);
secure_ram_addr(_do_nonsec_entry)(
efi_run_in_hyp,
(uintptr_t)entry,
- (uintptr_t)loaded_image_info_obj.handle,
+ (uintptr_t)image_handle,
(uintptr_t)&systab);
/* Should never reach here, efi exits with longjmp */
}
#endif
- ret = efi_do_enter(loaded_image_info_obj.handle, &systab, entry);
+ ret = efi_do_enter(image_handle, &systab, entry);
exit:
/* image has returned, loaded-image obj goes *poof*: */
- list_del(&loaded_image_info_obj.link);
- if (mem_obj.handle)
- list_del(&mem_obj.link);
+ if (image_handle)
+ efi_delete_handle(&image_handle->parent);
+ if (mem_handle)
+ efi_delete_handle(mem_handle);
return ret;
}
char *saddr;
efi_status_t r;
unsigned long fdt_addr;
- void *fdt;
/* Allow unaligned memory access */
allow_unaligned();
if (!fdt_addr && *argv[2] != '0')
return CMD_RET_USAGE;
/* Install device tree */
- fdt = map_sysmem(fdt_addr, 0);
- r = efi_install_fdt(fdt);
+ r = efi_install_fdt(fdt_addr);
if (r != EFI_SUCCESS) {
printf("ERROR: failed to install device tree\n");
return CMD_RET_FAILURE;
#endif
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
if (!strcmp(argv[1], "selftest")) {
- struct efi_loaded_image loaded_image_info = {};
- struct efi_object loaded_image_info_obj = {};
+ struct efi_loaded_image_obj *image_handle;
+ struct efi_loaded_image *loaded_image_info;
/* Construct a dummy device path. */
bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
(uintptr_t)&efi_selftest);
bootefi_image_path = efi_dp_from_file(NULL, 0, "\\selftest");
- efi_setup_loaded_image(&loaded_image_info,
- &loaded_image_info_obj,
- bootefi_device_path, bootefi_image_path);
+ r = efi_setup_loaded_image(bootefi_device_path,
+ bootefi_image_path, &image_handle,
+ &loaded_image_info);
+ if (r != EFI_SUCCESS)
+ return CMD_RET_FAILURE;
+
/*
* gd lives in a fixed register which may get clobbered while we
* execute the payload. So save it here and restore it on every
*/
efi_save_gd();
/* Transfer environment variable efi_selftest as load options */
- set_load_options(&loaded_image_info, "efi_selftest");
+ set_load_options(loaded_image_info, "efi_selftest");
/* Execute the test */
- r = efi_selftest(loaded_image_info_obj.handle, &systab);
+ r = efi_selftest(image_handle, &systab);
efi_restore_gd();
- free(loaded_image_info.load_options);
- list_del(&loaded_image_info_obj.link);
+ free(loaded_image_info->load_options);
+ efi_delete_handle(&image_handle->parent);
return r != EFI_SUCCESS;
} else
#endif
char filename[32] = { 0 }; /* dp->str is u16[32] long */
char *s;
+ /* efi_set_bootdev is typically called repeatedly, recover memory */
+ efi_free_pool(bootefi_device_path);
+ efi_free_pool(bootefi_image_path);
+ /* If blk_get_device_part_str fails, avoid duplicate free. */
+ bootefi_device_path = NULL;
+ bootefi_image_path = NULL;
+
if (strcmp(dev, "Net")) {
struct blk_desc *desc;
disk_partition_t fs_partition;
#include <common.h>
#include <command.h>
#include <clk.h>
+#if defined(CONFIG_DM) && defined(CONFIG_CLK)
+#include <dm.h>
+#include <dm/device-internal.h>
+#endif
int __weak soc_clk_dump(void)
{
+#if defined(CONFIG_DM) && defined(CONFIG_CLK)
+ struct udevice *dev;
+ struct uclass *uc;
+ struct clk clk;
+ int ret;
+
+ /* Device addresses start at 1 */
+ ret = uclass_get(UCLASS_CLK, &uc);
+ if (ret)
+ return ret;
+
+ uclass_foreach_dev(dev, uc) {
+ memset(&clk, 0, sizeof(clk));
+ ret = device_probe(dev);
+ if (ret) {
+ printf("%-30.30s : ? Hz\n", dev->name);
+ continue;
+ }
+
+ ret = clk_request(dev, &clk);
+ if (ret) {
+ printf("%-30.30s : ? Hz\n", dev->name);
+ continue;
+ }
+
+ printf("%-30.30s : %lu Hz\n", dev->name, clk_get_rate(&clk));
+
+ clk_free(&clk);
+ }
+
+ return 0;
+#else
puts("Not implemented\n");
return 1;
+#endif
}
static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'conitrace' command prints the codes received from the console input as
+ * hexadecimal numbers.
+ *
+ * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+#include <common.h>
+#include <command.h>
+
+static int do_conitrace(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ bool first = true;
+
+ printf("Waiting for your input\n");
+ printf("To terminate type 'x'\n");
+
+ /* Empty input buffer */
+ while (tstc())
+ getc();
+
+ for (;;) {
+ int c = getc();
+
+ if (first && (c == 'x' || c == 'X'))
+ break;
+
+ printf("%02x ", c);
+ first = false;
+
+ /* 1 ms delay - serves to detect separate keystrokes */
+ udelay(1000);
+ if (!tstc()) {
+ printf("\n");
+ first = true;
+ }
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char conitrace_help_text[] = "";
+#endif
+
+U_BOOT_CMD_COMPLETE(
+ conitrace, 2, 0, do_conitrace,
+ "trace console input",
+ conitrace_help_text, NULL
+);
memcpy((void *)(uintptr_t)shdr->sh_addr,
(const void *)image, shdr->sh_size);
}
- flush_cache(shdr->sh_addr, shdr->sh_size);
+ flush_cache(rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN),
+ roundup((shdr->sh_addr + shdr->sh_size),
+ ARCH_DMA_MINALIGN) -
+ rounddown(shdr->sh_addr, ARCH_DMA_MINALIGN));
}
return ehdr->e_entry;
int ret;
unsigned long addr;
unsigned long count;
+ long offset;
struct blk_desc *dev_desc = NULL;
disk_partition_t info;
int dev = 0;
}
addr = simple_strtoul(argv[3], NULL, 16);
count = (argc <= 5) ? 0 : simple_strtoul(argv[5], NULL, 16);
+ /* offset should be a hex, but "-1" is allowed */
+ offset = (argc <= 6) ? 0 : simple_strtol(argv[6], NULL, 16);
buf = map_sysmem(addr, count);
- ret = file_fat_write(argv[4], buf, 0, count, &size);
+ ret = file_fat_write(argv[4], buf, offset, count, &size);
unmap_sysmem(buf);
if (ret < 0) {
printf("\n** Unable to write \"%s\" from %s %d:%d **\n",
}
U_BOOT_CMD(
- fatwrite, 6, 0, do_fat_fswrite,
+ fatwrite, 7, 0, do_fat_fswrite,
"write file into a dos filesystem",
- "<interface> <dev[:part]> <addr> <filename> [<bytes>]\n"
+ "<interface> <dev[:part]> <addr> <filename> [<bytes> [<offset>]]\n"
" - write file 'filename' from the address 'addr' in RAM\n"
" to 'dev' on 'interface'"
);
+
+static int do_fat_rm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return do_rm(cmdtp, flag, argc, argv, FS_TYPE_FAT);
+}
+
+U_BOOT_CMD(
+ fatrm, 4, 1, do_fat_rm,
+ "delete a file",
+ "<interface> [<dev[:part]>] <filename>\n"
+ " - delete a file from 'dev' on 'interface'"
+);
+
+static int do_fat_mkdir(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return do_mkdir(cmdtp, flag, argc, argv, FS_TYPE_FAT);
+}
+
+U_BOOT_CMD(
+ fatmkdir, 4, 1, do_fat_mkdir,
+ "create a directory",
+ "<interface> [<dev[:part]>] <directory>\n"
+ " - create a directory in 'dev' on 'interface'"
+);
#endif
}
if (chk) {
- envp->crc = crc32(0, envp->data, ENV_SIZE);
+ envp->crc = crc32(0, envp->data,
+ size ? size - offsetof(env_t, data) : ENV_SIZE);
#ifdef CONFIG_ENV_ADDR_REDUND
envp->flags = ACTIVE_FLAG;
#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * based on the gdsys osd driver, which is
+ *
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <hexdump.h>
+#include <video_osd.h>
+#include <malloc.h>
+
+/* Container for selected OSD device */
+static struct udevice *osd_cur;
+
+/**
+ * cmd_osd_set_osd_num() - Set the OSD selected for operation
+ *
+ * Set the OSD device, which will be used by all subsequent OSD commands.
+ *
+ * Devices are identified by their uclass sequence number (as listed by 'osd
+ * show').
+ *
+ * @osdnum: The OSD device to be selected, identified by its sequence number.
+ * Return: 0 if OK, -ve on error
+ */
+static int cmd_osd_set_osd_num(unsigned int osdnum)
+{
+ struct udevice *osd;
+ int res;
+
+ res = uclass_get_device_by_seq(UCLASS_VIDEO_OSD, osdnum, &osd);
+ if (res) {
+ printf("%s: No OSD %u (err = %d)\n", __func__, osdnum, res);
+ return res;
+ }
+ osd_cur = osd;
+
+ return 0;
+}
+
+/**
+ * osd_get_osd_cur() - Get the selected OSD device
+ *
+ * Get the OSD device that is used by all OSD commands.
+ *
+ * @osdp: Pointer to structure that will receive the currently selected OSD
+ * device.
+ * Return: 0 if OK, -ve on error
+ */
+static int osd_get_osd_cur(struct udevice **osdp)
+{
+ if (!osd_cur) {
+ puts("No osd selected\n");
+ return -ENODEV;
+ }
+ *osdp = osd_cur;
+
+ return 0;
+}
+
+/**
+ * show_osd() - Display information about a OSD device
+ *
+ * Display a device's ID (sequence number), and whether it is active (i.e.
+ * probed) or not.
+ *
+ * @osd: OSD device to print information for
+ */
+static void show_osd(struct udevice *osd)
+{
+ printf("OSD %d:\t%s", osd->req_seq, osd->name);
+ if (device_active(osd))
+ printf(" (active %d)", osd->seq);
+ printf("\n");
+}
+
+static int do_osd_write(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ uint x, y;
+ uint count;
+ char *hexstr;
+ u8 *buffer;
+ size_t buflen;
+ int res;
+
+ if (argc < 4 || (strlen(argv[3]) % 2))
+ return CMD_RET_USAGE;
+
+ if (!osd_cur) {
+ puts("No osd selected\n");
+ return CMD_RET_FAILURE;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ hexstr = argv[3];
+ count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
+
+ buflen = strlen(hexstr) / 2;
+
+ buffer = malloc(buflen);
+ if (!buffer) {
+ puts("Memory allocation failure\n");
+ return CMD_RET_FAILURE;
+ }
+
+ res = hex2bin(buffer, hexstr, buflen);
+ if (res) {
+ free(buffer);
+ puts("Hexadecimal input contained invalid characters\n");
+ return CMD_RET_FAILURE;
+ }
+
+ res = video_osd_set_mem(osd_cur, x, y, buffer, buflen, count);
+ if (res) {
+ free(buffer);
+ printf("%s: Could not write to video mem\n",
+ osd_cur->name);
+ return CMD_RET_FAILURE;
+ }
+
+ free(buffer);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_osd_print(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ uint x, y;
+ u8 color;
+ char *text;
+ int res;
+
+ if (argc < 5)
+ return CMD_RET_USAGE;
+
+ if (!osd_cur) {
+ puts("No osd selected\n");
+ return CMD_RET_FAILURE;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ color = simple_strtoul(argv[3], NULL, 16);
+ text = argv[4];
+
+ res = video_osd_print(osd_cur, x, y, color, text);
+ if (res) {
+ printf("Could not print string to osd %s\n", osd_cur->name);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_osd_size(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ uint x, y;
+ int res;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ if (!osd_cur) {
+ puts("No osd selected\n");
+ return CMD_RET_FAILURE;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+
+ res = video_osd_set_size(osd_cur, x, y);
+ if (res) {
+ printf("Could not set size on osd %s\n", osd_cur->name);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_show_osd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *osd;
+
+ if (argc == 1) {
+ /* show all OSDs */
+ struct uclass *uc;
+ int res;
+
+ res = uclass_get(UCLASS_VIDEO_OSD, &uc);
+ if (res) {
+ printf("Error while getting OSD uclass (err=%d)\n",
+ res);
+ return CMD_RET_FAILURE;
+ }
+
+ uclass_foreach_dev(osd, uc)
+ show_osd(osd);
+ } else {
+ int i, res;
+
+ /* show specific OSD */
+ i = simple_strtoul(argv[1], NULL, 10);
+
+ res = uclass_get_device_by_seq(UCLASS_VIDEO_OSD, i, &osd);
+ if (res) {
+ printf("Invalid osd %d: err=%d\n", i, res);
+ return CMD_RET_FAILURE;
+ }
+ show_osd(osd);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_osd_num(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int osd_no;
+ int res = 0;
+
+ if (argc == 1) {
+ /* querying current setting */
+ struct udevice *osd;
+
+ if (!osd_get_osd_cur(&osd))
+ osd_no = osd->seq;
+ else
+ osd_no = -1;
+ printf("Current osd is %d\n", osd_no);
+ } else {
+ osd_no = simple_strtoul(argv[1], NULL, 10);
+ printf("Setting osd to %d\n", osd_no);
+
+ res = cmd_osd_set_osd_num(osd_no);
+ if (res)
+ printf("Failure changing osd number (err = %d)\n", res);
+ }
+
+ return res ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+static cmd_tbl_t cmd_osd_sub[] = {
+ U_BOOT_CMD_MKENT(show, 1, 1, do_show_osd, "", ""),
+ U_BOOT_CMD_MKENT(dev, 1, 1, do_osd_num, "", ""),
+ U_BOOT_CMD_MKENT(write, 4, 1, do_osd_write, "", ""),
+ U_BOOT_CMD_MKENT(print, 4, 1, do_osd_print, "", ""),
+ U_BOOT_CMD_MKENT(size, 2, 1, do_osd_size, "", ""),
+};
+
+static int do_osd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading 'osd' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_osd_sub[0], ARRAY_SIZE(cmd_osd_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+static char osd_help_text[] =
+ "show - show OSD info\n"
+ "osd dev [dev] - show or set current OSD\n"
+ "write [pos_x] [pos_y] [buffer] [count] - write 8-bit hex encoded buffer to osd memory at a given position\n"
+ "print [pos_x] [pos_y] [color] [text] - write ASCII buffer (given by text data and driver-specific color information) to osd memory\n"
+ "size [size_x] [size_y] - set OSD XY size in characters\n";
+
+U_BOOT_CMD(
+ osd, 6, 1, do_osd,
+ "OSD sub-system",
+ osd_help_text
+);
static struct ubi_device *ubi;
#ifdef CONFIG_CMD_UBIFS
-int ubifs_is_mounted(void);
-void cmd_ubifs_umount(void);
+#include <ubifs_uboot.h>
#endif
static void display_volume_info(struct ubi_device *ubi)
static int ubifs_initialized;
static int ubifs_mounted;
-static int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+int cmd_ubifs_mount(char *vol_name)
{
- char *vol_name;
int ret;
- if (argc != 2)
- return CMD_RET_USAGE;
-
- vol_name = argv[1];
debug("Using volume %s\n", vol_name);
if (ubifs_initialized == 0) {
ubifs_mounted = 1;
- return 0;
+ return ret;
+}
+static int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ char *vol_name;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ vol_name = argv[1];
+
+ return cmd_ubifs_mount(vol_name);
}
int ubifs_is_mounted(void)
return ubifs_mounted;
}
-void cmd_ubifs_umount(void)
+int cmd_ubifs_umount(void)
{
+ if (ubifs_initialized == 0) {
+ printf("No UBIFS volume mounted!\n");
+ return -1;
+ }
+
uboot_ubifs_umount();
ubifs_mounted = 0;
ubifs_initialized = 0;
+
+ return 0;
}
static int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc,
if (argc != 1)
return CMD_RET_USAGE;
- if (ubifs_initialized == 0) {
- printf("No UBIFS volume mounted!\n");
- return -1;
- }
-
- cmd_ubifs_umount();
-
- return 0;
+ return cmd_ubifs_umount();
}
static int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc,
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * (C) Copyright 2018
+ * Microchip Technology, Inc.
+ * Eugen Hristev <eugen.hristev@microchip.com>
+ */
+#include <common.h>
+#include <command.h>
+#include <w1.h>
+#include <w1-eeprom.h>
+#include <dm/device-internal.h>
+
+static int w1_bus(void)
+{
+ struct udevice *bus, *dev;
+ int ret;
+
+ ret = w1_get_bus(0, &bus);
+ if (ret) {
+ printf("one wire interface not found\n");
+ return CMD_RET_FAILURE;
+ }
+ printf("Bus %d:\t%s", bus->seq, bus->name);
+ if (device_active(bus))
+ printf(" (active)");
+ printf("\n");
+
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ ret = device_probe(dev);
+
+ printf("\t%s (%d) uclass %s : ", dev->name, dev->seq,
+ dev->uclass->uc_drv->name);
+
+ if (ret)
+ printf("device error\n");
+ else
+ printf("family 0x%x\n", w1_get_device_family(dev));
+ }
+ return CMD_RET_SUCCESS;
+}
+
+static int w1_read(int argc, char *const argv[])
+{
+ int bus_n = 0, dev_n = 0, offset = 0, len = 512;
+ int i;
+ struct udevice *bus, *dev;
+ int ret;
+ u8 buf[512];
+
+ if (argc > 2)
+ bus_n = simple_strtoul(argv[2], NULL, 10);
+
+ if (argc > 3)
+ dev_n = simple_strtoul(argv[3], NULL, 10);
+
+ if (argc > 4)
+ offset = simple_strtoul(argv[4], NULL, 10);
+
+ if (argc > 5)
+ len = simple_strtoul(argv[5], NULL, 10);
+
+ if (len > 512) {
+ printf("len needs to be <= 512\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = w1_get_bus(bus_n, &bus);
+ if (ret) {
+ printf("one wire interface not found\n");
+ return CMD_RET_FAILURE;
+ }
+
+ for (device_find_first_child(bus, &dev), i = 0;
+ dev && i <= dev_n;
+ device_find_next_child(&dev), i++) {
+ ret = device_probe(dev);
+ if (!ret && i == dev_n)
+ break;
+ }
+
+ if (i != dev_n || ret || !dev) {
+ printf("invalid dev\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (strcmp(dev->uclass->uc_drv->name, "w1_eeprom")) {
+ printf("the device present on the interface is of unknown device class\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = w1_eeprom_read_buf(dev, offset, (u8 *)buf, len);
+ if (ret) {
+ printf("error reading device %s\n", dev->name);
+ return CMD_RET_FAILURE;
+ }
+
+ for (i = 0; i < len; i++)
+ printf("%x", buf[i]);
+ printf("\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+int do_w1(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(argv[1], "bus"))
+ return w1_bus();
+
+ if (!strcmp(argv[1], "read"))
+ return w1_read(argc, argv);
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(w1, 6, 0, do_w1,
+ "onewire interface utility commands",
+ "bus - show onewire bus info (all)\n"
+ "w1 read [<bus> [<dev> [offset [length]]]]"
+ " - read from onewire device 'dev' on onewire bus 'bus'"
+ " starting from offset 'offset' and length 'length'\n"
+ " defaults: bus 0, dev 0, offset 0, length 512 bytes.");
The buffer is allocated immediately after the malloc() region is
ready.
+config DISABLE_CONSOLE
+ bool "Add functionality to disable console completely"
+ help
+ Disable console (in & out).
+
config IDENT_STRING
string "Board specific string to be added to uboot version string"
help
next reset.
config BOARD_LATE_INIT
- bool
+ bool "Execute Board late init"
help
Sometimes board require some initialization code that might
require once the actual init done, example saving board specific env,
puts("Could not find a valid device tree\n");
return 1;
}
- set_working_fdt_addr((ulong)images.ft_addr);
+ set_working_fdt_addr(map_to_sysmem(images.ft_addr));
#endif
#if IMAGE_ENABLE_FIT
*of_flat_tree = of_start;
*of_size = of_len;
- set_working_fdt_addr((ulong)*of_flat_tree);
+ set_working_fdt_addr(map_to_sysmem(*of_flat_tree));
return 0;
error:
/* Nothing to do! */
}
+__weak struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+ return (struct image_header *)(CONFIG_SYS_TEXT_BASE + offset);
+}
+
void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
{
ulong u_boot_pos = binman_sym(ulong, u_boot_any, image_pos);
loff_t filelen, actlen;
disk_partition_t part_info = {};
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
+ header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
if (part_get_info(block_dev, partition, &part_info)) {
printf("spl: no partition table found\n");
if (err)
goto end;
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
+ header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
err = file_fat_read(filename, header, sizeof(struct image_header));
if (err <= 0)
board_fit_image_post_process(&src, &length);
#endif
- if (IS_ENABLED(CONFIG_SPL_OS_BOOT) &&
- IS_ENABLED(CONFIG_SPL_GZIP) &&
- image_comp == IH_COMP_GZIP &&
- type == IH_TYPE_KERNEL) {
+ if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
size = length;
if (gunzip((void *)load_addr, CONFIG_SYS_BOOTM_LEN,
src, &size)) {
struct spl_image_info image_info;
int node = -1;
int images, ret;
- int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
+ int base_offset, hsize, align_len = ARCH_DMA_MINALIGN - 1;
int index = 0;
/*
* For FIT with data embedded, data is loaded as part of FIT image.
* For FIT with external data, data is not loaded in this step.
*/
- fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len -
- align_len) & ~align_len);
+ hsize = (size + info->bl_len + align_len) & ~align_len;
+ fit = spl_get_load_buffer(-hsize, hsize);
sectors = get_aligned_image_size(info, size, 0);
count = info->read(info, sector, sectors, fit);
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
{
unsigned long count;
struct image_header *header;
+ struct blk_desc *bd = mmc_get_blk_desc(mmc);
int ret = 0;
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
+ header = spl_get_load_buffer(-sizeof(*header), bd->blksz);
/* read image header to find the image size & load address */
- count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, header);
+ count = blk_dread(bd, sector, 1, header);
debug("hdr read sector %lx, count=%lu\n", sector, count);
if (count == 0) {
ret = -EIO;
#endif
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: could not find mmc device. error: %d\n", err);
+ printf("spl: could not find mmc device %d. error: %d\n",
+ mmc_dev, err);
#endif
return err;
}
#endif
nand_init();
- /*use CONFIG_SYS_TEXT_BASE as temporary storage area */
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+ header = spl_get_load_buffer(0, sizeof(*header));
+
#ifdef CONFIG_SPL_OS_BOOT
if (!spl_start_uboot()) {
/*
debug("spl: onenand\n");
- /*use CONFIG_SYS_TEXT_BASE as temporary storage area */
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+ header = spl_get_load_buffer(0, CONFIG_SYS_ONENAND_PAGE_SIZE);
/* Load u-boot */
onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header);
* No binman support or no information. For now, fix it
* to the address pointed to by U-Boot.
*/
- u_boot_pos = CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header);
+ header = spl_get_load_buffer(-sizeof(*header),
+ sizeof(*header));
+
}
header = (struct image_header *)map_sysmem(u_boot_pos, 0);
return -ENODEV;
}
- /* use CONFIG_SYS_TEXT_BASE as temporary storage area */
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+ header = spl_get_load_buffer(-sizeof(*header), 0x40);
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
payload_offs = fdtdec_get_config_int(gd->fdt_blob,
puts("Loading Linux failed, falling back to U-Boot.\n");
}
#endif
- header = (struct image_header *)
- (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
+ header = spl_get_load_buffer(-sizeof(*header), sizeof(header));
volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_MONITOR_ID;
volumes[0].load_addr = (void *)header;
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_OF_PLATDATA=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM_PCA953X=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
# CONFIG_TWL4030_POWER is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY=y
CONFIG_BCM6368_USBH_PHY=y
+CONFIG_PINCTRL=y
CONFIG_POWER_DOMAIN=y
CONFIG_BCM6328_POWER_DOMAIN=y
CONFIG_DM_RESET=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_EEPROM is not set
+CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPT is not set
# CONFIG_CMD_PART is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_DA850_LOWLEVEL=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_NR_DRAM_BANKS=1
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="USE_NOR,DIRECT_NOR_BOOT"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_CMD_IMLS=y
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_EEPROM is not set
+CONFIG_CMD_DM=y
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
# CONFIG_CMD_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CRC32_VERIFY=y
# CONFIG_CMD_EEPROM is not set
+CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPT is not set
CONFIG_CMD_NAND=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
+# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_MSM_GPIO=y
CONFIG_PM8916_GPIO=y
CONFIG_LED=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MSM=y
+CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_DM_PMIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
+CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DUALSPEED=n
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_ARCH_MT7620=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_CLK=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=57600
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_SYSRESET_SYSCON=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x9c000000
+CONFIG_ARCH_MT7620=y
+CONFIG_BOOT_ROM=y
+CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
+CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_CLK=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=57600
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_SYSRESET_SYSCON=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_ARCH_MT7620=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_CLK=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=57600
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_SYSRESET_SYSCON=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x9c000000
+CONFIG_ARCH_MT7620=y
+CONFIG_BOOT_ROM=y
+CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
+CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_TIME=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_CLK=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=57600
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_SYSRESET_SYSCON=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FSL_PFE=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_FSL_PFE=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_BLK=y
+CONFIG_DM_MMC=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DATE=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DATE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_TARGET_SAMA5D27_SOM1_EK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_DM_VIDEO=y
CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_TARGET_SAMA5D2_XPLAINED=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=83000000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_DM_VIDEO=y
CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_DM_VIDEO=y
CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_DM_VIDEO=y
CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_DM_VIDEO=y
CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_DM_VIDEO=y
CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
CONFIG_DM_DEMO_SHAPE=y
+CONFIG_BOARD=y
+CONFIG_BOARD_SANDBOX=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_OSD=y
+CONFIG_SANDBOX_OSD=y
CONFIG_WDT=y
CONFIG_WDT_SANDBOX=y
CONFIG_FS_CBFS=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
CONFIG_DM_DEMO_SHAPE=y
+CONFIG_BOARD=y
+CONFIG_BOARD_SANDBOX=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_SANDBOX=y
+CONFIG_OSD=y
+CONFIG_SANDBOX_OSD=y
CONFIG_WDT=y
CONFIG_WDT_SANDBOX=y
CONFIG_FS_CBFS=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SF=y
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
CONFIG_DM_DEMO_SHAPE=y
+CONFIG_BOARD=y
+CONFIG_BOARD_SANDBOX=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_OSD=y
+CONFIG_SANDBOX_OSD=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_LZ4=y
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SF=y
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
CONFIG_DM_DEMO_SHAPE=y
+CONFIG_BOARD=y
+CONFIG_BOARD_SANDBOX=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_OSD=y
+CONFIG_SANDBOX_OSD=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SF=y
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
CONFIG_DM_DEMO_SHAPE=y
+CONFIG_BOARD=y
+CONFIG_BOARD_SANDBOX=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_OSD=y
+CONFIG_SANDBOX_OSD=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
CONFIG_STM32_SDMMC2=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
# CONFIG_PINCTRL_FULL is not set
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR_STPMU1=y
CONFIG_SERIAL_RX_BUFFER=y
CONFIG_STM32_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
+# CONFIG_EFI_UNICODE_CAPITALIZATION is not set
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
+# CONFIG_EFI_UNICODE_CAPITALIZATION is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=-1
CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=-1
CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
CONFIG_FIT=y
CONFIG_BOOTDELAY=-1
CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
CONFIG_NR_DRAM_BANKS=1
# CONFIG_IMAGE_FORMAT_LEGACY is not set
CONFIG_BOOTDELAY=-1
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SYS_MALLOC_LEN=0x1000
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_BOOTDELAY=-1
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=-1
# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_ARCH_EARLY_INIT_R is not set
CONFIG_SPL_STACK_R=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
+CONFIG_DISPLAY=y
You should not define this property yourself in the device-tree, as it
may be overwritten without warning.
+
+firmware-loader property
+------------------------
+Multiple file system firmware loader nodes could be defined in device trees for
+multiple storage type and their default partition, then a property
+"firmware-loader" can be used to pass default firmware loader
+node(default storage type) to the firmware loader driver.
+
+Example
+-------
+/ {
+ chosen {
+ firmware-loader = &fs_loader0;
+ };
+
+ fs_loader0: fs-loader@0 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc 1>;
+ };
+};
--- /dev/null
+* File system firmware loader
+
+Required properties:
+--------------------
+
+- compatible: should contain "u-boot,fs-loader"
+- phandlepart: which block storage device and partition the image loading from,
+ this property is required for mmc, usb and sata. This is unsigned
+ 32-bit array. For example phandlepart=<&mmc_0 1>, meaning use
+ that MMC0 node pointer, partition 1.
+- mdtpart: which partition of ubi the image loading from, this property is
+ required for ubi and mounting.
+- ubivol: which volume of ubi the image loading from, this property is required
+ for ubi and mounting.
+
+Example of storage device and partition search set for mmc, usb, sata and
+ubi in device tree source as shown in below:
+
+ Example of storage type and device partition search set for mmc, usb,
+ sata and ubi as shown in below:
+ Example for mmc:
+ fs_loader0: fs-loader@0 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc_0 1>;
+ };
+
+ Example for usb:
+ fs_loader1: fs-loader@1 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&usb0 1>;
+ };
+
+ Example for sata:
+ fs_loader2: fs-loader@2 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&sata0 1>;
+ };
+
+ Example for ubi:
+ fs_loader3: fs-loader@3 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ mtdpart = "UBI",
+ ubivol = "ubi0";
+ };
--- /dev/null
+* broadcom bcm6838 pinctrl
+
+Required properties for the pinctrl driver:
+- compatible: "brcm,bcm6838-pinctrl"
+- regmap: specify the gpio test port syscon
+- brcm,pins-count: the number of pin
+- brcm,functions-count: the number of function
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+Example:
+
+ gpio_test_port: syscon@14e00294 {
+ compatible = "syscon";
+ reg = <0x14e00294 0x1c>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "brcm,bcm6838-pinctrl";
+ regmap = <&gpio_test_port>;
+ brcm,pins-count = <74>;
+ brcm,functions-count = <8>;
+
+ usb0: usb0 {
+ usb0_pwrflt {
+ pins = "69";
+ function = "1";
+ };
+ usb0_pwron {
+ pins = "70";
+ function = "1";
+ };
+ };
+ };
--- /dev/null
+* Guntermann & Drunck Integrated Hardware Systems OSD
+
+Required properties:
+- compatible: "gdsys,ihs_video_out"
+- reg: A combination of three register spaces:
+ - Register base for the video registers
+ - Register base for the OSD registers
+ - Address of the OSD video memory
+- mode: The initial resolution and frequency: "1024_768_60", "720_400_70", or
+ "640_480_70"
+- clk_gen: phandle to the pixel clock generator
+- dp_tx: phandle to the display associated with the OSD
+
+Example:
+
+fpga0_video0 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x100 0x40
+ 0x180 0x20
+ 0x1000 0x1000>;
+ dp_tx = <&fpga0_dp_video0>;
+ clk_gen = <&fpga0_video0_clkgen>;
+};
--- /dev/null
+Maxim DS24 families driver device binding - one wire protocol EEPROMS from Maxim
+=======================
+
+This memory needs to be connected to a onewire bus, as a child node.
+The bus will read the device serial number and match this node with a found
+device on the bus
+Also check doc/device-tree-bindings/w1 for onewire bus drivers
+
+Driver:
+- drivers/w1-eeprom/ds24xxx.c
+
+Software ds24xxx device-tree node properties:
+Required:
+* compatible = "maxim,ds24b33"
+or
+* compatible = "maxim,ds2431"
+Further memories can be added.
+
+Optional:
+* none
+
+Example:
+ eeprom1: eeprom@0 {
+ compatible = "maxim,ds24xxx";
+ }
+
+Example with parent bus:
+
+onewire_tm: onewire {
+ compatible = "w1-gpio";
+ gpios = <&pioA 32 0>;
+
+ eeprom1: eeprom@0 {
+ compatible = "maxim,ds24xxx";
+ }
+};
+
--- /dev/null
+Onewire EEPROM sandbox driver device binding - one wire protocol sandbox EEPROM
+=======================
+
+This memory needs to be connected to a onewire bus, as a child node.
+The bus will read the device serial number and match this node with a found
+device on the bus
+Also check doc/device-tree-bindings/w1 for onewire bus drivers
+
+Driver:
+- drivers/w1-eeprom/eep_sandbox.c
+
+Software ds24xxx device-tree node properties:
+Required:
+* compatible = "sandbox,w1-eeprom"
+
+Optional:
+* none
+
+Example:
+ eeprom1: eeprom@0 {
+ compatible = "sandbox,w1-eeprom";
+ }
+
+Example with parent bus:
+
+onewire_tm: onewire {
+ compatible = "w1-gpio";
+ gpios = <&gpio_a 8>;
+
+ eeprom1: eeprom@0 {
+ compatible = "sandbox,w1-eeprom";
+ }
+};
+
--- /dev/null
+W1 gpio device binding - one wire protocol over bitbanged gpio
+=======================
+
+
+Child nodes are required in device tree. The driver will detect
+the devices serial number and then search in the child nodes in the device tree
+for the proper node and try to match it with the device.
+
+Also check doc/device-tree-bindings/w1-eeprom for possible child nodes drivers
+
+Driver:
+- drivers/w1/w1-gpio.c
+
+Software w1 device-tree node properties:
+Required:
+* compatible = "w1-gpio";
+* gpios = <...>;
+ This is the gpio used for one wire protocol, using bitbanging
+
+Optional:
+* none
+
+Example:
+
+onewire_tm: onewire {
+ compatible = "w1-gpio";
+ gpios = <&pioA 32 0>;
+};
+
+Example with child:
+
+onewire_tm: onewire {
+ compatible = "w1-gpio";
+ gpios = <&pioA 32 0>;
+
+ eeprom1: eeprom@0 {
+ compatible = "maxim,ds24xxx";
+ }
+};
+
root driver is at device tree offset 0 (the root node, '/'), and its
children are the children of the root node.
+In order for a device tree to be valid, the content must be correct with
+respect to either device tree specification
+(https://www.devicetree.org/specifications/) or the device tree bindings that
+are found in the doc/device-tree-bindings directory. When not U-Boot specific
+the bindings in this directory tend to come from the Linux Kernel. As such
+certain design decisions may have been made already for us in terms of how
+specific devices are described and bound. In most circumstances we wish to
+retain compatibility without additional changes being made to the device tree
+source files.
Declaring Uclasses
------------------
--- /dev/null
+# Copyright (C) 2018 Intel Corporation <www.intel.com>
+#
+# SPDX-License-Identifier: GPL-2.0
+
+Introduction
+============
+
+This is file system firmware loader for U-Boot framework, which has very close
+to some Linux Firmware API. For the details of Linux Firmware API, you can refer
+to https://01.org/linuxgraphics/gfx-docs/drm/driver-api/firmware/index.html.
+
+File system firmware loader can be used to load whatever(firmware, image,
+and binary) from the storage device in file system format into target location
+such as memory, then consumer driver such as FPGA driver can program FPGA image
+from the target location into FPGA.
+
+To enable firmware loader, CONFIG_FS_LOADER need to be set at
+<board_name>_defconfig such as "CONFIG_FS_LOADER=y".
+
+Firmware Loader API core features
+---------------------------------
+
+Firmware storage device described in device tree source
+-------------------------------------------------------
+ For passing data like storage device phandle and partition where the
+ firmware loading from to the firmware loader driver, those data could be
+ defined in fs-loader node as shown in below:
+
+ Example for block device:
+ fs_loader0: fs-loader@0 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc 1>;
+ };
+
+ <&mmc 1> means block storage device pointer and its partition.
+
+ Above example is a description for block storage, but for UBI storage
+ device, it can be described in FDT as shown in below:
+
+ Example for ubi:
+ fs_loader1: fs-loader@1 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ mtdpart = "UBI",
+ ubivol = "ubi0";
+ };
+
+ Then, firmware_loader property would be set with the path of fs_loader
+ node under /chosen node such as:
+ /{
+ chosen {
+ firmware_loader = &fs_loader0;
+ };
+ };
+
+ However, this driver is also designed to support U-boot environment
+ variables, so all these data from FDT can be overwritten
+ through the U-boot environment variable during run time.
+ For examples:
+ "storage_interface" - Storage interface, it can be "mmc", "usb", "sata"
+ or "ubi".
+ "fw_dev_part" - Block device number and its partition, it can be "0:1".
+ "fw_ubi_mtdpart" - UBI device mtd partition, it can be "UBI".
+ "fw_ubi_volume" - UBI volume, it can be "ubi0".
+
+ When above environment variables are set, environment values would be
+ used instead of data from FDT.
+ The benefit of this design allows user to change storage attribute data
+ at run time through U-boot console and saving the setting as default
+ environment values in the storage for the next power cycle, so no
+ compilation is required for both driver and FDT.
+
+File system firmware Loader API
+-------------------------------
+
+int request_firmware_into_buf(struct device_platdata *plat,
+ const char *name,
+ void *buf, size_t size, u32 offset,
+ struct firmware **firmwarep)
+--------------------------------------------------------------------
+Load firmware into a previously allocated buffer
+
+Parameters:
+
+1. struct device_platdata *plat
+ Platform data such as storage and partition firmware loading from
+
+2. const char *name
+ name of firmware file
+
+3. void *buf
+ address of buffer to load firmware into
+
+4. size_t size
+ size of buffer
+
+5. u32 offset
+ offset of a file for start reading into buffer
+
+6. struct firmware **firmwarep
+ pointer to firmware image
+
+return:
+ size of total read
+ -ve when error
+
+Description:
+ The firmware is loaded directly into the buffer pointed to by buf and
+ the @firmwarep data member is pointed at buf
+
+Note: Memory would be allocated for firmware image, hence user should
+ free() *firmwarep and *firmwarep->priv structs after usage of
+ request_firmware_into_buf(), otherwise it will always leak memory
+ while subsequent calls of request_firmware_into_buf() with the same
+ *firmwarep argument. Those arguments can be free through calling API
+ below release_firmware();
+
+Example of creating firmware loader instance and calling
+request_firmware_into_buf API:
+ if (uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &dev)) {
+ request_firmware_into_buf(dev->plat, filename, buffer_location,
+ buffer_size, offset_ofreading, &fw);
+ }
+
+void release_firmware(struct firmware *firmware)
+------------------------------------------------
+Release the resource associated with a firmware image
+
+Parameters:
+
+1. struct firmware *firmware
+ Firmware resource to release
source "drivers/demo/Kconfig"
+source "drivers/board/Kconfig"
+
source "drivers/ddr/fsl/Kconfig"
source "drivers/dfu/Kconfig"
source "drivers/pwm/Kconfig"
+source "drivers/qe/Kconfig"
+
source "drivers/ram/Kconfig"
source "drivers/remoteproc/Kconfig"
source "drivers/video/Kconfig"
+source "drivers/w1/Kconfig"
+
+source "drivers/w1-eeprom/Kconfig"
+
source "drivers/watchdog/Kconfig"
config PHYS_TO_BUS
obj-$(CONFIG_DM_DEMO) += demo/
obj-$(CONFIG_BIOSEMU) += bios_emulator/
obj-y += block/
+obj-y += board/
obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-y += soc/
obj-y += thermal/
obj-y += axi/
+obj-$(CONFIG_W1) += w1/
+obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
endif
debug("cap 0x%x port_map 0x%x n_ports %d\n",
uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
+#if !defined(CONFIG_DM_SCSI)
if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
+#endif
for (i = 0; i < uc_priv->n_ports; i++) {
if (!(port_map & (1 << i)))
linkmap = uc_priv->link_port_map;
- for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
+ for (i = 0; i < uc_priv->n_ports; i++) {
if (((linkmap >> i) & 0x01)) {
if (ahci_port_start(uc_priv, (u8) i)) {
printf("Can not start port %d\n", i);
#define CEVA_TRANS_CFG 0x08000029
#define CEVA_AXICC_CFG 0x3fffffff
+/* for ls1021a */
+#define LS1021_AHCI_VEND_AXICC 0xC0
+#define LS1021_CEVA_PHY2_CFG 0x28183414
+#define LS1021_CEVA_PHY3_CFG 0x0e080e06
+#define LS1021_CEVA_PHY4_CFG 0x064a080b
+#define LS1021_CEVA_PHY5_CFG 0x2aa86470
+
/* ecc addr-val pair */
#define ECC_DIS_ADDR_CH2 0x80000000
-#define ECC_DIS_VAL_CH2 0x20140520
+#define ECC_DIS_VAL_CH2 0x20140520
+#define SATA_ECC_REG_ADDR 0x20220520
+#define SATA_ECC_DISABLE 0x00020000
enum ceva_soc {
CEVA_1V84,
CEVA_LS1012A,
+ CEVA_LS1021A,
+ CEVA_LS1043A,
};
struct ceva_sata_priv {
writel(tmp, base + AHCI_VEND_PTC);
break;
+ case CEVA_LS1021A:
+ writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR);
+ writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
+ writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
+ writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
+ writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
+ writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
+ writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
+ if (priv->flag & FLAG_COHERENT)
+ writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC);
+ break;
+
case CEVA_LS1012A:
+ case CEVA_LS1043A:
writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
static const struct udevice_id sata_ceva_ids[] = {
{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
+ { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
+ { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
{ }
};
return NULL;
}
+/**
+ * blk_get_by_device() - Get the block device descriptor for the given device
+ * @dev: Instance of a storage device
+ *
+ * Return: With block device descriptor on success , NULL if there is no such
+ * block device.
+ */
+struct blk_desc *blk_get_by_device(struct udevice *dev)
+{
+ struct udevice *child_dev, *next;
+
+ device_foreach_child_safe(child_dev, next, dev) {
+ if (device_get_uclass_id(child_dev) != UCLASS_BLK)
+ continue;
+
+ return dev_get_uclass_platdata(child_dev);
+ }
+
+ debug("%s: No block device found\n", __func__);
+
+ return NULL;
+}
+
/**
* get_desc() - Get the block device descriptor for the given device number
*
--- /dev/null
+menuconfig BOARD
+ bool "Device Information"
+ help
+ Support methods to query hardware configurations from internal
+ mechanisms (e.g. reading GPIO values, determining the presence of
+ devices on busses, etc.). This enables the usage of U-Boot with
+ modular board architectures.
+
+if BOARD
+
+
+config BOARD_GAZERBEAM
+ bool "Enable board driver for the Gazerbeam board"
+ help
+ Support querying device information for the gdsys Gazerbeam board.
+
+config BOARD_SANDBOX
+ bool "Enable board driver for the Sandbox board"
+ help
+ Support querying device information for the Sandbox boards.
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2017
+# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+obj-$(CONFIG_BOARD) += board-uclass.o
+obj-$(CONFIG_BOARD_GAZERBEAM) += gazerbeam.o
+obj-$(CONFIG_BOARD_SANDBOX) += sandbox.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <board.h>
+
+int board_get(struct udevice **devp)
+{
+ return uclass_first_device_err(UCLASS_BOARD, devp);
+}
+
+int board_detect(struct udevice *dev)
+{
+ struct board_ops *ops = board_get_ops(dev);
+
+ if (!ops->detect)
+ return -ENOSYS;
+
+ return ops->detect(dev);
+}
+
+int board_get_bool(struct udevice *dev, int id, bool *val)
+{
+ struct board_ops *ops = board_get_ops(dev);
+
+ if (!ops->get_bool)
+ return -ENOSYS;
+
+ return ops->get_bool(dev, id, val);
+}
+
+int board_get_int(struct udevice *dev, int id, int *val)
+{
+ struct board_ops *ops = board_get_ops(dev);
+
+ if (!ops->get_int)
+ return -ENOSYS;
+
+ return ops->get_int(dev, id, val);
+}
+
+int board_get_str(struct udevice *dev, int id, size_t size, char *val)
+{
+ struct board_ops *ops = board_get_ops(dev);
+
+ if (!ops->get_str)
+ return -ENOSYS;
+
+ return ops->get_str(dev, id, size, val);
+}
+
+UCLASS_DRIVER(board) = {
+ .id = UCLASS_BOARD,
+ .name = "board",
+ .post_bind = dm_scan_fdt_dev,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <board.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+
+#include "gazerbeam.h"
+
+/* Sequence number of I2C bus that holds the GPIO expanders */
+static const int I2C_BUS_SEQ_NO = 1;
+
+/* I2C address of SC/MC2 expander */
+static const int MC2_EXPANDER_ADDR = 0x20;
+/* I2C address of MC4 expander */
+static const int MC4_EXPANDER_ADDR = 0x22;
+
+/* Number of the GPIO to read the SC data from */
+static const int SC_GPIO_NO;
+/* Number of the GPIO to read the CON data from */
+static const int CON_GPIO_NO = 1;
+
+/**
+ * struct board_gazerbeam_priv - Private data structure for the gazerbeam board
+ * driver.
+ * @reset_gpios: GPIOs for the board's reset GPIOs.
+ * @var_gpios: GPIOs for the board's hardware variant GPIOs
+ * @ver_gpios: GPIOs for the board's hardware version GPIOs
+ * @variant: Container for the board's hardware variant (CON/CPU)
+ * @multichannel: Container for the board's multichannel variant (MC4/MC2/SC)
+ * @hwversion: Container for the board's hardware version
+ */
+struct board_gazerbeam_priv {
+ struct gpio_desc reset_gpios[2];
+ struct gpio_desc var_gpios[2];
+ struct gpio_desc ver_gpios[4];
+ int variant;
+ int multichannel;
+ int hwversion;
+};
+
+/**
+ * _read_board_variant_data() - Read variant information from the hardware.
+ * @dev: The board device for which to determine the multichannel and device
+ * type information.
+ *
+ * The data read from the board's hardware (mostly hard-wired GPIOs) is stored
+ * in the private data structure of the driver to be used by other driver
+ * methods.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+static int _read_board_variant_data(struct udevice *dev)
+{
+ struct board_gazerbeam_priv *priv = dev_get_priv(dev);
+ struct udevice *i2c_bus;
+ struct udevice *dummy;
+ char *listname;
+ int mc4, mc2, sc, con;
+ int gpio_num;
+ int res;
+
+ res = uclass_get_device_by_seq(UCLASS_I2C, I2C_BUS_SEQ_NO, &i2c_bus);
+ if (res) {
+ debug("%s: Could not get I2C bus %d (err = %d)\n",
+ dev->name, I2C_BUS_SEQ_NO, res);
+ return res;
+ }
+
+ if (!i2c_bus) {
+ debug("%s: Could not get I2C bus %d\n",
+ dev->name, I2C_BUS_SEQ_NO);
+ return -EIO;
+ }
+
+ mc2 = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy);
+ mc4 = !dm_i2c_probe(i2c_bus, MC4_EXPANDER_ADDR, 0, &dummy);
+
+ if (mc2 && mc4) {
+ debug("%s: Board hardware configuration inconsistent.\n",
+ dev->name);
+ return -EINVAL;
+ }
+
+ listname = mc2 ? "var-gpios-mc2" : "var-gpios-mc4";
+
+ gpio_num = gpio_request_list_by_name(dev, listname, priv->var_gpios,
+ ARRAY_SIZE(priv->var_gpios),
+ GPIOD_IS_IN);
+ if (gpio_num < 0) {
+ debug("%s: Requesting gpio list %s failed (err = %d).\n",
+ dev->name, listname, gpio_num);
+ return gpio_num;
+ }
+
+ sc = dm_gpio_get_value(&priv->var_gpios[SC_GPIO_NO]);
+ if (sc < 0) {
+ debug("%s: Error while reading 'sc' GPIO (err = %d)",
+ dev->name, sc);
+ return sc;
+ }
+
+ con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]);
+ if (con < 0) {
+ debug("%s: Error while reading 'con' GPIO (err = %d)",
+ dev->name, con);
+ return con;
+ }
+
+ if ((sc && mc2) || (sc && mc4) || (!sc && !mc2 && !mc4)) {
+ debug("%s: Board hardware configuration inconsistent.\n",
+ dev->name);
+ return -EINVAL;
+ }
+
+ priv->variant = con ? VAR_CON : VAR_CPU;
+
+ priv->multichannel = mc4 ? 4 : (mc2 ? 2 : (sc ? 1 : 0));
+
+ return 0;
+}
+
+/**
+ * _read_hwversion() - Read the hardware version from the board.
+ * @dev: The board device for which to read the hardware version.
+ *
+ * The hardware version read from the board (from hard-wired GPIOs) is stored
+ * in the private data structure of the driver to be used by other driver
+ * methods.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+static int _read_hwversion(struct udevice *dev)
+{
+ struct board_gazerbeam_priv *priv = dev_get_priv(dev);
+ int res;
+
+ res = gpio_request_list_by_name(dev, "ver-gpios", priv->ver_gpios,
+ ARRAY_SIZE(priv->ver_gpios),
+ GPIOD_IS_IN);
+ if (res < 0) {
+ debug("%s: Error getting GPIO list 'ver-gpios' (err = %d)\n",
+ dev->name, res);
+ return -ENODEV;
+ }
+
+ res = dm_gpio_get_values_as_int(priv->ver_gpios,
+ ARRAY_SIZE(priv->ver_gpios));
+ if (res < 0) {
+ debug("%s: Error reading HW version from expander (err = %d)\n",
+ dev->name, res);
+ return res;
+ }
+
+ priv->hwversion = res;
+
+ res = gpio_free_list(dev, priv->ver_gpios, ARRAY_SIZE(priv->ver_gpios));
+ if (res < 0) {
+ debug("%s: Error freeing HW version GPIO list (err = %d)\n",
+ dev->name, res);
+ return res;
+ }
+
+ return 0;
+}
+
+static int board_gazerbeam_detect(struct udevice *dev)
+{
+ int res;
+
+ res = _read_board_variant_data(dev);
+ if (res) {
+ debug("%s: Error reading multichannel variant (err = %d)\n",
+ dev->name, res);
+ return res;
+ }
+
+ res = _read_hwversion(dev);
+ if (res) {
+ debug("%s: Error reading hardware version (err = %d)\n",
+ dev->name, res);
+ return res;
+ }
+
+ return 0;
+}
+
+static int board_gazerbeam_get_int(struct udevice *dev, int id, int *val)
+{
+ struct board_gazerbeam_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case BOARD_MULTICHANNEL:
+ *val = priv->multichannel;
+ break;
+ case BOARD_VARIANT:
+ *val = priv->variant;
+ break;
+ case BOARD_HWVERSION:
+ *val = priv->hwversion;
+ break;
+ default:
+ debug("%s: Integer value %d unknown\n", dev->name, id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id board_gazerbeam_ids[] = {
+ { .compatible = "gdsys,board_gazerbeam" },
+ { /* sentinel */ }
+};
+
+static const struct board_ops board_gazerbeam_ops = {
+ .detect = board_gazerbeam_detect,
+ .get_int = board_gazerbeam_get_int,
+};
+
+static int board_gazerbeam_probe(struct udevice *dev)
+{
+ struct board_gazerbeam_priv *priv = dev_get_priv(dev);
+ int gpio_num, i;
+
+ gpio_num = gpio_request_list_by_name(dev, "reset-gpios",
+ priv->reset_gpios,
+ ARRAY_SIZE(priv->reset_gpios),
+ GPIOD_IS_OUT);
+
+ if (gpio_num < 0) {
+ debug("%s: Error getting GPIO list 'reset-gpios' (err = %d)\n",
+ dev->name, gpio_num);
+ return gpio_num;
+ }
+
+ /* Set startup-finished GPIOs */
+ for (i = 0; i < ARRAY_SIZE(priv->reset_gpios); i++) {
+ int res = dm_gpio_set_value(&priv->reset_gpios[i], 0);
+
+ if (res) {
+ debug("%s: Error while setting GPIO %d (err = %d)\n",
+ dev->name, i, res);
+ return res;
+ }
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(board_gazerbeam) = {
+ .name = "board_gazerbeam",
+ .id = UCLASS_BOARD,
+ .of_match = board_gazerbeam_ids,
+ .ops = &board_gazerbeam_ops,
+ .priv_auto_alloc_size = sizeof(struct board_gazerbeam_priv),
+ .probe = board_gazerbeam_probe,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+enum {
+ BOARD_MULTICHANNEL,
+ BOARD_VARIANT,
+ BOARD_HWVERSION,
+};
+
+enum {
+ VAR_CON,
+ VAR_CPU,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <board.h>
+
+#include "sandbox.h"
+
+struct board_sandbox_priv {
+ bool called_detect;
+ int test_i1;
+ int test_i2;
+};
+
+char vacation_spots[][64] = {"R'lyeh", "Dreamlands", "Plateau of Leng",
+ "Carcosa", "Yuggoth", "The Nameless City"};
+
+int board_sandbox_detect(struct udevice *dev)
+{
+ struct board_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->called_detect = true;
+ priv->test_i2 = 100;
+
+ return 0;
+}
+
+int board_sandbox_get_bool(struct udevice *dev, int id, bool *val)
+{
+ struct board_sandbox_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case BOOL_CALLED_DETECT:
+ /* Checks if the dectect method has been called */
+ *val = priv->called_detect;
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+int board_sandbox_get_int(struct udevice *dev, int id, int *val)
+{
+ struct board_sandbox_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case INT_TEST1:
+ *val = priv->test_i1;
+ /* Increments with every call */
+ priv->test_i1++;
+ return 0;
+ case INT_TEST2:
+ *val = priv->test_i2;
+ /* Decrements with every call */
+ priv->test_i2--;
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+int board_sandbox_get_str(struct udevice *dev, int id, size_t size, char *val)
+{
+ struct board_sandbox_priv *priv = dev_get_priv(dev);
+ int i1 = priv->test_i1;
+ int i2 = priv->test_i2;
+ int index = (i1 * i2) % ARRAY_SIZE(vacation_spots);
+
+ switch (id) {
+ case STR_VACATIONSPOT:
+ /* Picks a vacation spot depending on i1 and i2 */
+ snprintf(val, size, vacation_spots[index]);
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+static const struct udevice_id board_sandbox_ids[] = {
+ { .compatible = "sandbox,board_sandbox" },
+ { /* sentinel */ }
+};
+
+static const struct board_ops board_sandbox_ops = {
+ .detect = board_sandbox_detect,
+ .get_bool = board_sandbox_get_bool,
+ .get_int = board_sandbox_get_int,
+ .get_str = board_sandbox_get_str,
+};
+
+int board_sandbox_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+U_BOOT_DRIVER(board_sandbox) = {
+ .name = "board_sandbox",
+ .id = UCLASS_BOARD,
+ .of_match = board_sandbox_ids,
+ .ops = &board_sandbox_ops,
+ .priv_auto_alloc_size = sizeof(struct board_sandbox_priv),
+ .probe = board_sandbox_probe,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+enum {
+ BOOL_CALLED_DETECT,
+ INT_TEST1,
+ INT_TEST2,
+ STR_VACATIONSPOT,
+};
help
Enable this to support the cgu clocks on Synopsys ARC HSDK
+config CLK_VEXPRESS_OSC
+ bool "Enable driver for Arm Versatile Express OSC clock generators"
+ depends on CLK && VEXPRESS_CONFIG
+ help
+ This clock driver adds support for clock generators present on
+ Arm Versatile Express platforms.
+
config CLK_ZYNQ
bool "Enable clock driver support for Zynq"
depends on CLK && ARCH_ZYNQ
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Arm Ltd
+ * Author: Liviu Dudau <liviu.dudau@foss.arm.com>
+ *
+ */
+#define DEBUG
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <errno.h>
+#include <misc.h>
+
+#define CLK_FUNCTION BIT(20)
+
+struct vexpress_osc_clk_priv {
+ u8 osc;
+ ulong rate_min;
+ ulong rate_max;
+};
+
+static ulong vexpress_osc_clk_get_rate(struct clk *clk)
+{
+ int err;
+ u32 data;
+ struct udevice *vexpress_cfg = dev_get_parent(clk->dev);
+ struct vexpress_osc_clk_priv *priv = dev_get_priv(clk->dev);
+
+ data = CLK_FUNCTION | priv->osc;
+ err = misc_read(vexpress_cfg, 0, &data, sizeof(data));
+ if (err)
+ return err;
+
+ return data;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate)
+{
+ int err;
+ u32 buffer[2];
+ struct udevice *vexpress_cfg = dev_get_parent(clk->dev);
+ struct vexpress_osc_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (rate < priv->rate_min || rate > priv->rate_max)
+ return -EINVAL;
+
+ /*
+ * we are sending the parent the info about the oscillator
+ * and the value we want to set
+ */
+ buffer[0] = CLK_FUNCTION | priv->osc;
+ buffer[1] = rate;
+ err = misc_write(vexpress_cfg, 0, buffer, 2 * sizeof(u32));
+ if (err)
+ return err;
+
+ return rate;
+}
+#endif
+
+static struct clk_ops vexpress_osc_clk_ops = {
+ .get_rate = vexpress_osc_clk_get_rate,
+#ifndef CONFIG_SPL_BUILD
+ .set_rate = vexpress_osc_clk_set_rate,
+#endif
+};
+
+static int vexpress_osc_clk_probe(struct udevice *dev)
+{
+ struct vexpress_osc_clk_priv *priv = dev_get_priv(dev);
+ u32 values[2];
+ int err;
+
+ err = dev_read_u32_array(dev, "freq-range", values, 2);
+ if (err)
+ return err;
+ priv->rate_min = values[0];
+ priv->rate_max = values[1];
+
+ err = dev_read_u32_array(dev, "arm,vexpress-sysreg,func", values, 2);
+ if (err)
+ return err;
+
+ if (values[0] != 1) {
+ dev_err(dev, "Invalid VExpress function for clock, must be '1'");
+ return -EINVAL;
+ }
+ priv->osc = values[1];
+ debug("clk \"%s%d\", min freq %luHz, max freq %luHz\n", dev->name,
+ priv->osc, priv->rate_min, priv->rate_max);
+
+ return 0;
+}
+
+static const struct udevice_id vexpress_osc_clk_ids[] = {
+ { .compatible = "arm,vexpress-osc", },
+ {}
+};
+
+U_BOOT_DRIVER(vexpress_osc_clk) = {
+ .name = "vexpress_osc_clk",
+ .id = UCLASS_CLK,
+ .of_match = vexpress_osc_clk_ids,
+ .ops = &vexpress_osc_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct vexpress_osc_clk_priv),
+ .probe = vexpress_osc_clk_probe,
+};
return 0;
}
+/**
+ * device_find_by_ofnode() - Return device associated with given ofnode
+ *
+ * The returned device is *not* activated.
+ *
+ * @node: The ofnode for which a associated device should be looked up
+ * @devp: Pointer to structure to hold the found device
+ * Return: 0 if OK, -ve on error
+ */
+static int device_find_by_ofnode(ofnode node, struct udevice **devp)
+{
+ struct uclass *uc;
+ struct udevice *dev;
+ int ret;
+
+ list_for_each_entry(uc, &gd->uclass_root, sibling_node) {
+ ret = uclass_find_device_by_ofnode(uc->uc_drv->id, node,
+ &dev);
+ if (!ret || dev) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
int device_get_child(struct udevice *parent, int index, struct udevice **devp)
{
struct udevice *dev;
return !fdt_node_check_compatible(fdt, 0, compat);
}
+
+int dev_disable_by_path(const char *path)
+{
+ struct uclass *uc;
+ ofnode node = ofnode_path(path);
+ struct udevice *dev;
+ int ret = 1;
+
+ if (!of_live_active())
+ return -ENOSYS;
+
+ list_for_each_entry(uc, &gd->uclass_root, sibling_node) {
+ ret = uclass_find_device_by_ofnode(uc->uc_drv->id, node, &dev);
+ if (!ret)
+ break;
+ }
+
+ if (ret)
+ return ret;
+
+ ret = device_remove(dev, DM_REMOVE_NORMAL);
+ if (ret)
+ return ret;
+
+ ret = device_unbind(dev);
+ if (ret)
+ return ret;
+
+ return ofnode_set_enabled(node, false);
+}
+
+int dev_enable_by_path(const char *path)
+{
+ ofnode node = ofnode_path(path);
+ ofnode pnode = ofnode_get_parent(node);
+ struct udevice *parent;
+ int ret = 1;
+
+ if (!of_live_active())
+ return -ENOSYS;
+
+ ret = device_find_by_ofnode(pnode, &parent);
+ if (ret)
+ return ret;
+
+ ret = ofnode_set_enabled(node, true);
+ if (ret)
+ return ret;
+
+ return lists_bind_fdt(parent, node, NULL);
+}
propname, propval, proplen));
}
}
+
+int ofnode_write_prop(ofnode node, const char *propname, int len,
+ const void *value)
+{
+ const struct device_node *np = ofnode_to_np(node);
+ struct property *pp;
+ struct property *pp_last = NULL;
+ struct property *new;
+
+ if (!of_live_active())
+ return -ENOSYS;
+
+ if (!np)
+ return -EINVAL;
+
+ for (pp = np->properties; pp; pp = pp->next) {
+ if (strcmp(pp->name, propname) == 0) {
+ /* Property exists -> change value */
+ pp->value = (void *)value;
+ pp->length = len;
+ return 0;
+ }
+ pp_last = pp;
+ }
+
+ if (!pp_last)
+ return -ENOENT;
+
+ /* Property does not exist -> append new property */
+ new = malloc(sizeof(struct property));
+ if (!new)
+ return -ENOMEM;
+
+ new->name = strdup(propname);
+ if (!new->name)
+ return -ENOMEM;
+
+ new->value = (void *)value;
+ new->length = len;
+ new->next = NULL;
+
+ pp_last->next = new;
+
+ return 0;
+}
+
+int ofnode_write_string(ofnode node, const char *propname, const char *value)
+{
+ if (!of_live_active())
+ return -ENOSYS;
+
+ assert(ofnode_valid(node));
+
+ debug("%s: %s = %s", __func__, propname, value);
+
+ return ofnode_write_prop(node, propname, strlen(value) + 1, value);
+}
+
+int ofnode_set_enabled(ofnode node, bool value)
+{
+ if (!of_live_active())
+ return -ENOSYS;
+
+ assert(ofnode_valid(node));
+
+ if (value)
+ return ofnode_write_string(node, "status", "okay");
+ else
+ return ofnode_write_string(node, "status", "disable");
+}
config FIRMWARE
- bool
+ bool "Enable Firmware driver support"
config ARM_PSCI_FW
bool
obj-$(CONFIG_FIRMWARE) += firmware-uclass.o
obj-$(CONFIG_ARM_PSCI_FW) += psci.o
obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
+obj-$(CONFIG_SANDBOX) += firmware-sandbox.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * sandbox firmware driver
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+
+static const struct udevice_id generic_sandbox_firmware_ids[] = {
+ { .compatible = "sandbox,firmware" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_firmware) = {
+ .name = "sandbox_firmware",
+ .id = UCLASS_FIRMWARE,
+ .of_match = generic_sandbox_firmware_ids,
+};
UCLASS_DRIVER(firmware) = {
.id = UCLASS_FIRMWARE,
.name = "firmware",
-#if CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.post_bind = dm_scan_fdt_dev,
#endif
};
new_buf[i] = load_word(&buf[i], swap);
buf = new_buf;
- } else if (swap != SWAP_DONE) {
+ } else if ((swap != SWAP_DONE) &&
+ (zynqmp_pmufw_version() <= PMUFW_V1_0)) {
/* For bitstream which are aligned */
u32 *new_buf = (u32 *)buf;
bitstream_type bstype)
{
ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
- u32 swap;
+ u32 swap = 0;
ulong bin_buf;
int ret;
u32 buf_lo, buf_hi;
u32 ret_payload[PAYLOAD_ARG_CNT];
-
- if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
- return FPGA_FAIL;
+ bool xilfpga_old = false;
+
+ if (zynqmp_pmufw_version() <= PMUFW_V1_0) {
+ puts("WARN: PMUFW v1.0 or less is detected\n");
+ puts("WARN: Not all bitstream formats are supported\n");
+ puts("WARN: Please upgrade PMUFW\n");
+ xilfpga_old = true;
+ if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
+ return FPGA_FAIL;
+ bsizeptr = (u32 *)&bsize;
+ flush_dcache_range((ulong)bsizeptr,
+ (ulong)bsizeptr + sizeof(size_t));
+ bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
+ }
bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
- bsizeptr = (u32 *)&bsize;
debug("%s called!\n", __func__);
flush_dcache_range(bin_buf, bin_buf + bsize);
- flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
buf_lo = (u32)bin_buf;
buf_hi = upper_32_bits(bin_buf);
- bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
- ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
- (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
+
+ if (xilfpga_old)
+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+ (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
+ else
+ ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
+ (u32)bsize, 0, ret_payload);
+
if (ret)
debug("PL FPGA LOAD fail\n");
help
Support for serdes found on MPC83xx SoCs.
+config FS_LOADER
+ bool "Enable loader driver for file system"
+ help
+ This is file system generic loader which can be used to load
+ the file image from the storage into target such as memory.
+
+ The consumer driver would then use this loader to program whatever,
+ ie. the FPGA device.
+
endmenu
obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
+obj-$(CONFIG_FS_LOADER) += fs_loader.o
--- /dev/null
+/*
+ * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <blk.h>
+#include <fs.h>
+#include <fs_loader.h>
+#include <linux/string.h>
+#include <mapmem.h>
+#include <malloc.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct firmware_priv {
+ const char *name; /* Filename */
+ u32 offset; /* Offset of reading a file */
+};
+
+#ifdef CONFIG_CMD_UBIFS
+static int mount_ubifs(char *mtdpart, char *ubivol)
+{
+ int ret = ubi_part(mtdpart, NULL);
+
+ if (ret) {
+ debug("Cannot find mtd partition %s\n", mtdpart);
+ return ret;
+ }
+
+ return cmd_ubifs_mount(ubivol);
+}
+
+static int umount_ubifs(void)
+{
+ return cmd_ubifs_umount();
+}
+#else
+static int mount_ubifs(char *mtdpart, char *ubivol)
+{
+ debug("Error: Cannot load image: no UBIFS support\n");
+ return -ENOSYS;
+}
+#endif
+
+static int select_fs_dev(struct device_platdata *plat)
+{
+ int ret;
+
+ if (plat->phandlepart.phandle) {
+ ofnode node;
+
+ node = ofnode_get_by_phandle(plat->phandlepart.phandle);
+
+ int of_offset = ofnode_to_offset(node);
+
+ struct udevice *dev;
+
+ ret = device_get_global_by_of_offset(of_offset, &dev);
+ if (!ret) {
+ struct blk_desc *desc = blk_get_by_device(dev);
+ if (desc) {
+ ret = fs_set_blk_dev_with_part(desc,
+ plat->phandlepart.partition);
+ } else {
+ debug("%s: No device found\n", __func__);
+ return -ENODEV;
+ }
+ }
+ } else if (plat->mtdpart && plat->ubivol) {
+ ret = mount_ubifs(plat->mtdpart, plat->ubivol);
+ if (ret)
+ return ret;
+
+ ret = fs_set_blk_dev("ubi", NULL, FS_TYPE_UBIFS);
+ } else {
+ debug("Error: unsupported storage device.\n");
+ return -ENODEV;
+ }
+
+ if (ret)
+ debug("Error: could not access storage.\n");
+
+ return ret;
+}
+
+/**
+ * _request_firmware_prepare - Prepare firmware struct.
+ *
+ * @name: Name of firmware file.
+ * @dbuf: Address of buffer to load firmware into.
+ * @size: Size of buffer.
+ * @offset: Offset of a file for start reading into buffer.
+ * @firmwarep: Pointer to pointer to firmware image.
+ *
+ * Return: Negative value if fail, 0 for successful.
+ */
+static int _request_firmware_prepare(const char *name, void *dbuf,
+ size_t size, u32 offset,
+ struct firmware **firmwarep)
+{
+ if (!name || name[0] == '\0')
+ return -EINVAL;
+
+ /* No memory allocation is required if *firmwarep is allocated */
+ if (!(*firmwarep)) {
+ (*firmwarep) = calloc(1, sizeof(struct firmware));
+ if (!(*firmwarep))
+ return -ENOMEM;
+
+ (*firmwarep)->priv = calloc(1, sizeof(struct firmware_priv));
+ if (!(*firmwarep)->priv) {
+ free(*firmwarep);
+ return -ENOMEM;
+ }
+ } else if (!(*firmwarep)->priv) {
+ (*firmwarep)->priv = calloc(1, sizeof(struct firmware_priv));
+ if (!(*firmwarep)->priv) {
+ free(*firmwarep);
+ return -ENOMEM;
+ }
+ }
+
+ ((struct firmware_priv *)((*firmwarep)->priv))->name = name;
+ ((struct firmware_priv *)((*firmwarep)->priv))->offset = offset;
+ (*firmwarep)->data = dbuf;
+ (*firmwarep)->size = size;
+
+ return 0;
+}
+
+/**
+ * release_firmware - Release the resource associated with a firmware image
+ * @firmware: Firmware resource to release
+ */
+void release_firmware(struct firmware *firmware)
+{
+ if (firmware) {
+ if (firmware->priv) {
+ free(firmware->priv);
+ firmware->priv = NULL;
+ }
+ free(firmware);
+ }
+}
+
+/**
+ * fw_get_filesystem_firmware - load firmware into an allocated buffer.
+ * @plat: Platform data such as storage and partition firmware loading from.
+ * @firmware: pointer to firmware image.
+ *
+ * Return: Size of total read, negative value when error.
+ */
+static int fw_get_filesystem_firmware(struct device_platdata *plat,
+ struct firmware *firmware)
+{
+ struct firmware_priv *fw_priv = NULL;
+ loff_t actread;
+ char *storage_interface, *dev_part, *ubi_mtdpart, *ubi_volume;
+ int ret;
+
+ storage_interface = env_get("storage_interface");
+ dev_part = env_get("fw_dev_part");
+ ubi_mtdpart = env_get("fw_ubi_mtdpart");
+ ubi_volume = env_get("fw_ubi_volume");
+
+ if (storage_interface && dev_part) {
+ ret = fs_set_blk_dev(storage_interface, dev_part, FS_TYPE_ANY);
+ } else if (storage_interface && ubi_mtdpart && ubi_volume) {
+ ret = mount_ubifs(ubi_mtdpart, ubi_volume);
+ if (ret)
+ return ret;
+
+ if (!strcmp("ubi", storage_interface))
+ ret = fs_set_blk_dev(storage_interface, NULL,
+ FS_TYPE_UBIFS);
+ else
+ ret = -ENODEV;
+ } else {
+ ret = select_fs_dev(plat);
+ }
+
+ if (ret)
+ goto out;
+
+ fw_priv = firmware->priv;
+
+ ret = fs_read(fw_priv->name, (ulong)map_to_sysmem(firmware->data),
+ fw_priv->offset, firmware->size, &actread);
+ if (ret) {
+ debug("Error: %d Failed to read %s from flash %lld != %d.\n",
+ ret, fw_priv->name, actread, firmware->size);
+ } else {
+ ret = actread;
+ }
+
+out:
+#ifdef CONFIG_CMD_UBIFS
+ umount_ubifs();
+#endif
+ return ret;
+}
+
+/**
+ * request_firmware_into_buf - Load firmware into a previously allocated buffer.
+ * @plat: Platform data such as storage and partition firmware loading from.
+ * @name: Name of firmware file.
+ * @buf: Address of buffer to load firmware into.
+ * @size: Size of buffer.
+ * @offset: Offset of a file for start reading into buffer.
+ * @firmwarep: Pointer to firmware image.
+ *
+ * The firmware is loaded directly into the buffer pointed to by @buf and
+ * the @firmwarep data member is pointed at @buf.
+ *
+ * Return: Size of total read, negative value when error.
+ */
+int request_firmware_into_buf(struct device_platdata *plat,
+ const char *name,
+ void *buf, size_t size, u32 offset,
+ struct firmware **firmwarep)
+{
+ int ret;
+
+ if (!plat)
+ return -EINVAL;
+
+ ret = _request_firmware_prepare(name, buf, size, offset, firmwarep);
+ if (ret < 0) /* error */
+ return ret;
+
+ ret = fw_get_filesystem_firmware(plat, *firmwarep);
+
+ return ret;
+}
+
+static int fs_loader_ofdata_to_platdata(struct udevice *dev)
+{
+ const char *fs_loader_path;
+ u32 phandlepart[2];
+
+ fs_loader_path = ofnode_get_chosen_prop("firmware-loader");
+
+ if (fs_loader_path) {
+ ofnode fs_loader_node;
+
+ fs_loader_node = ofnode_path(fs_loader_path);
+ if (ofnode_valid(fs_loader_node)) {
+ struct device_platdata *plat;
+ plat = dev->platdata;
+
+ if (!ofnode_read_u32_array(fs_loader_node,
+ "phandlepart",
+ phandlepart, 2)) {
+ plat->phandlepart.phandle = phandlepart[0];
+ plat->phandlepart.partition = phandlepart[1];
+ }
+
+ plat->mtdpart = (char *)ofnode_read_string(
+ fs_loader_node, "mtdpart");
+
+ plat->ubivol = (char *)ofnode_read_string(
+ fs_loader_node, "ubivol");
+ }
+ }
+
+ return 0;
+}
+
+static int fs_loader_probe(struct udevice *dev)
+{
+ return 0;
+};
+
+static const struct udevice_id fs_loader_ids[] = {
+ { .compatible = "u-boot,fs-loader"},
+ { }
+};
+
+U_BOOT_DRIVER(fs_loader) = {
+ .name = "fs-loader",
+ .id = UCLASS_FS_FIRMWARE_LOADER,
+ .of_match = fs_loader_ids,
+ .probe = fs_loader_probe,
+ .ofdata_to_platdata = fs_loader_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct device_platdata),
+};
+
+UCLASS_DRIVER(fs_loader) = {
+ .id = UCLASS_FS_FIRMWARE_LOADER,
+ .name = "fs-loader",
+};
out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
}
#else
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
int i;
for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
char compat[64];
int compat_len;
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
int smmu_ph = fdt_get_smmu_phandle(blob);
#endif
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
while (off != -FDT_ERR_NOTFOUND) {
-#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1043A) || \
+defined(CONFIG_ARCH_LS1046A)
#ifdef CONFIG_FSL_CORENET
u32 liodns[2];
#endif
int j;
#endif
-#endif /* CONFIG_PPC || CONFIG_ARCH_LS1046A */
+#endif /* CONFIG_PPC || CONFIG_ARCH_LS1043A || CONFIG_ARCH_LS1046A */
err = fdt_setprop(blob, off, "compatible", compat, compat_len);
if (err < 0)
goto err;
goto err;
#endif
#else
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
if (smmu_ph >= 0) {
u32 icids[3];
#if CONFIG_IS_ENABLED(DM_MMC)
struct gpio_desc cd_gpio; /* Change Detect GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
- bool cd_inverted;
#else
int cd_gpio;
int wp_gpio;
/* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
pbias_lite &= ~PBIASLITEVMODE0;
#endif
+#ifdef CONFIG_TARGET_OMAP3_LOGIC
+ /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
+ pbias_lite &= ~PBIASLITEVMODE1;
+#endif
#ifdef CONFIG_MMC_OMAP36XX_PINS
if (get_cpu_family() == CPU_OMAP36XX) {
/* Disable extended drain IO before changing PBIAS */
#if CONFIG_IS_ENABLED(DM_MMC)
static int omap_hsmmc_getcd(struct udevice *dev)
{
- struct omap_hsmmc_data *priv = dev_get_priv(dev);
int value = -1;
#if CONFIG_IS_ENABLED(DM_GPIO)
+ struct omap_hsmmc_data *priv = dev_get_priv(dev);
value = dm_gpio_get_value(&priv->cd_gpio);
#endif
/* if no CD return as 1 */
if (value < 0)
return 1;
- if (priv->cd_inverted)
- return !value;
return value;
}
}
#endif
-#ifdef OMAP_HSMMC_USE_GPIO
- plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
-#endif
-
return 0;
}
#endif
priv->base_addr = plat->base_addr;
priv->controller_flags = plat->controller_flags;
priv->hw_rev = plat->hw_rev;
-#ifdef OMAP_HSMMC_USE_GPIO
- priv->cd_inverted = plat->cd_inverted;
-#endif
#ifdef CONFIG_BLK
mmc = plat->mmc;
return 1;
}
+static void cpsw_phy_addr_update(struct cpsw_priv *priv)
+{
+ struct cpsw_platform_data *data = &priv->data;
+ u16 alive = mdio_regs->alive & GENMASK(15, 0);
+ int active = data->active_slave;
+ int new_addr = ffs(alive) - 1;
+
+ /*
+ * If there is only one phy alive and its address does not match
+ * that of active slave, then phy address can safely be updated.
+ */
+ if (hweight16(alive) == 1 &&
+ data->slave_data[active].phy_addr != new_addr) {
+ printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
+ active, data->slave_data[active].phy_addr, new_addr);
+ data->slave_data[active].phy_addr = new_addr;
+ }
+}
+
int _cpsw_register(struct cpsw_priv *priv)
{
struct cpsw_slave *slave;
}
cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div);
+
+ cpsw_phy_addr_update(priv);
+
priv->bus = miiphy_get_dev_by_name(priv->dev->name);
for_active_slave(slave, priv)
cpsw_phy_init(priv, slave);
return 0;
}
+int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
+{
+ struct cpsw_priv *priv = dev_get_priv(dev);
+ struct cpsw_platform_data *data = &priv->data;
+
+ return data->slave_data[slave].phy_addr;
+}
static const struct udevice_id cpsw_eth_ids[] = {
{ .compatible = "ti,cpsw" },
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
addr);
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
ft_fixup_port(blob, &fm_info[i],
"fsl,fman-1g-mac");
} else {
- if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec"))
+ if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-xgec") &&
+ ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec"))
ft_fixup_port(blob, &fm_info[i],
"fsl,fman-10g-mac");
}
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*/
#include <common.h>
#include <errno.h>
#define MC_BOOT_ENV_VAR "mcinitcmd"
DECLARE_GLOBAL_DATA_PTR;
+static int mc_memset_resv_ram;
static int mc_boot_status = -1;
static int mc_dpl_applied = -1;
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
MC_FIXUP_DPL);
}
+void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
+{
+ u32 *prop;
+ u32 iommu_map[4];
+ int offset;
+ int lenp;
+
+ /* find fsl-mc node */
+ offset = fdt_path_offset(blob, "/soc/fsl-mc");
+ if (offset < 0)
+ offset = fdt_path_offset(blob, "/fsl-mc");
+ if (offset < 0) {
+ printf("%s: fsl-mc: ERR: fsl-mc node not found in DT, err %d\n",
+ __func__, offset);
+ return;
+ }
+
+ prop = fdt_getprop_w(blob, offset, "iommu-map", &lenp);
+ if (!prop) {
+ debug("%s: fsl-mc: ERR: missing iommu-map in fsl-mc bus node\n",
+ __func__);
+ return;
+ }
+
+ iommu_map[0] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
+ iommu_map[1] = *++prop;
+ iommu_map[2] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
+ iommu_map[3] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_END -
+ FSL_DPAA2_STREAM_ID_START + 1);
+
+ fdt_setprop_inplace(blob, offset, "iommu-map",
+ iommu_map, sizeof(iommu_map));
+}
+
static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
struct eth_device *eth_dev)
{
{
size_t mc_ram_size = mc_get_dram_block_size();
+ if (!mc_memset_resv_ram || (get_mc_boot_status() < 0)) {
+ mc_memset_resv_ram = 1;
+ memset((void *)gd->arch.resv_ram, 0, mc_ram_size);
+ }
+
return (gd->arch.resv_ram + mc_ram_size - 1) &
MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
}
if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
sgmii_2500 = 1;
- printf("%s %d\n", __func__, priv->gemac_port);
/* PCS configuration done with corresponding GEMAC */
bus.priv = gem_info[priv->gemac_port].gemac_base;
/* Hardcode for now */
priv->phyaddr = -1;
- if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
- &phandle_args)) {
- debug("phy-handle does not exist %s\n", dev->name);
- return -ENOENT;
+ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args)) {
+ debug("phy-handle does exist %s\n", dev->name);
+ priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
+ "reg", -1);
+ priv->phy_of_node = phandle_args.node;
+ priv->max_speed = ofnode_read_u32_default(phandle_args.node,
+ "max-speed",
+ SPEED_1000);
}
- priv->phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1);
- priv->phy_of_node = phandle_args.node;
phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
}
priv->interface = pdata->phy_interface;
- priv->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
This is the generic phy driver for the Amlogic Meson GXL
USB2 and USB3 PHYS.
+config MSM8916_USB_PHY
+ bool "Qualcomm MSM8916 USB PHY support"
+ depends on PHY
+ help
+ Support the USB PHY in msm8916
+
+ This PHY is found on qualcomm dragonboard410c development board.
+
endmenu
obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
+obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <usb/ehci-ci.h>
+#include <usb/ulpi.h>
+#include <asm/io.h>
+
+/* PHY viewport regs */
+#define ULPI_MISC_A_READ 0x96
+#define ULPI_MISC_A_SET 0x97
+#define ULPI_MISC_A_CLEAR 0x98
+#define ULPI_MISC_A_VBUSVLDEXT BIT(0)
+#define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1)
+#define GEN2_SESS_VLD_CTRL_EN BIT(7)
+#define SESS_VLD_CTRL BIT(25)
+
+struct msm_phy_priv {
+ void __iomem *regs;
+ struct usb_ehci *ehci; /* Start of IP core*/
+ struct ulpi_viewport ulpi_vp; /* ULPI Viewport */
+};
+
+static int msm_phy_power_on(struct phy *phy)
+{
+ struct msm_phy_priv *priv = dev_get_priv(phy->dev);
+
+ /* Select and enable external configuration with USB PHY */
+ ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_SET,
+ ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
+
+ return 0;
+}
+
+static int msm_phy_power_off(struct phy *phy)
+{
+ struct msm_phy_priv *priv = dev_get_priv(phy->dev);
+
+ /* Disable VBUS mimicing in the controller. */
+ ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR,
+ ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
+ return 0;
+}
+
+static int msm_phy_reset(struct phy *phy)
+{
+ struct msm_phy_priv *p = dev_get_priv(phy->dev);
+
+ /* select ULPI phy */
+ writel(PORT_PTS_ULPI, &p->ehci->portsc);
+
+ /* Enable sess_vld */
+ setbits_le32(&p->ehci->genconfig2, GEN2_SESS_VLD_CTRL_EN);
+
+ /* Enable external vbus configuration in the LINK */
+ setbits_le32(&p->ehci->usbcmd, SESS_VLD_CTRL);
+
+ /* USB_OTG_HS_AHB_BURST */
+ writel(0x0, &p->ehci->sbuscfg);
+
+ /* USB_OTG_HS_AHB_MODE: HPROT_MODE */
+ /* Bus access related config. */
+ writel(0x08, &p->ehci->sbusmode);
+
+ return 0;
+}
+
+static int msm_phy_probe(struct udevice *dev)
+{
+ struct msm_phy_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_remap_addr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ priv->ehci = (struct usb_ehci *)priv->regs;
+ priv->ulpi_vp.port_num = 0;
+
+ /* Warning: this will not work if viewport address is > 64 bit due to
+ * ULPI design.
+ */
+ priv->ulpi_vp.viewport_addr = (phys_addr_t)&priv->ehci->ulpi_viewpoint;
+
+ return 0;
+}
+
+static struct phy_ops msm_phy_ops = {
+ .power_on = msm_phy_power_on,
+ .power_off = msm_phy_power_off,
+ .reset = msm_phy_reset,
+};
+
+static const struct udevice_id msm_phy_ids[] = {
+ { .compatible = "qcom,apq8016-usbphy" },
+ { }
+};
+
+U_BOOT_DRIVER(msm8916_usbphy) = {
+ .name = "msm8916_usbphy",
+ .id = UCLASS_PHY,
+ .of_match = msm_phy_ids,
+ .ops = &msm_phy_ops,
+ .probe = msm_phy_probe,
+ .priv_auto_alloc_size = sizeof(struct msm_phy_priv),
+};
help
Support pin multiplexing and pin configuration control on
Broadcom's 283x family of SoCs.
+
+config PINCTRL_BCM6838
+ depends on ARCH_BMIPS && PINCTRL_FULL && OF_CONTROL
+ default y
+ bool "Broadcom 6838 family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Broadcom's 6838 family of SoCs.
# https://spdx.org/licenses
obj-$(CONFIG_PINCTRL_BCM283X) += pinctrl-bcm283x.o
+obj-$(CONFIG_PINCTRL_BCM6838) += pinctrl-bcm6838.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <dm/pinctrl.h>
+
+#define BCM6838_CMD_LOAD_MUX 0x21
+
+#define BCM6838_FUNC_OFFS 12
+#define BCM6838_FUNC_MASK (0x37 << BCM6838_FUNC_OFFS)
+#define BCM6838_PIN_OFFS 0
+#define BCM6838_PIN_MASK (0xfff << BCM6838_PIN_OFFS)
+
+#define BCM6838_MAX_PIN_NAME_LEN 8
+static char bcm6838_pin_name[BCM6838_MAX_PIN_NAME_LEN];
+
+#define BCM6838_MAX_FUNC_NAME_LEN 8
+static char bcm6838_func_name[BCM6838_MAX_FUNC_NAME_LEN];
+
+struct bcm6838_test_port_hw {
+ unsigned long port_blk_data1;
+ unsigned long port_blk_data2;
+ unsigned long port_command;
+};
+
+static const struct bcm6838_test_port_hw bcm6838_hw = {
+ .port_blk_data1 = 0x10,
+ .port_blk_data2 = 0x14,
+ .port_command = 0x18
+};
+
+struct bcm6838_pinctrl_priv {
+ const struct bcm6838_test_port_hw *hw;
+ struct regmap *regmap;
+ u32 pins_count;
+ u32 functions_count;
+};
+
+int bcm6838_pinctrl_get_pins_count(struct udevice *dev)
+{
+ struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->pins_count;
+}
+
+const char *bcm6838_pinctrl_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ snprintf(bcm6838_pin_name, BCM6838_MAX_PIN_NAME_LEN, "%u", selector);
+ return bcm6838_pin_name;
+}
+
+int bcm6838_pinctrl_get_functions_count(struct udevice *dev)
+{
+ struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->functions_count;
+}
+
+const char *bcm6838_pinctrl_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ snprintf(bcm6838_func_name, BCM6838_MAX_FUNC_NAME_LEN, "%u", selector);
+ return bcm6838_func_name;
+}
+
+int bcm6838_pinctrl_pinmux_set(struct udevice *dev,
+ unsigned int pin_selector,
+ unsigned int func_selector)
+{
+ struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct bcm6838_test_port_hw *hw = priv->hw;
+ unsigned int data;
+
+ regmap_write(priv->regmap, hw->port_blk_data1, 0);
+ data = (func_selector << BCM6838_FUNC_OFFS) & BCM6838_FUNC_MASK;
+ data |= (pin_selector << BCM6838_PIN_OFFS) & BCM6838_PIN_MASK;
+ regmap_write(priv->regmap, hw->port_blk_data2, data);
+ regmap_write(priv->regmap, hw->port_command, BCM6838_CMD_LOAD_MUX);
+
+ return 0;
+}
+
+int bcm6838_pinctrl_probe(struct udevice *dev)
+{
+ struct bcm6838_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct bcm6838_test_port_hw *hw =
+ (const struct bcm6838_test_port_hw *)dev_get_driver_data(dev);
+ int err;
+ u32 phandle;
+ ofnode node;
+
+ err = ofnode_read_u32(dev_ofnode(dev), "regmap", &phandle);
+ if (err) {
+ dev_err(dev, "%s: unable to read regmap\n", __func__);
+ goto out;
+ }
+
+ node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "%s: unable to find node\n", __func__);
+ err = -EINVAL;
+ goto out;
+ }
+
+ priv->regmap = syscon_node_to_regmap(node);
+ if (!priv->regmap) {
+ dev_err(dev, "%s: unable to find regmap\n", __func__);
+ err = -ENODEV;
+ goto out;
+ }
+
+ err = ofnode_read_u32(dev_ofnode(dev), "brcm,pins-count",
+ &priv->pins_count);
+ if (err) {
+ dev_err(dev, "%s: unable to read brcm,pins-count\n",
+ __func__);
+ goto out;
+ }
+
+ err = ofnode_read_u32(dev_ofnode(dev), "brcm,functions-count",
+ &priv->functions_count);
+ if (err) {
+ dev_err(dev, "%s: unable to read brcm,functions-count\n",
+ __func__);
+ goto out;
+ }
+
+ priv->hw = hw;
+
+ out:
+ return err;
+}
+
+const struct pinctrl_ops bcm6838_pinctrl_ops = {
+ .set_state = pinctrl_generic_set_state,
+ .get_pins_count = bcm6838_pinctrl_get_pins_count,
+ .get_pin_name = bcm6838_pinctrl_get_pin_name,
+ .get_functions_count = bcm6838_pinctrl_get_functions_count,
+ .get_function_name = bcm6838_pinctrl_get_function_name,
+ .pinmux_set = bcm6838_pinctrl_pinmux_set,
+};
+
+static const struct udevice_id bcm6838_pinctrl_match[] = {
+ {
+ .compatible = "brcm,bcm6838-pinctrl",
+ .data = (ulong)&bcm6838_hw,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6838_pinctrl) = {
+ .name = "bcm6838_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = bcm6838_pinctrl_match,
+ .ops = &bcm6838_pinctrl_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm6838_pinctrl_priv),
+ .probe = bcm6838_pinctrl_probe,
+};
"SDA",
"TX",
"RX",
+ "W1"
};
static const char * const sandbox_groups[] = {
"serial_a",
"serial_b",
"spi",
+ "w1",
};
static const char * const sandbox_functions[] = {
"i2c",
"serial",
"spi",
+ "w1",
};
static const struct pinconf_param sandbox_conf_params[] = {
--- /dev/null
+#
+# QUICC Engine Drivers
+#
+config U_QE
+ bool "Enable support for U QUICC Engine"
+ default y if (ARCH_LS1021A && !SD_BOOT && !NAND_BOOT && !QSPI_BOOT) \
+ || (TARGET_T1024QDS) \
+ || (TARGET_T1024RDB) \
+ || (TARGET_T1040QDS && !NOBQFMAN) \
+ || (TARGET_LS1043ARDB && !SPL_NO_QE && !NAND_BOOT && !QSPI_BOOT)
+ help
+ Choose this option to add support for U QUICC Engine.
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
+ (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
addr);
}
#endif
#include <common.h>
#include <command.h>
+#include <dm.h>
+#include <errno.h>
#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-#ifndef CONFIG_SYS_RTC_PL031_BASE
-#error CONFIG_SYS_RTC_PL031_BASE is not defined!
-#endif
+#include <asm/io.h>
+#include <asm/types.h>
/*
* Register definitions
#define RTC_CR_START (1 << 0)
-#define RTC_WRITE_REG(addr, val) \
- (*(volatile unsigned int *)(CONFIG_SYS_RTC_PL031_BASE + (addr)) = (val))
-#define RTC_READ_REG(addr) \
- (*(volatile unsigned int *)(CONFIG_SYS_RTC_PL031_BASE + (addr)))
+struct pl031_platdata {
+ phys_addr_t base;
+};
-static int pl031_initted = 0;
+static inline u32 pl031_read_reg(struct udevice *dev, int reg)
+{
+ struct pl031_platdata *pdata = dev_get_platdata(dev);
-/* Enable RTC Start in Control register*/
-void rtc_init(void)
+ return readl(pdata->base + reg);
+}
+
+static inline u32 pl031_write_reg(struct udevice *dev, int reg, u32 value)
{
- RTC_WRITE_REG(RTC_CR, RTC_CR_START);
+ struct pl031_platdata *pdata = dev_get_platdata(dev);
- pl031_initted = 1;
+ return writel(value, pdata->base + reg);
}
/*
- * Reset the RTC. We set the date back to 1970-01-01.
+ * Probe RTC device
+ */
+static int pl031_probe(struct udevice *dev)
+{
+ /* Enable RTC Start in Control register*/
+ pl031_write_reg(dev, RTC_CR, RTC_CR_START);
+
+ return 0;
+}
+
+/*
+ * Get the current time from the RTC
*/
-void rtc_reset(void)
+static int pl031_get(struct udevice *dev, struct rtc_time *tm)
{
- RTC_WRITE_REG(RTC_LR, 0x00);
- if(!pl031_initted)
- rtc_init();
+ unsigned long tim;
+
+ if (!tm)
+ return -EINVAL;
+
+ tim = pl031_read_reg(dev, RTC_DR);
+
+ rtc_to_tm(tim, tm);
+
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ return 0;
}
/*
* Set the RTC
-*/
-int rtc_set(struct rtc_time *tmp)
+ */
+static int pl031_set(struct udevice *dev, const struct rtc_time *tm)
{
unsigned long tim;
- if(!pl031_initted)
- rtc_init();
+ if (!tm)
+ return -EINVAL;
- if (tmp == NULL) {
- puts("Error setting the date/time\n");
- return -1;
- }
+ debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
/* Calculate number of seconds this incoming time represents */
- tim = rtc_mktime(tmp);
+ tim = rtc_mktime(tm);
- RTC_WRITE_REG(RTC_LR, tim);
+ pl031_write_reg(dev, RTC_LR, tim);
- return -1;
+ return 0;
}
/*
- * Get the current time from the RTC
+ * Reset the RTC. We set the date back to 1970-01-01.
*/
-int rtc_get(struct rtc_time *tmp)
+static int pl031_reset(struct udevice *dev)
{
- ulong tim;
+ pl031_write_reg(dev, RTC_LR, 0);
- if(!pl031_initted)
- rtc_init();
+ return 0;
+}
- if (tmp == NULL) {
- puts("Error getting the date/time\n");
- return -1;
- }
+static const struct rtc_ops pl031_ops = {
+ .get = pl031_get,
+ .set = pl031_set,
+ .reset = pl031_reset,
+};
- tim = RTC_READ_REG(RTC_DR);
+static const struct udevice_id pl031_ids[] = {
+ { .compatible = "arm,pl031" },
+ { }
+};
- rtc_to_tm(tim, tmp);
+static int pl031_ofdata_to_platdata(struct udevice *dev)
+{
+ struct pl031_platdata *pdata = dev_get_platdata(dev);
- debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ pdata->base = dev_read_addr(dev);
return 0;
}
-#endif
+U_BOOT_DRIVER(rtc_pl031) = {
+ .name = "rtc-pl031",
+ .id = UCLASS_RTC,
+ .of_match = pl031_ids,
+ .probe = pl031_probe,
+ .ofdata_to_platdata = pl031_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct pl031_platdata),
+ .ops = &pl031_ops,
+};
/* Information about the efi console */
struct serial_efi_priv {
- struct efi_simple_input_interface *con_in;
+ struct efi_simple_text_input_protocol *con_in;
struct efi_simple_text_output_protocol *con_out;
struct efi_input_key key;
bool have_key;
{ .compatible = "ti,am3352-uart", },
{ .compatible = "ti,am4372-uart", },
{ .compatible = "ti,dra742-uart", },
+ { .compatible = "ti,am654-uart", },
{}
};
#endif /* OF_CONTROL && !OF_PLATDATA */
struct stm32_uart_info stm32f7_info = {
.uart_enable_bit = 0,
.stm32f4 = false,
- .has_fifo = false,
+ .has_fifo = true,
};
struct stm32_uart_info stm32h7_info = {
to access the SPI NOR flash, MMC-over-SPI on platforms based on
Microchip PIC32 family devices.
+config PL022_SPI
+ bool "ARM AMBA PL022 SSP controller driver"
+ depends on ARM
+ help
+ This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP
+ controller. If you have an embedded system with an AMBA(R)
+ bus and a PL022 controller, say Y or M here.
+
config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver"
depends on RCAR_GEN3
obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
+obj-$(CONFIG_PL022_SPI) += pl022_spi.o
obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012
+ * Armando Visconti, ST Microelectronics, armando.visconti@st.com.
+ *
+ * (C) Copyright 2018
+ * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
+ *
+ * Driver for ARM PL022 SPI Controller.
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/pl022_spi.h>
+#include <fdtdec.h>
+#include <linux/bitops.h>
+#include <linux/bug.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <spi.h>
+
+#define SSP_CR0 0x000
+#define SSP_CR1 0x004
+#define SSP_DR 0x008
+#define SSP_SR 0x00C
+#define SSP_CPSR 0x010
+#define SSP_IMSC 0x014
+#define SSP_RIS 0x018
+#define SSP_MIS 0x01C
+#define SSP_ICR 0x020
+#define SSP_DMACR 0x024
+#define SSP_CSR 0x030 /* vendor extension */
+#define SSP_ITCR 0x080
+#define SSP_ITIP 0x084
+#define SSP_ITOP 0x088
+#define SSP_TDR 0x08C
+
+#define SSP_PID0 0xFE0
+#define SSP_PID1 0xFE4
+#define SSP_PID2 0xFE8
+#define SSP_PID3 0xFEC
+
+#define SSP_CID0 0xFF0
+#define SSP_CID1 0xFF4
+#define SSP_CID2 0xFF8
+#define SSP_CID3 0xFFC
+
+/* SSP Control Register 0 - SSP_CR0 */
+#define SSP_CR0_SPO (0x1 << 6)
+#define SSP_CR0_SPH (0x1 << 7)
+#define SSP_CR0_BIT_MODE(x) ((x) - 1)
+#define SSP_SCR_MIN (0x00)
+#define SSP_SCR_MAX (0xFF)
+#define SSP_SCR_SHFT 8
+#define DFLT_CLKRATE 2
+
+/* SSP Control Register 1 - SSP_CR1 */
+#define SSP_CR1_MASK_SSE (0x1 << 1)
+
+#define SSP_CPSR_MIN (0x02)
+#define SSP_CPSR_MAX (0xFE)
+#define DFLT_PRESCALE (0x40)
+
+/* SSP Status Register - SSP_SR */
+#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */
+#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */
+#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */
+#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */
+#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */
+
+struct pl022_spi_slave {
+ void *base;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct clk clk;
+#else
+ unsigned int freq;
+#endif
+};
+
+/*
+ * ARM PL022 exists in different 'flavors'.
+ * This drivers currently support the standard variant (0x00041022), that has a
+ * 16bit wide and 8 locations deep TX/RX FIFO.
+ */
+static int pl022_is_supported(struct pl022_spi_slave *ps)
+{
+ /* PL022 version is 0x00041022 */
+ if ((readw(ps->base + SSP_PID0) == 0x22) &&
+ (readw(ps->base + SSP_PID1) == 0x10) &&
+ ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
+ (readw(ps->base + SSP_PID3) == 0x00))
+ return 1;
+
+ return 0;
+}
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int pl022_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct pl022_spi_pdata *plat = bus->platdata;
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+
+ plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);
+
+ return clk_get_by_index(bus, 0, &plat->clk);
+}
+#endif
+
+static int pl022_spi_probe(struct udevice *bus)
+{
+ struct pl022_spi_pdata *plat = dev_get_platdata(bus);
+ struct pl022_spi_slave *ps = dev_get_priv(bus);
+
+ ps->base = ioremap(plat->addr, plat->size);
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ ps->clk = plat->clk;
+#else
+ ps->freq = plat->freq;
+#endif
+
+ /* Check the PL022 version */
+ if (!pl022_is_supported(ps))
+ return -ENOTSUPP;
+
+ /* 8 bits per word, high polarity and default clock rate */
+ writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
+ writew(DFLT_PRESCALE, ps->base + SSP_CPSR);
+
+ return 0;
+}
+
+static void flush(struct pl022_spi_slave *ps)
+{
+ do {
+ while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
+ readw(ps->base + SSP_DR);
+ } while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
+}
+
+static int pl022_spi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct pl022_spi_slave *ps = dev_get_priv(bus);
+ u16 reg;
+
+ /* Enable the SPI hardware */
+ reg = readw(ps->base + SSP_CR1);
+ reg |= SSP_CR1_MASK_SSE;
+ writew(reg, ps->base + SSP_CR1);
+
+ flush(ps);
+
+ return 0;
+}
+
+static int pl022_spi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct pl022_spi_slave *ps = dev_get_priv(bus);
+ u16 reg;
+
+ flush(ps);
+
+ /* Disable the SPI hardware */
+ reg = readw(ps->base + SSP_CR1);
+ reg &= ~SSP_CR1_MASK_SSE;
+ writew(reg, ps->base + SSP_CR1);
+
+ return 0;
+}
+
+static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct pl022_spi_slave *ps = dev_get_priv(bus);
+ u32 len_tx = 0, len_rx = 0, len;
+ u32 ret = 0;
+ const u8 *txp = dout;
+ u8 *rxp = din, value;
+
+ if (bitlen == 0)
+ /* Finish any previously submitted transfers */
+ return 0;
+
+ /*
+ * TODO: The controller can do non-multiple-of-8 bit
+ * transfers, but this driver currently doesn't support it.
+ *
+ * It's also not clear how such transfers are supposed to be
+ * represented as a stream of bytes...this is a limitation of
+ * the current SPI interface.
+ */
+ if (bitlen % 8) {
+ /* Errors always terminate an ongoing transfer */
+ flags |= SPI_XFER_END;
+ return -1;
+ }
+
+ len = bitlen / 8;
+
+ while (len_tx < len) {
+ if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
+ value = txp ? *txp++ : 0;
+ writew(value, ps->base + SSP_DR);
+ len_tx++;
+ }
+
+ if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
+ value = readw(ps->base + SSP_DR);
+ if (rxp)
+ *rxp++ = value;
+ len_rx++;
+ }
+ }
+
+ while (len_rx < len_tx) {
+ if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
+ value = readw(ps->base + SSP_DR);
+ if (rxp)
+ *rxp++ = value;
+ len_rx++;
+ }
+ }
+
+ return ret;
+}
+
+static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
+{
+ return rate / (cpsdvsr * (1 + scr));
+}
+
+static int pl022_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct pl022_spi_slave *ps = dev_get_priv(bus);
+ u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
+ best_cpsr = cpsr;
+ u32 min, max, best_freq = 0, tmp;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ u32 rate = clk_get_rate(&ps->clk);
+#else
+ u32 rate = ps->freq;
+#endif
+ bool found = false;
+
+ max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
+ min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);
+
+ if (speed > max || speed < min) {
+ pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
+ speed, min, max);
+ return -EINVAL;
+ }
+
+ while (cpsr <= SSP_CPSR_MAX && !found) {
+ while (scr <= SSP_SCR_MAX) {
+ tmp = spi_rate(rate, cpsr, scr);
+
+ if (abs(speed - tmp) < abs(speed - best_freq)) {
+ best_freq = tmp;
+ best_cpsr = cpsr;
+ best_scr = scr;
+
+ if (tmp == speed) {
+ found = true;
+ break;
+ }
+ }
+
+ scr++;
+ }
+ cpsr += 2;
+ scr = SSP_SCR_MIN;
+ }
+
+ writew(best_cpsr, ps->base + SSP_CPSR);
+ cr0 = readw(ps->base + SSP_CR0);
+ writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);
+
+ return 0;
+}
+
+static int pl022_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct pl022_spi_slave *ps = dev_get_priv(bus);
+ u16 reg;
+
+ reg = readw(ps->base + SSP_CR0);
+ reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO);
+ if (mode & SPI_CPHA)
+ reg |= SSP_CR0_SPH;
+ if (mode & SPI_CPOL)
+ reg |= SSP_CR0_SPO;
+ writew(reg, ps->base + SSP_CR0);
+
+ return 0;
+}
+
+static int pl022_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+{
+ return 0;
+}
+
+static const struct dm_spi_ops pl022_spi_ops = {
+ .claim_bus = pl022_spi_claim_bus,
+ .release_bus = pl022_spi_release_bus,
+ .xfer = pl022_spi_xfer,
+ .set_speed = pl022_spi_set_speed,
+ .set_mode = pl022_spi_set_mode,
+ .cs_info = pl022_cs_info,
+};
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+static const struct udevice_id pl022_spi_ids[] = {
+ { .compatible = "arm,pl022-spi" },
+ { }
+};
+#endif
+
+U_BOOT_DRIVER(pl022_spi) = {
+ .name = "pl022_spi",
+ .id = UCLASS_SPI,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .of_match = pl022_spi_ids,
+#endif
+ .ops = &pl022_spi_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .ofdata_to_platdata = pl022_spi_ofdata_to_platdata,
+#endif
+ .platdata_auto_alloc_size = sizeof(struct pl022_spi_pdata),
+ .priv_auto_alloc_size = sizeof(struct pl022_spi_slave),
+ .probe = pl022_spi_probe,
+};
.free_request = ci_ep_free_request,
};
+__weak void ci_init_after_reset(struct ehci_ctrl *ctrl)
+{
+}
+
/* Init values for USB endpoints. */
static const struct usb_ep ci_ep_init[5] = {
[0] = { /* EP 0 */
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
udelay(200);
+ ci_init_after_reset(controller.ctrl);
+
writel((unsigned long)controller.epts, &udc->epinitaddr);
/* select DEVICE mode */
writel(0xffffffff, &udc->epflush);
/* Turn on the USB connection by enabling the pullup resistor */
- writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd);
+ setbits_le32(&udc->usbcmd, USBCMD_ITC(MICRO_8FRAME) |
+ USBCMD_RUN);
} else {
udc_disconnect();
}
bool "Support for Qualcomm on-chip EHCI USB controller"
depends on DM_USB
select USB_ULPI_VIEWPORT
+ select MSM8916_USB_PHY
default n
---help---
Enables support for the on-chip EHCI controller on Qualcomm
Snapdragon SoCs.
- This driver supports combination of Chipidea USB controller
- and Synapsys USB PHY in host mode only.
config USB_EHCI_PCI
bool "Support for PCI-based EHCI USB controller"
#include <linux/compat.h>
#include "ehci.h"
-/* PHY viewport regs */
-#define ULPI_MISC_A_READ 0x96
-#define ULPI_MISC_A_SET 0x97
-#define ULPI_MISC_A_CLEAR 0x98
-#define ULPI_MISC_A_VBUSVLDEXTSEL (1 << 1)
-#define ULPI_MISC_A_VBUSVLDEXT (1 << 0)
-
-#define GEN2_SESS_VLD_CTRL_EN (1 << 7)
-
-#define SESS_VLD_CTRL (1 << 25)
-
struct msm_ehci_priv {
struct ehci_ctrl ctrl; /* Needed by EHCI */
struct usb_ehci *ehci; /* Start of IP core*/
struct ulpi_viewport ulpi_vp; /* ULPI Viewport */
+ struct phy phy;
};
-int __weak board_prepare_usb(enum usb_init_type type)
-{
- return 0;
-}
-
-static void setup_usb_phy(struct msm_ehci_priv *priv)
-{
- /* Select and enable external configuration with USB PHY */
- ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_SET,
- ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
-}
-
-static void reset_usb_phy(struct msm_ehci_priv *priv)
-{
- /* Disable VBUS mimicing in the controller. */
- ulpi_write(&priv->ulpi_vp, (u8 *)ULPI_MISC_A_CLEAR,
- ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT);
-}
-
-
static int msm_init_after_reset(struct ehci_ctrl *dev)
{
struct msm_ehci_priv *p = container_of(dev, struct msm_ehci_priv, ctrl);
struct usb_ehci *ehci = p->ehci;
- /* select ULPI phy */
- writel(PORT_PTS_ULPI, &ehci->portsc);
- setup_usb_phy(p);
-
- /* Enable sess_vld */
- setbits_le32(&ehci->genconfig2, GEN2_SESS_VLD_CTRL_EN);
-
- /* Enable external vbus configuration in the LINK */
- setbits_le32(&ehci->usbcmd, SESS_VLD_CTRL);
-
- /* USB_OTG_HS_AHB_BURST */
- writel(0x0, &ehci->sbuscfg);
-
- /* USB_OTG_HS_AHB_MODE: HPROT_MODE */
- /* Bus access related config. */
- writel(0x08, &ehci->sbusmode);
+ generic_phy_reset(&p->phy);
/* set mode to host controller */
writel(CM_HOST, &ehci->usbmode);
{
struct msm_ehci_priv *p = dev_get_priv(dev);
struct usb_ehci *ehci = p->ehci;
+ struct usb_platdata *plat = dev_get_platdata(dev);
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int ret;
hcor = (struct ehci_hcor *)((phys_addr_t)hccr +
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
- ret = board_prepare_usb(USB_INIT_HOST);
+ ret = ehci_setup_phy(dev, &p->phy, 0);
+ if (ret)
+ return ret;
+
+ ret = board_usb_init(0, plat->init_type);
if (ret < 0)
return ret;
- return ehci_register(dev, hccr, hcor, &msm_ehci_ops, 0, USB_INIT_HOST);
+ return ehci_register(dev, hccr, hcor, &msm_ehci_ops, 0,
+ plat->init_type);
}
static int ehci_usb_remove(struct udevice *dev)
/* Stop controller. */
clrbits_le32(&ehci->usbcmd, CMD_RUN);
- reset_usb_phy(p);
+ ret = ehci_shutdown_phy(dev, &p->phy);
+ if (ret)
+ return ret;
- ret = board_prepare_usb(USB_INIT_DEVICE); /* Board specific hook */
+ ret = board_usb_init(0, USB_INIT_DEVICE); /* Board specific hook */
if (ret < 0)
return ret;
return 0;
}
+#if defined(CONFIG_CI_UDC)
+/* Little quirk that MSM needs with Chipidea controller
+ * Must reinit phy after reset
+ */
+void ci_init_after_reset(struct ehci_ctrl *ctrl)
+{
+ struct msm_ehci_priv *p = ctrl->priv;
+
+ generic_phy_reset(&p->phy);
+}
+#endif
+
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "qcom,ehci-host", },
{ }
.remove = ehci_usb_remove,
.ops = &ehci_usb_ops,
.priv_auto_alloc_size = sizeof(struct msm_ehci_priv),
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
The devices provide a simple interface to start up the display,
read display information and enable it.
+config NXP_TDA19988
+ bool "Enable NXP TDA19988 support"
+ depends on DISPLAY
+ default n
+ help
+ This enables support for the NXP TDA19988 HDMI encoder. This encoder
+ will convert RGB data streams into HDMI-encoded signals.
+
config ATMEL_HLCD
bool "Enable ATMEL video support using HLCDC"
depends on DM_VIDEO
source "drivers/video/rockchip/Kconfig"
+config VIDEO_ARM_MALIDP
+ bool "Enable Arm Mali Display Processor support"
+ depends on DM_VIDEO && OF_CONTROL
+ select VEXPRESS_CLK
+ help
+ This enables support for Arm Ltd Mali Display Processors from
+ the DP500, DP550 and DP650 family.
+
config VIDEO_SANDBOX_SDL
bool "Enable sandbox video console using SDL"
depends on SANDBOX
The video output is initialized by U-Boot, and kept by the
kernel.
+config OSD
+ bool "Enable OSD support"
+ depends on DM
+ default n
+ help
+ This supports drivers that provide a OSD (on-screen display), which
+ is a (usually text-oriented) graphics buffer to show information on
+ a display.
+
+config SANDBOX_OSD
+ bool "Enable sandbox OSD"
+ depends on OSD
+ help
+ Enable support for sandbox OSD device used for testing purposes.
+
+config IHS_VIDEO_OUT
+ bool "Enable IHS video out driver"
+ depends on OSD
+ help
+ Enable support for the gdsys Integrated Hardware Systems (IHS) video
+ out On-screen Display (OSD) used on gdsys FPGAs to control dynamic
+ textual overlays of the display outputs.
+
endmenu
obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
+obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o
obj-$(CONFIG_LD9040) += ld9040.o
obj-$(CONFIG_LG4573) += lg4573.o
obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o
+obj-$(CONFIG_NXP_TDA19988) += tda19988.o
+obj-$(CONFIG_OSD) += video_osd-uclass.o
obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
+obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o
obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
+obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o
obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
break;
}
}
+
+ if (cfb_do_flush_cache)
+ flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE);
+
return 0;
error:
printf("Error: Too much encoded pixel data, validate your bitmap\n");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * based on the gdsys osd driver, which is
+ *
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.de
+ */
+
+#include <common.h>
+#include <display.h>
+#include <dm.h>
+#include <regmap.h>
+#include <video_osd.h>
+#include <asm/gpio.h>
+
+static const uint MAX_X_CHARS = 53;
+static const uint MAX_Y_CHARS = 26;
+static const uint MAX_VIDEOMEM_WIDTH = 64;
+static const uint MAX_VIDEOMEM_HEIGHT = 32;
+static const uint CHAR_WIDTH = 12;
+static const uint CHAR_HEIGHT = 18;
+
+static const u16 BASE_WIDTH_MASK = 0x3f00;
+static const uint BASE_WIDTH_SHIFT = 8;
+static const u16 BASE_HEIGTH_MASK = 0x001f;
+static const uint BASE_HEIGTH_SHIFT;
+
+struct ihs_video_out_regs {
+ /* Device version register */
+ u16 versions;
+ /* Device feature register */
+ u16 features;
+ /* Device control register */
+ u16 control;
+ /* Register controlling screen size */
+ u16 xy_size;
+ /* Register controlling screen scaling */
+ u16 xy_scale;
+ /* Register controlling screen x position */
+ u16 x_pos;
+ /* Register controlling screen y position */
+ u16 y_pos;
+};
+
+#define ihs_video_out_set(map, member, val) \
+ regmap_range_set(map, 1, struct ihs_video_out_regs, member, val)
+
+#define ihs_video_out_get(map, member, valp) \
+ regmap_range_get(map, 1, struct ihs_video_out_regs, member, valp)
+
+enum {
+ CONTROL_FILTER_BLACK = (0 << 0),
+ CONTROL_FILTER_ORIGINAL = (1 << 0),
+ CONTROL_FILTER_DARKER = (2 << 0),
+ CONTROL_FILTER_GRAY = (3 << 0),
+
+ CONTROL_MODE_PASSTHROUGH = (0 << 3),
+ CONTROL_MODE_OSD = (1 << 3),
+ CONTROL_MODE_AUTO = (2 << 3),
+ CONTROL_MODE_OFF = (3 << 3),
+
+ CONTROL_ENABLE_OFF = (0 << 6),
+ CONTROL_ENABLE_ON = (1 << 6),
+};
+
+struct ihs_video_out_priv {
+ /* Register map for OSD device */
+ struct regmap *map;
+ /* Pointer to video memory */
+ u16 *vidmem;
+ /* Display width in text columns */
+ uint base_width;
+ /* Display height in text rows */
+ uint base_height;
+ /* x-resolution of the display in pixels */
+ uint res_x;
+ /* y-resolution of the display in pixels */
+ uint res_y;
+ /* OSD's sync mode (resolution + frequency) */
+ int sync_src;
+ /* The display port output for this OSD */
+ struct udevice *video_tx;
+ /* The pixel clock generator for the display */
+ struct udevice *clk_gen;
+};
+
+static const struct udevice_id ihs_video_out_ids[] = {
+ { .compatible = "gdsys,ihs_video_out" },
+ { }
+};
+
+/**
+ * set_control() - Set the control register to a given value
+ *
+ * The current value of sync_src is preserved by the function automatically.
+ *
+ * @dev: the OSD device whose control register to set
+ * @value: the 16-bit value to write to the control register
+ * Return: 0
+ */
+static int set_control(struct udevice *dev, u16 value)
+{
+ struct ihs_video_out_priv *priv = dev_get_priv(dev);
+
+ if (priv->sync_src)
+ value |= ((priv->sync_src & 0x7) << 8);
+
+ ihs_video_out_set(priv->map, control, value);
+
+ return 0;
+}
+
+int ihs_video_out_get_info(struct udevice *dev, struct video_osd_info *info)
+{
+ struct ihs_video_out_priv *priv = dev_get_priv(dev);
+ u16 versions;
+
+ ihs_video_out_get(priv->map, versions, &versions);
+
+ info->width = priv->base_width;
+ info->height = priv->base_height;
+ info->major_version = versions / 100;
+ info->minor_version = versions % 100;
+
+ return 0;
+}
+
+int ihs_video_out_set_mem(struct udevice *dev, uint col, uint row, u8 *buf,
+ size_t buflen, uint count)
+{
+ struct ihs_video_out_priv *priv = dev_get_priv(dev);
+ int res;
+ uint offset;
+ uint k, rep;
+ u16 data;
+
+ /* Repetitions (controlled via count parmeter) */
+ for (rep = 0; rep < count; ++rep) {
+ offset = row * priv->base_width + col + rep * (buflen / 2);
+
+ /* Write a single buffer copy */
+ for (k = 0; k < buflen / 2; ++k) {
+ uint max_size = priv->base_width * priv->base_height;
+
+ if (offset + k >= max_size) {
+ debug("%s: Write would be out of OSD bounds\n",
+ dev->name);
+ return -E2BIG;
+ }
+
+ data = buf[2 * k + 1] + 256 * buf[2 * k];
+ out_le16(priv->vidmem + offset + k, data);
+ }
+ }
+
+ res = set_control(dev, CONTROL_FILTER_ORIGINAL |
+ CONTROL_MODE_OSD |
+ CONTROL_ENABLE_ON);
+ if (res) {
+ debug("%s: Could not set control register\n", dev->name);
+ return res;
+ }
+
+ return 0;
+}
+
+/**
+ * div2_u16() - Approximately divide a 16-bit number by 2
+ *
+ * @val: The 16-bit value to divide by two
+ * Return: The approximate division of val by two
+ */
+static inline u16 div2_u16(u16 val)
+{
+ return (32767 * val) / 65535;
+}
+
+int ihs_video_out_set_size(struct udevice *dev, uint col, uint row)
+{
+ struct ihs_video_out_priv *priv = dev_get_priv(dev);
+
+ if (!col || col > MAX_VIDEOMEM_WIDTH || col > MAX_X_CHARS ||
+ !row || row > MAX_VIDEOMEM_HEIGHT || row > MAX_Y_CHARS) {
+ debug("%s: Desired OSD size invalid\n", dev->name);
+ return -EINVAL;
+ }
+
+ ihs_video_out_set(priv->map, xy_size, ((col - 1) << 8) | (row - 1));
+ /* Center OSD on screen */
+ ihs_video_out_set(priv->map, x_pos,
+ div2_u16(priv->res_x - CHAR_WIDTH * col));
+ ihs_video_out_set(priv->map, y_pos,
+ div2_u16(priv->res_y - CHAR_HEIGHT * row));
+
+ return 0;
+}
+
+int ihs_video_out_print(struct udevice *dev, uint col, uint row, ulong color,
+ char *text)
+{
+ int res;
+ u8 buffer[2 * MAX_VIDEOMEM_WIDTH];
+ uint k;
+ uint charcount = strlen(text);
+ uint len = min(charcount, 2 * MAX_VIDEOMEM_WIDTH);
+
+ for (k = 0; k < len; ++k) {
+ buffer[2 * k] = text[k];
+ buffer[2 * k + 1] = color;
+ }
+
+ res = ihs_video_out_set_mem(dev, col, row, buffer, 2 * len, 1);
+ if (res < 0) {
+ debug("%s: Could not write to video memory\n", dev->name);
+ return res;
+ }
+
+ return 0;
+}
+
+static const struct video_osd_ops ihs_video_out_ops = {
+ .get_info = ihs_video_out_get_info,
+ .set_mem = ihs_video_out_set_mem,
+ .set_size = ihs_video_out_set_size,
+ .print = ihs_video_out_print,
+};
+
+int ihs_video_out_probe(struct udevice *dev)
+{
+ struct ihs_video_out_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args phandle_args;
+ const char *mode;
+ u16 features;
+ struct display_timing timing;
+ int res;
+
+ res = regmap_init_mem(dev_ofnode(dev), &priv->map);
+ if (!res) {
+ debug("%s: Could initialize regmap (err = %d)\n", dev->name,
+ res);
+ return res;
+ }
+
+ /* Range with index 2 is video memory */
+ priv->vidmem = regmap_get_range(priv->map, 2);
+
+ mode = dev_read_string(dev, "mode");
+ if (!mode) {
+ debug("%s: Could not read mode property\n", dev->name);
+ return -EINVAL;
+ }
+
+ if (!strcmp(mode, "1024_768_60")) {
+ priv->sync_src = 2;
+ priv->res_x = 1024;
+ priv->res_y = 768;
+ timing.hactive.typ = 1024;
+ timing.vactive.typ = 768;
+ } else if (!strcmp(mode, "720_400_70")) {
+ priv->sync_src = 1;
+ priv->res_x = 720;
+ priv->res_y = 400;
+ timing.hactive.typ = 720;
+ timing.vactive.typ = 400;
+ } else {
+ priv->sync_src = 0;
+ priv->res_x = 640;
+ priv->res_y = 480;
+ timing.hactive.typ = 640;
+ timing.vactive.typ = 480;
+ }
+
+ ihs_video_out_get(priv->map, features, &features);
+
+ res = set_control(dev, CONTROL_FILTER_ORIGINAL |
+ CONTROL_MODE_OSD |
+ CONTROL_ENABLE_OFF);
+ if (res) {
+ debug("%s: Could not set control register (err = %d)\n",
+ dev->name, res);
+ return res;
+ }
+
+ priv->base_width = ((features & BASE_WIDTH_MASK)
+ >> BASE_WIDTH_SHIFT) + 1;
+ priv->base_height = ((features & BASE_HEIGTH_MASK)
+ >> BASE_HEIGTH_SHIFT) + 1;
+
+ res = dev_read_phandle_with_args(dev, "clk_gen", NULL, 0, 0,
+ &phandle_args);
+ if (res) {
+ debug("%s: Could not get clk_gen node (err = %d)\n",
+ dev->name, res);
+ return -EINVAL;
+ }
+
+ res = uclass_get_device_by_ofnode(UCLASS_CLK, phandle_args.node,
+ &priv->clk_gen);
+ if (res) {
+ debug("%s: Could not get clk_gen dev (err = %d)\n",
+ dev->name, res);
+ return -EINVAL;
+ }
+
+ res = dev_read_phandle_with_args(dev, "video_tx", NULL, 0, 0,
+ &phandle_args);
+ if (res) {
+ debug("%s: Could not get video_tx (err = %d)\n",
+ dev->name, res);
+ return -EINVAL;
+ }
+
+ res = uclass_get_device_by_ofnode(UCLASS_DISPLAY, phandle_args.node,
+ &priv->video_tx);
+ if (res) {
+ debug("%s: Could not get video_tx dev (err = %d)\n",
+ dev->name, res);
+ return -EINVAL;
+ }
+
+ res = display_enable(priv->video_tx, 8, &timing);
+ if (res) {
+ debug("%s: Could not enable the display (err = %d)\n",
+ dev->name, res);
+ return res;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(ihs_video_out_drv) = {
+ .name = "ihs_video_out_drv",
+ .id = UCLASS_VIDEO_OSD,
+ .ops = &ihs_video_out_ops,
+ .of_match = ihs_video_out_ids,
+ .probe = ihs_video_out_probe,
+ .priv_auto_alloc_size = sizeof(struct ihs_video_out_priv),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016-2018 ARM Ltd.
+ * Author: Liviu Dudau <liviu.dudau@foss.arm.com>
+ *
+ */
+#define DEBUG
+#include <common.h>
+#include <video.h>
+#include <dm.h>
+#ifdef CONFIG_DISPLAY
+#include <display.h>
+#endif
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <os.h>
+#include <fdt_support.h>
+#include <clk.h>
+#include <linux/sizes.h>
+
+#define MALIDP_CORE_ID 0x0018
+#define MALIDP_REG_BG_COLOR 0x0044
+#define MALIDP_LAYER_LV1 0x0100
+#define MALIDP_DC_STATUS 0xc000
+#define MALIDP_DC_CONTROL 0xc010
+#define MALIDP_DC_CFG_VALID 0xc014
+
+/* offsets inside the modesetting register block */
+#define MALIDP_H_INTERVALS 0x0000
+#define MALIDP_V_INTERVALS 0x0004
+#define MALIDP_SYNC_CONTROL 0x0008
+#define MALIDP_HV_ACTIVESIZE 0x000c
+#define MALIDP_OUTPUT_DEPTH 0x001c
+
+/* offsets inside the layer register block */
+#define MALIDP_LAYER_FORMAT 0x0000
+#define MALIDP_LAYER_CONTROL 0x0004
+#define MALIDP_LAYER_IN_SIZE 0x000c
+#define MALIDP_LAYER_CMP_SIZE 0x0010
+#define MALIDP_LAYER_STRIDE 0x0018
+#define MALIDP_LAYER_PTR_LOW 0x0024
+#define MALIDP_LAYER_PTR_HIGH 0x0028
+
+/* offsets inside the IRQ control blocks */
+#define MALIDP_REG_MASKIRQ 0x0008
+#define MALIDP_REG_CLEARIRQ 0x000c
+
+#define M1BITS 0x0001
+#define M2BITS 0x0003
+#define M4BITS 0x000f
+#define M8BITS 0x00ff
+#define M10BITS 0x03ff
+#define M12BITS 0x0fff
+#define M13BITS 0x1fff
+#define M16BITS 0xffff
+#define M17BITS 0x1ffff
+
+#define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0)
+#define MALIDP_H_BACKPORCH(x) (((x) & M10BITS) << 16)
+#define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0)
+#define MALIDP_V_BACKPORCH(x) (((x) & M8BITS) << 16)
+#define MALIDP_H_SYNCWIDTH(x) (((x) & M10BITS) << 0)
+#define MALIDP_V_SYNCWIDTH(x) (((x) & M8BITS) << 16)
+#define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0)
+#define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16)
+
+#define MALIDP_CMP_V_SIZE(x) (((x) & M13BITS) << 16)
+#define MALIDP_CMP_H_SIZE(x) (((x) & M13BITS) << 0)
+
+#define MALIDP_IN_V_SIZE(x) (((x) & M13BITS) << 16)
+#define MALIDP_IN_H_SIZE(x) (((x) & M13BITS) << 0)
+
+#define MALIDP_DC_CM_CONTROL(x) ((x) & M1BITS) << 16, 1 << 16
+#define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS)
+
+#define MALIDP_FORMAT_ARGB8888 0x08
+#define MALIDP_DEFAULT_BG_R 0x0
+#define MALIDP_DEFAULT_BG_G 0x0
+#define MALIDP_DEFAULT_BG_B 0x0
+
+#define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16)
+
+#define MALIDP500 0x500
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct malidp_priv {
+ phys_addr_t base_addr;
+ phys_addr_t dc_status_addr;
+ phys_addr_t dc_control_addr;
+ phys_addr_t cval_addr;
+ struct udevice *display; /* display device attached */
+ struct clk aclk;
+ struct clk pxlclk;
+ u16 modeset_regs_offset;
+ u8 config_bit_shift;
+ u8 clear_irq; /* offset for IRQ clear register */
+};
+
+static const struct video_ops malidp_ops = {
+};
+
+static int malidp_get_hwid(phys_addr_t base_addr)
+{
+ int hwid;
+
+ /*
+ * reading from the old CORE_ID offset will always
+ * return 0x5000000 on DP500
+ */
+ hwid = readl(base_addr + MALIDP_CORE_ID);
+ if (MALIDP_PRODUCT_ID(hwid) == MALIDP500)
+ return hwid;
+ /* otherwise try the other gen CORE_ID offset */
+ hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID);
+
+ return hwid;
+}
+
+/*
+ * wait for config mode bit setup to be acted upon by the hardware
+ */
+static int malidp_wait_configdone(struct malidp_priv *malidp)
+{
+ u32 status, tries = 300;
+
+ while (tries--) {
+ status = readl(malidp->dc_status_addr);
+ if ((status >> malidp->config_bit_shift) & 1)
+ break;
+ udelay(500);
+ }
+
+ if (!tries)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+/*
+ * signal the hardware to enter configuration mode
+ */
+static int malidp_enter_config(struct malidp_priv *malidp)
+{
+ setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
+ return malidp_wait_configdone(malidp);
+}
+
+/*
+ * signal the hardware to exit configuration mode
+ */
+static int malidp_leave_config(struct malidp_priv *malidp)
+{
+ clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
+ return malidp_wait_configdone(malidp);
+}
+
+static void malidp_setup_timings(struct malidp_priv *malidp,
+ struct display_timing *timings)
+{
+ u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) |
+ MALIDP_V_SYNCWIDTH(timings->vsync_len.typ);
+ writel(val, malidp->base_addr + malidp->modeset_regs_offset +
+ MALIDP_SYNC_CONTROL);
+ val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) |
+ MALIDP_H_FRONTPORCH(timings->hfront_porch.typ);
+ writel(val, malidp->base_addr + malidp->modeset_regs_offset +
+ MALIDP_H_INTERVALS);
+ val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) |
+ MALIDP_V_FRONTPORCH(timings->vfront_porch.typ);
+ writel(val, malidp->base_addr + malidp->modeset_regs_offset +
+ MALIDP_V_INTERVALS);
+ val = MALIDP_H_ACTIVE(timings->hactive.typ) |
+ MALIDP_V_ACTIVE(timings->vactive.typ);
+ writel(val, malidp->base_addr + malidp->modeset_regs_offset +
+ MALIDP_HV_ACTIVESIZE);
+ /* default output bit-depth per colour is 8 bits */
+ writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset +
+ MALIDP_OUTPUT_DEPTH);
+}
+
+static int malidp_setup_mode(struct malidp_priv *malidp,
+ struct display_timing *timings)
+{
+ int err;
+
+ if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0)
+ return -EIO;
+
+ malidp_setup_timings(malidp, timings);
+
+ err = display_enable(malidp->display, 8, timings);
+ if (err)
+ printf("display_enable failed with %d\n", err);
+
+ return err;
+}
+
+static void malidp_setup_layer(struct malidp_priv *malidp,
+ struct display_timing *timings,
+ u32 layer_offset, phys_addr_t fb_addr)
+{
+ u32 val;
+
+ /* setup the base layer's pixel format to A8R8G8B8 */
+ writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset +
+ MALIDP_LAYER_FORMAT);
+ /* setup layer composition size */
+ val = MALIDP_CMP_V_SIZE(timings->vactive.typ) |
+ MALIDP_CMP_H_SIZE(timings->hactive.typ);
+ writel(val, malidp->base_addr + layer_offset +
+ MALIDP_LAYER_CMP_SIZE);
+ /* setup layer input size */
+ val = MALIDP_IN_V_SIZE(timings->vactive.typ) |
+ MALIDP_IN_H_SIZE(timings->hactive.typ);
+ writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE);
+ /* setup layer stride in bytes */
+ writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset +
+ MALIDP_LAYER_STRIDE);
+ /* set framebuffer address */
+ writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset +
+ MALIDP_LAYER_PTR_LOW);
+ writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset +
+ MALIDP_LAYER_PTR_HIGH);
+ /* enable layer */
+ setbits_le32(malidp->base_addr + layer_offset +
+ MALIDP_LAYER_CONTROL, 1);
+}
+
+static void malidp_set_configvalid(struct malidp_priv *malidp)
+{
+ setbits_le32(malidp->cval_addr, 1);
+}
+
+static int malidp_update_timings_from_edid(struct udevice *dev,
+ struct display_timing *timings)
+{
+#ifdef CONFIG_DISPLAY
+ struct malidp_priv *priv = dev_get_priv(dev);
+ struct udevice *disp_dev;
+ int err;
+
+ err = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
+ if (err)
+ return err;
+
+ priv->display = disp_dev;
+
+ err = display_read_timing(disp_dev, timings);
+ if (err)
+ return err;
+
+#endif
+ return 0;
+}
+
+static int malidp_probe(struct udevice *dev)
+{
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer");
+ struct malidp_priv *priv = dev_get_priv(dev);
+ struct display_timing timings;
+ phys_addr_t fb_base, fb_size;
+ const char *format;
+ u32 value;
+ int err;
+
+ if (!ofnode_valid(framebuffer))
+ return -EINVAL;
+
+ err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk);
+ if (err) {
+ dev_err(dev, "failed to get pixel clock\n");
+ return err;
+ }
+ err = clk_get_by_name(dev, "aclk", &priv->aclk);
+ if (err) {
+ dev_err(dev, "failed to get AXI clock\n");
+ goto fail_aclk;
+ }
+
+ err = ofnode_decode_display_timing(dev_ofnode(dev), 1, &timings);
+ if (err) {
+ dev_err(dev, "failed to get any display timings\n");
+ goto fail_timings;
+ }
+
+ err = malidp_update_timings_from_edid(dev, &timings);
+ if (err) {
+ printf("malidp_update_timings_from_edid failed: %d\n", err);
+ goto fail_timings;
+ }
+
+ fb_base = ofnode_get_addr_size(framebuffer, "reg", &fb_size);
+ if (fb_base != FDT_ADDR_T_NONE) {
+ uc_plat->base = fb_base;
+ uc_plat->size = fb_size;
+ } else {
+ printf("cannot get address size for framebuffer\n");
+ }
+
+ err = ofnode_read_u32(framebuffer, "width", &value);
+ if (err)
+ goto fail_timings;
+ uc_priv->xsize = (ushort)value;
+
+ err = ofnode_read_u32(framebuffer, "height", &value);
+ if (err)
+ goto fail_timings;
+ uc_priv->ysize = (ushort)value;
+
+ format = ofnode_read_string(framebuffer, "format");
+ if (!format) {
+ err = -EINVAL;
+ goto fail_timings;
+ } else if (!strncmp(format, "a8r8g8b8", 8)) {
+ uc_priv->bpix = VIDEO_BPP32;
+ }
+
+ uc_priv->rot = 0;
+ priv->base_addr = (phys_addr_t)dev_read_addr(dev);
+
+ clk_enable(&priv->pxlclk);
+ clk_enable(&priv->aclk);
+
+ value = malidp_get_hwid(priv->base_addr);
+ printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value),
+ (value >> 12) & 0xf, (value >> 8) & 0xf);
+
+ if (MALIDP_PRODUCT_ID(value) == MALIDP500) {
+ /* DP500 is special */
+ priv->modeset_regs_offset = 0x28;
+ priv->dc_status_addr = priv->base_addr;
+ priv->dc_control_addr = priv->base_addr + 0xc;
+ priv->cval_addr = priv->base_addr + 0xf00;
+ priv->config_bit_shift = 17;
+ priv->clear_irq = 0;
+ } else {
+ priv->modeset_regs_offset = 0x30;
+ priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS;
+ priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL;
+ priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID;
+ priv->config_bit_shift = 16;
+ priv->clear_irq = MALIDP_REG_CLEARIRQ;
+ }
+
+ /* enter config mode */
+ err = malidp_enter_config(priv);
+ if (err)
+ return err;
+
+ /* disable interrupts */
+ writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ);
+ writel(0xffffffff, priv->dc_status_addr + priv->clear_irq);
+
+ err = malidp_setup_mode(priv, &timings);
+ if (err)
+ goto fail_timings;
+
+ malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1,
+ (phys_addr_t)uc_plat->base);
+
+ err = malidp_leave_config(priv);
+ if (err)
+ goto fail_timings;
+
+ malidp_set_configvalid(priv);
+
+ return 0;
+
+fail_timings:
+ clk_free(&priv->aclk);
+fail_aclk:
+ clk_free(&priv->pxlclk);
+
+ return err;
+}
+
+static int malidp_bind(struct udevice *dev)
+{
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+
+ /* choose max possible size: 2K x 2K, XRGB888 framebuffer */
+ uc_plat->size = 4 * 2048 * 2048;
+
+ return 0;
+}
+
+static const struct udevice_id malidp_ids[] = {
+ { .compatible = "arm,mali-dp500" },
+ { .compatible = "arm,mali-dp550" },
+ { .compatible = "arm,mali-dp650" },
+ { }
+};
+
+U_BOOT_DRIVER(mali_dp) = {
+ .name = "mali_dp",
+ .id = UCLASS_VIDEO,
+ .of_match = malidp_ids,
+ .bind = malidp_bind,
+ .probe = malidp_probe,
+ .priv_auto_alloc_size = sizeof(struct malidp_priv),
+ .ops = &malidp_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+#include <common.h>
+#include <display.h>
+#include <dm.h>
+#include <video_osd.h>
+
+#include "sandbox_osd.h"
+
+struct sandbox_osd_priv {
+ uint width;
+ uint height;
+ u16 *buf;
+};
+
+static const struct udevice_id sandbox_osd_ids[] = {
+ { .compatible = "sandbox,sandbox_osd" },
+ { }
+};
+
+inline u16 make_memval(u8 chr, u8 color)
+{
+ return chr * 0x100 + color;
+}
+
+int sandbox_osd_get_info(struct udevice *dev, struct video_osd_info *info)
+{
+ struct sandbox_osd_priv *priv = dev_get_priv(dev);
+
+ info->width = priv->width;
+ info->height = priv->height;
+ info->major_version = 1;
+ info->minor_version = 0;
+
+ return 0;
+}
+
+int sandbox_osd_set_mem(struct udevice *dev, uint col, uint row, u8 *buf,
+ size_t buflen, uint count)
+{
+ struct sandbox_osd_priv *priv = dev_get_priv(dev);
+ int pos;
+ u8 *mem = (u8 *)priv->buf;
+ int i;
+
+ pos = 2 * (row * priv->width + col);
+
+ if (pos >= 2 * (priv->width * priv->height))
+ return -EINVAL;
+
+ for (i = 0; i < count; i++)
+ memcpy(mem + pos + (i * buflen), buf, buflen);
+
+ return 0;
+}
+
+int _sandbox_osd_set_size(struct udevice *dev, uint col, uint row)
+{
+ struct sandbox_osd_priv *priv = dev_get_priv(dev);
+ int i;
+ uint size;
+
+ priv->width = col;
+ priv->height = row;
+ size = priv->width * priv->height;
+ if (!priv->buf)
+ priv->buf = calloc(size, sizeof(u16));
+ else
+ priv->buf = realloc(priv->buf, size * sizeof(u16));
+
+ if (!priv->buf)
+ return -ENOMEM;
+
+ /* Fill OSD with black spaces */
+ for (i = 0; i < size; i++)
+ priv->buf[i] = make_memval(' ', 'k');
+
+ return 0;
+}
+
+int sandbox_osd_set_size(struct udevice *dev, uint col, uint row)
+{
+ return _sandbox_osd_set_size(dev, col, row);
+}
+
+int sandbox_osd_print(struct udevice *dev, uint col, uint row, ulong color,
+ char *text)
+{
+ struct sandbox_osd_priv *priv = dev_get_priv(dev);
+ char cval;
+ char *p;
+ int pos;
+
+ if (col >= priv->width || row >= priv->height)
+ return -EINVAL;
+
+ switch (color) {
+ case COLOR_BLACK:
+ cval = 'k';
+ break;
+ case COLOR_WHITE:
+ cval = 'w';
+ break;
+ case COLOR_RED:
+ cval = 'r';
+ break;
+ case COLOR_GREEN:
+ cval = 'g';
+ break;
+ case COLOR_BLUE:
+ cval = 'b';
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ p = text;
+ pos = row * priv->width + col;
+
+ while (*p)
+ priv->buf[pos++] = make_memval(*(p++), cval);
+
+ return 0;
+}
+
+int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen)
+{
+ struct sandbox_osd_priv *priv = dev_get_priv(dev);
+ uint memsize = 2 * (priv->width * priv->height);
+
+ if (buflen < memsize)
+ return -EINVAL;
+
+ memcpy(buf, priv->buf, memsize);
+
+ return 0;
+}
+
+static const struct video_osd_ops sandbox_osd_ops = {
+ .get_info = sandbox_osd_get_info,
+ .set_mem = sandbox_osd_set_mem,
+ .set_size = sandbox_osd_set_size,
+ .print = sandbox_osd_print,
+};
+
+int sandbox_osd_probe(struct udevice *dev)
+{
+ return _sandbox_osd_set_size(dev, 10, 10);
+}
+
+U_BOOT_DRIVER(sandbox_osd_drv) = {
+ .name = "sandbox_osd_drv",
+ .id = UCLASS_VIDEO_OSD,
+ .ops = &sandbox_osd_ops,
+ .of_match = sandbox_osd_ids,
+ .probe = sandbox_osd_probe,
+ .priv_auto_alloc_size = sizeof(struct sandbox_osd_priv),
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+enum {
+ COLOR_BLACK,
+ COLOR_WHITE,
+ COLOR_RED,
+ COLOR_GREEN,
+ COLOR_BLUE,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Liviu Dudau <liviu@dudau.co.uk>
+ *
+ * Based on the Linux driver, (C) 2012 Texas Instruments
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <display.h>
+#include <i2c.h>
+
+/*
+ * TDA19988 uses paged registers. We encode the page# in the upper
+ * bits of the register#. It also means that reads/writes to a register
+ * have to ensure that the register's page is selected as the current
+ * page.
+ */
+#define REG(page, addr) (((page) << 8) | (addr))
+#define REG2ADDR(reg) ((reg) & 0xff)
+#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
+
+/* register for setting current page */
+#define REG_CURRENT_PAGE 0xff
+
+/* Page 00h: General Control */
+#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
+#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
+#define MAIN_CNTRL0_SR BIT(0)
+#define MAIN_CNTRL0_DECS BIT(1)
+#define MAIN_CNTRL0_DEHS BIT(2)
+#define MAIN_CNTRL0_CECS BIT(3)
+#define MAIN_CNTRL0_CEHS BIT(4)
+#define MAIN_CNTRL0_SCALER BIT(7)
+#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
+#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
+#define SOFTRESET_AUDIO BIT(0)
+#define SOFTRESET_I2C_MASTER BIT(1)
+#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
+#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
+#define I2C_MASTER_DIS_MM BIT(0)
+#define I2C_MASTER_DIS_FILT BIT(1)
+#define I2C_MASTER_APP_STRT_LAT BIT(2)
+#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
+#define FEAT_POWERDOWN_PREFILT BIT(0)
+#define FEAT_POWERDOWN_CSC BIT(1)
+#define FEAT_POWERDOWN_SPDIF BIT(3)
+#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
+#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
+#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
+#define INT_FLAGS_2_EDID_BLK_RD BIT(1)
+#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
+#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
+#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
+#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
+#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
+#define VIP_CNTRL_0_MIRR_A BIT(7)
+#define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
+#define VIP_CNTRL_0_MIRR_B BIT(3)
+#define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
+#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
+#define VIP_CNTRL_1_MIRR_C BIT(7)
+#define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
+#define VIP_CNTRL_1_MIRR_D BIT(3)
+#define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
+#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
+#define VIP_CNTRL_2_MIRR_E BIT(7)
+#define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
+#define VIP_CNTRL_2_MIRR_F BIT(3)
+#define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
+#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
+#define VIP_CNTRL_3_X_TGL BIT(0)
+#define VIP_CNTRL_3_H_TGL BIT(1)
+#define VIP_CNTRL_3_V_TGL BIT(2)
+#define VIP_CNTRL_3_EMB BIT(3)
+#define VIP_CNTRL_3_SYNC_DE BIT(4)
+#define VIP_CNTRL_3_SYNC_HS BIT(5)
+#define VIP_CNTRL_3_DE_INT BIT(6)
+#define VIP_CNTRL_3_EDGE BIT(7)
+#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
+#define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
+#define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
+#define VIP_CNTRL_4_CCIR656 BIT(4)
+#define VIP_CNTRL_4_656_ALT BIT(5)
+#define VIP_CNTRL_4_TST_656 BIT(6)
+#define VIP_CNTRL_4_TST_PAT BIT(7)
+#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
+#define VIP_CNTRL_5_CKCASE BIT(0)
+#define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
+#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
+#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
+#define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
+#define MAT_CONTRL_MAT_BP BIT(2)
+#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
+#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
+#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
+#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
+#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
+#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
+#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
+#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
+#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
+#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
+#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
+#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
+#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
+#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
+#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
+#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
+#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
+#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
+#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
+#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
+#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
+#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
+#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
+#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
+#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
+#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
+#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
+#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
+#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
+#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
+#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
+#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
+#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
+#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
+#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
+#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
+#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
+#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
+#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
+#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
+#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
+#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
+#define TBG_CNTRL_0_TOP_TGL BIT(0)
+#define TBG_CNTRL_0_TOP_SEL BIT(1)
+#define TBG_CNTRL_0_DE_EXT BIT(2)
+#define TBG_CNTRL_0_TOP_EXT BIT(3)
+#define TBG_CNTRL_0_FRAME_DIS BIT(5)
+#define TBG_CNTRL_0_SYNC_MTHD BIT(6)
+#define TBG_CNTRL_0_SYNC_ONCE BIT(7)
+#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
+#define TBG_CNTRL_1_H_TGL BIT(0)
+#define TBG_CNTRL_1_V_TGL BIT(1)
+#define TBG_CNTRL_1_TGL_EN BIT(2)
+#define TBG_CNTRL_1_X_EXT BIT(3)
+#define TBG_CNTRL_1_H_EXT BIT(4)
+#define TBG_CNTRL_1_V_EXT BIT(5)
+#define TBG_CNTRL_1_DWIN_DIS BIT(6)
+#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
+#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
+#define HVF_CNTRL_0_SM BIT(7)
+#define HVF_CNTRL_0_RWB BIT(6)
+#define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
+#define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
+#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
+#define HVF_CNTRL_1_FOR BIT(0)
+#define HVF_CNTRL_1_YUVBLK BIT(1)
+#define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
+#define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
+#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
+#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
+#define AIP_CLKSEL_AIP_SPDIF (0 << 3)
+#define AIP_CLKSEL_AIP_I2S BIT(3)
+#define AIP_CLKSEL_FS_ACLK (0 << 0)
+#define AIP_CLKSEL_FS_MCLK BIT(0)
+
+/* Page 02h: PLL settings */
+#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
+#define PLL_SERIAL_1_SRL_FDN BIT(0)
+#define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
+#define PLL_SERIAL_1_SRL_MAN_IZ BIT(6)
+#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
+#define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
+#define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
+#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
+#define PLL_SERIAL_3_SRL_CCIR BIT(0)
+#define PLL_SERIAL_3_SRL_DE BIT(2)
+#define PLL_SERIAL_3_SRL_PXIN_SEL BIT(4)
+#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
+#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
+#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
+#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
+#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
+#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
+#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
+#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
+#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
+#define AUDIO_DIV_SERCLK_1 0
+#define AUDIO_DIV_SERCLK_2 1
+#define AUDIO_DIV_SERCLK_4 2
+#define AUDIO_DIV_SERCLK_8 3
+#define AUDIO_DIV_SERCLK_16 4
+#define AUDIO_DIV_SERCLK_32 5
+#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
+#define SEL_CLK_SEL_CLK1 BIT(0)
+#define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
+#define SEL_CLK_ENA_SC_CLK BIT(3)
+#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
+
+/* Page 09h: EDID Control */
+#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
+/* next 127 successive registers are the EDID block */
+#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
+#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
+#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
+#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
+#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
+
+/* Page 11h: audio settings and content info packets */
+#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
+#define AIP_CNTRL_0_RST_FIFO BIT(0)
+#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
+#define ENC_CNTRL_RST_ENC BIT(0)
+#define ENC_CNTRL_RST_SEL BIT(1)
+#define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
+
+/* Page 12h: HDCP and OTP */
+#define REG_TX3 REG(0x12, 0x9a) /* read/write */
+#define REG_TX4 REG(0x12, 0x9b) /* read/write */
+#define TX4_PD_RAM BIT(1)
+#define REG_TX33 REG(0x12, 0xb8) /* read/write */
+#define TX33_HDMI BIT(1)
+
+/* CEC registers, not paged */
+#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
+#define CEC_FRO_IM_CLK_CTRL_GHOST_DIS BIT(7)
+#define CEC_FRO_IM_CLK_CTRL_ENA_OTP BIT(6)
+#define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL BIT(1)
+#define CEC_FRO_IM_CLK_CTRL_FRO_DIV BIT(0)
+#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
+#define REG_CEC_RXSHPDINT 0xfd /* read */
+#define CEC_RXSHPDINT_RXSENS BIT(0)
+#define CEC_RXSHPDINT_HPD BIT(1)
+#define TDA19988_CEC_ENAMODS 0xff /* read/write */
+#define CEC_ENAMODS_EN_RXSENS BIT(2)
+#define CEC_ENAMODS_EN_HDMI BIT(1)
+#define CEC_ENAMODS_EN_CEC BIT(0)
+
+/* Device versions */
+#define TDA9989N2 0x0101
+#define TDA19989 0x0201
+#define TDA19989N2 0x0202
+#define TDA19988 0x0301
+
+struct tda19988_priv {
+ struct udevice *chip;
+ struct udevice *cec_chip;
+ u16 revision;
+ u8 current_page;
+};
+
+static void tda19988_register_set(struct tda19988_priv *priv, u16 reg, u8 val)
+{
+ u8 old_val, page = REG2PAGE(reg);
+
+ if (priv->current_page != page) {
+ dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
+ priv->current_page = page;
+ }
+ old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
+ old_val |= val;
+ dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
+}
+
+static void tda19988_register_clear(struct tda19988_priv *priv, u16 reg, u8 val)
+{
+ u8 old_val, page = REG2PAGE(reg);
+
+ if (priv->current_page != page) {
+ dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
+ priv->current_page = page;
+ }
+ old_val = dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
+ old_val &= ~val;
+ dm_i2c_reg_write(priv->chip, REG2ADDR(reg), old_val);
+}
+
+static void tda19988_register_write(struct tda19988_priv *priv, u16 reg, u8 val)
+{
+ u8 page = REG2PAGE(reg);
+
+ if (priv->current_page != page) {
+ dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
+ priv->current_page = page;
+ }
+ dm_i2c_reg_write(priv->chip, REG2ADDR(reg), val);
+}
+
+static int tda19988_register_read(struct tda19988_priv *priv, u16 reg)
+{
+ u8 page = REG2PAGE(reg);
+
+ if (priv->current_page != page) {
+ dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
+ priv->current_page = page;
+ }
+ return dm_i2c_reg_read(priv->chip, REG2ADDR(reg));
+}
+
+static void tda19988_register_write16(struct tda19988_priv *priv,
+ u16 reg, u16 val)
+{
+ u8 buf[] = { val >> 8, val }, page = REG2PAGE(reg);
+
+ if (priv->current_page != page) {
+ dm_i2c_reg_write(priv->chip, REG_CURRENT_PAGE, page);
+ priv->current_page = page;
+ }
+ dm_i2c_write(priv->chip, REG2ADDR(reg), buf, 2);
+}
+
+static int tda19988_read_edid(struct udevice *dev, u8 *buf, int buf_size)
+{
+ struct tda19988_priv *priv = dev_get_priv(dev);
+ int i, val = 0, offset = 0;
+
+ /*
+ * The TDA998x has a problem when trying to read the EDID close to a
+ * HPD assertion: it needs a delay of 100ms to avoid timing out while
+ * trying to read EDID data.
+ */
+ mdelay(120);
+
+ if (priv->revision == TDA19988)
+ tda19988_register_clear(priv, REG_TX4, TX4_PD_RAM);
+
+ while (offset < buf_size) {
+ tda19988_register_write(priv, REG_DDC_ADDR, 0xa0);
+ tda19988_register_write(priv, REG_DDC_OFFS, offset);
+ tda19988_register_write(priv, REG_DDC_SEGM_ADDR, 0x60);
+ tda19988_register_write(priv, REG_DDC_SEGM, 0);
+
+ /* enable reading EDID */
+ tda19988_register_write(priv, REG_EDID_CTRL, 1);
+
+ /* flags must be cleared by software */
+ tda19988_register_write(priv, REG_EDID_CTRL, 0);
+
+ /* wait for block read to complete */
+ for (i = 300; i > 0; i--) {
+ mdelay(1);
+ val = tda19988_register_read(priv, REG_INT_FLAGS_2);
+ if (val < 0)
+ return val;
+ if (val & INT_FLAGS_2_EDID_BLK_RD)
+ break;
+ }
+
+ if (i == 0)
+ return -ETIMEDOUT;
+
+ priv->current_page = REG2PAGE(REG_EDID_DATA_0);
+ dm_i2c_reg_write(priv->chip,
+ REG_CURRENT_PAGE, REG2PAGE(REG_EDID_DATA_0));
+ val = dm_i2c_read(priv->chip,
+ REG2ADDR(REG_EDID_DATA_0), buf + offset, 128);
+ offset += 128;
+ }
+
+ if (priv->revision == TDA19988)
+ tda19988_register_set(priv, REG_TX4, TX4_PD_RAM);
+
+ return offset;
+}
+
+static int tda19988_enable(struct udevice *dev, int panel_bpp,
+ const struct display_timing *timing)
+{
+ struct tda19988_priv *priv = dev_get_priv(dev);
+ u8 div = 148500000 / timing->pixelclock.typ, reg;
+ u16 line_clocks, lines;
+
+ if (dev != 0) {
+ div--;
+ if (div > 3)
+ div = 3;
+ }
+ /* first disable the video ports */
+ tda19988_register_write(priv, REG_ENA_VP_0, 0);
+ tda19988_register_write(priv, REG_ENA_VP_1, 0);
+ tda19988_register_write(priv, REG_ENA_VP_2, 0);
+
+ /* shutdown audio */
+ tda19988_register_write(priv, REG_ENA_AP, 0);
+
+ line_clocks = timing->hsync_len.typ + timing->hback_porch.typ +
+ timing->hactive.typ + timing->hfront_porch.typ;
+ lines = timing->vsync_len.typ + timing->vback_porch.typ +
+ timing->vactive.typ + timing->vfront_porch.typ;
+
+ /* mute the audio FIFO */
+ tda19988_register_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
+ /* HDMI HDCP: off */
+ tda19988_register_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
+ tda19988_register_clear(priv, REG_TX33, TX33_HDMI);
+ tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
+
+ /* no pre-filter or interpolator */
+ tda19988_register_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
+ HVF_CNTRL_0_INTPOL(0));
+ tda19988_register_set(priv, REG_FEAT_POWERDOWN,
+ FEAT_POWERDOWN_PREFILT);
+ tda19988_register_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
+ tda19988_register_write(priv, REG_VIP_CNTRL_4,
+ VIP_CNTRL_4_BLANKIT(0) | VIP_CNTRL_4_BLC(0) |
+ VIP_CNTRL_4_TST_PAT);
+
+ tda19988_register_clear(priv, REG_PLL_SERIAL_1,
+ PLL_SERIAL_1_SRL_MAN_IZ);
+ tda19988_register_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
+ PLL_SERIAL_3_SRL_DE);
+
+ tda19988_register_write(priv, REG_SERIALIZER, 0);
+ tda19988_register_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
+
+ tda19988_register_write(priv, REG_RPT_CNTRL, 0);
+ tda19988_register_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
+ SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
+ tda19988_register_write(priv, REG_PLL_SERIAL_2,
+ PLL_SERIAL_2_SRL_NOSC(div) |
+ PLL_SERIAL_2_SRL_PR(0));
+
+ /* set color matrix bypass flag: */
+ tda19988_register_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
+ MAT_CONTRL_MAT_SC(1));
+ tda19988_register_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
+
+ /* set BIAS tmds value: */
+ tda19988_register_write(priv, REG_ANA_GENERAL, 0x09);
+
+ /*
+ * Sync on rising HSYNC/VSYNC
+ */
+ reg = VIP_CNTRL_3_SYNC_HS;
+
+ /*
+ * TDA19988 requires high-active sync at input stage,
+ * so invert low-active sync provided by master encoder here
+ */
+ if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
+ reg |= VIP_CNTRL_3_H_TGL;
+ if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
+ reg |= VIP_CNTRL_3_V_TGL;
+ tda19988_register_write(priv, REG_VIP_CNTRL_3, reg);
+
+ tda19988_register_write(priv, REG_VIDFORMAT, 0x00);
+ tda19988_register_write16(priv, REG_REFPIX_MSB,
+ timing->hfront_porch.typ + 3);
+ tda19988_register_write16(priv, REG_REFLINE_MSB,
+ timing->vfront_porch.typ + 1);
+ tda19988_register_write16(priv, REG_NPIX_MSB, line_clocks);
+ tda19988_register_write16(priv, REG_NLINE_MSB, lines);
+ tda19988_register_write16(priv, REG_VS_LINE_STRT_1_MSB,
+ timing->vfront_porch.typ);
+ tda19988_register_write16(priv, REG_VS_PIX_STRT_1_MSB,
+ timing->hfront_porch.typ);
+ tda19988_register_write16(priv, REG_VS_LINE_END_1_MSB,
+ timing->vfront_porch.typ +
+ timing->vsync_len.typ);
+ tda19988_register_write16(priv, REG_VS_PIX_END_1_MSB,
+ timing->hfront_porch.typ);
+ tda19988_register_write16(priv, REG_VS_LINE_STRT_2_MSB, 0);
+ tda19988_register_write16(priv, REG_VS_PIX_STRT_2_MSB, 0);
+ tda19988_register_write16(priv, REG_VS_LINE_END_2_MSB, 0);
+ tda19988_register_write16(priv, REG_VS_PIX_END_2_MSB, 0);
+ tda19988_register_write16(priv, REG_HS_PIX_START_MSB,
+ timing->hfront_porch.typ);
+ tda19988_register_write16(priv, REG_HS_PIX_STOP_MSB,
+ timing->hfront_porch.typ +
+ timing->hsync_len.typ);
+ tda19988_register_write16(priv, REG_VWIN_START_1_MSB,
+ lines - timing->vactive.typ - 1);
+ tda19988_register_write16(priv, REG_VWIN_END_1_MSB, lines - 1);
+ tda19988_register_write16(priv, REG_VWIN_START_2_MSB, 0);
+ tda19988_register_write16(priv, REG_VWIN_END_2_MSB, 0);
+ tda19988_register_write16(priv, REG_DE_START_MSB,
+ line_clocks - timing->hactive.typ);
+ tda19988_register_write16(priv, REG_DE_STOP_MSB, line_clocks);
+
+ if (priv->revision == TDA19988) {
+ /* let incoming pixels fill the active space (if any) */
+ tda19988_register_write(priv, REG_ENABLE_SPACE, 0x00);
+ }
+
+ /*
+ * Always generate sync polarity relative to input sync and
+ * revert input stage toggled sync at output stage
+ */
+ reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
+ if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
+ reg |= TBG_CNTRL_1_H_TGL;
+ if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
+ reg |= TBG_CNTRL_1_V_TGL;
+ tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
+
+ /* must be last register set: */
+ tda19988_register_write(priv, REG_TBG_CNTRL_0, 0);
+
+ /* turn on HDMI HDCP */
+ reg &= ~TBG_CNTRL_1_DWIN_DIS;
+ tda19988_register_write(priv, REG_TBG_CNTRL_1, reg);
+ tda19988_register_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
+ tda19988_register_set(priv, REG_TX33, TX33_HDMI);
+
+ mdelay(400);
+
+ /* enable video ports */
+ tda19988_register_write(priv, REG_ENA_VP_0, 0xff);
+ tda19988_register_write(priv, REG_ENA_VP_1, 0xff);
+ tda19988_register_write(priv, REG_ENA_VP_2, 0xff);
+ /* set muxing after enabling ports: */
+ tda19988_register_write(priv, REG_VIP_CNTRL_0,
+ VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3));
+ tda19988_register_write(priv, REG_VIP_CNTRL_1,
+ VIP_CNTRL_1_SWAP_C(4) | VIP_CNTRL_1_SWAP_D(5));
+ tda19988_register_write(priv, REG_VIP_CNTRL_2,
+ VIP_CNTRL_2_SWAP_E(0) | VIP_CNTRL_2_SWAP_F(1));
+
+ return 0;
+}
+
+struct dm_display_ops tda19988_ops = {
+ .read_edid = tda19988_read_edid,
+ .enable = tda19988_enable,
+};
+
+static const struct udevice_id tda19988_ids[] = {
+ { .compatible = "nxp,tda998x" },
+ { }
+};
+
+static int tda19988_probe(struct udevice *dev)
+{
+ u8 cec_addr, chip_addr, rev_lo, rev_hi;
+ int err;
+ struct tda19988_priv *priv = dev_get_priv(dev);
+
+ chip_addr = dev_read_addr(dev);
+ /* CEC I2C address is using TDA19988 I2C address configuration pins */
+ cec_addr = 0x34 + (chip_addr & 0x03);
+
+ err = i2c_get_chip_for_busnum(0, cec_addr, 1, &priv->cec_chip);
+ if (err) {
+ printf("cec i2c_get_chip_for_busnum returned %d\n", err);
+ return err;
+ }
+
+ err = i2c_get_chip_for_busnum(0, chip_addr, 1, &priv->chip);
+ if (err) {
+ printf("i2c_get_chip_for_busnum returned %d\n", err);
+ return err;
+ }
+
+ priv->current_page = 0xff;
+
+ /* wake up device */
+ dm_i2c_reg_write(priv->cec_chip, TDA19988_CEC_ENAMODS,
+ CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
+
+ /* reset audio and I2C master */
+ tda19988_register_write(priv, REG_SOFTRESET,
+ SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
+ mdelay(50);
+ tda19988_register_write(priv, REG_SOFTRESET, 0);
+ mdelay(50);
+
+ /* reset transmitter */
+ tda19988_register_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
+ tda19988_register_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
+
+ /* PLL registers common configuration */
+ tda19988_register_write(priv, REG_PLL_SERIAL_1, 0x00);
+ tda19988_register_write(priv, REG_PLL_SERIAL_2,
+ PLL_SERIAL_2_SRL_NOSC(1));
+ tda19988_register_write(priv, REG_PLL_SERIAL_3, 0x00);
+ tda19988_register_write(priv, REG_SERIALIZER, 0x00);
+ tda19988_register_write(priv, REG_BUFFER_OUT, 0x00);
+ tda19988_register_write(priv, REG_PLL_SCG1, 0x00);
+ tda19988_register_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
+ tda19988_register_write(priv, REG_SEL_CLK,
+ SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
+ tda19988_register_write(priv, REG_PLL_SCGN1, 0xfa);
+ tda19988_register_write(priv, REG_PLL_SCGN2, 0x00);
+ tda19988_register_write(priv, REG_PLL_SCGR1, 0x5b);
+ tda19988_register_write(priv, REG_PLL_SCGR2, 0x00);
+ tda19988_register_write(priv, REG_PLL_SCG2, 0x10);
+
+ /* Write the default value MUX register */
+ tda19988_register_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
+
+ /* read version */
+ rev_lo = dm_i2c_reg_read(priv->chip, REG_VERSION_LSB);
+ rev_hi = dm_i2c_reg_read(priv->chip, REG_VERSION_MSB);
+
+ /* mask off feature bits */
+ priv->revision = ((rev_hi << 8) | rev_lo) & ~0x30;
+
+ printf("HDMI: ");
+ switch (priv->revision) {
+ case TDA9989N2:
+ printf("TDA9989 n2\n");
+ break;
+ case TDA19989:
+ printf("TDA19989\n");
+ break;
+ case TDA19989N2:
+ printf("TDA19989 n2\n");
+ break;
+ case TDA19988:
+ printf("TDA19988\n");
+ break;
+ default:
+ printf("unknown TDA device: 0x%04x\n", priv->revision);
+ return -ENXIO;
+ }
+
+ /* after reset, enable DDC */
+ tda19988_register_write(priv, REG_DDC_DISABLE, 0x00);
+
+ /* set clock on DDC channel */
+ tda19988_register_write(priv, REG_TX3, 39);
+
+ /* if necessary, disable multi-master */
+ if (priv->revision == TDA19989)
+ tda19988_register_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
+
+ dm_i2c_reg_write(priv->cec_chip, REG_CEC_FRO_IM_CLK_CTRL,
+ CEC_FRO_IM_CLK_CTRL_GHOST_DIS |
+ CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
+ /* ensure interrupts are disabled */
+ dm_i2c_reg_write(priv->cec_chip, REG_CEC_RXSHPDINTENA, 0);
+ /* clear pending interrupts */
+ dm_i2c_reg_read(priv->cec_chip, REG_CEC_RXSHPDINT);
+ tda19988_register_read(priv, REG_INT_FLAGS_0);
+ tda19988_register_read(priv, REG_INT_FLAGS_1);
+ tda19988_register_read(priv, REG_INT_FLAGS_2);
+
+ /* enable EDID read irq */
+ tda19988_register_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(tda19988) = {
+ .name = "tda19988",
+ .id = UCLASS_DISPLAY,
+ .of_match = tda19988_ids,
+ .ops = &tda19988_ops,
+ .probe = tda19988_probe,
+ .priv_auto_alloc_size = sizeof(struct tda19988_priv),
+};
return end;
}
+/**
+ * set_cursor_position() - set cursor position
+ *
+ * @priv: private data of the video console
+ * @row: new row
+ * @col: new column
+ */
+static void set_cursor_position(struct vidconsole_priv *priv, int row, int col)
+{
+ /*
+ * Ensure we stay in the bounds of the screen.
+ */
+ if (row >= priv->rows)
+ row = priv->rows - 1;
+ if (col >= priv->cols)
+ col = priv->cols - 1;
+
+ priv->ycur = row * priv->y_charsize;
+ priv->xcur_frac = priv->xstart_frac +
+ VID_TO_POS(col * priv->x_charsize);
+}
+
+/**
+ * get_cursor_position() - get cursor position
+ *
+ * @priv: private data of the video console
+ * @row: row
+ * @col: column
+ */
+static void get_cursor_position(struct vidconsole_priv *priv,
+ int *row, int *col)
+{
+ *row = priv->ycur / priv->y_charsize;
+ *col = VID_TO_PIXEL(priv->xcur_frac - priv->xstart_frac) /
+ priv->x_charsize;
+}
+
/*
* Process a character while accumulating an escape string. Chars are
* accumulated into escape_buf until the end of escape sequence is
/* Sanity checking for bogus ESC sequences: */
if (priv->escape_len >= sizeof(priv->escape_buf))
goto error;
- if (priv->escape_len == 0 && ch != '[')
- goto error;
+ if (priv->escape_len == 0) {
+ switch (ch) {
+ case '7':
+ /* Save cursor position */
+ get_cursor_position(priv, &priv->row_saved,
+ &priv->col_saved);
+ priv->escape = 0;
+
+ return;
+ case '8': {
+ /* Restore cursor position */
+ int row = priv->row_saved;
+ int col = priv->col_saved;
+
+ set_cursor_position(priv, row, col);
+ priv->escape = 0;
+ return;
+ }
+ case '[':
+ break;
+ default:
+ goto error;
+ }
+ }
priv->escape_buf[priv->escape_len++] = ch;
s++; /* ; */
s = parsenum(s, &col);
- priv->ycur = row * priv->y_charsize;
- priv->xcur_frac = priv->xstart_frac +
- VID_TO_POS(col * priv->x_charsize);
+ set_cursor_position(priv, row, col);
break;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <video_osd.h>
+
+int video_osd_get_info(struct udevice *dev, struct video_osd_info *info)
+{
+ struct video_osd_ops *ops = video_osd_get_ops(dev);
+
+ return ops->get_info(dev, info);
+}
+
+int video_osd_set_mem(struct udevice *dev, uint col, uint row, u8 *buf,
+ size_t buflen, uint count)
+{
+ struct video_osd_ops *ops = video_osd_get_ops(dev);
+
+ return ops->set_mem(dev, col, row, buf, buflen, count);
+}
+
+int video_osd_set_size(struct udevice *dev, uint col, uint row)
+{
+ struct video_osd_ops *ops = video_osd_get_ops(dev);
+
+ return ops->set_size(dev, col, row);
+}
+
+int video_osd_print(struct udevice *dev, uint col, uint row, ulong color,
+ char *text)
+{
+ struct video_osd_ops *ops = video_osd_get_ops(dev);
+
+ return ops->print(dev, col, row, color, text);
+}
+
+UCLASS_DRIVER(video_osd) = {
+ .id = UCLASS_VIDEO_OSD,
+ .name = "video_osd",
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+};
--- /dev/null
+#
+# EEPROM subsystem configuration
+#
+
+menu "1-wire EEPROM support"
+
+config W1_EEPROM
+ bool "Enable support for EEPROMs on 1wire interface"
+ depends on DM
+ help
+ Support for the EEPROMs connected on 1-wire Dallas protocol interface
+
+if W1_EEPROM
+
+config W1_EEPROM_DS24XXX
+ bool "Enable Maxim DS24 families EEPROM support"
+ depends on W1
+ help
+ Maxim DS24 EEPROMs 1-Wire EEPROM support
+
+config W1_EEPROM_SANDBOX
+ bool "Enable sandbox onewire EEPROM driver"
+ depends on W1
+ help
+ Sandbox driver for a onewire EEPROM memory
+
+endif
+
+endmenu
--- /dev/null
+obj-$(CONFIG_W1_EEPROM) += w1-eeprom-uclass.o
+
+obj-$(CONFIG_W1_EEPROM_DS24XXX) += ds24xxx.o
+
+obj-$(CONFIG_W1_EEPROM_SANDBOX) += eep_sandbox.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co
+ * Copyright (c) 2018 Microchip Technology, Inc.
+ *
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <dm.h>
+#include <w1-eeprom.h>
+#include <w1.h>
+
+#define W1_F2D_READ_EEPROM 0xf0
+
+static int ds24xxx_read_buf(struct udevice *dev, unsigned int offset,
+ u8 *buf, unsigned int count)
+{
+ w1_reset_select(dev);
+
+ w1_write_byte(dev, W1_F2D_READ_EEPROM);
+ w1_write_byte(dev, offset & 0xff);
+ w1_write_byte(dev, offset >> 8);
+
+ return w1_read_buf(dev, buf, count);
+}
+
+static int ds24xxx_probe(struct udevice *dev)
+{
+ struct w1_device *w1;
+
+ w1 = dev_get_platdata(dev);
+ w1->id = 0;
+ return 0;
+}
+
+static const struct w1_eeprom_ops ds24xxx_ops = {
+ .read_buf = ds24xxx_read_buf,
+};
+
+static const struct udevice_id ds24xxx_id[] = {
+ { .compatible = "maxim,ds24b33", .data = W1_FAMILY_DS24B33 },
+ { .compatible = "maxim,ds2431", .data = W1_FAMILY_DS2431 },
+ { },
+};
+
+U_BOOT_DRIVER(ds24xxx) = {
+ .name = "ds24xxx",
+ .id = UCLASS_W1_EEPROM,
+ .of_match = ds24xxx_id,
+ .ops = &ds24xxx_ops,
+ .probe = ds24xxx_probe,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (c) 2018 Microchip Technology, Inc.
+ *
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <dm.h>
+#include <w1-eeprom.h>
+#include <w1.h>
+
+#define W1_F2D_READ_EEPROM 0xf0
+
+#define EEP_SANDBOX_SAMPLE_MEM "this is a sample EEPROM memory string."
+
+static int eep_sandbox_read_buf(struct udevice *dev, unsigned int offset,
+ u8 *buf, unsigned int count)
+{
+ /* do not allow to copy more than our maximum sample string */
+ if (offset + count < strlen(EEP_SANDBOX_SAMPLE_MEM)) {
+ offset = 0;
+ count = strlen(EEP_SANDBOX_SAMPLE_MEM);
+ }
+ strncpy((char *)buf, EEP_SANDBOX_SAMPLE_MEM, count);
+
+ /*
+ * in case the w1 subsystem uses some different kind of sandbox testing,
+ * like randomized gpio values , we take the buffer from there
+ */
+
+ w1_reset_select(dev);
+
+ w1_write_byte(dev, W1_F2D_READ_EEPROM);
+ w1_write_byte(dev, offset & 0xff);
+ w1_write_byte(dev, offset >> 8);
+
+ w1_read_buf(dev, buf, count);
+
+ /*
+ * even if read buf from w1 fails, return success as we hardcoded
+ * the buffer.
+ */
+ return 0;
+}
+
+static const struct w1_eeprom_ops eep_sandbox_ops = {
+ .read_buf = eep_sandbox_read_buf,
+};
+
+static const struct udevice_id eep_sandbox_id[] = {
+ { .compatible = "sandbox,w1-eeprom", .data = W1_FAMILY_EEP_SANDBOX },
+ { },
+};
+
+U_BOOT_DRIVER(eep_sandbox) = {
+ .name = "eep_sandbox",
+ .id = UCLASS_W1_EEPROM,
+ .of_match = eep_sandbox_id,
+ .ops = &eep_sandbox_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co.
+ * Copyright (c) 2018 Microchip Technology, Inc.
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ * Eugen Hristev <eugen.hristev@microchip.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <w1.h>
+#include <w1-eeprom.h>
+
+#include <dm/device-internal.h>
+
+int w1_eeprom_read_buf(struct udevice *dev, unsigned int offset,
+ u8 *buf, unsigned int count)
+{
+ const struct w1_eeprom_ops *ops = device_get_ops(dev);
+ u64 id = 0;
+ int ret;
+
+ if (!ops->read_buf)
+ return -ENOSYS;
+
+ ret = w1_eeprom_get_id(dev, &id);
+ if (ret)
+ return ret;
+ if (!id)
+ return -ENODEV;
+
+ return ops->read_buf(dev, offset, buf, count);
+}
+
+int w1_eeprom_register_new_device(u64 id)
+{
+ u8 family = id & 0xff;
+ int ret;
+ struct udevice *dev;
+
+ for (ret = uclass_first_device(UCLASS_W1_EEPROM, &dev);
+ !ret && dev;
+ uclass_next_device(&dev)) {
+ if (ret || !dev) {
+ debug("cannot find w1 eeprom dev\n");
+ return ret;
+ }
+ if (dev_get_driver_data(dev) == family) {
+ struct w1_device *w1;
+
+ w1 = dev_get_parent_platdata(dev);
+ if (w1->id) /* device already in use */
+ continue;
+ w1->id = id;
+ debug("%s: Match found: %s:%s %llx\n", __func__,
+ dev->name, dev->driver->name, id);
+ return 0;
+ }
+ }
+
+ debug("%s: No matches found: error %d\n", __func__, ret);
+
+ return ret;
+}
+
+int w1_eeprom_get_id(struct udevice *dev, u64 *id)
+{
+ struct w1_device *w1 = dev_get_parent_platdata(dev);
+
+ if (!w1)
+ return -ENODEV;
+ *id = w1->id;
+
+ return 0;
+}
+
+UCLASS_DRIVER(w1_eeprom) = {
+ .name = "w1_eeprom",
+ .id = UCLASS_W1_EEPROM,
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .post_bind = dm_scan_fdt_dev,
+#endif
+};
+
+int w1_eeprom_dm_init(void)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_W1_EEPROM, &uc);
+ if (ret) {
+ debug("W1_EEPROM uclass not available\n");
+ return ret;
+ }
+
+ uclass_foreach_dev(dev, uc) {
+ ret = device_probe(dev);
+ if (ret == -ENODEV) { /* No such device. */
+ debug("W1_EEPROM not available.\n");
+ continue;
+ }
+
+ if (ret) { /* Other error. */
+ printf("W1_EEPROM probe failed, error %d\n", ret);
+ continue;
+ }
+ }
+
+ return 0;
+}
--- /dev/null
+#
+# W1 subsystem configuration
+#
+
+menu "1-Wire support"
+
+config W1
+ bool "Enable 1-wire controllers support"
+ default no
+ depends on DM
+ help
+ Support for the Dallas 1-Wire bus.
+
+if W1
+
+config W1_GPIO
+ bool "Enable 1-wire GPIO bitbanging"
+ default no
+ depends on DM_GPIO
+ help
+ Emulate a 1-wire bus using a GPIO.
+
+endif
+
+endmenu
--- /dev/null
+obj-$(CONFIG_W1) += w1-uclass.o
+
+obj-$(CONFIG_W1_GPIO) += w1-gpio.o
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <w1.h>
+
+#include <asm/gpio.h>
+
+#define W1_TIMING_A 6
+#define W1_TIMING_B 64
+#define W1_TIMING_C 60
+#define W1_TIMING_D 10
+#define W1_TIMING_E 9
+#define W1_TIMING_F 55
+#define W1_TIMING_G 0
+#define W1_TIMING_H 480
+#define W1_TIMING_I 70
+#define W1_TIMING_J 410
+
+struct w1_gpio_pdata {
+ struct gpio_desc gpio;
+ u64 search_id;
+};
+
+static bool w1_gpio_read_bit(struct udevice *dev)
+{
+ struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+ int val;
+
+ dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT);
+ udelay(W1_TIMING_A);
+
+ dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_IN);
+ udelay(W1_TIMING_E);
+
+ val = dm_gpio_get_value(&pdata->gpio);
+ if (val < 0)
+ debug("error in retrieving GPIO value");
+ udelay(W1_TIMING_F);
+
+ return val;
+}
+
+static u8 w1_gpio_read_byte(struct udevice *dev)
+{
+ int i;
+ u8 ret = 0;
+
+ for (i = 0; i < 8; ++i)
+ ret |= (w1_gpio_read_bit(dev) ? 1 : 0) << i;
+
+ return ret;
+}
+
+static void w1_gpio_write_bit(struct udevice *dev, bool bit)
+{
+ struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+
+ dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT);
+
+ bit ? udelay(W1_TIMING_A) : udelay(W1_TIMING_C);
+
+ dm_gpio_set_value(&pdata->gpio, 1);
+
+ bit ? udelay(W1_TIMING_B) : udelay(W1_TIMING_D);
+}
+
+static void w1_gpio_write_byte(struct udevice *dev, u8 byte)
+{
+ int i;
+
+ for (i = 0; i < 8; ++i)
+ w1_gpio_write_bit(dev, (byte >> i) & 0x1);
+}
+
+static bool w1_gpio_reset(struct udevice *dev)
+{
+ struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+ int val;
+
+ /* initiate the reset pulse. first we must pull the bus to low */
+ dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ udelay(W1_TIMING_G);
+
+ dm_gpio_set_value(&pdata->gpio, 0);
+ /* wait for the specified time with the bus kept low */
+ udelay(W1_TIMING_H);
+
+ /* now we must read the presence pulse */
+ dm_gpio_set_dir_flags(&pdata->gpio, GPIOD_IS_IN);
+ udelay(W1_TIMING_I);
+
+ val = dm_gpio_get_value(&pdata->gpio);
+ if (val < 0)
+ debug("error in retrieving GPIO value");
+
+ /* if nobody pulled the bus down , it means nobody is on the bus */
+ if (val != 0)
+ return 1;
+ /* we have the bus pulled down, let's wait for the specified presence time */
+ udelay(W1_TIMING_J);
+
+ /* read again, the other end should leave the bus free */
+ val = dm_gpio_get_value(&pdata->gpio);
+ if (val < 0)
+ debug("error in retrieving GPIO value");
+
+ /* bus is not going up again, so we have an error */
+ if (val != 1)
+ return 1;
+
+ /* all good, presence detected */
+ return 0;
+}
+
+static u8 w1_gpio_triplet(struct udevice *dev, bool bdir)
+{
+ u8 id_bit = w1_gpio_read_bit(dev);
+ u8 comp_bit = w1_gpio_read_bit(dev);
+ u8 retval;
+
+ if (id_bit && comp_bit)
+ return 0x03; /* error */
+
+ if (!id_bit && !comp_bit) {
+ /* Both bits are valid, take the direction given */
+ retval = bdir ? 0x04 : 0;
+ } else {
+ /* Only one bit is valid, take that direction */
+ bdir = id_bit;
+ retval = id_bit ? 0x05 : 0x02;
+ }
+
+ w1_gpio_write_bit(dev, bdir);
+ return retval;
+}
+
+static const struct w1_ops w1_gpio_ops = {
+ .read_byte = w1_gpio_read_byte,
+ .reset = w1_gpio_reset,
+ .triplet = w1_gpio_triplet,
+ .write_byte = w1_gpio_write_byte,
+};
+
+static int w1_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+ struct w1_gpio_pdata *pdata = dev_get_platdata(dev);
+ int ret;
+
+ ret = gpio_request_by_name(dev, "gpios", 0, &pdata->gpio, 0);
+ if (ret < 0)
+ printf("Error claiming GPIO %d\n", ret);
+
+ return ret;
+};
+
+static const struct udevice_id w1_gpio_id[] = {
+ { "w1-gpio", 0 },
+ { },
+};
+
+U_BOOT_DRIVER(w1_gpio_drv) = {
+ .id = UCLASS_W1,
+ .name = "w1_gpio_drv",
+ .of_match = w1_gpio_id,
+ .ofdata_to_platdata = w1_gpio_ofdata_to_platdata,
+ .ops = &w1_gpio_ops,
+ .platdata_auto_alloc_size = sizeof(struct w1_gpio_pdata),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co.
+ * Copyright (c) 2018 Microchip Technology, Inc.
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ * Eugen Hristev <eugen.hristev@microchip.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <w1.h>
+#include <w1-eeprom.h>
+
+#include <dm/device-internal.h>
+
+#define W1_MATCH_ROM 0x55
+#define W1_SKIP_ROM 0xcc
+#define W1_SEARCH 0xf0
+
+struct w1_bus {
+ u64 search_id;
+};
+
+static int w1_enumerate(struct udevice *bus)
+{
+ const struct w1_ops *ops = device_get_ops(bus);
+ struct w1_bus *w1 = dev_get_uclass_priv(bus);
+ u64 last_rn, rn = w1->search_id, tmp64;
+ bool last_device = false;
+ int search_bit, desc_bit = 64;
+ int last_zero = -1;
+ u8 triplet_ret = 0;
+ int i;
+
+ if (!ops->reset || !ops->write_byte || !ops->triplet)
+ return -ENOSYS;
+
+ while (!last_device) {
+ last_rn = rn;
+ rn = 0;
+
+ /*
+ * Reset bus and all 1-wire device state machines
+ * so they can respond to our requests.
+ *
+ * Return 0 - device(s) present, 1 - no devices present.
+ */
+ if (ops->reset(bus)) {
+ debug("%s: No devices present on the wire.\n",
+ __func__);
+ break;
+ }
+
+ /* Start the search */
+ ops->write_byte(bus, W1_SEARCH);
+ for (i = 0; i < 64; ++i) {
+ /* Determine the direction/search bit */
+ if (i == desc_bit)
+ /* took the 0 path last time, so take the 1 path */
+ search_bit = 1;
+ else if (i > desc_bit)
+ /* take the 0 path on the next branch */
+ search_bit = 0;
+ else
+ search_bit = ((last_rn >> i) & 0x1);
+
+ /* Read two bits and write one bit */
+ triplet_ret = ops->triplet(bus, search_bit);
+
+ /* quit if no device responded */
+ if ((triplet_ret & 0x03) == 0x03)
+ break;
+
+ /* If both directions were valid, and we took the 0 path... */
+ if (triplet_ret == 0)
+ last_zero = i;
+
+ /* extract the direction taken & update the device number */
+ tmp64 = (triplet_ret >> 2);
+ rn |= (tmp64 << i);
+ }
+
+ /* last device or error, aborting here */
+ if ((triplet_ret & 0x03) == 0x03)
+ last_device = true;
+
+ if ((triplet_ret & 0x03) != 0x03) {
+ if (desc_bit == last_zero || last_zero < 0) {
+ last_device = 1;
+ w1->search_id = 0;
+ } else {
+ w1->search_id = rn;
+ }
+ desc_bit = last_zero;
+
+ debug("%s: Detected new device 0x%llx (family 0x%x)\n",
+ bus->name, rn, (u8)(rn & 0xff));
+
+ /* attempt to register as w1-eeprom device */
+ w1_eeprom_register_new_device(rn);
+ }
+ }
+
+ return 0;
+}
+
+int w1_get_bus(int busnum, struct udevice **busp)
+{
+ int ret, i = 0;
+
+ struct udevice *dev;
+
+ for (ret = uclass_first_device(UCLASS_W1, &dev);
+ !ret;
+ uclass_next_device(&dev), i++) {
+ if (ret) {
+ debug("Cannot find w1 bus %d\n", busnum);
+ return ret;
+ }
+ if (i == busnum) {
+ *busp = dev;
+ return 0;
+ }
+ }
+ return ret;
+}
+
+u8 w1_get_device_family(struct udevice *dev)
+{
+ struct w1_device *w1 = dev_get_parent_platdata(dev);
+
+ return w1->id & 0xff;
+}
+
+int w1_reset_select(struct udevice *dev)
+{
+ struct w1_device *w1 = dev_get_parent_platdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ const struct w1_ops *ops = device_get_ops(bus);
+ int i;
+
+ if (!ops->reset || !ops->write_byte)
+ return -ENOSYS;
+
+ ops->reset(bus);
+
+ ops->write_byte(bus, W1_MATCH_ROM);
+
+ for (i = 0; i < sizeof(w1->id); i++)
+ ops->write_byte(bus, (w1->id >> (i * 8)) & 0xff);
+
+ return 0;
+}
+
+int w1_read_byte(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ const struct w1_ops *ops = device_get_ops(bus);
+
+ if (!ops->read_byte)
+ return -ENOSYS;
+
+ return ops->read_byte(bus);
+}
+
+int w1_read_buf(struct udevice *dev, u8 *buf, unsigned int count)
+{
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ ret = w1_read_byte(dev);
+ if (ret < 0)
+ return ret;
+
+ buf[i] = ret & 0xff;
+ }
+
+ return 0;
+}
+
+int w1_write_byte(struct udevice *dev, u8 byte)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ const struct w1_ops *ops = device_get_ops(bus);
+
+ if (!ops->write_byte)
+ return -ENOSYS;
+
+ ops->write_byte(bus, byte);
+
+ return 0;
+}
+
+static int w1_post_probe(struct udevice *bus)
+{
+ w1_enumerate(bus);
+
+ return 0;
+}
+
+int w1_init(void)
+{
+ struct udevice *bus;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_W1, &uc);
+ if (ret)
+ return ret;
+
+ uclass_foreach_dev(bus, uc) {
+ ret = device_probe(bus);
+ if (ret == -ENODEV) { /* No such device. */
+ printf("W1 controller not available.\n");
+ continue;
+ }
+
+ if (ret) { /* Other error. */
+ printf("W1 controller probe failed.\n");
+ continue;
+ }
+ }
+ return 0;
+}
+
+UCLASS_DRIVER(w1) = {
+ .name = "w1",
+ .id = UCLASS_W1,
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+ .per_device_auto_alloc_size = sizeof(struct w1_bus),
+ .post_probe = w1_post_probe,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .post_bind = dm_scan_fdt_dev,
+#endif
+ .per_child_platdata_auto_alloc_size = sizeof(struct w1_device),
+};
clean-files := dt.dtb.S dt-spl.dtb.S
# Let clean descend into dts directories
-subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts
+subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts
#include "btrfs.h"
#include <malloc.h>
+#include <memalign.h>
int btrfs_comp_keys(struct btrfs_key *a, struct btrfs_key *b)
{
static int read_tree_node(u64 physical, union btrfs_tree_node **buf)
{
- struct btrfs_header hdr;
- unsigned long size, offset = sizeof(hdr);
+ ALLOC_CACHE_ALIGN_BUFFER(struct btrfs_header, hdr,
+ sizeof(struct btrfs_header));
+ unsigned long size, offset = sizeof(*hdr);
union btrfs_tree_node *res;
u32 i;
- if (!btrfs_devread(physical, sizeof(hdr), &hdr))
+ if (!btrfs_devread(physical, sizeof(*hdr), hdr))
return -1;
- btrfs_header_to_cpu(&hdr);
+ btrfs_header_to_cpu(hdr);
- if (hdr.level)
+ if (hdr->level)
size = sizeof(struct btrfs_node)
- + hdr.nritems * sizeof(struct btrfs_key_ptr);
+ + hdr->nritems * sizeof(struct btrfs_key_ptr);
else
size = btrfs_info.sb.nodesize;
- res = malloc(size);
+ res = malloc_cache_aligned(size);
if (!res) {
debug("%s: malloc failed\n", __func__);
return -1;
return -1;
}
- res->header = hdr;
- if (hdr.level)
- for (i = 0; i < hdr.nritems; ++i)
+ memcpy(&res->header, hdr, sizeof(*hdr));
+ if (hdr->level)
+ for (i = 0; i < hdr->nritems; ++i)
btrfs_key_ptr_to_cpu(&res->node.ptrs[i]);
else
- for (i = 0; i < hdr.nritems; ++i)
+ for (i = 0; i < hdr->nritems; ++i)
btrfs_item_to_cpu(&res->leaf.items[i]);
*buf = res;
#include "btrfs.h"
#include <malloc.h>
+#include <memalign.h>
u64 btrfs_read_extent_inline(struct btrfs_path *path,
struct btrfs_file_extent_item *extent, u64 offset,
return size;
}
- cbuf = malloc(dlen > size ? clen + dlen : clen);
+ cbuf = malloc_cache_aligned(dlen > size ? clen + dlen : clen);
if (!cbuf)
return -1ULL;
*/
#include "btrfs.h"
+#include <memalign.h>
#define BTRFS_SUPER_FLAG_SUPP (BTRFS_HEADER_FLAG_WRITTEN \
| BTRFS_HEADER_FLAG_RELOC \
0x4000000000ull,
0x4000000000000ull
};
- char raw_sb[BTRFS_SUPER_INFO_SIZE];
+ ALLOC_CACHE_ALIGN_BUFFER(char, raw_sb, BTRFS_SUPER_INFO_SIZE);
struct btrfs_super_block *sb = (struct btrfs_super_block *) raw_sb;
u64 dev_total_bytes;
int i;
if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {
ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
- printf("FAT: Misaligned buffer address (%p)\n", buffer);
+ debug("FAT: Misaligned buffer address (%p)\n", buffer);
while (size >= mydata->sect_size) {
ret = disk_read(startsect++, 1, tmpbuf);
return ret;
}
-/*
- * TODO these should go away once fat_write is reworked to use the
- * directory iterator
- */
-__u8 get_dentfromdir_block[MAX_CLUSTSIZE]
- __aligned(ARCH_DMA_MINALIGN);
-__u8 do_fat_read_at_block[MAX_CLUSTSIZE]
- __aligned(ARCH_DMA_MINALIGN);
-
/*
* Read boot sector and volume info from a FAT filesystem
*/
if (mydata->fatsize == 32) {
mydata->fatlength = bs.fat32_length;
+ mydata->total_sect = bs.total_sect;
} else {
mydata->fatlength = bs.fat_length;
+ mydata->total_sect = (bs.sectors[1] << 8) + bs.sectors[0];
+ if (!mydata->total_sect)
+ mydata->total_sect = bs.total_sect;
}
+ if (!mydata->total_sect) /* unlikely */
+ mydata->total_sect = (u32)cur_part_info.size;
+ mydata->fats = bs.fats;
mydata->fat_sect = bs.reserved;
mydata->rootdir_sect = mydata->fat_sect + mydata->fatlength * bs.fats;
typedef struct {
fsdata *fsdata; /* filesystem parameters */
+ unsigned start_clust; /* first cluster */
unsigned clust; /* current cluster */
+ unsigned next_clust; /* next cluster if remaining == 0 */
int last_cluster; /* set once we've read last cluster */
int is_root; /* is iterator at root directory */
int remaining; /* remaining dent's in current cluster */
return -ENXIO;
itr->fsdata = fsdata;
+ itr->start_clust = 0;
itr->clust = fsdata->root_cluster;
+ itr->next_clust = fsdata->root_cluster;
itr->dent = NULL;
itr->remaining = 0;
itr->last_cluster = 0;
assert(fat_itr_isdir(parent));
itr->fsdata = parent->fsdata;
+ itr->start_clust = clustnum;
if (clustnum > 0) {
itr->clust = clustnum;
+ itr->next_clust = clustnum;
itr->is_root = 0;
} else {
itr->clust = parent->fsdata->root_cluster;
+ itr->next_clust = parent->fsdata->root_cluster;
itr->is_root = 1;
}
itr->dent = NULL;
if (itr->last_cluster)
return NULL;
- sect = clust_to_sect(itr->fsdata, itr->clust);
+ sect = clust_to_sect(itr->fsdata, itr->next_clust);
debug("FAT read(sect=%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n",
sect, itr->fsdata->clust_size, DIRENTSPERBLOCK);
return NULL;
}
+ itr->clust = itr->next_clust;
if (itr->is_root && itr->fsdata->fatsize != 32) {
- itr->clust++;
- sect = clust_to_sect(itr->fsdata, itr->clust);
+ itr->next_clust++;
+ sect = clust_to_sect(itr->fsdata, itr->next_clust);
if (sect - itr->fsdata->rootdir_sect >=
itr->fsdata->rootdir_size) {
- debug("cursect: 0x%x\n", itr->clust);
+ debug("nextclust: 0x%x\n", itr->next_clust);
itr->last_cluster = 1;
}
} else {
- itr->clust = get_fatent(itr->fsdata, itr->clust);
- if (CHECK_CLUST(itr->clust, itr->fsdata->fatsize)) {
- debug("cursect: 0x%x\n", itr->clust);
+ itr->next_clust = get_fatent(itr->fsdata, itr->next_clust);
+ if (CHECK_CLUST(itr->next_clust, itr->fsdata->fatsize)) {
+ debug("nextclust: 0x%x\n", itr->next_clust);
itr->last_cluster = 1;
}
}
itr->fsdata->clust_size;
/* have we reached the last cluster? */
- if (!dent)
+ if (!dent) {
+ /* a sign for no more entries left */
+ itr->dent = NULL;
return NULL;
+ }
itr->remaining = nbytes / sizeof(dir_entry) - 1;
itr->dent = dent;
while (next[0] && !ISDIRDELIM(next[0]))
next++;
+ if (itr->is_root) {
+ /* root dir doesn't have "." nor ".." */
+ if ((((next - path) == 1) && !strncmp(path, ".", 1)) ||
+ (((next - path) == 2) && !strncmp(path, "..", 2))) {
+ /* point back to itself */
+ itr->clust = itr->fsdata->root_cluster;
+ itr->next_clust = itr->fsdata->root_cluster;
+ itr->dent = NULL;
+ itr->remaining = 0;
+ itr->last_cluster = 0;
+
+ if (next[0] == 0) {
+ if (type & TYPE_DIR)
+ return 0;
+ else
+ return -ENOENT;
+ }
+
+ return fat_itr_resolve(itr, next, type);
+ }
+ }
+
while (fat_itr_next(itr)) {
int match = 0;
unsigned n = max(strlen(itr->name), (size_t)(next - path));
debug("ext : %s\n", dirent->ext);
}
-static __u8 num_of_fats;
/*
* Write fat buffer into block device
*/
return -1;
}
- if (num_of_fats == 2) {
+ if (mydata->fats == 2) {
/* Update corresponding second FAT blocks */
startblock += mydata->fatlength;
if (disk_write(startblock, getsize, bufptr) < 0) {
return 1;
}
-static int is_next_clust(fsdata *mydata, dir_entry *dentptr);
-static void flush_dir_table(fsdata *mydata, dir_entry **dentptr);
+static int flush_dir_table(fat_itr *itr);
/*
* Fill dir_slot entries with appropriate name, id, and attr
- * The real directory entry is returned by 'dentptr'
+ * 'itr' will point to a next entry
*/
-static void
-fill_dir_slot(fsdata *mydata, dir_entry **dentptr, const char *l_name)
+static int
+fill_dir_slot(fat_itr *itr, const char *l_name)
{
__u8 temp_dir_slot_buffer[MAX_LFN_SLOT * sizeof(dir_slot)];
dir_slot *slotptr = (dir_slot *)temp_dir_slot_buffer;
int idx = 0, ret;
/* Get short file name checksum value */
- checksum = mkcksum((*dentptr)->name, (*dentptr)->ext);
+ checksum = mkcksum(itr->dent->name, itr->dent->ext);
do {
memset(slotptr, 0x00, sizeof(dir_slot));
slotptr->id |= LAST_LONG_ENTRY_MASK;
while (counter >= 1) {
- if (is_next_clust(mydata, *dentptr)) {
- /* A new cluster is allocated for directory table */
- flush_dir_table(mydata, dentptr);
- }
- memcpy(*dentptr, slotptr, sizeof(dir_slot));
- (*dentptr)++;
+ memcpy(itr->dent, slotptr, sizeof(dir_slot));
slotptr--;
counter--;
- }
-
- if (is_next_clust(mydata, *dentptr)) {
- /* A new cluster is allocated for directory table */
- flush_dir_table(mydata, dentptr);
- }
-}
-
-static __u32 dir_curclust;
-
-/*
- * Extract the full long filename starting at 'retdent' (which is really
- * a slot) into 'l_name'. If successful also copy the real directory entry
- * into 'retdent'
- * If additional adjacent cluster for directory entries is read into memory,
- * then 'get_contents_vfatname_block' is copied into 'get_dentfromdir_block' and
- * the location of the real directory entry is returned by 'retdent'
- * Return 0 on success, -1 otherwise.
- */
-static int
-get_long_file_name(fsdata *mydata, int curclust, __u8 *cluster,
- dir_entry **retdent, char *l_name)
-{
- dir_entry *realdent;
- dir_slot *slotptr = (dir_slot *)(*retdent);
- dir_slot *slotptr2 = NULL;
- __u8 *buflimit = cluster + mydata->sect_size * ((curclust == 0) ?
- PREFETCH_BLOCKS :
- mydata->clust_size);
- __u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff;
- int idx = 0, cur_position = 0;
-
- if (counter > VFAT_MAXSEQ) {
- debug("Error: VFAT name is too long\n");
- return -1;
- }
-
- while ((__u8 *)slotptr < buflimit) {
- if (counter == 0)
- break;
- if (((slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff) != counter)
- return -1;
- slotptr++;
- counter--;
- }
-
- if ((__u8 *)slotptr >= buflimit) {
- if (curclust == 0)
- return -1;
- curclust = get_fatent(mydata, dir_curclust);
- if (CHECK_CLUST(curclust, mydata->fatsize)) {
- debug("curclust: 0x%x\n", curclust);
- printf("Invalid FAT entry\n");
- return -1;
- }
-
- dir_curclust = curclust;
-
- if (get_cluster(mydata, curclust, get_contents_vfatname_block,
- mydata->clust_size * mydata->sect_size) != 0) {
- debug("Error: reading directory block\n");
- return -1;
- }
-
- slotptr2 = (dir_slot *)get_contents_vfatname_block;
- while (counter > 0) {
- if (((slotptr2->id & ~LAST_LONG_ENTRY_MASK)
- & 0xff) != counter)
+ if (!fat_itr_next(itr))
+ if (!itr->dent && !itr->is_root && flush_dir_table(itr))
return -1;
- slotptr2++;
- counter--;
- }
-
- /* Save the real directory entry */
- realdent = (dir_entry *)slotptr2;
- while ((__u8 *)slotptr2 > get_contents_vfatname_block) {
- slotptr2--;
- slot2str(slotptr2, l_name, &idx);
- }
- } else {
- /* Save the real directory entry */
- realdent = (dir_entry *)slotptr;
}
- do {
- slotptr--;
- if (slot2str(slotptr, l_name, &idx))
- break;
- } while (!(slotptr->id & LAST_LONG_ENTRY_MASK));
-
- l_name[idx] = '\0';
- if (*l_name == DELETED_FLAG)
- *l_name = '\0';
- else if (*l_name == aRING)
- *l_name = DELETED_FLAG;
- downcase(l_name, INT_MAX);
-
- /* Return the real directory entry */
- *retdent = realdent;
-
- if (slotptr2) {
- memcpy(get_dentfromdir_block, get_contents_vfatname_block,
- mydata->clust_size * mydata->sect_size);
- cur_position = (__u8 *)realdent - get_contents_vfatname_block;
- *retdent = (dir_entry *) &get_dentfromdir_block[cur_position];
- }
+ if (!itr->dent && !itr->is_root)
+ /*
+ * don't care return value here because we have already
+ * finished completing an entry with name, only ending up
+ * no more entry left
+ */
+ flush_dir_table(itr);
return 0;
}
if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {
ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
- printf("FAT: Misaligned buffer address (%p)\n", buffer);
+ debug("FAT: Misaligned buffer address (%p)\n", buffer);
while (size >= mydata->sect_size) {
memcpy(tmpbuf, buffer, mydata->sect_size);
return 0;
}
+static __u8 tmpbuf_cluster[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN);
+
+/*
+ * Read and modify data on existing and consecutive cluster blocks
+ */
+static int
+get_set_cluster(fsdata *mydata, __u32 clustnum, loff_t pos, __u8 *buffer,
+ loff_t size, loff_t *gotsize)
+{
+ unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
+ __u32 startsect;
+ loff_t wsize;
+ int clustcount, i, ret;
+
+ *gotsize = 0;
+ if (!size)
+ return 0;
+
+ assert(pos < bytesperclust);
+ startsect = clust_to_sect(mydata, clustnum);
+
+ debug("clustnum: %d, startsect: %d, pos: %lld\n",
+ clustnum, startsect, pos);
+
+ /* partial write at beginning */
+ if (pos) {
+ wsize = min(bytesperclust - pos, size);
+ ret = disk_read(startsect, mydata->clust_size, tmpbuf_cluster);
+ if (ret != mydata->clust_size) {
+ debug("Error reading data (got %d)\n", ret);
+ return -1;
+ }
+
+ memcpy(tmpbuf_cluster + pos, buffer, wsize);
+ ret = disk_write(startsect, mydata->clust_size, tmpbuf_cluster);
+ if (ret != mydata->clust_size) {
+ debug("Error writing data (got %d)\n", ret);
+ return -1;
+ }
+
+ size -= wsize;
+ buffer += wsize;
+ *gotsize += wsize;
+
+ startsect += mydata->clust_size;
+
+ if (!size)
+ return 0;
+ }
+
+ /* full-cluster write */
+ if (size >= bytesperclust) {
+ clustcount = lldiv(size, bytesperclust);
+
+ if (!((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1))) {
+ wsize = clustcount * bytesperclust;
+ ret = disk_write(startsect,
+ clustcount * mydata->clust_size,
+ buffer);
+ if (ret != clustcount * mydata->clust_size) {
+ debug("Error writing data (got %d)\n", ret);
+ return -1;
+ }
+
+ size -= wsize;
+ buffer += wsize;
+ *gotsize += wsize;
+
+ startsect += clustcount * mydata->clust_size;
+ } else {
+ for (i = 0; i < clustcount; i++) {
+ memcpy(tmpbuf_cluster, buffer, bytesperclust);
+ ret = disk_write(startsect,
+ mydata->clust_size,
+ tmpbuf_cluster);
+ if (ret != mydata->clust_size) {
+ debug("Error writing data (got %d)\n",
+ ret);
+ return -1;
+ }
+
+ size -= bytesperclust;
+ buffer += bytesperclust;
+ *gotsize += bytesperclust;
+
+ startsect += mydata->clust_size;
+ }
+ }
+ }
+
+ /* partial write at end */
+ if (size) {
+ wsize = size;
+ ret = disk_read(startsect, mydata->clust_size, tmpbuf_cluster);
+ if (ret != mydata->clust_size) {
+ debug("Error reading data (got %d)\n", ret);
+ return -1;
+ }
+ memcpy(tmpbuf_cluster, buffer, wsize);
+ ret = disk_write(startsect, mydata->clust_size, tmpbuf_cluster);
+ if (ret != mydata->clust_size) {
+ debug("Error writing data (got %d)\n", ret);
+ return -1;
+ }
+
+ size -= wsize;
+ buffer += wsize;
+ *gotsize += wsize;
+ }
+
+ assert(!size);
+
+ return 0;
+}
+
/*
* Find the first empty cluster
*/
}
/*
- * Write directory entries in 'get_dentfromdir_block' to block device
+ * Write directory entries in itr's buffer to block device
*/
-static void flush_dir_table(fsdata *mydata, dir_entry **dentptr)
+static int flush_dir_table(fat_itr *itr)
{
+ fsdata *mydata = itr->fsdata;
int dir_newclust = 0;
+ unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
- if (set_cluster(mydata, dir_curclust,
- get_dentfromdir_block,
- mydata->clust_size * mydata->sect_size) != 0) {
- printf("error: wrinting directory entry\n");
- return;
+ if (set_cluster(mydata, itr->clust, itr->block, bytesperclust) != 0) {
+ printf("error: writing directory entry\n");
+ return -1;
}
dir_newclust = find_empty_cluster(mydata);
- set_fatent_value(mydata, dir_curclust, dir_newclust);
+ set_fatent_value(mydata, itr->clust, dir_newclust);
if (mydata->fatsize == 32)
set_fatent_value(mydata, dir_newclust, 0xffffff8);
else if (mydata->fatsize == 16)
else if (mydata->fatsize == 12)
set_fatent_value(mydata, dir_newclust, 0xff8);
- dir_curclust = dir_newclust;
+ itr->clust = dir_newclust;
+ itr->next_clust = dir_newclust;
if (flush_dirty_fat_buffer(mydata) < 0)
- return;
+ return -1;
- memset(get_dentfromdir_block, 0x00,
- mydata->clust_size * mydata->sect_size);
+ memset(itr->block, 0x00, bytesperclust);
- *dentptr = (dir_entry *) get_dentfromdir_block;
+ itr->dent = (dir_entry *)itr->block;
+ itr->last_cluster = 1;
+ itr->remaining = bytesperclust / sizeof(dir_entry) - 1;
+
+ return 0;
}
/*
return 0;
}
+/*
+ * Set start cluster in directory entry
+ */
+static void set_start_cluster(const fsdata *mydata, dir_entry *dentptr,
+ __u32 start_cluster)
+{
+ if (mydata->fatsize == 32)
+ dentptr->starthi =
+ cpu_to_le16((start_cluster & 0xffff0000) >> 16);
+ dentptr->start = cpu_to_le16(start_cluster & 0xffff);
+}
+
+/*
+ * Check whether adding a file makes the file system to
+ * exceed the size of the block device
+ * Return -1 when overflow occurs, otherwise return 0
+ */
+static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size)
+{
+ __u32 startsect, sect_num, offset;
+
+ if (clustnum > 0)
+ startsect = clust_to_sect(mydata, clustnum);
+ else
+ startsect = mydata->rootdir_sect;
+
+ sect_num = div_u64_rem(size, mydata->sect_size, &offset);
+
+ if (offset != 0)
+ sect_num++;
+
+ if (startsect + sect_num > total_sector)
+ return -1;
+ return 0;
+}
+
/*
* Write at most 'maxsize' bytes from 'buffer' into
* the file associated with 'dentptr'
* or return -1 on fatal errors.
*/
static int
-set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer,
- loff_t maxsize, loff_t *gotsize)
+set_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, __u8 *buffer,
+ loff_t maxsize, loff_t *gotsize)
{
- loff_t filesize = FAT2CPU32(dentptr->size);
+ loff_t filesize;
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
__u32 curclust = START(dentptr);
__u32 endclust = 0, newclust = 0;
- loff_t actsize;
+ loff_t cur_pos, offset, actsize, wsize;
*gotsize = 0;
- debug("Filesize: %llu bytes\n", filesize);
-
- if (maxsize > 0 && filesize > maxsize)
- filesize = maxsize;
+ filesize = pos + maxsize;
debug("%llu bytes\n", filesize);
+ if (!filesize) {
+ if (!curclust)
+ return 0;
+ if (!CHECK_CLUST(curclust, mydata->fatsize) ||
+ IS_LAST_CLUST(curclust, mydata->fatsize)) {
+ clear_fatent(mydata, curclust);
+ set_start_cluster(mydata, dentptr, 0);
+ return 0;
+ }
+ debug("curclust: 0x%x\n", curclust);
+ debug("Invalid FAT entry\n");
+ return -1;
+ }
+
if (!curclust) {
- if (filesize) {
- debug("error: nonempty clusterless file!\n");
+ assert(pos == 0);
+ goto set_clusters;
+ }
+
+ /* go to cluster at pos */
+ cur_pos = bytesperclust;
+ while (1) {
+ if (pos <= cur_pos)
+ break;
+ if (IS_LAST_CLUST(curclust, mydata->fatsize))
+ break;
+
+ newclust = get_fatent(mydata, curclust);
+ if (!IS_LAST_CLUST(newclust, mydata->fatsize) &&
+ CHECK_CLUST(newclust, mydata->fatsize)) {
+ debug("curclust: 0x%x\n", curclust);
+ debug("Invalid FAT entry\n");
return -1;
}
+
+ cur_pos += bytesperclust;
+ curclust = newclust;
+ }
+ if (IS_LAST_CLUST(curclust, mydata->fatsize)) {
+ assert(pos == cur_pos);
+ goto set_clusters;
+ }
+
+ assert(pos < cur_pos);
+ cur_pos -= bytesperclust;
+
+ /* overwrite */
+ assert(IS_LAST_CLUST(curclust, mydata->fatsize) ||
+ !CHECK_CLUST(curclust, mydata->fatsize));
+
+ while (1) {
+ /* search for allocated consecutive clusters */
+ actsize = bytesperclust;
+ endclust = curclust;
+ while (1) {
+ if (filesize <= (cur_pos + actsize))
+ break;
+
+ newclust = get_fatent(mydata, endclust);
+
+ if (IS_LAST_CLUST(newclust, mydata->fatsize))
+ break;
+ if (CHECK_CLUST(newclust, mydata->fatsize)) {
+ debug("curclust: 0x%x\n", curclust);
+ debug("Invalid FAT entry\n");
+ return -1;
+ }
+
+ actsize += bytesperclust;
+ endclust = newclust;
+ }
+
+ /* overwrite to <curclust..endclust> */
+ if (pos < cur_pos)
+ offset = 0;
+ else
+ offset = pos - cur_pos;
+ wsize = min(cur_pos + actsize, filesize) - pos;
+ if (get_set_cluster(mydata, curclust, offset,
+ buffer, wsize, &actsize)) {
+ printf("Error get-and-setting cluster\n");
+ return -1;
+ }
+ buffer += wsize;
+ *gotsize += wsize;
+ cur_pos += offset + wsize;
+
+ if (filesize <= cur_pos)
+ break;
+
+ /* CHECK: newclust = get_fatent(mydata, endclust); */
+
+ if (IS_LAST_CLUST(newclust, mydata->fatsize))
+ /* no more clusters */
+ break;
+
+ curclust = newclust;
+ }
+
+ if (filesize <= cur_pos) {
+ /* no more write */
+ newclust = get_fatent(mydata, endclust);
+ if (!IS_LAST_CLUST(newclust, mydata->fatsize)) {
+ /* truncate the rest */
+ clear_fatent(mydata, newclust);
+
+ /* Mark end of file in FAT */
+ if (mydata->fatsize == 12)
+ newclust = 0xfff;
+ else if (mydata->fatsize == 16)
+ newclust = 0xffff;
+ else if (mydata->fatsize == 32)
+ newclust = 0xfffffff;
+ set_fatent_value(mydata, endclust, newclust);
+ }
+
return 0;
}
+ curclust = endclust;
+ filesize -= cur_pos;
+ assert(!(cur_pos % bytesperclust));
+
+set_clusters:
+ /* allocate and write */
+ assert(!pos);
+
+ /* Assure that curclust is valid */
+ if (!curclust) {
+ curclust = find_empty_cluster(mydata);
+ set_start_cluster(mydata, dentptr, curclust);
+ } else {
+ newclust = get_fatent(mydata, curclust);
+
+ if (IS_LAST_CLUST(newclust, mydata->fatsize)) {
+ newclust = determine_fatent(mydata, curclust);
+ set_fatent_value(mydata, curclust, newclust);
+ curclust = newclust;
+ } else {
+ debug("error: something wrong\n");
+ return -1;
+ }
+ }
+
+ /* TODO: already partially written */
+ if (check_overflow(mydata, curclust, filesize)) {
+ printf("Error: no space left: %llu\n", filesize);
+ return -1;
+ }
+
actsize = bytesperclust;
endclust = curclust;
do {
newclust = determine_fatent(mydata, endclust);
if ((newclust - 1) != endclust)
+ /* write to <curclust..endclust> */
goto getit;
if (CHECK_CLUST(newclust, mydata->fatsize)) {
actsize = bytesperclust;
curclust = endclust = newclust;
} while (1);
-}
-/*
- * Set start cluster in directory entry
- */
-static void set_start_cluster(const fsdata *mydata, dir_entry *dentptr,
- __u32 start_cluster)
-{
- if (mydata->fatsize == 32)
- dentptr->starthi =
- cpu_to_le16((start_cluster & 0xffff0000) >> 16);
- dentptr->start = cpu_to_le16(start_cluster & 0xffff);
+ return 0;
}
/*
}
/*
- * Check whether adding a file makes the file system to
- * exceed the size of the block device
- * Return -1 when overflow occurs, otherwise return 0
+ * Find a directory entry based on filename or start cluster number
+ * If the directory entry is not found,
+ * the new position for writing a directory entry will be returned
*/
-static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size)
+static dir_entry *find_directory_entry(fat_itr *itr, char *filename)
{
- __u32 startsect, sect_num, offset;
+ int match = 0;
- if (clustnum > 0) {
- startsect = clust_to_sect(mydata, clustnum);
- } else {
- startsect = mydata->rootdir_sect;
+ while (fat_itr_next(itr)) {
+ /* check both long and short name: */
+ if (!strcasecmp(filename, itr->name))
+ match = 1;
+ else if (itr->name != itr->s_name &&
+ !strcasecmp(filename, itr->s_name))
+ match = 1;
+
+ if (!match)
+ continue;
+
+ if (itr->dent->name[0] == '\0')
+ return NULL;
+ else
+ return itr->dent;
}
- sect_num = div_u64_rem(size, mydata->sect_size, &offset);
+ if (!itr->dent && !itr->is_root && flush_dir_table(itr))
+ /* indicate that allocating dent failed */
+ itr->dent = NULL;
- if (offset != 0)
- sect_num++;
+ return NULL;
+}
+
+static int split_filename(char *filename, char **dirname, char **basename)
+{
+ char *p, *last_slash, *last_slash_cont;
+
+again:
+ p = filename;
+ last_slash = NULL;
+ last_slash_cont = NULL;
+ while (*p) {
+ if (ISDIRDELIM(*p)) {
+ last_slash = p;
+ last_slash_cont = p;
+ /* continuous slashes */
+ while (ISDIRDELIM(*p))
+ last_slash_cont = p++;
+ if (!*p)
+ break;
+ }
+ p++;
+ }
+
+ if (last_slash) {
+ if (last_slash_cont == (filename + strlen(filename) - 1)) {
+ /* remove trailing slashes */
+ *last_slash = '\0';
+ goto again;
+ }
+
+ if (last_slash == filename) {
+ /* avoid ""(null) directory */
+ *dirname = "/";
+ } else {
+ *last_slash = '\0';
+ *dirname = filename;
+ }
+
+ *last_slash_cont = '\0';
+ *basename = last_slash_cont + 1;
+ } else {
+ *dirname = "/"; /* root by default */
+ *basename = filename;
+ }
- if (startsect + sect_num > total_sector)
- return -1;
return 0;
}
-/*
- * Check if adding several entries exceed one cluster boundary
- */
-static int is_next_clust(fsdata *mydata, dir_entry *dentptr)
+static int normalize_longname(char *l_filename, const char *filename)
{
- int cur_position;
+ const char *p, legal[] = "!#$%&\'()-.@^`_{}~";
+ char c;
+ int name_len;
- cur_position = (__u8 *)dentptr - get_dentfromdir_block;
+ /* Check that the filename is valid */
+ for (p = filename; p < filename + strlen(filename); p++) {
+ c = *p;
+
+ if (('0' <= c) && (c <= '9'))
+ continue;
+ if (('A' <= c) && (c <= 'Z'))
+ continue;
+ if (('a' <= c) && (c <= 'z'))
+ continue;
+ if (strchr(legal, c))
+ continue;
+ /* extended code */
+ if ((0x80 <= c) && (c <= 0xff))
+ continue;
- if (cur_position >= mydata->clust_size * mydata->sect_size)
- return 1;
- else
- return 0;
+ return -1;
+ }
+
+ /* Normalize it */
+ name_len = strlen(filename);
+ if (name_len >= VFAT_MAXLEN_BYTES)
+ /* should return an error? */
+ name_len = VFAT_MAXLEN_BYTES - 1;
+
+ memcpy(l_filename, filename, name_len);
+ l_filename[name_len] = 0; /* terminate the string */
+ downcase(l_filename, INT_MAX);
+
+ return 0;
}
-static dir_entry *empty_dentptr;
-/*
- * Find a directory entry based on filename or start cluster number
- * If the directory entry is not found,
- * the new position for writing a directory entry will be returned
- */
-static dir_entry *find_directory_entry(fsdata *mydata, int startsect,
- char *filename, dir_entry *retdent, __u32 start)
+int file_fat_write_at(const char *filename, loff_t pos, void *buffer,
+ loff_t size, loff_t *actwrite)
{
- __u32 curclust = sect_to_clust(mydata, startsect);
+ dir_entry *retdent;
+ fsdata datablock = { .fatbuf = NULL, };
+ fsdata *mydata = &datablock;
+ fat_itr *itr = NULL;
+ int ret = -1;
+ char *filename_copy, *parent, *basename;
+ char l_filename[VFAT_MAXLEN_BYTES];
- debug("get_dentfromdir: %s\n", filename);
+ debug("writing %s\n", filename);
- while (1) {
- dir_entry *dentptr;
+ filename_copy = strdup(filename);
+ if (!filename_copy)
+ return -ENOMEM;
- int i;
+ split_filename(filename_copy, &parent, &basename);
+ if (!strlen(basename)) {
+ ret = -EINVAL;
+ goto exit;
+ }
- if (get_cluster(mydata, curclust, get_dentfromdir_block,
- mydata->clust_size * mydata->sect_size) != 0) {
- printf("Error: reading directory block\n");
- return NULL;
- }
+ filename = basename;
+ if (normalize_longname(l_filename, filename)) {
+ printf("FAT: illegal filename (%s)\n", filename);
+ ret = -EINVAL;
+ goto exit;
+ }
- dentptr = (dir_entry *)get_dentfromdir_block;
+ itr = malloc_cache_aligned(sizeof(fat_itr));
+ if (!itr) {
+ ret = -ENOMEM;
+ goto exit;
+ }
- dir_curclust = curclust;
+ ret = fat_itr_root(itr, &datablock);
+ if (ret)
+ goto exit;
- for (i = 0; i < DIRENTSPERCLUST; i++) {
- char s_name[14], l_name[VFAT_MAXLEN_BYTES];
+ total_sector = datablock.total_sect;
- l_name[0] = '\0';
- if (dentptr->name[0] == DELETED_FLAG) {
- dentptr++;
- if (is_next_clust(mydata, dentptr))
- break;
- continue;
- }
- if ((dentptr->attr & ATTR_VOLUME)) {
- if ((dentptr->attr & ATTR_VFAT) &&
- (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
- get_long_file_name(mydata, curclust,
- get_dentfromdir_block,
- &dentptr, l_name);
- debug("vfatname: |%s|\n", l_name);
- } else {
- /* Volume label or VFAT entry */
- dentptr++;
- if (is_next_clust(mydata, dentptr))
- break;
- continue;
- }
- }
- if (dentptr->name[0] == 0) {
- debug("Dentname == NULL - %d\n", i);
- empty_dentptr = dentptr;
- return NULL;
- }
+ ret = fat_itr_resolve(itr, parent, TYPE_DIR);
+ if (ret) {
+ printf("%s: doesn't exist (%d)\n", parent, ret);
+ goto exit;
+ }
- get_name(dentptr, s_name);
+ retdent = find_directory_entry(itr, l_filename);
- if (strncasecmp(filename, s_name, sizeof(s_name)) &&
- strncasecmp(filename, l_name, sizeof(l_name))) {
- debug("Mismatch: |%s|%s|\n",
- s_name, l_name);
- dentptr++;
- if (is_next_clust(mydata, dentptr))
- break;
- continue;
- }
+ if (retdent) {
+ if (fat_itr_isdir(itr)) {
+ ret = -EISDIR;
+ goto exit;
+ }
- memcpy(retdent, dentptr, sizeof(dir_entry));
+ /* A file exists */
+ if (pos == -1)
+ /* Append to the end */
+ pos = FAT2CPU32(retdent->size);
+ if (pos > retdent->size) {
+ /* No hole allowed */
+ ret = -EINVAL;
+ goto exit;
+ }
- debug("DentName: %s", s_name);
- debug(", start: 0x%x", START(dentptr));
- debug(", size: 0x%x %s\n",
- FAT2CPU32(dentptr->size),
- (dentptr->attr & ATTR_DIR) ?
- "(DIR)" : "");
+ /* Update file size in a directory entry */
+ retdent->size = cpu_to_le32(pos + size);
+ } else {
+ /* Create a new file */
- return dentptr;
+ if (itr->is_root) {
+ /* root dir cannot have "." or ".." */
+ if (!strcmp(l_filename, ".") ||
+ !strcmp(l_filename, "..")) {
+ ret = -EINVAL;
+ goto exit;
+ }
}
- /*
- * In FAT16/12, the root dir is locate before data area, shows
- * in following:
- * -------------------------------------------------------------
- * | Boot | FAT1 & 2 | Root dir | Data (start from cluster #2) |
- * -------------------------------------------------------------
- *
- * As a result if curclust is in Root dir, it is a negative
- * number or 0, 1.
- *
- */
- if (mydata->fatsize != 32 && (int)curclust <= 1) {
- /* Current clust is in root dir, set to next clust */
- curclust++;
- if ((int)curclust <= 1)
- continue; /* continue to find */
-
- /* Reach the end of root dir */
- empty_dentptr = dentptr;
- return NULL;
+ if (!itr->dent) {
+ printf("Error: allocating new dir entry\n");
+ ret = -EIO;
+ goto exit;
}
- curclust = get_fatent(mydata, dir_curclust);
- if (IS_LAST_CLUST(curclust, mydata->fatsize)) {
- empty_dentptr = dentptr;
- return NULL;
+ if (pos) {
+ /* No hole allowed */
+ ret = -EINVAL;
+ goto exit;
}
- if (CHECK_CLUST(curclust, mydata->fatsize)) {
- debug("curclust: 0x%x\n", curclust);
- debug("Invalid FAT entry\n");
- return NULL;
+
+ memset(itr->dent, 0, sizeof(*itr->dent));
+
+ /* Set short name to set alias checksum field in dir_slot */
+ set_name(itr->dent, filename);
+ if (fill_dir_slot(itr, filename)) {
+ ret = -EIO;
+ goto exit;
}
+
+ /* Set attribute as archive for regular file */
+ fill_dentry(itr->fsdata, itr->dent, filename, 0, size, 0x20);
+
+ retdent = itr->dent;
}
- return NULL;
+ ret = set_contents(mydata, retdent, pos, buffer, size, actwrite);
+ if (ret < 0) {
+ printf("Error: writing contents\n");
+ ret = -EIO;
+ goto exit;
+ }
+ debug("attempt to write 0x%llx bytes\n", *actwrite);
+
+ /* Flush fat buffer */
+ ret = flush_dirty_fat_buffer(mydata);
+ if (ret) {
+ printf("Error: flush fat buffer\n");
+ ret = -EIO;
+ goto exit;
+ }
+
+ /* Write directory table to device */
+ ret = set_cluster(mydata, itr->clust, itr->block,
+ mydata->clust_size * mydata->sect_size);
+ if (ret) {
+ printf("Error: writing directory entry\n");
+ ret = -EIO;
+ }
+
+exit:
+ free(filename_copy);
+ free(mydata->fatbuf);
+ free(itr);
+ return ret;
}
-static int do_fat_write(const char *filename, void *buffer, loff_t size,
- loff_t *actwrite)
+int file_fat_write(const char *filename, void *buffer, loff_t offset,
+ loff_t maxsize, loff_t *actwrite)
{
- dir_entry *dentptr, *retdent;
- __u32 startsect;
- __u32 start_cluster;
- boot_sector bs;
- volume_info volinfo;
- fsdata datablock;
- fsdata *mydata = &datablock;
- int cursect, i;
- int ret = -1, name_len;
- char l_filename[VFAT_MAXLEN_BYTES];
- char bad[2] = " ";
- const char illegal[] = "<>:\"/\\|?*";
+ return file_fat_write_at(filename, offset, buffer, maxsize, actwrite);
+}
- *actwrite = size;
- dir_curclust = 0;
+static int fat_dir_entries(fat_itr *itr)
+{
+ fat_itr *dirs;
+ fsdata fsdata = { .fatbuf = NULL, }, *mydata = &fsdata;
+ /* for FATBUFSIZE */
+ int count;
- if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) {
- debug("error: reading boot sector\n");
- return -1;
+ dirs = malloc_cache_aligned(sizeof(fat_itr));
+ if (!dirs) {
+ debug("Error: allocating memory\n");
+ count = -ENOMEM;
+ goto exit;
}
- total_sector = bs.total_sect;
- if (total_sector == 0)
- total_sector = (int)cur_part_info.size; /* cast of lbaint_t */
+ /* duplicate fsdata */
+ fat_itr_child(dirs, itr);
+ fsdata = *dirs->fsdata;
- if (mydata->fatsize == 32)
- mydata->fatlength = bs.fat32_length;
- else
- mydata->fatlength = bs.fat_length;
+ /* allocate local fat buffer */
+ fsdata.fatbuf = malloc_cache_aligned(FATBUFSIZE);
+ if (!fsdata.fatbuf) {
+ debug("Error: allocating memory\n");
+ count = -ENOMEM;
+ goto exit;
+ }
+ fsdata.fatbufnum = -1;
+ dirs->fsdata = &fsdata;
- mydata->fat_sect = bs.reserved;
+ for (count = 0; fat_itr_next(dirs); count++)
+ ;
- cursect = mydata->rootdir_sect
- = mydata->fat_sect + mydata->fatlength * bs.fats;
- num_of_fats = bs.fats;
+exit:
+ free(fsdata.fatbuf);
+ free(dirs);
+ return count;
+}
- mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0];
- mydata->clust_size = bs.cluster_size;
+static int delete_dentry(fat_itr *itr)
+{
+ fsdata *mydata = itr->fsdata;
+ dir_entry *dentptr = itr->dent;
- if (mydata->fatsize == 32) {
- mydata->data_begin = mydata->rootdir_sect -
- (mydata->clust_size * 2);
- } else {
- int rootdir_size;
-
- rootdir_size = ((bs.dir_entries[1] * (int)256 +
- bs.dir_entries[0]) *
- sizeof(dir_entry)) /
- mydata->sect_size;
- mydata->data_begin = mydata->rootdir_sect +
- rootdir_size -
- (mydata->clust_size * 2);
+ /* free cluster blocks */
+ clear_fatent(mydata, START(dentptr));
+ if (flush_dirty_fat_buffer(mydata) < 0) {
+ printf("Error: flush fat buffer\n");
+ return -EIO;
}
- mydata->fatbufnum = -1;
- mydata->fat_dirty = 0;
- mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
- if (mydata->fatbuf == NULL) {
- debug("Error: allocating memory\n");
- return -1;
+ /*
+ * update a directory entry
+ * TODO:
+ * - long file name support
+ * - find and mark the "new" first invalid entry as name[0]=0x00
+ */
+ memset(dentptr, 0, sizeof(*dentptr));
+ dentptr->name[0] = 0xe5;
+
+ if (set_cluster(mydata, itr->clust, itr->block,
+ mydata->clust_size * mydata->sect_size) != 0) {
+ printf("error: writing directory entry\n");
+ return -EIO;
}
- if (disk_read(cursect,
- (mydata->fatsize == 32) ?
- (mydata->clust_size) :
- PREFETCH_BLOCKS, do_fat_read_at_block) < 0) {
- debug("Error: reading rootdir block\n");
+ return 0;
+}
+
+int fat_unlink(const char *filename)
+{
+ fsdata fsdata = { .fatbuf = NULL, };
+ fat_itr *itr = NULL;
+ int n_entries, ret;
+ char *filename_copy, *dirname, *basename;
+
+ filename_copy = strdup(filename);
+ split_filename(filename_copy, &dirname, &basename);
+
+ if (!strcmp(dirname, "/") && !strcmp(basename, "")) {
+ printf("Error: cannot remove root\n");
+ ret = -EINVAL;
goto exit;
}
- dentptr = (dir_entry *) do_fat_read_at_block;
- /* Strip leading (back-)slashes */
- while ISDIRDELIM(*filename)
- ++filename;
- /* Check that the filename is valid */
- for (i = 0; i < strlen(illegal); ++i) {
- *bad = illegal[i];
- if (strstr(filename, bad)) {
- printf("FAT: illegal filename (%s)\n", filename);
- return -1;
+ itr = malloc_cache_aligned(sizeof(fat_itr));
+ if (!itr) {
+ printf("Error: allocating memory\n");
+ return -ENOMEM;
+ }
+
+ ret = fat_itr_root(itr, &fsdata);
+ if (ret)
+ goto exit;
+
+ total_sector = fsdata.total_sect;
+
+ ret = fat_itr_resolve(itr, dirname, TYPE_DIR);
+ if (ret) {
+ printf("%s: doesn't exist (%d)\n", dirname, ret);
+ ret = -ENOENT;
+ goto exit;
+ }
+
+ if (!find_directory_entry(itr, basename)) {
+ printf("%s: doesn't exist\n", basename);
+ ret = -ENOENT;
+ goto exit;
+ }
+
+ if (fat_itr_isdir(itr)) {
+ n_entries = fat_dir_entries(itr);
+ if (n_entries < 0) {
+ ret = n_entries;
+ goto exit;
+ }
+ if (n_entries > 2) {
+ printf("Error: directory is not empty: %d\n",
+ n_entries);
+ ret = -EINVAL;
+ goto exit;
}
}
- name_len = strlen(filename);
- if (name_len >= VFAT_MAXLEN_BYTES)
- name_len = VFAT_MAXLEN_BYTES - 1;
+ ret = delete_dentry(itr);
- memcpy(l_filename, filename, name_len);
- l_filename[name_len] = 0; /* terminate the string */
- downcase(l_filename, INT_MAX);
+exit:
+ free(fsdata.fatbuf);
+ free(itr);
+ free(filename_copy);
- startsect = mydata->rootdir_sect;
- retdent = find_directory_entry(mydata, startsect,
- l_filename, dentptr, 0);
- if (retdent) {
- /* Update file size and start_cluster in a directory entry */
- retdent->size = cpu_to_le32(size);
- start_cluster = START(retdent);
-
- if (start_cluster) {
- if (size) {
- ret = check_overflow(mydata, start_cluster,
- size);
- if (ret) {
- printf("Error: %llu overflow\n", size);
- goto exit;
- }
- }
+ return ret;
+}
- ret = clear_fatent(mydata, start_cluster);
- if (ret) {
- printf("Error: clearing FAT entries\n");
- goto exit;
- }
+int fat_mkdir(const char *new_dirname)
+{
+ dir_entry *retdent;
+ fsdata datablock = { .fatbuf = NULL, };
+ fsdata *mydata = &datablock;
+ fat_itr *itr = NULL;
+ char *dirname_copy, *parent, *dirname;
+ char l_dirname[VFAT_MAXLEN_BYTES];
+ int ret = -1;
+ loff_t actwrite;
+ unsigned int bytesperclust;
+ dir_entry *dotdent = NULL;
+
+ dirname_copy = strdup(new_dirname);
+ if (!dirname_copy)
+ goto exit;
- if (!size)
- set_start_cluster(mydata, retdent, 0);
- } else if (size) {
- ret = start_cluster = find_empty_cluster(mydata);
- if (ret < 0) {
- printf("Error: finding empty cluster\n");
- goto exit;
- }
+ split_filename(dirname_copy, &parent, &dirname);
+ if (!strlen(dirname)) {
+ ret = -EINVAL;
+ goto exit;
+ }
- ret = check_overflow(mydata, start_cluster, size);
- if (ret) {
- printf("Error: %llu overflow\n", size);
- goto exit;
- }
+ if (normalize_longname(l_dirname, dirname)) {
+ printf("FAT: illegal filename (%s)\n", dirname);
+ ret = -EINVAL;
+ goto exit;
+ }
- set_start_cluster(mydata, retdent, start_cluster);
- }
- } else {
- /* Set short name to set alias checksum field in dir_slot */
- set_name(empty_dentptr, filename);
- fill_dir_slot(mydata, &empty_dentptr, filename);
+ itr = malloc_cache_aligned(sizeof(fat_itr));
+ if (!itr) {
+ ret = -ENOMEM;
+ goto exit;
+ }
- if (size) {
- ret = start_cluster = find_empty_cluster(mydata);
- if (ret < 0) {
- printf("Error: finding empty cluster\n");
- goto exit;
- }
+ ret = fat_itr_root(itr, &datablock);
+ if (ret)
+ goto exit;
+
+ total_sector = datablock.total_sect;
+
+ ret = fat_itr_resolve(itr, parent, TYPE_DIR);
+ if (ret) {
+ printf("%s: doesn't exist (%d)\n", parent, ret);
+ goto exit;
+ }
+
+ retdent = find_directory_entry(itr, l_dirname);
- ret = check_overflow(mydata, start_cluster, size);
- if (ret) {
- printf("Error: %llu overflow\n", size);
+ if (retdent) {
+ printf("%s: already exists\n", l_dirname);
+ ret = -EEXIST;
+ goto exit;
+ } else {
+ if (itr->is_root) {
+ /* root dir cannot have "." or ".." */
+ if (!strcmp(l_dirname, ".") ||
+ !strcmp(l_dirname, "..")) {
+ ret = -EINVAL;
goto exit;
}
- } else {
- start_cluster = 0;
}
- /* Set attribute as archieve for regular file */
- fill_dentry(mydata, empty_dentptr, filename,
- start_cluster, size, 0x20);
+ if (!itr->dent) {
+ printf("Error: allocating new dir entry\n");
+ ret = -EIO;
+ goto exit;
+ }
+
+ memset(itr->dent, 0, sizeof(*itr->dent));
+
+ /* Set short name to set alias checksum field in dir_slot */
+ set_name(itr->dent, dirname);
+ fill_dir_slot(itr, dirname);
+
+ /* Set attribute as archive for regular file */
+ fill_dentry(itr->fsdata, itr->dent, dirname, 0, 0,
+ ATTR_DIR | ATTR_ARCH);
- retdent = empty_dentptr;
+ retdent = itr->dent;
}
- ret = set_contents(mydata, retdent, buffer, size, actwrite);
+ /* Default entries */
+ bytesperclust = mydata->clust_size * mydata->sect_size;
+ dotdent = malloc_cache_aligned(bytesperclust);
+ if (!dotdent) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+ memset(dotdent, 0, bytesperclust);
+
+ memcpy(dotdent[0].name, ". ", 8);
+ memcpy(dotdent[0].ext, " ", 3);
+ dotdent[0].attr = ATTR_DIR | ATTR_ARCH;
+
+ memcpy(dotdent[1].name, ".. ", 8);
+ memcpy(dotdent[1].ext, " ", 3);
+ dotdent[1].attr = ATTR_DIR | ATTR_ARCH;
+ set_start_cluster(mydata, &dotdent[1], itr->start_clust);
+
+ ret = set_contents(mydata, retdent, 0, (__u8 *)dotdent,
+ bytesperclust, &actwrite);
+ if (ret < 0) {
+ printf("Error: writing contents\n");
+ goto exit;
+ }
+ /* Write twice for "." */
+ set_start_cluster(mydata, &dotdent[0], START(retdent));
+ ret = set_contents(mydata, retdent, 0, (__u8 *)dotdent,
+ bytesperclust, &actwrite);
if (ret < 0) {
printf("Error: writing contents\n");
goto exit;
}
- debug("attempt to write 0x%llx bytes\n", *actwrite);
/* Flush fat buffer */
ret = flush_dirty_fat_buffer(mydata);
}
/* Write directory table to device */
- ret = set_cluster(mydata, dir_curclust, get_dentfromdir_block,
- mydata->clust_size * mydata->sect_size);
+ ret = set_cluster(mydata, itr->clust, itr->block,
+ mydata->clust_size * mydata->sect_size);
if (ret)
printf("Error: writing directory entry\n");
exit:
+ free(dirname_copy);
free(mydata->fatbuf);
+ free(itr);
+ free(dotdent);
return ret;
}
-
-int file_fat_write(const char *filename, void *buffer, loff_t offset,
- loff_t maxsize, loff_t *actwrite)
-{
- if (offset != 0) {
- printf("Error: non zero offset is currently not supported.\n");
- return -1;
- }
-
- printf("writing %s\n", filename);
- return do_fat_write(filename, buffer, maxsize, actwrite);
-}
return -EACCES;
}
+static inline int fs_unlink_unsupported(const char *filename)
+{
+ return -1;
+}
+
+static inline int fs_mkdir_unsupported(const char *dirname)
+{
+ return -1;
+}
+
struct fstype_info {
int fstype;
char *name;
int (*readdir)(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
/* see fs_closedir() */
void (*closedir)(struct fs_dir_stream *dirs);
+ int (*unlink)(const char *filename);
+ int (*mkdir)(const char *dirname);
};
static struct fstype_info fstypes[] = {
.read = fat_read_file,
#ifdef CONFIG_FAT_WRITE
.write = file_fat_write,
+ .unlink = fat_unlink,
+ .mkdir = fat_mkdir,
#else
.write = fs_write_unsupported,
+ .unlink = fs_unlink_unsupported,
+ .mkdir = fs_mkdir_unsupported,
#endif
.uuid = fs_uuid_unsupported,
.opendir = fat_opendir,
#endif
.uuid = ext4fs_uuid,
.opendir = fs_opendir_unsupported,
+ .unlink = fs_unlink_unsupported,
+ .mkdir = fs_mkdir_unsupported,
},
#endif
#ifdef CONFIG_SANDBOX
.write = fs_write_sandbox,
.uuid = fs_uuid_unsupported,
.opendir = fs_opendir_unsupported,
+ .unlink = fs_unlink_unsupported,
+ .mkdir = fs_mkdir_unsupported,
},
#endif
#ifdef CONFIG_CMD_UBIFS
.write = fs_write_unsupported,
.uuid = fs_uuid_unsupported,
.opendir = fs_opendir_unsupported,
+ .unlink = fs_unlink_unsupported,
+ .mkdir = fs_mkdir_unsupported,
},
#endif
#ifdef CONFIG_FS_BTRFS
.write = fs_write_unsupported,
.uuid = btrfs_uuid,
.opendir = fs_opendir_unsupported,
+ .unlink = fs_unlink_unsupported,
+ .mkdir = fs_mkdir_unsupported,
},
#endif
{
.write = fs_write_unsupported,
.uuid = fs_uuid_unsupported,
.opendir = fs_opendir_unsupported,
+ .unlink = fs_unlink_unsupported,
+ .mkdir = fs_mkdir_unsupported,
},
};
fs_close();
}
+int fs_unlink(const char *filename)
+{
+ int ret;
+
+ struct fstype_info *info = fs_get_info(fs_type);
+
+ ret = info->unlink(filename);
+
+ fs_type = FS_TYPE_ANY;
+ fs_close();
+
+ return ret;
+}
+
+int fs_mkdir(const char *dirname)
+{
+ int ret;
+
+ struct fstype_info *info = fs_get_info(fs_type);
+
+ ret = info->mkdir(dirname);
+
+ fs_type = FS_TYPE_ANY;
+ fs_close();
+
+ return ret;
+}
int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype)
return CMD_RET_SUCCESS;
}
+int do_rm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype)
+{
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ if (fs_set_blk_dev(argv[1], argv[2], fstype))
+ return 1;
+
+ if (fs_unlink(argv[3]))
+ return 1;
+
+ return 0;
+}
+
+int do_mkdir(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype)
+{
+ int ret;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ if (fs_set_blk_dev(argv[1], argv[2], fstype))
+ return 1;
+
+ ret = fs_mkdir(argv[3]);
+ if (ret) {
+ printf("** Unable to create a directory \"%s\" **\n", argv[3]);
+ return 1;
+ }
+
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _ASM_GENERIC_ATOMIC_H
+#define _ASM_GENERIC_ATOMIC_H
+
+typedef struct { volatile int counter; } atomic_t;
+#if BITS_PER_LONG == 32
+typedef struct { volatile long long counter; } atomic64_t;
+#else /* BIT_PER_LONG == 32 */
+typedef struct { volatile long counter; } atomic64_t;
+#endif
+
+#define ATOMIC_INIT(i) { (i) }
+
+#define atomic_read(v) ((v)->counter)
+#define atomic_set(v, i) ((v)->counter = (i))
+#define atomic64_read(v) atomic_read(v)
+#define atomic64_set(v, i) atomic_set(v, i)
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_inc(atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ ++v->counter;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_dec(atomic_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ --v->counter;
+ local_irq_restore(flags);
+}
+
+static inline int atomic_dec_and_test(volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+ int val;
+
+ local_irq_save(flags);
+ val = v->counter;
+ v->counter = val -= 1;
+ local_irq_restore(flags);
+
+ return val == 0;
+}
+
+static inline int atomic_add_negative(int i, volatile atomic_t *v)
+{
+ unsigned long flags = 0;
+ int val;
+
+ local_irq_save(flags);
+ val = v->counter;
+ v->counter = val += i;
+ local_irq_restore(flags);
+
+ return val < 0;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ *addr &= ~mask;
+ local_irq_restore(flags);
+}
+
+#if BITS_PER_LONG == 32
+
+static inline void atomic64_add(long long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+
+#else /* BIT_PER_LONG == 32 */
+
+static inline void atomic64_add(long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long i, volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+#endif
+
+static inline void atomic64_inc(volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter += 1;
+ local_irq_restore(flags);
+}
+
+static inline void atomic64_dec(volatile atomic64_t *v)
+{
+ unsigned long flags = 0;
+
+ local_irq_save(flags);
+ v->counter -= 1;
+ local_irq_restore(flags);
+}
+
+#endif
*/
int blk_get_from_parent(struct udevice *parent, struct udevice **devp);
+/**
+ * blk_get_by_device() - Get the block device descriptor for the given device
+ * @dev: Instance of a storage device
+ *
+ * Return: With block device descriptor on success , NULL if there is no such
+ * block device.
+ */
+struct blk_desc *blk_get_by_device(struct udevice *dev);
+
#else
#include <errno.h>
/*
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+/*
+ * This uclass encapsulates hardware methods to gather information about a
+ * board or a specific device such as hard-wired GPIOs on GPIO expanders,
+ * read-only data in flash ICs, or similar.
+ *
+ * The interface offers functions to read the usual standard data types (bool,
+ * int, string) from the device, each of which is identified by a static
+ * numeric ID (which will usually be defined as a enum in a header file).
+ *
+ * If for example the board had a read-only serial number flash IC, we could
+ * call
+ *
+ * ret = board_detect(dev);
+ * if (ret) {
+ * debug("board device not found.");
+ * return ret;
+ * }
+ *
+ * ret = board_get_int(dev, ID_SERIAL_NUMBER, &serial);
+ * if (ret) {
+ * debug("Error when reading serial number from device.");
+ * return ret;
+ * }
+ *
+ * to read the serial number.
+ */
+
+struct board_ops {
+ /**
+ * detect() - Run the hardware info detection procedure for this
+ * device.
+ * @dev: The device containing the information
+ *
+ * This operation might take a long time (e.g. read from EEPROM,
+ * check the presence of a device on a bus etc.), hence this is not
+ * done in the probe() method, but later during operation in this
+ * dedicated method.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+ int (*detect)(struct udevice *dev);
+
+ /**
+ * get_bool() - Read a specific bool data value that describes the
+ * hardware setup.
+ * @dev: The board instance to gather the data.
+ * @id: A unique identifier for the bool value to be read.
+ * @val: Pointer to a buffer that receives the value read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+ int (*get_bool)(struct udevice *dev, int id, bool *val);
+
+ /**
+ * get_int() - Read a specific int data value that describes the
+ * hardware setup.
+ * @dev: The board instance to gather the data.
+ * @id: A unique identifier for the int value to be read.
+ * @val: Pointer to a buffer that receives the value read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+ int (*get_int)(struct udevice *dev, int id, int *val);
+
+ /**
+ * get_str() - Read a specific string data value that describes the
+ * hardware setup.
+ * @dev: The board instance to gather the data.
+ * @id: A unique identifier for the string value to be read.
+ * @size: The size of the buffer to receive the string data.
+ * @val: Pointer to a buffer that receives the value read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+ int (*get_str)(struct udevice *dev, int id, size_t size, char *val);
+};
+
+#define board_get_ops(dev) ((struct board_ops *)(dev)->driver->ops)
+
+/**
+ * board_detect() - Run the hardware info detection procedure for this device.
+ *
+ * @dev: The device containing the information
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_detect(struct udevice *dev);
+
+/**
+ * board_get_bool() - Read a specific bool data value that describes the
+ * hardware setup.
+ * @dev: The board instance to gather the data.
+ * @id: A unique identifier for the bool value to be read.
+ * @val: Pointer to a buffer that receives the value read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_get_bool(struct udevice *dev, int id, bool *val);
+
+/**
+ * board_get_int() - Read a specific int data value that describes the
+ * hardware setup.
+ * @dev: The board instance to gather the data.
+ * @id: A unique identifier for the int value to be read.
+ * @val: Pointer to a buffer that receives the value read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_get_int(struct udevice *dev, int id, int *val);
+
+/**
+ * board_get_str() - Read a specific string data value that describes the
+ * hardware setup.
+ * @dev: The board instance to gather the data.
+ * @id: A unique identifier for the string value to be read.
+ * @size: The size of the buffer to receive the string data.
+ * @val: Pointer to a buffer that receives the value read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_get_str(struct udevice *dev, int id, size_t size, char *val);
+
+/**
+ * board_get() - Return the board device for the board in question.
+ * @devp: Pointer to structure to receive the board device.
+ *
+ * Since there can only be at most one board instance, the API can supply a
+ * function that returns the unique device. This is especially useful for use
+ * in board files.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_get(struct udevice **devp);
--- /dev/null
+/* SPDX-License-Identifier: Unicode-DFS-2016 */
+/*
+ * Capitalization tables
+ */
+
+struct capitalization_table {
+ u16 upper;
+ u16 lower;
+};
+
+/*
+ * Correspondence table for small and capital Unicode letters in the range of
+ * 0x0000 - 0xffff based on http://www.unicode.org/Public/UCA/11.0.0/allkeys.txt
+ */
+#define UNICODE_CAPITALIZATION_TABLE { \
+ { 0x0531, /* ARMENIAN CAPITAL LETTER AYB */ \
+ 0x0561, /* ARMENIAN SMALL LETTER AYB */ }, \
+ { 0x0532, /* ARMENIAN CAPITAL LETTER BEN */ \
+ 0x0562, /* ARMENIAN SMALL LETTER BEN */ }, \
+ { 0x053E, /* ARMENIAN CAPITAL LETTER CA */ \
+ 0x056E, /* ARMENIAN SMALL LETTER CA */ }, \
+ { 0x0549, /* ARMENIAN CAPITAL LETTER CHA */ \
+ 0x0579, /* ARMENIAN SMALL LETTER CHA */ }, \
+ { 0x0543, /* ARMENIAN CAPITAL LETTER CHEH */ \
+ 0x0573, /* ARMENIAN SMALL LETTER CHEH */ }, \
+ { 0x0551, /* ARMENIAN CAPITAL LETTER CO */ \
+ 0x0581, /* ARMENIAN SMALL LETTER CO */ }, \
+ { 0x0534, /* ARMENIAN CAPITAL LETTER DA */ \
+ 0x0564, /* ARMENIAN SMALL LETTER DA */ }, \
+ { 0x0535, /* ARMENIAN CAPITAL LETTER ECH */ \
+ 0x0565, /* ARMENIAN SMALL LETTER ECH */ }, \
+ { 0x0537, /* ARMENIAN CAPITAL LETTER EH */ \
+ 0x0567, /* ARMENIAN SMALL LETTER EH */ }, \
+ { 0x0538, /* ARMENIAN CAPITAL LETTER ET */ \
+ 0x0568, /* ARMENIAN SMALL LETTER ET */ }, \
+ { 0x0556, /* ARMENIAN CAPITAL LETTER FEH */ \
+ 0x0586, /* ARMENIAN SMALL LETTER FEH */ }, \
+ { 0x0542, /* ARMENIAN CAPITAL LETTER GHAD */ \
+ 0x0572, /* ARMENIAN SMALL LETTER GHAD */ }, \
+ { 0x0533, /* ARMENIAN CAPITAL LETTER GIM */ \
+ 0x0563, /* ARMENIAN SMALL LETTER GIM */ }, \
+ { 0x0540, /* ARMENIAN CAPITAL LETTER HO */ \
+ 0x0570, /* ARMENIAN SMALL LETTER HO */ }, \
+ { 0x053B, /* ARMENIAN CAPITAL LETTER INI */ \
+ 0x056B, /* ARMENIAN SMALL LETTER INI */ }, \
+ { 0x0541, /* ARMENIAN CAPITAL LETTER JA */ \
+ 0x0571, /* ARMENIAN SMALL LETTER JA */ }, \
+ { 0x054B, /* ARMENIAN CAPITAL LETTER JHEH */ \
+ 0x057B, /* ARMENIAN SMALL LETTER JHEH */ }, \
+ { 0x0554, /* ARMENIAN CAPITAL LETTER KEH */ \
+ 0x0584, /* ARMENIAN SMALL LETTER KEH */ }, \
+ { 0x053F, /* ARMENIAN CAPITAL LETTER KEN */ \
+ 0x056F, /* ARMENIAN SMALL LETTER KEN */ }, \
+ { 0x053C, /* ARMENIAN CAPITAL LETTER LIWN */ \
+ 0x056C, /* ARMENIAN SMALL LETTER LIWN */ }, \
+ { 0x0544, /* ARMENIAN CAPITAL LETTER MEN */ \
+ 0x0574, /* ARMENIAN SMALL LETTER MEN */ }, \
+ { 0x0546, /* ARMENIAN CAPITAL LETTER NOW */ \
+ 0x0576, /* ARMENIAN SMALL LETTER NOW */ }, \
+ { 0x0555, /* ARMENIAN CAPITAL LETTER OH */ \
+ 0x0585, /* ARMENIAN SMALL LETTER OH */ }, \
+ { 0x054A, /* ARMENIAN CAPITAL LETTER PEH */ \
+ 0x057A, /* ARMENIAN SMALL LETTER PEH */ }, \
+ { 0x0553, /* ARMENIAN CAPITAL LETTER PIWR */ \
+ 0x0583, /* ARMENIAN SMALL LETTER PIWR */ }, \
+ { 0x054C, /* ARMENIAN CAPITAL LETTER RA */ \
+ 0x057C, /* ARMENIAN SMALL LETTER RA */ }, \
+ { 0x0550, /* ARMENIAN CAPITAL LETTER REH */ \
+ 0x0580, /* ARMENIAN SMALL LETTER REH */ }, \
+ { 0x054D, /* ARMENIAN CAPITAL LETTER SEH */ \
+ 0x057D, /* ARMENIAN SMALL LETTER SEH */ }, \
+ { 0x0547, /* ARMENIAN CAPITAL LETTER SHA */ \
+ 0x0577, /* ARMENIAN SMALL LETTER SHA */ }, \
+ { 0x054F, /* ARMENIAN CAPITAL LETTER TIWN */ \
+ 0x057F, /* ARMENIAN SMALL LETTER TIWN */ }, \
+ { 0x0539, /* ARMENIAN CAPITAL LETTER TO */ \
+ 0x0569, /* ARMENIAN SMALL LETTER TO */ }, \
+ { 0x054E, /* ARMENIAN CAPITAL LETTER VEW */ \
+ 0x057E, /* ARMENIAN SMALL LETTER VEW */ }, \
+ { 0x0548, /* ARMENIAN CAPITAL LETTER VO */ \
+ 0x0578, /* ARMENIAN SMALL LETTER VO */ }, \
+ { 0x053D, /* ARMENIAN CAPITAL LETTER XEH */ \
+ 0x056D, /* ARMENIAN SMALL LETTER XEH */ }, \
+ { 0x0545, /* ARMENIAN CAPITAL LETTER YI */ \
+ 0x0575, /* ARMENIAN SMALL LETTER YI */ }, \
+ { 0x0552, /* ARMENIAN CAPITAL LETTER YIWN */ \
+ 0x0582, /* ARMENIAN SMALL LETTER YIWN */ }, \
+ { 0x0536, /* ARMENIAN CAPITAL LETTER ZA */ \
+ 0x0566, /* ARMENIAN SMALL LETTER ZA */ }, \
+ { 0x053A, /* ARMENIAN CAPITAL LETTER ZHE */ \
+ 0x056A, /* ARMENIAN SMALL LETTER ZHE */ }, \
+ { 0x24B6, /* CIRCLED LATIN CAPITAL LETTER A */ \
+ 0x24D0, /* CIRCLED LATIN SMALL LETTER A */ }, \
+ { 0x24B7, /* CIRCLED LATIN CAPITAL LETTER B */ \
+ 0x24D1, /* CIRCLED LATIN SMALL LETTER B */ }, \
+ { 0x24B8, /* CIRCLED LATIN CAPITAL LETTER C */ \
+ 0x24D2, /* CIRCLED LATIN SMALL LETTER C */ }, \
+ { 0x24B9, /* CIRCLED LATIN CAPITAL LETTER D */ \
+ 0x24D3, /* CIRCLED LATIN SMALL LETTER D */ }, \
+ { 0x24BA, /* CIRCLED LATIN CAPITAL LETTER E */ \
+ 0x24D4, /* CIRCLED LATIN SMALL LETTER E */ }, \
+ { 0x24BB, /* CIRCLED LATIN CAPITAL LETTER F */ \
+ 0x24D5, /* CIRCLED LATIN SMALL LETTER F */ }, \
+ { 0x24BC, /* CIRCLED LATIN CAPITAL LETTER G */ \
+ 0x24D6, /* CIRCLED LATIN SMALL LETTER G */ }, \
+ { 0x24BD, /* CIRCLED LATIN CAPITAL LETTER H */ \
+ 0x24D7, /* CIRCLED LATIN SMALL LETTER H */ }, \
+ { 0x24BE, /* CIRCLED LATIN CAPITAL LETTER I */ \
+ 0x24D8, /* CIRCLED LATIN SMALL LETTER I */ }, \
+ { 0x24BF, /* CIRCLED LATIN CAPITAL LETTER J */ \
+ 0x24D9, /* CIRCLED LATIN SMALL LETTER J */ }, \
+ { 0x24C0, /* CIRCLED LATIN CAPITAL LETTER K */ \
+ 0x24DA, /* CIRCLED LATIN SMALL LETTER K */ }, \
+ { 0x24C1, /* CIRCLED LATIN CAPITAL LETTER L */ \
+ 0x24DB, /* CIRCLED LATIN SMALL LETTER L */ }, \
+ { 0x24C2, /* CIRCLED LATIN CAPITAL LETTER M */ \
+ 0x24DC, /* CIRCLED LATIN SMALL LETTER M */ }, \
+ { 0x24C3, /* CIRCLED LATIN CAPITAL LETTER N */ \
+ 0x24DD, /* CIRCLED LATIN SMALL LETTER N */ }, \
+ { 0x24C4, /* CIRCLED LATIN CAPITAL LETTER O */ \
+ 0x24DE, /* CIRCLED LATIN SMALL LETTER O */ }, \
+ { 0x24C5, /* CIRCLED LATIN CAPITAL LETTER P */ \
+ 0x24DF, /* CIRCLED LATIN SMALL LETTER P */ }, \
+ { 0x24C6, /* CIRCLED LATIN CAPITAL LETTER Q */ \
+ 0x24E0, /* CIRCLED LATIN SMALL LETTER Q */ }, \
+ { 0x24C7, /* CIRCLED LATIN CAPITAL LETTER R */ \
+ 0x24E1, /* CIRCLED LATIN SMALL LETTER R */ }, \
+ { 0x24C8, /* CIRCLED LATIN CAPITAL LETTER S */ \
+ 0x24E2, /* CIRCLED LATIN SMALL LETTER S */ }, \
+ { 0x24C9, /* CIRCLED LATIN CAPITAL LETTER T */ \
+ 0x24E3, /* CIRCLED LATIN SMALL LETTER T */ }, \
+ { 0x24CA, /* CIRCLED LATIN CAPITAL LETTER U */ \
+ 0x24E4, /* CIRCLED LATIN SMALL LETTER U */ }, \
+ { 0x24CB, /* CIRCLED LATIN CAPITAL LETTER V */ \
+ 0x24E5, /* CIRCLED LATIN SMALL LETTER V */ }, \
+ { 0x24CC, /* CIRCLED LATIN CAPITAL LETTER W */ \
+ 0x24E6, /* CIRCLED LATIN SMALL LETTER W */ }, \
+ { 0x24CD, /* CIRCLED LATIN CAPITAL LETTER X */ \
+ 0x24E7, /* CIRCLED LATIN SMALL LETTER X */ }, \
+ { 0x24CE, /* CIRCLED LATIN CAPITAL LETTER Y */ \
+ 0x24E8, /* CIRCLED LATIN SMALL LETTER Y */ }, \
+ { 0x24CF, /* CIRCLED LATIN CAPITAL LETTER Z */ \
+ 0x24E9, /* CIRCLED LATIN SMALL LETTER Z */ }, \
+ { 0x2CC8, /* COPTIC CAPITAL LETTER AKHMIMIC KHEI */ \
+ 0x2CC9, /* COPTIC SMALL LETTER AKHMIMIC KHEI */ }, \
+ { 0x2C80, /* COPTIC CAPITAL LETTER ALFA */ \
+ 0x2C81, /* COPTIC SMALL LETTER ALFA */ }, \
+ { 0x2CF2, /* COPTIC CAPITAL LETTER BOHAIRIC KHEI */ \
+ 0x2CF3, /* COPTIC SMALL LETTER BOHAIRIC KHEI */ }, \
+ { 0x2CC2, /* COPTIC CAPITAL LETTER CROSSED SHEI */ \
+ 0x2CC3, /* COPTIC SMALL LETTER CROSSED SHEI */ }, \
+ { 0x2CB6, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC EIE */ \
+ 0x2CB7, /* COPTIC SMALL LETTER CRYPTOGRAMMIC EIE */ }, \
+ { 0x2CED, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC GANGIA */ \
+ 0x2CEE, /* COPTIC SMALL LETTER CRYPTOGRAMMIC GANGIA */ }, \
+ { 0x2CBC, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC NI */ \
+ 0x2CBD, /* COPTIC SMALL LETTER CRYPTOGRAMMIC NI */ }, \
+ { 0x2CEB, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC SHEI */ \
+ 0x2CEC, /* COPTIC SMALL LETTER CRYPTOGRAMMIC SHEI */ }, \
+ { 0x2C86, /* COPTIC CAPITAL LETTER DALDA */ \
+ 0x2C87, /* COPTIC SMALL LETTER DALDA */ }, \
+ { 0x03EE, /* COPTIC CAPITAL LETTER DEI */ \
+ 0x03EF, /* COPTIC SMALL LETTER DEI */ }, \
+ { 0x2CB2, /* COPTIC CAPITAL LETTER DIALECT-P ALEF */ \
+ 0x2CB3, /* COPTIC SMALL LETTER DIALECT-P ALEF */ }, \
+ { 0x2CCA, /* COPTIC CAPITAL LETTER DIALECT-P HORI */ \
+ 0x2CCB, /* COPTIC SMALL LETTER DIALECT-P HORI */ }, \
+ { 0x2CB8, /* COPTIC CAPITAL LETTER DIALECT-P KAPA */ \
+ 0x2CB9, /* COPTIC SMALL LETTER DIALECT-P KAPA */ }, \
+ { 0x2CBA, /* COPTIC CAPITAL LETTER DIALECT-P NI */ \
+ 0x2CBB, /* COPTIC SMALL LETTER DIALECT-P NI */ }, \
+ { 0x2C88, /* COPTIC CAPITAL LETTER EIE */ \
+ 0x2C89, /* COPTIC SMALL LETTER EIE */ }, \
+ { 0x03E4, /* COPTIC CAPITAL LETTER FEI */ \
+ 0x03E5, /* COPTIC SMALL LETTER FEI */ }, \
+ { 0x2CAA, /* COPTIC CAPITAL LETTER FI */ \
+ 0x2CAB, /* COPTIC SMALL LETTER FI */ }, \
+ { 0x2C84, /* COPTIC CAPITAL LETTER GAMMA */ \
+ 0x2C85, /* COPTIC SMALL LETTER GAMMA */ }, \
+ { 0x03EA, /* COPTIC CAPITAL LETTER GANGIA */ \
+ 0x03EB, /* COPTIC SMALL LETTER GANGIA */ }, \
+ { 0x2C8E, /* COPTIC CAPITAL LETTER HATE */ \
+ 0x2C8F, /* COPTIC SMALL LETTER HATE */ }, \
+ { 0x03E8, /* COPTIC CAPITAL LETTER HORI */ \
+ 0x03E9, /* COPTIC SMALL LETTER HORI */ }, \
+ { 0x2C92, /* COPTIC CAPITAL LETTER IAUDA */ \
+ 0x2C93, /* COPTIC SMALL LETTER IAUDA */ }, \
+ { 0x2C94, /* COPTIC CAPITAL LETTER KAPA */ \
+ 0x2C95, /* COPTIC SMALL LETTER KAPA */ }, \
+ { 0x03E6, /* COPTIC CAPITAL LETTER KHEI */ \
+ 0x03E7, /* COPTIC SMALL LETTER KHEI */ }, \
+ { 0x2CAC, /* COPTIC CAPITAL LETTER KHI */ \
+ 0x2CAD, /* COPTIC SMALL LETTER KHI */ }, \
+ { 0x2C9C, /* COPTIC CAPITAL LETTER KSI */ \
+ 0x2C9D, /* COPTIC SMALL LETTER KSI */ }, \
+ { 0x2C96, /* COPTIC CAPITAL LETTER LAULA */ \
+ 0x2C97, /* COPTIC SMALL LETTER LAULA */ }, \
+ { 0x2CD0, /* COPTIC CAPITAL LETTER L-SHAPED HA */ \
+ 0x2CD1, /* COPTIC SMALL LETTER L-SHAPED HA */ }, \
+ { 0x2C98, /* COPTIC CAPITAL LETTER MI */ \
+ 0x2C99, /* COPTIC SMALL LETTER MI */ }, \
+ { 0x2C9A, /* COPTIC CAPITAL LETTER NI */ \
+ 0x2C9B, /* COPTIC SMALL LETTER NI */ }, \
+ { 0x2C9E, /* COPTIC CAPITAL LETTER O */ \
+ 0x2C9F, /* COPTIC SMALL LETTER O */ }, \
+ { 0x2CB4, /* COPTIC CAPITAL LETTER OLD COPTIC AIN */ \
+ 0x2CB5, /* COPTIC SMALL LETTER OLD COPTIC AIN */ }, \
+ { 0x2CD8, /* COPTIC CAPITAL LETTER OLD COPTIC DJA */ \
+ 0x2CD9, /* COPTIC SMALL LETTER OLD COPTIC DJA */ }, \
+ { 0x2CC6, /* COPTIC CAPITAL LETTER OLD COPTIC ESH */ \
+ 0x2CC7, /* COPTIC SMALL LETTER OLD COPTIC ESH */ }, \
+ { 0x2CD6, /* COPTIC CAPITAL LETTER OLD COPTIC GANGIA */ \
+ 0x2CD7, /* COPTIC SMALL LETTER OLD COPTIC GANGIA */ }, \
+ { 0x2CCE, /* COPTIC CAPITAL LETTER OLD COPTIC HA */ \
+ 0x2CCF, /* COPTIC SMALL LETTER OLD COPTIC HA */ }, \
+ { 0x2CD4, /* COPTIC CAPITAL LETTER OLD COPTIC HAT */ \
+ 0x2CD5, /* COPTIC SMALL LETTER OLD COPTIC HAT */ }, \
+ { 0x2CD2, /* COPTIC CAPITAL LETTER OLD COPTIC HEI */ \
+ 0x2CD3, /* COPTIC SMALL LETTER OLD COPTIC HEI */ }, \
+ { 0x2CCC, /* COPTIC CAPITAL LETTER OLD COPTIC HORI */ \
+ 0x2CCD, /* COPTIC SMALL LETTER OLD COPTIC HORI */ }, \
+ { 0x2CBE, /* COPTIC CAPITAL LETTER OLD COPTIC OOU */ \
+ 0x2CBF, /* COPTIC SMALL LETTER OLD COPTIC OOU */ }, \
+ { 0x2CC4, /* COPTIC CAPITAL LETTER OLD COPTIC SHEI */ \
+ 0x2CC5, /* COPTIC SMALL LETTER OLD COPTIC SHEI */ }, \
+ { 0x2CDA, /* COPTIC CAPITAL LETTER OLD COPTIC SHIMA */ \
+ 0x2CDB, /* COPTIC SMALL LETTER OLD COPTIC SHIMA */ }, \
+ { 0x2CDE, /* COPTIC CAPITAL LETTER OLD NUBIAN NGI */ \
+ 0x2CDF, /* COPTIC SMALL LETTER OLD NUBIAN NGI */ }, \
+ { 0x2CE0, /* COPTIC CAPITAL LETTER OLD NUBIAN NYI */ \
+ 0x2CE1, /* COPTIC SMALL LETTER OLD NUBIAN NYI */ }, \
+ { 0x2CDC, /* COPTIC CAPITAL LETTER OLD NUBIAN SHIMA */ \
+ 0x2CDD, /* COPTIC SMALL LETTER OLD NUBIAN SHIMA */ }, \
+ { 0x2CE2, /* COPTIC CAPITAL LETTER OLD NUBIAN WAU */ \
+ 0x2CE3, /* COPTIC SMALL LETTER OLD NUBIAN WAU */ }, \
+ { 0x2CB0, /* COPTIC CAPITAL LETTER OOU */ \
+ 0x2CB1, /* COPTIC SMALL LETTER OOU */ }, \
+ { 0x2CA0, /* COPTIC CAPITAL LETTER PI */ \
+ 0x2CA1, /* COPTIC SMALL LETTER PI */ }, \
+ { 0x2CAE, /* COPTIC CAPITAL LETTER PSI */ \
+ 0x2CAF, /* COPTIC SMALL LETTER PSI */ }, \
+ { 0x2CA2, /* COPTIC CAPITAL LETTER RO */ \
+ 0x2CA3, /* COPTIC SMALL LETTER RO */ }, \
+ { 0x2CC0, /* COPTIC CAPITAL LETTER SAMPI */ \
+ 0x2CC1, /* COPTIC SMALL LETTER SAMPI */ }, \
+ { 0x03E2, /* COPTIC CAPITAL LETTER SHEI */ \
+ 0x03E3, /* COPTIC SMALL LETTER SHEI */ }, \
+ { 0x03EC, /* COPTIC CAPITAL LETTER SHIMA */ \
+ 0x03ED, /* COPTIC SMALL LETTER SHIMA */ }, \
+ { 0x2CA4, /* COPTIC CAPITAL LETTER SIMA */ \
+ 0x2CA5, /* COPTIC SMALL LETTER SIMA */ }, \
+ { 0x2C8A, /* COPTIC CAPITAL LETTER SOU */ \
+ 0x2C8B, /* COPTIC SMALL LETTER SOU */ }, \
+ { 0x2CA6, /* COPTIC CAPITAL LETTER TAU */ \
+ 0x2CA7, /* COPTIC SMALL LETTER TAU */ }, \
+ { 0x2C90, /* COPTIC CAPITAL LETTER THETHE */ \
+ 0x2C91, /* COPTIC SMALL LETTER THETHE */ }, \
+ { 0x2CA8, /* COPTIC CAPITAL LETTER UA */ \
+ 0x2CA9, /* COPTIC SMALL LETTER UA */ }, \
+ { 0x2C82, /* COPTIC CAPITAL LETTER VIDA */ \
+ 0x2C83, /* COPTIC SMALL LETTER VIDA */ }, \
+ { 0x2C8C, /* COPTIC CAPITAL LETTER ZATA */ \
+ 0x2C8D, /* COPTIC SMALL LETTER ZATA */ }, \
+ { 0x0410, /* CYRILLIC CAPITAL LETTER A */ \
+ 0x0430, /* CYRILLIC SMALL LETTER A */ }, \
+ { 0x04D0, /* CYRILLIC CAPITAL LETTER A WITH BREVE */ \
+ 0x04D1, /* CYRILLIC SMALL LETTER A WITH BREVE */ }, \
+ { 0x04D2, /* CYRILLIC CAPITAL LETTER A WITH DIAERESIS */ \
+ 0x04D3, /* CYRILLIC SMALL LETTER A WITH DIAERESIS */ }, \
+ { 0x04BC, /* CYRILLIC CAPITAL LETTER ABKHASIAN CHE */ \
+ 0x04BD, /* CYRILLIC SMALL LETTER ABKHASIAN CHE */ }, \
+ { 0x04BE, /* CYRILLIC CAPITAL LETTER ABKHASIAN CHE WITH DESCENDER */ \
+ 0x04BF, /* CYRILLIC SMALL LETTER ABKHASIAN CHE WITH DESCENDER */ }, \
+ { 0x04E0, /* CYRILLIC CAPITAL LETTER ABKHASIAN DZE */ \
+ 0x04E1, /* CYRILLIC SMALL LETTER ABKHASIAN DZE */ }, \
+ { 0x04A8, /* CYRILLIC CAPITAL LETTER ABKHASIAN HA */ \
+ 0x04A9, /* CYRILLIC SMALL LETTER ABKHASIAN HA */ }, \
+ { 0x051E, /* CYRILLIC CAPITAL LETTER ALEUT KA */ \
+ 0x051F, /* CYRILLIC SMALL LETTER ALEUT KA */ }, \
+ { 0x04E8, /* CYRILLIC CAPITAL LETTER BARRED O */ \
+ 0x04E9, /* CYRILLIC SMALL LETTER BARRED O */ }, \
+ { 0x04EA, /* CYRILLIC CAPITAL LETTER BARRED O WITH DIAERESIS */ \
+ 0x04EB, /* CYRILLIC SMALL LETTER BARRED O WITH DIAERESIS */ }, \
+ { 0x04A0, /* CYRILLIC CAPITAL LETTER BASHKIR KA */ \
+ 0x04A1, /* CYRILLIC SMALL LETTER BASHKIR KA */ }, \
+ { 0x0411, /* CYRILLIC CAPITAL LETTER BE */ \
+ 0x0431, /* CYRILLIC SMALL LETTER BE */ }, \
+ { 0x046A, /* CYRILLIC CAPITAL LETTER BIG YUS */ \
+ 0x046B, /* CYRILLIC SMALL LETTER BIG YUS */ }, \
+ { 0xA66A, /* CYRILLIC CAPITAL LETTER BINOCULAR O */ \
+ 0xA66B, /* CYRILLIC SMALL LETTER BINOCULAR O */ }, \
+ { 0xA65A, /* CYRILLIC CAPITAL LETTER BLENDED YUS */ \
+ 0xA65B, /* CYRILLIC SMALL LETTER BLENDED YUS */ }, \
+ { 0xA64C, /* CYRILLIC CAPITAL LETTER BROAD OMEGA */ \
+ 0xA64D, /* CYRILLIC SMALL LETTER BROAD OMEGA */ }, \
+ { 0x0406, /* CYRILLIC CAPITAL LETTER BYELORUSSIAN-UKRAINIAN I */ \
+ 0x0456, /* CYRILLIC SMALL LETTER BYELORUSSIAN-UKRAINIAN I */ }, \
+ { 0xA686, /* CYRILLIC CAPITAL LETTER CCHE */ \
+ 0xA687, /* CYRILLIC SMALL LETTER CCHE */ }, \
+ { 0x0427, /* CYRILLIC CAPITAL LETTER CHE */ \
+ 0x0447, /* CYRILLIC SMALL LETTER CHE */ }, \
+ { 0x04B6, /* CYRILLIC CAPITAL LETTER CHE WITH DESCENDER */ \
+ 0x04B7, /* CYRILLIC SMALL LETTER CHE WITH DESCENDER */ }, \
+ { 0x04F4, /* CYRILLIC CAPITAL LETTER CHE WITH DIAERESIS */ \
+ 0x04F5, /* CYRILLIC SMALL LETTER CHE WITH DIAERESIS */ }, \
+ { 0x04B8, /* CYRILLIC CAPITAL LETTER CHE WITH VERTICAL STROKE */ \
+ 0x04B9, /* CYRILLIC SMALL LETTER CHE WITH VERTICAL STROKE */ }, \
+ { 0xA658, /* CYRILLIC CAPITAL LETTER CLOSED LITTLE YUS */ \
+ 0xA659, /* CYRILLIC SMALL LETTER CLOSED LITTLE YUS */ }, \
+ { 0xA69A, /* CYRILLIC CAPITAL LETTER CROSSED O */ \
+ 0xA69B, /* CYRILLIC SMALL LETTER CROSSED O */ }, \
+ { 0x052C, /* CYRILLIC CAPITAL LETTER DCHE */ \
+ 0x052D, /* CYRILLIC SMALL LETTER DCHE */ }, \
+ { 0x0414, /* CYRILLIC CAPITAL LETTER DE */ \
+ 0x0434, /* CYRILLIC SMALL LETTER DE */ }, \
+ { 0x0402, /* CYRILLIC CAPITAL LETTER DJE */ \
+ 0x0452, /* CYRILLIC SMALL LETTER DJE */ }, \
+ { 0xA648, /* CYRILLIC CAPITAL LETTER DJERV */ \
+ 0xA649, /* CYRILLIC SMALL LETTER DJERV */ }, \
+ { 0xA66C, /* CYRILLIC CAPITAL LETTER DOUBLE MONOCULAR O */ \
+ 0xA66D, /* CYRILLIC SMALL LETTER DOUBLE MONOCULAR O */ }, \
+ { 0xA698, /* CYRILLIC CAPITAL LETTER DOUBLE O */ \
+ 0xA699, /* CYRILLIC SMALL LETTER DOUBLE O */ }, \
+ { 0xA680, /* CYRILLIC CAPITAL LETTER DWE */ \
+ 0xA681, /* CYRILLIC SMALL LETTER DWE */ }, \
+ { 0x0405, /* CYRILLIC CAPITAL LETTER DZE */ \
+ 0x0455, /* CYRILLIC SMALL LETTER DZE */ }, \
+ { 0xA642, /* CYRILLIC CAPITAL LETTER DZELO */ \
+ 0xA643, /* CYRILLIC SMALL LETTER DZELO */ }, \
+ { 0x040F, /* CYRILLIC CAPITAL LETTER DZHE */ \
+ 0x045F, /* CYRILLIC SMALL LETTER DZHE */ }, \
+ { 0xA682, /* CYRILLIC CAPITAL LETTER DZWE */ \
+ 0xA683, /* CYRILLIC SMALL LETTER DZWE */ }, \
+ { 0xA688, /* CYRILLIC CAPITAL LETTER DZZE */ \
+ 0xA689, /* CYRILLIC SMALL LETTER DZZE */ }, \
+ { 0x052A, /* CYRILLIC CAPITAL LETTER DZZHE */ \
+ 0x052B, /* CYRILLIC SMALL LETTER DZZHE */ }, \
+ { 0x042D, /* CYRILLIC CAPITAL LETTER E */ \
+ 0x044D, /* CYRILLIC SMALL LETTER E */ }, \
+ { 0x04EC, /* CYRILLIC CAPITAL LETTER E WITH DIAERESIS */ \
+ 0x04ED, /* CYRILLIC SMALL LETTER E WITH DIAERESIS */ }, \
+ { 0x0424, /* CYRILLIC CAPITAL LETTER EF */ \
+ 0x0444, /* CYRILLIC SMALL LETTER EF */ }, \
+ { 0x041B, /* CYRILLIC CAPITAL LETTER EL */ \
+ 0x043B, /* CYRILLIC SMALL LETTER EL */ }, \
+ { 0x052E, /* CYRILLIC CAPITAL LETTER EL WITH DESCENDER */ \
+ 0x052F, /* CYRILLIC SMALL LETTER EL WITH DESCENDER */ }, \
+ { 0x0512, /* CYRILLIC CAPITAL LETTER EL WITH HOOK */ \
+ 0x0513, /* CYRILLIC SMALL LETTER EL WITH HOOK */ }, \
+ { 0x0520, /* CYRILLIC CAPITAL LETTER EL WITH MIDDLE HOOK */ \
+ 0x0521, /* CYRILLIC SMALL LETTER EL WITH MIDDLE HOOK */ }, \
+ { 0x04C5, /* CYRILLIC CAPITAL LETTER EL WITH TAIL */ \
+ 0x04C6, /* CYRILLIC SMALL LETTER EL WITH TAIL */ }, \
+ { 0x041C, /* CYRILLIC CAPITAL LETTER EM */ \
+ 0x043C, /* CYRILLIC SMALL LETTER EM */ }, \
+ { 0x04CD, /* CYRILLIC CAPITAL LETTER EM WITH TAIL */ \
+ 0x04CE, /* CYRILLIC SMALL LETTER EM WITH TAIL */ }, \
+ { 0x041D, /* CYRILLIC CAPITAL LETTER EN */ \
+ 0x043D, /* CYRILLIC SMALL LETTER EN */ }, \
+ { 0x04A2, /* CYRILLIC CAPITAL LETTER EN WITH DESCENDER */ \
+ 0x04A3, /* CYRILLIC SMALL LETTER EN WITH DESCENDER */ }, \
+ { 0x04C7, /* CYRILLIC CAPITAL LETTER EN WITH HOOK */ \
+ 0x04C8, /* CYRILLIC SMALL LETTER EN WITH HOOK */ }, \
+ { 0x0528, /* CYRILLIC CAPITAL LETTER EN WITH LEFT HOOK */ \
+ 0x0529, /* CYRILLIC SMALL LETTER EN WITH LEFT HOOK */ }, \
+ { 0x0522, /* CYRILLIC CAPITAL LETTER EN WITH MIDDLE HOOK */ \
+ 0x0523, /* CYRILLIC SMALL LETTER EN WITH MIDDLE HOOK */ }, \
+ { 0x04C9, /* CYRILLIC CAPITAL LETTER EN WITH TAIL */ \
+ 0x04CA, /* CYRILLIC SMALL LETTER EN WITH TAIL */ }, \
+ { 0x0420, /* CYRILLIC CAPITAL LETTER ER */ \
+ 0x0440, /* CYRILLIC SMALL LETTER ER */ }, \
+ { 0x048E, /* CYRILLIC CAPITAL LETTER ER WITH TICK */ \
+ 0x048F, /* CYRILLIC SMALL LETTER ER WITH TICK */ }, \
+ { 0x0421, /* CYRILLIC CAPITAL LETTER ES */ \
+ 0x0441, /* CYRILLIC SMALL LETTER ES */ }, \
+ { 0x04AA, /* CYRILLIC CAPITAL LETTER ES WITH DESCENDER */ \
+ 0x04AB, /* CYRILLIC SMALL LETTER ES WITH DESCENDER */ }, \
+ { 0x0472, /* CYRILLIC CAPITAL LETTER FITA */ \
+ 0x0473, /* CYRILLIC SMALL LETTER FITA */ }, \
+ { 0x0413, /* CYRILLIC CAPITAL LETTER GHE */ \
+ 0x0433, /* CYRILLIC SMALL LETTER GHE */ }, \
+ { 0x04F6, /* CYRILLIC CAPITAL LETTER GHE WITH DESCENDER */ \
+ 0x04F7, /* CYRILLIC SMALL LETTER GHE WITH DESCENDER */ }, \
+ { 0x0494, /* CYRILLIC CAPITAL LETTER GHE WITH MIDDLE HOOK */ \
+ 0x0495, /* CYRILLIC SMALL LETTER GHE WITH MIDDLE HOOK */ }, \
+ { 0x0492, /* CYRILLIC CAPITAL LETTER GHE WITH STROKE */ \
+ 0x0493, /* CYRILLIC SMALL LETTER GHE WITH STROKE */ }, \
+ { 0x04FA, /* CYRILLIC CAPITAL LETTER GHE WITH STROKE AND HOOK */ \
+ 0x04FB, /* CYRILLIC SMALL LETTER GHE WITH STROKE AND HOOK */ }, \
+ { 0x0490, /* CYRILLIC CAPITAL LETTER GHE WITH UPTURN */ \
+ 0x0491, /* CYRILLIC SMALL LETTER GHE WITH UPTURN */ }, \
+ { 0x0403, /* CYRILLIC CAPITAL LETTER GJE */ \
+ 0x0453, /* CYRILLIC SMALL LETTER GJE */ }, \
+ { 0x0425, /* CYRILLIC CAPITAL LETTER HA */ \
+ 0x0445, /* CYRILLIC SMALL LETTER HA */ }, \
+ { 0x04B2, /* CYRILLIC CAPITAL LETTER HA WITH DESCENDER */ \
+ 0x04B3, /* CYRILLIC SMALL LETTER HA WITH DESCENDER */ }, \
+ { 0x04FC, /* CYRILLIC CAPITAL LETTER HA WITH HOOK */ \
+ 0x04FD, /* CYRILLIC SMALL LETTER HA WITH HOOK */ }, \
+ { 0x04FE, /* CYRILLIC CAPITAL LETTER HA WITH STROKE */ \
+ 0x04FF, /* CYRILLIC SMALL LETTER HA WITH STROKE */ }, \
+ { 0x042A, /* CYRILLIC CAPITAL LETTER HARD SIGN */ \
+ 0x044A, /* CYRILLIC SMALL LETTER HARD SIGN */ }, \
+ { 0xA694, /* CYRILLIC CAPITAL LETTER HWE */ \
+ 0xA695, /* CYRILLIC SMALL LETTER HWE */ }, \
+ { 0x0418, /* CYRILLIC CAPITAL LETTER I */ \
+ 0x0438, /* CYRILLIC SMALL LETTER I */ }, \
+ { 0x04E4, /* CYRILLIC CAPITAL LETTER I WITH DIAERESIS */ \
+ 0x04E5, /* CYRILLIC SMALL LETTER I WITH DIAERESIS */ }, \
+ { 0x040D, /* CYRILLIC CAPITAL LETTER I WITH GRAVE */ \
+ 0x045D, /* CYRILLIC SMALL LETTER I WITH GRAVE */ }, \
+ { 0x04E2, /* CYRILLIC CAPITAL LETTER I WITH MACRON */ \
+ 0x04E3, /* CYRILLIC SMALL LETTER I WITH MACRON */ }, \
+ { 0x0415, /* CYRILLIC CAPITAL LETTER IE */ \
+ 0x0435, /* CYRILLIC SMALL LETTER IE */ }, \
+ { 0x04D6, /* CYRILLIC CAPITAL LETTER IE WITH BREVE */ \
+ 0x04D7, /* CYRILLIC SMALL LETTER IE WITH BREVE */ }, \
+ { 0x0400, /* CYRILLIC CAPITAL LETTER IE WITH GRAVE */ \
+ 0x0450, /* CYRILLIC SMALL LETTER IE WITH GRAVE */ }, \
+ { 0x0401, /* CYRILLIC CAPITAL LETTER IO */ \
+ 0x0451, /* CYRILLIC SMALL LETTER IO */ }, \
+ { 0xA646, /* CYRILLIC CAPITAL LETTER IOTA */ \
+ 0xA647, /* CYRILLIC SMALL LETTER IOTA */ }, \
+ { 0xA656, /* CYRILLIC CAPITAL LETTER IOTIFIED A */ \
+ 0xA657, /* CYRILLIC SMALL LETTER IOTIFIED A */ }, \
+ { 0x046C, /* CYRILLIC CAPITAL LETTER IOTIFIED BIG YUS */ \
+ 0x046D, /* CYRILLIC SMALL LETTER IOTIFIED BIG YUS */ }, \
+ { 0xA65C, /* CYRILLIC CAPITAL LETTER IOTIFIED CLOSED LITTLE YUS */ \
+ 0xA65D, /* CYRILLIC SMALL LETTER IOTIFIED CLOSED LITTLE YUS */ }, \
+ { 0x0464, /* CYRILLIC CAPITAL LETTER IOTIFIED E */ \
+ 0x0465, /* CYRILLIC SMALL LETTER IOTIFIED E */ }, \
+ { 0x0468, /* CYRILLIC CAPITAL LETTER IOTIFIED LITTLE YUS */ \
+ 0x0469, /* CYRILLIC SMALL LETTER IOTIFIED LITTLE YUS */ }, \
+ { 0xA652, /* CYRILLIC CAPITAL LETTER IOTIFIED YAT */ \
+ 0xA653, /* CYRILLIC SMALL LETTER IOTIFIED YAT */ }, \
+ { 0x0474, /* CYRILLIC CAPITAL LETTER IZHITSA */ \
+ 0x0475, /* CYRILLIC SMALL LETTER IZHITSA */ }, \
+ { 0x0476, /* CYRILLIC CAPITAL LETTER IZHITSA WITH DOUBLE GRAVE ACCENT */ \
+ 0x0477, /* CYRILLIC SMALL LETTER IZHITSA WITH DOUBLE GRAVE ACCENT */ }, \
+ { 0x0408, /* CYRILLIC CAPITAL LETTER JE */ \
+ 0x0458, /* CYRILLIC SMALL LETTER JE */ }, \
+ { 0x041A, /* CYRILLIC CAPITAL LETTER KA */ \
+ 0x043A, /* CYRILLIC SMALL LETTER KA */ }, \
+ { 0x049A, /* CYRILLIC CAPITAL LETTER KA WITH DESCENDER */ \
+ 0x049B, /* CYRILLIC SMALL LETTER KA WITH DESCENDER */ }, \
+ { 0x04C3, /* CYRILLIC CAPITAL LETTER KA WITH HOOK */ \
+ 0x04C4, /* CYRILLIC SMALL LETTER KA WITH HOOK */ }, \
+ { 0x049E, /* CYRILLIC CAPITAL LETTER KA WITH STROKE */ \
+ 0x049F, /* CYRILLIC SMALL LETTER KA WITH STROKE */ }, \
+ { 0x049C, /* CYRILLIC CAPITAL LETTER KA WITH VERTICAL STROKE */ \
+ 0x049D, /* CYRILLIC SMALL LETTER KA WITH VERTICAL STROKE */ }, \
+ { 0x04CB, /* CYRILLIC CAPITAL LETTER KHAKASSIAN CHE */ \
+ 0x04CC, /* CYRILLIC SMALL LETTER KHAKASSIAN CHE */ }, \
+ { 0x040C, /* CYRILLIC CAPITAL LETTER KJE */ \
+ 0x045C, /* CYRILLIC SMALL LETTER KJE */ }, \
+ { 0x0500, /* CYRILLIC CAPITAL LETTER KOMI DE */ \
+ 0x0501, /* CYRILLIC SMALL LETTER KOMI DE */ }, \
+ { 0x0502, /* CYRILLIC CAPITAL LETTER KOMI DJE */ \
+ 0x0503, /* CYRILLIC SMALL LETTER KOMI DJE */ }, \
+ { 0x0506, /* CYRILLIC CAPITAL LETTER KOMI DZJE */ \
+ 0x0507, /* CYRILLIC SMALL LETTER KOMI DZJE */ }, \
+ { 0x0508, /* CYRILLIC CAPITAL LETTER KOMI LJE */ \
+ 0x0509, /* CYRILLIC SMALL LETTER KOMI LJE */ }, \
+ { 0x050A, /* CYRILLIC CAPITAL LETTER KOMI NJE */ \
+ 0x050B, /* CYRILLIC SMALL LETTER KOMI NJE */ }, \
+ { 0x050C, /* CYRILLIC CAPITAL LETTER KOMI SJE */ \
+ 0x050D, /* CYRILLIC SMALL LETTER KOMI SJE */ }, \
+ { 0x050E, /* CYRILLIC CAPITAL LETTER KOMI TJE */ \
+ 0x050F, /* CYRILLIC SMALL LETTER KOMI TJE */ }, \
+ { 0x0504, /* CYRILLIC CAPITAL LETTER KOMI ZJE */ \
+ 0x0505, /* CYRILLIC SMALL LETTER KOMI ZJE */ }, \
+ { 0x0480, /* CYRILLIC CAPITAL LETTER KOPPA */ \
+ 0x0481, /* CYRILLIC SMALL LETTER KOPPA */ }, \
+ { 0x046E, /* CYRILLIC CAPITAL LETTER KSI */ \
+ 0x046F, /* CYRILLIC SMALL LETTER KSI */ }, \
+ { 0x0514, /* CYRILLIC CAPITAL LETTER LHA */ \
+ 0x0515, /* CYRILLIC SMALL LETTER LHA */ }, \
+ { 0x0466, /* CYRILLIC CAPITAL LETTER LITTLE YUS */ \
+ 0x0467, /* CYRILLIC SMALL LETTER LITTLE YUS */ }, \
+ { 0x0409, /* CYRILLIC CAPITAL LETTER LJE */ \
+ 0x0459, /* CYRILLIC SMALL LETTER LJE */ }, \
+ { 0xA668, /* CYRILLIC CAPITAL LETTER MONOCULAR O */ \
+ 0xA669, /* CYRILLIC SMALL LETTER MONOCULAR O */ }, \
+ { 0xA64A, /* CYRILLIC CAPITAL LETTER MONOGRAPH UK */ \
+ 0xA64B, /* CYRILLIC SMALL LETTER MONOGRAPH UK */ }, \
+ { 0xA64E, /* CYRILLIC CAPITAL LETTER NEUTRAL YER */ \
+ 0xA64F, /* CYRILLIC SMALL LETTER NEUTRAL YER */ }, \
+ { 0x040A, /* CYRILLIC CAPITAL LETTER NJE */ \
+ 0x045A, /* CYRILLIC SMALL LETTER NJE */ }, \
+ { 0x041E, /* CYRILLIC CAPITAL LETTER O */ \
+ 0x043E, /* CYRILLIC SMALL LETTER O */ }, \
+ { 0x04E6, /* CYRILLIC CAPITAL LETTER O WITH DIAERESIS */ \
+ 0x04E7, /* CYRILLIC SMALL LETTER O WITH DIAERESIS */ }, \
+ { 0x0460, /* CYRILLIC CAPITAL LETTER OMEGA */ \
+ 0x0461, /* CYRILLIC SMALL LETTER OMEGA */ }, \
+ { 0x047C, /* CYRILLIC CAPITAL LETTER OMEGA WITH TITLO */ \
+ 0x047D, /* CYRILLIC SMALL LETTER OMEGA WITH TITLO */ }, \
+ { 0x047E, /* CYRILLIC CAPITAL LETTER OT */ \
+ 0x047F, /* CYRILLIC SMALL LETTER OT */ }, \
+ { 0x041F, /* CYRILLIC CAPITAL LETTER PE */ \
+ 0x043F, /* CYRILLIC SMALL LETTER PE */ }, \
+ { 0x0524, /* CYRILLIC CAPITAL LETTER PE WITH DESCENDER */ \
+ 0x0525, /* CYRILLIC SMALL LETTER PE WITH DESCENDER */ }, \
+ { 0x04A6, /* CYRILLIC CAPITAL LETTER PE WITH MIDDLE HOOK */ \
+ 0x04A7, /* CYRILLIC SMALL LETTER PE WITH MIDDLE HOOK */ }, \
+ { 0x0470, /* CYRILLIC CAPITAL LETTER PSI */ \
+ 0x0471, /* CYRILLIC SMALL LETTER PSI */ }, \
+ { 0x051A, /* CYRILLIC CAPITAL LETTER QA */ \
+ 0x051B, /* CYRILLIC SMALL LETTER QA */ }, \
+ { 0xA644, /* CYRILLIC CAPITAL LETTER REVERSED DZE */ \
+ 0xA645, /* CYRILLIC SMALL LETTER REVERSED DZE */ }, \
+ { 0xA660, /* CYRILLIC CAPITAL LETTER REVERSED TSE */ \
+ 0xA661, /* CYRILLIC SMALL LETTER REVERSED TSE */ }, \
+ { 0xA654, /* CYRILLIC CAPITAL LETTER REVERSED YU */ \
+ 0xA655, /* CYRILLIC SMALL LETTER REVERSED YU */ }, \
+ { 0x0510, /* CYRILLIC CAPITAL LETTER REVERSED ZE */ \
+ 0x0511, /* CYRILLIC SMALL LETTER REVERSED ZE */ }, \
+ { 0x0516, /* CYRILLIC CAPITAL LETTER RHA */ \
+ 0x0517, /* CYRILLIC SMALL LETTER RHA */ }, \
+ { 0x047A, /* CYRILLIC CAPITAL LETTER ROUND OMEGA */ \
+ 0x047B, /* CYRILLIC SMALL LETTER ROUND OMEGA */ }, \
+ { 0x04D8, /* CYRILLIC CAPITAL LETTER SCHWA */ \
+ 0x04D9, /* CYRILLIC SMALL LETTER SCHWA */ }, \
+ { 0x04DA, /* CYRILLIC CAPITAL LETTER SCHWA WITH DIAERESIS */ \
+ 0x04DB, /* CYRILLIC SMALL LETTER SCHWA WITH DIAERESIS */ }, \
+ { 0x048C, /* CYRILLIC CAPITAL LETTER SEMISOFT SIGN */ \
+ 0x048D, /* CYRILLIC SMALL LETTER SEMISOFT SIGN */ }, \
+ { 0x0428, /* CYRILLIC CAPITAL LETTER SHA */ \
+ 0x0448, /* CYRILLIC SMALL LETTER SHA */ }, \
+ { 0x0429, /* CYRILLIC CAPITAL LETTER SHCHA */ \
+ 0x0449, /* CYRILLIC SMALL LETTER SHCHA */ }, \
+ { 0x04BA, /* CYRILLIC CAPITAL LETTER SHHA */ \
+ 0x04BB, /* CYRILLIC SMALL LETTER SHHA */ }, \
+ { 0x0526, /* CYRILLIC CAPITAL LETTER SHHA WITH DESCENDER */ \
+ 0x0527, /* CYRILLIC SMALL LETTER SHHA WITH DESCENDER */ }, \
+ { 0x048A, /* CYRILLIC CAPITAL LETTER SHORT I WITH TAIL */ \
+ 0x048B, /* CYRILLIC SMALL LETTER SHORT I WITH TAIL */ }, \
+ { 0x040E, /* CYRILLIC CAPITAL LETTER SHORT U */ \
+ 0x045E, /* CYRILLIC SMALL LETTER SHORT U */ }, \
+ { 0xA696, /* CYRILLIC CAPITAL LETTER SHWE */ \
+ 0xA697, /* CYRILLIC SMALL LETTER SHWE */ }, \
+ { 0xA662, /* CYRILLIC CAPITAL LETTER SOFT DE */ \
+ 0xA663, /* CYRILLIC SMALL LETTER SOFT DE */ }, \
+ { 0xA664, /* CYRILLIC CAPITAL LETTER SOFT EL */ \
+ 0xA665, /* CYRILLIC SMALL LETTER SOFT EL */ }, \
+ { 0xA666, /* CYRILLIC CAPITAL LETTER SOFT EM */ \
+ 0xA667, /* CYRILLIC SMALL LETTER SOFT EM */ }, \
+ { 0x042C, /* CYRILLIC CAPITAL LETTER SOFT SIGN */ \
+ 0x044C, /* CYRILLIC SMALL LETTER SOFT SIGN */ }, \
+ { 0x04AE, /* CYRILLIC CAPITAL LETTER STRAIGHT U */ \
+ 0x04AF, /* CYRILLIC SMALL LETTER STRAIGHT U */ }, \
+ { 0x04B0, /* CYRILLIC CAPITAL LETTER STRAIGHT U WITH STROKE */ \
+ 0x04B1, /* CYRILLIC SMALL LETTER STRAIGHT U WITH STROKE */ }, \
+ { 0xA692, /* CYRILLIC CAPITAL LETTER TCHE */ \
+ 0xA693, /* CYRILLIC SMALL LETTER TCHE */ }, \
+ { 0x0422, /* CYRILLIC CAPITAL LETTER TE */ \
+ 0x0442, /* CYRILLIC SMALL LETTER TE */ }, \
+ { 0x04AC, /* CYRILLIC CAPITAL LETTER TE WITH DESCENDER */ \
+ 0x04AD, /* CYRILLIC SMALL LETTER TE WITH DESCENDER */ }, \
+ { 0xA68A, /* CYRILLIC CAPITAL LETTER TE WITH MIDDLE HOOK */ \
+ 0xA68B, /* CYRILLIC SMALL LETTER TE WITH MIDDLE HOOK */ }, \
+ { 0x0426, /* CYRILLIC CAPITAL LETTER TSE */ \
+ 0x0446, /* CYRILLIC SMALL LETTER TSE */ }, \
+ { 0x040B, /* CYRILLIC CAPITAL LETTER TSHE */ \
+ 0x045B, /* CYRILLIC SMALL LETTER TSHE */ }, \
+ { 0xA690, /* CYRILLIC CAPITAL LETTER TSSE */ \
+ 0xA691, /* CYRILLIC SMALL LETTER TSSE */ }, \
+ { 0xA68E, /* CYRILLIC CAPITAL LETTER TSWE */ \
+ 0xA68F, /* CYRILLIC SMALL LETTER TSWE */ }, \
+ { 0xA68C, /* CYRILLIC CAPITAL LETTER TWE */ \
+ 0xA68D, /* CYRILLIC SMALL LETTER TWE */ }, \
+ { 0x0423, /* CYRILLIC CAPITAL LETTER U */ \
+ 0x0443, /* CYRILLIC SMALL LETTER U */ }, \
+ { 0x04F0, /* CYRILLIC CAPITAL LETTER U WITH DIAERESIS */ \
+ 0x04F1, /* CYRILLIC SMALL LETTER U WITH DIAERESIS */ }, \
+ { 0x04F2, /* CYRILLIC CAPITAL LETTER U WITH DOUBLE ACUTE */ \
+ 0x04F3, /* CYRILLIC SMALL LETTER U WITH DOUBLE ACUTE */ }, \
+ { 0x04EE, /* CYRILLIC CAPITAL LETTER U WITH MACRON */ \
+ 0x04EF, /* CYRILLIC SMALL LETTER U WITH MACRON */ }, \
+ { 0x0478, /* CYRILLIC CAPITAL LETTER UK */ \
+ 0x0479, /* CYRILLIC SMALL LETTER UK */ }, \
+ { 0x0404, /* CYRILLIC CAPITAL LETTER UKRAINIAN IE */ \
+ 0x0454, /* CYRILLIC SMALL LETTER UKRAINIAN IE */ }, \
+ { 0x0412, /* CYRILLIC CAPITAL LETTER VE */ \
+ 0x0432, /* CYRILLIC SMALL LETTER VE */ }, \
+ { 0x051C, /* CYRILLIC CAPITAL LETTER WE */ \
+ 0x051D, /* CYRILLIC SMALL LETTER WE */ }, \
+ { 0x042F, /* CYRILLIC CAPITAL LETTER YA */ \
+ 0x044F, /* CYRILLIC SMALL LETTER YA */ }, \
+ { 0x0518, /* CYRILLIC CAPITAL LETTER YAE */ \
+ 0x0519, /* CYRILLIC SMALL LETTER YAE */ }, \
+ { 0x0462, /* CYRILLIC CAPITAL LETTER YAT */ \
+ 0x0463, /* CYRILLIC SMALL LETTER YAT */ }, \
+ { 0x042B, /* CYRILLIC CAPITAL LETTER YERU */ \
+ 0x044B, /* CYRILLIC SMALL LETTER YERU */ }, \
+ { 0xA650, /* CYRILLIC CAPITAL LETTER YERU WITH BACK YER */ \
+ 0xA651, /* CYRILLIC SMALL LETTER YERU WITH BACK YER */ }, \
+ { 0x04F8, /* CYRILLIC CAPITAL LETTER YERU WITH DIAERESIS */ \
+ 0x04F9, /* CYRILLIC SMALL LETTER YERU WITH DIAERESIS */ }, \
+ { 0x0407, /* CYRILLIC CAPITAL LETTER YI */ \
+ 0x0457, /* CYRILLIC SMALL LETTER YI */ }, \
+ { 0xA65E, /* CYRILLIC CAPITAL LETTER YN */ \
+ 0xA65F, /* CYRILLIC SMALL LETTER YN */ }, \
+ { 0x042E, /* CYRILLIC CAPITAL LETTER YU */ \
+ 0x044E, /* CYRILLIC SMALL LETTER YU */ }, \
+ { 0x0417, /* CYRILLIC CAPITAL LETTER ZE */ \
+ 0x0437, /* CYRILLIC SMALL LETTER ZE */ }, \
+ { 0x0498, /* CYRILLIC CAPITAL LETTER ZE WITH DESCENDER */ \
+ 0x0499, /* CYRILLIC SMALL LETTER ZE WITH DESCENDER */ }, \
+ { 0x04DE, /* CYRILLIC CAPITAL LETTER ZE WITH DIAERESIS */ \
+ 0x04DF, /* CYRILLIC SMALL LETTER ZE WITH DIAERESIS */ }, \
+ { 0xA640, /* CYRILLIC CAPITAL LETTER ZEMLYA */ \
+ 0xA641, /* CYRILLIC SMALL LETTER ZEMLYA */ }, \
+ { 0x0416, /* CYRILLIC CAPITAL LETTER ZHE */ \
+ 0x0436, /* CYRILLIC SMALL LETTER ZHE */ }, \
+ { 0x04C1, /* CYRILLIC CAPITAL LETTER ZHE WITH BREVE */ \
+ 0x04C2, /* CYRILLIC SMALL LETTER ZHE WITH BREVE */ }, \
+ { 0x0496, /* CYRILLIC CAPITAL LETTER ZHE WITH DESCENDER */ \
+ 0x0497, /* CYRILLIC SMALL LETTER ZHE WITH DESCENDER */ }, \
+ { 0x04DC, /* CYRILLIC CAPITAL LETTER ZHE WITH DIAERESIS */ \
+ 0x04DD, /* CYRILLIC SMALL LETTER ZHE WITH DIAERESIS */ }, \
+ { 0xA684, /* CYRILLIC CAPITAL LETTER ZHWE */ \
+ 0xA685, /* CYRILLIC SMALL LETTER ZHWE */ }, \
+ { 0xFF21, /* FULLWIDTH LATIN CAPITAL LETTER A */ \
+ 0xFF41, /* FULLWIDTH LATIN SMALL LETTER A */ }, \
+ { 0xFF22, /* FULLWIDTH LATIN CAPITAL LETTER B */ \
+ 0xFF42, /* FULLWIDTH LATIN SMALL LETTER B */ }, \
+ { 0xFF23, /* FULLWIDTH LATIN CAPITAL LETTER C */ \
+ 0xFF43, /* FULLWIDTH LATIN SMALL LETTER C */ }, \
+ { 0xFF24, /* FULLWIDTH LATIN CAPITAL LETTER D */ \
+ 0xFF44, /* FULLWIDTH LATIN SMALL LETTER D */ }, \
+ { 0xFF25, /* FULLWIDTH LATIN CAPITAL LETTER E */ \
+ 0xFF45, /* FULLWIDTH LATIN SMALL LETTER E */ }, \
+ { 0xFF26, /* FULLWIDTH LATIN CAPITAL LETTER F */ \
+ 0xFF46, /* FULLWIDTH LATIN SMALL LETTER F */ }, \
+ { 0xFF27, /* FULLWIDTH LATIN CAPITAL LETTER G */ \
+ 0xFF47, /* FULLWIDTH LATIN SMALL LETTER G */ }, \
+ { 0xFF28, /* FULLWIDTH LATIN CAPITAL LETTER H */ \
+ 0xFF48, /* FULLWIDTH LATIN SMALL LETTER H */ }, \
+ { 0xFF29, /* FULLWIDTH LATIN CAPITAL LETTER I */ \
+ 0xFF49, /* FULLWIDTH LATIN SMALL LETTER I */ }, \
+ { 0xFF2A, /* FULLWIDTH LATIN CAPITAL LETTER J */ \
+ 0xFF4A, /* FULLWIDTH LATIN SMALL LETTER J */ }, \
+ { 0xFF2B, /* FULLWIDTH LATIN CAPITAL LETTER K */ \
+ 0xFF4B, /* FULLWIDTH LATIN SMALL LETTER K */ }, \
+ { 0xFF2C, /* FULLWIDTH LATIN CAPITAL LETTER L */ \
+ 0xFF4C, /* FULLWIDTH LATIN SMALL LETTER L */ }, \
+ { 0xFF2D, /* FULLWIDTH LATIN CAPITAL LETTER M */ \
+ 0xFF4D, /* FULLWIDTH LATIN SMALL LETTER M */ }, \
+ { 0xFF2E, /* FULLWIDTH LATIN CAPITAL LETTER N */ \
+ 0xFF4E, /* FULLWIDTH LATIN SMALL LETTER N */ }, \
+ { 0xFF2F, /* FULLWIDTH LATIN CAPITAL LETTER O */ \
+ 0xFF4F, /* FULLWIDTH LATIN SMALL LETTER O */ }, \
+ { 0xFF30, /* FULLWIDTH LATIN CAPITAL LETTER P */ \
+ 0xFF50, /* FULLWIDTH LATIN SMALL LETTER P */ }, \
+ { 0xFF31, /* FULLWIDTH LATIN CAPITAL LETTER Q */ \
+ 0xFF51, /* FULLWIDTH LATIN SMALL LETTER Q */ }, \
+ { 0xFF32, /* FULLWIDTH LATIN CAPITAL LETTER R */ \
+ 0xFF52, /* FULLWIDTH LATIN SMALL LETTER R */ }, \
+ { 0xFF33, /* FULLWIDTH LATIN CAPITAL LETTER S */ \
+ 0xFF53, /* FULLWIDTH LATIN SMALL LETTER S */ }, \
+ { 0xFF34, /* FULLWIDTH LATIN CAPITAL LETTER T */ \
+ 0xFF54, /* FULLWIDTH LATIN SMALL LETTER T */ }, \
+ { 0xFF35, /* FULLWIDTH LATIN CAPITAL LETTER U */ \
+ 0xFF55, /* FULLWIDTH LATIN SMALL LETTER U */ }, \
+ { 0xFF36, /* FULLWIDTH LATIN CAPITAL LETTER V */ \
+ 0xFF56, /* FULLWIDTH LATIN SMALL LETTER V */ }, \
+ { 0xFF37, /* FULLWIDTH LATIN CAPITAL LETTER W */ \
+ 0xFF57, /* FULLWIDTH LATIN SMALL LETTER W */ }, \
+ { 0xFF38, /* FULLWIDTH LATIN CAPITAL LETTER X */ \
+ 0xFF58, /* FULLWIDTH LATIN SMALL LETTER X */ }, \
+ { 0xFF39, /* FULLWIDTH LATIN CAPITAL LETTER Y */ \
+ 0xFF59, /* FULLWIDTH LATIN SMALL LETTER Y */ }, \
+ { 0xFF3A, /* FULLWIDTH LATIN CAPITAL LETTER Z */ \
+ 0xFF5A, /* FULLWIDTH LATIN SMALL LETTER Z */ }, \
+ { 0x10CD, /* GEORGIAN CAPITAL LETTER AEN */ \
+ 0x2D2D, /* GEORGIAN SMALL LETTER AEN */ }, \
+ { 0x10A0, /* GEORGIAN CAPITAL LETTER AN */ \
+ 0x2D00, /* GEORGIAN SMALL LETTER AN */ }, \
+ { 0x10A1, /* GEORGIAN CAPITAL LETTER BAN */ \
+ 0x2D01, /* GEORGIAN SMALL LETTER BAN */ }, \
+ { 0x10BA, /* GEORGIAN CAPITAL LETTER CAN */ \
+ 0x2D1A, /* GEORGIAN SMALL LETTER CAN */ }, \
+ { 0x10BD, /* GEORGIAN CAPITAL LETTER CHAR */ \
+ 0x2D1D, /* GEORGIAN SMALL LETTER CHAR */ }, \
+ { 0x10B9, /* GEORGIAN CAPITAL LETTER CHIN */ \
+ 0x2D19, /* GEORGIAN SMALL LETTER CHIN */ }, \
+ { 0x10BC, /* GEORGIAN CAPITAL LETTER CIL */ \
+ 0x2D1C, /* GEORGIAN SMALL LETTER CIL */ }, \
+ { 0x10A3, /* GEORGIAN CAPITAL LETTER DON */ \
+ 0x2D03, /* GEORGIAN SMALL LETTER DON */ }, \
+ { 0x10A4, /* GEORGIAN CAPITAL LETTER EN */ \
+ 0x2D04, /* GEORGIAN SMALL LETTER EN */ }, \
+ { 0x10A2, /* GEORGIAN CAPITAL LETTER GAN */ \
+ 0x2D02, /* GEORGIAN SMALL LETTER GAN */ }, \
+ { 0x10B6, /* GEORGIAN CAPITAL LETTER GHAN */ \
+ 0x2D16, /* GEORGIAN SMALL LETTER GHAN */ }, \
+ { 0x10C0, /* GEORGIAN CAPITAL LETTER HAE */ \
+ 0x2D20, /* GEORGIAN SMALL LETTER HAE */ }, \
+ { 0x10C4, /* GEORGIAN CAPITAL LETTER HAR */ \
+ 0x2D24, /* GEORGIAN SMALL LETTER HAR */ }, \
+ { 0x10C1, /* GEORGIAN CAPITAL LETTER HE */ \
+ 0x2D21, /* GEORGIAN SMALL LETTER HE */ }, \
+ { 0x10C2, /* GEORGIAN CAPITAL LETTER HIE */ \
+ 0x2D22, /* GEORGIAN SMALL LETTER HIE */ }, \
+ { 0x10C5, /* GEORGIAN CAPITAL LETTER HOE */ \
+ 0x2D25, /* GEORGIAN SMALL LETTER HOE */ }, \
+ { 0x10A8, /* GEORGIAN CAPITAL LETTER IN */ \
+ 0x2D08, /* GEORGIAN SMALL LETTER IN */ }, \
+ { 0x10BF, /* GEORGIAN CAPITAL LETTER JHAN */ \
+ 0x2D1F, /* GEORGIAN SMALL LETTER JHAN */ }, \
+ { 0x10BB, /* GEORGIAN CAPITAL LETTER JIL */ \
+ 0x2D1B, /* GEORGIAN SMALL LETTER JIL */ }, \
+ { 0x10A9, /* GEORGIAN CAPITAL LETTER KAN */ \
+ 0x2D09, /* GEORGIAN SMALL LETTER KAN */ }, \
+ { 0x10B5, /* GEORGIAN CAPITAL LETTER KHAR */ \
+ 0x2D15, /* GEORGIAN SMALL LETTER KHAR */ }, \
+ { 0x10AA, /* GEORGIAN CAPITAL LETTER LAS */ \
+ 0x2D0A, /* GEORGIAN SMALL LETTER LAS */ }, \
+ { 0x10AB, /* GEORGIAN CAPITAL LETTER MAN */ \
+ 0x2D0B, /* GEORGIAN SMALL LETTER MAN */ }, \
+ { 0x10AC, /* GEORGIAN CAPITAL LETTER NAR */ \
+ 0x2D0C, /* GEORGIAN SMALL LETTER NAR */ }, \
+ { 0x10AD, /* GEORGIAN CAPITAL LETTER ON */ \
+ 0x2D0D, /* GEORGIAN SMALL LETTER ON */ }, \
+ { 0x10AE, /* GEORGIAN CAPITAL LETTER PAR */ \
+ 0x2D0E, /* GEORGIAN SMALL LETTER PAR */ }, \
+ { 0x10B4, /* GEORGIAN CAPITAL LETTER PHAR */ \
+ 0x2D14, /* GEORGIAN SMALL LETTER PHAR */ }, \
+ { 0x10B7, /* GEORGIAN CAPITAL LETTER QAR */ \
+ 0x2D17, /* GEORGIAN SMALL LETTER QAR */ }, \
+ { 0x10B0, /* GEORGIAN CAPITAL LETTER RAE */ \
+ 0x2D10, /* GEORGIAN SMALL LETTER RAE */ }, \
+ { 0x10B1, /* GEORGIAN CAPITAL LETTER SAN */ \
+ 0x2D11, /* GEORGIAN SMALL LETTER SAN */ }, \
+ { 0x10B8, /* GEORGIAN CAPITAL LETTER SHIN */ \
+ 0x2D18, /* GEORGIAN SMALL LETTER SHIN */ }, \
+ { 0x10A7, /* GEORGIAN CAPITAL LETTER TAN */ \
+ 0x2D07, /* GEORGIAN SMALL LETTER TAN */ }, \
+ { 0x10B2, /* GEORGIAN CAPITAL LETTER TAR */ \
+ 0x2D12, /* GEORGIAN SMALL LETTER TAR */ }, \
+ { 0x10B3, /* GEORGIAN CAPITAL LETTER UN */ \
+ 0x2D13, /* GEORGIAN SMALL LETTER UN */ }, \
+ { 0x10A5, /* GEORGIAN CAPITAL LETTER VIN */ \
+ 0x2D05, /* GEORGIAN SMALL LETTER VIN */ }, \
+ { 0x10C3, /* GEORGIAN CAPITAL LETTER WE */ \
+ 0x2D23, /* GEORGIAN SMALL LETTER WE */ }, \
+ { 0x10BE, /* GEORGIAN CAPITAL LETTER XAN */ \
+ 0x2D1E, /* GEORGIAN SMALL LETTER XAN */ }, \
+ { 0x10C7, /* GEORGIAN CAPITAL LETTER YN */ \
+ 0x2D27, /* GEORGIAN SMALL LETTER YN */ }, \
+ { 0x10A6, /* GEORGIAN CAPITAL LETTER ZEN */ \
+ 0x2D06, /* GEORGIAN SMALL LETTER ZEN */ }, \
+ { 0x10AF, /* GEORGIAN CAPITAL LETTER ZHAR */ \
+ 0x2D0F, /* GEORGIAN SMALL LETTER ZHAR */ }, \
+ { 0x2C00, /* GLAGOLITIC CAPITAL LETTER AZU */ \
+ 0x2C30, /* GLAGOLITIC SMALL LETTER AZU */ }, \
+ { 0x2C28, /* GLAGOLITIC CAPITAL LETTER BIG YUS */ \
+ 0x2C58, /* GLAGOLITIC SMALL LETTER BIG YUS */ }, \
+ { 0x2C01, /* GLAGOLITIC CAPITAL LETTER BUKY */ \
+ 0x2C31, /* GLAGOLITIC SMALL LETTER BUKY */ }, \
+ { 0x2C1D, /* GLAGOLITIC CAPITAL LETTER CHRIVI */ \
+ 0x2C4D, /* GLAGOLITIC SMALL LETTER CHRIVI */ }, \
+ { 0x2C0C, /* GLAGOLITIC CAPITAL LETTER DJERVI */ \
+ 0x2C3C, /* GLAGOLITIC SMALL LETTER DJERVI */ }, \
+ { 0x2C04, /* GLAGOLITIC CAPITAL LETTER DOBRO */ \
+ 0x2C34, /* GLAGOLITIC SMALL LETTER DOBRO */ }, \
+ { 0x2C07, /* GLAGOLITIC CAPITAL LETTER DZELO */ \
+ 0x2C37, /* GLAGOLITIC SMALL LETTER DZELO */ }, \
+ { 0x2C2A, /* GLAGOLITIC CAPITAL LETTER FITA */ \
+ 0x2C5A, /* GLAGOLITIC SMALL LETTER FITA */ }, \
+ { 0x2C17, /* GLAGOLITIC CAPITAL LETTER FRITU */ \
+ 0x2C47, /* GLAGOLITIC SMALL LETTER FRITU */ }, \
+ { 0x2C03, /* GLAGOLITIC CAPITAL LETTER GLAGOLI */ \
+ 0x2C33, /* GLAGOLITIC SMALL LETTER GLAGOLI */ }, \
+ { 0x2C18, /* GLAGOLITIC CAPITAL LETTER HERU */ \
+ 0x2C48, /* GLAGOLITIC SMALL LETTER HERU */ }, \
+ { 0x2C0B, /* GLAGOLITIC CAPITAL LETTER I */ \
+ 0x2C3B, /* GLAGOLITIC SMALL LETTER I */ }, \
+ { 0x2C0A, /* GLAGOLITIC CAPITAL LETTER INITIAL IZHE */ \
+ 0x2C3A, /* GLAGOLITIC SMALL LETTER INITIAL IZHE */ }, \
+ { 0x2C29, /* GLAGOLITIC CAPITAL LETTER IOTATED BIG YUS */ \
+ 0x2C59, /* GLAGOLITIC SMALL LETTER IOTATED BIG YUS */ }, \
+ { 0x2C27, /* GLAGOLITIC CAPITAL LETTER IOTATED SMALL YUS */ \
+ 0x2C57, /* GLAGOLITIC SMALL LETTER IOTATED SMALL YUS */ }, \
+ { 0x2C09, /* GLAGOLITIC CAPITAL LETTER IZHE */ \
+ 0x2C39, /* GLAGOLITIC SMALL LETTER IZHE */ }, \
+ { 0x2C2B, /* GLAGOLITIC CAPITAL LETTER IZHITSA */ \
+ 0x2C5B, /* GLAGOLITIC SMALL LETTER IZHITSA */ }, \
+ { 0x2C0D, /* GLAGOLITIC CAPITAL LETTER KAKO */ \
+ 0x2C3D, /* GLAGOLITIC SMALL LETTER KAKO */ }, \
+ { 0x2C2E, /* GLAGOLITIC CAPITAL LETTER LATINATE MYSLITE */ \
+ 0x2C5E, /* GLAGOLITIC SMALL LETTER LATINATE MYSLITE */ }, \
+ { 0x2C0E, /* GLAGOLITIC CAPITAL LETTER LJUDIJE */ \
+ 0x2C3E, /* GLAGOLITIC SMALL LETTER LJUDIJE */ }, \
+ { 0x2C0F, /* GLAGOLITIC CAPITAL LETTER MYSLITE */ \
+ 0x2C3F, /* GLAGOLITIC SMALL LETTER MYSLITE */ }, \
+ { 0x2C10, /* GLAGOLITIC CAPITAL LETTER NASHI */ \
+ 0x2C40, /* GLAGOLITIC SMALL LETTER NASHI */ }, \
+ { 0x2C11, /* GLAGOLITIC CAPITAL LETTER ONU */ \
+ 0x2C41, /* GLAGOLITIC SMALL LETTER ONU */ }, \
+ { 0x2C19, /* GLAGOLITIC CAPITAL LETTER OTU */ \
+ 0x2C49, /* GLAGOLITIC SMALL LETTER OTU */ }, \
+ { 0x2C1A, /* GLAGOLITIC CAPITAL LETTER PE */ \
+ 0x2C4A, /* GLAGOLITIC SMALL LETTER PE */ }, \
+ { 0x2C12, /* GLAGOLITIC CAPITAL LETTER POKOJI */ \
+ 0x2C42, /* GLAGOLITIC SMALL LETTER POKOJI */ }, \
+ { 0x2C13, /* GLAGOLITIC CAPITAL LETTER RITSI */ \
+ 0x2C43, /* GLAGOLITIC SMALL LETTER RITSI */ }, \
+ { 0x2C1E, /* GLAGOLITIC CAPITAL LETTER SHA */ \
+ 0x2C4E, /* GLAGOLITIC SMALL LETTER SHA */ }, \
+ { 0x2C1B, /* GLAGOLITIC CAPITAL LETTER SHTA */ \
+ 0x2C4B, /* GLAGOLITIC SMALL LETTER SHTA */ }, \
+ { 0x2C2C, /* GLAGOLITIC CAPITAL LETTER SHTAPIC */ \
+ 0x2C5C, /* GLAGOLITIC SMALL LETTER SHTAPIC */ }, \
+ { 0x2C14, /* GLAGOLITIC CAPITAL LETTER SLOVO */ \
+ 0x2C44, /* GLAGOLITIC SMALL LETTER SLOVO */ }, \
+ { 0x2C24, /* GLAGOLITIC CAPITAL LETTER SMALL YUS */ \
+ 0x2C54, /* GLAGOLITIC SMALL LETTER SMALL YUS */ }, \
+ { 0x2C25, /* GLAGOLITIC CAPITAL LETTER SMALL YUS WITH TAIL */ \
+ 0x2C55, /* GLAGOLITIC SMALL LETTER SMALL YUS WITH TAIL */ }, \
+ { 0x2C22, /* GLAGOLITIC CAPITAL LETTER SPIDERY HA */ \
+ 0x2C52, /* GLAGOLITIC SMALL LETTER SPIDERY HA */ }, \
+ { 0x2C2D, /* GLAGOLITIC CAPITAL LETTER TROKUTASTI A */ \
+ 0x2C5D, /* GLAGOLITIC SMALL LETTER TROKUTASTI A */ }, \
+ { 0x2C1C, /* GLAGOLITIC CAPITAL LETTER TSI */ \
+ 0x2C4C, /* GLAGOLITIC SMALL LETTER TSI */ }, \
+ { 0x2C15, /* GLAGOLITIC CAPITAL LETTER TVRIDO */ \
+ 0x2C45, /* GLAGOLITIC SMALL LETTER TVRIDO */ }, \
+ { 0x2C16, /* GLAGOLITIC CAPITAL LETTER UKU */ \
+ 0x2C46, /* GLAGOLITIC SMALL LETTER UKU */ }, \
+ { 0x2C02, /* GLAGOLITIC CAPITAL LETTER VEDE */ \
+ 0x2C32, /* GLAGOLITIC SMALL LETTER VEDE */ }, \
+ { 0x2C21, /* GLAGOLITIC CAPITAL LETTER YATI */ \
+ 0x2C51, /* GLAGOLITIC SMALL LETTER YATI */ }, \
+ { 0x2C20, /* GLAGOLITIC CAPITAL LETTER YERI */ \
+ 0x2C50, /* GLAGOLITIC SMALL LETTER YERI */ }, \
+ { 0x2C1F, /* GLAGOLITIC CAPITAL LETTER YERU */ \
+ 0x2C4F, /* GLAGOLITIC SMALL LETTER YERU */ }, \
+ { 0x2C05, /* GLAGOLITIC CAPITAL LETTER YESTU */ \
+ 0x2C35, /* GLAGOLITIC SMALL LETTER YESTU */ }, \
+ { 0x2C26, /* GLAGOLITIC CAPITAL LETTER YO */ \
+ 0x2C56, /* GLAGOLITIC SMALL LETTER YO */ }, \
+ { 0x2C23, /* GLAGOLITIC CAPITAL LETTER YU */ \
+ 0x2C53, /* GLAGOLITIC SMALL LETTER YU */ }, \
+ { 0x2C08, /* GLAGOLITIC CAPITAL LETTER ZEMLJA */ \
+ 0x2C38, /* GLAGOLITIC SMALL LETTER ZEMLJA */ }, \
+ { 0x2C06, /* GLAGOLITIC CAPITAL LETTER ZHIVETE */ \
+ 0x2C36, /* GLAGOLITIC SMALL LETTER ZHIVETE */ }, \
+ { 0x0391, /* GREEK CAPITAL LETTER ALPHA */ \
+ 0x03B1, /* GREEK SMALL LETTER ALPHA */ }, \
+ { 0x1F09, /* GREEK CAPITAL LETTER ALPHA WITH DASIA */ \
+ 0x1F01, /* GREEK SMALL LETTER ALPHA WITH DASIA */ }, \
+ { 0x1F0D, /* GREEK CAPITAL LETTER ALPHA WITH DASIA AND OXIA */ \
+ 0x1F05, /* GREEK SMALL LETTER ALPHA WITH DASIA AND OXIA */ }, \
+ { 0x1F0F, /* GREEK CAPITAL LETTER ALPHA WITH DASIA AND PERISPOMENI */ \
+ 0x1F07, /* GREEK SMALL LETTER ALPHA WITH DASIA AND PERISPOMENI */ }, \
+ { 0x1F0B, /* GREEK CAPITAL LETTER ALPHA WITH DASIA AND VARIA */ \
+ 0x1F03, /* GREEK SMALL LETTER ALPHA WITH DASIA AND VARIA */ }, \
+ { 0x1FB9, /* GREEK CAPITAL LETTER ALPHA WITH MACRON */ \
+ 0x1FB1, /* GREEK SMALL LETTER ALPHA WITH MACRON */ }, \
+ { 0x1FBB, /* GREEK CAPITAL LETTER ALPHA WITH OXIA */ \
+ 0x1F71, /* GREEK SMALL LETTER ALPHA WITH OXIA */ }, \
+ { 0x1F08, /* GREEK CAPITAL LETTER ALPHA WITH PSILI */ \
+ 0x1F00, /* GREEK SMALL LETTER ALPHA WITH PSILI */ }, \
+ { 0x1F0C, /* GREEK CAPITAL LETTER ALPHA WITH PSILI AND OXIA */ \
+ 0x1F04, /* GREEK SMALL LETTER ALPHA WITH PSILI AND OXIA */ }, \
+ { 0x1F0E, /* GREEK CAPITAL LETTER ALPHA WITH PSILI AND PERISPOMENI */ \
+ 0x1F06, /* GREEK SMALL LETTER ALPHA WITH PSILI AND PERISPOMENI */ }, \
+ { 0x1F0A, /* GREEK CAPITAL LETTER ALPHA WITH PSILI AND VARIA */ \
+ 0x1F02, /* GREEK SMALL LETTER ALPHA WITH PSILI AND VARIA */ }, \
+ { 0x0386, /* GREEK CAPITAL LETTER ALPHA WITH TONOS */ \
+ 0x03AC, /* GREEK SMALL LETTER ALPHA WITH TONOS */ }, \
+ { 0x1FBA, /* GREEK CAPITAL LETTER ALPHA WITH VARIA */ \
+ 0x1F70, /* GREEK SMALL LETTER ALPHA WITH VARIA */ }, \
+ { 0x1FB8, /* GREEK CAPITAL LETTER ALPHA WITH VRACHY */ \
+ 0x1FB0, /* GREEK SMALL LETTER ALPHA WITH VRACHY */ }, \
+ { 0x0372, /* GREEK CAPITAL LETTER ARCHAIC SAMPI */ \
+ 0x0373, /* GREEK SMALL LETTER ARCHAIC SAMPI */ }, \
+ { 0x0392, /* GREEK CAPITAL LETTER BETA */ \
+ 0x03B2, /* GREEK SMALL LETTER BETA */ }, \
+ { 0x03A7, /* GREEK CAPITAL LETTER CHI */ \
+ 0x03C7, /* GREEK SMALL LETTER CHI */ }, \
+ { 0x0394, /* GREEK CAPITAL LETTER DELTA */ \
+ 0x03B4, /* GREEK SMALL LETTER DELTA */ }, \
+ { 0x0395, /* GREEK CAPITAL LETTER EPSILON */ \
+ 0x03B5, /* GREEK SMALL LETTER EPSILON */ }, \
+ { 0x1F19, /* GREEK CAPITAL LETTER EPSILON WITH DASIA */ \
+ 0x1F11, /* GREEK SMALL LETTER EPSILON WITH DASIA */ }, \
+ { 0x1F1D, /* GREEK CAPITAL LETTER EPSILON WITH DASIA AND OXIA */ \
+ 0x1F15, /* GREEK SMALL LETTER EPSILON WITH DASIA AND OXIA */ }, \
+ { 0x1F1B, /* GREEK CAPITAL LETTER EPSILON WITH DASIA AND VARIA */ \
+ 0x1F13, /* GREEK SMALL LETTER EPSILON WITH DASIA AND VARIA */ }, \
+ { 0x1FC9, /* GREEK CAPITAL LETTER EPSILON WITH OXIA */ \
+ 0x1F73, /* GREEK SMALL LETTER EPSILON WITH OXIA */ }, \
+ { 0x1F18, /* GREEK CAPITAL LETTER EPSILON WITH PSILI */ \
+ 0x1F10, /* GREEK SMALL LETTER EPSILON WITH PSILI */ }, \
+ { 0x1F1C, /* GREEK CAPITAL LETTER EPSILON WITH PSILI AND OXIA */ \
+ 0x1F14, /* GREEK SMALL LETTER EPSILON WITH PSILI AND OXIA */ }, \
+ { 0x1F1A, /* GREEK CAPITAL LETTER EPSILON WITH PSILI AND VARIA */ \
+ 0x1F12, /* GREEK SMALL LETTER EPSILON WITH PSILI AND VARIA */ }, \
+ { 0x0388, /* GREEK CAPITAL LETTER EPSILON WITH TONOS */ \
+ 0x03AD, /* GREEK SMALL LETTER EPSILON WITH TONOS */ }, \
+ { 0x1FC8, /* GREEK CAPITAL LETTER EPSILON WITH VARIA */ \
+ 0x1F72, /* GREEK SMALL LETTER EPSILON WITH VARIA */ }, \
+ { 0x0397, /* GREEK CAPITAL LETTER ETA */ \
+ 0x03B7, /* GREEK SMALL LETTER ETA */ }, \
+ { 0x1F29, /* GREEK CAPITAL LETTER ETA WITH DASIA */ \
+ 0x1F21, /* GREEK SMALL LETTER ETA WITH DASIA */ }, \
+ { 0x1F2D, /* GREEK CAPITAL LETTER ETA WITH DASIA AND OXIA */ \
+ 0x1F25, /* GREEK SMALL LETTER ETA WITH DASIA AND OXIA */ }, \
+ { 0x1F2F, /* GREEK CAPITAL LETTER ETA WITH DASIA AND PERISPOMENI */ \
+ 0x1F27, /* GREEK SMALL LETTER ETA WITH DASIA AND PERISPOMENI */ }, \
+ { 0x1F2B, /* GREEK CAPITAL LETTER ETA WITH DASIA AND VARIA */ \
+ 0x1F23, /* GREEK SMALL LETTER ETA WITH DASIA AND VARIA */ }, \
+ { 0x1FCB, /* GREEK CAPITAL LETTER ETA WITH OXIA */ \
+ 0x1F75, /* GREEK SMALL LETTER ETA WITH OXIA */ }, \
+ { 0x1F28, /* GREEK CAPITAL LETTER ETA WITH PSILI */ \
+ 0x1F20, /* GREEK SMALL LETTER ETA WITH PSILI */ }, \
+ { 0x1F2C, /* GREEK CAPITAL LETTER ETA WITH PSILI AND OXIA */ \
+ 0x1F24, /* GREEK SMALL LETTER ETA WITH PSILI AND OXIA */ }, \
+ { 0x1F2E, /* GREEK CAPITAL LETTER ETA WITH PSILI AND PERISPOMENI */ \
+ 0x1F26, /* GREEK SMALL LETTER ETA WITH PSILI AND PERISPOMENI */ }, \
+ { 0x1F2A, /* GREEK CAPITAL LETTER ETA WITH PSILI AND VARIA */ \
+ 0x1F22, /* GREEK SMALL LETTER ETA WITH PSILI AND VARIA */ }, \
+ { 0x0389, /* GREEK CAPITAL LETTER ETA WITH TONOS */ \
+ 0x03AE, /* GREEK SMALL LETTER ETA WITH TONOS */ }, \
+ { 0x1FCA, /* GREEK CAPITAL LETTER ETA WITH VARIA */ \
+ 0x1F74, /* GREEK SMALL LETTER ETA WITH VARIA */ }, \
+ { 0x0393, /* GREEK CAPITAL LETTER GAMMA */ \
+ 0x03B3, /* GREEK SMALL LETTER GAMMA */ }, \
+ { 0x0370, /* GREEK CAPITAL LETTER HETA */ \
+ 0x0371, /* GREEK SMALL LETTER HETA */ }, \
+ { 0x0399, /* GREEK CAPITAL LETTER IOTA */ \
+ 0x03B9, /* GREEK SMALL LETTER IOTA */ }, \
+ { 0x1F39, /* GREEK CAPITAL LETTER IOTA WITH DASIA */ \
+ 0x1F31, /* GREEK SMALL LETTER IOTA WITH DASIA */ }, \
+ { 0x1F3D, /* GREEK CAPITAL LETTER IOTA WITH DASIA AND OXIA */ \
+ 0x1F35, /* GREEK SMALL LETTER IOTA WITH DASIA AND OXIA */ }, \
+ { 0x1F3F, /* GREEK CAPITAL LETTER IOTA WITH DASIA AND PERISPOMENI */ \
+ 0x1F37, /* GREEK SMALL LETTER IOTA WITH DASIA AND PERISPOMENI */ }, \
+ { 0x1F3B, /* GREEK CAPITAL LETTER IOTA WITH DASIA AND VARIA */ \
+ 0x1F33, /* GREEK SMALL LETTER IOTA WITH DASIA AND VARIA */ }, \
+ { 0x03AA, /* GREEK CAPITAL LETTER IOTA WITH DIALYTIKA */ \
+ 0x03CA, /* GREEK SMALL LETTER IOTA WITH DIALYTIKA */ }, \
+ { 0x1FD9, /* GREEK CAPITAL LETTER IOTA WITH MACRON */ \
+ 0x1FD1, /* GREEK SMALL LETTER IOTA WITH MACRON */ }, \
+ { 0x1FDB, /* GREEK CAPITAL LETTER IOTA WITH OXIA */ \
+ 0x1F77, /* GREEK SMALL LETTER IOTA WITH OXIA */ }, \
+ { 0x1F38, /* GREEK CAPITAL LETTER IOTA WITH PSILI */ \
+ 0x1F30, /* GREEK SMALL LETTER IOTA WITH PSILI */ }, \
+ { 0x1F3C, /* GREEK CAPITAL LETTER IOTA WITH PSILI AND OXIA */ \
+ 0x1F34, /* GREEK SMALL LETTER IOTA WITH PSILI AND OXIA */ }, \
+ { 0x1F3E, /* GREEK CAPITAL LETTER IOTA WITH PSILI AND PERISPOMENI */ \
+ 0x1F36, /* GREEK SMALL LETTER IOTA WITH PSILI AND PERISPOMENI */ }, \
+ { 0x1F3A, /* GREEK CAPITAL LETTER IOTA WITH PSILI AND VARIA */ \
+ 0x1F32, /* GREEK SMALL LETTER IOTA WITH PSILI AND VARIA */ }, \
+ { 0x038A, /* GREEK CAPITAL LETTER IOTA WITH TONOS */ \
+ 0x03AF, /* GREEK SMALL LETTER IOTA WITH TONOS */ }, \
+ { 0x1FDA, /* GREEK CAPITAL LETTER IOTA WITH VARIA */ \
+ 0x1F76, /* GREEK SMALL LETTER IOTA WITH VARIA */ }, \
+ { 0x1FD8, /* GREEK CAPITAL LETTER IOTA WITH VRACHY */ \
+ 0x1FD0, /* GREEK SMALL LETTER IOTA WITH VRACHY */ }, \
+ { 0x039A, /* GREEK CAPITAL LETTER KAPPA */ \
+ 0x03BA, /* GREEK SMALL LETTER KAPPA */ }, \
+ { 0x039B, /* GREEK CAPITAL LETTER LAMDA */ \
+ 0x03BB, /* GREEK SMALL LETTER LAMDA */ }, \
+ { 0x039C, /* GREEK CAPITAL LETTER MU */ \
+ 0x03BC, /* GREEK SMALL LETTER MU */ }, \
+ { 0x039D, /* GREEK CAPITAL LETTER NU */ \
+ 0x03BD, /* GREEK SMALL LETTER NU */ }, \
+ { 0x03A9, /* GREEK CAPITAL LETTER OMEGA */ \
+ 0x03C9, /* GREEK SMALL LETTER OMEGA */ }, \
+ { 0x1F69, /* GREEK CAPITAL LETTER OMEGA WITH DASIA */ \
+ 0x1F61, /* GREEK SMALL LETTER OMEGA WITH DASIA */ }, \
+ { 0x1F6D, /* GREEK CAPITAL LETTER OMEGA WITH DASIA AND OXIA */ \
+ 0x1F65, /* GREEK SMALL LETTER OMEGA WITH DASIA AND OXIA */ }, \
+ { 0x1F6F, /* GREEK CAPITAL LETTER OMEGA WITH DASIA AND PERISPOMENI */ \
+ 0x1F67, /* GREEK SMALL LETTER OMEGA WITH DASIA AND PERISPOMENI */ }, \
+ { 0x1F6B, /* GREEK CAPITAL LETTER OMEGA WITH DASIA AND VARIA */ \
+ 0x1F63, /* GREEK SMALL LETTER OMEGA WITH DASIA AND VARIA */ }, \
+ { 0x1FFB, /* GREEK CAPITAL LETTER OMEGA WITH OXIA */ \
+ 0x1F7D, /* GREEK SMALL LETTER OMEGA WITH OXIA */ }, \
+ { 0x1F68, /* GREEK CAPITAL LETTER OMEGA WITH PSILI */ \
+ 0x1F60, /* GREEK SMALL LETTER OMEGA WITH PSILI */ }, \
+ { 0x1F6C, /* GREEK CAPITAL LETTER OMEGA WITH PSILI AND OXIA */ \
+ 0x1F64, /* GREEK SMALL LETTER OMEGA WITH PSILI AND OXIA */ }, \
+ { 0x1F6E, /* GREEK CAPITAL LETTER OMEGA WITH PSILI AND PERISPOMENI */ \
+ 0x1F66, /* GREEK SMALL LETTER OMEGA WITH PSILI AND PERISPOMENI */ }, \
+ { 0x1F6A, /* GREEK CAPITAL LETTER OMEGA WITH PSILI AND VARIA */ \
+ 0x1F62, /* GREEK SMALL LETTER OMEGA WITH PSILI AND VARIA */ }, \
+ { 0x038F, /* GREEK CAPITAL LETTER OMEGA WITH TONOS */ \
+ 0x03CE, /* GREEK SMALL LETTER OMEGA WITH TONOS */ }, \
+ { 0x1FFA, /* GREEK CAPITAL LETTER OMEGA WITH VARIA */ \
+ 0x1F7C, /* GREEK SMALL LETTER OMEGA WITH VARIA */ }, \
+ { 0x039F, /* GREEK CAPITAL LETTER OMICRON */ \
+ 0x03BF, /* GREEK SMALL LETTER OMICRON */ }, \
+ { 0x1F49, /* GREEK CAPITAL LETTER OMICRON WITH DASIA */ \
+ 0x1F41, /* GREEK SMALL LETTER OMICRON WITH DASIA */ }, \
+ { 0x1F4D, /* GREEK CAPITAL LETTER OMICRON WITH DASIA AND OXIA */ \
+ 0x1F45, /* GREEK SMALL LETTER OMICRON WITH DASIA AND OXIA */ }, \
+ { 0x1F4B, /* GREEK CAPITAL LETTER OMICRON WITH DASIA AND VARIA */ \
+ 0x1F43, /* GREEK SMALL LETTER OMICRON WITH DASIA AND VARIA */ }, \
+ { 0x1FF9, /* GREEK CAPITAL LETTER OMICRON WITH OXIA */ \
+ 0x1F79, /* GREEK SMALL LETTER OMICRON WITH OXIA */ }, \
+ { 0x1F48, /* GREEK CAPITAL LETTER OMICRON WITH PSILI */ \
+ 0x1F40, /* GREEK SMALL LETTER OMICRON WITH PSILI */ }, \
+ { 0x1F4C, /* GREEK CAPITAL LETTER OMICRON WITH PSILI AND OXIA */ \
+ 0x1F44, /* GREEK SMALL LETTER OMICRON WITH PSILI AND OXIA */ }, \
+ { 0x1F4A, /* GREEK CAPITAL LETTER OMICRON WITH PSILI AND VARIA */ \
+ 0x1F42, /* GREEK SMALL LETTER OMICRON WITH PSILI AND VARIA */ }, \
+ { 0x038C, /* GREEK CAPITAL LETTER OMICRON WITH TONOS */ \
+ 0x03CC, /* GREEK SMALL LETTER OMICRON WITH TONOS */ }, \
+ { 0x1FF8, /* GREEK CAPITAL LETTER OMICRON WITH VARIA */ \
+ 0x1F78, /* GREEK SMALL LETTER OMICRON WITH VARIA */ }, \
+ { 0x0376, /* GREEK CAPITAL LETTER PAMPHYLIAN DIGAMMA */ \
+ 0x0377, /* GREEK SMALL LETTER PAMPHYLIAN DIGAMMA */ }, \
+ { 0x03A6, /* GREEK CAPITAL LETTER PHI */ \
+ 0x03C6, /* GREEK SMALL LETTER PHI */ }, \
+ { 0x03A0, /* GREEK CAPITAL LETTER PI */ \
+ 0x03C0, /* GREEK SMALL LETTER PI */ }, \
+ { 0x03A8, /* GREEK CAPITAL LETTER PSI */ \
+ 0x03C8, /* GREEK SMALL LETTER PSI */ }, \
+ { 0x03A1, /* GREEK CAPITAL LETTER RHO */ \
+ 0x03C1, /* GREEK SMALL LETTER RHO */ }, \
+ { 0x1FEC, /* GREEK CAPITAL LETTER RHO WITH DASIA */ \
+ 0x1FE5, /* GREEK SMALL LETTER RHO WITH DASIA */ }, \
+ { 0x03FA, /* GREEK CAPITAL LETTER SAN */ \
+ 0x03FB, /* GREEK SMALL LETTER SAN */ }, \
+ { 0x03F7, /* GREEK CAPITAL LETTER SHO */ \
+ 0x03F8, /* GREEK SMALL LETTER SHO */ }, \
+ { 0x03A3, /* GREEK CAPITAL LETTER SIGMA */ \
+ 0x03C3, /* GREEK SMALL LETTER SIGMA */ }, \
+ { 0x03A4, /* GREEK CAPITAL LETTER TAU */ \
+ 0x03C4, /* GREEK SMALL LETTER TAU */ }, \
+ { 0x0398, /* GREEK CAPITAL LETTER THETA */ \
+ 0x03B8, /* GREEK SMALL LETTER THETA */ }, \
+ { 0x03A5, /* GREEK CAPITAL LETTER UPSILON */ \
+ 0x03C5, /* GREEK SMALL LETTER UPSILON */ }, \
+ { 0x1F59, /* GREEK CAPITAL LETTER UPSILON WITH DASIA */ \
+ 0x1F51, /* GREEK SMALL LETTER UPSILON WITH DASIA */ }, \
+ { 0x1F5D, /* GREEK CAPITAL LETTER UPSILON WITH DASIA AND OXIA */ \
+ 0x1F55, /* GREEK SMALL LETTER UPSILON WITH DASIA AND OXIA */ }, \
+ { 0x1F5F, /* GREEK CAPITAL LETTER UPSILON WITH DASIA AND PERISPOMENI */ \
+ 0x1F57, /* GREEK SMALL LETTER UPSILON WITH DASIA AND PERISPOMENI */ }, \
+ { 0x1F5B, /* GREEK CAPITAL LETTER UPSILON WITH DASIA AND VARIA */ \
+ 0x1F53, /* GREEK SMALL LETTER UPSILON WITH DASIA AND VARIA */ }, \
+ { 0x03AB, /* GREEK CAPITAL LETTER UPSILON WITH DIALYTIKA */ \
+ 0x03CB, /* GREEK SMALL LETTER UPSILON WITH DIALYTIKA */ }, \
+ { 0x1FE9, /* GREEK CAPITAL LETTER UPSILON WITH MACRON */ \
+ 0x1FE1, /* GREEK SMALL LETTER UPSILON WITH MACRON */ }, \
+ { 0x1FEB, /* GREEK CAPITAL LETTER UPSILON WITH OXIA */ \
+ 0x1F7B, /* GREEK SMALL LETTER UPSILON WITH OXIA */ }, \
+ { 0x038E, /* GREEK CAPITAL LETTER UPSILON WITH TONOS */ \
+ 0x03CD, /* GREEK SMALL LETTER UPSILON WITH TONOS */ }, \
+ { 0x1FEA, /* GREEK CAPITAL LETTER UPSILON WITH VARIA */ \
+ 0x1F7A, /* GREEK SMALL LETTER UPSILON WITH VARIA */ }, \
+ { 0x1FE8, /* GREEK CAPITAL LETTER UPSILON WITH VRACHY */ \
+ 0x1FE0, /* GREEK SMALL LETTER UPSILON WITH VRACHY */ }, \
+ { 0x039E, /* GREEK CAPITAL LETTER XI */ \
+ 0x03BE, /* GREEK SMALL LETTER XI */ }, \
+ { 0x0396, /* GREEK CAPITAL LETTER ZETA */ \
+ 0x03B6, /* GREEK SMALL LETTER ZETA */ }, \
+ { 0x0041, /* LATIN CAPITAL LETTER A */ \
+ 0x0061, /* LATIN SMALL LETTER A */ }, \
+ { 0x00C1, /* LATIN CAPITAL LETTER A WITH ACUTE */ \
+ 0x00E1, /* LATIN SMALL LETTER A WITH ACUTE */ }, \
+ { 0x0102, /* LATIN CAPITAL LETTER A WITH BREVE */ \
+ 0x0103, /* LATIN SMALL LETTER A WITH BREVE */ }, \
+ { 0x1EAE, /* LATIN CAPITAL LETTER A WITH BREVE AND ACUTE */ \
+ 0x1EAF, /* LATIN SMALL LETTER A WITH BREVE AND ACUTE */ }, \
+ { 0x1EB6, /* LATIN CAPITAL LETTER A WITH BREVE AND DOT BELOW */ \
+ 0x1EB7, /* LATIN SMALL LETTER A WITH BREVE AND DOT BELOW */ }, \
+ { 0x1EB0, /* LATIN CAPITAL LETTER A WITH BREVE AND GRAVE */ \
+ 0x1EB1, /* LATIN SMALL LETTER A WITH BREVE AND GRAVE */ }, \
+ { 0x1EB2, /* LATIN CAPITAL LETTER A WITH BREVE AND HOOK ABOVE */ \
+ 0x1EB3, /* LATIN SMALL LETTER A WITH BREVE AND HOOK ABOVE */ }, \
+ { 0x1EB4, /* LATIN CAPITAL LETTER A WITH BREVE AND TILDE */ \
+ 0x1EB5, /* LATIN SMALL LETTER A WITH BREVE AND TILDE */ }, \
+ { 0x01CD, /* LATIN CAPITAL LETTER A WITH CARON */ \
+ 0x01CE, /* LATIN SMALL LETTER A WITH CARON */ }, \
+ { 0x00C2, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX */ \
+ 0x00E2, /* LATIN SMALL LETTER A WITH CIRCUMFLEX */ }, \
+ { 0x1EA4, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND ACUTE */ \
+ 0x1EA5, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND ACUTE */ }, \
+ { 0x1EAC, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND DOT BELOW */ \
+ 0x1EAD, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND DOT BELOW */ }, \
+ { 0x1EA6, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND GRAVE */ \
+ 0x1EA7, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND GRAVE */ }, \
+ { 0x1EA8, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND HOOK ABOVE */ \
+ 0x1EA9, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND HOOK ABOVE */ }, \
+ { 0x1EAA, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND TILDE */ \
+ 0x1EAB, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND TILDE */ }, \
+ { 0x00C4, /* LATIN CAPITAL LETTER A WITH DIAERESIS */ \
+ 0x00E4, /* LATIN SMALL LETTER A WITH DIAERESIS */ }, \
+ { 0x01DE, /* LATIN CAPITAL LETTER A WITH DIAERESIS AND MACRON */ \
+ 0x01DF, /* LATIN SMALL LETTER A WITH DIAERESIS AND MACRON */ }, \
+ { 0x0226, /* LATIN CAPITAL LETTER A WITH DOT ABOVE */ \
+ 0x0227, /* LATIN SMALL LETTER A WITH DOT ABOVE */ }, \
+ { 0x01E0, /* LATIN CAPITAL LETTER A WITH DOT ABOVE AND MACRON */ \
+ 0x01E1, /* LATIN SMALL LETTER A WITH DOT ABOVE AND MACRON */ }, \
+ { 0x1EA0, /* LATIN CAPITAL LETTER A WITH DOT BELOW */ \
+ 0x1EA1, /* LATIN SMALL LETTER A WITH DOT BELOW */ }, \
+ { 0x0200, /* LATIN CAPITAL LETTER A WITH DOUBLE GRAVE */ \
+ 0x0201, /* LATIN SMALL LETTER A WITH DOUBLE GRAVE */ }, \
+ { 0x00C0, /* LATIN CAPITAL LETTER A WITH GRAVE */ \
+ 0x00E0, /* LATIN SMALL LETTER A WITH GRAVE */ }, \
+ { 0x1EA2, /* LATIN CAPITAL LETTER A WITH HOOK ABOVE */ \
+ 0x1EA3, /* LATIN SMALL LETTER A WITH HOOK ABOVE */ }, \
+ { 0x0202, /* LATIN CAPITAL LETTER A WITH INVERTED BREVE */ \
+ 0x0203, /* LATIN SMALL LETTER A WITH INVERTED BREVE */ }, \
+ { 0x0100, /* LATIN CAPITAL LETTER A WITH MACRON */ \
+ 0x0101, /* LATIN SMALL LETTER A WITH MACRON */ }, \
+ { 0x0104, /* LATIN CAPITAL LETTER A WITH OGONEK */ \
+ 0x0105, /* LATIN SMALL LETTER A WITH OGONEK */ }, \
+ { 0x00C5, /* LATIN CAPITAL LETTER A WITH RING ABOVE */ \
+ 0x00E5, /* LATIN SMALL LETTER A WITH RING ABOVE */ }, \
+ { 0x01FA, /* LATIN CAPITAL LETTER A WITH RING ABOVE AND ACUTE */ \
+ 0x01FB, /* LATIN SMALL LETTER A WITH RING ABOVE AND ACUTE */ }, \
+ { 0x1E00, /* LATIN CAPITAL LETTER A WITH RING BELOW */ \
+ 0x1E01, /* LATIN SMALL LETTER A WITH RING BELOW */ }, \
+ { 0x023A, /* LATIN CAPITAL LETTER A WITH STROKE */ \
+ 0x2C65, /* LATIN SMALL LETTER A WITH STROKE */ }, \
+ { 0x00C3, /* LATIN CAPITAL LETTER A WITH TILDE */ \
+ 0x00E3, /* LATIN SMALL LETTER A WITH TILDE */ }, \
+ { 0xA732, /* LATIN CAPITAL LETTER AA */ \
+ 0xA733, /* LATIN SMALL LETTER AA */ }, \
+ { 0x00C6, /* LATIN CAPITAL LETTER AE */ \
+ 0x00E6, /* LATIN SMALL LETTER AE */ }, \
+ { 0x01FC, /* LATIN CAPITAL LETTER AE WITH ACUTE */ \
+ 0x01FD, /* LATIN SMALL LETTER AE WITH ACUTE */ }, \
+ { 0x01E2, /* LATIN CAPITAL LETTER AE WITH MACRON */ \
+ 0x01E3, /* LATIN SMALL LETTER AE WITH MACRON */ }, \
+ { 0x2C6D, /* LATIN CAPITAL LETTER ALPHA */ \
+ 0x0251, /* LATIN SMALL LETTER ALPHA */ }, \
+ { 0xA734, /* LATIN CAPITAL LETTER AO */ \
+ 0xA735, /* LATIN SMALL LETTER AO */ }, \
+ { 0xA736, /* LATIN CAPITAL LETTER AU */ \
+ 0xA737, /* LATIN SMALL LETTER AU */ }, \
+ { 0xA738, /* LATIN CAPITAL LETTER AV */ \
+ 0xA739, /* LATIN SMALL LETTER AV */ }, \
+ { 0xA73A, /* LATIN CAPITAL LETTER AV WITH HORIZONTAL BAR */ \
+ 0xA73B, /* LATIN SMALL LETTER AV WITH HORIZONTAL BAR */ }, \
+ { 0xA73C, /* LATIN CAPITAL LETTER AY */ \
+ 0xA73D, /* LATIN SMALL LETTER AY */ }, \
+ { 0x0042, /* LATIN CAPITAL LETTER B */ \
+ 0x0062, /* LATIN SMALL LETTER B */ }, \
+ { 0x1E02, /* LATIN CAPITAL LETTER B WITH DOT ABOVE */ \
+ 0x1E03, /* LATIN SMALL LETTER B WITH DOT ABOVE */ }, \
+ { 0x1E04, /* LATIN CAPITAL LETTER B WITH DOT BELOW */ \
+ 0x1E05, /* LATIN SMALL LETTER B WITH DOT BELOW */ }, \
+ { 0xA796, /* LATIN CAPITAL LETTER B WITH FLOURISH */ \
+ 0xA797, /* LATIN SMALL LETTER B WITH FLOURISH */ }, \
+ { 0x0181, /* LATIN CAPITAL LETTER B WITH HOOK */ \
+ 0x0253, /* LATIN SMALL LETTER B WITH HOOK */ }, \
+ { 0x1E06, /* LATIN CAPITAL LETTER B WITH LINE BELOW */ \
+ 0x1E07, /* LATIN SMALL LETTER B WITH LINE BELOW */ }, \
+ { 0x0243, /* LATIN CAPITAL LETTER B WITH STROKE */ \
+ 0x0180, /* LATIN SMALL LETTER B WITH STROKE */ }, \
+ { 0x0182, /* LATIN CAPITAL LETTER B WITH TOPBAR */ \
+ 0x0183, /* LATIN SMALL LETTER B WITH TOPBAR */ }, \
+ { 0xA7B4, /* LATIN CAPITAL LETTER BETA */ \
+ 0xA7B5, /* LATIN SMALL LETTER BETA */ }, \
+ { 0xA746, /* LATIN CAPITAL LETTER BROKEN L */ \
+ 0xA747, /* LATIN SMALL LETTER BROKEN L */ }, \
+ { 0x0043, /* LATIN CAPITAL LETTER C */ \
+ 0x0063, /* LATIN SMALL LETTER C */ }, \
+ { 0x0106, /* LATIN CAPITAL LETTER C WITH ACUTE */ \
+ 0x0107, /* LATIN SMALL LETTER C WITH ACUTE */ }, \
+ { 0xA792, /* LATIN CAPITAL LETTER C WITH BAR */ \
+ 0xA793, /* LATIN SMALL LETTER C WITH BAR */ }, \
+ { 0x010C, /* LATIN CAPITAL LETTER C WITH CARON */ \
+ 0x010D, /* LATIN SMALL LETTER C WITH CARON */ }, \
+ { 0x00C7, /* LATIN CAPITAL LETTER C WITH CEDILLA */ \
+ 0x00E7, /* LATIN SMALL LETTER C WITH CEDILLA */ }, \
+ { 0x1E08, /* LATIN CAPITAL LETTER C WITH CEDILLA AND ACUTE */ \
+ 0x1E09, /* LATIN SMALL LETTER C WITH CEDILLA AND ACUTE */ }, \
+ { 0x0108, /* LATIN CAPITAL LETTER C WITH CIRCUMFLEX */ \
+ 0x0109, /* LATIN SMALL LETTER C WITH CIRCUMFLEX */ }, \
+ { 0x010A, /* LATIN CAPITAL LETTER C WITH DOT ABOVE */ \
+ 0x010B, /* LATIN SMALL LETTER C WITH DOT ABOVE */ }, \
+ { 0x0187, /* LATIN CAPITAL LETTER C WITH HOOK */ \
+ 0x0188, /* LATIN SMALL LETTER C WITH HOOK */ }, \
+ { 0x023B, /* LATIN CAPITAL LETTER C WITH STROKE */ \
+ 0x023C, /* LATIN SMALL LETTER C WITH STROKE */ }, \
+ { 0xA7B3, /* LATIN CAPITAL LETTER CHI */ \
+ 0xAB53, /* LATIN SMALL LETTER CHI */ }, \
+ { 0xA76E, /* LATIN CAPITAL LETTER CON */ \
+ 0xA76F, /* LATIN SMALL LETTER CON */ }, \
+ { 0xA72C, /* LATIN CAPITAL LETTER CUATRILLO */ \
+ 0xA72D, /* LATIN SMALL LETTER CUATRILLO */ }, \
+ { 0xA72E, /* LATIN CAPITAL LETTER CUATRILLO WITH COMMA */ \
+ 0xA72F, /* LATIN SMALL LETTER CUATRILLO WITH COMMA */ }, \
+ { 0x0044, /* LATIN CAPITAL LETTER D */ \
+ 0x0064, /* LATIN SMALL LETTER D */ }, \
+ { 0x010E, /* LATIN CAPITAL LETTER D WITH CARON */ \
+ 0x010F, /* LATIN SMALL LETTER D WITH CARON */ }, \
+ { 0x1E10, /* LATIN CAPITAL LETTER D WITH CEDILLA */ \
+ 0x1E11, /* LATIN SMALL LETTER D WITH CEDILLA */ }, \
+ { 0x1E12, /* LATIN CAPITAL LETTER D WITH CIRCUMFLEX BELOW */ \
+ 0x1E13, /* LATIN SMALL LETTER D WITH CIRCUMFLEX BELOW */ }, \
+ { 0x1E0A, /* LATIN CAPITAL LETTER D WITH DOT ABOVE */ \
+ 0x1E0B, /* LATIN SMALL LETTER D WITH DOT ABOVE */ }, \
+ { 0x1E0C, /* LATIN CAPITAL LETTER D WITH DOT BELOW */ \
+ 0x1E0D, /* LATIN SMALL LETTER D WITH DOT BELOW */ }, \
+ { 0x018A, /* LATIN CAPITAL LETTER D WITH HOOK */ \
+ 0x0257, /* LATIN SMALL LETTER D WITH HOOK */ }, \
+ { 0x1E0E, /* LATIN CAPITAL LETTER D WITH LINE BELOW */ \
+ 0x1E0F, /* LATIN SMALL LETTER D WITH LINE BELOW */ }, \
+ { 0x0110, /* LATIN CAPITAL LETTER D WITH STROKE */ \
+ 0x0111, /* LATIN SMALL LETTER D WITH STROKE */ }, \
+ { 0x018B, /* LATIN CAPITAL LETTER D WITH TOPBAR */ \
+ 0x018C, /* LATIN SMALL LETTER D WITH TOPBAR */ }, \
+ { 0x01F1, /* LATIN CAPITAL LETTER DZ */ \
+ 0x01F3, /* LATIN SMALL LETTER DZ */ }, \
+ { 0x01C4, /* LATIN CAPITAL LETTER DZ WITH CARON */ \
+ 0x01C6, /* LATIN SMALL LETTER DZ WITH CARON */ }, \
+ { 0x0045, /* LATIN CAPITAL LETTER E */ \
+ 0x0065, /* LATIN SMALL LETTER E */ }, \
+ { 0x00C9, /* LATIN CAPITAL LETTER E WITH ACUTE */ \
+ 0x00E9, /* LATIN SMALL LETTER E WITH ACUTE */ }, \
+ { 0x0114, /* LATIN CAPITAL LETTER E WITH BREVE */ \
+ 0x0115, /* LATIN SMALL LETTER E WITH BREVE */ }, \
+ { 0x011A, /* LATIN CAPITAL LETTER E WITH CARON */ \
+ 0x011B, /* LATIN SMALL LETTER E WITH CARON */ }, \
+ { 0x0228, /* LATIN CAPITAL LETTER E WITH CEDILLA */ \
+ 0x0229, /* LATIN SMALL LETTER E WITH CEDILLA */ }, \
+ { 0x1E1C, /* LATIN CAPITAL LETTER E WITH CEDILLA AND BREVE */ \
+ 0x1E1D, /* LATIN SMALL LETTER E WITH CEDILLA AND BREVE */ }, \
+ { 0x00CA, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX */ \
+ 0x00EA, /* LATIN SMALL LETTER E WITH CIRCUMFLEX */ }, \
+ { 0x1EBE, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND ACUTE */ \
+ 0x1EBF, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND ACUTE */ }, \
+ { 0x1EC6, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND DOT BELOW */ \
+ 0x1EC7, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND DOT BELOW */ }, \
+ { 0x1EC0, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND GRAVE */ \
+ 0x1EC1, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND GRAVE */ }, \
+ { 0x1EC2, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND HOOK ABOVE */ \
+ 0x1EC3, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND HOOK ABOVE */ }, \
+ { 0x1EC4, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND TILDE */ \
+ 0x1EC5, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND TILDE */ }, \
+ { 0x1E18, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX BELOW */ \
+ 0x1E19, /* LATIN SMALL LETTER E WITH CIRCUMFLEX BELOW */ }, \
+ { 0x00CB, /* LATIN CAPITAL LETTER E WITH DIAERESIS */ \
+ 0x00EB, /* LATIN SMALL LETTER E WITH DIAERESIS */ }, \
+ { 0x0116, /* LATIN CAPITAL LETTER E WITH DOT ABOVE */ \
+ 0x0117, /* LATIN SMALL LETTER E WITH DOT ABOVE */ }, \
+ { 0x1EB8, /* LATIN CAPITAL LETTER E WITH DOT BELOW */ \
+ 0x1EB9, /* LATIN SMALL LETTER E WITH DOT BELOW */ }, \
+ { 0x0204, /* LATIN CAPITAL LETTER E WITH DOUBLE GRAVE */ \
+ 0x0205, /* LATIN SMALL LETTER E WITH DOUBLE GRAVE */ }, \
+ { 0x00C8, /* LATIN CAPITAL LETTER E WITH GRAVE */ \
+ 0x00E8, /* LATIN SMALL LETTER E WITH GRAVE */ }, \
+ { 0x1EBA, /* LATIN CAPITAL LETTER E WITH HOOK ABOVE */ \
+ 0x1EBB, /* LATIN SMALL LETTER E WITH HOOK ABOVE */ }, \
+ { 0x0206, /* LATIN CAPITAL LETTER E WITH INVERTED BREVE */ \
+ 0x0207, /* LATIN SMALL LETTER E WITH INVERTED BREVE */ }, \
+ { 0x0112, /* LATIN CAPITAL LETTER E WITH MACRON */ \
+ 0x0113, /* LATIN SMALL LETTER E WITH MACRON */ }, \
+ { 0x1E16, /* LATIN CAPITAL LETTER E WITH MACRON AND ACUTE */ \
+ 0x1E17, /* LATIN SMALL LETTER E WITH MACRON AND ACUTE */ }, \
+ { 0x1E14, /* LATIN CAPITAL LETTER E WITH MACRON AND GRAVE */ \
+ 0x1E15, /* LATIN SMALL LETTER E WITH MACRON AND GRAVE */ }, \
+ { 0x0118, /* LATIN CAPITAL LETTER E WITH OGONEK */ \
+ 0x0119, /* LATIN SMALL LETTER E WITH OGONEK */ }, \
+ { 0x0246, /* LATIN CAPITAL LETTER E WITH STROKE */ \
+ 0x0247, /* LATIN SMALL LETTER E WITH STROKE */ }, \
+ { 0x1EBC, /* LATIN CAPITAL LETTER E WITH TILDE */ \
+ 0x1EBD, /* LATIN SMALL LETTER E WITH TILDE */ }, \
+ { 0x1E1A, /* LATIN CAPITAL LETTER E WITH TILDE BELOW */ \
+ 0x1E1B, /* LATIN SMALL LETTER E WITH TILDE BELOW */ }, \
+ { 0xA724, /* LATIN CAPITAL LETTER EGYPTOLOGICAL AIN */ \
+ 0xA725, /* LATIN SMALL LETTER EGYPTOLOGICAL AIN */ }, \
+ { 0xA722, /* LATIN CAPITAL LETTER EGYPTOLOGICAL ALEF */ \
+ 0xA723, /* LATIN SMALL LETTER EGYPTOLOGICAL ALEF */ }, \
+ { 0x014A, /* LATIN CAPITAL LETTER ENG */ \
+ 0x014B, /* LATIN SMALL LETTER ENG */ }, \
+ { 0x01A9, /* LATIN CAPITAL LETTER ESH */ \
+ 0x0283, /* LATIN SMALL LETTER ESH */ }, \
+ { 0xA76A, /* LATIN CAPITAL LETTER ET */ \
+ 0xA76B, /* LATIN SMALL LETTER ET */ }, \
+ { 0x00D0, /* LATIN CAPITAL LETTER ETH */ \
+ 0x00F0, /* LATIN SMALL LETTER ETH */ }, \
+ { 0x01B7, /* LATIN CAPITAL LETTER EZH */ \
+ 0x0292, /* LATIN SMALL LETTER EZH */ }, \
+ { 0x01B8, /* LATIN CAPITAL LETTER EZH REVERSED */ \
+ 0x01B9, /* LATIN SMALL LETTER EZH REVERSED */ }, \
+ { 0x01EE, /* LATIN CAPITAL LETTER EZH WITH CARON */ \
+ 0x01EF, /* LATIN SMALL LETTER EZH WITH CARON */ }, \
+ { 0x0046, /* LATIN CAPITAL LETTER F */ \
+ 0x0066, /* LATIN SMALL LETTER F */ }, \
+ { 0x1E1E, /* LATIN CAPITAL LETTER F WITH DOT ABOVE */ \
+ 0x1E1F, /* LATIN SMALL LETTER F WITH DOT ABOVE */ }, \
+ { 0x0191, /* LATIN CAPITAL LETTER F WITH HOOK */ \
+ 0x0192, /* LATIN SMALL LETTER F WITH HOOK */ }, \
+ { 0xA798, /* LATIN CAPITAL LETTER F WITH STROKE */ \
+ 0xA799, /* LATIN SMALL LETTER F WITH STROKE */ }, \
+ { 0x0047, /* LATIN CAPITAL LETTER G */ \
+ 0x0067, /* LATIN SMALL LETTER G */ }, \
+ { 0x01F4, /* LATIN CAPITAL LETTER G WITH ACUTE */ \
+ 0x01F5, /* LATIN SMALL LETTER G WITH ACUTE */ }, \
+ { 0x011E, /* LATIN CAPITAL LETTER G WITH BREVE */ \
+ 0x011F, /* LATIN SMALL LETTER G WITH BREVE */ }, \
+ { 0x01E6, /* LATIN CAPITAL LETTER G WITH CARON */ \
+ 0x01E7, /* LATIN SMALL LETTER G WITH CARON */ }, \
+ { 0x0122, /* LATIN CAPITAL LETTER G WITH CEDILLA */ \
+ 0x0123, /* LATIN SMALL LETTER G WITH CEDILLA */ }, \
+ { 0x011C, /* LATIN CAPITAL LETTER G WITH CIRCUMFLEX */ \
+ 0x011D, /* LATIN SMALL LETTER G WITH CIRCUMFLEX */ }, \
+ { 0x0120, /* LATIN CAPITAL LETTER G WITH DOT ABOVE */ \
+ 0x0121, /* LATIN SMALL LETTER G WITH DOT ABOVE */ }, \
+ { 0x0193, /* LATIN CAPITAL LETTER G WITH HOOK */ \
+ 0x0260, /* LATIN SMALL LETTER G WITH HOOK */ }, \
+ { 0x1E20, /* LATIN CAPITAL LETTER G WITH MACRON */ \
+ 0x1E21, /* LATIN SMALL LETTER G WITH MACRON */ }, \
+ { 0xA7A0, /* LATIN CAPITAL LETTER G WITH OBLIQUE STROKE */ \
+ 0xA7A1, /* LATIN SMALL LETTER G WITH OBLIQUE STROKE */ }, \
+ { 0x01E4, /* LATIN CAPITAL LETTER G WITH STROKE */ \
+ 0x01E5, /* LATIN SMALL LETTER G WITH STROKE */ }, \
+ { 0x0194, /* LATIN CAPITAL LETTER GAMMA */ \
+ 0x0263, /* LATIN SMALL LETTER GAMMA */ }, \
+ { 0x0241, /* LATIN CAPITAL LETTER GLOTTAL STOP */ \
+ 0x0242, /* LATIN SMALL LETTER GLOTTAL STOP */ }, \
+ { 0x0048, /* LATIN CAPITAL LETTER H */ \
+ 0x0068, /* LATIN SMALL LETTER H */ }, \
+ { 0x1E2A, /* LATIN CAPITAL LETTER H WITH BREVE BELOW */ \
+ 0x1E2B, /* LATIN SMALL LETTER H WITH BREVE BELOW */ }, \
+ { 0x021E, /* LATIN CAPITAL LETTER H WITH CARON */ \
+ 0x021F, /* LATIN SMALL LETTER H WITH CARON */ }, \
+ { 0x1E28, /* LATIN CAPITAL LETTER H WITH CEDILLA */ \
+ 0x1E29, /* LATIN SMALL LETTER H WITH CEDILLA */ }, \
+ { 0x0124, /* LATIN CAPITAL LETTER H WITH CIRCUMFLEX */ \
+ 0x0125, /* LATIN SMALL LETTER H WITH CIRCUMFLEX */ }, \
+ { 0x2C67, /* LATIN CAPITAL LETTER H WITH DESCENDER */ \
+ 0x2C68, /* LATIN SMALL LETTER H WITH DESCENDER */ }, \
+ { 0x1E26, /* LATIN CAPITAL LETTER H WITH DIAERESIS */ \
+ 0x1E27, /* LATIN SMALL LETTER H WITH DIAERESIS */ }, \
+ { 0x1E22, /* LATIN CAPITAL LETTER H WITH DOT ABOVE */ \
+ 0x1E23, /* LATIN SMALL LETTER H WITH DOT ABOVE */ }, \
+ { 0x1E24, /* LATIN CAPITAL LETTER H WITH DOT BELOW */ \
+ 0x1E25, /* LATIN SMALL LETTER H WITH DOT BELOW */ }, \
+ { 0xA7AA, /* LATIN CAPITAL LETTER H WITH HOOK */ \
+ 0x0266, /* LATIN SMALL LETTER H WITH HOOK */ }, \
+ { 0x0126, /* LATIN CAPITAL LETTER H WITH STROKE */ \
+ 0x0127, /* LATIN SMALL LETTER H WITH STROKE */ }, \
+ { 0x2C75, /* LATIN CAPITAL LETTER HALF H */ \
+ 0x2C76, /* LATIN SMALL LETTER HALF H */ }, \
+ { 0xA726, /* LATIN CAPITAL LETTER HENG */ \
+ 0xA727, /* LATIN SMALL LETTER HENG */ }, \
+ { 0x0049, /* LATIN CAPITAL LETTER I */ \
+ 0x0069, /* LATIN SMALL LETTER I */ }, \
+ { 0x00CD, /* LATIN CAPITAL LETTER I WITH ACUTE */ \
+ 0x00ED, /* LATIN SMALL LETTER I WITH ACUTE */ }, \
+ { 0x012C, /* LATIN CAPITAL LETTER I WITH BREVE */ \
+ 0x012D, /* LATIN SMALL LETTER I WITH BREVE */ }, \
+ { 0x01CF, /* LATIN CAPITAL LETTER I WITH CARON */ \
+ 0x01D0, /* LATIN SMALL LETTER I WITH CARON */ }, \
+ { 0x00CE, /* LATIN CAPITAL LETTER I WITH CIRCUMFLEX */ \
+ 0x00EE, /* LATIN SMALL LETTER I WITH CIRCUMFLEX */ }, \
+ { 0x00CF, /* LATIN CAPITAL LETTER I WITH DIAERESIS */ \
+ 0x00EF, /* LATIN SMALL LETTER I WITH DIAERESIS */ }, \
+ { 0x1E2E, /* LATIN CAPITAL LETTER I WITH DIAERESIS AND ACUTE */ \
+ 0x1E2F, /* LATIN SMALL LETTER I WITH DIAERESIS AND ACUTE */ }, \
+ { 0x1ECA, /* LATIN CAPITAL LETTER I WITH DOT BELOW */ \
+ 0x1ECB, /* LATIN SMALL LETTER I WITH DOT BELOW */ }, \
+ { 0x0208, /* LATIN CAPITAL LETTER I WITH DOUBLE GRAVE */ \
+ 0x0209, /* LATIN SMALL LETTER I WITH DOUBLE GRAVE */ }, \
+ { 0x00CC, /* LATIN CAPITAL LETTER I WITH GRAVE */ \
+ 0x00EC, /* LATIN SMALL LETTER I WITH GRAVE */ }, \
+ { 0x1EC8, /* LATIN CAPITAL LETTER I WITH HOOK ABOVE */ \
+ 0x1EC9, /* LATIN SMALL LETTER I WITH HOOK ABOVE */ }, \
+ { 0x020A, /* LATIN CAPITAL LETTER I WITH INVERTED BREVE */ \
+ 0x020B, /* LATIN SMALL LETTER I WITH INVERTED BREVE */ }, \
+ { 0x012A, /* LATIN CAPITAL LETTER I WITH MACRON */ \
+ 0x012B, /* LATIN SMALL LETTER I WITH MACRON */ }, \
+ { 0x012E, /* LATIN CAPITAL LETTER I WITH OGONEK */ \
+ 0x012F, /* LATIN SMALL LETTER I WITH OGONEK */ }, \
+ { 0x0197, /* LATIN CAPITAL LETTER I WITH STROKE */ \
+ 0x0268, /* LATIN SMALL LETTER I WITH STROKE */ }, \
+ { 0x0128, /* LATIN CAPITAL LETTER I WITH TILDE */ \
+ 0x0129, /* LATIN SMALL LETTER I WITH TILDE */ }, \
+ { 0x1E2C, /* LATIN CAPITAL LETTER I WITH TILDE BELOW */ \
+ 0x1E2D, /* LATIN SMALL LETTER I WITH TILDE BELOW */ }, \
+ { 0xA779, /* LATIN CAPITAL LETTER INSULAR D */ \
+ 0xA77A, /* LATIN SMALL LETTER INSULAR D */ }, \
+ { 0xA77B, /* LATIN CAPITAL LETTER INSULAR F */ \
+ 0xA77C, /* LATIN SMALL LETTER INSULAR F */ }, \
+ { 0xA77D, /* LATIN CAPITAL LETTER INSULAR G */ \
+ 0x1D79, /* LATIN SMALL LETTER INSULAR G */ }, \
+ { 0xA782, /* LATIN CAPITAL LETTER INSULAR R */ \
+ 0xA783, /* LATIN SMALL LETTER INSULAR R */ }, \
+ { 0xA784, /* LATIN CAPITAL LETTER INSULAR S */ \
+ 0xA785, /* LATIN SMALL LETTER INSULAR S */ }, \
+ { 0xA786, /* LATIN CAPITAL LETTER INSULAR T */ \
+ 0xA787, /* LATIN SMALL LETTER INSULAR T */ }, \
+ { 0x0196, /* LATIN CAPITAL LETTER IOTA */ \
+ 0x0269, /* LATIN SMALL LETTER IOTA */ }, \
+ { 0xA76C, /* LATIN CAPITAL LETTER IS */ \
+ 0xA76D, /* LATIN SMALL LETTER IS */ }, \
+ { 0x004A, /* LATIN CAPITAL LETTER J */ \
+ 0x006A, /* LATIN SMALL LETTER J */ }, \
+ { 0x0134, /* LATIN CAPITAL LETTER J WITH CIRCUMFLEX */ \
+ 0x0135, /* LATIN SMALL LETTER J WITH CIRCUMFLEX */ }, \
+ { 0xA7B2, /* LATIN CAPITAL LETTER J WITH CROSSED-TAIL */ \
+ 0x029D, /* LATIN SMALL LETTER J WITH CROSSED-TAIL */ }, \
+ { 0x0248, /* LATIN CAPITAL LETTER J WITH STROKE */ \
+ 0x0249, /* LATIN SMALL LETTER J WITH STROKE */ }, \
+ { 0x004B, /* LATIN CAPITAL LETTER K */ \
+ 0x006B, /* LATIN SMALL LETTER K */ }, \
+ { 0x1E30, /* LATIN CAPITAL LETTER K WITH ACUTE */ \
+ 0x1E31, /* LATIN SMALL LETTER K WITH ACUTE */ }, \
+ { 0x01E8, /* LATIN CAPITAL LETTER K WITH CARON */ \
+ 0x01E9, /* LATIN SMALL LETTER K WITH CARON */ }, \
+ { 0x0136, /* LATIN CAPITAL LETTER K WITH CEDILLA */ \
+ 0x0137, /* LATIN SMALL LETTER K WITH CEDILLA */ }, \
+ { 0x2C69, /* LATIN CAPITAL LETTER K WITH DESCENDER */ \
+ 0x2C6A, /* LATIN SMALL LETTER K WITH DESCENDER */ }, \
+ { 0xA742, /* LATIN CAPITAL LETTER K WITH DIAGONAL STROKE */ \
+ 0xA743, /* LATIN SMALL LETTER K WITH DIAGONAL STROKE */ }, \
+ { 0x1E32, /* LATIN CAPITAL LETTER K WITH DOT BELOW */ \
+ 0x1E33, /* LATIN SMALL LETTER K WITH DOT BELOW */ }, \
+ { 0x0198, /* LATIN CAPITAL LETTER K WITH HOOK */ \
+ 0x0199, /* LATIN SMALL LETTER K WITH HOOK */ }, \
+ { 0x1E34, /* LATIN CAPITAL LETTER K WITH LINE BELOW */ \
+ 0x1E35, /* LATIN SMALL LETTER K WITH LINE BELOW */ }, \
+ { 0xA7A2, /* LATIN CAPITAL LETTER K WITH OBLIQUE STROKE */ \
+ 0xA7A3, /* LATIN SMALL LETTER K WITH OBLIQUE STROKE */ }, \
+ { 0xA740, /* LATIN CAPITAL LETTER K WITH STROKE */ \
+ 0xA741, /* LATIN SMALL LETTER K WITH STROKE */ }, \
+ { 0xA744, /* LATIN CAPITAL LETTER K WITH STROKE AND DIAGONAL STROKE */ \
+ 0xA745, /* LATIN SMALL LETTER K WITH STROKE AND DIAGONAL STROKE */ }, \
+ { 0x004C, /* LATIN CAPITAL LETTER L */ \
+ 0x006C, /* LATIN SMALL LETTER L */ }, \
+ { 0x0139, /* LATIN CAPITAL LETTER L WITH ACUTE */ \
+ 0x013A, /* LATIN SMALL LETTER L WITH ACUTE */ }, \
+ { 0x023D, /* LATIN CAPITAL LETTER L WITH BAR */ \
+ 0x019A, /* LATIN SMALL LETTER L WITH BAR */ }, \
+ { 0xA7AD, /* LATIN CAPITAL LETTER L WITH BELT */ \
+ 0x026C, /* LATIN SMALL LETTER L WITH BELT */ }, \
+ { 0x013D, /* LATIN CAPITAL LETTER L WITH CARON */ \
+ 0x013E, /* LATIN SMALL LETTER L WITH CARON */ }, \
+ { 0x013B, /* LATIN CAPITAL LETTER L WITH CEDILLA */ \
+ 0x013C, /* LATIN SMALL LETTER L WITH CEDILLA */ }, \
+ { 0x1E3C, /* LATIN CAPITAL LETTER L WITH CIRCUMFLEX BELOW */ \
+ 0x1E3D, /* LATIN SMALL LETTER L WITH CIRCUMFLEX BELOW */ }, \
+ { 0x1E36, /* LATIN CAPITAL LETTER L WITH DOT BELOW */ \
+ 0x1E37, /* LATIN SMALL LETTER L WITH DOT BELOW */ }, \
+ { 0x1E38, /* LATIN CAPITAL LETTER L WITH DOT BELOW AND MACRON */ \
+ 0x1E39, /* LATIN SMALL LETTER L WITH DOT BELOW AND MACRON */ }, \
+ { 0x2C60, /* LATIN CAPITAL LETTER L WITH DOUBLE BAR */ \
+ 0x2C61, /* LATIN SMALL LETTER L WITH DOUBLE BAR */ }, \
+ { 0xA748, /* LATIN CAPITAL LETTER L WITH HIGH STROKE */ \
+ 0xA749, /* LATIN SMALL LETTER L WITH HIGH STROKE */ }, \
+ { 0x1E3A, /* LATIN CAPITAL LETTER L WITH LINE BELOW */ \
+ 0x1E3B, /* LATIN SMALL LETTER L WITH LINE BELOW */ }, \
+ { 0x013F, /* LATIN CAPITAL LETTER L WITH MIDDLE DOT */ \
+ 0x0140, /* LATIN SMALL LETTER L WITH MIDDLE DOT */ }, \
+ { 0x2C62, /* LATIN CAPITAL LETTER L WITH MIDDLE TILDE */ \
+ 0x026B, /* LATIN SMALL LETTER L WITH MIDDLE TILDE */ }, \
+ { 0x0141, /* LATIN CAPITAL LETTER L WITH STROKE */ \
+ 0x0142, /* LATIN SMALL LETTER L WITH STROKE */ }, \
+ { 0x01C7, /* LATIN CAPITAL LETTER LJ */ \
+ 0x01C9, /* LATIN SMALL LETTER LJ */ }, \
+ { 0x004D, /* LATIN CAPITAL LETTER M */ \
+ 0x006D, /* LATIN SMALL LETTER M */ }, \
+ { 0x1E3E, /* LATIN CAPITAL LETTER M WITH ACUTE */ \
+ 0x1E3F, /* LATIN SMALL LETTER M WITH ACUTE */ }, \
+ { 0x1E40, /* LATIN CAPITAL LETTER M WITH DOT ABOVE */ \
+ 0x1E41, /* LATIN SMALL LETTER M WITH DOT ABOVE */ }, \
+ { 0x1E42, /* LATIN CAPITAL LETTER M WITH DOT BELOW */ \
+ 0x1E43, /* LATIN SMALL LETTER M WITH DOT BELOW */ }, \
+ { 0x2C6E, /* LATIN CAPITAL LETTER M WITH HOOK */ \
+ 0x0271, /* LATIN SMALL LETTER M WITH HOOK */ }, \
+ { 0x1EFA, /* LATIN CAPITAL LETTER MIDDLE-WELSH LL */ \
+ 0x1EFB, /* LATIN SMALL LETTER MIDDLE-WELSH LL */ }, \
+ { 0x1EFC, /* LATIN CAPITAL LETTER MIDDLE-WELSH V */ \
+ 0x1EFD, /* LATIN SMALL LETTER MIDDLE-WELSH V */ }, \
+ { 0x004E, /* LATIN CAPITAL LETTER N */ \
+ 0x006E, /* LATIN SMALL LETTER N */ }, \
+ { 0x0143, /* LATIN CAPITAL LETTER N WITH ACUTE */ \
+ 0x0144, /* LATIN SMALL LETTER N WITH ACUTE */ }, \
+ { 0x0147, /* LATIN CAPITAL LETTER N WITH CARON */ \
+ 0x0148, /* LATIN SMALL LETTER N WITH CARON */ }, \
+ { 0x0145, /* LATIN CAPITAL LETTER N WITH CEDILLA */ \
+ 0x0146, /* LATIN SMALL LETTER N WITH CEDILLA */ }, \
+ { 0x1E4A, /* LATIN CAPITAL LETTER N WITH CIRCUMFLEX BELOW */ \
+ 0x1E4B, /* LATIN SMALL LETTER N WITH CIRCUMFLEX BELOW */ }, \
+ { 0xA790, /* LATIN CAPITAL LETTER N WITH DESCENDER */ \
+ 0xA791, /* LATIN SMALL LETTER N WITH DESCENDER */ }, \
+ { 0x1E44, /* LATIN CAPITAL LETTER N WITH DOT ABOVE */ \
+ 0x1E45, /* LATIN SMALL LETTER N WITH DOT ABOVE */ }, \
+ { 0x1E46, /* LATIN CAPITAL LETTER N WITH DOT BELOW */ \
+ 0x1E47, /* LATIN SMALL LETTER N WITH DOT BELOW */ }, \
+ { 0x01F8, /* LATIN CAPITAL LETTER N WITH GRAVE */ \
+ 0x01F9, /* LATIN SMALL LETTER N WITH GRAVE */ }, \
+ { 0x019D, /* LATIN CAPITAL LETTER N WITH LEFT HOOK */ \
+ 0x0272, /* LATIN SMALL LETTER N WITH LEFT HOOK */ }, \
+ { 0x1E48, /* LATIN CAPITAL LETTER N WITH LINE BELOW */ \
+ 0x1E49, /* LATIN SMALL LETTER N WITH LINE BELOW */ }, \
+ { 0x0220, /* LATIN CAPITAL LETTER N WITH LONG RIGHT LEG */ \
+ 0x019E, /* LATIN SMALL LETTER N WITH LONG RIGHT LEG */ }, \
+ { 0xA7A4, /* LATIN CAPITAL LETTER N WITH OBLIQUE STROKE */ \
+ 0xA7A5, /* LATIN SMALL LETTER N WITH OBLIQUE STROKE */ }, \
+ { 0x00D1, /* LATIN CAPITAL LETTER N WITH TILDE */ \
+ 0x00F1, /* LATIN SMALL LETTER N WITH TILDE */ }, \
+ { 0x01CA, /* LATIN CAPITAL LETTER NJ */ \
+ 0x01CC, /* LATIN SMALL LETTER NJ */ }, \
+ { 0x004F, /* LATIN CAPITAL LETTER O */ \
+ 0x006F, /* LATIN SMALL LETTER O */ }, \
+ { 0x00D3, /* LATIN CAPITAL LETTER O WITH ACUTE */ \
+ 0x00F3, /* LATIN SMALL LETTER O WITH ACUTE */ }, \
+ { 0x014E, /* LATIN CAPITAL LETTER O WITH BREVE */ \
+ 0x014F, /* LATIN SMALL LETTER O WITH BREVE */ }, \
+ { 0x01D1, /* LATIN CAPITAL LETTER O WITH CARON */ \
+ 0x01D2, /* LATIN SMALL LETTER O WITH CARON */ }, \
+ { 0x00D4, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX */ \
+ 0x00F4, /* LATIN SMALL LETTER O WITH CIRCUMFLEX */ }, \
+ { 0x1ED0, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND ACUTE */ \
+ 0x1ED1, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND ACUTE */ }, \
+ { 0x1ED8, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND DOT BELOW */ \
+ 0x1ED9, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND DOT BELOW */ }, \
+ { 0x1ED2, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND GRAVE */ \
+ 0x1ED3, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND GRAVE */ }, \
+ { 0x1ED4, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND HOOK ABOVE */ \
+ 0x1ED5, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND HOOK ABOVE */ }, \
+ { 0x1ED6, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND TILDE */ \
+ 0x1ED7, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND TILDE */ }, \
+ { 0x00D6, /* LATIN CAPITAL LETTER O WITH DIAERESIS */ \
+ 0x00F6, /* LATIN SMALL LETTER O WITH DIAERESIS */ }, \
+ { 0x022A, /* LATIN CAPITAL LETTER O WITH DIAERESIS AND MACRON */ \
+ 0x022B, /* LATIN SMALL LETTER O WITH DIAERESIS AND MACRON */ }, \
+ { 0x022E, /* LATIN CAPITAL LETTER O WITH DOT ABOVE */ \
+ 0x022F, /* LATIN SMALL LETTER O WITH DOT ABOVE */ }, \
+ { 0x0230, /* LATIN CAPITAL LETTER O WITH DOT ABOVE AND MACRON */ \
+ 0x0231, /* LATIN SMALL LETTER O WITH DOT ABOVE AND MACRON */ }, \
+ { 0x1ECC, /* LATIN CAPITAL LETTER O WITH DOT BELOW */ \
+ 0x1ECD, /* LATIN SMALL LETTER O WITH DOT BELOW */ }, \
+ { 0x0150, /* LATIN CAPITAL LETTER O WITH DOUBLE ACUTE */ \
+ 0x0151, /* LATIN SMALL LETTER O WITH DOUBLE ACUTE */ }, \
+ { 0x020C, /* LATIN CAPITAL LETTER O WITH DOUBLE GRAVE */ \
+ 0x020D, /* LATIN SMALL LETTER O WITH DOUBLE GRAVE */ }, \
+ { 0x00D2, /* LATIN CAPITAL LETTER O WITH GRAVE */ \
+ 0x00F2, /* LATIN SMALL LETTER O WITH GRAVE */ }, \
+ { 0x1ECE, /* LATIN CAPITAL LETTER O WITH HOOK ABOVE */ \
+ 0x1ECF, /* LATIN SMALL LETTER O WITH HOOK ABOVE */ }, \
+ { 0x01A0, /* LATIN CAPITAL LETTER O WITH HORN */ \
+ 0x01A1, /* LATIN SMALL LETTER O WITH HORN */ }, \
+ { 0x1EDA, /* LATIN CAPITAL LETTER O WITH HORN AND ACUTE */ \
+ 0x1EDB, /* LATIN SMALL LETTER O WITH HORN AND ACUTE */ }, \
+ { 0x1EE2, /* LATIN CAPITAL LETTER O WITH HORN AND DOT BELOW */ \
+ 0x1EE3, /* LATIN SMALL LETTER O WITH HORN AND DOT BELOW */ }, \
+ { 0x1EDC, /* LATIN CAPITAL LETTER O WITH HORN AND GRAVE */ \
+ 0x1EDD, /* LATIN SMALL LETTER O WITH HORN AND GRAVE */ }, \
+ { 0x1EDE, /* LATIN CAPITAL LETTER O WITH HORN AND HOOK ABOVE */ \
+ 0x1EDF, /* LATIN SMALL LETTER O WITH HORN AND HOOK ABOVE */ }, \
+ { 0x1EE0, /* LATIN CAPITAL LETTER O WITH HORN AND TILDE */ \
+ 0x1EE1, /* LATIN SMALL LETTER O WITH HORN AND TILDE */ }, \
+ { 0x020E, /* LATIN CAPITAL LETTER O WITH INVERTED BREVE */ \
+ 0x020F, /* LATIN SMALL LETTER O WITH INVERTED BREVE */ }, \
+ { 0xA74A, /* LATIN CAPITAL LETTER O WITH LONG STROKE OVERLAY */ \
+ 0xA74B, /* LATIN SMALL LETTER O WITH LONG STROKE OVERLAY */ }, \
+ { 0xA74C, /* LATIN CAPITAL LETTER O WITH LOOP */ \
+ 0xA74D, /* LATIN SMALL LETTER O WITH LOOP */ }, \
+ { 0x014C, /* LATIN CAPITAL LETTER O WITH MACRON */ \
+ 0x014D, /* LATIN SMALL LETTER O WITH MACRON */ }, \
+ { 0x1E52, /* LATIN CAPITAL LETTER O WITH MACRON AND ACUTE */ \
+ 0x1E53, /* LATIN SMALL LETTER O WITH MACRON AND ACUTE */ }, \
+ { 0x1E50, /* LATIN CAPITAL LETTER O WITH MACRON AND GRAVE */ \
+ 0x1E51, /* LATIN SMALL LETTER O WITH MACRON AND GRAVE */ }, \
+ { 0x01EA, /* LATIN CAPITAL LETTER O WITH OGONEK */ \
+ 0x01EB, /* LATIN SMALL LETTER O WITH OGONEK */ }, \
+ { 0x01EC, /* LATIN CAPITAL LETTER O WITH OGONEK AND MACRON */ \
+ 0x01ED, /* LATIN SMALL LETTER O WITH OGONEK AND MACRON */ }, \
+ { 0x00D8, /* LATIN CAPITAL LETTER O WITH STROKE */ \
+ 0x00F8, /* LATIN SMALL LETTER O WITH STROKE */ }, \
+ { 0x01FE, /* LATIN CAPITAL LETTER O WITH STROKE AND ACUTE */ \
+ 0x01FF, /* LATIN SMALL LETTER O WITH STROKE AND ACUTE */ }, \
+ { 0x00D5, /* LATIN CAPITAL LETTER O WITH TILDE */ \
+ 0x00F5, /* LATIN SMALL LETTER O WITH TILDE */ }, \
+ { 0x1E4C, /* LATIN CAPITAL LETTER O WITH TILDE AND ACUTE */ \
+ 0x1E4D, /* LATIN SMALL LETTER O WITH TILDE AND ACUTE */ }, \
+ { 0x1E4E, /* LATIN CAPITAL LETTER O WITH TILDE AND DIAERESIS */ \
+ 0x1E4F, /* LATIN SMALL LETTER O WITH TILDE AND DIAERESIS */ }, \
+ { 0x022C, /* LATIN CAPITAL LETTER O WITH TILDE AND MACRON */ \
+ 0x022D, /* LATIN SMALL LETTER O WITH TILDE AND MACRON */ }, \
+ { 0x01A2, /* LATIN CAPITAL LETTER OI */ \
+ 0x01A3, /* LATIN SMALL LETTER OI */ }, \
+ { 0xA7B6, /* LATIN CAPITAL LETTER OMEGA */ \
+ 0xA7B7, /* LATIN SMALL LETTER OMEGA */ }, \
+ { 0xA74E, /* LATIN CAPITAL LETTER OO */ \
+ 0xA74F, /* LATIN SMALL LETTER OO */ }, \
+ { 0x0190, /* LATIN CAPITAL LETTER OPEN E */ \
+ 0x025B, /* LATIN SMALL LETTER OPEN E */ }, \
+ { 0x0186, /* LATIN CAPITAL LETTER OPEN O */ \
+ 0x0254, /* LATIN SMALL LETTER OPEN O */ }, \
+ { 0x0222, /* LATIN CAPITAL LETTER OU */ \
+ 0x0223, /* LATIN SMALL LETTER OU */ }, \
+ { 0x0050, /* LATIN CAPITAL LETTER P */ \
+ 0x0070, /* LATIN SMALL LETTER P */ }, \
+ { 0x1E54, /* LATIN CAPITAL LETTER P WITH ACUTE */ \
+ 0x1E55, /* LATIN SMALL LETTER P WITH ACUTE */ }, \
+ { 0x1E56, /* LATIN CAPITAL LETTER P WITH DOT ABOVE */ \
+ 0x1E57, /* LATIN SMALL LETTER P WITH DOT ABOVE */ }, \
+ { 0xA752, /* LATIN CAPITAL LETTER P WITH FLOURISH */ \
+ 0xA753, /* LATIN SMALL LETTER P WITH FLOURISH */ }, \
+ { 0x01A4, /* LATIN CAPITAL LETTER P WITH HOOK */ \
+ 0x01A5, /* LATIN SMALL LETTER P WITH HOOK */ }, \
+ { 0xA754, /* LATIN CAPITAL LETTER P WITH SQUIRREL TAIL */ \
+ 0xA755, /* LATIN SMALL LETTER P WITH SQUIRREL TAIL */ }, \
+ { 0x2C63, /* LATIN CAPITAL LETTER P WITH STROKE */ \
+ 0x1D7D, /* LATIN SMALL LETTER P WITH STROKE */ }, \
+ { 0xA750, /* LATIN CAPITAL LETTER P WITH STROKE THROUGH DESCENDER */ \
+ 0xA751, /* LATIN SMALL LETTER P WITH STROKE THROUGH DESCENDER */ }, \
+ { 0x0051, /* LATIN CAPITAL LETTER Q */ \
+ 0x0071, /* LATIN SMALL LETTER Q */ }, \
+ { 0xA758, /* LATIN CAPITAL LETTER Q WITH DIAGONAL STROKE */ \
+ 0xA759, /* LATIN SMALL LETTER Q WITH DIAGONAL STROKE */ }, \
+ { 0xA756, /* LATIN CAPITAL LETTER Q WITH STROKE THROUGH DESCENDER */ \
+ 0xA757, /* LATIN SMALL LETTER Q WITH STROKE THROUGH DESCENDER */ }, \
+ { 0x0052, /* LATIN CAPITAL LETTER R */ \
+ 0x0072, /* LATIN SMALL LETTER R */ }, \
+ { 0xA75A, /* LATIN CAPITAL LETTER R ROTUNDA */ \
+ 0xA75B, /* LATIN SMALL LETTER R ROTUNDA */ }, \
+ { 0x0154, /* LATIN CAPITAL LETTER R WITH ACUTE */ \
+ 0x0155, /* LATIN SMALL LETTER R WITH ACUTE */ }, \
+ { 0x0158, /* LATIN CAPITAL LETTER R WITH CARON */ \
+ 0x0159, /* LATIN SMALL LETTER R WITH CARON */ }, \
+ { 0x0156, /* LATIN CAPITAL LETTER R WITH CEDILLA */ \
+ 0x0157, /* LATIN SMALL LETTER R WITH CEDILLA */ }, \
+ { 0x1E58, /* LATIN CAPITAL LETTER R WITH DOT ABOVE */ \
+ 0x1E59, /* LATIN SMALL LETTER R WITH DOT ABOVE */ }, \
+ { 0x1E5A, /* LATIN CAPITAL LETTER R WITH DOT BELOW */ \
+ 0x1E5B, /* LATIN SMALL LETTER R WITH DOT BELOW */ }, \
+ { 0x1E5C, /* LATIN CAPITAL LETTER R WITH DOT BELOW AND MACRON */ \
+ 0x1E5D, /* LATIN SMALL LETTER R WITH DOT BELOW AND MACRON */ }, \
+ { 0x0210, /* LATIN CAPITAL LETTER R WITH DOUBLE GRAVE */ \
+ 0x0211, /* LATIN SMALL LETTER R WITH DOUBLE GRAVE */ }, \
+ { 0x0212, /* LATIN CAPITAL LETTER R WITH INVERTED BREVE */ \
+ 0x0213, /* LATIN SMALL LETTER R WITH INVERTED BREVE */ }, \
+ { 0x1E5E, /* LATIN CAPITAL LETTER R WITH LINE BELOW */ \
+ 0x1E5F, /* LATIN SMALL LETTER R WITH LINE BELOW */ }, \
+ { 0xA7A6, /* LATIN CAPITAL LETTER R WITH OBLIQUE STROKE */ \
+ 0xA7A7, /* LATIN SMALL LETTER R WITH OBLIQUE STROKE */ }, \
+ { 0x024C, /* LATIN CAPITAL LETTER R WITH STROKE */ \
+ 0x024D, /* LATIN SMALL LETTER R WITH STROKE */ }, \
+ { 0x2C64, /* LATIN CAPITAL LETTER R WITH TAIL */ \
+ 0x027D, /* LATIN SMALL LETTER R WITH TAIL */ }, \
+ { 0xA73E, /* LATIN CAPITAL LETTER REVERSED C WITH DOT */ \
+ 0xA73F, /* LATIN SMALL LETTER REVERSED C WITH DOT */ }, \
+ { 0x018E, /* LATIN CAPITAL LETTER REVERSED E */ \
+ 0x0258, /* LATIN SMALL LETTER REVERSED E */ }, \
+ { 0xA7AB, /* LATIN CAPITAL LETTER REVERSED OPEN E */ \
+ 0x025C, /* LATIN SMALL LETTER REVERSED OPEN E */ }, \
+ { 0xA75C, /* LATIN CAPITAL LETTER RUM ROTUNDA */ \
+ 0xA75D, /* LATIN SMALL LETTER RUM ROTUNDA */ }, \
+ { 0x0053, /* LATIN CAPITAL LETTER S */ \
+ 0x0073, /* LATIN SMALL LETTER S */ }, \
+ { 0x015A, /* LATIN CAPITAL LETTER S WITH ACUTE */ \
+ 0x015B, /* LATIN SMALL LETTER S WITH ACUTE */ }, \
+ { 0x1E64, /* LATIN CAPITAL LETTER S WITH ACUTE AND DOT ABOVE */ \
+ 0x1E65, /* LATIN SMALL LETTER S WITH ACUTE AND DOT ABOVE */ }, \
+ { 0x0160, /* LATIN CAPITAL LETTER S WITH CARON */ \
+ 0x0161, /* LATIN SMALL LETTER S WITH CARON */ }, \
+ { 0x1E66, /* LATIN CAPITAL LETTER S WITH CARON AND DOT ABOVE */ \
+ 0x1E67, /* LATIN SMALL LETTER S WITH CARON AND DOT ABOVE */ }, \
+ { 0x015E, /* LATIN CAPITAL LETTER S WITH CEDILLA */ \
+ 0x015F, /* LATIN SMALL LETTER S WITH CEDILLA */ }, \
+ { 0x015C, /* LATIN CAPITAL LETTER S WITH CIRCUMFLEX */ \
+ 0x015D, /* LATIN SMALL LETTER S WITH CIRCUMFLEX */ }, \
+ { 0x0218, /* LATIN CAPITAL LETTER S WITH COMMA BELOW */ \
+ 0x0219, /* LATIN SMALL LETTER S WITH COMMA BELOW */ }, \
+ { 0x1E60, /* LATIN CAPITAL LETTER S WITH DOT ABOVE */ \
+ 0x1E61, /* LATIN SMALL LETTER S WITH DOT ABOVE */ }, \
+ { 0x1E62, /* LATIN CAPITAL LETTER S WITH DOT BELOW */ \
+ 0x1E63, /* LATIN SMALL LETTER S WITH DOT BELOW */ }, \
+ { 0x1E68, /* LATIN CAPITAL LETTER S WITH DOT BELOW AND DOT ABOVE */ \
+ 0x1E69, /* LATIN SMALL LETTER S WITH DOT BELOW AND DOT ABOVE */ }, \
+ { 0xA7A8, /* LATIN CAPITAL LETTER S WITH OBLIQUE STROKE */ \
+ 0xA7A9, /* LATIN SMALL LETTER S WITH OBLIQUE STROKE */ }, \
+ { 0x2C7E, /* LATIN CAPITAL LETTER S WITH SWASH TAIL */ \
+ 0x023F, /* LATIN SMALL LETTER S WITH SWASH TAIL */ }, \
+ { 0xA78B, /* LATIN CAPITAL LETTER SALTILLO */ \
+ 0xA78C, /* LATIN SMALL LETTER SALTILLO */ }, \
+ { 0x018F, /* LATIN CAPITAL LETTER SCHWA */ \
+ 0x0259, /* LATIN SMALL LETTER SCHWA */ }, \
+ { 0xA7AC, /* LATIN CAPITAL LETTER SCRIPT G */ \
+ 0x0261, /* LATIN SMALL LETTER SCRIPT G */ }, \
+ { 0x1E9E, /* LATIN CAPITAL LETTER SHARP S */ \
+ 0x00DF, /* LATIN SMALL LETTER SHARP S */ }, \
+ { 0x0054, /* LATIN CAPITAL LETTER T */ \
+ 0x0074, /* LATIN SMALL LETTER T */ }, \
+ { 0x0164, /* LATIN CAPITAL LETTER T WITH CARON */ \
+ 0x0165, /* LATIN SMALL LETTER T WITH CARON */ }, \
+ { 0x0162, /* LATIN CAPITAL LETTER T WITH CEDILLA */ \
+ 0x0163, /* LATIN SMALL LETTER T WITH CEDILLA */ }, \
+ { 0x1E70, /* LATIN CAPITAL LETTER T WITH CIRCUMFLEX BELOW */ \
+ 0x1E71, /* LATIN SMALL LETTER T WITH CIRCUMFLEX BELOW */ }, \
+ { 0x021A, /* LATIN CAPITAL LETTER T WITH COMMA BELOW */ \
+ 0x021B, /* LATIN SMALL LETTER T WITH COMMA BELOW */ }, \
+ { 0x023E, /* LATIN CAPITAL LETTER T WITH DIAGONAL STROKE */ \
+ 0x2C66, /* LATIN SMALL LETTER T WITH DIAGONAL STROKE */ }, \
+ { 0x1E6A, /* LATIN CAPITAL LETTER T WITH DOT ABOVE */ \
+ 0x1E6B, /* LATIN SMALL LETTER T WITH DOT ABOVE */ }, \
+ { 0x1E6C, /* LATIN CAPITAL LETTER T WITH DOT BELOW */ \
+ 0x1E6D, /* LATIN SMALL LETTER T WITH DOT BELOW */ }, \
+ { 0x01AC, /* LATIN CAPITAL LETTER T WITH HOOK */ \
+ 0x01AD, /* LATIN SMALL LETTER T WITH HOOK */ }, \
+ { 0x1E6E, /* LATIN CAPITAL LETTER T WITH LINE BELOW */ \
+ 0x1E6F, /* LATIN SMALL LETTER T WITH LINE BELOW */ }, \
+ { 0x01AE, /* LATIN CAPITAL LETTER T WITH RETROFLEX HOOK */ \
+ 0x0288, /* LATIN SMALL LETTER T WITH RETROFLEX HOOK */ }, \
+ { 0x0166, /* LATIN CAPITAL LETTER T WITH STROKE */ \
+ 0x0167, /* LATIN SMALL LETTER T WITH STROKE */ }, \
+ { 0x00DE, /* LATIN CAPITAL LETTER THORN */ \
+ 0x00FE, /* LATIN SMALL LETTER THORN */ }, \
+ { 0xA764, /* LATIN CAPITAL LETTER THORN WITH STROKE */ \
+ 0xA765, /* LATIN SMALL LETTER THORN WITH STROKE */ }, \
+ { 0xA766, /* LATIN CAPITAL LETTER THORN WITH STROKE THROUGH DESCENDER */ \
+ 0xA767, /* LATIN SMALL LETTER THORN WITH STROKE THROUGH DESCENDER */ }, \
+ { 0x01BC, /* LATIN CAPITAL LETTER TONE FIVE */ \
+ 0x01BD, /* LATIN SMALL LETTER TONE FIVE */ }, \
+ { 0x0184, /* LATIN CAPITAL LETTER TONE SIX */ \
+ 0x0185, /* LATIN SMALL LETTER TONE SIX */ }, \
+ { 0x01A7, /* LATIN CAPITAL LETTER TONE TWO */ \
+ 0x01A8, /* LATIN SMALL LETTER TONE TWO */ }, \
+ { 0xA72A, /* LATIN CAPITAL LETTER TRESILLO */ \
+ 0xA72B, /* LATIN SMALL LETTER TRESILLO */ }, \
+ { 0x2C6F, /* LATIN CAPITAL LETTER TURNED A */ \
+ 0x0250, /* LATIN SMALL LETTER TURNED A */ }, \
+ { 0x2C70, /* LATIN CAPITAL LETTER TURNED ALPHA */ \
+ 0x0252, /* LATIN SMALL LETTER TURNED ALPHA */ }, \
+ { 0xA78D, /* LATIN CAPITAL LETTER TURNED H */ \
+ 0x0265, /* LATIN SMALL LETTER TURNED H */ }, \
+ { 0xA77E, /* LATIN CAPITAL LETTER TURNED INSULAR G */ \
+ 0xA77F, /* LATIN SMALL LETTER TURNED INSULAR G */ }, \
+ { 0xA7B0, /* LATIN CAPITAL LETTER TURNED K */ \
+ 0x029E, /* LATIN SMALL LETTER TURNED K */ }, \
+ { 0xA780, /* LATIN CAPITAL LETTER TURNED L */ \
+ 0xA781, /* LATIN SMALL LETTER TURNED L */ }, \
+ { 0x019C, /* LATIN CAPITAL LETTER TURNED M */ \
+ 0x026F, /* LATIN SMALL LETTER TURNED M */ }, \
+ { 0xA7B1, /* LATIN CAPITAL LETTER TURNED T */ \
+ 0x0287, /* LATIN SMALL LETTER TURNED T */ }, \
+ { 0x0245, /* LATIN CAPITAL LETTER TURNED V */ \
+ 0x028C, /* LATIN SMALL LETTER TURNED V */ }, \
+ { 0xA728, /* LATIN CAPITAL LETTER TZ */ \
+ 0xA729, /* LATIN SMALL LETTER TZ */ }, \
+ { 0x0055, /* LATIN CAPITAL LETTER U */ \
+ 0x0075, /* LATIN SMALL LETTER U */ }, \
+ { 0x0244, /* LATIN CAPITAL LETTER U BAR */ \
+ 0x0289, /* LATIN SMALL LETTER U BAR */ }, \
+ { 0x00DA, /* LATIN CAPITAL LETTER U WITH ACUTE */ \
+ 0x00FA, /* LATIN SMALL LETTER U WITH ACUTE */ }, \
+ { 0x016C, /* LATIN CAPITAL LETTER U WITH BREVE */ \
+ 0x016D, /* LATIN SMALL LETTER U WITH BREVE */ }, \
+ { 0x01D3, /* LATIN CAPITAL LETTER U WITH CARON */ \
+ 0x01D4, /* LATIN SMALL LETTER U WITH CARON */ }, \
+ { 0x00DB, /* LATIN CAPITAL LETTER U WITH CIRCUMFLEX */ \
+ 0x00FB, /* LATIN SMALL LETTER U WITH CIRCUMFLEX */ }, \
+ { 0x1E76, /* LATIN CAPITAL LETTER U WITH CIRCUMFLEX BELOW */ \
+ 0x1E77, /* LATIN SMALL LETTER U WITH CIRCUMFLEX BELOW */ }, \
+ { 0x00DC, /* LATIN CAPITAL LETTER U WITH DIAERESIS */ \
+ 0x00FC, /* LATIN SMALL LETTER U WITH DIAERESIS */ }, \
+ { 0x01D7, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND ACUTE */ \
+ 0x01D8, /* LATIN SMALL LETTER U WITH DIAERESIS AND ACUTE */ }, \
+ { 0x01D9, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND CARON */ \
+ 0x01DA, /* LATIN SMALL LETTER U WITH DIAERESIS AND CARON */ }, \
+ { 0x01DB, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND GRAVE */ \
+ 0x01DC, /* LATIN SMALL LETTER U WITH DIAERESIS AND GRAVE */ }, \
+ { 0x01D5, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND MACRON */ \
+ 0x01D6, /* LATIN SMALL LETTER U WITH DIAERESIS AND MACRON */ }, \
+ { 0x1E72, /* LATIN CAPITAL LETTER U WITH DIAERESIS BELOW */ \
+ 0x1E73, /* LATIN SMALL LETTER U WITH DIAERESIS BELOW */ }, \
+ { 0x1EE4, /* LATIN CAPITAL LETTER U WITH DOT BELOW */ \
+ 0x1EE5, /* LATIN SMALL LETTER U WITH DOT BELOW */ }, \
+ { 0x0170, /* LATIN CAPITAL LETTER U WITH DOUBLE ACUTE */ \
+ 0x0171, /* LATIN SMALL LETTER U WITH DOUBLE ACUTE */ }, \
+ { 0x0214, /* LATIN CAPITAL LETTER U WITH DOUBLE GRAVE */ \
+ 0x0215, /* LATIN SMALL LETTER U WITH DOUBLE GRAVE */ }, \
+ { 0x00D9, /* LATIN CAPITAL LETTER U WITH GRAVE */ \
+ 0x00F9, /* LATIN SMALL LETTER U WITH GRAVE */ }, \
+ { 0x1EE6, /* LATIN CAPITAL LETTER U WITH HOOK ABOVE */ \
+ 0x1EE7, /* LATIN SMALL LETTER U WITH HOOK ABOVE */ }, \
+ { 0x01AF, /* LATIN CAPITAL LETTER U WITH HORN */ \
+ 0x01B0, /* LATIN SMALL LETTER U WITH HORN */ }, \
+ { 0x1EE8, /* LATIN CAPITAL LETTER U WITH HORN AND ACUTE */ \
+ 0x1EE9, /* LATIN SMALL LETTER U WITH HORN AND ACUTE */ }, \
+ { 0x1EF0, /* LATIN CAPITAL LETTER U WITH HORN AND DOT BELOW */ \
+ 0x1EF1, /* LATIN SMALL LETTER U WITH HORN AND DOT BELOW */ }, \
+ { 0x1EEA, /* LATIN CAPITAL LETTER U WITH HORN AND GRAVE */ \
+ 0x1EEB, /* LATIN SMALL LETTER U WITH HORN AND GRAVE */ }, \
+ { 0x1EEC, /* LATIN CAPITAL LETTER U WITH HORN AND HOOK ABOVE */ \
+ 0x1EED, /* LATIN SMALL LETTER U WITH HORN AND HOOK ABOVE */ }, \
+ { 0x1EEE, /* LATIN CAPITAL LETTER U WITH HORN AND TILDE */ \
+ 0x1EEF, /* LATIN SMALL LETTER U WITH HORN AND TILDE */ }, \
+ { 0x0216, /* LATIN CAPITAL LETTER U WITH INVERTED BREVE */ \
+ 0x0217, /* LATIN SMALL LETTER U WITH INVERTED BREVE */ }, \
+ { 0x016A, /* LATIN CAPITAL LETTER U WITH MACRON */ \
+ 0x016B, /* LATIN SMALL LETTER U WITH MACRON */ }, \
+ { 0x1E7A, /* LATIN CAPITAL LETTER U WITH MACRON AND DIAERESIS */ \
+ 0x1E7B, /* LATIN SMALL LETTER U WITH MACRON AND DIAERESIS */ }, \
+ { 0x0172, /* LATIN CAPITAL LETTER U WITH OGONEK */ \
+ 0x0173, /* LATIN SMALL LETTER U WITH OGONEK */ }, \
+ { 0x016E, /* LATIN CAPITAL LETTER U WITH RING ABOVE */ \
+ 0x016F, /* LATIN SMALL LETTER U WITH RING ABOVE */ }, \
+ { 0xA7B8, /* LATIN CAPITAL LETTER U WITH STROKE */ \
+ 0xA7B9, /* LATIN SMALL LETTER U WITH STROKE */ }, \
+ { 0x0168, /* LATIN CAPITAL LETTER U WITH TILDE */ \
+ 0x0169, /* LATIN SMALL LETTER U WITH TILDE */ }, \
+ { 0x1E78, /* LATIN CAPITAL LETTER U WITH TILDE AND ACUTE */ \
+ 0x1E79, /* LATIN SMALL LETTER U WITH TILDE AND ACUTE */ }, \
+ { 0x1E74, /* LATIN CAPITAL LETTER U WITH TILDE BELOW */ \
+ 0x1E75, /* LATIN SMALL LETTER U WITH TILDE BELOW */ }, \
+ { 0x01B1, /* LATIN CAPITAL LETTER UPSILON */ \
+ 0x028A, /* LATIN SMALL LETTER UPSILON */ }, \
+ { 0x0056, /* LATIN CAPITAL LETTER V */ \
+ 0x0076, /* LATIN SMALL LETTER V */ }, \
+ { 0xA75E, /* LATIN CAPITAL LETTER V WITH DIAGONAL STROKE */ \
+ 0xA75F, /* LATIN SMALL LETTER V WITH DIAGONAL STROKE */ }, \
+ { 0x1E7E, /* LATIN CAPITAL LETTER V WITH DOT BELOW */ \
+ 0x1E7F, /* LATIN SMALL LETTER V WITH DOT BELOW */ }, \
+ { 0x01B2, /* LATIN CAPITAL LETTER V WITH HOOK */ \
+ 0x028B, /* LATIN SMALL LETTER V WITH HOOK */ }, \
+ { 0x1E7C, /* LATIN CAPITAL LETTER V WITH TILDE */ \
+ 0x1E7D, /* LATIN SMALL LETTER V WITH TILDE */ }, \
+ { 0xA768, /* LATIN CAPITAL LETTER VEND */ \
+ 0xA769, /* LATIN SMALL LETTER VEND */ }, \
+ { 0xA762, /* LATIN CAPITAL LETTER VISIGOTHIC Z */ \
+ 0xA763, /* LATIN SMALL LETTER VISIGOTHIC Z */ }, \
+ { 0xA79A, /* LATIN CAPITAL LETTER VOLAPUK AE */ \
+ 0xA79B, /* LATIN SMALL LETTER VOLAPUK AE */ }, \
+ { 0xA79C, /* LATIN CAPITAL LETTER VOLAPUK OE */ \
+ 0xA79D, /* LATIN SMALL LETTER VOLAPUK OE */ }, \
+ { 0xA79E, /* LATIN CAPITAL LETTER VOLAPUK UE */ \
+ 0xA79F, /* LATIN SMALL LETTER VOLAPUK UE */ }, \
+ { 0xA760, /* LATIN CAPITAL LETTER VY */ \
+ 0xA761, /* LATIN SMALL LETTER VY */ }, \
+ { 0x0057, /* LATIN CAPITAL LETTER W */ \
+ 0x0077, /* LATIN SMALL LETTER W */ }, \
+ { 0x1E82, /* LATIN CAPITAL LETTER W WITH ACUTE */ \
+ 0x1E83, /* LATIN SMALL LETTER W WITH ACUTE */ }, \
+ { 0x0174, /* LATIN CAPITAL LETTER W WITH CIRCUMFLEX */ \
+ 0x0175, /* LATIN SMALL LETTER W WITH CIRCUMFLEX */ }, \
+ { 0x1E84, /* LATIN CAPITAL LETTER W WITH DIAERESIS */ \
+ 0x1E85, /* LATIN SMALL LETTER W WITH DIAERESIS */ }, \
+ { 0x1E86, /* LATIN CAPITAL LETTER W WITH DOT ABOVE */ \
+ 0x1E87, /* LATIN SMALL LETTER W WITH DOT ABOVE */ }, \
+ { 0x1E88, /* LATIN CAPITAL LETTER W WITH DOT BELOW */ \
+ 0x1E89, /* LATIN SMALL LETTER W WITH DOT BELOW */ }, \
+ { 0x1E80, /* LATIN CAPITAL LETTER W WITH GRAVE */ \
+ 0x1E81, /* LATIN SMALL LETTER W WITH GRAVE */ }, \
+ { 0x2C72, /* LATIN CAPITAL LETTER W WITH HOOK */ \
+ 0x2C73, /* LATIN SMALL LETTER W WITH HOOK */ }, \
+ { 0x0058, /* LATIN CAPITAL LETTER X */ \
+ 0x0078, /* LATIN SMALL LETTER X */ }, \
+ { 0x1E8C, /* LATIN CAPITAL LETTER X WITH DIAERESIS */ \
+ 0x1E8D, /* LATIN SMALL LETTER X WITH DIAERESIS */ }, \
+ { 0x1E8A, /* LATIN CAPITAL LETTER X WITH DOT ABOVE */ \
+ 0x1E8B, /* LATIN SMALL LETTER X WITH DOT ABOVE */ }, \
+ { 0x0059, /* LATIN CAPITAL LETTER Y */ \
+ 0x0079, /* LATIN SMALL LETTER Y */ }, \
+ { 0x00DD, /* LATIN CAPITAL LETTER Y WITH ACUTE */ \
+ 0x00FD, /* LATIN SMALL LETTER Y WITH ACUTE */ }, \
+ { 0x0176, /* LATIN CAPITAL LETTER Y WITH CIRCUMFLEX */ \
+ 0x0177, /* LATIN SMALL LETTER Y WITH CIRCUMFLEX */ }, \
+ { 0x0178, /* LATIN CAPITAL LETTER Y WITH DIAERESIS */ \
+ 0x00FF, /* LATIN SMALL LETTER Y WITH DIAERESIS */ }, \
+ { 0x1E8E, /* LATIN CAPITAL LETTER Y WITH DOT ABOVE */ \
+ 0x1E8F, /* LATIN SMALL LETTER Y WITH DOT ABOVE */ }, \
+ { 0x1EF4, /* LATIN CAPITAL LETTER Y WITH DOT BELOW */ \
+ 0x1EF5, /* LATIN SMALL LETTER Y WITH DOT BELOW */ }, \
+ { 0x1EF2, /* LATIN CAPITAL LETTER Y WITH GRAVE */ \
+ 0x1EF3, /* LATIN SMALL LETTER Y WITH GRAVE */ }, \
+ { 0x01B3, /* LATIN CAPITAL LETTER Y WITH HOOK */ \
+ 0x01B4, /* LATIN SMALL LETTER Y WITH HOOK */ }, \
+ { 0x1EF6, /* LATIN CAPITAL LETTER Y WITH HOOK ABOVE */ \
+ 0x1EF7, /* LATIN SMALL LETTER Y WITH HOOK ABOVE */ }, \
+ { 0x1EFE, /* LATIN CAPITAL LETTER Y WITH LOOP */ \
+ 0x1EFF, /* LATIN SMALL LETTER Y WITH LOOP */ }, \
+ { 0x0232, /* LATIN CAPITAL LETTER Y WITH MACRON */ \
+ 0x0233, /* LATIN SMALL LETTER Y WITH MACRON */ }, \
+ { 0x024E, /* LATIN CAPITAL LETTER Y WITH STROKE */ \
+ 0x024F, /* LATIN SMALL LETTER Y WITH STROKE */ }, \
+ { 0x1EF8, /* LATIN CAPITAL LETTER Y WITH TILDE */ \
+ 0x1EF9, /* LATIN SMALL LETTER Y WITH TILDE */ }, \
+ { 0x021C, /* LATIN CAPITAL LETTER YOGH */ \
+ 0x021D, /* LATIN SMALL LETTER YOGH */ }, \
+ { 0x005A, /* LATIN CAPITAL LETTER Z */ \
+ 0x007A, /* LATIN SMALL LETTER Z */ }, \
+ { 0x0179, /* LATIN CAPITAL LETTER Z WITH ACUTE */ \
+ 0x017A, /* LATIN SMALL LETTER Z WITH ACUTE */ }, \
+ { 0x017D, /* LATIN CAPITAL LETTER Z WITH CARON */ \
+ 0x017E, /* LATIN SMALL LETTER Z WITH CARON */ }, \
+ { 0x1E90, /* LATIN CAPITAL LETTER Z WITH CIRCUMFLEX */ \
+ 0x1E91, /* LATIN SMALL LETTER Z WITH CIRCUMFLEX */ }, \
+ { 0x2C6B, /* LATIN CAPITAL LETTER Z WITH DESCENDER */ \
+ 0x2C6C, /* LATIN SMALL LETTER Z WITH DESCENDER */ }, \
+ { 0x017B, /* LATIN CAPITAL LETTER Z WITH DOT ABOVE */ \
+ 0x017C, /* LATIN SMALL LETTER Z WITH DOT ABOVE */ }, \
+ { 0x1E92, /* LATIN CAPITAL LETTER Z WITH DOT BELOW */ \
+ 0x1E93, /* LATIN SMALL LETTER Z WITH DOT BELOW */ }, \
+ { 0x0224, /* LATIN CAPITAL LETTER Z WITH HOOK */ \
+ 0x0225, /* LATIN SMALL LETTER Z WITH HOOK */ }, \
+ { 0x1E94, /* LATIN CAPITAL LETTER Z WITH LINE BELOW */ \
+ 0x1E95, /* LATIN SMALL LETTER Z WITH LINE BELOW */ }, \
+ { 0x01B5, /* LATIN CAPITAL LETTER Z WITH STROKE */ \
+ 0x01B6, /* LATIN SMALL LETTER Z WITH STROKE */ }, \
+ { 0x2C7F, /* LATIN CAPITAL LETTER Z WITH SWASH TAIL */ \
+ 0x0240, /* LATIN SMALL LETTER Z WITH SWASH TAIL */ }, \
+ { 0x0000, /* END OF LIST CAPITAL LETTERS */ \
+ 0x0000, /* END OF LIST SMALL LETTERS */ }, \
+}
+
+/*
+ * Correspondence table for small and capital letters of codepage 437.
+ * Letters A-Z are handled in code.
+ */
+#define CP437_CAPITALIZATION_TABLE { \
+ { 0x00C4, /* LATIN CAPITAL LETTER A WITH DIAERESIS */ \
+ 0x00E4, /* LATIN SMALL LETTER A WITH DIAERESIS */ }, \
+ { 0x00C5, /* LATIN CAPITAL LETTER A WITH RING ABOVE */ \
+ 0x00E5, /* LATIN SMALL LETTER A WITH RING ABOVE */ }, \
+ { 0x00C6, /* LATIN CAPITAL LETTER AE */ \
+ 0x00E6, /* LATIN SMALL LETTER AE */ }, \
+ { 0x00C7, /* LATIN CAPITAL LETTER C WITH CEDILLA */ \
+ 0x00E7, /* LATIN SMALL LETTER C WITH CEDILLA */ }, \
+ { 0x00C9, /* LATIN CAPITAL LETTER E WITH ACUTE */ \
+ 0x00E9, /* LATIN SMALL LETTER E WITH ACUTE */ }, \
+ { 0x00D1, /* LATIN CAPITAL LETTER N WITH TILDE */ \
+ 0x00F1, /* LATIN SMALL LETTER N WITH TILDE */ }, \
+ { 0x00D6, /* LATIN CAPITAL LETTER O WITH DIAERESIS */ \
+ 0x00F6, /* LATIN SMALL LETTER O WITH DIAERESIS */ }, \
+ { 0x00DC, /* LATIN CAPITAL LETTER U WITH DIAERESIS */ \
+ 0x00FC, /* LATIN SMALL LETTER U WITH DIAERESIS */ }, \
+ { 0x03A3, /* GREEK CAPITAL LETTER SIGMA */ \
+ 0x03C3, /* GREEK SMALL LETTER SIGMA */ }, \
+ { 0x03A6, /* GREEK CAPITAL LETTER PHI */ \
+ 0x03C6, /* GREEK SMALL LETTER PHI */ }, \
+ { 0x0000, 0x0000, }, \
+}
+
+/*
+ * Correspondence table for small and capital letters of codepage 1250.
+ * Letters A-Z are handled in code.
+ */
+#define CP1250_CAPITALIZATION_TABLE { \
+ { 0x00C1, /* LATIN CAPITAL LETTER A WITH ACUTE */ \
+ 0x00E1, /* LATIN SMALL LETTER A WITH ACUTE */ }, \
+ { 0x00C2, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX */ \
+ 0x00E2, /* LATIN SMALL LETTER A WITH CIRCUMFLEX */ }, \
+ { 0x00C4, /* LATIN CAPITAL LETTER A WITH DIAERESIS */ \
+ 0x00E4, /* LATIN SMALL LETTER A WITH DIAERESIS */ }, \
+ { 0x00C7, /* LATIN CAPITAL LETTER C WITH CEDILLA */ \
+ 0x00E7, /* LATIN SMALL LETTER C WITH CEDILLA */ }, \
+ { 0x00C9, /* LATIN CAPITAL LETTER E WITH ACUTE */ \
+ 0x00E9, /* LATIN SMALL LETTER E WITH ACUTE */ }, \
+ { 0x00CB, /* LATIN CAPITAL LETTER E WITH DIAERESIS */ \
+ 0x00EB, /* LATIN SMALL LETTER E WITH DIAERESIS */ }, \
+ { 0x00CD, /* LATIN CAPITAL LETTER I WITH ACUTE */ \
+ 0x00ED, /* LATIN SMALL LETTER I WITH ACUTE */ }, \
+ { 0x00CE, /* LATIN CAPITAL LETTER I WITH CIRCUMFLEX */ \
+ 0x00EE, /* LATIN SMALL LETTER I WITH CIRCUMFLEX */ }, \
+ { 0x00D3, /* LATIN CAPITAL LETTER O WITH ACUTE */ \
+ 0x00F3, /* LATIN SMALL LETTER O WITH ACUTE */ }, \
+ { 0x00D4, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX */ \
+ 0x00F4, /* LATIN SMALL LETTER O WITH CIRCUMFLEX */ }, \
+ { 0x00D6, /* LATIN CAPITAL LETTER O WITH DIAERESIS */ \
+ 0x00F6, /* LATIN SMALL LETTER O WITH DIAERESIS */ }, \
+ { 0x00DA, /* LATIN CAPITAL LETTER U WITH ACUTE */ \
+ 0x00FA, /* LATIN SMALL LETTER U WITH ACUTE */ }, \
+ { 0x00DC, /* LATIN CAPITAL LETTER U WITH DIAERESIS */ \
+ 0x00FC, /* LATIN SMALL LETTER U WITH DIAERESIS */ }, \
+ { 0x00DD, /* LATIN CAPITAL LETTER Y WITH ACUTE */ \
+ 0x00FD, /* LATIN SMALL LETTER Y WITH ACUTE */ }, \
+ { 0x0102, /* LATIN CAPITAL LETTER A WITH BREVE */ \
+ 0x0103, /* LATIN SMALL LETTER A WITH BREVE */ }, \
+ { 0x0104, /* LATIN CAPITAL LETTER A WITH OGONEK */ \
+ 0x0105, /* LATIN SMALL LETTER A WITH OGONEK */ }, \
+ { 0x0106, /* LATIN CAPITAL LETTER C WITH ACUTE */ \
+ 0x0107, /* LATIN SMALL LETTER C WITH ACUTE */ }, \
+ { 0x010C, /* LATIN CAPITAL LETTER C WITH CARON */ \
+ 0x010D, /* LATIN SMALL LETTER C WITH CARON */ }, \
+ { 0x010E, /* LATIN CAPITAL LETTER D WITH CARON */ \
+ 0x010F, /* LATIN SMALL LETTER D WITH CARON */ }, \
+ { 0x0110, /* LATIN CAPITAL LETTER D WITH STROKE */ \
+ 0x0111, /* LATIN SMALL LETTER D WITH STROKE */ }, \
+ { 0x0118, /* LATIN CAPITAL LETTER E WITH OGONEK */ \
+ 0x0119, /* LATIN SMALL LETTER E WITH OGONEK */ }, \
+ { 0x011A, /* LATIN CAPITAL LETTER E WITH CARON */ \
+ 0x011B, /* LATIN SMALL LETTER E WITH CARON */ }, \
+ { 0x0139, /* LATIN CAPITAL LETTER L WITH ACUTE */ \
+ 0x013A, /* LATIN SMALL LETTER L WITH ACUTE */ }, \
+ { 0x013D, /* LATIN CAPITAL LETTER L WITH CARON */ \
+ 0x013E, /* LATIN SMALL LETTER L WITH CARON */ }, \
+ { 0x0141, /* LATIN CAPITAL LETTER L WITH STROKE */ \
+ 0x0142, /* LATIN SMALL LETTER L WITH STROKE */ }, \
+ { 0x0143, /* LATIN CAPITAL LETTER N WITH ACUTE */ \
+ 0x0144, /* LATIN SMALL LETTER N WITH ACUTE */ }, \
+ { 0x0147, /* LATIN CAPITAL LETTER N WITH CARON */ \
+ 0x0148, /* LATIN SMALL LETTER N WITH CARON */ }, \
+ { 0x0150, /* LATIN CAPITAL LETTER O WITH DOUBLE ACUTE */ \
+ 0x0151, /* LATIN SMALL LETTER O WITH DOUBLE ACUTE */ }, \
+ { 0x0154, /* LATIN CAPITAL LETTER R WITH ACUTE */ \
+ 0x0155, /* LATIN SMALL LETTER R WITH ACUTE */ }, \
+ { 0x0158, /* LATIN CAPITAL LETTER R WITH CARON */ \
+ 0x0159, /* LATIN SMALL LETTER R WITH CARON */ }, \
+ { 0x015A, /* LATIN CAPITAL LETTER S WITH ACUTE */ \
+ 0x015B, /* LATIN SMALL LETTER S WITH ACUTE */ }, \
+ { 0x015E, /* LATIN CAPITAL LETTER S WITH CEDILLA */ \
+ 0x015F, /* LATIN SMALL LETTER S WITH CEDILLA */ }, \
+ { 0x0160, /* LATIN CAPITAL LETTER S WITH CARON */ \
+ 0x0161, /* LATIN SMALL LETTER S WITH CARON */ }, \
+ { 0x0162, /* LATIN CAPITAL LETTER T WITH CEDILLA */ \
+ 0x0163, /* LATIN SMALL LETTER T WITH CEDILLA */ }, \
+ { 0x0164, /* LATIN CAPITAL LETTER T WITH CARON */ \
+ 0x0165, /* LATIN SMALL LETTER T WITH CARON */ }, \
+ { 0x016E, /* LATIN CAPITAL LETTER U WITH RING ABOVE */ \
+ 0x016F, /* LATIN SMALL LETTER U WITH RING ABOVE */ }, \
+ { 0x0170, /* LATIN CAPITAL LETTER U WITH DOUBLE ACUTE */ \
+ 0x0171, /* LATIN SMALL LETTER U WITH DOUBLE ACUTE */ }, \
+ { 0x0179, /* LATIN CAPITAL LETTER Z WITH ACUTE */ \
+ 0x017A, /* LATIN SMALL LETTER Z WITH ACUTE */ }, \
+ { 0x017B, /* LATIN CAPITAL LETTER Z WITH DOT ABOVE */ \
+ 0x017C, /* LATIN SMALL LETTER Z WITH DOT ABOVE */ }, \
+ { 0x017D, /* LATIN CAPITAL LETTER Z WITH CARON */ \
+ 0x017E, /* LATIN SMALL LETTER Z WITH CARON */ }, \
+ { 0x0000, 0x0000, }, \
+}
#ifndef __CHARSET_H_
#define __CHARSET_H_
+#include <linux/kernel.h>
#include <linux/types.h>
#define MAX_UTF8_PER_UTF16 3
/**
- * utf16_strlen() - Get the length of an utf16 string
+ * console_read_unicode() - read Unicode code point from console
*
- * Returns the number of 16 bit characters in an utf16 string, not
- * including the terminating NULL character.
+ * @code: pointer to store Unicode code point
+ * Return: 0 = success
+ */
+int console_read_unicode(s32 *code);
+
+/**
+ * utf8_get() - get next UTF-8 code point from buffer
+ *
+ * @src: pointer to current byte, updated to point to next byte
+ * Return: code point, or 0 for end of string, or -1 if no legal
+ * code point is found. In case of an error src points to
+ * the incorrect byte.
+ */
+s32 utf8_get(const char **src);
+
+/**
+ * utf8_put() - write UTF-8 code point to buffer
+ *
+ * @code: code point
+ * @dst: pointer to destination buffer, updated to next position
+ * Return: -1 if the input parameters are invalid
+ */
+int utf8_put(s32 code, char **dst);
+
+/**
+ * utf8_utf16_strnlen() - length of a truncated utf-8 string after conversion
+ * to utf-16
+ *
+ * @src: utf-8 string
+ * @count: maximum number of code points to convert
+ * Return: length in bytes after conversion to utf-16 without the
+ * trailing \0. If an invalid UTF-8 sequence is hit one
+ * word will be reserved for a replacement character.
+ */
+size_t utf8_utf16_strnlen(const char *src, size_t count);
+
+/**
+ * utf8_utf16_strlen() - length of a utf-8 string after conversion to utf-16
+ *
+ * @src: utf-8 string
+ * Return: length in bytes after conversion to utf-16 without the
+ * trailing \0. -1 if the utf-8 string is not valid.
+ */
+#define utf8_utf16_strlen(a) utf8_utf16_strnlen((a), SIZE_MAX)
+
+/**
+ * utf8_utf16_strncpy() - copy utf-8 string to utf-16 string
+ *
+ * @dst: destination buffer
+ * @src: source buffer
+ * @count: maximum number of code points to copy
+ * Return: -1 if the input parameters are invalid
+ */
+int utf8_utf16_strncpy(u16 **dst, const char *src, size_t count);
+
+/**
+ * utf8_utf16_strcpy() - copy utf-8 string to utf-16 string
+ *
+ * @dst: destination buffer
+ * @src: source buffer
+ * Return: -1 if the input parameters are invalid
+ */
+#define utf8_utf16_strcpy(d, s) utf8_utf16_strncpy((d), (s), SIZE_MAX)
+
+/**
+ * utf16_get() - get next UTF-16 code point from buffer
+ *
+ * @src: pointer to current word, updated to point to next word
+ * Return: code point, or 0 for end of string, or -1 if no legal
+ * code point is found. In case of an error src points to
+ * the incorrect word.
+ */
+s32 utf16_get(const u16 **src);
+
+/**
+ * utf16_put() - write UTF-16 code point to buffer
+ *
+ * @code: code point
+ * @dst: pointer to destination buffer, updated to next position
+ * Return: -1 if the input parameters are invalid
+ */
+int utf16_put(s32 code, u16 **dst);
+
+/**
+ * utf16_strnlen() - length of a truncated utf-16 string
*
- * @in the string to measure
- * @return the string length
+ * @src: utf-16 string
+ * @count: maximum number of code points to convert
+ * Return: length in code points. If an invalid UTF-16 sequence is
+ * hit one position will be reserved for a replacement
+ * character.
*/
-size_t utf16_strlen(const uint16_t *in);
+size_t utf16_strnlen(const u16 *src, size_t count);
/**
- * utf16_strnlen() - Get the length of a fixed-size utf16 string.
+ * utf16_utf8_strnlen() - length of a truncated utf-16 string after conversion
+ * to utf-8
*
- * Returns the number of 16 bit characters in an utf16 string,
- * not including the terminating NULL character, but at most
- * 'count' number of characters. In doing this, utf16_strnlen()
- * looks at only the first 'count' characters.
+ * @src: utf-16 string
+ * @count: maximum number of code points to convert
+ * Return: length in bytes after conversion to utf-8 without the
+ * trailing \0. If an invalid UTF-16 sequence is hit one
+ * byte will be reserved for a replacement character.
+ */
+size_t utf16_utf8_strnlen(const u16 *src, size_t count);
+
+/**
+ * utf16_utf8_strlen() - length of a utf-16 string after conversion to utf-8
*
- * @in the string to measure
- * @count the maximum number of characters to count
- * @return the string length, up to a maximum of 'count'
+ * @src: utf-16 string
+ * Return: length in bytes after conversion to utf-8 without the
+ * trailing \0. -1 if the utf-16 string is not valid.
*/
-size_t utf16_strnlen(const uint16_t *in, size_t count);
+#define utf16_utf8_strlen(a) utf16_utf8_strnlen((a), SIZE_MAX)
/**
- * utf16_strcpy() - UTF16 equivalent of strcpy()
+ * utf16_utf8_strncpy() - copy utf-16 string to utf-8 string
+ *
+ * @dst: destination buffer
+ * @src: source buffer
+ * @count: maximum number of code points to copy
+ * Return: -1 if the input parameters are invalid
*/
-uint16_t *utf16_strcpy(uint16_t *dest, const uint16_t *src);
+int utf16_utf8_strncpy(char **dst, const u16 *src, size_t count);
/**
- * utf16_strdup() - UTF16 equivalent of strdup()
+ * utf16_utf8_strcpy() - copy utf-16 string to utf-8 string
+ *
+ * @dst: destination buffer
+ * @src: source buffer
+ * Return: -1 if the input parameters are invalid
*/
-uint16_t *utf16_strdup(const uint16_t *s);
+#define utf16_utf8_strcpy(d, s) utf16_utf8_strncpy((d), (s), SIZE_MAX)
+
+/**
+ * utf_to_lower() - convert a Unicode letter to lower case
+ *
+ * @code: letter to convert
+ * Return: lower case letter or unchanged letter
+ */
+s32 utf_to_lower(const s32 code);
+
+/**
+ * utf_to_upper() - convert a Unicode letter to upper case
+ *
+ * @code: letter to convert
+ * Return: upper case letter or unchanged letter
+ */
+s32 utf_to_upper(const s32 code);
+
+/**
+ * u16_strlen - count non-zero words
+ *
+ * This function matches wsclen() if the -fshort-wchar compiler flag is set.
+ * In the EFI context we explicitly need a function handling u16 strings.
+ *
+ * @in: null terminated u16 string
+ * ReturnValue: number of non-zero words.
+ * This is not the number of utf-16 letters!
+ */
+size_t u16_strlen(const u16 *in);
+
+/**
+ * u16_strlen - count non-zero words
+ *
+ * This function matches wscnlen_s() if the -fshort-wchar compiler flag is set.
+ * In the EFI context we explicitly need a function handling u16 strings.
+ *
+ * @in: null terminated u16 string
+ * @count: maximum number of words to count
+ * ReturnValue: number of non-zero words.
+ * This is not the number of utf-16 letters!
+ */
+size_t u16_strnlen(const u16 *in, size_t count);
/**
* utf16_to_utf8() - Convert an utf16 string to utf8
*/
uint8_t *utf16_to_utf8(uint8_t *dest, const uint16_t *src, size_t size);
-/**
- * utf8_to_utf16() - Convert an utf8 string to utf16
- *
- * Converts up to 'size' characters of the utf16 string 'src' to utf8
- * written to the 'dest' buffer. Stops at 0x00.
- *
- * @dest the destination buffer to write the utf8 characters
- * @src the source utf16 string
- * @size maximum number of utf16 characters to convert
- * @return the pointer to the first unwritten byte in 'dest'
- */
-uint16_t *utf8_to_utf16(uint16_t *dest, const uint8_t *src, size_t size);
-
#endif /* __CHARSET_H_ */
*
* A driver that implements UCLASS_CLOCK is a clock provider. A provider will
* often implement multiple separate clocks, since the hardware it manages
- * often has this capability. clock_uclass.h describes the interface which
+ * often has this capability. clk-uclass.h describes the interface which
* clock providers must implement.
*
* Clock consumers/clients are the HW modules driven by the clock signals. This
#if defined(CONFIG_CMD_DHCP)
#if defined(CONFIG_EFI_LOADER)
/* http://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml */
-#if defined(CONFIG_ARM64)
+#if defined(CONFIG_ARM64) || defined(__aarch64__)
#define BOOTENV_EFI_PXE_ARCH "0xb"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"
-#elif defined(CONFIG_ARM)
+#elif defined(CONFIG_ARM) || defined(__arm__)
#define BOOTENV_EFI_PXE_ARCH "0xa"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000"
-#elif defined(CONFIG_X86)
-/* Always assume we're running 64bit */
+#elif defined(CONFIG_X86) || defined(__x86_64__)
#define BOOTENV_EFI_PXE_ARCH "0x7"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"
-#elif defined(CONFIG_CPU_RISCV_32)
+#elif defined(__i386__)
+#define BOOTENV_EFI_PXE_ARCH "0x6"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00006:UNDI:003000"
+#elif defined(CONFIG_CPU_RISCV_32) || ((defined(__riscv) && __riscv_xlen == 32))
#define BOOTENV_EFI_PXE_ARCH "0x19"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00025:UNDI:003000"
-#elif defined(CONFIG_CPU_RISCV_64)
+#elif defined(CONFIG_CPU_RISCV_64) || ((defined(__riscv) && __riscv_xlen == 64))
#define BOOTENV_EFI_PXE_ARCH "0x1b"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00027:UNDI:003000"
+#elif defined(CONFIG_SANDBOX)
+# error "sandbox EFI support is only supported on ARM and x86"
#else
#error Please specify an EFI client identifier
#endif
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
-#endif /* SCSCI */
+#endif /* CONFIG_SCSI_AHCI */
#endif /* CONFIG_PCI */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
#endif /* SCSI */
#endif /* CONFIG_PCI */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
#endif
#endif /* CONFIG_PCI */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
#endif
#endif /* CONFIG_PCI */
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_QE
-#define CONFIG_U_QE
/* Default address of microcode for the Linux FMan driver */
#if defined(CONFIG_SPIFLASH)
/*
#ifdef CONFIG_TARGET_T1024RDB
#define CONFIG_QE
-#define CONFIG_U_QE
#endif
/* Default address of microcode for the Linux FMan driver */
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_DPAA_PME
#define CONFIG_QE
-#define CONFIG_U_QE
/* Default address of microcode for the Linux Fman driver */
#if defined(CONFIG_SPIFLASH)
/*
* Serial Driver info
*/
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
+#if !CONFIG_IS_ENABLED(DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
/* NAND support */
#ifdef CONFIG_NAND
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H
+#define __CONFIG_GARDENA_SMART_GATEWAY_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+#ifdef CONFIG_BOOT_RAM
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+ 230400, 500000, 1500000 }
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x80400000
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_CBSIZE 512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/* Environment settings */
+#define CONFIG_ENV_OFFSET 0x80000
+#define CONFIG_ENV_SIZE (64 << 10)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * Environment is right behind U-Boot in flash. Make sure U-Boot
+ * doesn't grow into the environment area.
+ */
+#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
+
+#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */
/* CPU Timer rate */
#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
-/* Cache Configuration */
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-
/*----------------------------------------------------------------------
* Memory Layout
*/
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __CONFIG_LINKIT_SMART_7688_H
+#define __CONFIG_LINKIT_SMART_7688_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+#ifdef CONFIG_BOOT_RAM
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+ 230400, 500000, 1500000 }
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x80400000
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_CBSIZE 512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/* Environment settings */
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SIZE (16 << 10)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+
+/*
+ * Environment is right behind U-Boot in flash. Make sure U-Boot
+ * doesn't grow into the environment area.
+ */
+#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
+
+#endif /* __CONFIG_LINKIT_SMART_7688_H */
#include "ls1012a_common.h"
/* Board Rev*/
-#define BOARD_REV_A 0x0
-#define BOARD_REV_B 0x200
-
+#define BOARD_REV_A_B 0x0
+#define BOARD_REV_C 0x00080000
+#define BOARD_REV_MASK 0x001A0000
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
-#define CONFIG_U_QE
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#endif
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
-#define CONFIG_U_QE
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#endif
#endif
#endif
-/* QE */
-#ifndef SPL_NO_QE
-#if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT)
-#define CONFIG_U_QE
-#endif
-#endif
-
/* SATA */
#ifndef SPL_NO_SATA
#ifndef CONFIG_CMD_EXT2
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
- func(SCSI, scsi, 0) \
- func(DHCP, dhcp, na)
+ func(SCSI, scsi, 0)
#include <config_distro_bootcmd.h>
#endif
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
- func(SCSI, scsi, 0) \
- func(DHCP, dhcp, na)
+ func(SCSI, scsi, 0)
#include <config_distro_bootcmd.h>
#ifdef CONFIG_QSPI_BOOT
/* CPU Timer rate */
#define CONFIG_SYS_MIPS_TIMER_FREQ 100000000
-/* Cache Configuration */
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-
/*----------------------------------------------------------------------
* Memory Layout
*/
/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
#define CONFIG_SYS_HZ 1000
-/* For block devices, QEMU emulates an ICH9 AHCI controller over PCI */
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 6
-
-/* QEMU emulates the ARM AMBA PL031 RTC */
-#define CONFIG_SYS_RTC_PL031_BASE 0x09010000
-
/* Environment options */
#define CONFIG_ENV_SIZE SZ_64K
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_SD_BOOT
/* u-boot env in sd/mmc card */
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0"
-#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_SIZE 0x4000
/* bootstrap + u-boot + env in sd card */
-#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d27_som1_ek.dtb; " \
- "fatload mmc 0:1 0x22000000 zImage; " \
+#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d27_som1_ek.dtb; " \
+ "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \
"bootz 0x22000000 - 0x21000000"
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
#endif
#ifdef CONFIG_QSPI_BOOT
/* bootstrap + u-boot + env in sd card */
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "fatload mmc 1:1 0x21000000 at91-sama5d2_xplained.dtb; " \
- "fatload mmc 1:1 0x22000000 zImage; " \
+#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d2_xplained.dtb; " \
+ "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \
"bootz 0x22000000 - 0x21000000"
#elif CONFIG_SPI_BOOT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
#endif
#endif /* CONFIG_PCI */
#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
#endif
/* Generic TPM interfaced through LPC bus */
# define CONFIG_SYS_EEPROM_SIZE (64 * 1024)
#endif
-#ifdef CONFIG_SATA_CEVA
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
#define CONFIG_CLOCKS
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_VXWORKS
#undef CONFIG_BOOTM_LINUX
-#undef CONFIG_BOARD_LATE_INIT
/* BOOTP options */
#undef CONFIG_BOOTP_BOOTFILESIZE
/* Boot configuration */
#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
-/* Distro boot enablement */
-
#ifdef CONFIG_SPL_BUILD
#define BOOTENV
#else
#define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds"
-/* Commands */
-
-/* SPL part */
-
/* MMC support */
#ifdef CONFIG_MMC_SDHCI_ZYNQ
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
CONFIG_SYS_SPI_ARGS_SIZE)
#endif
-/* for booting directly linux */
-
/* SP location before relocation, must use scratch RAM */
#define CONFIG_SPL_TEXT_BASE 0x0
/* Undef unneeded configs */
#undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_BOARD_LATE_INIT
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50
-#define CONFIG_DISPLAY
-#define CONFIG_I2C_EDID
#include <configs/zynq-common.h>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Constant CP1250 contains the Unicode code points for characters 0x80 - 0xff
+ * of the code page 1250.
+ */
+#define CP1250 { \
+ 0x20ac, 0x0000, 0x201a, 0x0000, \
+ 0x201e, 0x2026, 0x2020, 0x2021, \
+ 0x0000, 0x2030, 0x0160, 0x2039, \
+ 0x015a, 0x0164, 0x017d, 0x0179, \
+ 0x0000, 0x2018, 0x2019, 0x201c, \
+ 0x201d, 0x2022, 0x2013, 0x2014, \
+ 0x0000, 0x2122, 0x0161, 0x203a, \
+ 0x015b, 0x0165, 0x017e, 0x017a, \
+ 0x00a0, 0x02c7, 0x02d8, 0x0141, \
+ 0x00a4, 0x0104, 0x00a6, 0x00a7, \
+ 0x00a8, 0x00a9, 0x015e, 0x00ab, \
+ 0x00ac, 0x00ad, 0x00ae, 0x017b, \
+ 0x00b0, 0x00b1, 0x02db, 0x0142, \
+ 0x00b4, 0x00b5, 0x00b6, 0x00b7, \
+ 0x00b8, 0x0105, 0x015f, 0x00bb, \
+ 0x013d, 0x02dd, 0x013e, 0x017c, \
+ 0x0154, 0x00c1, 0x00c2, 0x0102, \
+ 0x00c4, 0x0139, 0x0106, 0x00c7, \
+ 0x010c, 0x00c9, 0x0118, 0x00cb, \
+ 0x011a, 0x00cd, 0x00ce, 0x010e, \
+ 0x0110, 0x0143, 0x0147, 0x00d3, \
+ 0x00d4, 0x0150, 0x00d6, 0x00d7, \
+ 0x0158, 0x016e, 0x00da, 0x0170, \
+ 0x00dc, 0x00dd, 0x0162, 0x00df, \
+ 0x0155, 0x00e1, 0x00e2, 0x0103, \
+ 0x00e4, 0x013a, 0x0107, 0x00e7, \
+ 0x010d, 0x00e9, 0x0119, 0x00eb, \
+ 0x011b, 0x00ed, 0x00ee, 0x010f, \
+ 0x0111, 0x0144, 0x0148, 0x00f3, \
+ 0x00f4, 0x0151, 0x00f6, 0x00f7, \
+ 0x0159, 0x016f, 0x00fa, 0x0171, \
+ 0x00fc, 0x00fd, 0x0163, 0x02d9, \
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Constant CP437 contains the Unicode code points for characters 0x80 - 0xff
+ * of the code page 437.
+ */
+#define CP437 { \
+ 0x00c7, 0x00fc, 0x00e9, 0x00e2, \
+ 0x00e4, 0x00e0, 0x00e5, 0x00e7, \
+ 0x00ea, 0x00eb, 0x00e8, 0x00ef, \
+ 0x00ee, 0x00ec, 0x00c4, 0x00c5, \
+ 0x00c9, 0x00e6, 0x00c6, 0x00f4, \
+ 0x00f6, 0x00f2, 0x00fb, 0x00f9, \
+ 0x00ff, 0x00d6, 0x00dc, 0x00a2, \
+ 0x00a3, 0x00a5, 0x20a7, 0x0192, \
+ 0x00e1, 0x00ed, 0x00f3, 0x00fa, \
+ 0x00f1, 0x00d1, 0x00aa, 0x00ba, \
+ 0x00bf, 0x2310, 0x00ac, 0x00bd, \
+ 0x00bc, 0x00a1, 0x00ab, 0x00bb, \
+ 0x2591, 0x2592, 0x2593, 0x2502, \
+ 0x2524, 0x2561, 0x2562, 0x2556, \
+ 0x2555, 0x2563, 0x2551, 0x2557, \
+ 0x255d, 0x255c, 0x255b, 0x2510, \
+ 0x2514, 0x2534, 0x252c, 0x251c, \
+ 0x2500, 0x253c, 0x255e, 0x255f, \
+ 0x255a, 0x2554, 0x2569, 0x2566, \
+ 0x2560, 0x2550, 0x256c, 0x2567, \
+ 0x2568, 0x2564, 0x2565, 0x2559, \
+ 0x2558, 0x2552, 0x2553, 0x256b, \
+ 0x256a, 0x2518, 0x250c, 0x2588, \
+ 0x2584, 0x258c, 0x2590, 0x2580, \
+ 0x03b1, 0x00df, 0x0393, 0x03c0, \
+ 0x03a3, 0x03c3, 0x00b5, 0x03c4, \
+ 0x03a6, 0x0398, 0x03a9, 0x03b4, \
+ 0x221e, 0x03c6, 0x03b5, 0x2229, \
+ 0x2261, 0x00b1, 0x2265, 0x2264, \
+ 0x2320, 0x2321, 0x00f7, 0x2248, \
+ 0x00b0, 0x2219, 0x00b7, 0x221a, \
+ 0x207f, 0x00b2, 0x25a0, 0x00a0, \
+}
int cpsw_register(struct cpsw_platform_data *data);
int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr);
+int cpsw_get_slave_phy_addr(struct udevice *dev, int slave);
#endif /* _CPSW_H_ */
#ifndef _DM_H_
#define _DM_H_
-#include <dm/ofnode.h>
#include <dm/device.h>
#include <dm/fdtaddr.h>
#include <dm/ofnode.h>
*/
bool of_machine_is_compatible(const char *compat);
+/**
+ * dev_disable_by_path() - Disable a device given its device tree path
+ *
+ * @path: The device tree path identifying the device to be disabled
+ * @return 0 on success, -ve on error
+ */
+int dev_disable_by_path(const char *path);
+
+/**
+ * dev_enable_by_path() - Enable a device given its device tree path
+ *
+ * @path: The device tree path identifying the device to be enabled
+ * @return 0 on success, -ve on error
+ */
+int dev_enable_by_path(const char *path);
+
/**
* device_is_on_pci_bus - Test if a device is on a PCI bus
*
* @return true if OK, false if the compatible is not found
*/
int ofnode_device_is_compatible(ofnode node, const char *compat);
+
+/**
+ * ofnode_write_prop() - Set a property of a ofnode
+ *
+ * Note that the value passed to the function is *not* allocated by the
+ * function itself, but must be allocated by the caller if necessary.
+ *
+ * @node: The node for whose property should be set
+ * @propname: The name of the property to set
+ * @len: The length of the new value of the property
+ * @value: The new value of the property (must be valid prior to calling
+ * the function)
+ * @return 0 if successful, -ve on error
+ */
+int ofnode_write_prop(ofnode node, const char *propname, int len,
+ const void *value);
+
+/**
+ * ofnode_write_string() - Set a string property of a ofnode
+ *
+ * Note that the value passed to the function is *not* allocated by the
+ * function itself, but must be allocated by the caller if necessary.
+ *
+ * @node: The node for whose string property should be set
+ * @propname: The name of the string property to set
+ * @value: The new value of the string property (must be valid prior to
+ * calling the function)
+ * @return 0 if successful, -ve on error
+ */
+int ofnode_write_string(ofnode node, const char *propname, const char *value);
+
+/**
+ * ofnode_set_enabled() - Enable or disable a device tree node given by its
+ * ofnode
+ *
+ * This function effectively sets the node's "status" property to either "okay"
+ * or "disable", hence making it available for driver model initialization or
+ * not.
+ *
+ * @node: The node to enable
+ * @value: Flag that tells the function to either disable or enable the
+ * node
+ * @return 0 if successful, -ve on error
+ */
+int ofnode_set_enabled(ofnode node, bool value);
+
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
+ *
+ * Structure for use with U_BOOT_DEVICE for pl022 SPI devices or to use
+ * in ofdata_to_platdata.
+ */
+
+#ifndef __PL022_SPI_H__
+#define __PL022_SPI_H__
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+#include <clk.h>
+#endif
+#include <fdtdec.h>
+
+struct pl022_spi_pdata {
+ fdt_addr_t addr;
+ fdt_size_t size;
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct clk clk;
+#else
+ unsigned int freq;
+#endif
+};
+
+#endif
UCLASS_ADC, /* Analog-to-digital converter */
UCLASS_AHCI, /* SATA disk controller */
UCLASS_BLK, /* Block device */
+ UCLASS_BOARD, /* Device information from hardware */
UCLASS_CLK, /* Clock source, e.g. used by peripherals */
UCLASS_CPU, /* CPU, typically part of an SoC */
UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_DMA, /* Direct Memory Access */
UCLASS_EFI, /* EFI managed devices */
UCLASS_ETH, /* Ethernet device */
+ UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
UCLASS_GPIO, /* Bank of general-purpose I/O pins */
UCLASS_FIRMWARE, /* Firmware */
UCLASS_I2C, /* I2C bus */
UCLASS_VIDEO, /* Video or LCD device */
UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */
UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */
+ UCLASS_VIDEO_OSD, /* On-screen display */
+ UCLASS_W1, /* Dallas 1-Wire bus */
+ UCLASS_W1_EEPROM, /* one-wire EEPROMs */
UCLASS_WDT, /* Watchdot Timer driver */
UCLASS_COUNT,
--- /dev/null
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
+#define _DT_BINDINGS_CLK_SUN4I_A10_H_
+
+#define CLK_HOSC 1
+#define CLK_PLL_VIDEO0_2X 9
+#define CLK_PLL_VIDEO1_2X 18
+#define CLK_CPU 20
+
+/* AHB Gates */
+#define CLK_AHB_OTG 26
+#define CLK_AHB_EHCI0 27
+#define CLK_AHB_OHCI0 28
+#define CLK_AHB_EHCI1 29
+#define CLK_AHB_OHCI1 30
+#define CLK_AHB_SS 31
+#define CLK_AHB_DMA 32
+#define CLK_AHB_BIST 33
+#define CLK_AHB_MMC0 34
+#define CLK_AHB_MMC1 35
+#define CLK_AHB_MMC2 36
+#define CLK_AHB_MMC3 37
+#define CLK_AHB_MS 38
+#define CLK_AHB_NAND 39
+#define CLK_AHB_SDRAM 40
+#define CLK_AHB_ACE 41
+#define CLK_AHB_EMAC 42
+#define CLK_AHB_TS 43
+#define CLK_AHB_SPI0 44
+#define CLK_AHB_SPI1 45
+#define CLK_AHB_SPI2 46
+#define CLK_AHB_SPI3 47
+#define CLK_AHB_PATA 48
+#define CLK_AHB_SATA 49
+#define CLK_AHB_GPS 50
+#define CLK_AHB_HSTIMER 51
+#define CLK_AHB_VE 52
+#define CLK_AHB_TVD 53
+#define CLK_AHB_TVE0 54
+#define CLK_AHB_TVE1 55
+#define CLK_AHB_LCD0 56
+#define CLK_AHB_LCD1 57
+#define CLK_AHB_CSI0 58
+#define CLK_AHB_CSI1 59
+#define CLK_AHB_HDMI0 60
+#define CLK_AHB_HDMI1 61
+#define CLK_AHB_DE_BE0 62
+#define CLK_AHB_DE_BE1 63
+#define CLK_AHB_DE_FE0 64
+#define CLK_AHB_DE_FE1 65
+#define CLK_AHB_GMAC 66
+#define CLK_AHB_MP 67
+#define CLK_AHB_GPU 68
+
+/* APB0 Gates */
+#define CLK_APB0_CODEC 69
+#define CLK_APB0_SPDIF 70
+#define CLK_APB0_I2S0 71
+#define CLK_APB0_AC97 72
+#define CLK_APB0_I2S1 73
+#define CLK_APB0_PIO 74
+#define CLK_APB0_IR0 75
+#define CLK_APB0_IR1 76
+#define CLK_APB0_I2S2 77
+#define CLK_APB0_KEYPAD 78
+
+/* APB1 Gates */
+#define CLK_APB1_I2C0 79
+#define CLK_APB1_I2C1 80
+#define CLK_APB1_I2C2 81
+#define CLK_APB1_I2C3 82
+#define CLK_APB1_CAN 83
+#define CLK_APB1_SCR 84
+#define CLK_APB1_PS20 85
+#define CLK_APB1_PS21 86
+#define CLK_APB1_I2C4 87
+#define CLK_APB1_UART0 88
+#define CLK_APB1_UART1 89
+#define CLK_APB1_UART2 90
+#define CLK_APB1_UART3 91
+#define CLK_APB1_UART4 92
+#define CLK_APB1_UART5 93
+#define CLK_APB1_UART6 94
+#define CLK_APB1_UART7 95
+
+/* IP clocks */
+#define CLK_NAND 96
+#define CLK_MS 97
+#define CLK_MMC0 98
+#define CLK_MMC0_OUTPUT 99
+#define CLK_MMC0_SAMPLE 100
+#define CLK_MMC1 101
+#define CLK_MMC1_OUTPUT 102
+#define CLK_MMC1_SAMPLE 103
+#define CLK_MMC2 104
+#define CLK_MMC2_OUTPUT 105
+#define CLK_MMC2_SAMPLE 106
+#define CLK_MMC3 107
+#define CLK_MMC3_OUTPUT 108
+#define CLK_MMC3_SAMPLE 109
+#define CLK_TS 110
+#define CLK_SS 111
+#define CLK_SPI0 112
+#define CLK_SPI1 113
+#define CLK_SPI2 114
+#define CLK_PATA 115
+#define CLK_IR0 116
+#define CLK_IR1 117
+#define CLK_I2S0 118
+#define CLK_AC97 119
+#define CLK_SPDIF 120
+#define CLK_KEYPAD 121
+#define CLK_SATA 122
+#define CLK_USB_OHCI0 123
+#define CLK_USB_OHCI1 124
+#define CLK_USB_PHY 125
+#define CLK_GPS 126
+#define CLK_SPI3 127
+#define CLK_I2S1 128
+#define CLK_I2S2 129
+
+/* DRAM Gates */
+#define CLK_DRAM_VE 130
+#define CLK_DRAM_CSI0 131
+#define CLK_DRAM_CSI1 132
+#define CLK_DRAM_TS 133
+#define CLK_DRAM_TVD 134
+#define CLK_DRAM_TVE0 135
+#define CLK_DRAM_TVE1 136
+#define CLK_DRAM_OUT 137
+#define CLK_DRAM_DE_FE1 138
+#define CLK_DRAM_DE_FE0 139
+#define CLK_DRAM_DE_BE0 140
+#define CLK_DRAM_DE_BE1 141
+#define CLK_DRAM_MP 142
+#define CLK_DRAM_ACE 143
+
+/* Display Engine Clocks */
+#define CLK_DE_BE0 144
+#define CLK_DE_BE1 145
+#define CLK_DE_FE0 146
+#define CLK_DE_FE1 147
+#define CLK_DE_MP 148
+#define CLK_TCON0_CH0 149
+#define CLK_TCON1_CH0 150
+#define CLK_CSI_SCLK 151
+#define CLK_TVD_SCLK2 152
+#define CLK_TVD 153
+#define CLK_TCON0_CH1_SCLK2 154
+#define CLK_TCON0_CH1 155
+#define CLK_TCON1_CH1_SCLK2 156
+#define CLK_TCON1_CH1 157
+#define CLK_CSI0 158
+#define CLK_CSI1 159
+#define CLK_CODEC 160
+#define CLK_VE 161
+#define CLK_AVS 162
+#define CLK_ACE 163
+#define CLK_HDMI 164
+#define CLK_GPU 165
+
+#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
--- /dev/null
+/*
+ * Copyright 2016 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN5I_H_
+#define _DT_BINDINGS_CLK_SUN5I_H_
+
+#define CLK_HOSC 1
+
+#define CLK_PLL_VIDEO0_2X 9
+
+#define CLK_PLL_VIDEO1_2X 16
+#define CLK_CPU 17
+
+#define CLK_AHB_OTG 23
+#define CLK_AHB_EHCI 24
+#define CLK_AHB_OHCI 25
+#define CLK_AHB_SS 26
+#define CLK_AHB_DMA 27
+#define CLK_AHB_BIST 28
+#define CLK_AHB_MMC0 29
+#define CLK_AHB_MMC1 30
+#define CLK_AHB_MMC2 31
+#define CLK_AHB_NAND 32
+#define CLK_AHB_SDRAM 33
+#define CLK_AHB_EMAC 34
+#define CLK_AHB_TS 35
+#define CLK_AHB_SPI0 36
+#define CLK_AHB_SPI1 37
+#define CLK_AHB_SPI2 38
+#define CLK_AHB_GPS 39
+#define CLK_AHB_HSTIMER 40
+#define CLK_AHB_VE 41
+#define CLK_AHB_TVE 42
+#define CLK_AHB_LCD 43
+#define CLK_AHB_CSI 44
+#define CLK_AHB_HDMI 45
+#define CLK_AHB_DE_BE 46
+#define CLK_AHB_DE_FE 47
+#define CLK_AHB_IEP 48
+#define CLK_AHB_GPU 49
+#define CLK_APB0_CODEC 50
+#define CLK_APB0_SPDIF 51
+#define CLK_APB0_I2S 52
+#define CLK_APB0_PIO 53
+#define CLK_APB0_IR 54
+#define CLK_APB0_KEYPAD 55
+#define CLK_APB1_I2C0 56
+#define CLK_APB1_I2C1 57
+#define CLK_APB1_I2C2 58
+#define CLK_APB1_UART0 59
+#define CLK_APB1_UART1 60
+#define CLK_APB1_UART2 61
+#define CLK_APB1_UART3 62
+#define CLK_NAND 63
+#define CLK_MMC0 64
+#define CLK_MMC1 65
+#define CLK_MMC2 66
+#define CLK_TS 67
+#define CLK_SS 68
+#define CLK_SPI0 69
+#define CLK_SPI1 70
+#define CLK_SPI2 71
+#define CLK_IR 72
+#define CLK_I2S 73
+#define CLK_SPDIF 74
+#define CLK_KEYPAD 75
+#define CLK_USB_OHCI 76
+#define CLK_USB_PHY0 77
+#define CLK_USB_PHY1 78
+#define CLK_GPS 79
+#define CLK_DRAM_VE 80
+#define CLK_DRAM_CSI 81
+#define CLK_DRAM_TS 82
+#define CLK_DRAM_TVE 83
+#define CLK_DRAM_DE_FE 84
+#define CLK_DRAM_DE_BE 85
+#define CLK_DRAM_ACE 86
+#define CLK_DRAM_IEP 87
+#define CLK_DE_BE 88
+#define CLK_DE_FE 89
+#define CLK_TCON_CH0 90
+
+#define CLK_TCON_CH1 92
+#define CLK_CSI 93
+#define CLK_VE 94
+#define CLK_CODEC 95
+#define CLK_AVS 96
+#define CLK_HDMI 97
+#define CLK_GPU 98
+
+#define CLK_IEP 100
+
+#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
+#define _DT_BINDINGS_CLK_SUN6I_A31_H_
+
+#define CLK_PLL_VIDEO0_2X 7
+
+#define CLK_PLL_PERIPH 10
+
+#define CLK_PLL_VIDEO1_2X 13
+
+#define CLK_CPU 18
+
+#define CLK_AHB1_MIPIDSI 23
+#define CLK_AHB1_SS 24
+#define CLK_AHB1_DMA 25
+#define CLK_AHB1_MMC0 26
+#define CLK_AHB1_MMC1 27
+#define CLK_AHB1_MMC2 28
+#define CLK_AHB1_MMC3 29
+#define CLK_AHB1_NAND1 30
+#define CLK_AHB1_NAND0 31
+#define CLK_AHB1_SDRAM 32
+#define CLK_AHB1_EMAC 33
+#define CLK_AHB1_TS 34
+#define CLK_AHB1_HSTIMER 35
+#define CLK_AHB1_SPI0 36
+#define CLK_AHB1_SPI1 37
+#define CLK_AHB1_SPI2 38
+#define CLK_AHB1_SPI3 39
+#define CLK_AHB1_OTG 40
+#define CLK_AHB1_EHCI0 41
+#define CLK_AHB1_EHCI1 42
+#define CLK_AHB1_OHCI0 43
+#define CLK_AHB1_OHCI1 44
+#define CLK_AHB1_OHCI2 45
+#define CLK_AHB1_VE 46
+#define CLK_AHB1_LCD0 47
+#define CLK_AHB1_LCD1 48
+#define CLK_AHB1_CSI 49
+#define CLK_AHB1_HDMI 50
+#define CLK_AHB1_BE0 51
+#define CLK_AHB1_BE1 52
+#define CLK_AHB1_FE0 53
+#define CLK_AHB1_FE1 54
+#define CLK_AHB1_MP 55
+#define CLK_AHB1_GPU 56
+#define CLK_AHB1_DEU0 57
+#define CLK_AHB1_DEU1 58
+#define CLK_AHB1_DRC0 59
+#define CLK_AHB1_DRC1 60
+
+#define CLK_APB1_CODEC 61
+#define CLK_APB1_SPDIF 62
+#define CLK_APB1_DIGITAL_MIC 63
+#define CLK_APB1_PIO 64
+#define CLK_APB1_DAUDIO0 65
+#define CLK_APB1_DAUDIO1 66
+
+#define CLK_APB2_I2C0 67
+#define CLK_APB2_I2C1 68
+#define CLK_APB2_I2C2 69
+#define CLK_APB2_I2C3 70
+#define CLK_APB2_UART0 71
+#define CLK_APB2_UART1 72
+#define CLK_APB2_UART2 73
+#define CLK_APB2_UART3 74
+#define CLK_APB2_UART4 75
+#define CLK_APB2_UART5 76
+
+#define CLK_NAND0 77
+#define CLK_NAND1 78
+#define CLK_MMC0 79
+#define CLK_MMC0_SAMPLE 80
+#define CLK_MMC0_OUTPUT 81
+#define CLK_MMC1 82
+#define CLK_MMC1_SAMPLE 83
+#define CLK_MMC1_OUTPUT 84
+#define CLK_MMC2 85
+#define CLK_MMC2_SAMPLE 86
+#define CLK_MMC2_OUTPUT 87
+#define CLK_MMC3 88
+#define CLK_MMC3_SAMPLE 89
+#define CLK_MMC3_OUTPUT 90
+#define CLK_TS 91
+#define CLK_SS 92
+#define CLK_SPI0 93
+#define CLK_SPI1 94
+#define CLK_SPI2 95
+#define CLK_SPI3 96
+#define CLK_DAUDIO0 97
+#define CLK_DAUDIO1 98
+#define CLK_SPDIF 99
+#define CLK_USB_PHY0 100
+#define CLK_USB_PHY1 101
+#define CLK_USB_PHY2 102
+#define CLK_USB_OHCI0 103
+#define CLK_USB_OHCI1 104
+#define CLK_USB_OHCI2 105
+
+#define CLK_DRAM_VE 110
+#define CLK_DRAM_CSI_ISP 111
+#define CLK_DRAM_TS 112
+#define CLK_DRAM_DRC0 113
+#define CLK_DRAM_DRC1 114
+#define CLK_DRAM_DEU0 115
+#define CLK_DRAM_DEU1 116
+#define CLK_DRAM_FE0 117
+#define CLK_DRAM_FE1 118
+#define CLK_DRAM_BE0 119
+#define CLK_DRAM_BE1 120
+#define CLK_DRAM_MP 121
+
+#define CLK_BE0 122
+#define CLK_BE1 123
+#define CLK_FE0 124
+#define CLK_FE1 125
+#define CLK_MP 126
+#define CLK_LCD0_CH0 127
+#define CLK_LCD1_CH0 128
+#define CLK_LCD0_CH1 129
+#define CLK_LCD1_CH1 130
+#define CLK_CSI0_SCLK 131
+#define CLK_CSI0_MCLK 132
+#define CLK_CSI1_MCLK 133
+#define CLK_VE 134
+#define CLK_CODEC 135
+#define CLK_AVS 136
+#define CLK_DIGITAL_MIC 137
+#define CLK_HDMI 138
+#define CLK_HDMI_DDC 139
+#define CLK_PS 140
+
+#define CLK_MIPI_DSI 143
+#define CLK_MIPI_DSI_DPHY 144
+#define CLK_MIPI_CSI_DPHY 145
+#define CLK_IEP_DRC0 146
+#define CLK_IEP_DRC1 147
+#define CLK_IEP_DEU0 148
+#define CLK_IEP_DEU1 149
+#define CLK_GPU_CORE 150
+#define CLK_GPU_MEMORY 151
+#define CLK_GPU_HYD 152
+#define CLK_ATS 153
+#define CLK_TRACE 154
+
+#define CLK_OUT_A 155
+#define CLK_OUT_B 156
+#define CLK_OUT_C 157
+
+#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
+#define _DT_BINDINGS_CLK_SUN7I_A20_H_
+
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+
+#define CLK_MBUS 166
+#define CLK_HDMI1_SLOW 167
+#define CLK_HDMI1 168
+#define CLK_OUT_A 169
+#define CLK_OUT_B 170
+
+#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN4I_A10_H
+#define _DT_BINDINGS_RST_SUN4I_A10_H
+
+#define RST_USB_PHY0 1
+#define RST_USB_PHY1 2
+#define RST_USB_PHY2 3
+#define RST_GPS 4
+#define RST_DE_BE0 5
+#define RST_DE_BE1 6
+#define RST_DE_FE0 7
+#define RST_DE_FE1 8
+#define RST_DE_MP 9
+#define RST_TVE0 10
+#define RST_TCON0 11
+#define RST_TVE1 12
+#define RST_TCON1 13
+#define RST_CSI0 14
+#define RST_CSI1 15
+#define RST_VE 16
+#define RST_ACE 17
+#define RST_LVDS 18
+#define RST_GPU 19
+#define RST_HDMI_H 20
+#define RST_HDMI_SYS 21
+#define RST_HDMI_AUDIO_DMA 22
+
+#endif /* DT_BINDINGS_RST_SUN4I_A10_H */
--- /dev/null
+/*
+ * Copyright 2016 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _RST_SUN5I_H_
+#define _RST_SUN5I_H_
+
+#define RST_USB_PHY0 0
+#define RST_USB_PHY1 1
+#define RST_GPS 2
+#define RST_DE_BE 3
+#define RST_DE_FE 4
+#define RST_TVE 5
+#define RST_LCD 6
+#define RST_CSI 7
+#define RST_VE 8
+#define RST_GPU 9
+#define RST_IEP 10
+
+#endif /* _RST_SUN5I_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_
+#define _DT_BINDINGS_RST_SUN6I_A31_H_
+
+#define RST_USB_PHY0 0
+#define RST_USB_PHY1 1
+#define RST_USB_PHY2 2
+
+#define RST_AHB1_MIPI_DSI 3
+#define RST_AHB1_SS 4
+#define RST_AHB1_DMA 5
+#define RST_AHB1_MMC0 6
+#define RST_AHB1_MMC1 7
+#define RST_AHB1_MMC2 8
+#define RST_AHB1_MMC3 9
+#define RST_AHB1_NAND1 10
+#define RST_AHB1_NAND0 11
+#define RST_AHB1_SDRAM 12
+#define RST_AHB1_EMAC 13
+#define RST_AHB1_TS 14
+#define RST_AHB1_HSTIMER 15
+#define RST_AHB1_SPI0 16
+#define RST_AHB1_SPI1 17
+#define RST_AHB1_SPI2 18
+#define RST_AHB1_SPI3 19
+#define RST_AHB1_OTG 20
+#define RST_AHB1_EHCI0 21
+#define RST_AHB1_EHCI1 22
+#define RST_AHB1_OHCI0 23
+#define RST_AHB1_OHCI1 24
+#define RST_AHB1_OHCI2 25
+#define RST_AHB1_VE 26
+#define RST_AHB1_LCD0 27
+#define RST_AHB1_LCD1 28
+#define RST_AHB1_CSI 29
+#define RST_AHB1_HDMI 30
+#define RST_AHB1_BE0 31
+#define RST_AHB1_BE1 32
+#define RST_AHB1_FE0 33
+#define RST_AHB1_FE1 34
+#define RST_AHB1_MP 35
+#define RST_AHB1_GPU 36
+#define RST_AHB1_DEU0 37
+#define RST_AHB1_DEU1 38
+#define RST_AHB1_DRC0 39
+#define RST_AHB1_DRC1 40
+#define RST_AHB1_LVDS 41
+
+#define RST_APB1_CODEC 42
+#define RST_APB1_SPDIF 43
+#define RST_APB1_DIGITAL_MIC 44
+#define RST_APB1_DAUDIO0 45
+#define RST_APB1_DAUDIO1 46
+#define RST_APB2_I2C0 47
+#define RST_APB2_I2C1 48
+#define RST_APB2_I2C2 49
+#define RST_APB2_I2C3 50
+#define RST_APB2_UART0 51
+#define RST_APB2_UART1 52
+#define RST_APB2_UART2 53
+#define RST_APB2_UART3 54
+#define RST_APB2_UART4 55
+#define RST_APB2_UART5 56
+
+#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Extensible Firmware Interface
* Based on 'Extensible Firmware Interface Specification' version 0.9,
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Extensible Firmware Interface
* Based on 'Extensible Firmware Interface Specification' version 0.9,
EFI_TIMER_RELATIVE = 2
};
+#define efi_intn_t ssize_t
#define efi_uintn_t size_t
typedef uint16_t *efi_string_t;
EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3, \
0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
-struct efi_configuration_table
-{
+struct efi_configuration_table {
efi_guid_t guid;
void *table;
};
u16 *fw_vendor; /* physical addr of wchar_t vendor string */
u32 fw_revision;
efi_handle_t con_in_handle;
- struct efi_simple_input_interface *con_in;
+ struct efi_simple_text_input_protocol *con_in;
efi_handle_t con_out_handle;
struct efi_simple_text_output_protocol *con_out;
efi_handle_t stderr_handle;
unsigned int image_code_type;
unsigned int image_data_type;
unsigned long unload;
-
- /* Below are efi loader private fields */
-#ifdef CONFIG_EFI_LOADER
- void *reloc_base;
- aligned_u64 reloc_size;
- efi_status_t exit_status;
- struct jmp_buf_data exit_jmp;
-#endif
};
#define DEVICE_PATH_GUID \
EFI_GUID(0x09576e91, 0x6d3f, 0x11d2, \
- 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b )
+ 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
#define DEVICE_PATH_TYPE_END 0x7f
# define DEVICE_PATH_SUB_TYPE_INSTANCE_END 0x01
EFI_GUID(0x964e5b21, 0x6459, 0x11d2, \
0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
-struct efi_block_io_media
-{
+struct efi_block_io_media {
u32 media_id;
char removable_media;
char media_present;
bool cursor_visible;
};
-
#define EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID \
EFI_GUID(0x387477c2, 0x69c7, 0x11d2, \
0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
struct simple_text_output_mode *mode;
};
+#define EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID \
+ EFI_GUID(0xdd9e7534, 0x7762, 0x4698, \
+ 0x8c, 0x14, 0xf5, 0x85, 0x17, 0xa6, 0x25, 0xaa)
+
struct efi_input_key {
u16 scan_code;
s16 unicode_char;
};
+#define EFI_SHIFT_STATE_INVALID 0x00000000
+#define EFI_RIGHT_SHIFT_PRESSED 0x00000001
+#define EFI_LEFT_SHIFT_PRESSED 0x00000002
+#define EFI_RIGHT_CONTROL_PRESSED 0x00000004
+#define EFI_LEFT_CONTROL_PRESSED 0x00000008
+#define EFI_RIGHT_ALT_PRESSED 0x00000010
+#define EFI_LEFT_ALT_PRESSED 0x00000020
+#define EFI_RIGHT_LOGO_PRESSED 0x00000040
+#define EFI_LEFT_LOGO_PRESSED 0x00000080
+#define EFI_MENU_KEY_PRESSED 0x00000100
+#define EFI_SYS_REQ_PRESSED 0x00000200
+#define EFI_SHIFT_STATE_VALID 0x80000000
+
+#define EFI_TOGGLE_STATE_INVALID 0x00
+#define EFI_SCROLL_LOCK_ACTIVE 0x01
+#define EFI_NUM_LOCK_ACTIVE 0x02
+#define EFI_CAPS_LOCK_ACTIVE 0x04
+#define EFI_KEY_STATE_EXPOSED 0x40
+#define EFI_TOGGLE_STATE_VALID 0x80
+
+struct efi_key_state {
+ u32 key_shift_state;
+ u8 key_toggle_state;
+};
+
+struct efi_key_data {
+ struct efi_input_key key;
+ struct efi_key_state key_state;
+};
+
+struct efi_simple_text_input_ex_protocol {
+ efi_status_t (EFIAPI *reset) (
+ struct efi_simple_text_input_ex_protocol *this,
+ bool extended_verification);
+ efi_status_t (EFIAPI *read_key_stroke_ex) (
+ struct efi_simple_text_input_ex_protocol *this,
+ struct efi_key_data *key_data);
+ struct efi_event *wait_for_key_ex;
+ efi_status_t (EFIAPI *set_state) (
+ struct efi_simple_text_input_ex_protocol *this,
+ u8 key_toggle_state);
+ efi_status_t (EFIAPI *register_key_notify) (
+ struct efi_simple_text_input_ex_protocol *this,
+ struct efi_key_data *key_data,
+ efi_status_t (EFIAPI *key_notify_function)(
+ struct efi_key_data *key_data),
+ void **notify_handle);
+ efi_status_t (EFIAPI *unregister_key_notify) (
+ struct efi_simple_text_input_ex_protocol *this,
+ void *notification_handle);
+};
+
#define EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID \
EFI_GUID(0x387477c1, 0x69c7, 0x11d2, \
0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
-struct efi_simple_input_interface {
- efi_status_t(EFIAPI *reset)(struct efi_simple_input_interface *this,
- bool ExtendedVerification);
+struct efi_simple_text_input_protocol {
+ efi_status_t(EFIAPI *reset)(struct efi_simple_text_input_protocol *this,
+ bool extended_verification);
efi_status_t(EFIAPI *read_key_stroke)(
- struct efi_simple_input_interface *this,
+ struct efi_simple_text_input_protocol *this,
struct efi_input_key *key);
struct efi_event *wait_for_key;
};
EFI_GUID(0x8b843e20, 0x8132, 0x4852, \
0x90, 0xcc, 0x55, 0x1a, 0x4e, 0x4a, 0x7f, 0x1c)
-struct efi_device_path_to_text_protocol
-{
+struct efi_device_path_to_text_protocol {
uint16_t *(EFIAPI *convert_device_node_to_text)(
struct efi_device_path *device_node,
bool display_only,
#define EFI_GOT_BGRA8 1
#define EFI_GOT_BITMASK 2
-struct efi_gop_mode_info
-{
+struct efi_gop_mode_info {
u32 version;
u32 width;
u32 height;
u32 pixels_per_scanline;
};
-struct efi_gop_mode
-{
+struct efi_gop_mode {
u32 max_mode;
u32 mode;
struct efi_gop_mode_info *info;
#define EFI_BLT_BUFFER_TO_VIDEO 2
#define EFI_BLT_VIDEO_TO_VIDEO 3
-struct efi_gop
-{
+struct efi_gop {
efi_status_t (EFIAPI *query_mode)(struct efi_gop *this, u32 mode_number,
efi_uintn_t *size_of_info,
struct efi_gop_mode_info **info);
/* revision of the simple network protocol */
#define EFI_SIMPLE_NETWORK_PROTOCOL_REVISION 0x00010000
-struct efi_simple_network
-{
+struct efi_simple_network {
u64 revision;
efi_status_t (EFIAPI *start)(struct efi_simple_network *this);
efi_status_t (EFIAPI *stop)(struct efi_simple_network *this);
u8 packet[1472];
};
-struct efi_pxe_mode
-{
+struct efi_pxe_mode {
u8 started;
u8 ipv6_available;
u8 ipv6_supported;
efi_handle_t driver_binding_handle;
};
+#define EFI_UNICODE_COLLATION_PROTOCOL2_GUID \
+ EFI_GUID(0xa4c751fc, 0x23ae, 0x4c3e, \
+ 0x92, 0xe9, 0x49, 0x64, 0xcf, 0x63, 0xf3, 0x49)
+struct efi_unicode_collation_protocol {
+ efi_intn_t (EFIAPI *stri_coll)(
+ struct efi_unicode_collation_protocol *this, u16 *s1, u16 *s2);
+ bool (EFIAPI *metai_match)(struct efi_unicode_collation_protocol *this,
+ const u16 *string, const u16 *patter);
+ void (EFIAPI *str_lwr)(struct efi_unicode_collation_protocol
+ *this, u16 *string);
+ void (EFIAPI *str_upr)(struct efi_unicode_collation_protocol *this,
+ u16 *string);
+ void (EFIAPI *fat_to_str)(struct efi_unicode_collation_protocol *this,
+ efi_uintn_t fat_size, char *fat, u16 *string);
+ bool (EFIAPI *str_to_fat)(struct efi_unicode_collation_protocol *this,
+ const u16 *string, efi_uintn_t fat_size,
+ char *fat);
+ char *supported_languages;
+};
+
#endif
#include <efi_api.h>
/* No need for efi loader support in SPL */
-#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(EFI_LOADER)
#include <linux/list.h>
/* Maximum number of configuration tables */
#define EFI_MAX_CONFIGURATION_TABLES 16
+/* GUID used by the root node */
+#define U_BOOT_GUID \
+ EFI_GUID(0xe61d73b9, 0xa384, 0x4acc, \
+ 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3, 0x62, 0x8b)
+
int __efi_entry_check(void);
int __efi_exit_check(void);
const char *__efi_nesting(void);
extern struct efi_system_table systab;
extern struct efi_simple_text_output_protocol efi_con_out;
-extern struct efi_simple_input_interface efi_con_in;
+extern struct efi_simple_text_input_protocol efi_con_in;
extern struct efi_console_control_protocol efi_console_control;
extern const struct efi_device_path_to_text_protocol efi_device_path_to_text;
/* implementation of the EFI_DEVICE_PATH_UTILITIES_PROTOCOL */
extern const struct efi_device_path_utilities_protocol
efi_device_path_utilities;
+/* Implementation of the EFI_UNICODE_COLLATION_PROTOCOL */
+extern const struct efi_unicode_collation_protocol
+ efi_unicode_collation_protocol;
uint16_t *efi_dp_str(struct efi_device_path *dp);
+/* GUID of the U-Boot root node */
+extern const efi_guid_t efi_u_boot_guid;
/* GUID of the EFI_BLOCK_IO_PROTOCOL */
extern const efi_guid_t efi_block_io_guid;
extern const efi_guid_t efi_global_variable_guid;
/* GUID for file system information */
extern const efi_guid_t efi_file_system_info_guid;
extern const efi_guid_t efi_guid_device_path_utilities_protocol;
+/* GUID of the Unicode collation protocol */
+extern const efi_guid_t efi_guid_unicode_collation_protocol;
extern unsigned int __efi_runtime_start, __efi_runtime_stop;
extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
void *handle;
};
+/**
+ * struct efi_loaded_image_obj - handle of a loaded image
+ */
+struct efi_loaded_image_obj {
+ /* Generic EFI object parent class data */
+ struct efi_object parent;
+ void *reloc_base;
+ aligned_u64 reloc_size;
+ efi_status_t exit_status;
+ struct jmp_buf_data exit_jmp;
+ EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
+ struct efi_system_table *st);
+};
+
/**
* struct efi_event
*
/* List of all events */
extern struct list_head efi_events;
+/* Called by bootefi to initialize root node */
+efi_status_t efi_root_node_register(void);
/* Called by bootefi to initialize runtime */
efi_status_t efi_initialize_system_table(void);
/* Called by bootefi to make console interface available */
/* Called from places to check whether a timer expired */
void efi_timer_check(void);
/* PE loader implementation */
-void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info);
+void *efi_load_pe(struct efi_loaded_image_obj *handle, void *efi,
+ struct efi_loaded_image *loaded_image_info);
/* Called once to store the pristine gd pointer */
void efi_save_gd(void);
/* Special case handler for error/abort that just tries to dtrt to get
/* Adds new or overrides configuration table entry to the system table */
efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table);
/* Sets up a loaded image */
-efi_status_t efi_setup_loaded_image(
- struct efi_loaded_image *info, struct efi_object *obj,
- struct efi_device_path *device_path,
- struct efi_device_path *file_path);
+efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path,
+ struct efi_device_path *file_path,
+ struct efi_loaded_image_obj **handle_ptr,
+ struct efi_loaded_image **info_ptr);
efi_status_t efi_load_image_from_path(struct efi_device_path *file_path,
void **buffer);
-/* Print information about a loaded image */
-efi_status_t efi_print_image_info(struct efi_loaded_image *image, void *pc);
/* Print information about all loaded images */
void efi_print_image_infos(void *pc);
(((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
((_dp)->sub_type == DEVICE_PATH_SUB_TYPE_##_subtype))
-/* Convert strings from normal C strings to uEFI strings */
+/**
+ * ascii2unicode() - convert ASCII string to UTF-16 string
+ *
+ * A zero terminated ASCII string is converted to a zero terminated UTF-16
+ * string. The output buffer must be preassigned.
+ *
+ * @unicode: preassigned output buffer for UTF-16 string
+ * @ascii: ASCII string to be converted
+ */
static inline void ascii2unicode(u16 *unicode, const char *ascii)
{
while (*ascii)
void *efi_bootmgr_load(struct efi_device_path **device_path,
struct efi_device_path **file_path);
-#else /* defined(EFI_LOADER) && !defined(CONFIG_SPL_BUILD) */
+#else /* CONFIG_IS_ENABLED(EFI_LOADER) */
/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
#define __efi_runtime_data
static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
static inline void efi_print_image_infos(void *pc) { }
-#endif /* CONFIG_EFI_LOADER && !CONFIG_SPL_BUILD */
+#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
#endif /* _EFI_LOADER_H */
};
extern struct efi_simple_text_output_protocol *con_out;
-extern struct efi_simple_input_interface *con_in;
+extern struct efi_simple_text_input_protocol *con_in;
/*
* Exit the boot services.
void efi_st_printc(int color, const char *fmt, ...)
__attribute__ ((format (__printf__, 2, 3)));
+/**
+ * efi_st_translate_char() - translate a unicode character to a string
+ *
+ * @code: unicode character
+ * Return: string
+ */
+u16 *efi_st_translate_char(u16 code);
+
+/**
+ * efi_st_translate_code() - translate a scan code to a human readable string
+ *
+ * @code: unicode character
+ * Return: string
+ */
+u16 *efi_st_translate_code(u16 code);
+
/*
* Compare memory.
* We cannot use lib/string.c due to different CFLAGS values.
int fatbufnum; /* Used by get_fatent, init to -1 */
int rootdir_size; /* Size of root dir for non-FAT32 */
__u32 root_cluster; /* First cluster of root dir for FAT32 */
+ u32 total_sect; /* Number of sectors */
+ int fats; /* Number of FATs */
} fsdata;
static inline u32 clust_to_sect(fsdata *fsdata, u32 clust)
int fat_opendir(const char *filename, struct fs_dir_stream **dirsp);
int fat_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
void fat_closedir(struct fs_dir_stream *dirs);
+int fat_unlink(const char *filename);
+int fat_mkdir(const char *dirname);
void fat_close(void);
#endif /* _FAT_H_ */
*/
void fs_closedir(struct fs_dir_stream *dirs);
+/*
+ * fs_unlink - delete a file or directory
+ *
+ * If a given name is a directory, it will be deleted only if it's empty
+ *
+ * @filename: Name of file or directory to delete
+ * @return 0 on success, -1 on error conditions
+ */
+int fs_unlink(const char *filename);
+
+/*
+ * fs_mkdir - Create a directory
+ *
+ * @filename: Name of directory to create
+ * @return 0 on success, -1 on error conditions
+ */
+int fs_mkdir(const char *filename);
+
/*
* Common implementation for various filesystem commands, optionally limited
* to a specific filesystem type via the fstype parameter.
int fstype);
int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype);
+int do_rm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype);
+int do_mkdir(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype);
/*
* Determine the UUID of the specified filesystem and print it. Optionally it is
--- /dev/null
+/*
+ * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#ifndef _FS_LOADER_H_
+#define _FS_LOADER_H_
+
+#include <dm.h>
+
+/**
+ * struct firmware - A place for storing firmware and its attribute data.
+ *
+ * This holds information about a firmware and its content.
+ *
+ * @size: Size of a file
+ * @data: Buffer for file
+ * @priv: Firmware loader private fields
+ */
+struct firmware {
+ size_t size;
+ const u8 *data;
+ void *priv;
+};
+
+/**
+ * struct phandle_part - A place for storing phandle of node and its partition
+ *
+ * This holds information about a phandle of the block device, and its
+ * partition where the firmware would be loaded from.
+ *
+ * @phandle: Phandle of storage device node
+ * @partition: Partition of block device
+ */
+struct phandle_part {
+ u32 phandle;
+ u32 partition;
+};
+
+/**
+ * struct phandle_part - A place for storing all supported storage devices
+ *
+ * This holds information about all supported storage devices for driver use.
+ *
+ * @phandlepart: Attribute data for block device.
+ * @mtdpart: MTD partition for ubi partition.
+ * @ubivol: UBI volume-name for ubifsmount.
+ */
+struct device_platdata {
+ struct phandle_part phandlepart;
+ char *mtdpart;
+ char *ubivol;
+};
+
+/**
+ * release_firmware - Release the resource associated with a firmware image
+ * @firmware: Firmware resource to release
+ */
+void release_firmware(struct firmware *firmware);
+
+/**
+ * request_firmware_into_buf - Load firmware into a previously allocated buffer.
+ * @plat: Platform data such as storage and partition firmware loading from.
+ * @name: Name of firmware file.
+ * @buf: Address of buffer to load firmware into.
+ * @size: Size of buffer.
+ * @offset: Offset of a file for start reading into buffer.
+ * @firmwarep: Pointer to firmware image.
+ *
+ * The firmware is loaded directly into the buffer pointed to by @buf and
+ * the @firmwarep data member is pointed at @buf.
+ *
+ * Return: Size of total read, negative value when error.
+ */
+int request_firmware_into_buf(struct device_platdata *plat,
+ const char *name,
+ void *buf, size_t size, u32 offset,
+ struct firmware **firmwarep);
+#endif
u32 reg_error[];
};
+void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
int get_mc_boot_status(void);
int get_dpl_apply_status(void);
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
void os_localtime(struct rtc_time *rt);
/**
- * os_setjmp() - Call setjmp()
- *
- * Call the host system's setjmp() function.
- *
- * @jmp: Buffer to store current execution state
- * @size: Size of buffer
- * @return normal setjmp() value if OK, -ENOSPC if @size is too small
- */
-int os_setjmp(ulong *jmp, int size);
-
-/**
- * os_longjmp() - Call longjmp()
- *
- * Call the host system's longjmp() function.
- *
- * @jmp: Buffer where previous execution state was stored
- * @ret: Value to pass to longjmp()
+ * os_abort() - Raise SIGABRT to exit sandbox (e.g. to debugger)
*/
-void os_longjmp(ulong *jmp, int ret);
-
+void os_abort(void);
#endif
* the boot-payload
*/
void spl_perform_fixups(struct spl_image_info *spl_image);
+
+/*
+ * spl_get_load_buffer() - get buffer for loading partial image data
+ *
+ * Returns memory area which can be populated by partial image data,
+ * ie. uImage or fitImage header.
+ */
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size);
+
#endif
int cmd_ut_category(const char *name, struct unit_test *tests, int n_ents,
int argc, char * const argv[]);
+int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+int do_ut_unicode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif /* __TEST_SUITES_H__ */
} \
}
+/* Assert that two memory areas are equal */
+#define ut_asserteq_mem(expr1, expr2, len) { \
+ const u8 *val1 = (u8 *)(expr1), *val2 = (u8 *)(expr2); \
+ const uint __len = len; \
+ \
+ if (memcmp(val1, val2, __len)) { \
+ char __buf1[64 + 1] = "\0"; \
+ char __buf2[64 + 1] = "\0"; \
+ bin2hex(__buf1, val1, min(__len, (uint)32)); \
+ bin2hex(__buf2, val2, min(__len, (uint)32)); \
+ ut_failf(uts, __FILE__, __LINE__, __func__, \
+ #expr1 " = " #expr2, \
+ "Expected \"%s\", got \"%s\"", \
+ __buf1, __buf2); \
+ return CMD_RET_FAILURE; \
+ } \
+}
+
/* Assert that two pointers are equal */
#define ut_asserteq_ptr(expr1, expr2) { \
const void *val1 = (expr1), *val2 = (expr2); \
extern int ubi_volume_read(char *volume, char *buf, size_t size);
extern struct ubi_device *ubi_devices[];
+int cmd_ubifs_mount(char *vol_name);
+int cmd_ubifs_umount(void);
#endif
/* Video functions */
-struct stdio_dev;
-
-int video_init(void *videobase);
-void video_putc(struct stdio_dev *dev, const char c);
-void video_puts(struct stdio_dev *dev, const char *s);
-
/**
* Display a BMP format bitmap on the screen
*
* Drivers must set up @rows, @cols, @x_charsize, @y_charsize in their probe()
* method. Drivers may set up @xstart_frac if desired.
*
- * @sdev: stdio device, acting as an output sink
- * @xcur_frac: Current X position, in fractional units (VID_TO_POS(x))
- * @curr_row: Current Y position in pixels (0=top)
- * @rows: Number of text rows
- * @cols: Number of text columns
- * @x_charsize: Character width in pixels
- * @y_charsize: Character height in pixels
+ * @sdev: stdio device, acting as an output sink
+ * @xcur_frac: Current X position, in fractional units (VID_TO_POS(x))
+ * @ycur: Current Y position in pixels (0=top)
+ * @rows: Number of text rows
+ * @cols: Number of text columns
+ * @x_charsize: Character width in pixels
+ * @y_charsize: Character height in pixels
* @tab_width_frac: Tab width in fractional units
- * @xsize_frac: Width of the display in fractional units
+ * @xsize_frac: Width of the display in fractional units
* @xstart_frac: Left margin for the text console in fractional units
- * @last_ch: Last character written to the text console on this line
- * @escape: TRUE if currently accumulating an ANSI escape sequence
- * @escape_len: Length of accumulated escape sequence so far
- * @escape_buf: Buffer to accumulate escape sequence
+ * @last_ch: Last character written to the text console on this line
+ * @escape: TRUE if currently accumulating an ANSI escape sequence
+ * @escape_len: Length of accumulated escape sequence so far
+ * @col_saved: Saved X position, in fractional units (VID_TO_POS(x))
+ * @row_saved: Saved Y position in pixels (0=top)
+ * @escape_buf: Buffer to accumulate escape sequence
*/
struct vidconsole_priv {
struct stdio_dev sdev;
*/
int escape;
int escape_len;
+ int row_saved;
+ int col_saved;
char escape_buf[32];
};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef _VIDEO_OSD_H_
+#define _VIDEO_OSD_H_
+
+struct video_osd_info {
+ /* The width of the OSD display in columns */
+ uint width;
+ /* The height of the OSD display in rows */
+ uint height;
+ /* The major version of the OSD device */
+ uint major_version;
+ /* The minor version of the OSD device */
+ uint minor_version;
+};
+
+/**
+ * struct video_osd_ops - driver operations for OSD uclass
+ *
+ * The OSD uclass implements support for text-oriented on-screen displays,
+ * which are taken to be devices that independently display a graphical
+ * text-based overlay over the video output of an associated display.
+ *
+ * The functions defined by the uclass support writing text to the display in
+ * either a generic form (by specifying a string, a driver-specific color value
+ * for the text, and screen coordinates in rows and columns) or a
+ * driver-specific form (by specifying "raw" driver-specific data to display at
+ * a given coordinate).
+ *
+ * Functions to read device information and set the size of the virtual OSD
+ * screen (in rows and columns) are also supported.
+ *
+ * Drivers should support these operations unless otherwise noted. These
+ * operations are intended to be used by uclass code, not directly from
+ * other code.
+ */
+struct video_osd_ops {
+ /**
+ * get_info() - Get information about a OSD instance
+ *
+ * A OSD instance may keep some internal data about itself. This
+ * function can be used to access this data.
+ *
+ * @dev: OSD instance to query.
+ * @info: Pointer to a structure that takes the information read
+ * from the OSD instance.
+ * @return 0 if OK, -ve on error.
+ */
+ int (*get_info)(struct udevice *dev, struct video_osd_info *info);
+
+ /**
+ * set_mem() - Write driver-specific text data to OSD screen
+ *
+ * The passed data are device-specific, and it's up to the driver how
+ * to interpret them. How the count parameter is interpreted is also
+ * driver-specific; most likely the given data will be written to the
+ * OSD count times back-to-back, which is e.g. convenient for filling
+ * areas of the OSD with a single character.
+ *
+ * For example a invocation of
+ *
+ * video_osd_set_mem(dev, 0, 0, "A", 1, 10);
+ *
+ * will write the device-specific text data "A" to the positions (0, 0)
+ * to (9, 0) on the OSD.
+ *
+ * Device-specific text data may, e.g. be a special encoding of glyphs
+ * to display and color values in binary format.
+ *
+ * @dev: OSD instance to write to.
+ * @col: Horizontal character coordinate to write to.
+ * @row Vertical character coordinate to write to.
+ * @buf: Array containing device-specific data to write to the
+ * specified coordinate on the OSD screen.
+ * @buflen: Length of the data in the passed buffer (in byte).
+ * @count: Write count many repetitions of the given text data
+ * @return 0 if OK, -ve on error.
+ */
+ int (*set_mem)(struct udevice *dev, uint col, uint row, u8 *buf,
+ size_t buflen, uint count);
+
+ /**
+ * set_size() - Set the position and dimension of the OSD's
+ * writeable window
+ *
+ * @dev: OSD instance to write to.
+ * @col The number of characters in the window's columns
+ * @row The number of characters in the window's rows
+ * @return 0 if OK, -ve on error.
+ */
+ int (*set_size)(struct udevice *dev, uint col, uint row);
+
+ /**
+ * print() - Print a string in a given color to specified coordinates
+ * on the OSD
+ *
+ * @dev: OSD instance to write to.
+ * @col The x-coordinate of the position the string should be
+ * written to
+ * @row The y-coordinate of the position the string should be
+ * written to
+ * @color: The color in which the specified string should be
+ * printed; the interpretation of the value is
+ * driver-specific, and possible values should be defined
+ * e.g. in a driver include file.
+ * @text: The string data that should be printed on the OSD
+ * @return 0 if OK, -ve on error.
+ */
+ int (*print)(struct udevice *dev, uint col, uint row, ulong color,
+ char *text);
+};
+
+#define video_osd_get_ops(dev) ((struct video_osd_ops *)(dev)->driver->ops)
+
+/**
+ * video_osd_get_info() - Get information about a OSD instance
+ *
+ * A OSD instance may keep some internal data about itself. This function can
+ * be used to access this data.
+ *
+ * @dev: OSD instance to query.
+ * @info: Pointer to a structure that takes the information read from the
+ * OSD instance.
+ * @return 0 if OK, -ve on error.
+ */
+int video_osd_get_info(struct udevice *dev, struct video_osd_info *info);
+
+/**
+ * video_osd_set_mem() - Write text data to OSD memory
+ *
+ * The passed data are device-specific, and it's up to the driver how to
+ * interpret them. How the count parameter is interpreted is also
+ * driver-specific; most likely the given data will be written to the OSD count
+ * times back-to-back, which is e.g. convenient for filling areas of the OSD
+ * with a single character.
+ *
+ * For example a invocation of
+ *
+ * video_osd_set_mem(dev, 0, 0, "A", 1, 10);
+ *
+ * will write the device-specific text data "A" to the positions (0, 0) to (9,
+ * 0) on the OSD.
+ *
+ * Device-specific text data may, e.g. be a special encoding of glyphs to
+ * display and color values in binary format.
+ *
+ * @dev: OSD instance to write to.
+ * @col: Horizontal character coordinate to write to.
+ * @row Vertical character coordinate to write to.
+ * @buf: Array containing device-specific data to write to the specified
+ * coordinate on the OSD screen.
+ * @buflen: Length of the data in the passed buffer (in byte).
+ * @count: Write count many repetitions of the given text data
+ * @return 0 if OK, -ve on error.
+ */
+int video_osd_set_mem(struct udevice *dev, uint col, uint row, u8 *buf,
+ size_t buflen, uint count);
+
+/**
+ * video_osd_set_size() - Set the position and dimension of the OSD's
+ * writeable window
+ *
+ * @dev: OSD instance to write to.
+ * @col The number of characters in the window's columns
+ * @row The number of characters in the window's rows
+ * @return 0 if OK, -ve on error.
+ */
+int video_osd_set_size(struct udevice *dev, uint col, uint row);
+
+/**
+ * video_osd_print() - Print a string in a given color to specified coordinates
+ * on the OSD
+ *
+ * @dev: OSD instance to write to.
+ * @col The x-coordinate of the position the string should be written
+ * to
+ * @row The y-coordinate of the position the string should be written
+ * to
+ * @color: The color in which the specified string should be printed; the
+ * interpretation of the value is driver-specific, and possible
+ * values should be defined e.g. in a driver include file.
+ * @text: The string data that should be printed on the OSD
+ * @return 0 if OK, -ve on error.
+ */
+int video_osd_print(struct udevice *dev, uint col, uint row, ulong color,
+ char *text);
+
+#endif /* !_VIDEO_OSD_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co
+ * Copyright (c) 2018 Microchip Technology, Inc.
+ *
+ */
+
+#ifndef __W1_EEPROM_H
+#define __W1_EEPROM_H
+
+struct udevice;
+
+struct w1_eeprom_ops {
+ /*
+ * Reads a buff from the given EEPROM memory, starting at
+ * given offset and place the results into the given buffer.
+ * Should read given count of bytes.
+ * Should return 0 on success, and normal error.h on error
+ */
+ int (*read_buf)(struct udevice *dev, unsigned int offset,
+ u8 *buf, unsigned int count);
+};
+
+int w1_eeprom_read_buf(struct udevice *dev, unsigned int offset,
+ u8 *buf, unsigned int count);
+
+int w1_eeprom_dm_init(void);
+
+int w1_eeprom_register_new_device(u64 id);
+
+int w1_eeprom_get_id(struct udevice *dev, u64 *id);
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co
+ *
+ */
+
+#ifndef __W1_H
+#define __W1_H
+
+#include <dm.h>
+
+#define W1_FAMILY_DS24B33 0x23
+#define W1_FAMILY_DS2431 0x2d
+#define W1_FAMILY_EEP_SANDBOX 0xfe
+
+struct w1_device {
+ u64 id;
+};
+
+struct w1_ops {
+ u8 (*read_byte)(struct udevice *dev);
+ bool (*reset)(struct udevice *dev);
+ u8 (*triplet)(struct udevice *dev, bool bdir);
+ void (*write_byte)(struct udevice *dev, u8 byte);
+};
+
+int w1_get_bus(int busnum, struct udevice **busp);
+u8 w1_get_device_family(struct udevice *dev);
+
+int w1_read_buf(struct udevice *dev, u8 *buf, unsigned int count);
+int w1_read_byte(struct udevice *dev);
+int w1_reset_select(struct udevice *dev);
+int w1_write_buf(struct udevice *dev, u8 *buf, unsigned int count);
+int w1_write_byte(struct udevice *dev, u8 byte);
+
+#endif
obj-$(CONFIG_OPTEE) += optee/
obj-$(CONFIG_AES) += aes.o
+
+ifndef API_BUILD
+ifneq ($(CONFIG_UT_UNICODE)$(CONFIG_EFI_LOADER),)
obj-y += charset.o
+endif
+endif
obj-$(CONFIG_USB_TTY) += circbuf.o
obj-y += crc7.o
obj-y += crc8.o
* Copyright (c) 2017 Rob Clark
*/
+#include <common.h>
#include <charset.h>
+#include <capitalization.h>
#include <malloc.h>
-/*
- * utf8/utf16 conversion mostly lifted from grub
+static struct capitalization_table capitalization_table[] =
+#ifdef CONFIG_EFI_UNICODE_CAPITALIZATION
+ UNICODE_CAPITALIZATION_TABLE;
+#elif CONFIG_FAT_DEFAULT_CODEPAGE == 1250
+ CP1250_CAPITALIZATION_TABLE;
+#else
+ CP437_CAPITALIZATION_TABLE;
+#endif
+
+/**
+ * get_code() - read Unicode code point from UTF-8 stream
+ *
+ * @read_u8: - stream reader
+ * @src: - string buffer passed to stream reader, optional
+ * Return: - Unicode code point
+ */
+static int get_code(u8 (*read_u8)(void *data), void *data)
+{
+ s32 ch = 0;
+
+ ch = read_u8(data);
+ if (!ch)
+ return 0;
+ if (ch >= 0xc2 && ch <= 0xf4) {
+ int code = 0;
+
+ if (ch >= 0xe0) {
+ if (ch >= 0xf0) {
+ /* 0xf0 - 0xf4 */
+ ch &= 0x07;
+ code = ch << 18;
+ ch = read_u8(data);
+ if (ch < 0x80 || ch > 0xbf)
+ goto error;
+ ch &= 0x3f;
+ } else {
+ /* 0xe0 - 0xef */
+ ch &= 0x0f;
+ }
+ code += ch << 12;
+ if ((code >= 0xD800 && code <= 0xDFFF) ||
+ code >= 0x110000)
+ goto error;
+ ch = read_u8(data);
+ if (ch < 0x80 || ch > 0xbf)
+ goto error;
+ }
+ /* 0xc0 - 0xdf or continuation byte (0x80 - 0xbf) */
+ ch &= 0x3f;
+ code += ch << 6;
+ ch = read_u8(data);
+ if (ch < 0x80 || ch > 0xbf)
+ goto error;
+ ch &= 0x3f;
+ ch += code;
+ } else if (ch >= 0x80) {
+ goto error;
+ }
+ return ch;
+error:
+ return '?';
+}
+
+/**
+ * read_string() - read byte from character string
+ *
+ * @data: - pointer to string
+ * Return: - byte read
+ *
+ * The string pointer is incremented if it does not point to '\0'.
*/
+static u8 read_string(void *data)
-size_t utf16_strlen(const uint16_t *in)
{
- size_t i;
- for (i = 0; in[i]; i++);
- return i;
+ const char **src = (const char **)data;
+ u8 c;
+
+ if (!src || !*src || !**src)
+ return 0;
+ c = **src;
+ ++*src;
+ return c;
}
-size_t utf16_strnlen(const uint16_t *in, size_t count)
+/**
+ * read_console() - read byte from console
+ *
+ * @src - not used, needed to match interface
+ * Return: - byte read
+ */
+static u8 read_console(void *data)
{
- size_t i;
- for (i = 0; count-- && in[i]; i++);
- return i;
+ return getc();
+}
+
+int console_read_unicode(s32 *code)
+{
+ if (!tstc()) {
+ /* No input available */
+ return 1;
+ }
+
+ /* Read Unicode code */
+ *code = get_code(read_console, NULL);
+ return 0;
+}
+
+s32 utf8_get(const char **src)
+{
+ return get_code(read_string, src);
+}
+
+int utf8_put(s32 code, char **dst)
+{
+ if (!dst || !*dst)
+ return -1;
+ if ((code >= 0xD800 && code <= 0xDFFF) || code >= 0x110000)
+ return -1;
+ if (code <= 0x007F) {
+ **dst = code;
+ } else {
+ if (code <= 0x07FF) {
+ **dst = code >> 6 | 0xC0;
+ } else {
+ if (code < 0x10000) {
+ **dst = code >> 12 | 0xE0;
+ } else {
+ **dst = code >> 18 | 0xF0;
+ ++*dst;
+ **dst = (code >> 12 & 0x3F) | 0x80;
+ }
+ ++*dst;
+ **dst = (code >> 6 & 0x3F) | 0x80;
+ }
+ ++*dst;
+ **dst = (code & 0x3F) | 0x80;
+ }
+ ++*dst;
+ return 0;
+}
+
+size_t utf8_utf16_strnlen(const char *src, size_t count)
+{
+ size_t len = 0;
+
+ for (; *src && count; --count) {
+ s32 code = utf8_get(&src);
+
+ if (!code)
+ break;
+ if (code < 0) {
+ /* Reserve space for a replacement character */
+ len += 1;
+ } else if (code < 0x10000) {
+ len += 1;
+ } else {
+ len += 2;
+ }
+ }
+ return len;
+}
+
+int utf8_utf16_strncpy(u16 **dst, const char *src, size_t count)
+{
+ if (!src || !dst || !*dst)
+ return -1;
+
+ for (; count && *src; --count) {
+ s32 code = utf8_get(&src);
+
+ if (code < 0)
+ code = '?';
+ utf16_put(code, dst);
+ }
+ **dst = 0;
+ return 0;
+}
+
+s32 utf16_get(const u16 **src)
+{
+ s32 code, code2;
+
+ if (!src || !*src)
+ return -1;
+ if (!**src)
+ return 0;
+ code = **src;
+ ++*src;
+ if (code >= 0xDC00 && code <= 0xDFFF)
+ return -1;
+ if (code >= 0xD800 && code <= 0xDBFF) {
+ if (!**src)
+ return -1;
+ code &= 0x3ff;
+ code <<= 10;
+ code += 0x10000;
+ code2 = **src;
+ ++*src;
+ if (code2 <= 0xDC00 || code2 >= 0xDFFF)
+ return -1;
+ code2 &= 0x3ff;
+ code += code2;
+ }
+ return code;
+}
+
+int utf16_put(s32 code, u16 **dst)
+{
+ if (!dst || !*dst)
+ return -1;
+ if ((code >= 0xD800 && code <= 0xDFFF) || code >= 0x110000)
+ return -1;
+ if (code < 0x10000) {
+ **dst = code;
+ } else {
+ code -= 0x10000;
+ **dst = code >> 10 | 0xD800;
+ ++*dst;
+ **dst = (code & 0x3ff) | 0xDC00;
+ }
+ ++*dst;
+ return 0;
+}
+
+size_t utf16_strnlen(const u16 *src, size_t count)
+{
+ size_t len = 0;
+
+ for (; *src && count; --count) {
+ s32 code = utf16_get(&src);
+
+ if (!code)
+ break;
+ /*
+ * In case of an illegal sequence still reserve space for a
+ * replacement character.
+ */
+ ++len;
+ }
+ return len;
+}
+
+size_t utf16_utf8_strnlen(const u16 *src, size_t count)
+{
+ size_t len = 0;
+
+ for (; *src && count; --count) {
+ s32 code = utf16_get(&src);
+
+ if (!code)
+ break;
+ if (code < 0)
+ /* Reserve space for a replacement character */
+ len += 1;
+ else if (code < 0x80)
+ len += 1;
+ else if (code < 0x800)
+ len += 2;
+ else if (code < 0x10000)
+ len += 3;
+ else
+ len += 4;
+ }
+ return len;
}
-uint16_t *utf16_strcpy(uint16_t *dest, const uint16_t *src)
+int utf16_utf8_strncpy(char **dst, const u16 *src, size_t count)
{
- uint16_t *tmp = dest;
+ if (!src || !dst || !*dst)
+ return -1;
- while ((*dest++ = *src++) != '\0')
- /* nothing */;
- return tmp;
+ for (; count && *src; --count) {
+ s32 code = utf16_get(&src);
+ if (code < 0)
+ code = '?';
+ utf8_put(code, dst);
+ }
+ **dst = 0;
+ return 0;
}
-uint16_t *utf16_strdup(const uint16_t *s)
+s32 utf_to_lower(const s32 code)
{
- uint16_t *new;
- if (!s || !(new = malloc((utf16_strlen(s) + 1) * 2)))
- return NULL;
- utf16_strcpy(new, s);
- return new;
+ struct capitalization_table *pos = capitalization_table;
+ s32 ret = code;
+
+ if (code <= 0x7f) {
+ if (code >= 'A' && code <= 'Z')
+ ret += 0x20;
+ return ret;
+ }
+ for (; pos->upper; ++pos) {
+ if (pos->upper == code) {
+ ret = pos->lower;
+ break;
+ }
+ }
+ return ret;
+}
+
+s32 utf_to_upper(const s32 code)
+{
+ struct capitalization_table *pos = capitalization_table;
+ s32 ret = code;
+
+ if (code <= 0x7f) {
+ if (code >= 'a' && code <= 'z')
+ ret -= 0x20;
+ return ret;
+ }
+ for (; pos->lower; ++pos) {
+ if (pos->lower == code) {
+ ret = pos->upper;
+ break;
+ }
+ }
+ return ret;
+}
+
+size_t u16_strlen(const u16 *in)
+{
+ size_t i;
+ for (i = 0; in[i]; i++);
+ return i;
+}
+
+size_t u16_strnlen(const u16 *in, size_t count)
+{
+ size_t i;
+ for (i = 0; count-- && in[i]; i++);
+ return i;
}
/* Convert UTF-16 to UTF-8. */
return dest;
}
-
-uint16_t *utf8_to_utf16(uint16_t *dest, const uint8_t *src, size_t size)
-{
- while (size--) {
- int extension_bytes;
- uint32_t code;
-
- extension_bytes = 0;
- if (*src <= 0x7f) {
- code = *src++;
- /* Exit on zero byte */
- if (!code)
- size = 0;
- } else if (*src <= 0xbf) {
- /* Illegal code */
- code = '?';
- } else if (*src <= 0xdf) {
- code = *src++ & 0x1f;
- extension_bytes = 1;
- } else if (*src <= 0xef) {
- code = *src++ & 0x0f;
- extension_bytes = 2;
- } else if (*src <= 0xf7) {
- code = *src++ & 0x07;
- extension_bytes = 3;
- } else {
- /* Illegal code */
- code = '?';
- }
-
- for (; extension_bytes && size; --size, --extension_bytes) {
- if ((*src & 0xc0) == 0x80) {
- code <<= 6;
- code |= *src++ & 0x3f;
- } else {
- /* Illegal code */
- code = '?';
- ++src;
- --size;
- break;
- }
- }
-
- if (code < 0x10000) {
- *dest++ = code;
- } else {
- /*
- * Simplified expression for
- * (((code - 0x10000) >> 10) & 0x3ff) | 0xd800
- */
- *dest++ = (code >> 10) + 0xd7c0;
- *dest++ = (code & 0x3ff) | 0xdc00;
- }
- }
- return dest;
-}
#include <efi_driver.h>
-/*
- * Check node type. We do not support partitions as controller handles.
+/**
+ * check_node_type() - check node type
+ *
+ * We do not support partitions as controller handles.
*
- * @handle handle to be checked
- * @return status code
+ * @handle: handle to be checked
+ * Return: status code
*/
static efi_status_t check_node_type(efi_handle_t handle)
{
return ret;
}
-/*
- * Check if the driver supports the controller.
+/**
+ * efi_uc_supported() - check if the driver supports the controller
*
- * @this driver binding protocol
- * @controller_handle handle of the controller
- * @remaining_device_path path specifying the child controller
- * @return status code
+ * @this: driver binding protocol
+ * @controller_handle: handle of the controller
+ * @remaining_device_path: path specifying the child controller
+ * Return: status code
*/
static efi_status_t EFIAPI efi_uc_supported(
struct efi_driver_binding_protocol *this,
return EFI_EXIT(ret);
}
-/*
- * Create child controllers and attach driver.
+/**
+ * efi_uc_start() - create child controllers and attach driver
*
- * @this driver binding protocol
- * @controller_handle handle of the controller
- * @remaining_device_path path specifying the child controller
- * @return status code
+ * @this: driver binding protocol
+ * @controller_handle: handle of the controller
+ * @remaining_device_path: path specifying the child controller
+ * Return: status code
*/
static efi_status_t EFIAPI efi_uc_start(
struct efi_driver_binding_protocol *this,
return EFI_EXIT(ret);
}
-/*
- * Remove a single child controller from the parent controller.
+/**
+ * disconnect_child() - remove a single child controller from the parent
+ * controller
*
- * @controller_handle parent controller
- * @child_handle child controller
- * @return status code
+ * @controller_handle: parent controller
+ * @child_handle: child controller
+ * Return: status code
*/
static efi_status_t disconnect_child(efi_handle_t controller_handle,
efi_handle_t child_handle)
return ret;
}
-/*
- * Remove child controllers and disconnect the controller.
+/**
+ * efi_uc_stop() - Remove child controllers and disconnect the controller
*
- * @this driver binding protocol
- * @controller_handle handle of the controller
- * @number_of_children number of child controllers to remove
- * @child_handle_buffer handles of the child controllers to remove
- * @return status code
+ * @this: driver binding protocol
+ * @controller_handle: handle of the controller
+ * @number_of_children: number of child controllers to remove
+ * @child_handle_buffer: handles of the child controllers to remove
+ * Return: status code
*/
static efi_status_t EFIAPI efi_uc_stop(
struct efi_driver_binding_protocol *this,
return EFI_EXIT(ret);
}
+/**
+ * efi_add_driver() - add driver
+ *
+ * @drv: driver to add
+ * Return: status code
+ */
static efi_status_t efi_add_driver(struct driver *drv)
{
efi_status_t ret;
return ret;
}
-/*
- * Initialize the EFI drivers.
- * Called by board_init_r().
+/**
+ * efi_driver_init() - initialize the EFI drivers
*
- * @return 0 = success, any other value will stop further execution
+ * Called by efi_init_obj_list().
+ *
+ * Return: 0 = success, any other value will stop further execution
*/
efi_status_t efi_driver_init(void)
{
return ret;
}
+/**
+ * efi_uc_init() - initialize the EFI uclass
+ *
+ * @class: the EFI uclass
+ * Return: 0 = success
+ */
static int efi_uc_init(struct uclass *class)
{
printf("EFI: Initializing UCLASS_EFI\n");
return 0;
}
+/**
+ * efi_uc_destroy() - destroy the EFI uclass
+ *
+ * @class: the EFI uclass
+ * Return: 0 = success
+ */
static int efi_uc_destroy(struct uclass *class)
{
printf("Destroying UCLASS_EFI\n");
config EFI_LOADER
bool "Support running EFI Applications in U-Boot"
- depends on (ARM || X86 || RISCV) && OF_LIBFDT
+ depends on (ARM || X86 || RISCV || SANDBOX) && OF_LIBFDT
# We need EFI_STUB_64BIT to be set on x86_64 with EFI_STUB
depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
interfaces to a loaded EFI application, enabling it to reuse U-Boot's
device drivers.
+config EFI_UNICODE_CAPITALIZATION
+ bool "Support Unicode capitalization"
+ depends on EFI_LOADER
+ default y
+ help
+ Select this option to enable correct handling of the capitalization of
+ Unicode codepoints in the range 0x0000-0xffff. If this option is not
+ set, only the the correct handling of the letters of the codepage
+ used by the FAT file system is ensured.
+
config EFI_LOADER_BOUNCE_BUFFER
bool "EFI Applications use bounce buffers for DMA operations"
depends on EFI_LOADER && ARM64
endif
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
-obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
-obj-y += efi_memory.o efi_device_path_to_text.o efi_device_path.o
-obj-y += efi_device_path_utilities.o efi_file.o efi_variable.o efi_bootmgr.o
+obj-y += efi_bootmgr.o
+obj-y += efi_boottime.o
+obj-y += efi_console.o
+obj-y += efi_device_path.o
+obj-y += efi_device_path_to_text.o
+obj-y += efi_device_path_utilities.o
+obj-y += efi_file.o
+obj-y += efi_image_loader.o
+obj-y += efi_memory.o
+obj-y += efi_root_node.o
+obj-y += efi_runtime.o
+obj-y += efi_unicode_collation.o
+obj-y += efi_variable.o
obj-y += efi_watchdog.o
obj-$(CONFIG_LCD) += efi_gop.o
obj-$(CONFIG_DM_VIDEO) += efi_gop.o
ptr += sizeof(u16);
lo->label = ptr;
- ptr += (utf16_strlen(lo->label) + 1) * 2;
+ ptr += (u16_strlen(lo->label) + 1) * 2;
lo->file_path = ptr;
ptr += lo->file_path_length;
/* List of all events */
LIST_HEAD(efi_events);
-/*
- * If we're running on nasty systems (32bit ARM booting into non-EFI Linux)
- * we need to do trickery with caches. Since we don't want to break the EFI
- * aware boot path, only apply hacks when loading exiting directly (breaking
- * direct Linux EFI booting along the way - oh well).
- */
-static bool efi_is_direct_boot = true;
-
#ifdef CONFIG_ARM
/*
* The "gd" pointer lives in a register on ARM and AArch64 that we declare
/*
* Special case handler for error/abort that just forces things back to u-boot
- * world so we can dump out an abort msg, without any care about returning back
- * to UEFI world.
+ * world so we can dump out an abort message, without any care about returning
+ * back to UEFI world.
*/
void efi_restore_gd(void)
{
* is_valid_tpl() - check if the task priority level is valid
*
* @tpl: TPL level to check
- * ReturnValue: status code
+ * Return: status code
*/
efi_status_t is_valid_tpl(efi_uintn_t tpl)
{
evt->notify_function = notify_function;
evt->notify_context = notify_context;
evt->group = group;
- /* Disable timers on bootup */
+ /* Disable timers on boot up */
evt->trigger_next = -1ULL;
evt->is_queued = false;
evt->is_signaled = false;
* efi_set_timer() - set the trigger time for a timer event or stop the event
* @event: event for which the timer is set
* @type: type of the timer
- * @trigger_time: trigger period in multiples of 100ns
+ * @trigger_time: trigger period in multiples of 100 ns
*
* This is the function for internal usage in U-Boot. For the API function
* implementing the SetTimer service see efi_set_timer_ext.
return EFI_INVALID_PARAMETER;
/*
- * The parameter defines a multiple of 100ns.
- * We use multiples of 1000ns. So divide by 10.
+ * The parameter defines a multiple of 100 ns.
+ * We use multiples of 1000 ns. So divide by 10.
*/
do_div(trigger_time, 10);
* event
* @event: event for which the timer is set
* @type: type of the timer
- * @trigger_time: trigger period in multiples of 100ns
+ * @trigger_time: trigger period in multiples of 100 ns
*
* This function implements the SetTimer service.
*
/**
* efi_get_drivers() - get all drivers associated to a controller
* @efiobj: handle of the controller
- * @protocol: protocol guid (optional)
+ * @protocol: protocol GUID (optional)
* @number_of_drivers: number of child controllers
* @driver_handle_buffer: handles of the the drivers
*
/**
* efi_disconnect_all_drivers() - disconnect all drivers from a controller
* @efiobj: handle of the controller
- * @protocol: protocol guid (optional)
+ * @protocol: protocol GUID (optional)
* @child_handle: handle of the child to destroy
*
* This function implements the DisconnectController service.
if (!guid)
return EFI_INVALID_PARAMETER;
- /* Check for guid override */
+ /* Check for GUID override */
for (i = 0; i < systab.nr_tables; i++) {
if (!guidcmp(guid, &systab.tables[i].guid)) {
if (table)
systab.nr_tables = i + 1;
out:
- /* systab.nr_tables may have changed. So we need to update the crc32 */
+ /* systab.nr_tables may have changed. So we need to update the CRC32 */
efi_update_table_header_crc32(&systab.hdr);
/* Notify that the configuration table was changed */
*
* Return: status code
*/
-efi_status_t efi_setup_loaded_image(
- struct efi_loaded_image *info, struct efi_object *obj,
- struct efi_device_path *device_path,
- struct efi_device_path *file_path)
+efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path,
+ struct efi_device_path *file_path,
+ struct efi_loaded_image_obj **handle_ptr,
+ struct efi_loaded_image **info_ptr)
{
efi_status_t ret;
+ struct efi_loaded_image *info;
+ struct efi_loaded_image_obj *obj;
+
+ info = calloc(1, sizeof(*info));
+ if (!info)
+ return EFI_OUT_OF_RESOURCES;
+ obj = calloc(1, sizeof(*obj));
+ if (!obj) {
+ free(info);
+ return EFI_OUT_OF_RESOURCES;
+ }
/* Add internal object to object list */
- efi_add_handle(obj);
- /* efi_exit() assumes that the handle points to the info */
- obj->handle = info;
+ efi_add_handle(&obj->parent);
+
+ if (info_ptr)
+ *info_ptr = info;
+ if (handle_ptr)
+ *handle_ptr = obj;
info->revision = EFI_LOADED_IMAGE_PROTOCOL_REVISION;
info->file_path = file_path;
+ info->system_table = &systab;
if (device_path) {
info->device_handle = efi_dp_find_obj(device_path, NULL);
* When asking for the device path interface, return
* bootefi_device_path
*/
- ret = efi_add_protocol(obj->handle, &efi_guid_device_path,
- device_path);
+ ret = efi_add_protocol(obj->parent.handle,
+ &efi_guid_device_path, device_path);
if (ret != EFI_SUCCESS)
goto failure;
}
* When asking for the loaded_image interface, just
* return handle which points to loaded_image_info
*/
- ret = efi_add_protocol(obj->handle, &efi_guid_loaded_image, info);
- if (ret != EFI_SUCCESS)
- goto failure;
-
- ret = efi_add_protocol(obj->handle,
- &efi_guid_device_path_to_text_protocol,
- (void *)&efi_device_path_to_text);
- if (ret != EFI_SUCCESS)
- goto failure;
-
- ret = efi_add_protocol(obj->handle,
- &efi_guid_device_path_utilities_protocol,
- (void *)&efi_device_path_utilities);
+ ret = efi_add_protocol(obj->parent.handle,
+ &efi_guid_loaded_image, info);
if (ret != EFI_SUCCESS)
goto failure;
efi_handle_t *image_handle)
{
struct efi_loaded_image *info;
- struct efi_object *obj;
+ struct efi_loaded_image_obj **image_obj =
+ (struct efi_loaded_image_obj **)image_handle;
efi_status_t ret;
EFI_ENTRY("%d, %p, %pD, %p, %zd, %p", boot_policy, parent_image,
goto error;
}
- info = calloc(1, sizeof(*info));
- if (!info) {
- ret = EFI_OUT_OF_RESOURCES;
- goto error;
- }
- obj = calloc(1, sizeof(*obj));
- if (!obj) {
- free(info);
- ret = EFI_OUT_OF_RESOURCES;
- goto error;
- }
-
if (!source_buffer) {
struct efi_device_path *dp, *fp;
* file parts:
*/
efi_dp_split_file_path(file_path, &dp, &fp);
- ret = efi_setup_loaded_image(info, obj, dp, fp);
+ ret = efi_setup_loaded_image(dp, fp, image_obj, &info);
if (ret != EFI_SUCCESS)
goto failure;
} else {
- /* In this case, file_path is the "device" path, ie.
+ /* In this case, file_path is the "device" path, i.e.
* something like a HARDWARE_DEVICE:MEMORY_MAPPED
*/
- ret = efi_setup_loaded_image(info, obj, file_path, NULL);
+ ret = efi_setup_loaded_image(file_path, NULL, image_obj, &info);
if (ret != EFI_SUCCESS)
- goto failure;
+ goto error;
}
- info->reserved = efi_load_pe(source_buffer, info);
- if (!info->reserved) {
+ (*image_obj)->entry = efi_load_pe(*image_obj, source_buffer, info);
+ if (!(*image_obj)->entry) {
ret = EFI_UNSUPPORTED;
goto failure;
}
info->system_table = &systab;
info->parent_handle = parent_image;
- *image_handle = obj->handle;
return EFI_EXIT(EFI_SUCCESS);
failure:
+ efi_delete_handle(*image_handle);
+ *image_handle = NULL;
free(info);
- efi_delete_handle(obj);
error:
return EFI_EXIT(ret);
}
/**
- * efi_start_image() - dall the entry point of an image
+ * efi_start_image() - call the entry point of an image
* @image_handle: handle of the image
* @exit_data_size: size of the buffer
* @exit_data: buffer to receive the exit data of the called image
unsigned long *exit_data_size,
s16 **exit_data)
{
- EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
- struct efi_system_table *st);
- struct efi_loaded_image *info = image_handle;
+ struct efi_loaded_image_obj *image_obj =
+ (struct efi_loaded_image_obj *)image_handle;
efi_status_t ret;
EFI_ENTRY("%p, %p, %p", image_handle, exit_data_size, exit_data);
- entry = info->reserved;
-
- efi_is_direct_boot = false;
/* call the image! */
- if (setjmp(&info->exit_jmp)) {
+ if (setjmp(&image_obj->exit_jmp)) {
/*
* We called the entry point of the child image with EFI_CALL
* in the lines below. The child image called the Exit() boot
assert(__efi_entry_check());
debug("%sEFI: %lu returned by started image\n",
__efi_nesting_dec(),
- (unsigned long)((uintptr_t)info->exit_status &
+ (unsigned long)((uintptr_t)image_obj->exit_status &
~EFI_ERROR_MASK));
- return EFI_EXIT(info->exit_status);
+ return EFI_EXIT(image_obj->exit_status);
}
- ret = EFI_CALL(entry(image_handle, &systab));
+ ret = EFI_CALL(image_obj->entry(image_handle, &systab));
/*
* Usually UEFI applications call Exit() instead of returning.
- * But because the world doesn not consist of ponies and unicorns,
+ * But because the world doesn't consist of ponies and unicorns,
* we're happy to emulate that behavior on behalf of a payload
* that forgot.
*/
int16_t *exit_data)
{
/*
- * We require that the handle points to the original loaded
- * image protocol interface.
- *
- * For getting the longjmp address this is safer than locating
- * the protocol because the protocol may have been reinstalled
- * pointing to another memory location.
- *
* TODO: We should call the unload procedure of the loaded
* image protocol.
*/
- struct efi_loaded_image *loaded_image_info = (void *)image_handle;
+ struct efi_loaded_image_obj *image_obj =
+ (struct efi_loaded_image_obj *)image_handle;
EFI_ENTRY("%p, %ld, %ld, %p", image_handle, exit_status,
exit_data_size, exit_data);
*/
efi_restore_gd();
- loaded_image_info->exit_status = exit_status;
- longjmp(&loaded_image_info->exit_jmp, 1);
+ image_obj->exit_status = exit_status;
+ longjmp(&image_obj->exit_jmp, 1);
panic("EFI application exited");
}
return EFI_EXIT(EFI_SUCCESS);
}
-/**
- * efi_exit_caches() - fix up caches for EFI payloads if necessary
- */
-static void efi_exit_caches(void)
-{
-#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
- /*
- * Grub on 32bit ARM needs to have caches disabled before jumping into
- * a zImage, but does not know of all cache layers. Give it a hand.
- */
- if (efi_is_direct_boot)
- cleanup_before_linux();
-#endif
-}
-
/**
* efi_exit_boot_services() - stop all boot services
* @image_handle: handle of the loaded image
}
}
- /* TODO Should persist EFI variables here */
+ /* TODO: Should persist EFI variables here */
board_quiesce_devices();
- /* Fix up caches for EFI payloads if necessary */
- efi_exit_caches();
-
/* This stops all lingering devices */
bootm_disable_interrupts();
- /* Disable boottime services */
+ /* Disable boot time services */
systab.con_in_handle = NULL;
systab.con_in = NULL;
systab.con_out_handle = NULL;
++*protocol_buffer_count;
}
- /* Copy guids */
+ /* Copy GUIDs */
if (*protocol_buffer_count) {
size_t j = 0;
* efi_connect_single_controller() - connect a single driver to a controller
* @controller_handle: controller
* @driver_image_handle: driver
- * @remain_device_path: remainting path
+ * @remain_device_path: remaining path
*
* Return: status code
*/
* details.
*
* First all driver binding protocol handles are tried for binding drivers.
- * Afterwards all handles that have openened a protocol of the controller
+ * Afterwards all handles that have opened a protocol of the controller
* with EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER are connected to drivers.
*
* Return: status code
/**
* efi_initialize_system_table() - Initialize system table
*
- * Return Value: status code
+ * Return: status code
*/
efi_status_t efi_initialize_system_table(void)
{
sizeof(struct efi_configuration_table),
(void **)&systab.tables);
- /* Set crc32 field in table headers */
+ /* Set CRC32 field in table headers */
efi_update_table_header_crc32(&systab.hdr);
efi_update_table_header_crc32(&efi_runtime_services.hdr);
efi_update_table_header_crc32(&efi_boot_services.hdr);
},
};
-const efi_guid_t efi_guid_text_output_protocol =
- EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID;
+const efi_guid_t efi_guid_text_input_ex_protocol =
+ EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID;
const efi_guid_t efi_guid_text_input_protocol =
EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID;
+const efi_guid_t efi_guid_text_output_protocol =
+ EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID;
#define cESC '\x1b'
#define ESC "\x1b"
{
struct simple_text_output_mode *con = &efi_con_mode;
struct cout_mode *mode = &efi_cout_modes[con->mode];
-
- EFI_ENTRY("%p, %p", this, string);
-
- unsigned int n16 = utf16_strlen(string);
- char buf[MAX_UTF8_PER_UTF16 * n16 + 1];
+ char *buf, *pos;
u16 *p;
+ efi_status_t ret = EFI_SUCCESS;
- *utf16_to_utf8((u8 *)buf, string, n16) = '\0';
+ EFI_ENTRY("%p, %p", this, string);
+ buf = malloc(utf16_utf8_strlen(string) + 1);
+ if (!buf) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
+ pos = buf;
+ utf16_utf8_strcpy(&pos, string);
fputs(stdout, buf);
+ free(buf);
/*
* Update the cursor position.
*
* The UEFI spec provides advance rules for U+0000, U+0008, U+000A,
* and U000D. All other characters, including control characters
- * U+0007 (bel) and U+0009 (tab), have to increase the column by one.
+ * U+0007 (BEL) and U+0009 (TAB), have to increase the column by one.
*/
for (p = string; *p; ++p) {
switch (*p) {
con->cursor_row = min(con->cursor_row, (s32)mode->rows - 1);
}
- return EFI_EXIT(EFI_SUCCESS);
+out:
+ return EFI_EXIT(ret);
}
static efi_status_t EFIAPI efi_cout_test_string(
return (mode->rows == rows) && (mode->columns == cols);
}
+/**
+ * query_console_serial() - query console size
+ *
+ * @rows pointer to return number of rows
+ * @columns pointer to return number of columns
+ * Returns 0 on success
+ */
static int query_console_serial(int *rows, int *cols)
{
- /* Ask the terminal about its size */
- int n[3];
+ int ret = 0;
+ int n[2];
u64 timeout;
/* Empty input buffer */
while (tstc())
getc();
- printf(ESC"[18t");
+ /*
+ * Not all terminals understand CSI [18t for querying the console size.
+ * We should adhere to escape sequences documented in the console_codes
+ * manpage and the ECMA-48 standard.
+ *
+ * So here we follow a different approach. We position the cursor to the
+ * bottom right and query its position. Before leaving the function we
+ * restore the original cursor position.
+ */
+ printf(ESC "7" /* Save cursor position */
+ ESC "[r" /* Set scrolling region to full window */
+ ESC "[999;999H" /* Move to bottom right corner */
+ ESC "[6n"); /* Query cursor position */
- /* Check if we have a terminal that understands */
+ /* Allow up to one second for a response */
timeout = timer_get_us() + 1000000;
while (!tstc())
- if (timer_get_us() > timeout)
- return -1;
-
- /* Read {depth,rows,cols} */
- if (term_read_reply(n, 3, 't'))
- return -1;
+ if (timer_get_us() > timeout) {
+ ret = -1;
+ goto out;
+ }
- *cols = n[2];
- *rows = n[1];
+ /* Read {rows,cols} */
+ if (term_read_reply(n, 2, 'R')) {
+ ret = 1;
+ goto out;
+ }
- return 0;
+ *cols = n[1];
+ *rows = n[0];
+out:
+ printf(ESC "8"); /* Restore cursor position */
+ return ret;
}
/*
{ 36, 46 }, /* 3: cyan */
{ 31, 41 }, /* 4: red */
{ 35, 45 }, /* 5: magenta */
- { 33, 43 }, /* 6: brown, map to yellow as edk2 does*/
- { 37, 47 }, /* 7: light grey, map to white */
+ { 33, 43 }, /* 6: brown, map to yellow as EDK2 does*/
+ { 37, 47 }, /* 7: light gray, map to white */
};
/* See EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetAttribute(). */
struct efi_simple_text_output_protocol *this,
unsigned long column, unsigned long row)
{
+ efi_status_t ret = EFI_SUCCESS;
+ struct simple_text_output_mode *con = &efi_con_mode;
+ struct cout_mode *mode = &efi_cout_modes[con->mode];
+
EFI_ENTRY("%p, %ld, %ld", this, column, row);
- printf(ESC"[%d;%df", (int)row, (int)column);
+ /* Check parameters */
+ if (!this) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ if (row >= mode->rows || column >= mode->columns) {
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+
+ /*
+ * Set cursor position by sending CSI H.
+ * EFI origin is [0, 0], terminal origin is [1, 1].
+ */
+ printf(ESC "[%d;%dH", (int)row + 1, (int)column + 1);
efi_con_mode.cursor_column = column;
efi_con_mode.cursor_row = row;
-
- return EFI_EXIT(EFI_SUCCESS);
+out:
+ return EFI_EXIT(ret);
}
static efi_status_t EFIAPI efi_cout_enable_cursor(
.mode = (void*)&efi_con_mode,
};
-static efi_status_t EFIAPI efi_cin_reset(
- struct efi_simple_input_interface *this,
- bool extended_verification)
-{
- EFI_ENTRY("%p, %d", this, extended_verification);
+/**
+ * struct efi_cin_notify_function - registered console input notify function
+ *
+ * @link: link to list
+ * @data: key to notify
+ * @function: function to call
+ */
+struct efi_cin_notify_function {
+ struct list_head link;
+ struct efi_key_data key;
+ efi_status_t (EFIAPI *function)
+ (struct efi_key_data *key_data);
+};
- /* Empty input buffer */
- while (tstc())
- getc();
+static bool key_available;
+static struct efi_key_data next_key;
+static LIST_HEAD(cin_notify_functions);
- return EFI_EXIT(EFI_SUCCESS);
+/**
+ * set_shift_mask() - set shift mask
+ *
+ * @mod: Xterm shift mask
+ */
+void set_shift_mask(int mod, struct efi_key_state *key_state)
+{
+ key_state->key_shift_state = EFI_SHIFT_STATE_VALID;
+ if (mod) {
+ --mod;
+ if (mod & 1)
+ key_state->key_shift_state |= EFI_LEFT_SHIFT_PRESSED;
+ if (mod & 2)
+ key_state->key_shift_state |= EFI_LEFT_ALT_PRESSED;
+ if (mod & 4)
+ key_state->key_shift_state |= EFI_LEFT_CONTROL_PRESSED;
+ if (mod & 8)
+ key_state->key_shift_state |= EFI_LEFT_LOGO_PRESSED;
+ } else {
+ key_state->key_shift_state |= EFI_LEFT_LOGO_PRESSED;
+ }
}
-/*
- * Analyze modifiers (shift, alt, ctrl) for function keys.
+/**
+ * analyze_modifiers() - analyze modifiers (shift, alt, ctrl) for function keys
+ *
* This gets called when we have already parsed CSI.
*
* @modifiers: bitmask (shift, alt, ctrl)
* @return: the unmodified code
*/
-static char skip_modifiers(int *modifiers)
+static int analyze_modifiers(struct efi_key_state *key_state)
{
- char c, mod = 0, ret = 0;
+ int c, mod = 0, ret = 0;
c = getc();
}
}
out:
- if (mod)
- --mod;
- if (modifiers)
- *modifiers = mod;
+ set_shift_mask(mod, key_state);
if (!ret)
ret = c;
return ret;
}
-static efi_status_t EFIAPI efi_cin_read_key_stroke(
- struct efi_simple_input_interface *this,
- struct efi_input_key *key)
+/**
+ * efi_cin_read_key() - read a key from the console input
+ *
+ * @key: - key received
+ * Return: - status code
+ */
+static efi_status_t efi_cin_read_key(struct efi_key_data *key)
{
struct efi_input_key pressed_key = {
.scan_code = 0,
.unicode_char = 0,
};
- char ch;
+ s32 ch;
- EFI_ENTRY("%p, %p", this, key);
+ if (console_read_unicode(&ch))
+ return EFI_NOT_READY;
- /* We don't do interrupts, so check for timers cooperatively */
- efi_timer_check();
+ key->key_state.key_shift_state = EFI_SHIFT_STATE_INVALID;
+ key->key_state.key_toggle_state = EFI_TOGGLE_STATE_INVALID;
- if (!tstc()) {
- /* No key pressed */
- return EFI_EXIT(EFI_NOT_READY);
- }
+ /* We do not support multi-word codes */
+ if (ch >= 0x10000)
+ ch = '?';
- ch = getc();
- if (ch == cESC) {
+ switch (ch) {
+ case 0x1b:
/*
* Xterm Control Sequences
* https://www.xfree86.org/4.8.0/ctlseqs.html
break;
case 'O': /* F1 - F4 */
ch = getc();
- /* skip modifiers */
- if (ch <= '9')
+ /* consider modifiers */
+ if (ch < 'P') {
+ set_shift_mask(ch - '0', &key->key_state);
ch = getc();
+ }
pressed_key.scan_code = ch - 'P' + 11;
break;
- case 'a'...'z':
- ch = ch - 'a';
- break;
case '[':
ch = getc();
switch (ch) {
pressed_key.scan_code = 5;
break;
case '1':
- ch = skip_modifiers(NULL);
+ ch = analyze_modifiers(&key->key_state);
switch (ch) {
case '1'...'5': /* F1 - F5 */
pressed_key.scan_code = ch - '1' + 11;
}
break;
case '2':
- ch = skip_modifiers(NULL);
+ ch = analyze_modifiers(&key->key_state);
switch (ch) {
case '0'...'1': /* F9 - F10 */
pressed_key.scan_code = ch - '0' + 19;
break;
case '3': /* DEL */
pressed_key.scan_code = 8;
- skip_modifiers(NULL);
+ analyze_modifiers(&key->key_state);
break;
case '5': /* PG UP */
pressed_key.scan_code = 9;
- skip_modifiers(NULL);
+ analyze_modifiers(&key->key_state);
break;
case '6': /* PG DOWN */
pressed_key.scan_code = 10;
- skip_modifiers(NULL);
+ analyze_modifiers(&key->key_state);
break;
- }
+ } /* [ */
break;
+ default:
+ /* ALT key */
+ set_shift_mask(3, &key->key_state);
}
- } else if (ch == 0x7f) {
+ break;
+ case 0x7f:
/* Backspace */
ch = 0x08;
}
- if (!pressed_key.scan_code)
+ if (pressed_key.scan_code) {
+ key->key_state.key_shift_state |= EFI_SHIFT_STATE_VALID;
+ } else {
pressed_key.unicode_char = ch;
- *key = pressed_key;
- return EFI_EXIT(EFI_SUCCESS);
+ /*
+ * Assume left control key for control characters typically
+ * entered using the control key.
+ */
+ if (ch >= 0x01 && ch <= 0x1f) {
+ key->key_state.key_shift_state |=
+ EFI_SHIFT_STATE_VALID;
+ switch (ch) {
+ case 0x01 ... 0x07:
+ case 0x0b ... 0x0c:
+ case 0x0e ... 0x1f:
+ key->key_state.key_shift_state |=
+ EFI_LEFT_CONTROL_PRESSED;
+ }
+ }
+ }
+ key->key = pressed_key;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ * efi_cin_notify() - notify registered functions
+ */
+static void efi_cin_notify(void)
+{
+ struct efi_cin_notify_function *item;
+
+ list_for_each_entry(item, &cin_notify_functions, link) {
+ bool match = true;
+
+ /* We do not support toggle states */
+ if (item->key.key.unicode_char || item->key.key.scan_code) {
+ if (item->key.key.unicode_char !=
+ next_key.key.unicode_char ||
+ item->key.key.scan_code != next_key.key.scan_code)
+ match = false;
+ }
+ if (item->key.key_state.key_shift_state &&
+ item->key.key_state.key_shift_state !=
+ next_key.key_state.key_shift_state)
+ match = false;
+
+ if (match)
+ /* We don't bother about the return code */
+ EFI_CALL(item->function(&next_key));
+ }
+}
+
+/**
+ * efi_cin_check() - check if keyboard input is available
+ */
+static void efi_cin_check(void)
+{
+ efi_status_t ret;
+
+ if (key_available) {
+ efi_signal_event(efi_con_in.wait_for_key, true);
+ return;
+ }
+
+ if (tstc()) {
+ ret = efi_cin_read_key(&next_key);
+ if (ret == EFI_SUCCESS) {
+ key_available = true;
+
+ /* Notify registered functions */
+ efi_cin_notify();
+
+ /* Queue the wait for key event */
+ if (key_available)
+ efi_signal_event(efi_con_in.wait_for_key, true);
+ }
+ }
+}
+
+/**
+ * efi_cin_empty_buffer() - empty input buffer
+ */
+static void efi_cin_empty_buffer(void)
+{
+ while (tstc())
+ getc();
+ key_available = false;
+}
+
+/**
+ * efi_cin_reset_ex() - reset console input
+ *
+ * @this: - the extended simple text input protocol
+ * @extended_verification: - extended verification
+ *
+ * This function implements the reset service of the
+ * EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * Return: old value of the task priority level
+ */
+static efi_status_t EFIAPI efi_cin_reset_ex(
+ struct efi_simple_text_input_ex_protocol *this,
+ bool extended_verification)
+{
+ efi_status_t ret = EFI_SUCCESS;
+
+ EFI_ENTRY("%p, %d", this, extended_verification);
+
+ /* Check parameters */
+ if (!this) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ efi_cin_empty_buffer();
+out:
+ return EFI_EXIT(ret);
}
-struct efi_simple_input_interface efi_con_in = {
+/**
+ * efi_cin_read_key_stroke_ex() - read key stroke
+ *
+ * @this: instance of the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
+ * @key_data: key read from console
+ * Return: status code
+ *
+ * This function implements the ReadKeyStrokeEx service of the
+ * EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ */
+static efi_status_t EFIAPI efi_cin_read_key_stroke_ex(
+ struct efi_simple_text_input_ex_protocol *this,
+ struct efi_key_data *key_data)
+{
+ efi_status_t ret = EFI_SUCCESS;
+
+ EFI_ENTRY("%p, %p", this, key_data);
+
+ /* Check parameters */
+ if (!this || !key_data) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ /* We don't do interrupts, so check for timers cooperatively */
+ efi_timer_check();
+
+ /* Enable console input after ExitBootServices */
+ efi_cin_check();
+
+ if (!key_available) {
+ ret = EFI_NOT_READY;
+ goto out;
+ }
+ *key_data = next_key;
+ key_available = false;
+ efi_con_in.wait_for_key->is_signaled = false;
+out:
+ return EFI_EXIT(ret);
+}
+
+/**
+ * efi_cin_set_state() - set toggle key state
+ *
+ * @this: instance of the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
+ * @key_toggle_state: key toggle state
+ * Return: status code
+ *
+ * This function implements the SetState service of the
+ * EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ */
+static efi_status_t EFIAPI efi_cin_set_state(
+ struct efi_simple_text_input_ex_protocol *this,
+ u8 key_toggle_state)
+{
+ EFI_ENTRY("%p, %u", this, key_toggle_state);
+ /*
+ * U-Boot supports multiple console input sources like serial and
+ * net console for which a key toggle state cannot be set at all.
+ *
+ * According to the UEFI specification it is allowable to not implement
+ * this service.
+ */
+ return EFI_EXIT(EFI_UNSUPPORTED);
+}
+
+/**
+ * efi_cin_register_key_notify() - register key notification function
+ *
+ * @this: instance of the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
+ * @key_data: key to be notified
+ * @key_notify_function: function to be called if the key is pressed
+ * @notify_handle: handle for unregistering the notification
+ * Return: status code
+ *
+ * This function implements the SetState service of the
+ * EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ */
+static efi_status_t EFIAPI efi_cin_register_key_notify(
+ struct efi_simple_text_input_ex_protocol *this,
+ struct efi_key_data *key_data,
+ efi_status_t (EFIAPI *key_notify_function)(
+ struct efi_key_data *key_data),
+ void **notify_handle)
+{
+ efi_status_t ret = EFI_SUCCESS;
+ struct efi_cin_notify_function *notify_function;
+
+ EFI_ENTRY("%p, %p, %p, %p",
+ this, key_data, key_notify_function, notify_handle);
+
+ /* Check parameters */
+ if (!this || !key_data || !key_notify_function || !notify_handle) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ EFI_PRINT("u+%04x, sc %04x, sh %08x, tg %02x\n",
+ key_data->key.unicode_char,
+ key_data->key.scan_code,
+ key_data->key_state.key_shift_state,
+ key_data->key_state.key_toggle_state);
+
+ notify_function = calloc(1, sizeof(struct efi_cin_notify_function));
+ if (!notify_function) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
+ notify_function->key = *key_data;
+ notify_function->function = key_notify_function;
+ list_add_tail(¬ify_function->link, &cin_notify_functions);
+ *notify_handle = notify_function;
+out:
+ return EFI_EXIT(ret);
+}
+
+/**
+ * efi_cin_unregister_key_notify() - unregister key notification function
+ *
+ * @this: instance of the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
+ * @notification_handle: handle received when registering
+ * Return: status code
+ *
+ * This function implements the SetState service of the
+ * EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ */
+static efi_status_t EFIAPI efi_cin_unregister_key_notify(
+ struct efi_simple_text_input_ex_protocol *this,
+ void *notification_handle)
+{
+ efi_status_t ret = EFI_INVALID_PARAMETER;
+ struct efi_cin_notify_function *item, *notify_function =
+ notification_handle;
+
+ EFI_ENTRY("%p, %p", this, notification_handle);
+
+ /* Check parameters */
+ if (!this || !notification_handle)
+ goto out;
+
+ list_for_each_entry(item, &cin_notify_functions, link) {
+ if (item == notify_function) {
+ ret = EFI_SUCCESS;
+ break;
+ }
+ }
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ /* Remove the notify function */
+ list_del(¬ify_function->link);
+ free(notify_function);
+out:
+ return EFI_EXIT(ret);
+}
+
+
+/**
+ * efi_cin_reset() - drain the input buffer
+ *
+ * @this: instance of the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
+ * @extended_verification: allow for exhaustive verification
+ * Return: status code
+ *
+ * This function implements the Reset service of the
+ * EFI_SIMPLE_TEXT_INPUT_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ */
+static efi_status_t EFIAPI efi_cin_reset
+ (struct efi_simple_text_input_protocol *this,
+ bool extended_verification)
+{
+ efi_status_t ret = EFI_SUCCESS;
+
+ EFI_ENTRY("%p, %d", this, extended_verification);
+
+ /* Check parameters */
+ if (!this) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ efi_cin_empty_buffer();
+out:
+ return EFI_EXIT(ret);
+}
+
+/**
+ * efi_cin_read_key_stroke() - read key stroke
+ *
+ * @this: instance of the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
+ * @key: key read from console
+ * Return: status code
+ *
+ * This function implements the ReadKeyStroke service of the
+ * EFI_SIMPLE_TEXT_INPUT_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ */
+static efi_status_t EFIAPI efi_cin_read_key_stroke
+ (struct efi_simple_text_input_protocol *this,
+ struct efi_input_key *key)
+{
+ efi_status_t ret = EFI_SUCCESS;
+
+ EFI_ENTRY("%p, %p", this, key);
+
+ /* Check parameters */
+ if (!this || !key) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ /* We don't do interrupts, so check for timers cooperatively */
+ efi_timer_check();
+
+ /* Enable console input after ExitBootServices */
+ efi_cin_check();
+
+ if (!key_available) {
+ ret = EFI_NOT_READY;
+ goto out;
+ }
+ *key = next_key.key;
+ key_available = false;
+ efi_con_in.wait_for_key->is_signaled = false;
+out:
+ return EFI_EXIT(ret);
+}
+
+static struct efi_simple_text_input_ex_protocol efi_con_in_ex = {
+ .reset = efi_cin_reset_ex,
+ .read_key_stroke_ex = efi_cin_read_key_stroke_ex,
+ .wait_for_key_ex = NULL,
+ .set_state = efi_cin_set_state,
+ .register_key_notify = efi_cin_register_key_notify,
+ .unregister_key_notify = efi_cin_unregister_key_notify,
+};
+
+struct efi_simple_text_input_protocol efi_con_in = {
.reset = efi_cin_reset,
.read_key_stroke = efi_cin_read_key_stroke,
.wait_for_key = NULL,
static struct efi_event *console_timer_event;
-static void EFIAPI efi_key_notify(struct efi_event *event, void *context)
-{
-}
-
/*
- * Notification function of the console timer event.
+ * efi_console_timer_notify() - notify the console timer event
*
- * event: console timer event
- * context: not used
+ * @event: console timer event
+ * @context: not used
*/
static void EFIAPI efi_console_timer_notify(struct efi_event *event,
void *context)
{
EFI_ENTRY("%p, %p", event, context);
+ efi_cin_check();
+ EFI_EXIT(EFI_SUCCESS);
+}
- /* Check if input is available */
- if (tstc()) {
- /* Queue the wait for key event */
- efi_con_in.wait_for_key->is_signaled = true;
- efi_signal_event(efi_con_in.wait_for_key, true);
- }
+/**
+ * efi_key_notify() - notify the wait for key event
+ *
+ * @event: wait for key event
+ * @context: not used
+ */
+static void EFIAPI efi_key_notify(struct efi_event *event, void *context)
+{
+ EFI_ENTRY("%p, %p", event, context);
+ efi_cin_check();
EFI_EXIT(EFI_SUCCESS);
}
-/* This gets called from do_bootefi_exec(). */
+/**
+ * efi_console_register() - install the console protocols
+ *
+ * This function is called from do_bootefi_exec().
+ */
int efi_console_register(void)
{
efi_status_t r;
r = efi_create_handle((efi_handle_t *)&efi_console_output_obj);
if (r != EFI_SUCCESS)
goto out_of_memory;
+
r = efi_add_protocol(efi_console_output_obj->handle,
&efi_guid_text_output_protocol, &efi_con_out);
if (r != EFI_SUCCESS)
goto out_of_memory;
+ systab.con_out_handle = efi_console_output_obj->handle;
+ systab.stderr_handle = efi_console_output_obj->handle;
+
r = efi_create_handle((efi_handle_t *)&efi_console_input_obj);
if (r != EFI_SUCCESS)
goto out_of_memory;
+
r = efi_add_protocol(efi_console_input_obj->handle,
&efi_guid_text_input_protocol, &efi_con_in);
if (r != EFI_SUCCESS)
goto out_of_memory;
+ systab.con_in_handle = efi_console_input_obj->handle;
+ r = efi_add_protocol(efi_console_input_obj->handle,
+ &efi_guid_text_input_ex_protocol, &efi_con_in_ex);
+ if (r != EFI_SUCCESS)
+ goto out_of_memory;
/* Create console events */
r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK, efi_key_notify,
printf("ERROR: Failed to register WaitForKey event\n");
return r;
}
+ efi_con_in_ex.wait_for_key_ex = efi_con_in.wait_for_key;
r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
efi_console_timer_notify, NULL, NULL,
&console_timer_event);
printf("ERROR: Failed to set console timer\n");
return r;
out_of_memory:
- printf("ERROR: Out of meemory\n");
+ printf("ERROR: Out of memory\n");
return r;
}
.length = sizeof(END),
};
-#define U_BOOT_GUID \
- EFI_GUID(0xe61d73b9, 0xa384, 0x4acc, \
- 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3, 0x62, 0x8b)
-
/* template ROOT node: */
static const struct efi_device_path_vendor ROOT = {
.dp = {
const efi_guid_t efi_guid_device_path_to_text_protocol =
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID;
+/**
+ * efi_str_to_u16() - convert ASCII string to UTF-16
+ *
+ * A u16 buffer is allocated from pool. The ASCII string is copied to the u16
+ * buffer.
+ *
+ * @str: ASCII string
+ * Return: UTF-16 string. NULL if out of memory.
+ */
static u16 *efi_str_to_u16(char *str)
{
efi_uintn_t len;
if (ret != EFI_SUCCESS)
return NULL;
ascii2unicode(out, str);
- out[len - 1] = 0;
return out;
}
#include <charset.h>
#include <efi_loader.h>
#include <malloc.h>
+#include <mapmem.h>
#include <fs.h>
/* GUID for file system information */
return 0;
}
-/* NOTE: despite what you would expect, 'file_name' is actually a path.
- * With windoze style backlashes, ofc.
+/**
+ * file_open() - open a file handle
+ *
+ * @fs: file system
+ * @parent: directory relative to which the file is to be opened
+ * @file_name: path of the file to be opened. '\', '.', or '..' may
+ * be used as modifiers. A leading backslash indicates an
+ * absolute path.
+ * @mode: bit mask indicating the access mode (read, write,
+ * create)
+ * @attributes: attributes for newly created file
+ * Returns: handle to the opened file or NULL
*/
static struct efi_file_handle *file_open(struct file_system *fs,
- struct file_handle *parent, s16 *file_name, u64 mode)
+ struct file_handle *parent, s16 *file_name, u64 mode,
+ u64 attributes)
{
struct file_handle *fh;
char f0[MAX_UTF8_PER_UTF16] = {0};
if (file_name) {
utf16_to_utf8((u8 *)f0, (u16 *)file_name, 1);
- flen = utf16_strlen((u16 *)file_name);
+ flen = u16_strlen((u16 *)file_name);
}
/* we could have a parent, but also an absolute path: */
if (set_blk_dev(fh))
goto error;
- if (!((mode & EFI_FILE_MODE_CREATE) || fs_exists(fh->path)))
+ if ((mode & EFI_FILE_MODE_CREATE) &&
+ (attributes & EFI_FILE_DIRECTORY)) {
+ if (fs_mkdir(fh->path))
+ goto error;
+ } else if (!((mode & EFI_FILE_MODE_CREATE) ||
+ fs_exists(fh->path)))
goto error;
/* figure out if file is a directory: */
s16 *file_name, u64 open_mode, u64 attributes)
{
struct file_handle *fh = to_fh(file);
+ efi_status_t ret;
EFI_ENTRY("%p, %p, \"%ls\", %llx, %llu", file, new_handle, file_name,
open_mode, attributes);
- *new_handle = file_open(fh->fs, fh, file_name, open_mode);
- if (!*new_handle)
- return EFI_EXIT(EFI_NOT_FOUND);
+ /* Check parameters */
+ if (!file || !new_handle || !file_name) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ if (open_mode != EFI_FILE_MODE_READ &&
+ open_mode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE) &&
+ open_mode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE |
+ EFI_FILE_MODE_CREATE)) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ /*
+ * The UEFI spec requires that attributes are only set in create mode.
+ * The SCT does not care about this and sets EFI_FILE_DIRECTORY in
+ * read mode. EDK2 does not check that attributes are zero if not in
+ * create mode.
+ *
+ * So here we only check attributes in create mode and do not check
+ * that they are zero otherwise.
+ */
+ if ((open_mode & EFI_FILE_MODE_CREATE) &&
+ (attributes & (EFI_FILE_READ_ONLY | ~EFI_FILE_VALID_ATTR))) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
- return EFI_EXIT(EFI_SUCCESS);
+ /* Open file */
+ *new_handle = file_open(fh->fs, fh, file_name, open_mode, attributes);
+ if (*new_handle)
+ ret = EFI_SUCCESS;
+ else
+ ret = EFI_NOT_FOUND;
+out:
+ return EFI_EXIT(ret);
}
static efi_status_t file_close(struct file_handle *fh)
static efi_status_t EFIAPI efi_file_delete(struct efi_file_handle *file)
{
struct file_handle *fh = to_fh(file);
+ efi_status_t ret = EFI_SUCCESS;
+
EFI_ENTRY("%p", file);
+
+ if (set_blk_dev(fh)) {
+ ret = EFI_DEVICE_ERROR;
+ goto error;
+ }
+
+ if (fs_unlink(fh->path))
+ ret = EFI_DEVICE_ERROR;
file_close(fh);
- return EFI_EXIT(EFI_WARN_DELETE_FAILURE);
+
+error:
+ return EFI_EXIT(ret);
}
static efi_status_t file_read(struct file_handle *fh, u64 *buffer_size,
{
loff_t actread;
- if (fs_read(fh->path, (ulong)buffer, fh->offset,
+ if (fs_read(fh->path, map_to_sysmem(buffer), fh->offset,
*buffer_size, &actread))
return EFI_DEVICE_ERROR;
goto error;
}
- if (fs_write(fh->path, (ulong)buffer, fh->offset, *buffer_size,
+ if (fs_write(fh->path, map_to_sysmem(buffer), fh->offset, *buffer_size,
&actwrite)) {
ret = EFI_DEVICE_ERROR;
goto error;
struct file_handle *fh = to_fh(file);
efi_status_t ret = EFI_SUCCESS;
- EFI_ENTRY("%p, %p, %p, %p", file, info_type, buffer_size, buffer);
+ EFI_ENTRY("%p, %pUl, %p, %p", file, info_type, buffer_size, buffer);
if (!guidcmp(info_type, &efi_file_info_guid)) {
struct efi_file_info *info = buffer;
EFI_ENTRY("%p, %p", this, root);
- *root = file_open(fs, NULL, NULL, 0);
+ *root = file_open(fs, NULL, NULL, 0, 0);
return EFI_EXIT(EFI_SUCCESS);
}
* If the program counter is located within the image the offset to the base
* address is shown.
*
+ * @obj: EFI object
* @image: loaded image
* @pc: program counter (use NULL to suppress offset output)
* @return: status code
*/
-efi_status_t efi_print_image_info(struct efi_loaded_image *image, void *pc)
+static efi_status_t efi_print_image_info(struct efi_loaded_image_obj *obj,
+ struct efi_loaded_image *image,
+ void *pc)
{
- if (!image)
- return EFI_INVALID_PARAMETER;
printf("UEFI image");
printf(" [0x%p:0x%p]",
- image->reloc_base, image->reloc_base + image->reloc_size - 1);
- if (pc && pc >= image->reloc_base &&
- pc < image->reloc_base + image->reloc_size)
- printf(" pc=0x%zx", pc - image->reloc_base);
+ obj->reloc_base, obj->reloc_base + obj->reloc_size - 1);
+ if (pc && pc >= obj->reloc_base &&
+ pc < obj->reloc_base + obj->reloc_size)
+ printf(" pc=0x%zx", pc - obj->reloc_base);
if (image->file_path)
printf(" '%pD'", image->file_path);
printf("\n");
list_for_each_entry(handler, &efiobj->protocols, link) {
if (!guidcmp(handler->guid, &efi_guid_loaded_image)) {
efi_print_image_info(
+ (struct efi_loaded_image_obj *)efiobj,
handler->protocol_interface, pc);
}
}
* piece of memory. On successful load it then returns the entry point for
* the binary. Otherwise NULL.
*/
-void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info)
+void *efi_load_pe(struct efi_loaded_image_obj *handle, void *efi,
+ struct efi_loaded_image *loaded_image_info)
{
IMAGE_NT_HEADERS32 *nt;
IMAGE_DOS_HEADER *dos;
/* Populate the loaded image interface bits */
loaded_image_info->image_base = efi;
loaded_image_info->image_size = image_size;
- loaded_image_info->reloc_base = efi_reloc;
- loaded_image_info->reloc_size = virt_size;
+ handle->reloc_base = efi_reloc;
+ handle->reloc_size = virt_size;
return entry;
}
return -1;
}
+static uint64_t desc_get_end(struct efi_mem_desc *desc)
+{
+ return desc->physical_start + (desc->num_pages << EFI_PAGE_SHIFT);
+}
+
static void efi_mem_sort(void)
{
+ struct list_head *lhandle;
+ struct efi_mem_list *prevmem = NULL;
+ bool merge_again = true;
+
list_sort(NULL, &efi_mem, efi_mem_cmp);
+
+ /* Now merge entries that can be merged */
+ while (merge_again) {
+ merge_again = false;
+ list_for_each(lhandle, &efi_mem) {
+ struct efi_mem_list *lmem;
+ struct efi_mem_desc *prev = &prevmem->desc;
+ struct efi_mem_desc *cur;
+ uint64_t pages;
+
+ lmem = list_entry(lhandle, struct efi_mem_list, link);
+ if (!prevmem) {
+ prevmem = lmem;
+ continue;
+ }
+
+ cur = &lmem->desc;
+
+ if ((desc_get_end(cur) == prev->physical_start) &&
+ (prev->type == cur->type) &&
+ (prev->attribute == cur->attribute)) {
+ /* There is an existing map before, reuse it */
+ pages = cur->num_pages;
+ prev->num_pages += pages;
+ prev->physical_start -= pages << EFI_PAGE_SHIFT;
+ prev->virtual_start -= pages << EFI_PAGE_SHIFT;
+ list_del(&lmem->link);
+ free(lmem);
+
+ merge_again = true;
+ break;
+ }
+
+ prevmem = lmem;
+ }
+ }
}
/** efi_mem_carve_out - unmap memory region
switch (type) {
case EFI_ALLOCATE_ANY_PAGES:
/* Any page */
- addr = efi_find_free_memory(len, gd->start_addr_sp);
+ addr = efi_find_free_memory(len, -1ULL);
if (!addr) {
r = EFI_NOT_FOUND;
break;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Root node for system services
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <efi_loader.h>
+
+const efi_guid_t efi_u_boot_guid = U_BOOT_GUID;
+
+struct efi_root_dp {
+ struct efi_device_path_vendor vendor;
+ struct efi_device_path end;
+} __packed;
+
+/**
+ * efi_root_node_register() - create root node
+ *
+ * Create the root node on which we install all protocols that are
+ * not related to a loaded image or a driver.
+ *
+ * Return: status code
+ */
+efi_status_t efi_root_node_register(void)
+{
+ efi_handle_t root;
+ efi_status_t ret;
+ struct efi_root_dp *dp;
+
+ /* Create handle */
+ ret = efi_create_handle(&root);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ /* Install device path protocol */
+ dp = calloc(1, sizeof(*dp));
+ if (!dp)
+ return EFI_OUT_OF_RESOURCES;
+
+ /* Fill vendor node */
+ dp->vendor.dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE;
+ dp->vendor.dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR;
+ dp->vendor.dp.length = sizeof(struct efi_device_path_vendor);
+ dp->vendor.guid = efi_u_boot_guid;
+
+ /* Fill end node */
+ dp->end.type = DEVICE_PATH_TYPE_END;
+ dp->end.sub_type = DEVICE_PATH_SUB_TYPE_END;
+ dp->end.length = sizeof(struct efi_device_path);
+
+ /* Install device path protocol */
+ ret = efi_add_protocol(root, &efi_guid_device_path, dp);
+ if (ret != EFI_SUCCESS)
+ goto failure;
+
+ /* Install device path to text protocol */
+ ret = efi_add_protocol(root, &efi_guid_device_path_to_text_protocol,
+ (void *)&efi_device_path_to_text);
+ if (ret != EFI_SUCCESS)
+ goto failure;
+
+ /* Install device path utilities protocol */
+ ret = efi_add_protocol(root, &efi_guid_device_path_utilities_protocol,
+ (void *)&efi_device_path_utilities);
+ if (ret != EFI_SUCCESS)
+ goto failure;
+
+ /* Install Unicode collation protocol */
+ ret = efi_add_protocol(root, &efi_guid_unicode_collation_protocol,
+ (void *)&efi_unicode_collation_protocol);
+ if (ret != EFI_SUCCESS)
+ goto failure;
+
+failure:
+ return ret;
+}
static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void);
/*
- * TODO(sjg@chromium.org): These defines and structs should come from the elf
- * header for each arch (or a generic header) rather than being repeated here.
+ * TODO(sjg@chromium.org): These defines and structures should come from the ELF
+ * header for each architecture (or a generic header) rather than being repeated
+ * here.
*/
#if defined(__aarch64__)
#define R_RELATIVE R_AARCH64_RELATIVE
};
/*
- * EFI Runtime code lives in 2 stages. In the first stage, U-Boot and an EFI
+ * EFI runtime code lives in two stages. In the first stage, U-Boot and an EFI
* payload are running concurrently at the same time. In this mode, we can
* handle a good number of runtime callbacks
*/
}
/**
- * efi_reset_system_boottime() - reset system at boottime
+ * efi_reset_system_boottime() - reset system at boot time
*
* This function implements the ResetSystem() runtime service before
* SetVirtualAddressMap() is called.
}
/**
- * efi_get_time_boottime() - get current time at boottime
+ * efi_get_time_boottime() - get current time at boot time
*
* This function implements the GetTime runtime service before
* SetVirtualAddressMap() is called.
*p = newaddr;
}
- /* Update crc32 */
+ /* Update CRC32 */
efi_update_table_header_crc32(&efi_runtime_services.hdr);
}
* available at runtime.
*
* @mmio_ptr: address of the memory-mapped IO region
- * @len: size of thememory-mapped IO region
+ * @len: size of the memory-mapped IO region
* Returns: status code
*/
efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len)
*
* @capsule_header_array: pointer to array of virtual pointers
* @capsule_count: number of pointers in capsule_header_array
- * @capsule_size: maximum capsule size
+ * @maximum_capsule_size: maximum capsule size
* @reset_type: type of reset needed for capsule update
* Returns: status code
*/
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * EFI Unicode collation protocol
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#include <common.h>
+#include <charset.h>
+#include <cp1250.h>
+#include <cp437.h>
+#include <efi_loader.h>
+
+/* Characters that may not be used in file names */
+static const char illegal[] = "<>:\"/\\|?*";
+
+/*
+ * EDK2 assumes codepage 1250 when creating FAT 8.3 file names.
+ * Linux defaults to codepage 437 for FAT 8.3 file names.
+ */
+#if CONFIG_FAT_DEFAULT_CODEPAGE == 1250
+/* Unicode code points for code page 1250 characters 0x80 - 0xff */
+static const u16 codepage[] = CP1250;
+#else
+/* Unicode code points for code page 437 characters 0x80 - 0xff */
+static const u16 codepage[] = CP437;
+#endif
+
+/* GUID of the EFI_UNICODE_COLLATION_PROTOCOL */
+const efi_guid_t efi_guid_unicode_collation_protocol =
+ EFI_UNICODE_COLLATION_PROTOCOL2_GUID;
+
+/**
+ * efi_stri_coll() - compare utf-16 strings case-insenitively
+ *
+ * @this: unicode collation protocol instance
+ * @s1: first string
+ * @s2: second string
+ *
+ * This function implements the StriColl() service of the
+ * EFI_UNICODE_COLLATION_PROTOCOL.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * TODO:
+ * The implementation does not follow the Unicode collation algorithm.
+ * For ASCII characters it results in the same sort order as EDK2.
+ * We could use table UNICODE_CAPITALIZATION_TABLE for better results.
+ *
+ * Return: 0: s1 == s2, > 0: s1 > s2, < 0: s1 < s2
+ */
+static efi_intn_t EFIAPI efi_stri_coll(
+ struct efi_unicode_collation_protocol *this, u16 *s1, u16 *s2)
+{
+ s32 c1, c2;
+ efi_intn_t ret = 0;
+
+ EFI_ENTRY("%p, %ls, %ls", this, s1, s2);
+ for (; *s1 | *s2; ++s1, ++s2) {
+ c1 = utf_to_upper(*s1);
+ c2 = utf_to_upper(*s2);
+ if (c1 < c2) {
+ ret = -1;
+ goto out;
+ } else if (c1 > c2) {
+ ret = 1;
+ goto out;
+ }
+ }
+out:
+ EFI_EXIT(EFI_SUCCESS);
+ return ret;
+}
+
+/**
+ * metai_match() - compare utf-16 string with a pattern string case-insenitively
+ *
+ * @s: string to compare
+ * @p: pattern string
+ *
+ * The pattern string may use these:
+ * - * matches >= 0 characters
+ * - ? matches 1 character
+ * - [<char1><char2>...<charN>] match any character in the set
+ * - [<char1>-<char2>] matches any character in the range
+ *
+ * This function is called my efi_metai_match().
+ *
+ * For '*' pattern searches this function calls itself recursively.
+ * Performance-wise this is suboptimal, especially for multiple '*' wildcards.
+ * But it results in simple code.
+ *
+ * Return: true if the string is matched.
+ */
+static bool metai_match(const u16 *s, const u16 *p)
+{
+ u16 first;
+
+ for (; *s && *p; ++s, ++p) {
+ switch (*p) {
+ case '*':
+ /* Match 0 or more characters */
+ ++p;
+ for (;; ++s) {
+ if (metai_match(s, p))
+ return true;
+ if (!*s)
+ return false;
+ }
+ case '?':
+ /* Match any one character */
+ break;
+ case '[':
+ /* Match any character in the set */
+ ++p;
+ first = *p;
+ if (first == ']')
+ /* Empty set */
+ return false;
+ ++p;
+ if (*p == '-') {
+ /* Range */
+ ++p;
+ if (*s < first || *s > *p)
+ return false;
+ ++p;
+ if (*p != ']')
+ return false;
+ } else {
+ /* Set */
+ bool hit = false;
+
+ if (*s == first)
+ hit = true;
+ for (; *p && *p != ']'; ++p) {
+ if (*p == *s)
+ hit = true;
+ }
+ if (!hit || *p != ']')
+ return false;
+ }
+ break;
+ default:
+ /* Match one character */
+ if (*p != *s)
+ return false;
+ }
+ }
+ if (!*p && !*s)
+ return true;
+ return false;
+}
+
+/**
+ * efi_metai_match() - compare utf-16 string with a pattern string
+ * case-insenitively
+ *
+ * @this: unicode collation protocol instance
+ * @s: string to compare
+ * @p: pattern string
+ *
+ * The pattern string may use these:
+ * - * matches >= 0 characters
+ * - ? matches 1 character
+ * - [<char1><char2>...<charN>] match any character in the set
+ * - [<char1>-<char2>] matches any character in the range
+ *
+ * This function implements the MetaMatch() service of the
+ * EFI_UNICODE_COLLATION_PROTOCOL.
+ *
+ * Return: true if the string is matched.
+ */
+static bool EFIAPI efi_metai_match(struct efi_unicode_collation_protocol *this,
+ const u16 *string, const u16 *pattern)
+{
+ bool ret;
+
+ EFI_ENTRY("%p, %ls, %ls", this, string, pattern);
+ ret = metai_match(string, pattern);
+ EFI_EXIT(EFI_SUCCESS);
+ return ret;
+}
+
+/**
+ * efi_str_lwr() - convert to lower case
+ *
+ * @this: unicode collation protocol instance
+ * @string: string to convert
+ * @p: pattern string
+ *
+ * The conversion is done in place. As long as upper and lower letters use the
+ * same number of words this does not pose a problem.
+ *
+ * This function implements the StrLwr() service of the
+ * EFI_UNICODE_COLLATION_PROTOCOL.
+ */
+static void EFIAPI efi_str_lwr(struct efi_unicode_collation_protocol *this,
+ u16 *string)
+{
+ EFI_ENTRY("%p, %ls", this, string);
+ for (; *string; ++string)
+ *string = utf_to_lower(*string);
+ EFI_EXIT(EFI_SUCCESS);
+}
+
+/**
+ * efi_str_upr() - convert to upper case
+ *
+ * @this: unicode collation protocol instance
+ * @string: string to convert
+ * @p: pattern string
+ *
+ * The conversion is done in place. As long as upper and lower letters use the
+ * same number of words this does not pose a problem.
+ *
+ * This function implements the StrUpr() service of the
+ * EFI_UNICODE_COLLATION_PROTOCOL.
+ */
+static void EFIAPI efi_str_upr(struct efi_unicode_collation_protocol *this,
+ u16 *string)
+{
+ EFI_ENTRY("%p, %ls", this, string);
+ for (; *string; ++string)
+ *string = utf_to_upper(*string);
+ EFI_EXIT(EFI_SUCCESS);
+}
+
+/**
+ * efi_fat_to_str() - convert an 8.3 file name from an OEM codepage to Unicode
+ *
+ * @this: unicode collation protocol instance
+ * @fat_size: size of the string to convert
+ * @fat: string to convert
+ * @string: converted string
+ *
+ * This function implements the FatToStr() service of the
+ * EFI_UNICODE_COLLATION_PROTOCOL.
+ */
+static void EFIAPI efi_fat_to_str(struct efi_unicode_collation_protocol *this,
+ efi_uintn_t fat_size, char *fat, u16 *string)
+{
+ efi_uintn_t i;
+ u16 c;
+
+ EFI_ENTRY("%p, %zu, %s, %p", this, fat_size, fat, string);
+ for (i = 0; i < fat_size; ++i) {
+ c = (unsigned char)fat[i];
+ if (c > 0x80)
+ c = codepage[i - 0x80];
+ string[i] = c;
+ if (!c)
+ break;
+ }
+ string[i] = 0;
+ EFI_EXIT(EFI_SUCCESS);
+}
+
+/**
+ * efi_fat_to_str() - convert a utf-16 string to legal characters for a FAT
+ * file name in an OEM code page
+ *
+ * @this: unicode collation protocol instance
+ * @string: Unicode string to convert
+ * @fat_size: size of the target buffer
+ * @fat: converted string
+ *
+ * This function implements the StrToFat() service of the
+ * EFI_UNICODE_COLLATION_PROTOCOL.
+ *
+ * Return: true if an illegal character was substituted by '_'.
+ */
+static bool EFIAPI efi_str_to_fat(struct efi_unicode_collation_protocol *this,
+ const u16 *string, efi_uintn_t fat_size,
+ char *fat)
+{
+ efi_uintn_t i;
+ s32 c;
+ bool ret = false;
+
+ EFI_ENTRY("%p, %ls, %zu, %p", this, string, fat_size, fat);
+ for (i = 0; i < fat_size;) {
+ c = utf16_get(&string);
+ switch (c) {
+ /* Ignore period and space */
+ case '.':
+ case ' ':
+ continue;
+ case 0:
+ break;
+ }
+ c = utf_to_upper(c);
+ if (c >= 0x80) {
+ int j;
+
+ /* Look for codepage translation */
+ for (j = 0; j < 0x80; ++j) {
+ if (c == codepage[j]) {
+ c = j + 0x80;
+ break;
+ }
+ }
+ if (j >= 0x80) {
+ c = '_';
+ ret = true;
+ }
+ } else if (c && (c < 0x20 || strchr(illegal, c))) {
+ c = '_';
+ ret = true;
+ }
+
+ fat[i] = c;
+ if (!c)
+ break;
+ ++i;
+ }
+ EFI_EXIT(EFI_SUCCESS);
+ return ret;
+}
+
+const struct efi_unicode_collation_protocol efi_unicode_collation_protocol = {
+ .stri_coll = efi_stri_coll,
+ .metai_match = efi_metai_match,
+ .str_lwr = efi_str_lwr,
+ .str_upr = efi_str_upr,
+ .fat_to_str = efi_fat_to_str,
+ .str_to_fat = efi_str_to_fat,
+ .supported_languages = "en",
+};
* converted to utf16?
*/
-#define MAX_VAR_NAME 31
-#define MAX_NATIVE_VAR_NAME \
- (strlen("efi_xxxxxxxx-xxxx-xxxx-xxxxxxxxxxxxxxxx_") + \
- (MAX_VAR_NAME * MAX_UTF8_PER_UTF16))
+#define PREFIX_LEN (strlen("efi_xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx_"))
static int hex(int ch)
{
return hexstr;
}
-static efi_status_t efi_to_native(char *native, u16 *variable_name,
+static efi_status_t efi_to_native(char **native, const u16 *variable_name,
efi_guid_t *vendor)
{
size_t len;
+ char *pos;
- len = utf16_strlen((u16 *)variable_name);
- if (len >= MAX_VAR_NAME)
- return EFI_DEVICE_ERROR;
+ len = PREFIX_LEN + utf16_utf8_strlen(variable_name) + 1;
+ *native = malloc(len);
+ if (!*native)
+ return EFI_OUT_OF_RESOURCES;
- native += sprintf(native, "efi_%pUl_", vendor);
- native = (char *)utf16_to_utf8((u8 *)native, (u16 *)variable_name, len);
- *native = '\0';
+ pos = *native;
+ pos += sprintf(pos, "efi_%pUl_", vendor);
+ utf16_utf8_strcpy(&pos, variable_name);
return EFI_SUCCESS;
}
u32 *attributes, efi_uintn_t *data_size,
void *data)
{
- char native_name[MAX_NATIVE_VAR_NAME + 1];
+ char *native_name;
efi_status_t ret;
unsigned long in_size;
const char *val, *s;
if (!variable_name || !vendor || !data_size)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- ret = efi_to_native(native_name, variable_name, vendor);
+ ret = efi_to_native(&native_name, variable_name, vendor);
if (ret)
return EFI_EXIT(ret);
debug("%s: get '%s'\n", __func__, native_name);
val = env_get(native_name);
+ free(native_name);
if (!val)
return EFI_EXIT(EFI_NOT_FOUND);
u32 attributes, efi_uintn_t data_size,
void *data)
{
- char native_name[MAX_NATIVE_VAR_NAME + 1];
+ char *native_name = NULL, *val = NULL, *s;
efi_status_t ret = EFI_SUCCESS;
- char *val, *s;
u32 attr;
EFI_ENTRY("\"%ls\" %pUl %x %zu %p", variable_name, vendor, attributes,
data_size, data);
- if (!variable_name || !vendor)
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ if (!variable_name || !vendor) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
- ret = efi_to_native(native_name, variable_name, vendor);
+ ret = efi_to_native(&native_name, variable_name, vendor);
if (ret)
- return EFI_EXIT(ret);
+ goto out;
#define ACCESS_ATTR (EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_BOOTSERVICE_ACCESS)
if ((data_size == 0) || !(attributes & ACCESS_ATTR)) {
/* delete the variable: */
env_set(native_name, NULL);
- return EFI_EXIT(EFI_SUCCESS);
+ ret = EFI_SUCCESS;
+ goto out;
}
val = env_get(native_name);
if (val) {
parse_attr(val, &attr);
- if (attr & READ_ONLY)
- return EFI_EXIT(EFI_WRITE_PROTECTED);
+ if (attr & READ_ONLY) {
+ /* We should not free val */
+ val = NULL;
+ ret = EFI_WRITE_PROTECTED;
+ goto out;
+ }
}
val = malloc(2 * data_size + strlen("{ro,run,boot}(blob)") + 1);
if (env_set(native_name, val))
ret = EFI_DEVICE_ERROR;
+out:
+ free(native_name);
free(val);
return EFI_EXIT(ret);
config CMD_BOOTEFI_SELFTEST
bool "Allow booting an EFI efi_selftest"
- depends on CMD_BOOTEFI
+ depends on CMD_BOOTEFI && !SANDBOX
imply FAT
imply FAT_WRITE
help
efi_selftest_exitbootservices.o \
efi_selftest_fdt.o \
efi_selftest_gop.o \
+efi_selftest_loaded_image.o \
efi_selftest_manageprotocols.o \
efi_selftest_rtc.o \
efi_selftest_snp.o \
efi_selftest_textinput.o \
+efi_selftest_textinputex.o \
efi_selftest_textoutput.o \
efi_selftest_tpl.o \
+efi_selftest_unicode_collation.o \
efi_selftest_util.o \
efi_selftest_variables.o \
efi_selftest_watchdog.o
#include <vsprintf.h>
struct efi_simple_text_output_protocol *con_out;
-struct efi_simple_input_interface *con_in;
+struct efi_simple_text_input_protocol *con_in;
/*
* Print a MAC address to an u16 string
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_loaded_image
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This unit test checks the Loaded Image Protocol.
+ */
+
+#include <efi_selftest.h>
+
+static efi_guid_t loaded_image_protocol_guid =
+ EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2,
+ 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b);
+static struct efi_boot_services *boottime;
+efi_handle_t image_handle;
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ boottime = systable->boottime;
+ image_handle = img_handle;
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Verify that the loaded image protocol is installed on the image handle.
+ * Verify that the loaded image protocol points to the system table.
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_uintn_t i, protocol_buffer_count = 0;
+ efi_guid_t **protocol_buffer = NULL;
+ bool found = false;
+ struct efi_loaded_image *loaded_image_protocol;
+
+ /*
+ * Get the GUIDs of all protocols installed on the handle.
+ */
+ ret = boottime->protocols_per_handle(image_handle, &protocol_buffer,
+ &protocol_buffer_count);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("ProtocolsPerHandle failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!protocol_buffer_count | !protocol_buffer) {
+ efi_st_error("ProtocolsPerHandle returned no protocol\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("%u protocols installed on image handle\n",
+ (unsigned int)protocol_buffer_count);
+ for (i = 0; i < protocol_buffer_count; ++i) {
+ if (efi_st_memcmp(protocol_buffer[i],
+ &loaded_image_protocol_guid,
+ sizeof(efi_guid_t)))
+ found = true;
+ }
+ if (!found) {
+ efi_st_printf("LoadedImageProtocol not found\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(protocol_buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * Open the loaded image protocol.
+ */
+ ret = boottime->open_protocol(image_handle, &loaded_image_protocol_guid,
+ (void **)&loaded_image_protocol, NULL,
+ NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocol failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (loaded_image_protocol->revision !=
+ EFI_LOADED_IMAGE_PROTOCOL_REVISION) {
+ efi_st_printf("Incorrect revision\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!loaded_image_protocol->system_table ||
+ loaded_image_protocol->system_table->hdr.signature !=
+ EFI_SYSTEM_TABLE_SIGNATURE) {
+ efi_st_printf("System table reference missing\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(loadedimage) = {
+ .name = "loaded image",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
efi_st_error("LocateHandleBuffer failed to locate new handle\n");
return EFI_ST_FAILURE;
}
- boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0);
+ /* Release buffer */
+ ret = boottime->free_pool(buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
/*
* Test error handling in UninstallMultipleProtocols
efi_st_error("LocateHandleBuffer failed to locate new handle\n");
return EFI_ST_FAILURE;
}
+ /* Clear the buffer, we are reusing it it the next step. */
boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0);
/*
efi_st_error("LocateHandle failed to locate new handles\n");
return EFI_ST_FAILURE;
}
- boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0);
+ /* Release buffer */
+ ret = boottime->free_pool(buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
/*
* Test LocateProtocol
efi_st_error("Failed to get protocols per handle\n");
return EFI_ST_FAILURE;
}
+ /* Release buffer */
+ ret = boottime->free_pool(prot_buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
/*
* Uninstall remaining protocols
#include <efi_selftest.h>
-struct translate {
- u16 code;
- u16 *text;
-};
-
static struct efi_boot_services *boottime;
-static struct translate control_characters[] = {
- {0, L"Null"},
- {8, L"BS"},
- {9, L"TAB"},
- {10, L"LF"},
- {13, L"CR"},
- {0, NULL},
-};
-
-static u16 ch[] = L"' '";
-static u16 unknown[] = L"unknown";
-
-static struct translate scan_codes[] = {
- {0x00, L"Null"},
- {0x01, L"Up"},
- {0x02, L"Down"},
- {0x03, L"Right"},
- {0x04, L"Left"},
- {0x05, L"Home"},
- {0x06, L"End"},
- {0x07, L"Insert"},
- {0x08, L"Delete"},
- {0x09, L"Page Up"},
- {0x0a, L"Page Down"},
- {0x0b, L"FN 1"},
- {0x0c, L"FN 2"},
- {0x0d, L"FN 3"},
- {0x0e, L"FN 4"},
- {0x0f, L"FN 5"},
- {0x10, L"FN 6"},
- {0x11, L"FN 7"},
- {0x12, L"FN 8"},
- {0x13, L"FN 9"},
- {0x14, L"FN 10"},
- {0x15, L"FN 11"},
- {0x16, L"FN 12"},
- {0x17, L"Escape"},
- {0x68, L"FN 13"},
- {0x69, L"FN 14"},
- {0x6a, L"FN 15"},
- {0x6b, L"FN 16"},
- {0x6c, L"FN 17"},
- {0x6d, L"FN 18"},
- {0x6e, L"FN 19"},
- {0x6f, L"FN 20"},
- {0x70, L"FN 21"},
- {0x71, L"FN 22"},
- {0x72, L"FN 23"},
- {0x73, L"FN 24"},
- {0x7f, L"Mute"},
- {0x80, L"Volume Up"},
- {0x81, L"Volume Down"},
- {0x100, L"Brightness Up"},
- {0x101, L"Brightness Down"},
- {0x102, L"Suspend"},
- {0x103, L"Hibernate"},
- {0x104, L"Toggle Display"},
- {0x105, L"Recovery"},
- {0x106, L"Reject"},
- {0x0, NULL},
-};
-
-/*
- * Translate a unicode character to a string.
- *
- * @code unicode character
- * @return string
- */
-static u16 *translate_char(u16 code)
-{
- struct translate *tr;
-
- if (code >= ' ') {
- ch[1] = code;
- return ch;
- }
- for (tr = control_characters; tr->text; ++tr) {
- if (tr->code == code)
- return tr->text;
- }
- return unknown;
-}
-
-/*
- * Translate a scan code to a human readable string.
- *
- * @code unicode character
- * @return string
- */
-static u16 *translate_code(u16 code)
-{
- struct translate *tr;
-
- for (tr = scan_codes; tr->text; ++tr) {
- if (tr->code == code)
- return tr->text;
- }
- return unknown;
-}
-
/*
* Setup unit test.
*
{
struct efi_input_key input_key = {0};
efi_status_t ret;
+ efi_uintn_t index;
+
+ /* Drain the console input */
+ ret = con_in->reset(con_in, true);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Reset failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = con_in->read_key_stroke(con_in, &input_key);
+ if (ret != EFI_NOT_READY) {
+ efi_st_error("Empty buffer not reported\n");
+ return EFI_ST_FAILURE;
+ }
efi_st_printf("Waiting for your input\n");
efi_st_printf("To terminate type 'x'\n");
for (;;) {
/* Wait for next key */
- do {
- ret = con_in->read_key_stroke(con_in, &input_key);
- } while (ret == EFI_NOT_READY);
+ ret = boottime->wait_for_event(1, &con_in->wait_for_key,
+ &index);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("WaitForEvent failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = con_in->read_key_stroke(con_in, &input_key);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("ReadKeyStroke failed\n");
+ return EFI_ST_FAILURE;
+ }
/* Allow 5 minutes until time out */
boottime->set_watchdog_timer(300, 0, 0, NULL);
efi_st_printf("Unicode char %u (%ps), scan code %u (%ps)\n",
(unsigned int)input_key.unicode_char,
- translate_char(input_key.unicode_char),
+ efi_st_translate_char(input_key.unicode_char),
(unsigned int)input_key.scan_code,
- translate_code(input_key.scan_code));
+ efi_st_translate_code(input_key.scan_code));
switch (input_key.unicode_char) {
case 'x':
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_textinput
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * Provides a unit test for the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.
+ * The unicode character and the scan code are printed for text
+ * input. To run the test:
+ *
+ * setenv efi_selftest extended text input
+ * bootefi selftest
+ */
+
+#include <efi_selftest.h>
+
+static const efi_guid_t text_input_ex_protocol_guid =
+ EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID;
+
+static struct efi_simple_text_input_ex_protocol *con_in_ex;
+
+static struct efi_boot_services *boottime;
+
+static void *efi_key_notify_handle;
+static bool efi_running;
+
+/**
+ * efi_key_notify_function() - key notification function
+ *
+ * This function is called when the registered key is hit.
+ *
+ * @key_data: next key
+ * Return: status code
+ */
+static efi_status_t EFIAPI efi_key_notify_function
+ (struct efi_key_data *key_data)
+{
+ efi_running = false;
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+ struct efi_key_data key_data = {
+ .key = {
+ .scan_code = 0,
+ .unicode_char = 0x18
+ },
+ .key_state = {
+ .key_shift_state = EFI_SHIFT_STATE_VALID |
+ EFI_LEFT_CONTROL_PRESSED,
+ .key_toggle_state = EFI_TOGGLE_STATE_INVALID,
+ },
+ };
+
+ boottime = systable->boottime;
+
+ ret = boottime->locate_protocol(&text_input_ex_protocol_guid, NULL,
+ (void **)&con_in_ex);
+ if (ret != EFI_SUCCESS) {
+ con_in_ex = NULL;
+ efi_st_error
+ ("Extended text input protocol is not available.\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = con_in_ex->register_key_notify(con_in_ex, &key_data,
+ efi_key_notify_function,
+ &efi_key_notify_handle);
+ if (ret != EFI_SUCCESS) {
+ efi_key_notify_handle = NULL;
+ efi_st_error
+ ("Notify function could not be registered.\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_running = true;
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * Unregister notify function.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t ret;
+
+ ret = con_in_ex->unregister_key_notify
+ (con_in_ex, efi_key_notify_handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error
+ ("Notify function could not be registered.\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+/*
+ * Execute unit test.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ struct efi_key_data input_key = { {0, 0}, {0, 0} };
+ efi_status_t ret;
+ efi_uintn_t index;
+
+ if (!con_in_ex) {
+ efi_st_printf("Setup failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Drain the console input */
+ ret = con_in_ex->reset(con_in_ex, true);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Reset failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = con_in_ex->read_key_stroke_ex(con_in_ex, &input_key);
+ if (ret != EFI_NOT_READY) {
+ efi_st_error("Empty buffer not reported\n");
+ return EFI_ST_FAILURE;
+ }
+
+ efi_st_printf("Waiting for your input\n");
+ efi_st_printf("To terminate type 'CTRL+x'\n");
+
+ while (efi_running) {
+ /* Wait for next key */
+ ret = boottime->wait_for_event(1, &con_in_ex->wait_for_key_ex,
+ &index);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("WaitForEvent failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = con_in_ex->read_key_stroke_ex(con_in_ex, &input_key);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("ReadKeyStroke failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Allow 5 minutes until time out */
+ boottime->set_watchdog_timer(300, 0, 0, NULL);
+
+ efi_st_printf("Unicode char %u (%ps), scan code %u (",
+ (unsigned int)input_key.key.unicode_char,
+ efi_st_translate_char(input_key.key.unicode_char),
+ (unsigned int)input_key.key.scan_code);
+ if (input_key.key_state.key_shift_state &
+ EFI_SHIFT_STATE_VALID) {
+ if (input_key.key_state.key_shift_state &
+ (EFI_LEFT_SHIFT_PRESSED | EFI_RIGHT_SHIFT_PRESSED))
+ efi_st_printf("SHIFT+");
+ if (input_key.key_state.key_shift_state &
+ (EFI_LEFT_ALT_PRESSED | EFI_RIGHT_ALT_PRESSED))
+ efi_st_printf("ALT+");
+ if (input_key.key_state.key_shift_state &
+ (EFI_LEFT_CONTROL_PRESSED |
+ EFI_RIGHT_CONTROL_PRESSED))
+ efi_st_printf("CTRL+");
+ if (input_key.key_state.key_shift_state &
+ (EFI_LEFT_LOGO_PRESSED | EFI_RIGHT_LOGO_PRESSED))
+ efi_st_printf("META+");
+ if (input_key.key_state.key_shift_state ==
+ EFI_SHIFT_STATE_VALID)
+ efi_st_printf("+");
+ }
+
+ efi_st_printf("%ps)\n",
+ efi_st_translate_code(input_key.key.scan_code));
+
+ }
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(textinputex) = {
+ .name = "extended text input",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+ .on_request = true,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_unicode_collation
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * Test unicode collation protocol.
+ */
+
+#include <efi_selftest.h>
+
+static const efi_guid_t unicode_collation_protocol_guid =
+ EFI_UNICODE_COLLATION_PROTOCOL2_GUID;
+
+static struct efi_boot_services *boottime;
+
+static struct efi_unicode_collation_protocol *unicode_collation_protocol;
+
+/**
+ * setup() - setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * ReturnValue: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+
+ boottime = systable->boottime;
+
+ ret = boottime->locate_protocol(&unicode_collation_protocol_guid, NULL,
+ (void **)&unicode_collation_protocol);
+ if (ret != EFI_SUCCESS) {
+ unicode_collation_protocol = NULL;
+ efi_st_error("Unicode collation protocol is not available.\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+static int test_stri_coll(void)
+{
+ efi_intn_t ret;
+ u16 c1[] = L"first";
+ u16 c2[] = L"FIRST";
+ u16 c3[] = L"second";
+
+ ret = unicode_collation_protocol->stri_coll(unicode_collation_protocol,
+ c1, c2);
+ if (ret) {
+ efi_st_error(
+ "stri_coll(\"%ps\", \"%ps\") = %zu\n", c1, c2, ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->stri_coll(unicode_collation_protocol,
+ c1, c3);
+ if (ret >= 0) {
+ efi_st_error(
+ "stri_coll(\"%ps\", \"%ps\") = %zu\n", c1, c3, ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->stri_coll(unicode_collation_protocol,
+ c3, c1);
+ if (ret <= 0) {
+ efi_st_error(
+ "stri_coll(\"%ps\", \"%ps\") = %zu\n", c3, c1, ret);
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+static int test_metai_match(void)
+{
+ bool ret;
+ const u16 c[] = L"Das U-Boot";
+
+ ret = unicode_collation_protocol->metai_match(
+ unicode_collation_protocol, c, L"*");
+ if (!ret) {
+ efi_st_error("metai_match returned %u\n", ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->metai_match(
+ unicode_collation_protocol, c, L"Da[rstu] U-Boot");
+ if (!ret) {
+ efi_st_error("metai_match returned %u\n", ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->metai_match(
+ unicode_collation_protocol, c, L"Da[q-v] U-Boot");
+ if (!ret) {
+ efi_st_error("metai_match returned %u\n", ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->metai_match(
+ unicode_collation_protocol, c, L"Da? U-Boot");
+ if (!ret) {
+ efi_st_error("metai_match returned %u\n", ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->metai_match(
+ unicode_collation_protocol, c, L"D*Bo*t");
+ if (!ret) {
+ efi_st_error("metai_match returned %u\n", ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->metai_match(
+ unicode_collation_protocol, c, L"Da[xyz] U-Boot");
+ if (ret) {
+ efi_st_error("metai_match returned %u\n", ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->metai_match(
+ unicode_collation_protocol, c, L"Da[a-d] U-Boot");
+ if (ret) {
+ efi_st_error("metai_match returned %u\n", ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->metai_match(
+ unicode_collation_protocol, c, L"Da?? U-Boot");
+ if (ret) {
+ efi_st_error("metai_match returned %u\n", ret);
+ return EFI_ST_FAILURE;
+ }
+
+ ret = unicode_collation_protocol->metai_match(
+ unicode_collation_protocol, c, L"D*Bo*tt");
+ if (ret) {
+ efi_st_error("metai_match returned %u\n", ret);
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+static int test_str_lwr(void)
+{
+ u16 c[] = L"U-Boot";
+
+ unicode_collation_protocol->str_lwr(unicode_collation_protocol, c);
+ if (efi_st_strcmp_16_8(c, "u-boot")) {
+ efi_st_error("str_lwr returned \"%ps\"\n", c);
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+static int test_str_upr(void)
+{
+ u16 c[] = L"U-Boot";
+
+ unicode_collation_protocol->str_upr(unicode_collation_protocol, c);
+ if (efi_st_strcmp_16_8(c, "U-BOOT")) {
+ efi_st_error("str_lwr returned \"%ps\"\n", c);
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+static int test_fat_to_str(void)
+{
+ u16 str[16];
+
+ boottime->set_mem(str, sizeof(str), 0);
+ unicode_collation_protocol->fat_to_str(unicode_collation_protocol, 6,
+ "U-BOOT", str);
+ if (efi_st_strcmp_16_8(str, "U-BOOT")) {
+ efi_st_error("fat_to_str returned \"%ps\"\n", str);
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+static int test_str_to_fat(void)
+{
+ char fat[16];
+ bool ret;
+
+ boottime->set_mem(fat, sizeof(fat), 0);
+ ret = unicode_collation_protocol->str_to_fat(unicode_collation_protocol,
+ L"U -Boo.t", 6, fat);
+ if (ret || efi_st_strcmp_16_8(L"U-BOOT", fat)) {
+ efi_st_error("str_to_fat returned %u, \"%s\"\n", ret, fat);
+ return EFI_ST_FAILURE;
+ }
+
+ boottime->set_mem(fat, 16, 0);
+ ret = unicode_collation_protocol->str_to_fat(unicode_collation_protocol,
+ L"U\\Boot", 6, fat);
+ if (!ret || efi_st_strcmp_16_8(L"U_BOOT", fat)) {
+ efi_st_error("str_to_fat returned %u, \"%s\"\n", ret, fat);
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/**
+ * execute() - Execute unit test.
+ *
+ * ReturnValue: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ int ret;
+
+ if (!unicode_collation_protocol) {
+ efi_st_printf("Unicode collation protocol missing\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = test_stri_coll();
+ if (ret != EFI_ST_SUCCESS)
+ return ret;
+
+ ret = test_metai_match();
+ if (ret != EFI_ST_SUCCESS)
+ return ret;
+
+ ret = test_str_lwr();
+ if (ret != EFI_ST_SUCCESS)
+ return ret;
+
+ ret = test_str_upr();
+ if (ret != EFI_ST_SUCCESS)
+ return ret;
+
+ ret = test_fat_to_str();
+ if (ret != EFI_ST_SUCCESS)
+ return ret;
+
+ ret = test_str_to_fat();
+ if (ret != EFI_ST_SUCCESS)
+ return ret;
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(unicoll) = {
+ .name = "unicode collation",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .execute = execute,
+ .setup = setup,
+};
#include <efi_selftest.h>
+struct efi_st_translate {
+ u16 code;
+ u16 *text;
+};
+
+static struct efi_st_translate efi_st_control_characters[] = {
+ {0, L"Null"},
+ {8, L"BS"},
+ {9, L"TAB"},
+ {10, L"LF"},
+ {13, L"CR"},
+ {0, NULL},
+};
+
+static u16 efi_st_ch[] = L"' '";
+static u16 efi_st_unknown[] = L"unknown";
+
+static struct efi_st_translate efi_st_scan_codes[] = {
+ {0x00, L"Null"},
+ {0x01, L"Up"},
+ {0x02, L"Down"},
+ {0x03, L"Right"},
+ {0x04, L"Left"},
+ {0x05, L"Home"},
+ {0x06, L"End"},
+ {0x07, L"Insert"},
+ {0x08, L"Delete"},
+ {0x09, L"Page Up"},
+ {0x0a, L"Page Down"},
+ {0x0b, L"FN 1"},
+ {0x0c, L"FN 2"},
+ {0x0d, L"FN 3"},
+ {0x0e, L"FN 4"},
+ {0x0f, L"FN 5"},
+ {0x10, L"FN 6"},
+ {0x11, L"FN 7"},
+ {0x12, L"FN 8"},
+ {0x13, L"FN 9"},
+ {0x14, L"FN 10"},
+ {0x15, L"FN 11"},
+ {0x16, L"FN 12"},
+ {0x17, L"Escape"},
+ {0x68, L"FN 13"},
+ {0x69, L"FN 14"},
+ {0x6a, L"FN 15"},
+ {0x6b, L"FN 16"},
+ {0x6c, L"FN 17"},
+ {0x6d, L"FN 18"},
+ {0x6e, L"FN 19"},
+ {0x6f, L"FN 20"},
+ {0x70, L"FN 21"},
+ {0x71, L"FN 22"},
+ {0x72, L"FN 23"},
+ {0x73, L"FN 24"},
+ {0x7f, L"Mute"},
+ {0x80, L"Volume Up"},
+ {0x81, L"Volume Down"},
+ {0x100, L"Brightness Up"},
+ {0x101, L"Brightness Down"},
+ {0x102, L"Suspend"},
+ {0x103, L"Hibernate"},
+ {0x104, L"Toggle Display"},
+ {0x105, L"Recovery"},
+ {0x106, L"Reject"},
+ {0x0, NULL},
+};
+
+u16 *efi_st_translate_char(u16 code)
+{
+ struct efi_st_translate *tr;
+
+ if (code >= ' ') {
+ efi_st_ch[1] = code;
+ return efi_st_ch;
+ }
+ for (tr = efi_st_control_characters; tr->text; ++tr) {
+ if (tr->code == code)
+ return tr->text;
+ }
+ return efi_st_unknown;
+}
+
+u16 *efi_st_translate_code(u16 code)
+{
+ struct efi_st_translate *tr;
+
+ for (tr = efi_st_scan_codes; tr->text; ++tr) {
+ if (tr->code == code)
+ return tr->text;
+ }
+ return efi_st_unknown;
+}
+
int efi_st_memcmp(const void *buf1, const void *buf2, size_t length)
{
const u8 *pos1 = buf1;
#include <serial.h>
#include <asm/sections.h>
#include <linux/ctype.h>
+#include <linux/ioport.h>
#include <linux/lzo.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_NR_DRAM_BANKS)
-static int get_next_memory_node(const void *blob, int mem)
+static ofnode get_next_memory_node(ofnode mem)
{
do {
- mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
- "device_type", "memory", 7);
- } while (!fdtdec_get_is_enabled(blob, mem));
+ mem = ofnode_by_prop_value(mem, "device_type", "memory", 7);
+ } while (ofnode_valid(mem) && !ofnode_is_available(mem));
return mem;
}
int fdtdec_setup_memory_banksize(void)
{
- int bank, ret, mem, reg = 0;
- struct fdt_resource res;
+ int bank, reg = 0;
+ struct resource res;
+ ofnode mem;
- mem = get_next_memory_node(gd->fdt_blob, -1);
- if (mem < 0) {
- debug("%s: Missing /memory node\n", __func__);
- return -EINVAL;
- }
+ mem = get_next_memory_node(ofnode_null());
+ if (!ofnode_valid(mem))
+ goto missing_node;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
- if (ret == -FDT_ERR_NOTFOUND) {
+ while (ofnode_read_resource(mem, reg++, &res)) {
reg = 0;
- mem = get_next_memory_node(gd->fdt_blob, mem);
- if (mem == -FDT_ERR_NOTFOUND)
- break;
-
- ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
- if (ret == -FDT_ERR_NOTFOUND)
- break;
- }
- if (ret != 0) {
- return -EINVAL;
+ mem = get_next_memory_node(mem);
+ if (!ofnode_valid(mem)) {
+ if (bank)
+ return 0;
+ goto missing_node;
+ }
}
gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
}
return 0;
+
+missing_node:
+ debug("%s: Missing /memory node\n", __func__);
+ return -EINVAL;
}
#endif
return buf;
}
+/* U-Boot uses UTF-16 strings in the EFI context only. */
+#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
static char *string16(char *buf, char *end, u16 *s, int field_width,
int precision, int flags)
{
u16 *str = s ? s : L"<NULL>";
- int utf16_len = utf16_strnlen(str, precision);
- u8 utf8[utf16_len * MAX_UTF8_PER_UTF16];
- int utf8_len, i;
-
- utf8_len = utf16_to_utf8(utf8, str, utf16_len) - utf8;
+ ssize_t len = utf16_strnlen(str, precision);
if (!(flags & LEFT))
- while (utf8_len < field_width--)
+ for (; len < field_width; --field_width)
ADDCH(buf, ' ');
- for (i = 0; i < utf8_len; ++i)
- ADDCH(buf, utf8[i]);
- while (utf8_len < field_width--)
+ utf16_utf8_strncpy(&buf, str, len);
+ for (; len < field_width; --field_width)
ADDCH(buf, ' ');
return buf;
}
-#if defined(CONFIG_EFI_LOADER) && \
- !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
static char *device_path_string(char *buf, char *end, void *dp, int field_width,
int precision, int flags)
{
#endif
switch (*fmt) {
-#if defined(CONFIG_EFI_LOADER) && \
- !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+/* Device paths only exist in the EFI context. */
+#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
case 'D':
return device_path_string(buf, end, ptr, field_width,
precision, flags);
continue;
case 's':
- if (qualifier == 'l' && !IS_ENABLED(CONFIG_SPL_BUILD)) {
+/* U-Boot uses UTF-16 strings in the EFI context only. */
+#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
+ if (qualifier == 'l') {
str = string16(str, end, va_arg(args, u16 *),
field_width, precision, flags);
- } else {
+ } else
+#endif
+ {
str = string(str, end, va_arg(args, char *),
field_width, precision, flags);
}
squote := '
empty :=
space := $(empty) $(empty)
+pound := \#
###
# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
# Replace >$< with >$$< to preserve $ when reloading the .cmd file
# (needed for make)
-# Replace >#< with >\#< to avoid starting a comment in the .cmd file
+# Replace >#< with >$(pound)< to avoid starting a comment in the .cmd file
# (needed for make)
# Replace >'< with >'\''< to be able to enclose the whole string in '...'
# (needed for the shell)
-make-cmd = $(call escsq,$(subst \#,\\\#,$(subst $$,$$$$,$(cmd_$(1)))))
+make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1)))))
# Find any prerequisites that is newer than target or that does not exist.
# PHONY targets skipped in both cases.
# Modified for U-Boot
# Bring in any U-Boot-specific include at the end of the file
cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
- (cat $<; $(if $(u_boot_dtsi),echo '\#include "$(u_boot_dtsi)"')) > $(pre-tmp); \
+ (cat $<; $(if $(u_boot_dtsi),echo '$(pound)include "$(u_boot_dtsi)"')) > $(pre-tmp); \
$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \
$(DTC) -O dtb -o $@ -b 0 \
-i $(dir $<) $(DTC_FLAGS) \
CONFIG_DIALOG_POWER
CONFIG_DIMM_SLOTS_PER_CTLR
CONFIG_DIRECT_NOR_BOOT
-CONFIG_DISABLE_CONSOLE
CONFIG_DISCONTIGMEM
CONFIG_DISCOVER_PHY
CONFIG_DISPLAY_AER_xxxx
CONFIG_SYS_MFD
CONFIG_SYS_MHZ
CONFIG_SYS_MII_MODE
-CONFIG_SYS_MIPS_CACHE_MODE
CONFIG_SYS_MIPS_TIMER_FREQ
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
CONFIG_SYS_RTC_BUS_NUM
CONFIG_SYS_RTC_CNT
CONFIG_SYS_RTC_OSCILLATOR
-CONFIG_SYS_RTC_PL031_BASE
CONFIG_SYS_RTC_REG_BASE_ADDR
CONFIG_SYS_RTC_SETUP
CONFIG_SYS_RV3029_TCR
CONFIG_SYS_SCCR_USBMPHCM
CONFIG_SYS_SCR
CONFIG_SYS_SCRATCH_VA
-CONFIG_SYS_SCSI_MAXDEVICE
CONFIG_SYS_SCSI_MAX_DEVICE
CONFIG_SYS_SCSI_MAX_LUN
CONFIG_SYS_SCSI_MAX_SCSI_ID
CONFIG_SYS_XHCI_USB2_ADDR
CONFIG_SYS_XHCI_USB3_ADDR
CONFIG_SYS_XIMG_LEN
-CONFIG_SYS_XWAY_EBU_BOOTCFG
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_i2C_FSL
CONFIG_UTBIPAR_INIT_TBIPA
CONFIG_U_BOOT_HDR_ADDR
CONFIG_U_BOOT_HDR_SIZE
-CONFIG_U_QE
CONFIG_VAL
CONFIG_VAR_SIZE_SPL
CONFIG_VCT_NOR
return check_err(fdt_setprop(self._fdt, nodeoffset, prop_name,
val, len(val)), quiet)
- def delprop(self, nodeoffset, prop_name):
+ def delprop(self, nodeoffset, prop_name, quiet=()):
"""Delete a property from a node
Args:
nodeoffset: Node offset containing property to delete
prop_name: Name of property to delete
+ quiet: Errors to ignore (empty to raise on all errors)
+
+ Returns:
+ Error code, or 0 if OK
Raises:
FdtError if the property does not exist, or another error occurs
"""
- return check_err(fdt_delprop(self._fdt, nodeoffset, prop_name))
+ return check_err(fdt_delprop(self._fdt, nodeoffset, prop_name), quiet)
+
+ def add_subnode(self, parentoffset, name, quiet=()):
+ """Add a new subnode to a node
- def del_node(self, nodeoffset):
+ Args:
+ parentoffset: Parent offset to add the subnode to
+ name: Name of node to add
+
+ Returns:
+ offset of the node created, or negative error code on failure
+
+ Raises:
+ FdtError if there is not enough space, or another error occurs
+ """
+ return check_err(fdt_add_subnode(self._fdt, parentoffset, name), quiet)
+
+ def del_node(self, nodeoffset, quiet=()):
"""Delete a node
Args:
- nodeoffset: Node offset containing property to delete
+ nodeoffset: Offset of node to delete
+
+ Returns:
+ Error code, or 0 if OK
Raises:
- FdtError if the node does not exist, or another error occurs
+ FdtError if an error occurs
"""
- return check_err(fdt_del_node(self._fdt, nodeoffset))
+ return check_err(fdt_del_node(self._fdt, nodeoffset), quiet)
class Property(bytearray):
problems. But if you are having problems with udelay() and the like,
this is a good place to start.
+config UT_UNICODE
+ bool "Unit tests for Unicode functions"
+ depends on UNIT_TEST
+ default y
+ help
+ Enables the 'ut unicode' command which tests that the functions for
+ manipulating Unicode strings work correctly.
+
source "test/dm/Kconfig"
source "test/env/Kconfig"
source "test/overlay/Kconfig"
obj-$(CONFIG_SANDBOX) += compression.o
obj-$(CONFIG_SANDBOX) += print_ut.o
obj-$(CONFIG_UT_TIME) += time_ut.o
+obj-$(CONFIG_UT_UNICODE) += unicode_ut.o
obj-$(CONFIG_$(SPL_)LOG) += log/
+obj-$(CONFIG_UNIT_TEST) += lib/
#ifdef CONFIG_UT_TIME
U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""),
#endif
+#if CONFIG_IS_ENABLED(UT_UNICODE) && !defined(API_BUILD)
+ U_BOOT_CMD_MKENT(unicode, CONFIG_SYS_MAXARGS, 1, do_ut_unicode, "", ""),
+#endif
#ifdef CONFIG_SANDBOX
U_BOOT_CMD_MKENT(compression, CONFIG_SYS_MAXARGS, 1, do_ut_compression,
"", ""),
#ifdef CONFIG_SYS_LONGHELP
static char ut_help_text[] =
"all - execute all enabled tests\n"
+#ifdef CONFIG_SANDBOX
+ "ut compression - Test compressors and bootm decompression\n"
+#endif
#ifdef CONFIG_UT_DM
"ut dm [test-name]\n"
#endif
#ifdef CONFIG_UT_TIME
"ut time - Very basic test of time functions\n"
#endif
-#ifdef CONFIG_SANDBOX
- "ut compression - Test compressors and bootm decompression\n"
+#if defined(CONFIG_UT_UNICODE) && \
+ !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+ "ut unicode [test-name] - test Unicode functions\n"
#endif
;
-#endif
+#endif /* CONFIG_SYS_LONGHELP */
U_BOOT_CMD(
ut, CONFIG_SYS_MAXARGS, 1, do_ut,
obj-$(CONFIG_UT_DM) += core.o
ifneq ($(CONFIG_SANDBOX),)
obj-$(CONFIG_BLK) += blk.o
+obj-$(CONFIG_BOARD) += board.o
obj-$(CONFIG_CLK) += clk.o
obj-$(CONFIG_DM_ETH) += eth.o
+obj-$(CONFIG_FIRMWARE) += firmware.o
obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_I2C) += i2c.o
obj-$(CONFIG_LED) += led.o
obj-$(CONFIG_DM_MAILBOX) += mailbox.o
obj-$(CONFIG_DM_MMC) += mmc.o
obj-y += ofnode.o
+obj-$(CONFIG_OSD) += osd.o
obj-$(CONFIG_DM_PCI) += pci.o
obj-$(CONFIG_PHY) += phy.o
obj-$(CONFIG_POWER_DOMAIN) += power-domain.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <board.h>
+#include <test/ut.h>
+
+#include "../../drivers/board/sandbox.h"
+
+static int dm_test_board(struct unit_test_state *uts)
+{
+ struct udevice *board;
+ bool called_detect;
+ char str[64];
+ int i;
+
+ board_get(&board);
+ ut_assert(board);
+
+ board_get_bool(board, BOOL_CALLED_DETECT, &called_detect);
+ ut_assert(!called_detect);
+
+ board_detect(board);
+
+ board_get_bool(board, BOOL_CALLED_DETECT, &called_detect);
+ ut_assert(called_detect);
+
+ board_get_str(board, STR_VACATIONSPOT, sizeof(str), str);
+ ut_assertok(strcmp(str, "R'lyeh"));
+
+ board_get_int(board, INT_TEST1, &i);
+ ut_asserteq(0, i);
+
+ board_get_int(board, INT_TEST2, &i);
+ ut_asserteq(100, i);
+
+ board_get_str(board, STR_VACATIONSPOT, sizeof(str), str);
+ ut_assertok(strcmp(str, "Carcosa"));
+
+ board_get_int(board, INT_TEST1, &i);
+ ut_asserteq(1, i);
+
+ board_get_int(board, INT_TEST2, &i);
+ ut_asserteq(99, i);
+
+ board_get_str(board, STR_VACATIONSPOT, sizeof(str), str);
+ ut_assertok(strcmp(str, "Yuggoth"));
+
+ return 0;
+}
+
+DM_TEST(dm_test_board, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Base test of firmware probe */
+static int dm_test_firmware_probe(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_FIRMWARE,
+ "sandbox-firmware", &dev));
+ return 0;
+}
+DM_TEST(dm_test_firmware_probe, DM_TESTF_SCAN_FDT);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <display_options.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <test/ut.h>
+#include <video_osd.h>
+#include <asm/test.h>
+
+#include "../../drivers/video/sandbox_osd.h"
+
+const uint memsize = 2 * 10 * 10;
+
+static void split(u8 *mem, uint size, u8 *text, u8 *colors)
+{
+ int i;
+ u16 *p = (u16 *)mem;
+
+ for (i = 0; i < size; i++) {
+ colors[i] = p[i] % 0x100;
+ text[i] = p[i] / 0x100;
+ }
+}
+
+static void print_mem(u8 *mem, uint width, uint height)
+{
+ const uint memsize = 2 * 10 * 10;
+ u8 colors[memsize / 2];
+ u8 text[memsize / 2];
+ int i;
+
+ split(mem, memsize / 2, text, colors);
+
+ for (i = 0; i < width * height; i++) {
+ printf("%c", text[i]);
+ if (i > 0 && ((i + 1) % width) == 0)
+ printf("\n");
+ }
+
+ printf("\n");
+
+ for (i = 0; i < width * height; i++) {
+ printf("%c", colors[i]);
+ if (i > 0 && ((i + 1) % width) == 0)
+ printf("\n");
+ }
+}
+
+static int dm_test_osd_basics(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ u8 mem[memsize + 1];
+ u8 colors[memsize / 2];
+ u8 text[memsize / 2];
+ struct video_osd_info info;
+
+ ut_assertok(uclass_first_device_err(UCLASS_VIDEO_OSD, &dev));
+
+ video_osd_get_info(dev, &info);
+
+ ut_asserteq(10, info.width);
+ ut_asserteq(10, info.height);
+ ut_asserteq(1, info.major_version);
+ ut_asserteq(0, info.minor_version);
+
+ ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
+ split(mem, memsize / 2, text, colors);
+
+ ut_assertok(memcmp(text, " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " ", memsize / 2));
+
+ ut_assertok(memcmp(colors, "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk", memsize / 2));
+
+ print_mem(mem, 10, 10);
+
+ ut_assertok(video_osd_print(dev, 1, 1, COLOR_RED, "Blah"));
+
+ ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
+ split(mem, memsize / 2, text, colors);
+
+ ut_assertok(memcmp(text, " "
+ " Blah "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " "
+ " ", memsize / 2));
+
+ ut_assertok(memcmp(colors, "kkkkkkkkkk"
+ "krrrrkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk"
+ "kkkkkkkkkk", memsize / 2));
+
+ print_mem(mem, 10, 10);
+
+ return 0;
+}
+
+DM_TEST(dm_test_osd_basics, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_osd_extended(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ u8 mem[memsize + 1];
+ u8 colors[memsize / 2];
+ u8 text[memsize / 2];
+ struct video_osd_info info;
+ u16 val;
+
+ ut_assertok(uclass_first_device_err(UCLASS_VIDEO_OSD, &dev));
+
+ ut_assertok(video_osd_set_size(dev, 20, 5));
+
+ video_osd_get_info(dev, &info);
+
+ ut_asserteq(20, info.width);
+ ut_asserteq(5, info.height);
+ ut_asserteq(1, info.major_version);
+ ut_asserteq(0, info.minor_version);
+
+ ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
+ split(mem, memsize / 2, text, colors);
+
+ ut_assertok(memcmp(text, " "
+ " "
+ " "
+ " "
+ " ", memsize / 2));
+
+ ut_assertok(memcmp(colors, "kkkkkkkkkkkkkkkkkkkk"
+ "kkkkkkkkkkkkkkkkkkkk"
+ "kkkkkkkkkkkkkkkkkkkk"
+ "kkkkkkkkkkkkkkkkkkkk"
+ "kkkkkkkkkkkkkkkkkkkk", memsize / 2));
+
+ print_mem(mem, 20, 5);
+
+ /* Draw green border */
+ val = '-' * 0x100 + 'g';
+ ut_assertok(video_osd_set_mem(dev, 1, 0, (u8 *)&val, 2, 18));
+ ut_assertok(video_osd_set_mem(dev, 1, 4, (u8 *)&val, 2, 18));
+ ut_assertok(video_osd_print(dev, 0, 1, COLOR_GREEN, "|"));
+ ut_assertok(video_osd_print(dev, 0, 2, COLOR_GREEN, "|"));
+ ut_assertok(video_osd_print(dev, 0, 3, COLOR_GREEN, "|"));
+ ut_assertok(video_osd_print(dev, 19, 1, COLOR_GREEN, "|"));
+ ut_assertok(video_osd_print(dev, 19, 2, COLOR_GREEN, "|"));
+ ut_assertok(video_osd_print(dev, 19, 3, COLOR_GREEN, "|"));
+ ut_assertok(video_osd_print(dev, 0, 0, COLOR_GREEN, "+"));
+ ut_assertok(video_osd_print(dev, 19, 0, COLOR_GREEN, "+"));
+ ut_assertok(video_osd_print(dev, 19, 4, COLOR_GREEN, "+"));
+ ut_assertok(video_osd_print(dev, 0, 4, COLOR_GREEN, "+"));
+
+ /* Add menu caption and entries */
+ ut_assertok(video_osd_print(dev, 5, 0, COLOR_GREEN, " OSD menu "));
+ ut_assertok(video_osd_print(dev, 2, 1, COLOR_BLUE, " * Entry 1"));
+ ut_assertok(video_osd_print(dev, 2, 2, COLOR_BLUE, "(*) Entry 2"));
+ ut_assertok(video_osd_print(dev, 2, 3, COLOR_BLUE, " * Entry 3"));
+
+ ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
+ split(mem, memsize / 2, text, colors);
+
+ print_mem(mem, 20, 5);
+
+ ut_assertok(memcmp(text, "+---- OSD menu ----+"
+ "| * Entry 1 |"
+ "| (*) Entry 2 |"
+ "| * Entry 3 |"
+ "+------------------+", memsize / 2));
+
+ ut_assertok(memcmp(colors, "gggggggggggggggggggg"
+ "gkbbbbbbbbbbbkkkkkkg"
+ "gkbbbbbbbbbbbkkkkkkg"
+ "gkbbbbbbbbbbbkkkkkkg"
+ "gggggggggggggggggggg", memsize / 2));
+
+ return 0;
+}
+
+DM_TEST(dm_test_osd_extended, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <dm/util.h>
+#include <dm/lists.h>
+#include <dm/of_access.h>
#include <test/ut.h>
DECLARE_GLOBAL_DATA_PTR;
}
DM_TEST(dm_test_fdt_remap_addr_live,
DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_fdt_livetree_writing(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ ofnode node;
+
+ if (!of_live_active()) {
+ printf("Live tree not active; ignore test\n");
+ return 0;
+ }
+
+ /* Test enabling devices */
+
+ node = ofnode_path("/usb@2");
+
+ ut_assert(!of_device_is_available(ofnode_to_np(node)));
+ ofnode_set_enabled(node, true);
+ ut_assert(of_device_is_available(ofnode_to_np(node)));
+
+ device_bind_driver_to_node(dm_root(), "usb_sandbox", "usb@2", node,
+ &dev);
+ ut_assertok(uclass_find_device_by_seq(UCLASS_USB, 2, true, &dev));
+
+ /* Test string property setting */
+
+ ut_assert(device_is_compatible(dev, "sandbox,usb"));
+ ofnode_write_string(node, "compatible", "gdsys,super-usb");
+ ut_assert(device_is_compatible(dev, "gdsys,super-usb"));
+ ofnode_write_string(node, "compatible", "sandbox,usb");
+ ut_assert(device_is_compatible(dev, "sandbox,usb"));
+
+ /* Test setting generic properties */
+
+ /* Non-existent in DTB */
+ ut_asserteq(FDT_ADDR_T_NONE, dev_read_addr(dev));
+ /* reg = 0x42, size = 0x100 */
+ ut_assertok(ofnode_write_prop(node, "reg", 8,
+ "\x00\x00\x00\x42\x00\x00\x01\x00"));
+ ut_asserteq(0x42, dev_read_addr(dev));
+
+ /* Test disabling devices */
+
+ device_remove(dev, DM_REMOVE_NORMAL);
+ device_unbind(dev);
+
+ ut_assert(of_device_is_available(ofnode_to_np(node)));
+ ofnode_set_enabled(node, false);
+ ut_assert(!of_device_is_available(ofnode_to_np(node)));
+
+ return 0;
+}
+DM_TEST(dm_test_fdt_livetree_writing, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_fdt_disable_enable_by_path(struct unit_test_state *uts)
+{
+ ofnode node;
+
+ if (!of_live_active()) {
+ printf("Live tree not active; ignore test\n");
+ return 0;
+ }
+
+ node = ofnode_path("/usb@2");
+
+ /* Test enabling devices */
+
+ ut_assert(!of_device_is_available(ofnode_to_np(node)));
+ dev_enable_by_path("/usb@2");
+ ut_assert(of_device_is_available(ofnode_to_np(node)));
+
+ /* Test disabling devices */
+
+ ut_assert(of_device_is_available(ofnode_to_np(node)));
+ dev_disable_by_path("/usb@2");
+ ut_assert(!of_device_is_available(ofnode_to_np(node)));
+
+ return 0;
+}
+DM_TEST(dm_test_fdt_disable_enable_by_path, DM_TESTF_SCAN_PDATA |
+ DM_TESTF_SCAN_FDT);
# It currently tests the fs/sb and native commands for ext4 and fat partitions
# Expected results are as follows:
# EXT4 tests:
-# fs-test.sb.ext4.out: Summary: PASS: 24 FAIL: 0
-# fs-test.ext4.out: Summary: PASS: 24 FAIL: 0
-# fs-test.fs.ext4.out: Summary: PASS: 24 FAIL: 0
+# fs-test.sb.ext4 Summary: PASS: 24 FAIL: 0
+# fs-test.nonfs.ext4 Summary: PASS: 24 FAIL: 0
+# fs-test.fs.ext4 Summary: PASS: 24 FAIL: 0
# FAT16 tests:
-# fs-test.sb.fat16.out: Summary: PASS: 24 FAIL: 0
-# fs-test.fat16.out: Summary: PASS: 20 FAIL: 4
-# fs-test.fs.fat16.out: Summary: PASS: 20 FAIL: 4
+# fs-test.sb.fat16 Summary: PASS: 24 FAIL: 0
+# fs-test.nonfs.fat16 Summary: PASS: 24 FAIL: 0
+# fs-test.fs.fat16 Summary: PASS: 24 FAIL: 0
# FAT32 tests:
-# fs-test.sb.fat32.out: Summary: PASS: 24 FAIL: 0
-# fs-test.fat32.out: Summary: PASS: 20 FAIL: 4
-# fs-test.fs.fat32.out: Summary: PASS: 20 FAIL: 4
-# Total Summary: TOTAL PASS: 200 TOTAL FAIL: 16
+# fs-test.sb.fat32 Summary: PASS: 24 FAIL: 0
+# fs-test.nonfs.fat32 Summary: PASS: 24 FAIL: 0
+# fs-test.fs.fat32 Summary: PASS: 24 FAIL: 0
+# --------------------------------------------
+# Total Summary: TOTAL PASS: 216 TOTAL FAIL: 0
+# --------------------------------------------
# pre-requisite binaries list.
PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir"
"TC11: 1MB write to $3.w - content verified"
# Check lookup of 'dot' directory
- grep -A4 "Test Case 12 " "$1" | grep -q 'Unable to write file'
+ grep -A4 "Test Case 12 " "$1" | grep -q 'Unable to write'
pass_fail "TC12: 1MB write to . - write denied"
# Check directory traversal
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018
+# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+obj-y += hexdump.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <hexdump.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+static int lib_test_hex_to_bin(struct unit_test_state *uts)
+{
+ return 0;
+
+ ut_asserteq(0x0, hex_to_bin('0'));
+ ut_asserteq(0x1, hex_to_bin('1'));
+ ut_asserteq(0x2, hex_to_bin('2'));
+ ut_asserteq(0x3, hex_to_bin('3'));
+ ut_asserteq(0x4, hex_to_bin('4'));
+ ut_asserteq(0x5, hex_to_bin('5'));
+ ut_asserteq(0x6, hex_to_bin('6'));
+ ut_asserteq(0x7, hex_to_bin('7'));
+ ut_asserteq(0x8, hex_to_bin('8'));
+ ut_asserteq(0x9, hex_to_bin('9'));
+ ut_asserteq(0xa, hex_to_bin('a'));
+ ut_asserteq(0xb, hex_to_bin('b'));
+ ut_asserteq(0xc, hex_to_bin('c'));
+ ut_asserteq(0xd, hex_to_bin('d'));
+ ut_asserteq(0xe, hex_to_bin('e'));
+ ut_asserteq(0xf, hex_to_bin('f'));
+ ut_asserteq(-1, hex_to_bin('g'));
+}
+
+DM_TEST(lib_test_hex_to_bin, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int lib_test_hex2bin(struct unit_test_state *uts)
+{
+ u8 dst[4];
+
+ hex2bin(dst, "649421de", 4);
+ ut_asserteq_mem("\x64\x94\x21\xde", dst, 4);
+ hex2bin(dst, "aa2e7545", 4);
+ ut_asserteq_mem("\xaa\x2e\x75\x45", dst, 4);
+ hex2bin(dst, "75453bc5", 4);
+ ut_asserteq_mem("\x75\x45\x3b\xc5", dst, 4);
+ hex2bin(dst, "a16884c3", 4);
+ ut_asserteq_mem("\xa1\x68\x84\xc3", dst, 4);
+ hex2bin(dst, "156b2e5e", 4);
+ ut_asserteq_mem("\x15\x6b\x2e\x5e", dst, 4);
+ hex2bin(dst, "2e035fff", 4);
+ ut_asserteq_mem("\x2e\x03\x5f\xff", dst, 4);
+ hex2bin(dst, "0ffce99f", 4);
+ ut_asserteq_mem("\x0f\xfc\xe9\x9f", dst, 4);
+ hex2bin(dst, "d3999443", 4);
+ ut_asserteq_mem("\xd3\x99\x94\x43", dst, 4);
+ hex2bin(dst, "91dd87bc", 4);
+ ut_asserteq_mem("\x91\xdd\x87\xbc", dst, 4);
+ hex2bin(dst, "7fec8963", 4);
+ ut_asserteq_mem("\x7f\xec\x89\x63", dst, 4);
+
+ return 0;
+}
+
+DM_TEST(lib_test_hex2bin, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int lib_test_bin2hex(struct unit_test_state *uts)
+{
+ char dst[8 + 1] = "\0";
+
+ bin2hex(dst, "\x64\x94\x21\xde", 4);
+ ut_asserteq_str("649421de", dst);
+ bin2hex(dst, "\xaa\x2e\x75\x45", 4);
+ ut_asserteq_str("aa2e7545", dst);
+ bin2hex(dst, "\x75\x45\x3b\xc5", 4);
+ ut_asserteq_str("75453bc5", dst);
+ bin2hex(dst, "\xa1\x68\x84\xc3", 4);
+ ut_asserteq_str("a16884c3", dst);
+ bin2hex(dst, "\x15\x6b\x2e\x5e", 4);
+ ut_asserteq_str("156b2e5e", dst);
+ bin2hex(dst, "\x2e\x03\x5f\xff", 4);
+ ut_asserteq_str("2e035fff", dst);
+ bin2hex(dst, "\x0f\xfc\xe9\x9f", 4);
+ ut_asserteq_str("0ffce99f", dst);
+ bin2hex(dst, "\xd3\x99\x94\x43", 4);
+ ut_asserteq_str("d3999443", dst);
+ bin2hex(dst, "\x91\xdd\x87\xbc", 4);
+ ut_asserteq_str("91dd87bc", dst);
+ bin2hex(dst, "\x7f\xec\x89\x63", 4);
+ ut_asserteq_str("7fec8963", dst);
+
+ return 0;
+}
+
+DM_TEST(lib_test_bin2hex, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
#define DEBUG
#include <common.h>
-#if defined(CONFIG_EFI_LOADER) && \
- !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
#include <efi_api.h>
#endif
#include <display_options.h>
/* Test efi_loader specific printing */
static void efi_ut_print(void)
{
-#if defined(CONFIG_EFI_LOADER) && \
- !defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
+#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
char str[10];
u8 buf[sizeof(struct efi_device_path_sd_mmc_path) +
sizeof(struct efi_device_path)];
u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
m = u_boot_console.p.expect(['Summary: 0 failures', 'Press any key'])
if m != 0:
- raise Exception('Failures occured during the EFI selftest')
+ raise Exception('Failures occurred during the EFI selftest')
u_boot_console.run_command(cmd='', wait_for_echo=False, wait_for_prompt=False);
m = u_boot_console.p.expect(['resetting', 'U-Boot'])
if m != 0:
if m != 0:
raise Exception('Reset failed in \'watchdog reboot\' test')
u_boot_console.restart_uboot();
+
+@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
+def test_efi_selftest_text_input(u_boot_console):
+ """Test the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
+
+ :param u_boot_console: U-Boot console
+
+ This function calls the text input EFI selftest.
+ """
+ u_boot_console.run_command(cmd='setenv efi_selftest text input')
+ output = u_boot_console.run_command(cmd='bootefi selftest',
+ wait_for_prompt=False)
+ m = u_boot_console.p.expect(['To terminate type \'x\''])
+ if m != 0:
+ raise Exception('No prompt for \'text input\' test')
+ u_boot_console.drain_console()
+ u_boot_console.p.timeout = 500
+ # EOT
+ u_boot_console.run_command(cmd=chr(4), wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 4 \(unknown\), scan code 0 \(Null\)'])
+ if m != 0:
+ raise Exception('EOT failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # BS
+ u_boot_console.run_command(cmd=chr(8), wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 8 \(BS\), scan code 0 \(Null\)'])
+ if m != 0:
+ raise Exception('BS failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # TAB
+ u_boot_console.run_command(cmd=chr(9), wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 9 \(TAB\), scan code 0 \(Null\)'])
+ if m != 0:
+ raise Exception('BS failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # a
+ u_boot_console.run_command(cmd='a', wait_for_echo=False, send_nl=False,
+ wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 97 \(\'a\'\), scan code 0 \(Null\)'])
+ if m != 0:
+ raise Exception('\'a\' failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # UP escape sequence
+ u_boot_console.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 0 \(Null\), scan code 1 \(Up\)'])
+ if m != 0:
+ raise Exception('UP failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # Euro sign
+ u_boot_console.run_command(cmd='\xe2\x82\xac', wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(['Unicode char 8364 \(\''])
+ if m != 0:
+ raise Exception('Euro sign failed in \'text input\' test')
+ u_boot_console.drain_console()
+ u_boot_console.run_command(cmd='x', wait_for_echo=False, send_nl=False,
+ wait_for_prompt=False)
+ m = u_boot_console.p.expect(['Summary: 0 failures', 'Press any key'])
+ if m != 0:
+ raise Exception('Failures occurred during the EFI selftest')
+ u_boot_console.restart_uboot();
+
+@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
+def test_efi_selftest_text_input_ex(u_boot_console):
+ """Test the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL
+
+ :param u_boot_console: U-Boot console
+
+ This function calls the extended text input EFI selftest.
+ """
+ u_boot_console.run_command(cmd='setenv efi_selftest extended text input')
+ output = u_boot_console.run_command(cmd='bootefi selftest',
+ wait_for_prompt=False)
+ m = u_boot_console.p.expect(['To terminate type \'CTRL\+x\''])
+ if m != 0:
+ raise Exception('No prompt for \'text input\' test')
+ u_boot_console.drain_console()
+ u_boot_console.p.timeout = 500
+ # EOT
+ u_boot_console.run_command(cmd=chr(4), wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 4 \(unknown\), scan code 0 \(CTRL\+Null\)'])
+ if m != 0:
+ raise Exception('EOT failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # BS
+ u_boot_console.run_command(cmd=chr(8), wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 8 \(BS\), scan code 0 \(\+Null\)'])
+ if m != 0:
+ raise Exception('BS failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # TAB
+ u_boot_console.run_command(cmd=chr(9), wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 9 \(TAB\), scan code 0 \(\+Null\)'])
+ if m != 0:
+ raise Exception('TAB failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # a
+ u_boot_console.run_command(cmd='a', wait_for_echo=False, send_nl=False,
+ wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 97 \(\'a\'\), scan code 0 \(Null\)'])
+ if m != 0:
+ raise Exception('\'a\' failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # UP escape sequence
+ u_boot_console.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 0 \(Null\), scan code 1 \(\+Up\)'])
+ if m != 0:
+ raise Exception('UP failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # Euro sign
+ u_boot_console.run_command(cmd='\xe2\x82\xac', wait_for_echo=False,
+ send_nl=False, wait_for_prompt=False)
+ m = u_boot_console.p.expect(['Unicode char 8364 \(\''])
+ if m != 0:
+ raise Exception('Euro sign failed in \'text input\' test')
+ u_boot_console.drain_console()
+ # SHIFT+ALT+FN 5
+ u_boot_console.run_command(cmd='\x1b\x5b\x31\x35\x3b\x34\x7e',
+ wait_for_echo=False, send_nl=False,
+ wait_for_prompt=False)
+ m = u_boot_console.p.expect(
+ ['Unicode char 0 \(Null\), scan code 15 \(SHIFT\+ALT\+FN 5\)'])
+ if m != 0:
+ raise Exception('SHIFT+ALT+FN 5 failed in \'text input\' test')
+ u_boot_console.drain_console()
+ u_boot_console.run_command(cmd=chr(24), wait_for_echo=False, send_nl=False,
+ wait_for_prompt=False)
+ m = u_boot_console.p.expect(['Summary: 0 failures', 'Press any key'])
+ if m != 0:
+ raise Exception('Failures occurred during the EFI selftest')
+ u_boot_console.restart_uboot();
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018, Linaro Limited
+# Author: Takahiro Akashi <takahiro.akashi@linaro.org>
+
+import os
+import os.path
+import pytest
+import re
+from subprocess import call, check_call, check_output, CalledProcessError
+from fstest_defs import *
+
+supported_fs_basic = ['fat16', 'fat32', 'ext4']
+supported_fs_ext = ['fat16', 'fat32']
+supported_fs_mkdir = ['fat16', 'fat32']
+supported_fs_unlink = ['fat16', 'fat32']
+
+#
+# Filesystem test specific setup
+#
+def pytest_addoption(parser):
+ parser.addoption('--fs-type', action='append', default=None,
+ help='Targeting Filesystem Types')
+
+def pytest_configure(config):
+ global supported_fs_basic
+ global supported_fs_ext
+ global supported_fs_mkdir
+ global supported_fs_unlink
+
+ def intersect(listA, listB):
+ return [x for x in listA if x in listB]
+
+ supported_fs = config.getoption('fs_type')
+ if supported_fs:
+ print("*** FS TYPE modified: %s" % supported_fs)
+ supported_fs_basic = intersect(supported_fs, supported_fs_basic)
+ supported_fs_ext = intersect(supported_fs, supported_fs_ext)
+ supported_fs_mkdir = intersect(supported_fs, supported_fs_mkdir)
+ supported_fs_unlink = intersect(supported_fs, supported_fs_unlink)
+
+def pytest_generate_tests(metafunc):
+ if 'fs_obj_basic' in metafunc.fixturenames:
+ metafunc.parametrize('fs_obj_basic', supported_fs_basic,
+ indirect=True, scope='module')
+ if 'fs_obj_ext' in metafunc.fixturenames:
+ metafunc.parametrize('fs_obj_ext', supported_fs_ext,
+ indirect=True, scope='module')
+ if 'fs_obj_mkdir' in metafunc.fixturenames:
+ metafunc.parametrize('fs_obj_mkdir', supported_fs_mkdir,
+ indirect=True, scope='module')
+ if 'fs_obj_unlink' in metafunc.fixturenames:
+ metafunc.parametrize('fs_obj_unlink', supported_fs_unlink,
+ indirect=True, scope='module')
+
+#
+# Helper functions
+#
+def fstype_to_ubname(fs_type):
+ if re.match('fat', fs_type):
+ return 'fat'
+ else:
+ return fs_type
+
+def check_ubconfig(config, fs_type):
+ if not config.buildconfig.get('config_cmd_%s' % fs_type, None):
+ pytest.skip('.config feature "CMD_%s" not enabled' % fs_type.upper())
+ if not config.buildconfig.get('config_%s_write' % fs_type, None):
+ pytest.skip('.config feature "%s_WRITE" not enabled'
+ % fs_type.upper())
+
+def mk_fs(config, fs_type, size, id):
+ fs_img = '%s.%s.img' % (id, fs_type)
+ fs_img = config.persistent_data_dir + '/' + fs_img
+
+ if fs_type == 'fat16':
+ mkfs_opt = '-F 16'
+ elif fs_type == 'fat32':
+ mkfs_opt = '-F 32'
+ else:
+ mkfs_opt = ''
+
+ if re.match('fat', fs_type):
+ fs_lnxtype = 'vfat'
+ else:
+ fs_lnxtype = fs_type
+
+ count = (size + 1048576 - 1) / 1048576
+
+ try:
+ check_call('rm -f %s' % fs_img, shell=True)
+ check_call('dd if=/dev/zero of=%s bs=1M count=%d'
+ % (fs_img, count), shell=True)
+ check_call('mkfs.%s %s %s'
+ % (fs_lnxtype, mkfs_opt, fs_img), shell=True)
+ return fs_img
+ except CalledProcessError:
+ call('rm -f %s' % fs_img, shell=True)
+ raise
+
+# from test/py/conftest.py
+def tool_is_in_path(tool):
+ for path in os.environ["PATH"].split(os.pathsep):
+ fn = os.path.join(path, tool)
+ if os.path.isfile(fn) and os.access(fn, os.X_OK):
+ return True
+ return False
+
+fuse_mounted = False
+
+def mount_fs(fs_type, device, mount_point):
+ global fuse_mounted
+
+ fuse_mounted = False
+ try:
+ if tool_is_in_path('guestmount'):
+ fuse_mounted = True
+ check_call('guestmount -a %s -m /dev/sda %s'
+ % (device, mount_point), shell=True)
+ else:
+ mount_opt = "loop,rw"
+ if re.match('fat', fs_type):
+ mount_opt += ",umask=0000"
+
+ check_call('sudo mount -o %s %s %s'
+ % (mount_opt, device, mount_point), shell=True)
+
+ # may not be effective for some file systems
+ check_call('sudo chmod a+rw %s' % mount_point, shell=True)
+ except CalledProcessError:
+ raise
+
+def umount_fs(fs_type, mount_point):
+ if fuse_mounted:
+ call('sync')
+ call('guestunmount %s' % mount_point, shell=True)
+ else:
+ call('sudo umount %s' % mount_point, shell=True)
+
+#
+# Fixture for basic fs test
+# derived from test/fs/fs-test.sh
+#
+# NOTE: yield_fixture was deprecated since pytest-3.0
+@pytest.yield_fixture()
+def fs_obj_basic(request, u_boot_config):
+ fs_type = request.param
+ fs_img = ''
+
+ fs_ubtype = fstype_to_ubname(fs_type)
+ check_ubconfig(u_boot_config, fs_ubtype)
+
+ mount_dir = u_boot_config.persistent_data_dir + '/mnt'
+
+ small_file = mount_dir + '/' + SMALL_FILE
+ big_file = mount_dir + '/' + BIG_FILE
+
+ try:
+
+ # 3GiB volume
+ fs_img = mk_fs(u_boot_config, fs_type, 0xc0000000, '3GB')
+
+ # Mount the image so we can populate it.
+ check_call('mkdir -p %s' % mount_dir, shell=True)
+ mount_fs(fs_type, fs_img, mount_dir)
+
+ # Create a subdirectory.
+ check_call('mkdir %s/SUBDIR' % mount_dir, shell=True)
+
+ # Create big file in this image.
+ # Note that we work only on the start 1MB, couple MBs in the 2GB range
+ # and the last 1 MB of the huge 2.5GB file.
+ # So, just put random values only in those areas.
+ check_call('dd if=/dev/urandom of=%s bs=1M count=1'
+ % big_file, shell=True)
+ check_call('dd if=/dev/urandom of=%s bs=1M count=2 seek=2047'
+ % big_file, shell=True)
+ check_call('dd if=/dev/urandom of=%s bs=1M count=1 seek=2499'
+ % big_file, shell=True)
+
+ # Create a small file in this image.
+ check_call('dd if=/dev/urandom of=%s bs=1M count=1'
+ % small_file, shell=True)
+
+ # Delete the small file copies which possibly are written as part of a
+ # previous test.
+ # check_call('rm -f "%s.w"' % MB1, shell=True)
+ # check_call('rm -f "%s.w2"' % MB1, shell=True)
+
+ # Generate the md5sums of reads that we will test against small file
+ out = check_output(
+ 'dd if=%s bs=1M skip=0 count=1 2> /dev/null | md5sum'
+ % small_file, shell=True)
+ md5val = [ out.split()[0] ]
+
+ # Generate the md5sums of reads that we will test against big file
+ # One from beginning of file.
+ out = check_output(
+ 'dd if=%s bs=1M skip=0 count=1 2> /dev/null | md5sum'
+ % big_file, shell=True)
+ md5val.append(out.split()[0])
+
+ # One from end of file.
+ out = check_output(
+ 'dd if=%s bs=1M skip=2499 count=1 2> /dev/null | md5sum'
+ % big_file, shell=True)
+ md5val.append(out.split()[0])
+
+ # One from the last 1MB chunk of 2GB
+ out = check_output(
+ 'dd if=%s bs=1M skip=2047 count=1 2> /dev/null | md5sum'
+ % big_file, shell=True)
+ md5val.append(out.split()[0])
+
+ # One from the start 1MB chunk from 2GB
+ out = check_output(
+ 'dd if=%s bs=1M skip=2048 count=1 2> /dev/null | md5sum'
+ % big_file, shell=True)
+ md5val.append(out.split()[0])
+
+ # One 1MB chunk crossing the 2GB boundary
+ out = check_output(
+ 'dd if=%s bs=512K skip=4095 count=2 2> /dev/null | md5sum'
+ % big_file, shell=True)
+ md5val.append(out.split()[0])
+
+ umount_fs(fs_type, mount_dir)
+ except CalledProcessError:
+ pytest.skip('Setup failed for filesystem: ' + fs_type)
+ return
+ else:
+ yield [fs_ubtype, fs_img, md5val]
+ finally:
+ umount_fs(fs_type, mount_dir)
+ call('rmdir %s' % mount_dir, shell=True)
+ if fs_img:
+ call('rm -f %s' % fs_img, shell=True)
+
+#
+# Fixture for extended fs test
+#
+# NOTE: yield_fixture was deprecated since pytest-3.0
+@pytest.yield_fixture()
+def fs_obj_ext(request, u_boot_config):
+ fs_type = request.param
+ fs_img = ''
+
+ fs_ubtype = fstype_to_ubname(fs_type)
+ check_ubconfig(u_boot_config, fs_ubtype)
+
+ mount_dir = u_boot_config.persistent_data_dir + '/mnt'
+
+ min_file = mount_dir + '/' + MIN_FILE
+ tmp_file = mount_dir + '/tmpfile'
+
+ try:
+
+ # 128MiB volume
+ fs_img = mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
+
+ # Mount the image so we can populate it.
+ check_call('mkdir -p %s' % mount_dir, shell=True)
+ mount_fs(fs_type, fs_img, mount_dir)
+
+ # Create a test directory
+ check_call('mkdir %s/dir1' % mount_dir, shell=True)
+
+ # Create a small file and calculate md5
+ check_call('dd if=/dev/urandom of=%s bs=1K count=20'
+ % min_file, shell=True)
+ out = check_output(
+ 'dd if=%s bs=1K 2> /dev/null | md5sum'
+ % min_file, shell=True)
+ md5val = [ out.split()[0] ]
+
+ # Calculate md5sum of Test Case 4
+ check_call('dd if=%s of=%s bs=1K count=20'
+ % (min_file, tmp_file), shell=True)
+ check_call('dd if=%s of=%s bs=1K seek=5 count=20'
+ % (min_file, tmp_file), shell=True)
+ out = check_output('dd if=%s bs=1K 2> /dev/null | md5sum'
+ % tmp_file, shell=True)
+ md5val.append(out.split()[0])
+
+ # Calculate md5sum of Test Case 5
+ check_call('dd if=%s of=%s bs=1K count=20'
+ % (min_file, tmp_file), shell=True)
+ check_call('dd if=%s of=%s bs=1K seek=5 count=5'
+ % (min_file, tmp_file), shell=True)
+ out = check_output('dd if=%s bs=1K 2> /dev/null | md5sum'
+ % tmp_file, shell=True)
+ md5val.append(out.split()[0])
+
+ # Calculate md5sum of Test Case 7
+ check_call('dd if=%s of=%s bs=1K count=20'
+ % (min_file, tmp_file), shell=True)
+ check_call('dd if=%s of=%s bs=1K seek=20 count=20'
+ % (min_file, tmp_file), shell=True)
+ out = check_output('dd if=%s bs=1K 2> /dev/null | md5sum'
+ % tmp_file, shell=True)
+ md5val.append(out.split()[0])
+
+ check_call('rm %s' % tmp_file, shell=True)
+ umount_fs(fs_type, mount_dir)
+ except CalledProcessError:
+ pytest.skip('Setup failed for filesystem: ' + fs_type)
+ return
+ else:
+ yield [fs_ubtype, fs_img, md5val]
+ finally:
+ umount_fs(fs_type, mount_dir)
+ call('rmdir %s' % mount_dir, shell=True)
+ if fs_img:
+ call('rm -f %s' % fs_img, shell=True)
+
+#
+# Fixture for mkdir test
+#
+# NOTE: yield_fixture was deprecated since pytest-3.0
+@pytest.yield_fixture()
+def fs_obj_mkdir(request, u_boot_config):
+ fs_type = request.param
+ fs_img = ''
+
+ fs_ubtype = fstype_to_ubname(fs_type)
+ check_ubconfig(u_boot_config, fs_ubtype)
+
+ try:
+ # 128MiB volume
+ fs_img = mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
+ except:
+ pytest.skip('Setup failed for filesystem: ' + fs_type)
+ else:
+ yield [fs_ubtype, fs_img]
+ finally:
+ if fs_img:
+ call('rm -f %s' % fs_img, shell=True)
+
+#
+# Fixture for unlink test
+#
+# NOTE: yield_fixture was deprecated since pytest-3.0
+@pytest.yield_fixture()
+def fs_obj_unlink(request, u_boot_config):
+ fs_type = request.param
+ fs_img = ''
+
+ fs_ubtype = fstype_to_ubname(fs_type)
+ check_ubconfig(u_boot_config, fs_ubtype)
+
+ mount_dir = u_boot_config.persistent_data_dir + '/mnt'
+
+ try:
+
+ # 128MiB volume
+ fs_img = mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
+
+ # Mount the image so we can populate it.
+ check_call('mkdir -p %s' % mount_dir, shell=True)
+ mount_fs(fs_type, fs_img, mount_dir)
+
+ # Test Case 1 & 3
+ check_call('mkdir %s/dir1' % mount_dir, shell=True)
+ check_call('dd if=/dev/urandom of=%s/dir1/file1 bs=1K count=1'
+ % mount_dir, shell=True)
+ check_call('dd if=/dev/urandom of=%s/dir1/file2 bs=1K count=1'
+ % mount_dir, shell=True)
+
+ # Test Case 2
+ check_call('mkdir %s/dir2' % mount_dir, shell=True)
+ for i in range(0, 20):
+ check_call('mkdir %s/dir2/0123456789abcdef%02x'
+ % (mount_dir, i), shell=True)
+
+ # Test Case 4
+ check_call('mkdir %s/dir4' % mount_dir, shell=True)
+
+ # Test Case 5, 6 & 7
+ check_call('mkdir %s/dir5' % mount_dir, shell=True)
+ check_call('dd if=/dev/urandom of=%s/dir5/file1 bs=1K count=1'
+ % mount_dir, shell=True)
+
+ umount_fs(fs_type, mount_dir)
+ except CalledProcessError:
+ pytest.skip('Setup failed for filesystem: ' + fs_type)
+ return
+ else:
+ yield [fs_ubtype, fs_img]
+ finally:
+ umount_fs(fs_type, mount_dir)
+ call('rmdir %s' % mount_dir, shell=True)
+ if fs_img:
+ call('rm -f %s' % fs_img, shell=True)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+# $MIN_FILE is the name of the 20KB file in the file system image
+MIN_FILE='testfile'
+
+# $SMALL_FILE is the name of the 1MB file in the file system image
+SMALL_FILE='1MB.file'
+
+# $BIG_FILE is the name of the 2.5GB file in the file system image
+BIG_FILE='2.5GB.file'
+
+ADDR=0x01000008
+LENGTH=0x00100000
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018, Linaro Limited
+# Author: Takahiro Akashi <takahiro.akashi@linaro.org>
+#
+# U-Boot File System:Basic Test
+
+"""
+This test verifies basic read/write operation on file system.
+"""
+
+import pytest
+import re
+from fstest_defs import *
+
+@pytest.mark.boardspec('sandbox')
+class TestFsBasic(object):
+ def test_fs1(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 1 - ls command, listing a root directory and invalid directory
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 1a - ls'):
+ # Test Case 1 - ls
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sls host 0:0' % fs_type])
+ assert(re.search('2621440000 *%s' % BIG_FILE, ''.join(output)))
+ assert(re.search('1048576 *%s' % SMALL_FILE, ''.join(output)))
+
+ with u_boot_console.log.section('Test Case 1b - ls (invalid dir)'):
+ # In addition, test with a nonexistent directory to see if we crash.
+ output = u_boot_console.run_command(
+ '%sls host 0:0 invalid_d' % fs_type)
+ if fs_type == 'ext4':
+ assert('Can not find directory' in output)
+ else:
+ assert('' == output)
+
+ def test_fs2(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 2 - size command for a small file
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 2a - size (small)'):
+ # 1MB is 0x0010 0000
+ # Test Case 2a - size of small file
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%ssize host 0:0 /%s' % (fs_type, SMALL_FILE),
+ 'printenv filesize',
+ 'setenv filesize'])
+ assert('filesize=100000' in ''.join(output))
+
+ with u_boot_console.log.section('Test Case 2b - size (/../<file>)'):
+ # Test Case 2b - size of small file via a path using '..'
+ output = u_boot_console.run_command_list([
+ '%ssize host 0:0 /SUBDIR/../%s' % (fs_type, SMALL_FILE),
+ 'printenv filesize',
+ 'setenv filesize'])
+ assert('filesize=100000' in ''.join(output))
+
+ def test_fs3(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 3 - size command for a large file
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 3 - size (large)'):
+ # 2.5GB (1024*1024*2500) is 0x9C40 0000
+ # Test Case 3 - size of big file
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%ssize host 0:0 /%s' % (fs_type, BIG_FILE),
+ 'printenv filesize',
+ 'setenv filesize'])
+ assert('filesize=9c400000' in ''.join(output))
+
+ def test_fs4(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 4 - load a small file, 1MB
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 4 - load (small)'):
+ # Test Case 4a - Read full 1MB of small file
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
+ 'printenv filesize'])
+ assert('filesize=100000' in ''.join(output))
+
+ # Test Case 4b - Read full 1MB of small file
+ output = u_boot_console.run_command_list([
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[0] in ''.join(output))
+
+ def test_fs5(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 5 - load, reading first 1MB of 3GB file
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 5 - load (first 1MB)'):
+ # Test Case 5a - First 1MB of big file
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s %x 0x0' % (fs_type, ADDR, BIG_FILE, LENGTH),
+ 'printenv filesize'])
+ assert('filesize=100000' in ''.join(output))
+
+ # Test Case 5b - First 1MB of big file
+ output = u_boot_console.run_command_list([
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[1] in ''.join(output))
+
+ def test_fs6(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 6 - load, reading last 1MB of 3GB file
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 6 - load (last 1MB)'):
+ # fails for ext as no offset support
+ # Test Case 6a - Last 1MB of big file
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s %x 0x9c300000'
+ % (fs_type, ADDR, BIG_FILE, LENGTH),
+ 'printenv filesize'])
+ assert('filesize=100000' in ''.join(output))
+
+ # Test Case 6b - Last 1MB of big file
+ output = u_boot_console.run_command_list([
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[2] in ''.join(output))
+
+ def test_fs7(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 7 - load, 1MB from the last 1MB in 2GB
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 7 - load (last 1MB in 2GB)'):
+ # fails for ext as no offset support
+ # Test Case 7a - One from the last 1MB chunk of 2GB
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s %x 0x7ff00000'
+ % (fs_type, ADDR, BIG_FILE, LENGTH),
+ 'printenv filesize'])
+ assert('filesize=100000' in ''.join(output))
+
+ # Test Case 7b - One from the last 1MB chunk of 2GB
+ output = u_boot_console.run_command_list([
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[3] in ''.join(output))
+
+ def test_fs8(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 8 - load, reading first 1MB in 2GB
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 8 - load (first 1MB in 2GB)'):
+ # fails for ext as no offset support
+ # Test Case 8a - One from the start 1MB chunk from 2GB
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s %x 0x80000000'
+ % (fs_type, ADDR, BIG_FILE, LENGTH),
+ 'printenv filesize'])
+ assert('filesize=100000' in ''.join(output))
+
+ # Test Case 8b - One from the start 1MB chunk from 2GB
+ output = u_boot_console.run_command_list([
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[4] in ''.join(output))
+
+ def test_fs9(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 9 - load, 1MB crossing 2GB boundary
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 9 - load (crossing 2GB boundary)'):
+ # fails for ext as no offset support
+ # Test Case 9a - One 1MB chunk crossing the 2GB boundary
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s %x 0x7ff80000'
+ % (fs_type, ADDR, BIG_FILE, LENGTH),
+ 'printenv filesize'])
+ assert('filesize=100000' in ''.join(output))
+
+ # Test Case 9b - One 1MB chunk crossing the 2GB boundary
+ output = u_boot_console.run_command_list([
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[5] in ''.join(output))
+
+ def test_fs10(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 10 - load, reading beyond file end'):
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 10 - load (beyond file end)'):
+ # Generic failure case
+ # Test Case 10 - 2MB chunk from the last 1MB of big file
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s 0x00200000 0x9c300000'
+ % (fs_type, ADDR, BIG_FILE),
+ 'printenv filesize',
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert('filesize=100000' in ''.join(output))
+
+ def test_fs11(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 11 - write'
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 11 - write'):
+ # Read 1MB from small file
+ # Write it back to test the writes
+ # Test Case 11a - Check that the write succeeded
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
+ '%swrite host 0:0 %x /%s.w $filesize'
+ % (fs_type, ADDR, SMALL_FILE)])
+ assert('1048576 bytes written' in ''.join(output))
+
+ # Test Case 11b - Check md5 of written to is same
+ # as the one read from
+ output = u_boot_console.run_command_list([
+ '%sload host 0:0 %x /%s.w' % (fs_type, ADDR, SMALL_FILE),
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[0] in ''.join(output))
+
+ def test_fs12(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 12 - write to "." directory
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 12 - write (".")'):
+ # Next test case checks writing a file whose dirent
+ # is the first in the block, which is always true for "."
+ # The write should fail, but the lookup should work
+ # Test Case 12 - Check directory traversal
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%swrite host 0:0 %x /. 0x10' % (fs_type, ADDR)])
+ assert('Unable to write' in ''.join(output))
+
+ def test_fs13(self, u_boot_console, fs_obj_basic):
+ """
+ Test Case 13 - write to a file with "/./<filename>"
+ """
+ fs_type,fs_img,md5val = fs_obj_basic
+ with u_boot_console.log.section('Test Case 13 - write ("./<file>")'):
+ # Read 1MB from small file
+ # Write it via "same directory", i.e. "." dirent
+ # Test Case 13a - Check directory traversal
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
+ '%swrite host 0:0 %x /./%s2 $filesize'
+ % (fs_type, ADDR, SMALL_FILE)])
+ assert('1048576 bytes written' in ''.join(output))
+
+ # Test Case 13b - Check md5 of written to is same
+ # as the one read from
+ output = u_boot_console.run_command_list([
+ 'mw.b %x 00 100' % ADDR,
+ '%sload host 0:0 %x /./%s2' % (fs_type, ADDR, SMALL_FILE),
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[0] in ''.join(output))
+
+ # Test Case 13c - Check md5 of written to is same
+ # as the one read from
+ output = u_boot_console.run_command_list([
+ 'mw.b %x 00 100' % ADDR,
+ '%sload host 0:0 %x /%s2' % (fs_type, ADDR, SMALL_FILE),
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[0] in ''.join(output))
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018, Linaro Limited
+# Author: Takahiro Akashi <takahiro.akashi@linaro.org>
+#
+# U-Boot File System:Exntented Test
+
+"""
+This test verifies extended write operation on file system.
+"""
+
+import pytest
+import re
+from fstest_defs import *
+
+@pytest.mark.boardspec('sandbox')
+class TestFsExt(object):
+ def test_fs_ext1(self, u_boot_console, fs_obj_ext):
+ """
+ Test Case 1 - write a file with absolute path
+ """
+ fs_type,fs_img,md5val = fs_obj_ext
+ with u_boot_console.log.section('Test Case 1 - write with abs path'):
+ # Test Case 1a - Check if command successfully returned
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
+ '%swrite host 0:0 %x /dir1/%s.w1 $filesize'
+ % (fs_type, ADDR, MIN_FILE)])
+ assert('20480 bytes written' in ''.join(output))
+
+ # Test Case 1b - Check md5 of file content
+ output = u_boot_console.run_command_list([
+ 'mw.b %x 00 100' % ADDR,
+ '%sload host 0:0 %x /dir1/%s.w1' % (fs_type, ADDR, MIN_FILE),
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[0] in ''.join(output))
+
+ def test_fs_ext2(self, u_boot_console, fs_obj_ext):
+ """
+ Test Case 2 - write to a file with relative path
+ """
+ fs_type,fs_img,md5val = fs_obj_ext
+ with u_boot_console.log.section('Test Case 2 - write with rel path'):
+ # Test Case 2a - Check if command successfully returned
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
+ '%swrite host 0:0 %x dir1/%s.w2 $filesize'
+ % (fs_type, ADDR, MIN_FILE)])
+ assert('20480 bytes written' in ''.join(output))
+
+ # Test Case 2b - Check md5 of file content
+ output = u_boot_console.run_command_list([
+ 'mw.b %x 00 100' % ADDR,
+ '%sload host 0:0 %x dir1/%s.w2' % (fs_type, ADDR, MIN_FILE),
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[0] in ''.join(output))
+
+ def test_fs_ext3(self, u_boot_console, fs_obj_ext):
+ """
+ Test Case 3 - write to a file with invalid path
+ """
+ fs_type,fs_img,md5val = fs_obj_ext
+ with u_boot_console.log.section('Test Case 3 - write with invalid path'):
+ # Test Case 3 - Check if command expectedly failed
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
+ '%swrite host 0:0 %x /dir1/none/%s.w3 $filesize'
+ % (fs_type, ADDR, MIN_FILE)])
+ assert('Unable to write "/dir1/none/' in ''.join(output))
+
+ def test_fs_ext4(self, u_boot_console, fs_obj_ext):
+ """
+ Test Case 4 - write at non-zero offset, enlarging file size
+ """
+ fs_type,fs_img,md5val = fs_obj_ext
+ with u_boot_console.log.section('Test Case 4 - write at non-zero offset, enlarging file size'):
+ # Test Case 4a - Check if command successfully returned
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
+ '%swrite host 0:0 %x /dir1/%s.w4 $filesize'
+ % (fs_type, ADDR, MIN_FILE)])
+ output = u_boot_console.run_command(
+ '%swrite host 0:0 %x /dir1/%s.w4 $filesize 0x1400'
+ % (fs_type, ADDR, MIN_FILE))
+ assert('20480 bytes written' in output)
+
+ # Test Case 4b - Check size of written file
+ output = u_boot_console.run_command_list([
+ '%ssize host 0:0 /dir1/%s.w4' % (fs_type, MIN_FILE),
+ 'printenv filesize',
+ 'setenv filesize'])
+ assert('filesize=6400' in ''.join(output))
+
+ # Test Case 4c - Check md5 of file content
+ output = u_boot_console.run_command_list([
+ 'mw.b %x 00 100' % ADDR,
+ '%sload host 0:0 %x /dir1/%s.w4' % (fs_type, ADDR, MIN_FILE),
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[1] in ''.join(output))
+
+ def test_fs_ext5(self, u_boot_console, fs_obj_ext):
+ """
+ Test Case 5 - write at non-zero offset, shrinking file size
+ """
+ fs_type,fs_img,md5val = fs_obj_ext
+ with u_boot_console.log.section('Test Case 5 - write at non-zero offset, shrinking file size'):
+ # Test Case 5a - Check if command successfully returned
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
+ '%swrite host 0:0 %x /dir1/%s.w5 $filesize'
+ % (fs_type, ADDR, MIN_FILE)])
+ output = u_boot_console.run_command(
+ '%swrite host 0:0 %x /dir1/%s.w5 0x1400 0x1400'
+ % (fs_type, ADDR, MIN_FILE))
+ assert('5120 bytes written' in output)
+
+ # Test Case 5b - Check size of written file
+ output = u_boot_console.run_command_list([
+ '%ssize host 0:0 /dir1/%s.w5' % (fs_type, MIN_FILE),
+ 'printenv filesize',
+ 'setenv filesize'])
+ assert('filesize=2800' in ''.join(output))
+
+ # Test Case 5c - Check md5 of file content
+ output = u_boot_console.run_command_list([
+ 'mw.b %x 00 100' % ADDR,
+ '%sload host 0:0 %x /dir1/%s.w5' % (fs_type, ADDR, MIN_FILE),
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[2] in ''.join(output))
+
+ def test_fs_ext6(self, u_boot_console, fs_obj_ext):
+ """
+ Test Case 6 - write nothing at the start, truncating to zero
+ """
+ fs_type,fs_img,md5val = fs_obj_ext
+ with u_boot_console.log.section('Test Case 6 - write nothing at the start, truncating to zero'):
+ # Test Case 6a - Check if command successfully returned
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
+ '%swrite host 0:0 %x /dir1/%s.w6 $filesize'
+ % (fs_type, ADDR, MIN_FILE)])
+ output = u_boot_console.run_command(
+ '%swrite host 0:0 %x /dir1/%s.w6 0 0'
+ % (fs_type, ADDR, MIN_FILE))
+ assert('0 bytes written' in output)
+
+ # Test Case 6b - Check size of written file
+ output = u_boot_console.run_command_list([
+ '%ssize host 0:0 /dir1/%s.w6' % (fs_type, MIN_FILE),
+ 'printenv filesize',
+ 'setenv filesize'])
+ assert('filesize=0' in ''.join(output))
+
+ def test_fs_ext7(self, u_boot_console, fs_obj_ext):
+ """
+ Test Case 7 - write at the end (append)
+ """
+ fs_type,fs_img,md5val = fs_obj_ext
+ with u_boot_console.log.section('Test Case 7 - write at the end (append)'):
+ # Test Case 7a - Check if command successfully returned
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
+ '%swrite host 0:0 %x /dir1/%s.w7 $filesize'
+ % (fs_type, ADDR, MIN_FILE)])
+ output = u_boot_console.run_command(
+ '%swrite host 0:0 %x /dir1/%s.w7 $filesize $filesize'
+ % (fs_type, ADDR, MIN_FILE))
+ assert('20480 bytes written' in output)
+
+ # Test Case 7b - Check size of written file
+ output = u_boot_console.run_command_list([
+ '%ssize host 0:0 /dir1/%s.w7' % (fs_type, MIN_FILE),
+ 'printenv filesize',
+ 'setenv filesize'])
+ assert('filesize=a000' in ''.join(output))
+
+ # Test Case 7c - Check md5 of file content
+ output = u_boot_console.run_command_list([
+ 'mw.b %x 00 100' % ADDR,
+ '%sload host 0:0 %x /dir1/%s.w7' % (fs_type, ADDR, MIN_FILE),
+ 'md5sum %x $filesize' % ADDR,
+ 'setenv filesize'])
+ assert(md5val[3] in ''.join(output))
+
+ def test_fs_ext8(self, u_boot_console, fs_obj_ext):
+ """
+ Test Case 8 - write at offset beyond the end of file
+ """
+ fs_type,fs_img,md5val = fs_obj_ext
+ with u_boot_console.log.section('Test Case 8 - write beyond the end'):
+ # Test Case 8a - Check if command expectedly failed
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
+ '%swrite host 0:0 %x /dir1/%s.w8 $filesize'
+ % (fs_type, ADDR, MIN_FILE)])
+ output = u_boot_console.run_command(
+ '%swrite host 0:0 %x /dir1/%s.w8 0x1400 %x'
+ % (fs_type, ADDR, MIN_FILE, 0x100000 + 0x1400))
+ assert('Unable to write "/dir1' in output)
+
+ def test_fs_ext9(self, u_boot_console, fs_obj_ext):
+ """
+ Test Case 9 - write to a non-existing file at non-zero offset
+ """
+ fs_type,fs_img,md5val = fs_obj_ext
+ with u_boot_console.log.section('Test Case 9 - write to non-existing file with non-zero offset'):
+ # Test Case 9a - Check if command expectedly failed
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
+ '%swrite host 0:0 %x /dir1/%s.w9 0x1400 0x1400'
+ % (fs_type, ADDR, MIN_FILE)])
+ assert('Unable to write "/dir1' in ''.join(output))
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018, Linaro Limited
+# Author: Takahiro Akashi <takahiro.akashi@linaro.org>
+#
+# U-Boot File System:mkdir Test
+
+"""
+This test verifies mkdir operation on file system.
+"""
+
+import pytest
+
+@pytest.mark.boardspec('sandbox')
+class TestMkdir(object):
+ def test_mkdir1(self, u_boot_console, fs_obj_mkdir):
+ """
+ Test Case 1 - create a directory under a root
+ """
+ fs_type,fs_img = fs_obj_mkdir
+ with u_boot_console.log.section('Test Case 1 - mkdir'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%smkdir host 0:0 dir1' % fs_type,
+ '%sls host 0:0 /' % fs_type])
+ assert('dir1/' in ''.join(output))
+
+ output = u_boot_console.run_command(
+ '%sls host 0:0 dir1' % fs_type)
+ assert('./' in output)
+ assert('../' in output)
+
+ def test_mkdir2(self, u_boot_console, fs_obj_mkdir):
+ """
+ Test Case 2 - create a directory under a sub-directory
+ """
+ fs_type,fs_img = fs_obj_mkdir
+ with u_boot_console.log.section('Test Case 2 - mkdir (sub-sub directory)'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%smkdir host 0:0 dir1/dir2' % fs_type,
+ '%sls host 0:0 dir1' % fs_type])
+ assert('dir2/' in ''.join(output))
+
+ output = u_boot_console.run_command(
+ '%sls host 0:0 dir1/dir2' % fs_type)
+ assert('./' in output)
+ assert('../' in output)
+
+ def test_mkdir3(self, u_boot_console, fs_obj_mkdir):
+ """
+ Test Case 3 - trying to create a directory with a non-existing
+ path should fail
+ """
+ fs_type,fs_img = fs_obj_mkdir
+ with u_boot_console.log.section('Test Case 3 - mkdir (non-existing path)'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%smkdir host 0:0 none/dir3' % fs_type])
+ assert('Unable to create a directory' in ''.join(output))
+
+ def test_mkdir4(self, u_boot_console, fs_obj_mkdir):
+ """
+ Test Case 4 - trying to create "." should fail
+ """
+ fs_type,fs_img = fs_obj_mkdir
+ with u_boot_console.log.section('Test Case 4 - mkdir (".")'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%smkdir host 0:0 .' % fs_type])
+ assert('Unable to create a directory' in ''.join(output))
+
+ def test_mkdir5(self, u_boot_console, fs_obj_mkdir):
+ """
+ Test Case 5 - trying to create ".." should fail
+ """
+ fs_type,fs_img = fs_obj_mkdir
+ with u_boot_console.log.section('Test Case 5 - mkdir ("..")'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%smkdir host 0:0 ..' % fs_type])
+ assert('Unable to create a directory' in ''.join(output))
+
+ def test_mkdir6(self, u_boot_console, fs_obj_mkdir):
+ """
+ 'Test Case 6 - create as many directories as amount of directory
+ entries goes beyond a cluster size)'
+ """
+ fs_type,fs_img = fs_obj_mkdir
+ with u_boot_console.log.section('Test Case 6 - mkdir (create many)'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%smkdir host 0:0 dir6' % fs_type,
+ '%sls host 0:0 /' % fs_type])
+ assert('dir6/' in ''.join(output))
+
+ for i in range(0, 20):
+ output = u_boot_console.run_command(
+ '%smkdir host 0:0 dir6/0123456789abcdef%02x'
+ % (fs_type, i))
+ output = u_boot_console.run_command('%sls host 0:0 dir6' % fs_type)
+ assert('0123456789abcdef00/' in output)
+ assert('0123456789abcdef13/' in output)
+
+ output = u_boot_console.run_command(
+ '%sls host 0:0 dir6/0123456789abcdef13/.' % fs_type)
+ assert('./' in output)
+ assert('../' in output)
+
+ output = u_boot_console.run_command(
+ '%sls host 0:0 dir6/0123456789abcdef13/..' % fs_type)
+ assert('0123456789abcdef00/' in output)
+ assert('0123456789abcdef13/' in output)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018, Linaro Limited
+# Author: Takahiro Akashi <takahiro.akashi@linaro.org>
+#
+# U-Boot File System:unlink Test
+
+"""
+This test verifies unlink operation (deleting a file or a directory)
+on file system.
+"""
+
+import pytest
+
+@pytest.mark.boardspec('sandbox')
+class TestUnlink(object):
+ def test_unlink1(self, u_boot_console, fs_obj_unlink):
+ """
+ Test Case 1 - delete a file
+ """
+ fs_type,fs_img = fs_obj_unlink
+ with u_boot_console.log.section('Test Case 1 - unlink (file)'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%srm host 0:0 dir1/file1' % fs_type,
+ '%sls host 0:0 dir1/file1' % fs_type])
+ assert('' == ''.join(output))
+
+ output = u_boot_console.run_command(
+ '%sls host 0:0 dir1/' % fs_type)
+ assert(not 'file1' in output)
+ assert('file2' in output)
+
+ def test_unlink2(self, u_boot_console, fs_obj_unlink):
+ """
+ Test Case 2 - delete many files
+ """
+ fs_type,fs_img = fs_obj_unlink
+ with u_boot_console.log.section('Test Case 2 - unlink (many)'):
+ output = u_boot_console.run_command('host bind 0 %s' % fs_img)
+
+ for i in range(0, 20):
+ output = u_boot_console.run_command_list([
+ '%srm host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i),
+ '%sls host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i)])
+ assert('' == ''.join(output))
+
+ output = u_boot_console.run_command(
+ '%sls host 0:0 dir2' % fs_type)
+ assert('0 file(s), 2 dir(s)' in output)
+
+ def test_unlink3(self, u_boot_console, fs_obj_unlink):
+ """
+ Test Case 3 - trying to delete a non-existing file should fail
+ """
+ fs_type,fs_img = fs_obj_unlink
+ with u_boot_console.log.section('Test Case 3 - unlink (non-existing)'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%srm host 0:0 dir1/nofile' % fs_type])
+ assert('nofile: doesn\'t exist' in ''.join(output))
+
+ def test_unlink4(self, u_boot_console, fs_obj_unlink):
+ """
+ Test Case 4 - delete an empty directory
+ """
+ fs_type,fs_img = fs_obj_unlink
+ with u_boot_console.log.section('Test Case 4 - unlink (directory)'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%srm host 0:0 dir4' % fs_type])
+ assert('' == ''.join(output))
+
+ output = u_boot_console.run_command(
+ '%sls host 0:0 /' % fs_type)
+ assert(not 'dir4' in output)
+
+ def test_unlink5(self, u_boot_console, fs_obj_unlink):
+ """
+ Test Case 5 - trying to deleting a non-empty directory ".."
+ should fail
+ """
+ fs_type,fs_img = fs_obj_unlink
+ with u_boot_console.log.section('Test Case 5 - unlink ("non-empty directory")'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%srm host 0:0 dir5' % fs_type])
+ assert('directory is not empty' in ''.join(output))
+
+ def test_unlink6(self, u_boot_console, fs_obj_unlink):
+ """
+ Test Case 6 - trying to deleting a "." should fail
+ """
+ fs_type,fs_img = fs_obj_unlink
+ with u_boot_console.log.section('Test Case 6 - unlink (".")'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%srm host 0:0 dir5/.' % fs_type])
+ assert('directory is not empty' in ''.join(output))
+
+ def test_unlink7(self, u_boot_console, fs_obj_unlink):
+ """
+ Test Case 7 - trying to deleting a ".." should fail
+ """
+ fs_type,fs_img = fs_obj_unlink
+ with u_boot_console.log.section('Test Case 7 - unlink ("..")'):
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ '%srm host 0:0 dir5/..' % fs_type])
+ assert('directory is not empty' in ''.join(output))
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Unit tests for Unicode functions
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#include <common.h>
+#include <charset.h>
+#include <command.h>
+#include <errno.h>
+#include <test/test.h>
+#include <test/suites.h>
+#include <test/ut.h>
+
+/* Linker list entry for a Unicode test */
+#define UNICODE_TEST(_name) UNIT_TEST(_name, 0, unicode_test)
+
+/* Constants c1-c4 and d1-d4 encode the same letters */
+
+/* Six characters translating to one utf-8 byte each. */
+static const u16 c1[] = {0x55, 0x2d, 0x42, 0x6f, 0x6f, 0x74, 0x00};
+/* One character translating to two utf-8 bytes */
+static const u16 c2[] = {0x6b, 0x61, 0x66, 0x62, 0xe1, 0x74, 0x75, 0x72, 0x00};
+/* Three characters translating to three utf-8 bytes each */
+static const u16 c3[] = {0x6f5c, 0x6c34, 0x8266, 0x00};
+/* Three letters translating to four utf-8 bytes each */
+static const u16 c4[] = {0xd801, 0xdc8d, 0xd801, 0xdc96, 0xd801, 0xdc87,
+ 0x0000};
+
+/* Illegal utf-16 strings */
+static const u16 i1[] = {0x69, 0x31, 0xdc87, 0x6c, 0x00};
+static const u16 i2[] = {0x69, 0x32, 0xd801, 0xd801, 0x6c, 0x00};
+static const u16 i3[] = {0x69, 0x33, 0xd801, 0x00};
+
+/* Six characters translating to one utf-16 word each. */
+static const char d1[] = {0x55, 0x2d, 0x42, 0x6f, 0x6f, 0x74, 0x00};
+/* Eight characters translating to one utf-16 word each */
+static const char d2[] = {0x6b, 0x61, 0x66, 0x62, 0xc3, 0xa1, 0x74, 0x75,
+ 0x72, 0x00};
+/* Three characters translating to one utf-16 word each */
+static const char d3[] = {0xe6, 0xbd, 0x9c, 0xe6, 0xb0, 0xb4, 0xe8, 0x89,
+ 0xa6, 0x00};
+/* Three letters translating to two utf-16 word each */
+static const char d4[] = {0xf0, 0x90, 0x92, 0x8d, 0xf0, 0x90, 0x92, 0x96,
+ 0xf0, 0x90, 0x92, 0x87, 0x00};
+
+/* Illegal utf-8 strings */
+static const char j1[] = {0x6a, 0x31, 0xa1, 0x6c, 0x00};
+static const char j2[] = {0x6a, 0x32, 0xc3, 0xc3, 0x6c, 0x00};
+static const char j3[] = {0x6a, 0x33, 0xf0, 0x90, 0xf0, 0x00};
+
+/* U-Boot uses UTF-16 strings in the EFI context only. */
+#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
+static int ut_string16(struct unit_test_state *uts)
+{
+ char buf[20];
+
+ /* Test length and precision */
+ memset(buf, 0xff, sizeof(buf));
+ sprintf(buf, "%8.6ls", c2);
+ ut_asserteq(' ', buf[1]);
+ ut_assert(!strncmp(&buf[2], d2, 7));
+ ut_assert(!buf[9]);
+
+ memset(buf, 0xff, sizeof(buf));
+ sprintf(buf, "%8.6ls", c4);
+ ut_asserteq(' ', buf[4]);
+ ut_assert(!strncmp(&buf[5], d4, 12));
+ ut_assert(!buf[17]);
+
+ memset(buf, 0xff, sizeof(buf));
+ sprintf(buf, "%-8.2ls", c4);
+ ut_asserteq(' ', buf[8]);
+ ut_assert(!strncmp(buf, d4, 8));
+ ut_assert(!buf[14]);
+
+ /* Test handling of illegal utf-16 sequences */
+ memset(buf, 0xff, sizeof(buf));
+ sprintf(buf, "%ls", i1);
+ ut_asserteq_str("i1?l", buf);
+
+ memset(buf, 0xff, sizeof(buf));
+ sprintf(buf, "%ls", i2);
+ ut_asserteq_str("i2?l", buf);
+
+ memset(buf, 0xff, sizeof(buf));
+ sprintf(buf, "%ls", i3);
+ ut_asserteq_str("i3?", buf);
+
+ return 0;
+}
+UNICODE_TEST(ut_string16);
+#endif
+
+static int ut_utf8_get(struct unit_test_state *uts)
+{
+ const char *s;
+ s32 code;
+ int i;
+
+ /* Check characters less than 0x800 */
+ s = d2;
+ for (i = 0; i < 8; ++i) {
+ code = utf8_get((const char **)&s);
+ /* c2 is the utf-8 encoding of d2 */
+ ut_asserteq(c2[i], code);
+ if (!code)
+ break;
+ }
+ ut_asserteq_ptr(s, d2 + 9)
+
+ /* Check characters less than 0x10000 */
+ s = d3;
+ for (i = 0; i < 4; ++i) {
+ code = utf8_get((const char **)&s);
+ /* c3 is the utf-8 encoding of d3 */
+ ut_asserteq(c3[i], code);
+ if (!code)
+ break;
+ }
+ ut_asserteq_ptr(s, d3 + 9)
+
+ /* Check character greater 0xffff */
+ s = d4;
+ code = utf8_get((const char **)&s);
+ ut_asserteq(0x0001048d, code);
+ ut_asserteq_ptr(s, d4 + 4);
+
+ return 0;
+}
+UNICODE_TEST(ut_utf8_get);
+
+static int ut_utf8_put(struct unit_test_state *uts)
+{
+ char buffer[8] = { 0, };
+ char *pos;
+
+ /* Commercial at, translates to one character */
+ pos = buffer;
+ ut_assert(!utf8_put('@', &pos))
+ ut_asserteq(1, pos - buffer);
+ ut_asserteq('@', buffer[0]);
+ ut_assert(!buffer[1]);
+
+ /* Latin letter G with acute, translates to two charactes */
+ pos = buffer;
+ ut_assert(!utf8_put(0x1f4, &pos));
+ ut_asserteq(2, pos - buffer);
+ ut_asserteq_str("\xc7\xb4", buffer);
+
+ /* Tagalog letter i, translates to three characters */
+ pos = buffer;
+ ut_assert(!utf8_put(0x1701, &pos));
+ ut_asserteq(3, pos - buffer);
+ ut_asserteq_str("\xe1\x9c\x81", buffer);
+
+ /* Hamster face, translates to four characters */
+ pos = buffer;
+ ut_assert(!utf8_put(0x1f439, &pos));
+ ut_asserteq(4, pos - buffer);
+ ut_asserteq_str("\xf0\x9f\x90\xb9", buffer);
+
+ /* Illegal code */
+ pos = buffer;
+ ut_asserteq(-1, utf8_put(0xd888, &pos));
+
+ return 0;
+}
+UNICODE_TEST(ut_utf8_put);
+
+static int ut_utf8_utf16_strlen(struct unit_test_state *uts)
+{
+ ut_asserteq(6, utf8_utf16_strlen(d1));
+ ut_asserteq(8, utf8_utf16_strlen(d2));
+ ut_asserteq(3, utf8_utf16_strlen(d3));
+ ut_asserteq(6, utf8_utf16_strlen(d4));
+
+ /* illegal utf-8 sequences */
+ ut_asserteq(4, utf8_utf16_strlen(j1));
+ ut_asserteq(4, utf8_utf16_strlen(j2));
+ ut_asserteq(3, utf8_utf16_strlen(j3));
+
+ return 0;
+}
+UNICODE_TEST(ut_utf8_utf16_strlen);
+
+static int ut_utf8_utf16_strnlen(struct unit_test_state *uts)
+{
+ ut_asserteq(3, utf8_utf16_strnlen(d1, 3));
+ ut_asserteq(6, utf8_utf16_strnlen(d1, 13));
+ ut_asserteq(6, utf8_utf16_strnlen(d2, 6));
+ ut_asserteq(2, utf8_utf16_strnlen(d3, 2));
+ ut_asserteq(4, utf8_utf16_strnlen(d4, 2));
+ ut_asserteq(6, utf8_utf16_strnlen(d4, 3));
+
+ /* illegal utf-8 sequences */
+ ut_asserteq(4, utf8_utf16_strnlen(j1, 16));
+ ut_asserteq(4, utf8_utf16_strnlen(j2, 16));
+ ut_asserteq(3, utf8_utf16_strnlen(j3, 16));
+
+ return 0;
+}
+UNICODE_TEST(ut_utf8_utf16_strnlen);
+
+/**
+ * ut_u16_strcmp() - Compare to u16 strings.
+ *
+ * @a1: first string
+ * @a2: second string
+ * @count: number of u16 to compare
+ * Return: -1 if a1 < a2, 0 if a1 == a2, 1 if a1 > a2
+ */
+static int ut_u16_strcmp(const u16 *a1, const u16 *a2, size_t count)
+{
+ for (; (*a1 || *a2) && count; ++a1, ++a2, --count) {
+ if (*a1 < *a2)
+ return -1;
+ if (*a1 > *a2)
+ return 1;
+ }
+ return 0;
+}
+
+static int ut_utf8_utf16_strcpy(struct unit_test_state *uts)
+{
+ u16 buf[16];
+ u16 *pos;
+
+ pos = buf;
+ utf8_utf16_strcpy(&pos, d1);
+ ut_asserteq(6, pos - buf);
+ ut_assert(!ut_u16_strcmp(buf, c1, SIZE_MAX));
+
+ pos = buf;
+ utf8_utf16_strcpy(&pos, d2);
+ ut_asserteq(8, pos - buf);
+ ut_assert(!ut_u16_strcmp(buf, c2, SIZE_MAX));
+
+ pos = buf;
+ utf8_utf16_strcpy(&pos, d3);
+ ut_asserteq(3, pos - buf);
+ ut_assert(!ut_u16_strcmp(buf, c3, SIZE_MAX));
+
+ pos = buf;
+ utf8_utf16_strcpy(&pos, d4);
+ ut_asserteq(6, pos - buf);
+ ut_assert(!ut_u16_strcmp(buf, c4, SIZE_MAX));
+
+ /* Illegal utf-8 strings */
+ pos = buf;
+ utf8_utf16_strcpy(&pos, j1);
+ ut_asserteq(4, pos - buf);
+ ut_assert(!ut_u16_strcmp(buf, L"j1?l", SIZE_MAX));
+
+ pos = buf;
+ utf8_utf16_strcpy(&pos, j2);
+ ut_asserteq(4, pos - buf);
+ ut_assert(!ut_u16_strcmp(buf, L"j2?l", SIZE_MAX));
+
+ pos = buf;
+ utf8_utf16_strcpy(&pos, j3);
+ ut_asserteq(3, pos - buf);
+ ut_assert(!ut_u16_strcmp(buf, L"j3?", SIZE_MAX));
+
+ return 0;
+}
+UNICODE_TEST(ut_utf8_utf16_strcpy);
+
+int ut_utf8_utf16_strncpy(struct unit_test_state *uts)
+{
+ u16 buf[16];
+ u16 *pos;
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf8_utf16_strncpy(&pos, d1, 4);
+ ut_asserteq(4, pos - buf);
+ ut_assert(!buf[4]);
+ ut_assert(!ut_u16_strcmp(buf, c1, 4));
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf8_utf16_strncpy(&pos, d2, 10);
+ ut_asserteq(8, pos - buf);
+ ut_assert(buf[4]);
+ ut_assert(!ut_u16_strcmp(buf, c2, SIZE_MAX));
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf8_utf16_strncpy(&pos, d3, 2);
+ ut_asserteq(2, pos - buf);
+ ut_assert(!buf[2]);
+ ut_assert(!ut_u16_strcmp(buf, c3, 2));
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf8_utf16_strncpy(&pos, d4, 2);
+ ut_asserteq(4, pos - buf);
+ ut_assert(!buf[4]);
+ ut_assert(!ut_u16_strcmp(buf, c4, 4));
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf8_utf16_strncpy(&pos, d4, 10);
+ ut_asserteq(6, pos - buf);
+ ut_assert(buf[5]);
+ ut_assert(!ut_u16_strcmp(buf, c4, SIZE_MAX));
+
+ return 0;
+}
+UNICODE_TEST(ut_utf8_utf16_strncpy);
+
+static int ut_utf16_get(struct unit_test_state *uts)
+{
+ const u16 *s;
+ s32 code;
+ int i;
+
+ /* Check characters less than 0x10000 */
+ s = c2;
+ for (i = 0; i < 9; ++i) {
+ code = utf16_get((const u16 **)&s);
+ ut_asserteq(c2[i], code);
+ if (!code)
+ break;
+ }
+ ut_asserteq_ptr(c2 + 8, s);
+
+ /* Check character greater 0xffff */
+ s = c4;
+ code = utf16_get((const u16 **)&s);
+ ut_asserteq(0x0001048d, code);
+ ut_asserteq_ptr(c4 + 2, s);
+
+ return 0;
+}
+UNICODE_TEST(ut_utf16_get);
+
+static int ut_utf16_put(struct unit_test_state *uts)
+{
+ u16 buffer[4] = { 0, };
+ u16 *pos;
+
+ /* Commercial at, translates to one word */
+ pos = buffer;
+ ut_assert(!utf16_put('@', &pos));
+ ut_asserteq(1, pos - buffer);
+ ut_asserteq((u16)'@', buffer[0]);
+ ut_assert(!buffer[1]);
+
+ /* Hamster face, translates to two words */
+ pos = buffer;
+ ut_assert(!utf16_put(0x1f439, &pos));
+ ut_asserteq(2, pos - buffer);
+ ut_asserteq((u16)0xd83d, buffer[0]);
+ ut_asserteq((u16)0xdc39, buffer[1]);
+ ut_assert(!buffer[2]);
+
+ /* Illegal code */
+ pos = buffer;
+ ut_asserteq(-1, utf16_put(0xd888, &pos));
+
+ return 0;
+}
+UNICODE_TEST(ut_utf16_put);
+
+int ut_utf16_strnlen(struct unit_test_state *uts)
+{
+ ut_asserteq(3, utf16_strnlen(c1, 3));
+ ut_asserteq(6, utf16_strnlen(c1, 13));
+ ut_asserteq(6, utf16_strnlen(c2, 6));
+ ut_asserteq(2, utf16_strnlen(c3, 2));
+ ut_asserteq(2, utf16_strnlen(c4, 2));
+ ut_asserteq(3, utf16_strnlen(c4, 3));
+
+ /* illegal utf-16 word sequences */
+ ut_asserteq(4, utf16_strnlen(i1, 16));
+ ut_asserteq(4, utf16_strnlen(i2, 16));
+ ut_asserteq(3, utf16_strnlen(i3, 16));
+
+ return 0;
+}
+UNICODE_TEST(ut_utf16_strnlen);
+
+int ut_utf16_utf8_strlen(struct unit_test_state *uts)
+{
+ ut_asserteq(6, utf16_utf8_strlen(c1));
+ ut_asserteq(9, utf16_utf8_strlen(c2));
+ ut_asserteq(9, utf16_utf8_strlen(c3));
+ ut_asserteq(12, utf16_utf8_strlen(c4));
+
+ /* illegal utf-16 word sequences */
+ ut_asserteq(4, utf16_utf8_strlen(i1));
+ ut_asserteq(4, utf16_utf8_strlen(i2));
+ ut_asserteq(3, utf16_utf8_strlen(i3));
+
+ return 0;
+}
+UNICODE_TEST(ut_utf16_utf8_strlen);
+
+int ut_utf16_utf8_strnlen(struct unit_test_state *uts)
+{
+ ut_asserteq(3, utf16_utf8_strnlen(c1, 3));
+ ut_asserteq(6, utf16_utf8_strnlen(c1, 13));
+ ut_asserteq(7, utf16_utf8_strnlen(c2, 6));
+ ut_asserteq(6, utf16_utf8_strnlen(c3, 2));
+ ut_asserteq(8, utf16_utf8_strnlen(c4, 2));
+ ut_asserteq(12, utf16_utf8_strnlen(c4, 3));
+ return 0;
+}
+UNICODE_TEST(ut_utf16_utf8_strnlen);
+
+int ut_utf16_utf8_strcpy(struct unit_test_state *uts)
+{
+ char buf[16];
+ char *pos;
+
+ pos = buf;
+ utf16_utf8_strcpy(&pos, c1);
+ ut_asserteq(6, pos - buf);
+ ut_asserteq_str(d1, buf);
+
+ pos = buf;
+ utf16_utf8_strcpy(&pos, c2);
+ ut_asserteq(9, pos - buf);
+ ut_asserteq_str(d2, buf);
+
+ pos = buf;
+ utf16_utf8_strcpy(&pos, c3);
+ ut_asserteq(9, pos - buf);
+ ut_asserteq_str(d3, buf);
+
+ pos = buf;
+ utf16_utf8_strcpy(&pos, c4);
+ ut_asserteq(12, pos - buf);
+ ut_asserteq_str(d4, buf);
+
+ /* Illegal utf-16 strings */
+ pos = buf;
+ utf16_utf8_strcpy(&pos, i1);
+ ut_asserteq(4, pos - buf);
+ ut_asserteq_str("i1?l", buf);
+
+ pos = buf;
+ utf16_utf8_strcpy(&pos, i2);
+ ut_asserteq(4, pos - buf);
+ ut_asserteq_str("i2?l", buf);
+
+ pos = buf;
+ utf16_utf8_strcpy(&pos, i3);
+ ut_asserteq(3, pos - buf);
+ ut_asserteq_str("i3?", buf);
+
+ return 0;
+}
+UNICODE_TEST(ut_utf16_utf8_strcpy);
+
+int ut_utf16_utf8_strncpy(struct unit_test_state *uts)
+{
+ char buf[16];
+ char *pos;
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf16_utf8_strncpy(&pos, c1, 4);
+ ut_asserteq(4, pos - buf);
+ ut_assert(!buf[4]);
+ ut_assert(!strncmp(buf, d1, 4));
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf16_utf8_strncpy(&pos, c2, 10);
+ ut_asserteq(9, pos - buf);
+ ut_assert(buf[4]);
+ ut_assert(!strncmp(buf, d2, SIZE_MAX));
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf16_utf8_strncpy(&pos, c3, 2);
+ ut_asserteq(6, pos - buf);
+ ut_assert(!buf[6]);
+ ut_assert(!strncmp(buf, d3, 6));
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf16_utf8_strncpy(&pos, c4, 2);
+ ut_asserteq(8, pos - buf);
+ ut_assert(!buf[8]);
+ ut_assert(!strncmp(buf, d4, 8));
+
+ pos = buf;
+ memset(buf, 0, sizeof(buf));
+ utf16_utf8_strncpy(&pos, c4, 10);
+ ut_asserteq(12, pos - buf);
+ ut_assert(buf[5]);
+ ut_assert(!strncmp(buf, d4, SIZE_MAX));
+
+ return 0;
+}
+UNICODE_TEST(ut_utf16_utf8_strncpy);
+
+int ut_utf_to_lower(struct unit_test_state *uts)
+{
+ ut_asserteq('@', utf_to_lower('@'));
+ ut_asserteq('a', utf_to_lower('A'));
+ ut_asserteq('z', utf_to_lower('Z'));
+ ut_asserteq('[', utf_to_lower('['));
+ ut_asserteq('m', utf_to_lower('m'));
+ /* Latin letter O with diaresis (umlaut) */
+ ut_asserteq(0x00f6, utf_to_lower(0x00d6));
+#ifdef CONFIG_EFI_UNICODE_CAPITALIZATION
+ /* Cyrillic letter I*/
+ ut_asserteq(0x0438, utf_to_lower(0x0418));
+#endif
+ return 0;
+}
+UNICODE_TEST(ut_utf_to_lower);
+
+int ut_utf_to_upper(struct unit_test_state *uts)
+{
+ ut_asserteq('`', utf_to_upper('`'));
+ ut_asserteq('A', utf_to_upper('a'));
+ ut_asserteq('Z', utf_to_upper('z'));
+ ut_asserteq('{', utf_to_upper('{'));
+ ut_asserteq('M', utf_to_upper('M'));
+ /* Latin letter O with diaresis (umlaut) */
+ ut_asserteq(0x00d6, utf_to_upper(0x00f6));
+#ifdef CONFIG_EFI_UNICODE_CAPITALIZATION
+ /* Cyrillic letter I */
+ ut_asserteq(0x0418, utf_to_upper(0x0438));
+#endif
+ return 0;
+}
+UNICODE_TEST(ut_utf_to_upper);
+
+int do_ut_unicode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct unit_test *tests = ll_entry_start(struct unit_test, unicode_test);
+ const int n_ents = ll_entry_count(struct unit_test, unicode_test);
+
+ return cmd_ut_category("Unicode", tests, n_ents, argc, argv);
+}
for each entry. This makes it easy to find out exactly where the entry
ended up in the image, regardless of parent sections, etc.
+expand-size:
+ Expand the size of this entry to fit available space. This space is only
+ limited by the size of the image/section and the position of the next
+ entry.
-The attributes supported for images are described below. Several are similar
-to those for entries.
+The attributes supported for images and sections are described below. Several
+are similar to those for entries.
size:
Sets the image size in bytes, for example 'size = <0x100000>' for a
8MB ROM, the offset of the first entry would be 0xfff80000 with
this option, instead of 0 without this option.
+skip-at-start:
+ This property specifies the entry offset of the first entry.
+
+ For PowerPC mpc85xx based CPU, CONFIG_SYS_TEXT_BASE is the entry
+ offset of the first entry. It can be 0xeff40000 or 0xfff40000 for
+ nor flash boot, 0x201000 for sd boot etc.
+
+ 'end-at-4gb' property is not applicable where CONFIG_SYS_TEXT_BASE +
+ Image size != 4gb.
Examples of the above options can be found in the tests. See the
tools/binman/test directory.
binman -E >tools/binman/README.entries
-Special properties
-------------------
+Hashing Entries
+---------------
+
+It is possible to ask binman to hash the contents of an entry and write that
+value back to the device-tree node. For example:
+
+ binman {
+ u-boot {
+ hash {
+ algo = "sha256";
+ };
+ };
+ };
-Some entries support special properties, documented here:
+Here, a new 'value' property will be written to the 'hash' node containing
+the hash of the 'u-boot' entry. Only SHA256 is supported at present. Whole
+sections can be hased if desired, by adding the 'hash' node to the section.
-u-boot-with-ucode-ptr:
- optional-ucode: boolean property to make microcode optional. If the
- u-boot.bin image does not include microcode, no error will
- be generated.
+The has value can be chcked at runtime by hashing the data actually read and
+comparing this has to the value in the device tree.
Order of image creation
of each entry.
+Compression
+-----------
+
+Binman support compression for 'blob' entries (those of type 'blob' and
+derivatives). To enable this for an entry, add a 'compression' property:
+
+ blob {
+ filename = "datafile";
+ compression = "lz4";
+ };
+
+The entry will then contain the compressed data, using the 'lz4' compression
+algorithm. Currently this is the only one that is supported.
+
+
+
Map files
---------
Properties / Entry arguments:
- filename: Filename of file to read into entry
+ - compress: Compression algorithm to use:
+ none: No compression
+ lz4: Use lz4 compression (via 'lz4' command-line utility)
This entry reads data from a file and places it in the entry. The
default filename is often specified specified by the subclass. See for
example the 'u_boot' entry which provides the filename 'u-boot.bin'.
+If compression is enabled, an extra 'uncomp-size' property is written to
+the node (if enabled with -u) which provides the uncompressed size of the
+data.
+
+
+
+Entry: blob-dtb: A blob that holds a device tree
+------------------------------------------------
+
+This is a blob containing a device tree. The contents of the blob are
+obtained from the list of available device-tree files, managed by the
+'state' module.
+
Entry: blob-named-by-arg: A blob entry which gets its filename property from its subclass
+Entry: files: Entry containing a set of files
+---------------------------------------------
+
+Properties / Entry arguments:
+ - pattern: Filename pattern to match the files to include
+ - compress: Compression algorithm to use:
+ none: No compression
+ lz4: Use lz4 compression (via 'lz4' command-line utility)
+
+This entry reads a number of files and places each in a separate sub-entry
+within this entry. To access these you need to enable device-tree updates
+at run-time so you can obtain the file positions.
+
+
+
Entry: fill: An entry which is filled to a particular byte value
----------------------------------------------------------------
+Entry: powerpc-mpc85xx-bootpg-resetvec: PowerPC mpc85xx bootpg + resetvec code for U-Boot
+-----------------------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot-br.bin (default 'u-boot-br.bin')
+
+This enrty is valid for PowerPC mpc85xx cpus. This entry holds
+'bootpg + resetvec' code for PowerPC mpc85xx CPUs which needs to be
+placed at offset 'RESET_VECTOR_ADDRESS - 0xffc'.
+
+
+
Entry: section: Entry that contains other entries
-------------------------------------------------
U-Boot. U-Boot needs this to know what devices are present and which drivers
to activate.
+Note: This is mostly an internal entry type, used by others. This allows
+binman to know which entries contain a device tree.
+
Entry: u-boot-dtb-with-ucode: A U-Boot device tree file, with the microcode removed
+Entry: u-boot-elf: U-Boot ELF image
+-----------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot (default 'u-boot')
+
+This is the U-Boot ELF image. It does not include a device tree but can be
+relocated to any address for execution.
+
+
+
Entry: u-boot-img: U-Boot legacy image
--------------------------------------
+Entry: u-boot-spl-elf: U-Boot SPL ELF image
+-------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of SPL u-boot (default 'spl/u-boot')
+
+This is the U-Boot SPL ELF image. It does not include a device tree but can
+be relocated to any address for execution.
+
+
+
Entry: u-boot-spl-nodtb: SPL binary without device tree appended
----------------------------------------------------------------
Entry: u-boot-spl-with-ucode-ptr: U-Boot SPL with embedded microcode pointer
----------------------------------------------------------------------------
+This is used when SPL must set up the microcode for U-Boot.
+
See Entry_u_boot_ucode for full details of the entries involved in this
process.
+Entry: u-boot-tpl-dtb-with-ucode: U-Boot TPL with embedded microcode pointer
+----------------------------------------------------------------------------
+
+This is used when TPL must set up the microcode for U-Boot.
+
+See Entry_u_boot_ucode for full details of the entries involved in this
+process.
+
+
+
+Entry: u-boot-tpl-with-ucode-ptr: U-Boot TPL with embedded microcode pointer
+----------------------------------------------------------------------------
+
+See Entry_u_boot_ucode for full details of the entries involved in this
+process.
+
+
+
Entry: u-boot-ucode: U-Boot microcode block
-------------------------------------------
Properties / Entry arguments:
- filename: Filename of u-boot-nodtb.dtb (default 'u-boot-nodtb.dtb')
+ - optional-ucode: boolean property to make microcode optional. If the
+ u-boot.bin image does not include microcode, no error will
+ be generated.
See Entry_u_boot_ucode for full details of the three entries involved in
this process. This entry updates U-Boot with the offset and size of the
- kernelkey: Name of the kernel key to use (inside keydir)
- preamble-flags: Value of the vboot preamble flags (typically 0)
-Chromium OS signs the read-write firmware and kernel, writing the signature
+Output files:
+ - input.<unique_name> - input file passed to futility
+ - vblock.<unique_name> - output file generated by futility (which is
+ used as the entry contents)
+
+Chromium OS signs the read-write firmware and kernel, writing the signature
in this block. This allows U-Boot to verify that the next firmware stage
and kernel are genuine.
+Entry: x86-start16-tpl: x86 16-bit start-up code for TPL
+--------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of tpl/u-boot-x86-16bit-tpl.bin (default
+ 'tpl/u-boot-x86-16bit-tpl.bin')
+
+x86 CPUs start up in 16-bit mode, even if they are 64-bit CPUs. This code
+must be placed at a particular address. This entry holds that code. It is
+typically placed at offset CONFIG_SYS_X86_START16. The code is responsible
+for changing to 32-bit mode and starting TPL, which in turn jumps to SPL.
+
+If TPL is not being used, the 'x86_start16_spl or 'x86_start16' entry types
+may be used instead.
+
+
+
from __future__ import print_function
from collections import OrderedDict
+from sets import Set
import sys
import fdt_util
import re
+import state
import tools
class Section(object):
Attributes:
_node: Node object that contains the section definition in device tree
+ _parent_section: Parent Section object which created this Section
_size: Section size in bytes, or None if not known yet
_align_size: Section size alignment, or None
_pad_before: Number of bytes before the first entry starts. This
section
_entries: OrderedDict() of entries
"""
- def __init__(self, name, node, test=False):
+ def __init__(self, name, parent_section, node, image, test=False):
global entry
global Entry
import entry
from entry import Entry
+ self._parent_section = parent_section
self._name = name
self._node = node
+ self._image = image
self._offset = 0
self._size = None
self._align_size = None
self._pad_after = 0
self._pad_byte = 0
self._sort = False
- self._skip_at_start = 0
+ self._skip_at_start = None
self._end_4gb = False
self._name_prefix = ''
self._entries = OrderedDict()
+ self._image_pos = None
if not test:
self._ReadNode()
self._ReadEntries()
self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0)
self._sort = fdt_util.GetBool(self._node, 'sort-by-offset')
self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb')
- if self._end_4gb and not self._size:
- self._Raise("Section size must be provided when using end-at-4gb")
+ self._skip_at_start = fdt_util.GetInt(self._node, 'skip-at-start')
if self._end_4gb:
- self._skip_at_start = 0x100000000 - self._size
+ if not self._size:
+ self._Raise("Section size must be provided when using end-at-4gb")
+ if self._skip_at_start is not None:
+ self._Raise("Provide either 'end-at-4gb' or 'skip-at-start'")
+ else:
+ self._skip_at_start = 0x100000000 - self._size
+ else:
+ if self._skip_at_start is None:
+ self._skip_at_start = 0
self._name_prefix = fdt_util.GetString(self._node, 'name-prefix')
def _ReadEntries(self):
for node in self._node.subnodes:
+ if node.name == 'hash':
+ continue
entry = Entry.Create(self, node)
entry.SetPrefix(self._name_prefix)
self._entries[node.name] = entry
+ def GetFdtSet(self):
+ """Get the set of device tree files used by this image"""
+ fdt_set = Set()
+ for entry in self._entries.values():
+ fdt_set.update(entry.GetFdtSet())
+ return fdt_set
+
def SetOffset(self, offset):
self._offset = offset
+ def ExpandEntries(self):
+ for entry in self._entries.values():
+ entry.ExpandEntries()
+
def AddMissingProperties(self):
"""Add new properties to the device tree as needed for this entry"""
for prop in ['offset', 'size', 'image-pos']:
if not prop in self._node.props:
- self._node.AddZeroProp(prop)
+ state.AddZeroProp(self._node, prop)
+ state.CheckAddHashProp(self._node)
for entry in self._entries.values():
entry.AddMissingProperties()
def SetCalculatedProperties(self):
- self._node.SetInt('offset', self._offset)
- self._node.SetInt('size', self._size)
- self._node.SetInt('image-pos', self._image_pos)
+ state.SetInt(self._node, 'offset', self._offset)
+ state.SetInt(self._node, 'size', self._size)
+ image_pos = self._image_pos
+ if self._parent_section:
+ image_pos -= self._parent_section.GetRootSkipAtStart()
+ state.SetInt(self._node, 'image-pos', image_pos)
for entry in self._entries.values():
entry.SetCalculatedProperties()
for entry in entries:
self._entries[entry._node.name] = entry
+ def _ExpandEntries(self):
+ """Expand any entries that are permitted to"""
+ exp_entry = None
+ for entry in self._entries.values():
+ if exp_entry:
+ exp_entry.ExpandToLimit(entry.offset)
+ exp_entry = None
+ if entry.expand_size:
+ exp_entry = entry
+ if exp_entry:
+ exp_entry.ExpandToLimit(self._size)
+
def CheckEntries(self):
- """Check that entries do not overlap or extend outside the section"""
+ """Check that entries do not overlap or extend outside the section
+
+ This also sorts entries, if needed and expands
+ """
if self._sort:
self._SortEntries()
+ self._ExpandEntries()
offset = 0
prev_name = 'None'
for entry in self._entries.values():
entry.CheckOffset()
if (entry.offset < self._skip_at_start or
- entry.offset >= self._skip_at_start + self._size):
+ entry.offset + entry.size > self._skip_at_start + self._size):
entry.Raise("Offset %#x (%d) is outside the section starting "
"at %#x (%d)" %
(entry.offset, entry.offset, self._skip_at_start,
source_entry.Raise("Cannot find node for phandle %d" % phandle)
for entry in self._entries.values():
if entry._node == node:
- if entry.data is None:
- return None
- return entry.data
+ return entry.GetData()
source_entry.Raise("Cannot find entry for node '%s'" % node.name)
+
+ def ExpandSize(self, size):
+ if size != self._size:
+ self._size = size
+
+ def GetRootSkipAtStart(self):
+ if self._parent_section:
+ return self._parent_section.GetRootSkipAtStart()
+ return self._skip_at_start
+
+ def GetImageSize(self):
+ return self._image._size
help='Enabling debugging (provides a full traceback on error)')
parser.add_option('-E', '--entry-docs', action='store_true',
help='Write out entry documentation (see README.entries)')
+ parser.add_option('--fake-dtb', action='store_true',
+ help='Use fake device tree contents (for testing only)')
+ parser.add_option('-i', '--image', type='string', action='append',
+ help='Image filename to build (if not specified, build all)')
parser.add_option('-I', '--indir', action='append',
help='Add a path to a directory to use for input files')
parser.add_option('-H', '--full-help', action='store_true',
from collections import OrderedDict
import os
-import re
import sys
import tools
import command
import elf
from image import Image
+import state
import tout
# List of images we plan to create
# Make this global so that it can be referenced from tests
images = OrderedDict()
-# Records the device-tree files known to binman, keyed by filename (e.g.
-# 'u-boot-spl.dtb')
-fdt_files = {}
-
-# Arguments passed to binman to provide arguments to entries
-entry_args = {}
-
-
def _ReadImageDesc(binman_node):
"""Read the image descriptions from the /binman node
return node
return None
-def GetFdt(fname):
- """Get the Fdt object for a particular device-tree filename
-
- Binman keeps track of at least one device-tree file called u-boot.dtb but
- can also have others (e.g. for SPL). This function looks up the given
- filename and returns the associated Fdt object.
+def WriteEntryDocs(modules, test_missing=None):
+ """Write out documentation for all entries
Args:
- fname: Filename to look up (e.g. 'u-boot.dtb').
-
- Returns:
- Fdt object associated with the filename
+ modules: List of Module objects to get docs for
+ test_missing: Used for testing only, to force an entry's documeentation
+ to show as missing even if it is present. Should be set to None in
+ normal use.
"""
- return fdt_files[fname]
-
-def GetFdtPath(fname):
- return fdt_files[fname]._fname
-
-def SetEntryArgs(args):
- global entry_args
-
- entry_args = {}
- if args:
- for arg in args:
- m = re.match('([^=]*)=(.*)', arg)
- if not m:
- raise ValueError("Invalid entry arguemnt '%s'" % arg)
- entry_args[m.group(1)] = m.group(2)
-
-def GetEntryArg(name):
- return entry_args.get(name)
-
-def WriteEntryDocs(modules, test_missing=None):
from entry import Entry
Entry.WriteDocs(modules, test_missing)
tout.Init(options.verbosity)
elf.debug = options.debug
+ state.use_fake_dtb = options.fake_dtb
try:
tools.SetInputDirs(options.indir)
tools.PrepareOutputDir(options.outdir, options.preserve)
- SetEntryArgs(options.entry_arg)
+ state.SetEntryArgs(options.entry_arg)
# Get the device tree ready by compiling it and copying the compiled
# output into a file in our output directly. Then scan it for use
# in binman.
dtb_fname = fdt_util.EnsureCompiled(dtb_fname)
- fname = tools.GetOutputFilename('u-boot-out.dtb')
- with open(dtb_fname) as infd:
- with open(fname, 'wb') as outfd:
- outfd.write(infd.read())
+ fname = tools.GetOutputFilename('u-boot.dtb.out')
+ tools.WriteFile(fname, tools.ReadFile(dtb_fname))
dtb = fdt.FdtScan(fname)
- # Note the file so that GetFdt() can find it
- fdt_files['u-boot.dtb'] = dtb
node = _FindBinmanNode(dtb)
if not node:
raise ValueError("Device tree '%s' does not have a 'binman' "
images = _ReadImageDesc(node)
+ if options.image:
+ skip = []
+ for name, image in images.iteritems():
+ if name not in options.image:
+ del images[name]
+ skip.append(name)
+ if skip:
+ print 'Skipping images: %s\n' % ', '.join(skip)
+
+ state.Prepare(images, dtb)
+
# Prepare the device tree by making sure that any missing
# properties are added (e.g. 'pos' and 'size'). The values of these
# may not be correct yet, but we add placeholders so that the
# without changing the device-tree size, thus ensuring that our
# entry offsets remain the same.
for image in images.values():
+ image.ExpandEntries()
if options.update_fdt:
image.AddMissingProperties()
image.ProcessFdt(dtb)
- dtb.Pack()
- dtb.Flush()
+ for dtb_item in state.GetFdts():
+ dtb_item.Sync(auto_resize=True)
+ dtb_item.Pack()
+ dtb_item.Flush()
for image in images.values():
# Perform all steps for this image, including checking and
# completed and written, but that does not seem important.
image.GetEntryContents()
image.GetEntryOffsets()
- image.PackEntries()
- image.CheckSize()
- image.CheckEntries()
+ try:
+ image.PackEntries()
+ image.CheckSize()
+ image.CheckEntries()
+ except Exception as e:
+ if options.map:
+ fname = image.WriteMap()
+ print "Wrote map file '%s' to show errors" % fname
+ raise
image.SetImagePos()
if options.update_fdt:
image.SetCalculatedProperties()
+ for dtb_item in state.GetFdts():
+ dtb_item.Sync()
image.ProcessEntryContents()
image.WriteSymbols()
image.BuildImage()
if options.map:
image.WriteMap()
- with open(fname, 'wb') as outfd:
- outfd.write(dtb.GetContents())
+
+ # Write the updated FDTs to our output files
+ for dtb_item in state.GetFdts():
+ tools.WriteFile(dtb_item._fname, dtb_item.GetContents())
+
finally:
tools.FinaliseOutputDir()
finally:
except:
have_importlib = False
-import fdt_util
-import control
import os
+from sets import Set
import sys
+
+import fdt_util
+import state
import tools
modules = {}
self.pad_after = 0
self.offset_unset = False
self.image_pos = None
+ self._expand_size = False
if read_node:
self.ReadNode()
"of two" % (self._node.path, self.align_size))
self.align_end = fdt_util.GetInt(self._node, 'align-end')
self.offset_unset = fdt_util.GetBool(self._node, 'offset-unset')
+ self.expand_size = fdt_util.GetBool(self._node, 'expand-size')
+
+ def GetDefaultFilename(self):
+ return None
+
+ def GetFdtSet(self):
+ """Get the set of device trees used by this entry
+
+ Returns:
+ Set containing the filename from this entry, if it is a .dtb, else
+ an empty set
+ """
+ fname = self.GetDefaultFilename()
+ # It would be better to use isinstance(self, Entry_blob_dtb) here but
+ # we cannot access Entry_blob_dtb
+ if fname and fname.endswith('.dtb'):
+ return Set([fname])
+ return Set()
+
+ def ExpandEntries(self):
+ pass
def AddMissingProperties(self):
"""Add new properties to the device tree as needed for this entry"""
for prop in ['offset', 'size', 'image-pos']:
if not prop in self._node.props:
- self._node.AddZeroProp(prop)
+ state.AddZeroProp(self._node, prop)
+ err = state.CheckAddHashProp(self._node)
+ if err:
+ self.Raise(err)
def SetCalculatedProperties(self):
"""Set the value of device-tree properties calculated by binman"""
- self._node.SetInt('offset', self.offset)
- self._node.SetInt('size', self.size)
- self._node.SetInt('image-pos', self.image_pos)
+ state.SetInt(self._node, 'offset', self.offset)
+ state.SetInt(self._node, 'size', self.size)
+ state.SetInt(self._node, 'image-pos',
+ self.image_pos - self.section.GetRootSkipAtStart())
+ state.CheckSetHashValue(self._node, self.GetData)
def ProcessFdt(self, fdt):
+ """Allow entries to adjust the device tree
+
+ Some entries need to adjust the device tree for their purposes. This
+ may involve adding or deleting properties.
+
+ Returns:
+ True if processing is complete
+ False if processing could not be completed due to a dependency.
+ This will cause the entry to be retried after others have been
+ called
+ """
return True
def SetPrefix(self, prefix):
"""
pass
+ @staticmethod
+ def GetStr(value):
+ if value is None:
+ return '<none> '
+ return '%08x' % value
+
@staticmethod
def WriteMapLine(fd, indent, name, offset, size, image_pos):
- print('%08x %s%08x %08x %s' % (image_pos, ' ' * indent, offset,
- size, name), file=fd)
+ print('%s %s%s %s %s' % (Entry.GetStr(image_pos), ' ' * indent,
+ Entry.GetStr(offset), Entry.GetStr(size),
+ name), file=fd)
def WriteMap(self, fd, indent):
"""Write a map of the entry to a .map file
Raises:
ValueError if the argument cannot be converted to in
"""
- value = control.GetEntryArg(name)
+ value = state.GetEntryArg(name)
if value is not None:
if datatype == int:
try:
if missing:
raise ValueError('Documentation is missing for modules: %s' %
', '.join(missing))
+
+ def GetUniqueName(self):
+ """Get a unique name for a node
+
+ Returns:
+ String containing a unique name for a node, consisting of the name
+ of all ancestors (starting from within the 'binman' node) separated
+ by a dot ('.'). This can be useful for generating unique filesnames
+ in the output directory.
+ """
+ name = self.name
+ node = self._node
+ while node.parent:
+ node = node.parent
+ if node.name == 'binman':
+ break
+ name = '%s.%s' % (node.name, name)
+ return name
+
+ def ExpandToLimit(self, limit):
+ """Expand an entry so that it ends at the given offset limit"""
+ if self.offset + self.size < limit:
+ self.size = limit - self.offset
+ # Request the contents again, since changing the size requires that
+ # the data grows. This should not fail, but check it to be sure.
+ if not self.ObtainContents():
+ self.Raise('Cannot obtain contents when expanding entry')
self.assertIn("Unknown entry type 'invalid-name' in node "
"'invalid-path'", str(e.exception))
+ def testUniqueName(self):
+ """Test Entry.GetUniqueName"""
+ import entry
+ Node = collections.namedtuple('Node', ['name', 'parent'])
+ base_node = Node('root', None)
+ base_entry = entry.Entry(None, None, base_node, read_node=False)
+ self.assertEqual('root', base_entry.GetUniqueName())
+ sub_node = Node('subnode', base_node)
+ sub_entry = entry.Entry(None, None, sub_node, read_node=False)
+ self.assertEqual('root.subnode', sub_entry.GetUniqueName())
+
+ def testGetDefaultFilename(self):
+ """Trivial test for this base class function"""
+ import entry
+ base_entry = entry.Entry(None, None, None, read_node=False)
+ self.assertIsNone(base_entry.GetDefaultFilename())
if __name__ == "__main__":
unittest.main()
'return-unknown-contents')
self.bad_update_contents = fdt_util.GetBool(self._node,
'bad-update-contents')
+ self.return_contents_once = fdt_util.GetBool(self._node,
+ 'return-contents-once')
# Set to True when the entry is ready to process the FDT.
self.process_fdt_ready = False
EntryArg('test-existing-prop', str)], self.require_args)
if self.force_bad_datatype:
self.GetEntryArgsOrProps([EntryArg('test-bad-datatype-arg', bool)])
+ self.return_contents = True
def ObtainContents(self):
- if self.return_unknown_contents:
+ if self.return_unknown_contents or not self.return_contents:
return False
self.data = 'a'
self.contents_size = len(self.data)
+ if self.return_contents_once:
+ self.return_contents = False
return True
def GetOffsets(self):
from entry import Entry
import fdt_util
+import state
import tools
class Entry_blob(Entry):
Properties / Entry arguments:
- filename: Filename of file to read into entry
+ - compress: Compression algorithm to use:
+ none: No compression
+ lz4: Use lz4 compression (via 'lz4' command-line utility)
This entry reads data from a file and places it in the entry. The
default filename is often specified specified by the subclass. See for
example the 'u_boot' entry which provides the filename 'u-boot.bin'.
+
+ If compression is enabled, an extra 'uncomp-size' property is written to
+ the node (if enabled with -u) which provides the uncompressed size of the
+ data.
"""
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
- self._filename = fdt_util.GetString(self._node, "filename", self.etype)
+ self._filename = fdt_util.GetString(self._node, 'filename', self.etype)
+ self._compress = fdt_util.GetString(self._node, 'compress', 'none')
+ self._uncompressed_size = None
def ObtainContents(self):
self._filename = self.GetDefaultFilename()
return True
def ReadBlobContents(self):
- with open(self._pathname) as fd:
- # We assume the data is small enough to fit into memory. If this
- # is used for large filesystem image that might not be true.
- # In that case, Image.BuildImage() could be adjusted to use a
- # new Entry method which can read in chunks. Then we could copy
- # the data in chunks and avoid reading it all at once. For now
- # this seems like an unnecessary complication.
- self.SetContents(fd.read())
+ # We assume the data is small enough to fit into memory. If this
+ # is used for large filesystem image that might not be true.
+ # In that case, Image.BuildImage() could be adjusted to use a
+ # new Entry method which can read in chunks. Then we could copy
+ # the data in chunks and avoid reading it all at once. For now
+ # this seems like an unnecessary complication.
+ data = tools.ReadFile(self._pathname)
+ if self._compress == 'lz4':
+ self._uncompressed_size = len(data)
+ '''
+ import lz4 # Import this only if needed (python-lz4 dependency)
+
+ try:
+ data = lz4.frame.compress(data)
+ except AttributeError:
+ data = lz4.compress(data)
+ '''
+ data = tools.Run('lz4', '-c', self._pathname, )
+ self.SetContents(data)
return True
def GetDefaultFilename(self):
return self._filename
+
+ def AddMissingProperties(self):
+ Entry.AddMissingProperties(self)
+ if self._compress != 'none':
+ state.AddZeroProp(self._node, 'uncomp-size')
+
+ def SetCalculatedProperties(self):
+ Entry.SetCalculatedProperties(self)
+ if self._uncompressed_size is not None:
+ state.SetInt(self._node, 'uncomp-size', self._uncompressed_size)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for U-Boot device tree files
+#
+
+import state
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_blob_dtb(Entry_blob):
+ """A blob that holds a device tree
+
+ This is a blob containing a device tree. The contents of the blob are
+ obtained from the list of available device-tree files, managed by the
+ 'state' module.
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+
+ def ObtainContents(self):
+ """Get the device-tree from the list held by the 'state' module"""
+ self._filename = self.GetDefaultFilename()
+ self._pathname, data = state.GetFdtContents(self._filename)
+ self.SetContents(data)
+ return True
+
+ def ProcessContents(self):
+ """Re-read the DTB contents so that we get any calculated properties"""
+ _, data = state.GetFdtContents(self._filename)
+ self.SetContents(data)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for a set of files which are placed in individual
+# sub-entries
+#
+
+import glob
+import os
+
+from section import Entry_section
+import fdt_util
+import state
+import tools
+
+import bsection
+
+class Entry_files(Entry_section):
+ """Entry containing a set of files
+
+ Properties / Entry arguments:
+ - pattern: Filename pattern to match the files to include
+ - compress: Compression algorithm to use:
+ none: No compression
+ lz4: Use lz4 compression (via 'lz4' command-line utility)
+
+ This entry reads a number of files and places each in a separate sub-entry
+ within this entry. To access these you need to enable device-tree updates
+ at run-time so you can obtain the file positions.
+ """
+ def __init__(self, section, etype, node):
+ Entry_section.__init__(self, section, etype, node)
+ self._pattern = fdt_util.GetString(self._node, 'pattern')
+ if not self._pattern:
+ self.Raise("Missing 'pattern' property")
+ self._compress = fdt_util.GetString(self._node, 'compress', 'none')
+ self._require_matches = fdt_util.GetBool(self._node,
+ 'require-matches')
+
+ def ExpandEntries(self):
+ files = tools.GetInputFilenameGlob(self._pattern)
+ if self._require_matches and not files:
+ self.Raise("Pattern '%s' matched no files" % self._pattern)
+ for fname in files:
+ if not os.path.isfile(fname):
+ continue
+ name = os.path.basename(fname)
+ subnode = self._node.FindNode(name)
+ if not subnode:
+ subnode = state.AddSubnode(self._node, name)
+ state.AddString(subnode, 'type', 'blob')
+ state.AddString(subnode, 'filename', fname)
+ state.AddString(subnode, 'compress', self._compress)
+
+ # Read entries again, now that we have some
+ self._section._ReadEntries()
"""
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
- if not self.size:
+ if self.size is None:
self.Raise("'fill' entry must have a size property")
self.fill_value = fdt_util.GetByte(self._node, 'fill-byte', 0)
for subentry in entries.values():
_AddEntries(areas, subentry)
else:
- areas.append(fmap_util.FmapArea(entry.image_pos or 0,
- entry.size or 0, entry.name, 0))
+ pos = entry.image_pos
+ if pos is not None:
+ pos -= entry.section.GetRootSkipAtStart()
+ areas.append(fmap_util.FmapArea(pos or 0, entry.size or 0,
+ entry.name, 0))
- entries = self.section.GetEntries()
+ entries = self.section._image.GetEntries()
areas = []
for entry in entries.values():
_AddEntries(areas, entry)
- return fmap_util.EncodeFmap(self.section.GetSize() or 0, self.name,
+ return fmap_util.EncodeFmap(self.section.GetImageSize() or 0, self.name,
areas)
def ObtainContents(self):
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2018 NXP
+#
+# Entry-type module for the PowerPC mpc85xx bootpg and resetvec code for U-Boot
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_powerpc_mpc85xx_bootpg_resetvec(Entry_blob):
+ """PowerPC mpc85xx bootpg + resetvec code for U-Boot
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot-br.bin (default 'u-boot-br.bin')
+
+ This enrty is valid for PowerPC mpc85xx cpus. This entry holds
+ 'bootpg + resetvec' code for PowerPC mpc85xx CPUs which needs to be
+ placed at offset 'RESET_VECTOR_ADDRESS - 0xffc'.
+ """
+
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'u-boot-br.bin'
"""
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
- self._section = bsection.Section(node.name, node)
+ self._section = bsection.Section(node.name, section, node,
+ section._image)
+
+ def GetFdtSet(self):
+ return self._section.GetFdtSet()
def ProcessFdt(self, fdt):
return self._section.ProcessFdt(fdt)
+ def ExpandEntries(self):
+ Entry.ExpandEntries(self)
+ self._section.ExpandEntries()
+
def AddMissingProperties(self):
Entry.AddMissingProperties(self)
self._section.AddMissingProperties()
def GetEntries(self):
return self._section.GetEntries()
+
+ def ExpandToLimit(self, limit):
+ super(Entry_section, self).ExpandToLimit(limit)
+ self._section.ExpandSize(self.size)
self.text_label, = self.GetEntryArgsOrProps(
[EntryArg('text-label', str)])
self.value, = self.GetEntryArgsOrProps([EntryArg(self.text_label, str)])
+ if not self.value:
+ self.Raise("No value provided for text label '%s'" %
+ self.text_label)
def ObtainContents(self):
self.SetContents(self.value)
#
from entry import Entry
-from blob import Entry_blob
+from blob_dtb import Entry_blob_dtb
-class Entry_u_boot_dtb(Entry_blob):
+class Entry_u_boot_dtb(Entry_blob_dtb):
"""U-Boot device tree
Properties / Entry arguments:
This is the U-Boot device tree, containing configuration information for
U-Boot. U-Boot needs this to know what devices are present and which drivers
to activate.
+
+ Note: This is mostly an internal entry type, used by others. This allows
+ binman to know which entries contain a device tree.
"""
def __init__(self, section, etype, node):
- Entry_blob.__init__(self, section, etype, node)
+ Entry_blob_dtb.__init__(self, section, etype, node)
def GetDefaultFilename(self):
return 'u-boot.dtb'
# Entry-type module for U-Boot device tree with the microcode removed
#
-import control
from entry import Entry
-from blob import Entry_blob
+from blob_dtb import Entry_blob_dtb
+import state
import tools
-class Entry_u_boot_dtb_with_ucode(Entry_blob):
+class Entry_u_boot_dtb_with_ucode(Entry_blob_dtb):
"""A U-Boot device tree file, with the microcode removed
Properties / Entry arguments:
it available to u_boot_ucode.
"""
def __init__(self, section, etype, node):
- Entry_blob.__init__(self, section, etype, node)
+ Entry_blob_dtb.__init__(self, section, etype, node)
self.ucode_data = ''
self.collate = False
self.ucode_offset = None
# If the section does not need microcode, there is nothing to do
ucode_dest_entry = self.section.FindEntryType(
'u-boot-spl-with-ucode-ptr')
+ if not ucode_dest_entry or not ucode_dest_entry.target_offset:
+ ucode_dest_entry = self.section.FindEntryType(
+ 'u-boot-tpl-with-ucode-ptr')
if not ucode_dest_entry or not ucode_dest_entry.target_offset:
ucode_dest_entry = self.section.FindEntryType(
'u-boot-with-ucode-ptr')
# Remove the microcode
fname = self.GetDefaultFilename()
- fdt = control.GetFdt(fname)
+ fdt = state.GetFdt(fname)
self.ucode = fdt.GetNode('/microcode')
if not self.ucode:
raise self.Raise("No /microcode node found in '%s'" % fname)
def ObtainContents(self):
# Call the base class just in case it does something important.
- Entry_blob.ObtainContents(self)
- self._pathname = control.GetFdtPath(self._filename)
- self.ReadBlobContents()
- if self.ucode:
+ Entry_blob_dtb.ObtainContents(self)
+ if self.ucode and not self.collate:
for node in self.ucode.subnodes:
data_prop = node.props.get('data')
- if data_prop and not self.collate:
+ if data_prop:
# Find the offset in the device tree of the ucode data
self.ucode_offset = data_prop.GetOffset() + 12
self.ucode_size = len(data_prop.bytes)
- self.ready = True
- return True
+ self.ready = True
+ else:
+ self.ready = True
+ return self.ready
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for U-Boot ELF image
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+import fdt_util
+import tools
+
+class Entry_u_boot_elf(Entry_blob):
+ """U-Boot ELF image
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot (default 'u-boot')
+
+ This is the U-Boot ELF image. It does not include a device tree but can be
+ relocated to any address for execution.
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+ self._strip = fdt_util.GetBool(self._node, 'strip')
+
+ def ReadBlobContents(self):
+ if self._strip:
+ uniq = self.GetUniqueName()
+ out_fname = tools.GetOutputFilename('%s.stripped' % uniq)
+ tools.WriteFile(out_fname, tools.ReadFile(self._pathname))
+ tools.Run('strip', out_fname)
+ self.SetContents(tools.ReadFile(out_fname))
+ else:
+ self.SetContents(tools.ReadFile(self._pathname))
+ return True
+
+ def GetDefaultFilename(self):
+ return 'u-boot'
#
from entry import Entry
-from blob import Entry_blob
+from blob_dtb import Entry_blob_dtb
-class Entry_u_boot_spl_dtb(Entry_blob):
+class Entry_u_boot_spl_dtb(Entry_blob_dtb):
"""U-Boot SPL device tree
Properties / Entry arguments:
to activate.
"""
def __init__(self, section, etype, node):
- Entry_blob.__init__(self, section, etype, node)
+ Entry_blob_dtb.__init__(self, section, etype, node)
def GetDefaultFilename(self):
return 'spl/u-boot-spl.dtb'
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for U-Boot SPL ELF image
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_spl_elf(Entry_blob):
+ """U-Boot SPL ELF image
+
+ Properties / Entry arguments:
+ - filename: Filename of SPL u-boot (default 'spl/u-boot')
+
+ This is the U-Boot SPL ELF image. It does not include a device tree but can
+ be relocated to any address for execution.
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'spl/u-boot-spl'
class Entry_u_boot_spl_with_ucode_ptr(Entry_u_boot_with_ucode_ptr):
"""U-Boot SPL with embedded microcode pointer
+ This is used when SPL must set up the microcode for U-Boot.
+
See Entry_u_boot_ucode for full details of the entries involved in this
process.
"""
#
from entry import Entry
-from blob import Entry_blob
+from blob_dtb import Entry_blob_dtb
-class Entry_u_boot_tpl_dtb(Entry_blob):
+class Entry_u_boot_tpl_dtb(Entry_blob_dtb):
"""U-Boot TPL device tree
Properties / Entry arguments:
to activate.
"""
def __init__(self, section, etype, node):
- Entry_blob.__init__(self, section, etype, node)
+ Entry_blob_dtb.__init__(self, section, etype, node)
def GetDefaultFilename(self):
return 'tpl/u-boot-tpl.dtb'
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for U-Boot device tree with the microcode removed
+#
+
+import control
+from entry import Entry
+from u_boot_dtb_with_ucode import Entry_u_boot_dtb_with_ucode
+import tools
+
+class Entry_u_boot_tpl_dtb_with_ucode(Entry_u_boot_dtb_with_ucode):
+ """U-Boot TPL with embedded microcode pointer
+
+ This is used when TPL must set up the microcode for U-Boot.
+
+ See Entry_u_boot_ucode for full details of the entries involved in this
+ process.
+ """
+ def __init__(self, section, etype, node):
+ Entry_u_boot_dtb_with_ucode.__init__(self, section, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'tpl/u-boot-tpl.dtb'
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for an TPL binary with an embedded microcode pointer
+#
+
+import struct
+
+import command
+from entry import Entry
+from blob import Entry_blob
+from u_boot_with_ucode_ptr import Entry_u_boot_with_ucode_ptr
+import tools
+
+class Entry_u_boot_tpl_with_ucode_ptr(Entry_u_boot_with_ucode_ptr):
+ """U-Boot TPL with embedded microcode pointer
+
+ See Entry_u_boot_ucode for full details of the entries involved in this
+ process.
+ """
+ def __init__(self, section, etype, node):
+ Entry_u_boot_with_ucode_ptr.__init__(self, section, etype, node)
+ self.elf_fname = 'tpl/u-boot-tpl'
+
+ def GetDefaultFilename(self):
+ return 'tpl/u-boot-tpl-nodtb.bin'
def ObtainContents(self):
# If the section does not need microcode, there is nothing to do
- ucode_dest_entry = self.section.FindEntryType('u-boot-with-ucode-ptr')
- ucode_dest_entry_spl = self.section.FindEntryType(
- 'u-boot-spl-with-ucode-ptr')
- if ((not ucode_dest_entry or not ucode_dest_entry.target_offset) and
- (not ucode_dest_entry_spl or not ucode_dest_entry_spl.target_offset)):
+ found = False
+ for suffix in ['', '-spl', '-tpl']:
+ name = 'u-boot%s-with-ucode-ptr' % suffix
+ entry = self.section.FindEntryType(name)
+ if entry and entry.target_offset:
+ found = True
+ if not found:
self.data = ''
return True
-
# Get the microcode from the device tree entry. If it is not available
# yet, return False so we will be called later. If the section simply
# doesn't exist, then we may as well return True, since we are going to
# get an error anyway.
- fdt_entry = self.section.FindEntryType('u-boot-dtb-with-ucode')
+ for suffix in ['', '-spl', '-tpl']:
+ name = 'u-boot%s-dtb-with-ucode' % suffix
+ fdt_entry = self.section.FindEntryType(name)
+ if fdt_entry:
+ break
if not fdt_entry:
return True
if not fdt_entry.ready:
return True
# Write it out to a file
- dtb_name = 'u-boot-ucode.bin'
- fname = tools.GetOutputFilename(dtb_name)
- with open(fname, 'wb') as fd:
- fd.write(fdt_entry.ucode_data)
+ self._pathname = tools.GetOutputFilename('u-boot-ucode.bin')
+ tools.WriteFile(self._pathname, fdt_entry.ucode_data)
- self._pathname = fname
self.ReadBlobContents()
return True
Properties / Entry arguments:
- filename: Filename of u-boot-nodtb.dtb (default 'u-boot-nodtb.dtb')
+ - optional-ucode: boolean property to make microcode optional. If the
+ u-boot.bin image does not include microcode, no error will
+ be generated.
See Entry_u_boot_ucode for full details of the three entries involved in
this process. This entry updates U-Boot with the offset and size of the
# the U-Boot region must start at offset 7MB in the section. In this
# case the ROM starts at 0xff800000, so the offset of the first
# entry in the section corresponds to that.
- if (self.target_offset < self.offset or
- self.target_offset >= self.offset + self.size):
- self.Raise('Microcode pointer _dt_ucode_base_size at %08x is '
- 'outside the section ranging from %08x to %08x' %
- (self.target_offset, self.offset, self.offset + self.size))
+ if (self.target_offset < self.image_pos or
+ self.target_offset >= self.image_pos + self.size):
+ self.Raise('Microcode pointer _dt_ucode_base_size at %08x is outside the section ranging from %08x to %08x' %
+ (self.target_offset, self.image_pos,
+ self.image_pos + self.size))
# Get the microcode, either from u-boot-ucode or u-boot-dtb-with-ucode.
# If we have left the microcode in the device tree, then it will be
- # in the former. If we extracted the microcode from the device tree
- # and collated it in one place, it will be in the latter.
+ # in the latter. If we extracted the microcode from the device tree
+ # and collated it in one place, it will be in the former.
if ucode_entry.size:
offset, size = ucode_entry.offset, ucode_entry.size
else:
dtb_entry = self.section.FindEntryType('u-boot-dtb-with-ucode')
- if not dtb_entry or not dtb_entry.ready:
+ if not dtb_entry:
+ dtb_entry = self.section.FindEntryType(
+ 'u-boot-tpl-dtb-with-ucode')
+ if not dtb_entry:
self.Raise('Cannot find microcode region u-boot-dtb-with-ucode')
offset = dtb_entry.offset + dtb_entry.ucode_offset
size = dtb_entry.ucode_size
# Write the microcode offset and size into the entry
offset_and_size = struct.pack('<2L', offset, size)
- self.target_offset -= self.offset
+ self.target_offset -= self.image_pos
self.ProcessContentsUpdate(self.data[:self.target_offset] +
offset_and_size +
self.data[self.target_offset + 8:])
- kernelkey: Name of the kernel key to use (inside keydir)
- preamble-flags: Value of the vboot preamble flags (typically 0)
+ Output files:
+ - input.<unique_name> - input file passed to futility
+ - vblock.<unique_name> - output file generated by futility (which is
+ used as the entry contents)
+
Chromium OS signs the read-write firmware and kernel, writing the signature
in this block. This allows U-Boot to verify that the next firmware stage
and kernel are genuine.
return False
input_data += data
- output_fname = tools.GetOutputFilename('vblock.%s' % self.name)
- input_fname = tools.GetOutputFilename('input.%s' % self.name)
+ uniq = self.GetUniqueName()
+ output_fname = tools.GetOutputFilename('vblock.%s' % uniq)
+ input_fname = tools.GetOutputFilename('input.%s' % uniq)
tools.WriteFile(input_fname, input_data)
prefix = self.keydir + '/'
args = [
]
#out.Notice("Sign '%s' into %s" % (', '.join(self.value), self.label))
stdout = tools.Run('futility', *args)
- #out.Debug(stdout)
self.SetContents(tools.ReadFile(output_fname))
return True
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for the 16-bit x86 start-up code for U-Boot TPL
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_x86_start16_tpl(Entry_blob):
+ """x86 16-bit start-up code for TPL
+
+ Properties / Entry arguments:
+ - filename: Filename of tpl/u-boot-x86-16bit-tpl.bin (default
+ 'tpl/u-boot-x86-16bit-tpl.bin')
+
+ x86 CPUs start up in 16-bit mode, even if they are 64-bit CPUs. This code
+ must be placed at a particular address. This entry holds that code. It is
+ typically placed at offset CONFIG_SYS_X86_START16. The code is responsible
+ for changing to 32-bit mode and starting TPL, which in turn jumps to SPL.
+
+ If TPL is not being used, the 'x86_start16_spl or 'x86_start16' entry types
+ may be used instead.
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'tpl/u-boot-x86-16bit-tpl.bin'
FmapArea = collections.namedtuple('FmapArea', FMAP_AREA_NAMES)
+def NameToFmap(name):
+ return name.replace('\0', '').replace('-', '_').upper()
+
def ConvertName(field_names, fields):
"""Convert a name to something flashrom likes
value: value of that field (string for the ones we support)
"""
name_index = field_names.index('name')
- fields[name_index] = fields[name_index].replace('\0', '').replace('-', '_').upper()
+ fields[name_index] = NameToFmap(fields[name_index])
def DecodeFmap(data):
"""Decode a flashmap into a header and list of areas
"""
def _FormatBlob(fmt, names, obj):
params = [getattr(obj, name) for name in names]
+ ConvertName(names, params)
return struct.pack(fmt, *params)
values = FmapHeader(FMAP_SIGNATURE, 1, 0, 0, image_size, name, len(areas))
#
# python -m unittest func_test.TestFunctional.testHelp
+import hashlib
from optparse import OptionParser
import os
import shutil
import fdt_util
import fmap_util
import test_util
+import state
import tools
import tout
U_BOOT_TPL_DTB_DATA = 'tpldtb'
X86_START16_DATA = 'start16'
X86_START16_SPL_DATA = 'start16spl'
+X86_START16_TPL_DATA = 'start16tpl'
+PPC_MPC85XX_BR_DATA = 'ppcmpc85xxbr'
U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here'
U_BOOT_SPL_NODTB_DATA = 'splnodtb with microcode pointer somewhere in here'
+U_BOOT_TPL_NODTB_DATA = 'tplnodtb with microcode pointer somewhere in here'
FSP_DATA = 'fsp'
CMC_DATA = 'cmc'
VBT_DATA = 'vbt'
GBB_DATA = 'gbbd'
BMPBLK_DATA = 'bmp'
VBLOCK_DATA = 'vblk'
+FILES_DATA = ("sorry I'm late\nOh, don't bother apologising, I'm " +
+ "sorry you're alive\n")
+COMPRESS_DATA = 'data to compress'
class TestFunctional(unittest.TestCase):
TestFunctional._MakeInputFile('vga.bin', VGA_DATA)
self._ResetDtbs()
TestFunctional._MakeInputFile('u-boot-x86-16bit.bin', X86_START16_DATA)
+ TestFunctional._MakeInputFile('u-boot-br.bin', PPC_MPC85XX_BR_DATA)
TestFunctional._MakeInputFile('spl/u-boot-x86-16bit-spl.bin',
X86_START16_SPL_DATA)
+ TestFunctional._MakeInputFile('tpl/u-boot-x86-16bit-tpl.bin',
+ X86_START16_TPL_DATA)
TestFunctional._MakeInputFile('u-boot-nodtb.bin', U_BOOT_NODTB_DATA)
TestFunctional._MakeInputFile('spl/u-boot-spl-nodtb.bin',
U_BOOT_SPL_NODTB_DATA)
+ TestFunctional._MakeInputFile('tpl/u-boot-tpl-nodtb.bin',
+ U_BOOT_TPL_NODTB_DATA)
TestFunctional._MakeInputFile('fsp.bin', FSP_DATA)
TestFunctional._MakeInputFile('cmc.bin', CMC_DATA)
TestFunctional._MakeInputFile('vbt.bin', VBT_DATA)
with open(self.TestFile('descriptor.bin')) as fd:
TestFunctional._MakeInputFile('descriptor.bin', fd.read())
+ shutil.copytree(self.TestFile('files'),
+ os.path.join(self._indir, 'files'))
+
+ TestFunctional._MakeInputFile('compress', COMPRESS_DATA)
+
@classmethod
def tearDownClass(self):
"""Remove the temporary input directory and its contents"""
return control.Binman(options, args)
def _DoTestFile(self, fname, debug=False, map=False, update_dtb=False,
- entry_args=None):
+ entry_args=None, images=None, use_real_dtb=False):
"""Run binman with a given test file
Args:
map: True to output map files for the images
update_dtb: Update the offset and size of each entry in the device
tree before packing it into the image
+ entry_args: Dict of entry args to supply to binman
+ key: arg name
+ value: value of that arg
+ images: List of image names to build
"""
args = ['-p', '-I', self._indir, '-d', self.TestFile(fname)]
if debug:
args.append('-m')
if update_dtb:
args.append('-up')
+ if not use_real_dtb:
+ args.append('--fake-dtb')
if entry_args:
for arg, value in entry_args.iteritems():
args.append('-a%s=%s' % (arg, value))
+ if images:
+ for image in images:
+ args += ['-i', image]
return self._DoBinman(*args)
def _SetupDtb(self, fname, outfile='u-boot.dtb'):
TestFunctional._MakeInputFile(outfile, data)
return data
+ def _GetDtbContentsForSplTpl(self, dtb_data, name):
+ """Create a version of the main DTB for SPL or SPL
+
+ For testing we don't actually have different versions of the DTB. With
+ U-Boot we normally run fdtgrep to remove unwanted nodes, but for tests
+ we don't normally have any unwanted nodes.
+
+ We still want the DTBs for SPL and TPL to be different though, since
+ otherwise it is confusing to know which one we are looking at. So add
+ an 'spl' or 'tpl' property to the top-level node.
+ """
+ dtb = fdt.Fdt.FromData(dtb_data)
+ dtb.Scan()
+ dtb.GetNode('/binman').AddZeroProp(name)
+ dtb.Sync(auto_resize=True)
+ dtb.Pack()
+ return dtb.GetContents()
+
def _DoReadFileDtb(self, fname, use_real_dtb=False, map=False,
- update_dtb=False, entry_args=None):
+ update_dtb=False, entry_args=None, reset_dtbs=True):
"""Run binman and return the resulting image
This runs binman with a given test file and then reads the resulting
# Use the compiled test file as the u-boot-dtb input
if use_real_dtb:
dtb_data = self._SetupDtb(fname)
+ infile = os.path.join(self._indir, 'u-boot.dtb')
+
+ # For testing purposes, make a copy of the DT for SPL and TPL. Add
+ # a node indicating which it is, so aid verification.
+ for name in ['spl', 'tpl']:
+ dtb_fname = '%s/u-boot-%s.dtb' % (name, name)
+ outfile = os.path.join(self._indir, dtb_fname)
+ TestFunctional._MakeInputFile(dtb_fname,
+ self._GetDtbContentsForSplTpl(dtb_data, name))
try:
retcode = self._DoTestFile(fname, map=map, update_dtb=update_dtb,
- entry_args=entry_args)
+ entry_args=entry_args, use_real_dtb=use_real_dtb)
self.assertEqual(0, retcode)
- out_dtb_fname = control.GetFdtPath('u-boot.dtb')
+ out_dtb_fname = tools.GetOutputFilename('u-boot.dtb.out')
# Find the (only) image, read it and return its contents
image = control.images['image']
return fd.read(), dtb_data, map_data, out_dtb_fname
finally:
# Put the test file back
- if use_real_dtb:
+ if reset_dtbs and use_real_dtb:
self._ResetDtbs()
def _DoReadFile(self, fname, use_real_dtb=False):
self.assertIn("Section '/binman': Section size must be provided when "
"using end-at-4gb", str(e.exception))
+ def test4gbAndSkipAtStartTogether(self):
+ """Test that the end-at-4gb and skip-at-size property can't be used
+ together"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('80_4gb_and_skip_at_start_together.dts')
+ self.assertIn("Section '/binman': Provide either 'end-at-4gb' or "
+ "'skip-at-start'", str(e.exception))
+
def testPackX86RomOutside(self):
"""Test that the end-at-4gb property checks for offset boundaries"""
with self.assertRaises(ValueError) as e:
data = self._DoReadFile('33_x86-start16.dts')
self.assertEqual(X86_START16_DATA, data[:len(X86_START16_DATA)])
+ def testPackPowerpcMpc85xxBootpgResetvec(self):
+ """Test that an image with powerpc-mpc85xx-bootpg-resetvec can be
+ created"""
+ data = self._DoReadFile('81_powerpc_mpc85xx_bootpg_resetvec.dts')
+ self.assertEqual(PPC_MPC85XX_BR_DATA, data[:len(PPC_MPC85XX_BR_DATA)])
+
def _RunMicrocodeTest(self, dts_fname, nodtb_data, ucode_second=False):
"""Handle running a test for insertion of microcode
str(e.exception))
def testPackStart16Spl(self):
- """Test that an image with an x86 start16 region can be created"""
+ """Test that an image with an x86 start16 SPL region can be created"""
data = self._DoReadFile('48_x86-start16-spl.dts')
self.assertEqual(X86_START16_SPL_DATA, data[:len(X86_START16_SPL_DATA)])
"""Fake calls to the futility utility"""
if pipe_list[0][0] == 'futility':
fname = pipe_list[0][3]
- with open(fname, 'w') as fd:
+ with open(fname, 'wb') as fd:
fd.write(VBLOCK_DATA)
return command.CommandResult()
self.assertIn("Node '/binman/u-boot': Please use 'offset' instead of "
"'pos'", str(e.exception))
+ def testFillZero(self):
+ """Test for an fill entry type with a size of 0"""
+ data = self._DoReadFile('80_fill_empty.dts')
+ self.assertEqual(chr(0) * 16, data)
+
+ def testTextMissing(self):
+ """Test for a text entry type where there is no text"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('66_text.dts',)
+ self.assertIn("Node '/binman/text': No value provided for text label "
+ "'test-id'", str(e.exception))
+
+ def testPackStart16Tpl(self):
+ """Test that an image with an x86 start16 TPL region can be created"""
+ data = self._DoReadFile('81_x86-start16-tpl.dts')
+ self.assertEqual(X86_START16_TPL_DATA, data[:len(X86_START16_TPL_DATA)])
+
+ def testSelectImage(self):
+ """Test that we can select which images to build"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ retcode = self._DoTestFile('06_dual_image.dts', images=['image2'])
+ self.assertEqual(0, retcode)
+ self.assertIn('Skipping images: image1', stdout.getvalue())
+
+ self.assertFalse(os.path.exists(tools.GetOutputFilename('image1.bin')))
+ self.assertTrue(os.path.exists(tools.GetOutputFilename('image2.bin')))
+
+ def testUpdateFdtAll(self):
+ """Test that all device trees are updated with offset/size info"""
+ data, _, _, _ = self._DoReadFileDtb('82_fdt_update_all.dts',
+ use_real_dtb=True, update_dtb=True)
+
+ base_expected = {
+ 'section:image-pos': 0,
+ 'u-boot-tpl-dtb:size': 513,
+ 'u-boot-spl-dtb:size': 513,
+ 'u-boot-spl-dtb:offset': 493,
+ 'image-pos': 0,
+ 'section/u-boot-dtb:image-pos': 0,
+ 'u-boot-spl-dtb:image-pos': 493,
+ 'section/u-boot-dtb:size': 493,
+ 'u-boot-tpl-dtb:image-pos': 1006,
+ 'section/u-boot-dtb:offset': 0,
+ 'section:size': 493,
+ 'offset': 0,
+ 'section:offset': 0,
+ 'u-boot-tpl-dtb:offset': 1006,
+ 'size': 1519
+ }
+
+ # We expect three device-tree files in the output, one after the other.
+ # Read them in sequence. We look for an 'spl' property in the SPL tree,
+ # and 'tpl' in the TPL tree, to make sure they are distinct from the
+ # main U-Boot tree. All three should have the same postions and offset.
+ start = 0
+ for item in ['', 'spl', 'tpl']:
+ dtb = fdt.Fdt.FromData(data[start:])
+ dtb.Scan()
+ props = self._GetPropTree(dtb, ['offset', 'size', 'image-pos',
+ 'spl', 'tpl'])
+ expected = dict(base_expected)
+ if item:
+ expected[item] = 0
+ self.assertEqual(expected, props)
+ start += dtb._fdt_obj.totalsize()
+
+ def testUpdateFdtOutput(self):
+ """Test that output DTB files are updated"""
+ try:
+ data, dtb_data, _, _ = self._DoReadFileDtb('82_fdt_update_all.dts',
+ use_real_dtb=True, update_dtb=True, reset_dtbs=False)
+
+ # Unfortunately, compiling a source file always results in a file
+ # called source.dtb (see fdt_util.EnsureCompiled()). The test
+ # source file (e.g. test/75_fdt_update_all.dts) thus does not enter
+ # binman as a file called u-boot.dtb. To fix this, copy the file
+ # over to the expected place.
+ #tools.WriteFile(os.path.join(self._indir, 'u-boot.dtb'),
+ #tools.ReadFile(tools.GetOutputFilename('source.dtb')))
+ start = 0
+ for fname in ['u-boot.dtb.out', 'spl/u-boot-spl.dtb.out',
+ 'tpl/u-boot-tpl.dtb.out']:
+ dtb = fdt.Fdt.FromData(data[start:])
+ size = dtb._fdt_obj.totalsize()
+ pathname = tools.GetOutputFilename(os.path.split(fname)[1])
+ outdata = tools.ReadFile(pathname)
+ name = os.path.split(fname)[0]
+
+ if name:
+ orig_indata = self._GetDtbContentsForSplTpl(dtb_data, name)
+ else:
+ orig_indata = dtb_data
+ self.assertNotEqual(outdata, orig_indata,
+ "Expected output file '%s' be updated" % pathname)
+ self.assertEqual(outdata, data[start:start + size],
+ "Expected output file '%s' to match output image" %
+ pathname)
+ start += size
+ finally:
+ self._ResetDtbs()
+
+ def _decompress(self, data):
+ out = os.path.join(self._indir, 'lz4.tmp')
+ with open(out, 'wb') as fd:
+ fd.write(data)
+ return tools.Run('lz4', '-dc', out)
+ '''
+ try:
+ orig = lz4.frame.decompress(data)
+ except AttributeError:
+ orig = lz4.decompress(data)
+ '''
+
+ def testCompress(self):
+ """Test compression of blobs"""
+ data, _, _, out_dtb_fname = self._DoReadFileDtb('83_compress.dts',
+ use_real_dtb=True, update_dtb=True)
+ dtb = fdt.Fdt(out_dtb_fname)
+ dtb.Scan()
+ props = self._GetPropTree(dtb, ['size', 'uncomp-size'])
+ orig = self._decompress(data)
+ self.assertEquals(COMPRESS_DATA, orig)
+ expected = {
+ 'blob:uncomp-size': len(COMPRESS_DATA),
+ 'blob:size': len(data),
+ 'size': len(data),
+ }
+ self.assertEqual(expected, props)
+
+ def testFiles(self):
+ """Test bringing in multiple files"""
+ data = self._DoReadFile('84_files.dts')
+ self.assertEqual(FILES_DATA, data)
+
+ def testFilesCompress(self):
+ """Test bringing in multiple files and compressing them"""
+ data = self._DoReadFile('85_files_compress.dts')
+
+ image = control.images['image']
+ entries = image.GetEntries()
+ files = entries['files']
+ entries = files._section._entries
+
+ orig = ''
+ for i in range(1, 3):
+ key = '%d.dat' % i
+ start = entries[key].image_pos
+ len = entries[key].size
+ chunk = data[start:start + len]
+ orig += self._decompress(chunk)
+
+ self.assertEqual(FILES_DATA, orig)
+
+ def testFilesMissing(self):
+ """Test missing files"""
+ with self.assertRaises(ValueError) as e:
+ data = self._DoReadFile('86_files_none.dts')
+ self.assertIn("Node '/binman/files': Pattern \'files/*.none\' matched "
+ 'no files', str(e.exception))
+
+ def testFilesNoPattern(self):
+ """Test missing files"""
+ with self.assertRaises(ValueError) as e:
+ data = self._DoReadFile('87_files_no_pattern.dts')
+ self.assertIn("Node '/binman/files': Missing 'pattern' property",
+ str(e.exception))
+
+ def testExpandSize(self):
+ """Test an expanding entry"""
+ data, _, map_data, _ = self._DoReadFileDtb('88_expand_size.dts',
+ map=True)
+ expect = ('a' * 8 + U_BOOT_DATA +
+ MRC_DATA + 'b' * 1 + U_BOOT_DATA +
+ 'c' * 8 + U_BOOT_DATA +
+ 'd' * 8)
+ self.assertEqual(expect, data)
+ self.assertEqual('''ImagePos Offset Size Name
+00000000 00000000 00000028 main-section
+00000000 00000000 00000008 fill
+00000008 00000008 00000004 u-boot
+0000000c 0000000c 00000004 section
+0000000c 00000000 00000003 intel-mrc
+00000010 00000010 00000004 u-boot2
+00000014 00000014 0000000c section2
+00000014 00000000 00000008 fill
+0000001c 00000008 00000004 u-boot
+00000020 00000020 00000008 fill2
+''', map_data)
+
+ def testExpandSizeBad(self):
+ """Test an expanding entry which fails to provide contents"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('89_expand_size_bad.dts', map=True)
+ self.assertIn("Node '/binman/_testing': Cannot obtain contents when "
+ 'expanding entry', str(e.exception))
+
+ def testHash(self):
+ """Test hashing of the contents of an entry"""
+ _, _, _, out_dtb_fname = self._DoReadFileDtb('90_hash.dts',
+ use_real_dtb=True, update_dtb=True)
+ dtb = fdt.Fdt(out_dtb_fname)
+ dtb.Scan()
+ hash_node = dtb.GetNode('/binman/u-boot/hash').props['value']
+ m = hashlib.sha256()
+ m.update(U_BOOT_DATA)
+ self.assertEqual(m.digest(), ''.join(hash_node.value))
+
+ def testHashNoAlgo(self):
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('91_hash_no_algo.dts', update_dtb=True)
+ self.assertIn("Node \'/binman/u-boot\': Missing \'algo\' property for "
+ 'hash node', str(e.exception))
+
+ def testHashBadAlgo(self):
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('92_hash_bad_algo.dts', update_dtb=True)
+ self.assertIn("Node '/binman/u-boot': Unknown hash algorithm",
+ str(e.exception))
+
+ def testHashSection(self):
+ """Test hashing of the contents of an entry"""
+ _, _, _, out_dtb_fname = self._DoReadFileDtb('99_hash_section.dts',
+ use_real_dtb=True, update_dtb=True)
+ dtb = fdt.Fdt(out_dtb_fname)
+ dtb.Scan()
+ hash_node = dtb.GetNode('/binman/section/hash').props['value']
+ m = hashlib.sha256()
+ m.update(U_BOOT_DATA)
+ m.update(16 * 'a')
+ self.assertEqual(m.digest(), ''.join(hash_node.value))
+
+ def testPackUBootTplMicrocode(self):
+ """Test that x86 microcode can be handled correctly in TPL
+
+ We expect to see the following in the image, in order:
+ u-boot-tpl-nodtb.bin with a microcode pointer inserted at the correct
+ place
+ u-boot-tpl.dtb with the microcode removed
+ the microcode
+ """
+ with open(self.TestFile('u_boot_ucode_ptr')) as fd:
+ TestFunctional._MakeInputFile('tpl/u-boot-tpl', fd.read())
+ first, pos_and_size = self._RunMicrocodeTest('93_x86_tpl_ucode.dts',
+ U_BOOT_TPL_NODTB_DATA)
+ self.assertEqual('tplnodtb with microc' + pos_and_size +
+ 'ter somewhere in here', first)
+
+ def testFmapX86(self):
+ """Basic test of generation of a flashrom fmap"""
+ data = self._DoReadFile('94_fmap_x86.dts')
+ fhdr, fentries = fmap_util.DecodeFmap(data[32:])
+ expected = U_BOOT_DATA + MRC_DATA + 'a' * (32 - 7)
+ self.assertEqual(expected, data[:32])
+ fhdr, fentries = fmap_util.DecodeFmap(data[32:])
+
+ self.assertEqual(0x100, fhdr.image_size)
+
+ self.assertEqual(0, fentries[0].offset)
+ self.assertEqual(4, fentries[0].size)
+ self.assertEqual('U_BOOT', fentries[0].name)
+
+ self.assertEqual(4, fentries[1].offset)
+ self.assertEqual(3, fentries[1].size)
+ self.assertEqual('INTEL_MRC', fentries[1].name)
+
+ self.assertEqual(32, fentries[2].offset)
+ self.assertEqual(fmap_util.FMAP_HEADER_LEN +
+ fmap_util.FMAP_AREA_LEN * 3, fentries[2].size)
+ self.assertEqual('FMAP', fentries[2].name)
+
+ def testFmapX86Section(self):
+ """Basic test of generation of a flashrom fmap"""
+ data = self._DoReadFile('95_fmap_x86_section.dts')
+ expected = U_BOOT_DATA + MRC_DATA + 'b' * (32 - 7)
+ self.assertEqual(expected, data[:32])
+ fhdr, fentries = fmap_util.DecodeFmap(data[36:])
+
+ self.assertEqual(0x100, fhdr.image_size)
+
+ self.assertEqual(0, fentries[0].offset)
+ self.assertEqual(4, fentries[0].size)
+ self.assertEqual('U_BOOT', fentries[0].name)
+
+ self.assertEqual(4, fentries[1].offset)
+ self.assertEqual(3, fentries[1].size)
+ self.assertEqual('INTEL_MRC', fentries[1].name)
+
+ self.assertEqual(36, fentries[2].offset)
+ self.assertEqual(fmap_util.FMAP_HEADER_LEN +
+ fmap_util.FMAP_AREA_LEN * 3, fentries[2].size)
+ self.assertEqual('FMAP', fentries[2].name)
+
+ def testElf(self):
+ """Basic test of ELF entries"""
+ with open(self.TestFile('bss_data')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
+ with open(self.TestFile('bss_data')) as fd:
+ TestFunctional._MakeInputFile('-boot', fd.read())
+ data = self._DoReadFile('96_elf.dts')
+
+ def testElfStripg(self):
+ """Basic test of ELF entries"""
+ with open(self.TestFile('bss_data')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
+ with open(self.TestFile('bss_data')) as fd:
+ TestFunctional._MakeInputFile('-boot', fd.read())
+ data = self._DoReadFile('97_elf_strip.dts')
+
+ def testPackOverlapMap(self):
+ """Test that overlapping regions are detected"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('14_pack_overlap.dts', map=True)
+ map_fname = tools.GetOutputFilename('image.map')
+ self.assertEqual("Wrote map file '%s' to show errors\n" % map_fname,
+ stdout.getvalue())
+
+ # We should not get an inmage, but there should be a map file
+ self.assertFalse(os.path.exists(tools.GetOutputFilename('image.bin')))
+ self.assertTrue(os.path.exists(map_fname))
+ map_data = tools.ReadFile(map_fname)
+ self.assertEqual('''ImagePos Offset Size Name
+<none> 00000000 00000007 main-section
+<none> 00000000 00000004 u-boot
+<none> 00000003 00000004 u-boot-align
+''', map_data)
+
if __name__ == "__main__":
unittest.main()
self._size = None
self._filename = '%s.bin' % self._name
if test:
- self._section = bsection.Section('main-section', self._node, True)
+ self._section = bsection.Section('main-section', None, self._node,
+ self, True)
else:
self._ReadNode()
filename = fdt_util.GetString(self._node, 'filename')
if filename:
self._filename = filename
- self._section = bsection.Section('main-section', self._node)
+ self._section = bsection.Section('main-section', None, self._node, self)
+
+ def GetFdtSet(self):
+ """Get the set of device tree files used by this image"""
+ return self._section.GetFdtSet()
+
+ def ExpandEntries(self):
+ """Expand out any entries which have calculated sub-entries
+
+ Some entries are expanded out at runtime, e.g. 'files', which produces
+ a section containing a list of files. Process these entries so that
+ this information is added to the device tree.
+ """
+ self._section.ExpandEntries()
def AddMissingProperties(self):
"""Add properties that are not present in the device tree
self._section.AddMissingProperties()
def ProcessFdt(self, fdt):
+ """Allow entries to adjust the device tree
+
+ Some entries need to adjust the device tree for their purposes. This
+ may involve adding or deleting properties.
+ """
return self._section.ProcessFdt(fdt)
def GetEntryContents(self):
return self._section.GetEntries()
def WriteMap(self):
- """Write a map of the image to a .map file"""
+ """Write a map of the image to a .map file
+
+ Returns:
+ Filename of map file written
+ """
filename = '%s.map' % self._name
fname = tools.GetOutputFilename(filename)
with open(fname, 'w') as fd:
print('%8s %8s %8s %s' % ('ImagePos', 'Offset', 'Size', 'Name'),
file=fd)
self._section.WriteMap(fd, 0)
+ return fname
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Holds and modifies the state information held by binman
+#
+
+import hashlib
+import re
+from sets import Set
+
+import os
+import tools
+
+# Records the device-tree files known to binman, keyed by filename (e.g.
+# 'u-boot-spl.dtb')
+fdt_files = {}
+
+# Arguments passed to binman to provide arguments to entries
+entry_args = {}
+
+# True to use fake device-tree files for testing (see U_BOOT_DTB_DATA in
+# ftest.py)
+use_fake_dtb = False
+
+# Set of all device tree files references by images
+fdt_set = Set()
+
+# Same as above, but excluding the main one
+fdt_subset = Set()
+
+# The DTB which contains the full image information
+main_dtb = None
+
+def GetFdt(fname):
+ """Get the Fdt object for a particular device-tree filename
+
+ Binman keeps track of at least one device-tree file called u-boot.dtb but
+ can also have others (e.g. for SPL). This function looks up the given
+ filename and returns the associated Fdt object.
+
+ Args:
+ fname: Filename to look up (e.g. 'u-boot.dtb').
+
+ Returns:
+ Fdt object associated with the filename
+ """
+ return fdt_files[fname]
+
+def GetFdtPath(fname):
+ """Get the full pathname of a particular Fdt object
+
+ Similar to GetFdt() but returns the pathname associated with the Fdt.
+
+ Args:
+ fname: Filename to look up (e.g. 'u-boot.dtb').
+
+ Returns:
+ Full path name to the associated Fdt
+ """
+ return fdt_files[fname]._fname
+
+def GetFdtContents(fname):
+ """Looks up the FDT pathname and contents
+
+ This is used to obtain the Fdt pathname and contents when needed by an
+ entry. It supports a 'fake' dtb, allowing tests to substitute test data for
+ the real dtb.
+
+ Args:
+ fname: Filename to look up (e.g. 'u-boot.dtb').
+
+ Returns:
+ tuple:
+ pathname to Fdt
+ Fdt data (as bytes)
+ """
+ if fname in fdt_files and not use_fake_dtb:
+ pathname = GetFdtPath(fname)
+ data = GetFdt(fname).GetContents()
+ else:
+ pathname = tools.GetInputFilename(fname)
+ data = tools.ReadFile(pathname)
+ return pathname, data
+
+def SetEntryArgs(args):
+ """Set the value of the entry args
+
+ This sets up the entry_args dict which is used to supply entry arguments to
+ entries.
+
+ Args:
+ args: List of entry arguments, each in the format "name=value"
+ """
+ global entry_args
+
+ entry_args = {}
+ if args:
+ for arg in args:
+ m = re.match('([^=]*)=(.*)', arg)
+ if not m:
+ raise ValueError("Invalid entry arguemnt '%s'" % arg)
+ entry_args[m.group(1)] = m.group(2)
+
+def GetEntryArg(name):
+ """Get the value of an entry argument
+
+ Args:
+ name: Name of argument to retrieve
+
+ Returns:
+ String value of argument
+ """
+ return entry_args.get(name)
+
+def Prepare(images, dtb):
+ """Get device tree files ready for use
+
+ This sets up a set of device tree files that can be retrieved by GetFdts().
+ At present there is only one, that for U-Boot proper.
+
+ Args:
+ images: List of images being used
+ dtb: Main dtb
+ """
+ global fdt_set, fdt_subset, fdt_files, main_dtb
+ # Import these here in case libfdt.py is not available, in which case
+ # the above help option still works.
+ import fdt
+ import fdt_util
+
+ # If we are updating the DTBs we need to put these updated versions
+ # where Entry_blob_dtb can find them. We can ignore 'u-boot.dtb'
+ # since it is assumed to be the one passed in with options.dt, and
+ # was handled just above.
+ main_dtb = dtb
+ fdt_files.clear()
+ fdt_files['u-boot.dtb'] = dtb
+ fdt_subset = Set()
+ if not use_fake_dtb:
+ for image in images.values():
+ fdt_subset.update(image.GetFdtSet())
+ fdt_subset.discard('u-boot.dtb')
+ for other_fname in fdt_subset:
+ infile = tools.GetInputFilename(other_fname)
+ other_fname_dtb = fdt_util.EnsureCompiled(infile)
+ out_fname = tools.GetOutputFilename('%s.out' %
+ os.path.split(other_fname)[1])
+ tools.WriteFile(out_fname, tools.ReadFile(other_fname_dtb))
+ other_dtb = fdt.FdtScan(out_fname)
+ fdt_files[other_fname] = other_dtb
+
+def GetFdts():
+ """Yield all device tree files being used by binman
+
+ Yields:
+ Device trees being used (U-Boot proper, SPL, TPL)
+ """
+ yield main_dtb
+ for other_fname in fdt_subset:
+ yield fdt_files[other_fname]
+
+def GetUpdateNodes(node):
+ """Yield all the nodes that need to be updated in all device trees
+
+ The property referenced by this node is added to any device trees which
+ have the given node. Due to removable of unwanted notes, SPL and TPL may
+ not have this node.
+
+ Args:
+ node: Node object in the main device tree to look up
+
+ Yields:
+ Node objects in each device tree that is in use (U-Boot proper, which
+ is node, SPL and TPL)
+ """
+ yield node
+ for dtb in fdt_files.values():
+ if dtb != node.GetFdt():
+ other_node = dtb.GetNode(node.path)
+ if other_node:
+ yield other_node
+
+def AddZeroProp(node, prop):
+ """Add a new property to affected device trees with an integer value of 0.
+
+ Args:
+ prop_name: Name of property
+ """
+ for n in GetUpdateNodes(node):
+ n.AddZeroProp(prop)
+
+def AddSubnode(node, name):
+ """Add a new subnode to a node in affected device trees
+
+ Args:
+ node: Node to add to
+ name: name of node to add
+
+ Returns:
+ New subnode that was created in main tree
+ """
+ first = None
+ for n in GetUpdateNodes(node):
+ subnode = n.AddSubnode(name)
+ if not first:
+ first = subnode
+ return first
+
+def AddString(node, prop, value):
+ """Add a new string property to affected device trees
+
+ Args:
+ prop_name: Name of property
+ value: String value (which will be \0-terminated in the DT)
+ """
+ for n in GetUpdateNodes(node):
+ n.AddString(prop, value)
+
+def SetInt(node, prop, value):
+ """Update an integer property in affected device trees with an integer value
+
+ This is not allowed to change the size of the FDT.
+
+ Args:
+ prop_name: Name of property
+ """
+ for n in GetUpdateNodes(node):
+ n.SetInt(prop, value)
+
+def CheckAddHashProp(node):
+ hash_node = node.FindNode('hash')
+ if hash_node:
+ algo = hash_node.props.get('algo')
+ if not algo:
+ return "Missing 'algo' property for hash node"
+ if algo.value == 'sha256':
+ size = 32
+ else:
+ return "Unknown hash algorithm '%s'" % algo
+ for n in GetUpdateNodes(hash_node):
+ n.AddEmptyProp('value', size)
+
+def CheckSetHashValue(node, get_data_func):
+ hash_node = node.FindNode('hash')
+ if hash_node:
+ algo = hash_node.props.get('algo').value
+ if algo == 'sha256':
+ m = hashlib.sha256()
+ m.update(get_data_func())
+ data = m.digest()
+ for n in GetUpdateNodes(hash_node):
+ n.SetData('value', data)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <32>;
+ sort-by-offset;
+ end-at-4gb;
+ skip-at-start = <0xffffffe0>;
+ u-boot {
+ offset = <0xffffffe0>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+ fill {
+ size = <0>;
+ fill-byte = [ff];
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ powerpc-mpc85xx-bootpg-resetvec {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ x86-start16-tpl {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ section {
+ u-boot-dtb {
+ };
+ };
+ u-boot-spl-dtb {
+ };
+ u-boot-tpl-dtb {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ blob {
+ filename = "compress";
+ compress = "lz4";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ files {
+ pattern = "files/*.dat";
+ compress = "none";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ files {
+ pattern = "files/*.dat";
+ compress = "lz4";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ files {
+ pattern = "files/*.none";
+ compress = "none";
+ require-matches;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ files {
+ compress = "none";
+ require-matches;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ size = <40>;
+ fill {
+ expand-size;
+ fill-byte = [61];
+ size = <0>;
+ };
+ u-boot {
+ offset = <8>;
+ };
+ section {
+ expand-size;
+ pad-byte = <0x62>;
+ intel-mrc {
+ };
+ };
+ u-boot2 {
+ type = "u-boot";
+ offset = <16>;
+ };
+ section2 {
+ type = "section";
+ fill {
+ expand-size;
+ fill-byte = [63];
+ size = <0>;
+ };
+ u-boot {
+ offset = <8>;
+ };
+ };
+ fill2 {
+ type = "fill";
+ expand-size;
+ fill-byte = [64];
+ size = <0>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ _testing {
+ expand-size;
+ return-contents-once;
+ };
+ u-boot {
+ offset = <8>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ u-boot {
+ hash {
+ algo = "sha256";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ u-boot {
+ hash {
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ u-boot {
+ hash {
+ algo = "invalid";
+ };
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ sort-by-offset;
+ end-at-4gb;
+ size = <0x200>;
+ u-boot-tpl-with-ucode-ptr {
+ };
+
+ u-boot-tpl-dtb-with-ucode {
+ };
+
+ u-boot-ucode {
+ };
+ };
+
+ microcode {
+ update@0 {
+ data = <0x12345678 0x12345679>;
+ };
+ update@1 {
+ data = <0xabcd0000 0x78235609>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ end-at-4gb;
+ size = <0x100>;
+ pad-byte = <0x61>;
+ u-boot {
+ };
+ intel-mrc {
+ };
+ fmap {
+ offset = <0xffffff20>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ end-at-4gb;
+ size = <0x100>;
+ u-boot {
+ };
+ section {
+ pad-byte = <0x62>;
+ intel-mrc {
+ };
+ fmap {
+ offset = <0x20>;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot-elf {
+ };
+ u-boot-spl-elf {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot-elf {
+ strip;
+ };
+ u-boot-spl-elf {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ section {
+ u-boot {
+ };
+ fill {
+ size = <0x10>;
+ fill-byte = [61];
+ };
+ hash {
+ algo = "sha256";
+ };
+ };
+ };
+};
--- /dev/null
+sorry I'm late
--- /dev/null
+Oh, don't bother apologising, I'm sorry you're alive
--- /dev/null
+this does not have a .dat extenion
"""
cmd = [self.gnu_make] + list(args)
result = command.RunPipe([cmd], capture=True, capture_stderr=True,
- cwd=cwd, raise_on_error=False, **kwargs)
+ cwd=cwd, raise_on_error=False, infile='/dev/null', **kwargs)
if self.verbose_build:
result.stdout = '%s\n' % (' '.join(cmd)) + result.stdout
result.combined = '%s\n' % (' '.join(cmd)) + result.combined
self.name = name
self.value = None
self.bytes = str(bytes)
+ self.dirty = False
if not bytes:
self.type = TYPE_BOOL
self.value = True
if type == TYPE_BYTE:
return chr(0)
elif type == TYPE_INT:
- return struct.pack('<I', 0);
+ return struct.pack('>I', 0);
elif type == TYPE_STRING:
return ''
else:
self._node._fdt.CheckCache()
return self._node._fdt.GetStructOffset(self._offset)
+ def SetInt(self, val):
+ """Set the integer value of the property
+
+ The device tree is marked dirty so that the value will be written to
+ the block on the next sync.
+
+ Args:
+ val: Integer value (32-bit, single cell)
+ """
+ self.bytes = struct.pack('>I', val);
+ self.value = val
+ self.type = TYPE_INT
+ self.dirty = True
+
+ def SetData(self, bytes):
+ """Set the value of a property as bytes
+
+ Args:
+ bytes: New property value to set
+ """
+ self.bytes = str(bytes)
+ self.type, self.value = self.BytesToValue(bytes)
+ self.dirty = True
+
+ def Sync(self, auto_resize=False):
+ """Sync property changes back to the device tree
+
+ This updates the device tree blob with any changes to this property
+ since the last sync.
+
+ Args:
+ auto_resize: Resize the device tree automatically if it does not
+ have enough space for the update
+
+ Raises:
+ FdtException if auto_resize is False and there is not enough space
+ """
+ if self._offset is None or self.dirty:
+ node = self._node
+ fdt_obj = node._fdt._fdt_obj
+ if auto_resize:
+ while fdt_obj.setprop(node.Offset(), self.name, self.bytes,
+ (libfdt.NOSPACE,)) == -libfdt.NOSPACE:
+ fdt_obj.resize(fdt_obj.totalsize() + 1024)
+ fdt_obj.setprop(node.Offset(), self.name, self.bytes)
+ else:
+ fdt_obj.setprop(node.Offset(), self.name, self.bytes)
+
+
class Node:
"""A device tree node
Args:
prop_name: Name of property
"""
- fdt_obj = self._fdt._fdt_obj
- if fdt_obj.setprop_u32(self.Offset(), prop_name, 0,
- (libfdt.NOSPACE,)) == -libfdt.NOSPACE:
- fdt_obj.resize(fdt_obj.totalsize() + 1024)
- fdt_obj.setprop_u32(self.Offset(), prop_name, 0)
- self.props[prop_name] = Prop(self, -1, prop_name, '\0' * 4)
- self._fdt.Invalidate()
+ self.props[prop_name] = Prop(self, None, prop_name, '\0' * 4)
+
+ def AddEmptyProp(self, prop_name, len):
+ """Add a property with a fixed data size, for filling in later
+
+ The device tree is marked dirty so that the value will be written to
+ the blob on the next sync.
+
+ Args:
+ prop_name: Name of property
+ len: Length of data in property
+ """
+ value = chr(0) * len
+ self.props[prop_name] = Prop(self, None, prop_name, value)
def SetInt(self, prop_name, val):
"""Update an integer property int the device tree.
This is not allowed to change the size of the FDT.
+ The device tree is marked dirty so that the value will be written to
+ the blob on the next sync.
+
Args:
prop_name: Name of property
val: Value to set
"""
- fdt_obj = self._fdt._fdt_obj
- fdt_obj.setprop_u32(self.Offset(), prop_name, val)
+ self.props[prop_name].SetInt(val)
+
+ def SetData(self, prop_name, val):
+ """Set the data value of a property
+
+ The device tree is marked dirty so that the value will be written to
+ the blob on the next sync.
+
+ Args:
+ prop_name: Name of property to set
+ val: Data value to set
+ """
+ self.props[prop_name].SetData(val)
+
+ def SetString(self, prop_name, val):
+ """Set the string value of a property
+
+ The device tree is marked dirty so that the value will be written to
+ the blob on the next sync.
+
+ Args:
+ prop_name: Name of property to set
+ val: String value to set (will be \0-terminated in DT)
+ """
+ self.props[prop_name].SetData(val + chr(0))
+
+ def AddString(self, prop_name, val):
+ """Add a new string property to a node
+
+ The device tree is marked dirty so that the value will be written to
+ the blob on the next sync.
+
+ Args:
+ prop_name: Name of property to add
+ val: String value of property
+ """
+ self.props[prop_name] = Prop(self, None, prop_name, val + chr(0))
+
+ def AddSubnode(self, name):
+ """Add a new subnode to the node
+
+ Args:
+ name: name of node to add
+
+ Returns:
+ New subnode that was created
+ """
+ path = self.path + '/' + name
+ subnode = Node(self._fdt, self, None, name, path)
+ self.subnodes.append(subnode)
+ return subnode
+
+ def Sync(self, auto_resize=False):
+ """Sync node changes back to the device tree
+
+ This updates the device tree blob with any changes to this node and its
+ subnodes since the last sync.
+
+ Args:
+ auto_resize: Resize the device tree automatically if it does not
+ have enough space for the update
+
+ Raises:
+ FdtException if auto_resize is False and there is not enough space
+ """
+ if self._offset is None:
+ # The subnode doesn't exist yet, so add it
+ fdt_obj = self._fdt._fdt_obj
+ if auto_resize:
+ while True:
+ offset = fdt_obj.add_subnode(self.parent._offset, self.name,
+ (libfdt.NOSPACE,))
+ if offset != -libfdt.NOSPACE:
+ break
+ fdt_obj.resize(fdt_obj.totalsize() + 1024)
+ else:
+ offset = fdt_obj.add_subnode(self.parent._offset, self.name)
+ self._offset = offset
+
+ # Sync subnodes in reverse so that we don't disturb node offsets for
+ # nodes that are earlier in the DT. This avoids an O(n^2) rescan of
+ # node offsets.
+ for node in reversed(self.subnodes):
+ node.Sync(auto_resize)
+
+ # Sync properties now, whose offsets should not have been disturbed.
+ # We do this after subnodes, since this disturbs the offsets of these
+ # properties.
+ prop_list = sorted(self.props.values(), key=lambda prop: prop._offset,
+ reverse=True)
+ for prop in prop_list:
+ prop.Sync(auto_resize)
class Fdt:
with open(self._fname) as fd:
self._fdt_obj = libfdt.Fdt(fd.read())
+ @staticmethod
+ def FromData(data):
+ """Create a new Fdt object from the given data
+
+ Args:
+ data: Device-tree data blob
+
+ Returns:
+ Fdt object containing the data
+ """
+ fdt = Fdt(None)
+ fdt._fdt_obj = libfdt.Fdt(bytearray(data))
+ return fdt
+
def LookupPhandle(self, phandle):
"""Look up a phandle
with open(self._fname, 'wb') as fd:
fd.write(self._fdt_obj.as_bytearray())
+ def Sync(self, auto_resize=False):
+ """Make sure any DT changes are written to the blob
+
+ Args:
+ auto_resize: Resize the device tree automatically if it does not
+ have enough space for the update
+
+ Raises:
+ FdtException if auto_resize is False and there is not enough space
+ """
+ self._root.Sync(auto_resize)
+ self.Invalidate()
+
def Pack(self):
"""Pack the device tree down to its minimum size
self.node.AddZeroProp('one')
self.node.AddZeroProp('two')
self.node.AddZeroProp('three')
+ self.dtb.Sync(auto_resize=True)
# Updating existing properties should be OK, since the device-tree size
# does not change
self.node.SetInt('one', 1)
self.node.SetInt('two', 2)
self.node.SetInt('three', 3)
+ self.dtb.Sync(auto_resize=False)
# This should fail since it would need to increase the device-tree size
+ self.node.AddZeroProp('four')
with self.assertRaises(libfdt.FdtException) as e:
- self.node.SetInt('four', 4)
+ self.dtb.Sync(auto_resize=False)
self.assertIn('FDT_ERR_NOSPACE', str(e.exception))
+ self.dtb.Sync(auto_resize=True)
+
+ def testAddNode(self):
+ self.fdt.pack()
+ self.node.AddSubnode('subnode')
+ with self.assertRaises(libfdt.FdtException) as e:
+ self.dtb.Sync(auto_resize=False)
+ self.assertIn('FDT_ERR_NOSPACE', str(e.exception))
+
+ self.dtb.Sync(auto_resize=True)
+ offset = self.fdt.path_offset('/spl-test/subnode')
+ self.assertTrue(offset > 0)
+
+ def testAddMore(self):
+ """Test various other methods for adding and setting properties"""
+ self.node.AddZeroProp('one')
+ self.dtb.Sync(auto_resize=True)
+ data = self.fdt.getprop(self.node.Offset(), 'one')
+ self.assertEqual(0, fdt32_to_cpu(data))
+
+ self.node.SetInt('one', 1)
+ self.dtb.Sync(auto_resize=False)
+ data = self.fdt.getprop(self.node.Offset(), 'one')
+ self.assertEqual(1, fdt32_to_cpu(data))
+
+ val = '123' + chr(0) + '456'
+ self.node.AddString('string', val)
+ self.dtb.Sync(auto_resize=True)
+ data = self.fdt.getprop(self.node.Offset(), 'string')
+ self.assertEqual(val + '\0', data)
+
+ self.fdt.pack()
+ self.node.SetString('string', val + 'x')
+ with self.assertRaises(libfdt.FdtException) as e:
+ self.dtb.Sync(auto_resize=False)
+ self.assertIn('FDT_ERR_NOSPACE', str(e.exception))
+ self.node.SetString('string', val[:-1])
+
+ prop = self.node.props['string']
+ prop.SetData(val)
+ self.dtb.Sync(auto_resize=False)
+ data = self.fdt.getprop(self.node.Offset(), 'string')
+ self.assertEqual(val, data)
+
+ self.node.AddEmptyProp('empty', 5)
+ self.dtb.Sync(auto_resize=True)
+ prop = self.node.props['empty']
+ prop.SetData(val)
+ self.dtb.Sync(auto_resize=False)
+ data = self.fdt.getprop(self.node.Offset(), 'empty')
+ self.assertEqual(val, data)
+
+ self.node.SetData('empty', '123')
+ self.assertEqual('123', prop.bytes)
+
+ def testFromData(self):
+ dtb2 = fdt.Fdt.FromData(self.dtb.GetContents())
+ self.assertEqual(dtb2.GetContents(), self.dtb.GetContents())
+
+ self.node.AddEmptyProp('empty', 5)
+ self.dtb.Sync(auto_resize=True)
+ self.assertTrue(dtb2.GetContents() != self.dtb.GetContents())
class TestFdtUtil(unittest.TestCase):
#
import command
+import glob
import os
import shutil
import tempfile
# Search paths to use for Filename(), used to find files
search_paths = []
+# Tools and the packages that contain them, on debian
+packages = {
+ 'lz4': 'liblz4-tool',
+ }
def PrepareOutputDir(dirname, preserve=False):
"""Select an output directory, ensuring it exists.
raise ValueError("Filename '%s' not found in input path (%s) (cwd='%s')" %
(fname, ','.join(indir), os.getcwd()))
+def GetInputFilenameGlob(pattern):
+ """Return a list of filenames for use as input.
+
+ Args:
+ pattern: Filename pattern to search for
+
+ Returns:
+ A list of matching files in all input directories
+ """
+ if not indir:
+ return glob.glob(fname)
+ files = []
+ for dirname in indir:
+ pathname = os.path.join(dirname, pattern)
+ files += glob.glob(pathname)
+ return sorted(files)
+
def Align(pos, align):
if align:
mask = align - 1
def NotPowerOfTwo(num):
return num and (num & (num - 1))
+def PathHasFile(fname):
+ """Check if a given filename is in the PATH
+
+ Args:
+ fname: Filename to check
+
+ Returns:
+ True if found, False if not
+ """
+ for dir in os.environ['PATH'].split(':'):
+ if os.path.exists(os.path.join(dir, fname)):
+ return True
+ return False
+
def Run(name, *args):
- command.Run(name, *args, cwd=outdir)
+ try:
+ return command.Run(name, *args, cwd=outdir, capture=True)
+ except:
+ if not PathHasFile(name):
+ msg = "Plesae install tool '%s'" % name
+ package = packages.get(name)
+ if package:
+ msg += " (e.g. from package '%s')" % package
+ raise ValueError(msg)
+ raise
def Filename(fname):
"""Resolve a file path to an absolute path.
projects / project / bcm63xx / u-boot.git / commitdiff