Neoverse N1: Forces cacheable atomic to near

This patch forces all cacheable atomic instructions to be near, which
improves performance in highly contended parallelized use-cases.

Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index 908993e450b9eba592aab35ff8e652ee1936035f..ed5f136dd97260c2f3f4bcf5f3e24051b301559c 100644 (file)
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -13,10 +13,9 @@
 #define NEOVERSE_N1_MIDR               U(0x410fd0c0)
 
 /*******************************************************************************
- * CPU Extended Control register specific definitions.
+ * CPU Power Control register specific definitions.
  ******************************************************************************/
 #define NEOVERSE_N1_CPUPWRCTLR_EL1     S3_0_C15_C2_7
-#define NEOVERSE_N1_CPUECTLR_EL1       S3_0_C15_C1_4
 
 /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */
 #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1)
@@ -26,6 +25,18 @@
 #define NEOVERSE_N1_AMU_NR_COUNTERS    U(5)
 #define NEOVERSE_N1_AMU_GROUP0_MASK    U(0x1f)
 
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N1_CPUECTLR_EL1       S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N1_CPUACTLR2_EL1      S3_0_C15_C1_1
+
+#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2        (ULL(1) << 2)
+
 /* Instruction patching registers */
 #define CPUPSELR_EL3   S3_6_C15_C8_0
 #define CPUPCR_EL3     S3_6_C15_C8_1

diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 060c625d41172b2ead9581f74fe248c37647cbba..ce63899a7e50c062855bfa0edcf1b60c5fdd23e7 100644 (file)
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -50,6 +50,12 @@ func neoverse_n1_reset_func
        /* Disables speculative loads */
        msr     SSBS, xzr
 
+       /* Forces all cacheable atomic instructions to be near */
+       mrs     x0, NEOVERSE_N1_CPUACTLR2_EL1
+       orr     x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
+       msr     NEOVERSE_N1_CPUACTLR2_EL1, x0
+       isb
+
        bl      cpu_get_rev_var
        mov     x18, x0