diff options
| author | Markus Stockhausen | 2025-06-22 07:53:08 +0000 |
|---|---|---|
| committer | Robert Marko | 2025-06-22 21:12:02 +0000 |
| commit | 83880cd01ee4db9cdf5c63d9c7fa1973366e4acc (patch) | |
| tree | f2be38cd64bbca530a6d3111ed3ab58abdb3ee0f | |
| parent | ee46517a638263310999e38b74c2bfd64daf98dc (diff) | |
| download | openwrt-83880cd01ee4db9cdf5c63d9c7fa1973366e4acc.tar.gz | |
realtek: Use Otto timer on RTL931x
Until now the timer management on the RTL931x devices depends
on the MIPS default timer. Looking at the clock progress on
these devices one can see that it is totally off. It is running
at half the required speed (e.g. if 1 minute passes the date
command shows that according to the timers only 30 seconds have
elapsed). This is a mix from wrong DTS and bad startup code.
This is not only a cosmetic issue but has effects on every
delay operation inside the kernel. Switch RTL931x to the proven
Otto timer.
Tested on LGS352C based on RTL9311.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19205
Signed-off-by: Robert Marko <robimarko@gmail.com>
| -rw-r--r-- | target/linux/realtek/dts/rtl931x.dtsi | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/target/linux/realtek/dts/rtl931x.dtsi b/target/linux/realtek/dts/rtl931x.dtsi index c7feef4724..df85112464 100644 --- a/target/linux/realtek/dts/rtl931x.dtsi +++ b/target/linux/realtek/dts/rtl931x.dtsi @@ -89,12 +89,6 @@ * controller & should be probed first. */ interrupt-parent = <&cpuintc>; - - timer { - compatible = "mti,gic-timer"; - interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; - clocks = <&cpuclock>; - }; }; soc: soc { @@ -141,6 +135,18 @@ interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; }; + timer0: timer@3200 { + compatible = "realtek,rtl931x-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>, <0x3250 0x10>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&lx_clk>; + }; + uart0: uart@2000 { compatible = "ns16550a"; reg = <0x2000 0x100>; |