airoha: an7581: add pending patch to fix PCI

Add pending patch to fix PCIe missing register.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
(cherry picked from commit 77329b7d8d870897d85270a4e806ec0d04396685)

1 files changed, 83 insertions, 0 deletions

diff --git a/target/linux/airoha/patches-6.6/112-PCI-mediatek-gen3-configure-PBUS_CSR-registers-for-E.patch b/target/linux/airoha/patches-6.6/112-PCI-mediatek-gen3-configure-PBUS_CSR-registers-for-E.patch
new file mode 100644
index 0000000000..d896e1aee3
--- /dev/null
+++ b/target/linux/airoha/patches-6.6/112-PCI-mediatek-gen3-configure-PBUS_CSR-registers-for-E.patch
@@ -0,0 +1,83 @@
+From 2285d3b428c7d8f1c4fda2fb995e7e46a05350e0 Mon Sep 17 00:00:00 2001
+Message-ID: <2285d3b428c7d8f1c4fda2fb995e7e46a05350e0.1736324542.git.lorenzo@kernel.org>
+In-Reply-To: <0c0ae72f5c84c5a29495337b254ac3cc2d5c16bb.1736324541.git.lorenzo@kernel.org>
+References: <0c0ae72f5c84c5a29495337b254ac3cc2d5c16bb.1736324541.git.lorenzo@kernel.org>
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 3 Sep 2024 23:14:02 +0200
+Subject: [PATCH 2/2] PCI: mediatek-gen3: configure PBUS_CSR registers for
+ EN7581 SoC
+
+Configure PBus base address and address mask in order to allow the hw
+detecting if a given address is on PCIE0, PCIE1 or PCIE2.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ drivers/pci/controller/pcie-mediatek-gen3.c | 29 ++++++++++++++++++++-
+ 1 file changed, 28 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/controller/pcie-mediatek-gen3.c
++++ b/drivers/pci/controller/pcie-mediatek-gen3.c
+@@ -15,6 +15,7 @@
+ #include <linux/irqchip/chained_irq.h>
+ #include <linux/irqdomain.h>
+ #include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/msi.h>
+ #include <linux/of_device.h>
+@@ -24,6 +25,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/pm_domain.h>
+ #include <linux/pm_runtime.h>
++#include <linux/regmap.h>
+ #include <linux/reset.h>
+ 
+ #include "../pci.h"
+@@ -120,6 +122,13 @@
+ 
+ #define MAX_NUM_PHY_RESETS		3
+ 
++#define PCIE_EN7581_PBUS_ADDR(_n)	(0x00 + ((_n) << 3))
++#define PCIE_EN7581_PBUS_ADDR_MASK(_n)	(0x04 + ((_n) << 3))
++#define PCIE_EN7581_PBUS_BASE_ADDR(_n)	\
++	((_n) == 2 ? 0x28000000 :	\
++	 (_n) == 1 ? 0x24000000 : 0x20000000)
++#define PCIE_EN7581_PBUS_BASE_ADDR_MASK	GENMASK(31, 26)
++
+ /* Time in ms needed to complete PCIe reset on EN7581 SoC */
+ #define PCIE_EN7581_RESET_TIME_MS	100
+ 
+@@ -871,7 +880,8 @@ static int mtk_pcie_parse_port(struct mt
+ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
+ {
+ 	struct device *dev = pcie->dev;
+-	int err;
++	struct regmap *map;
++	int err, slot;
+ 	u32 val;
+ 
+ 	/*
+@@ -880,6 +890,23 @@ static int mtk_pcie_en7581_power_up(stru
+ 	 */
+ 	mdelay(PCIE_EN7581_RESET_TIME_MS);
+ 
++	map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr");
++	if (IS_ERR(map))
++		return PTR_ERR(map);
++
++	/*
++	 * Configure PBus base address and address mask in order to allow the
++	 * hw detecting if a given address is on PCIE0, PCIE1 or PCIE2.
++	 */
++	slot = of_get_pci_domain_nr(dev->of_node);
++	if (slot < 0)
++		return slot;
++
++	regmap_write(map, PCIE_EN7581_PBUS_ADDR(slot),
++		     PCIE_EN7581_PBUS_BASE_ADDR(slot));
++	regmap_write(map, PCIE_EN7581_PBUS_ADDR_MASK(slot),
++		     PCIE_EN7581_PBUS_BASE_ADDR_MASK);
++
+ 	err = phy_init(pcie->phy);
+ 	if (err) {
+ 		dev_err(dev, "failed to initialize PHY\n");