+++ /dev/null
-From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001
-From: Dragan Simic <dsimic@manjaro.org>
-Date: Tue, 12 Dec 2023 09:01:39 +0100
-Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for
- RK3566 boards
-
-Add ethernet0 alias to the board dts files for a few supported RK3566 boards
-that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM
-dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to
-the dependent board dts files, which actually enable the GMAC.
-
-Signed-off-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 +
- 1 files changed, 1 insertions(+), 0 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -14,6 +14,7 @@
- compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
-
- aliases {
-+ ethernet0 = &gmac1;
- mmc1 = &sdmmc0;
- };
-
+++ /dev/null
-From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001
-From: Tim Lunn <tim@feathertop.org>
-Date: Wed, 14 Feb 2024 15:07:30 +1100
-Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board
-
-Adjust compatible string to match the board vendor of Sinovoip
-
-Signed-off-by: Tim Lunn <tim@feathertop.org>
-Reviewed-by: Dragan Simic <dsimic@manjaro.org>
-Acked-by: Conor Dooley <conor.dooley@microchip.com>
-Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
-@@ -13,7 +13,7 @@
-
- / {
- model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
-- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
-+ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568";
-
- aliases {
- ethernet0 = &gmac0;
+++ /dev/null
-From 8612169a05c5e979af033868b7a9b177e0f9fcdf Mon Sep 17 00:00:00 2001
-From: Dragan Simic <dsimic@manjaro.org>
-Date: Sat, 9 Mar 2024 05:25:06 +0100
-Subject: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi
- for RK356x
-
-Add missing cache information to the Rockchip RK356x SoC dtsi, to allow
-the userspace, which includes lscpu(1) that uses the virtual files provided
-by the kernel under the /sys/devices/system/cpu directory, to display the
-proper RK3566 and RK3568 cache information.
-
-Adding the cache information to the RK356x SoC dtsi also makes the following
-warning message in the kernel log go away:
-
- cacheinfo: Unable to detect cache hierarchy for CPU 0
-
-The cache parameters for the RK356x dtsi were obtained and partially derived
-by hand from the cache size and layout specifications found in the following
-datasheets and technical reference manuals:
-
- - Rockchip RK3566 datasheet, version 1.1
- - Rockchip RK3568 datasheet, version 1.3
- - ARM Cortex-A55 revision r1p0 TRM, version 0100-00
- - ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02
-
-For future reference, here's a rather detailed summary of the documentation,
-which applies to both Rockchip RK3566 and RK3568 SoCs:
-
- - All caches employ the 64-byte cache line length
- - Each Cortex-A55 core has 32 KB of L1 4-way, set-associative instruction
- cache and 32 KB of L1 4-way, set-associative data cache
- - There are no L2 caches, which are per-core and private in Cortex-A55,
- because it belongs to the ARM DynamIQ IP core lineup
- - The entire SoC has 512 KB of unified L3 16-way, set-associative cache,
- which is shared among all four Cortex-A55 CPU cores
- - Cortex-A55 cores can be configured without private per-core L2 caches,
- in which case the shared L3 cache appears to them as an L2 cache; this
- is the case for the RK356x SoCs, so let's use "cache-level = <2>" to
- prevent the "huh, no L2 caches, but an L3 cache?" confusion among the
- users viewing the data presented to the userspace; another option could
- be to have additional 0 KB L2 caches defined, which may be technically
- correct, but would probably be even more confusing
-
-Helped-by: Anand Moon <linux.amoon@gmail.com>
-Tested-By: Diederik de Haas <didi.debian@cknow.org>
-Reviewed-by: Anand Moon <linux.amoon@gmail.com>
-Signed-off-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/2dee6dad8460b0c5f3b5da53cf55f735840efef1.1709957777.git.dsimic@manjaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 41 ++++++++++++++++++++++++
- 1 file changed, 41 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -57,6 +57,13 @@
- #cooling-cells = <2>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
-+ i-cache-size = <0x8000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <128>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ next-level-cache = <&l3_cache>;
- };
-
- cpu1: cpu@100 {
-@@ -66,6 +73,13 @@
- #cooling-cells = <2>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
-+ i-cache-size = <0x8000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <128>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ next-level-cache = <&l3_cache>;
- };
-
- cpu2: cpu@200 {
-@@ -75,6 +89,13 @@
- #cooling-cells = <2>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
-+ i-cache-size = <0x8000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <128>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ next-level-cache = <&l3_cache>;
- };
-
- cpu3: cpu@300 {
-@@ -84,9 +105,29 @@
- #cooling-cells = <2>;
- enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
-+ i-cache-size = <0x8000>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <128>;
-+ d-cache-size = <0x8000>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ next-level-cache = <&l3_cache>;
- };
- };
-
-+ /*
-+ * There are no private per-core L2 caches, but only the
-+ * L3 cache that appears to the CPU cores as L2 caches
-+ */
-+ l3_cache: l3-cache {
-+ compatible = "cache";
-+ cache-level = <2>;
-+ cache-unified;
-+ cache-size = <0x80000>;
-+ cache-line-size = <64>;
-+ cache-sets = <512>;
-+ };
-+
- cpu0_opp_table: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
+++ /dev/null
-From 0536fa6e6fa3e48f4ca11855b586c277be524fbe Mon Sep 17 00:00:00 2001
-From: David Wu <david.wu@rock-chips.com>
-Date: Tue, 21 May 2024 21:10:13 +0000
-Subject: [PATCH] soc: rockchip: io-domain: Add RK3308 IO voltage domains
-
-Add IO voltage domains support for the RK3308 SoC.
-
-Signed-off-by: David Wu <david.wu@rock-chips.com>
-Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20240521211029.1236094-11-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/soc/rockchip/io-domain.c | 40 ++++++++++++++++++++++++++++++++
- 1 file changed, 40 insertions(+)
-
---- a/drivers/soc/rockchip/io-domain.c
-+++ b/drivers/soc/rockchip/io-domain.c
-@@ -39,6 +39,10 @@
- #define RK3288_SOC_CON2_FLASH0 BIT(7)
- #define RK3288_SOC_FLASH_SUPPLY_NUM 2
-
-+#define RK3308_SOC_CON0 0x300
-+#define RK3308_SOC_CON0_VCCIO3 BIT(8)
-+#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3
-+
- #define RK3328_SOC_CON4 0x410
- #define RK3328_SOC_CON4_VCCIO2 BIT(7)
- #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
-@@ -229,6 +233,25 @@ static void rk3288_iodomain_init(struct
- dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
- }
-
-+static void rk3308_iodomain_init(struct rockchip_iodomain *iod)
-+{
-+ int ret;
-+ u32 val;
-+
-+ /* if no vccio3 supply we should leave things alone */
-+ if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg)
-+ return;
-+
-+ /*
-+ * set vccio3 iodomain to also use this framework
-+ * instead of a special gpio.
-+ */
-+ val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
-+ ret = regmap_write(iod->grf, RK3308_SOC_CON0, val);
-+ if (ret < 0)
-+ dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n");
-+}
-+
- static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
- {
- int ret;
-@@ -376,6 +399,19 @@ static const struct rockchip_iodomain_so
- .init = rk3288_iodomain_init,
- };
-
-+static const struct rockchip_iodomain_soc_data soc_data_rk3308 = {
-+ .grf_offset = 0x300,
-+ .supply_names = {
-+ "vccio0",
-+ "vccio1",
-+ "vccio2",
-+ "vccio3",
-+ "vccio4",
-+ "vccio5",
-+ },
-+ .init = rk3308_iodomain_init,
-+};
-+
- static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
- .grf_offset = 0x410,
- .supply_names = {
-@@ -529,6 +565,10 @@ static const struct of_device_id rockchi
- .data = &soc_data_rk3288
- },
- {
-+ .compatible = "rockchip,rk3308-io-voltage-domain",
-+ .data = &soc_data_rk3308
-+ },
-+ {
- .compatible = "rockchip,rk3328-io-voltage-domain",
- .data = &soc_data_rk3328
- },
+++ /dev/null
-From d1829ba469d5743734e37d59fece73e3668ab084 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Tue, 21 May 2024 21:10:14 +0000
-Subject: [PATCH] arm64: dts: rockchip: Add rk3308 IO voltage domains
-
-Add a disabled RK3308 IO voltage domains node to SoC DT.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20240521211029.1236094-12-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
-@@ -168,6 +168,11 @@
- compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff000000 0x0 0x08000>;
-
-+ io_domains: io-domains {
-+ compatible = "rockchip,rk3308-io-voltage-domain";
-+ status = "disabled";
-+ };
-+
- reboot-mode {
- compatible = "syscon-reboot-mode";
- offset = <0x500>;
+++ /dev/null
-From c45de75d7a9ab44a15dedc7a121d6371d6891301 Mon Sep 17 00:00:00 2001
-From: Trevor Woerner <twoerner@gmail.com>
-Date: Mon, 20 Nov 2023 11:22:32 -0500
-Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s
-
-Add names to the pins of the general-purpose expansion header as given in the
-Radxa GPIO page[1] following the conventions in the kernel documentation[2] to
-make it easier for users to correlate the pins with functions when using
-utilities such as gpioinfo.
-
-[1] https://wiki.radxa.com/RockpiS/hardware/gpio
-[2] Documentation/devicetree/bindings/gpio/gpio.txt
-
-Signed-off-by: Trevor Woerner <twoerner@gmail.com>
-Link: https://lore.kernel.org/r/20231120162232.27653-1-twoerner@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 58 +++++++++++++++++++
- 1 file changed, 58 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
-@@ -315,3 +315,61 @@
- &wdt {
- status = "okay";
- };
-+
-+&gpio0 {
-+ gpio-line-names =
-+ /* GPIO0_A0 - A7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO0_B0 - B7 */
-+ "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]",
-+ "", "", "header1-pin11 [GPIO0_B7]",
-+ /* GPIO0_C0 - C7 */
-+ "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "",
-+ "", "", "",
-+ /* GPIO0_D0 - D8 */
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&gpio1 {
-+ gpio-line-names =
-+ /* GPIO1_A0 - A7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO1_B0 - B7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO1_C0 - C7 */
-+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
-+ "header1-pin19 [GPIO1_C7]",
-+ /* GPIO1_D0 - D8 */
-+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "",
-+ "", "", "";
-+};
-+
-+&gpio2 {
-+ gpio-line-names =
-+ /* GPIO2_A0 - A7 */
-+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "",
-+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
-+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
-+ /* GPIO2_B0 - B7 */
-+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
-+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
-+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
-+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
-+ /* GPIO2_C0 - C7 */
-+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
-+ /* GPIO2_D0 - D8 */
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&gpio3 {
-+ gpio-line-names =
-+ /* GPIO3_A0 - A7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO3_B0 - B7 */
-+ "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]",
-+ "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "",
-+ /* GPIO3_C0 - C7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO3_D0 - D8 */
-+ "", "", "", "", "", "", "", "";
-+};
+++ /dev/null
-From 085021cc825ed90a6ddc4406f608fb8a85745f81 Mon Sep 17 00:00:00 2001
-From: Trevor Woerner <twoerner@gmail.com>
-Date: Tue, 19 Dec 2023 12:38:13 -0500
-Subject: [PATCH] arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names
- cleanup
-
-Perform the following cleanups on a previous patch:
-- indent lines after "gpio-line-names"
-- fix D0-D8 -> D0-D7
-- sort phandle references
-
-Fixes: c45de75d7a9a ("arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s")
-Signed-off-by: Trevor Woerner <twoerner@gmail.com>
-Link: https://lore.kernel.org/r/20231219173814.1569-1-twoerner@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3308-rock-pi-s.dts | 120 +++++++++---------
- 1 file changed, 62 insertions(+), 58 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
-@@ -166,6 +166,68 @@
- };
- };
-
-+&gpio0 {
-+ gpio-line-names =
-+ /* GPIO0_A0 - A7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO0_B0 - B7 */
-+ "", "", "", "header1-pin3 [GPIO0_B3]",
-+ "header1-pin5 [GPIO0_B4]", "", "",
-+ "header1-pin11 [GPIO0_B7]",
-+ /* GPIO0_C0 - C7 */
-+ "header1-pin13 [GPIO0_C0]",
-+ "header1-pin15 [GPIO0_C1]", "", "", "",
-+ "", "", "",
-+ /* GPIO0_D0 - D7 */
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&gpio1 {
-+ gpio-line-names =
-+ /* GPIO1_A0 - A7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO1_B0 - B7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO1_C0 - C7 */
-+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
-+ "header1-pin19 [GPIO1_C7]",
-+ /* GPIO1_D0 - D7 */
-+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]",
-+ "", "", "", "", "", "";
-+};
-+
-+&gpio2 {
-+ gpio-line-names =
-+ /* GPIO2_A0 - A7 */
-+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]",
-+ "", "",
-+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
-+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
-+ /* GPIO2_B0 - B7 */
-+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
-+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
-+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
-+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
-+ /* GPIO2_C0 - C7 */
-+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
-+ /* GPIO2_D0 - D7 */
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&gpio3 {
-+ gpio-line-names =
-+ /* GPIO3_A0 - A7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO3_B0 - B7 */
-+ "", "", "header2-pin42 [GPIO3_B2]",
-+ "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]",
-+ "header2-pin39 [GPIO3_B5]", "", "",
-+ /* GPIO3_C0 - C7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO3_D0 - D7 */
-+ "", "", "", "", "", "", "", "";
-+};
-+
- &i2c1 {
- status = "okay";
- };
-@@ -315,61 +377,3 @@
- &wdt {
- status = "okay";
- };
--
--&gpio0 {
-- gpio-line-names =
-- /* GPIO0_A0 - A7 */
-- "", "", "", "", "", "", "", "",
-- /* GPIO0_B0 - B7 */
-- "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]",
-- "", "", "header1-pin11 [GPIO0_B7]",
-- /* GPIO0_C0 - C7 */
-- "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "",
-- "", "", "",
-- /* GPIO0_D0 - D8 */
-- "", "", "", "", "", "", "", "";
--};
--
--&gpio1 {
-- gpio-line-names =
-- /* GPIO1_A0 - A7 */
-- "", "", "", "", "", "", "", "",
-- /* GPIO1_B0 - B7 */
-- "", "", "", "", "", "", "", "",
-- /* GPIO1_C0 - C7 */
-- "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
-- "header1-pin19 [GPIO1_C7]",
-- /* GPIO1_D0 - D8 */
-- "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "",
-- "", "", "";
--};
--
--&gpio2 {
-- gpio-line-names =
-- /* GPIO2_A0 - A7 */
-- "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "",
-- "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
-- "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
-- /* GPIO2_B0 - B7 */
-- "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
-- "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
-- "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
-- "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
-- /* GPIO2_C0 - C7 */
-- "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
-- /* GPIO2_D0 - D8 */
-- "", "", "", "", "", "", "", "";
--};
--
--&gpio3 {
-- gpio-line-names =
-- /* GPIO3_A0 - A7 */
-- "", "", "", "", "", "", "", "",
-- /* GPIO3_B0 - B7 */
-- "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]",
-- "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "",
-- /* GPIO3_C0 - C7 */
-- "", "", "", "", "", "", "", "",
-- /* GPIO3_D0 - D8 */
-- "", "", "", "", "", "", "", "";
--};
+++ /dev/null
-From 100b3bdee6035192f6d4a1847970fe004bb505fb Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Tue, 21 May 2024 21:10:15 +0000
-Subject: [PATCH] arm64: dts: rockchip: Add io-domains to rk3308-rock-pi-s
-
-The VCCIO4 io-domain used for WiFi/BT is using 1v8 IO signal voltage.
-
-Add io-domains node with the VCCIO supplies connected on the board.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20240521211029.1236094-13-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
-@@ -232,6 +232,16 @@
- status = "okay";
- };
-
-+&io_domains {
-+ vccio0-supply = <&vcc_io>;
-+ vccio1-supply = <&vcc_io>;
-+ vccio2-supply = <&vcc_io>;
-+ vccio3-supply = <&vcc_io>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_io>;
-+ status = "okay";
-+};
-+
- &pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&rtc_32k>;
+++ /dev/null
-From ee219017ddb50be14c60d3cbe3e51ac0b2008d40 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sun, 28 Apr 2024 20:36:18 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3C
-
-The Radxa ROCK 3C is a development board with the
-Rockchip RK3566 SoC. It has the following features:
-
-- 1/2/4GB LPDDR4
-- 1x HDMI Type A
-- 1x PCIE 2.0 slot
-- 1x FAN connector
-- 3.5mm jack with mic
-- 1GbE RTL8211F Ethernet
-- 1x USB 3.0, 3x USB 2.0
-- 40-pin expansion header
-- MicroSD card/eMMC socket
-- 16MB SPI NOR (gd25lq128d)
-- AP6256 or AIC8800 WiFi/BT
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Link: https://lore.kernel.org/r/20240428123618.72170-3-amadeus@jmu.edu.cn
-[dropped rk809-sound and not specified pmic sound properties]
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3566-rock-3c.dts | 726 ++++++++++++++++++
- 2 files changed, 727 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qu
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
-@@ -0,0 +1,726 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3566.dtsi"
-+
-+/ {
-+ model = "Radxa ROCK 3C";
-+ compatible = "radxa,rock-3c", "rockchip,rk3566";
-+
-+ aliases {
-+ ethernet0 = &gmac1;
-+ mmc0 = &sdhci;
-+ mmc1 = &sdmmc0;
-+ mmc2 = &sdmmc1;
-+ };
-+
-+ chosen: chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ gmac1_clkin: external-gmac1-clock {
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac1_clkin";
-+ #clock-cells = <0>;
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ type = "a";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ led-0 {
-+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-+ function = LED_FUNCTION_HEARTBEAT;
-+ color = <LED_COLOR_ID_BLUE>;
-+ linux,default-trigger = "heartbeat";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&user_led2>;
-+ };
-+ };
-+
-+ sdio_pwrseq: sdio-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ clocks = <&rk809 1>;
-+ clock-names = "ext_clock";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_reg_on_h>;
-+ post-power-on-delay-ms = <100>;
-+ power-off-delay-us = <5000000>;
-+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
-+ };
-+
-+ vcc5v_dcin: vcc5v-dcin-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v_dcin";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc3v3_pcie: vcc3v3-pcie-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_pwr_en>;
-+ regulator-name = "vcc3v3_pcie";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ vcc3v3_sys: vcc3v3-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v_dcin>;
-+ };
-+
-+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb30_host_en>;
-+ regulator-name = "vcc5v0_usb30_host";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
-+ regulator-name = "vcc5v0_usb_otg";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc_cam: vcc-cam-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc_cam_en>;
-+ regulator-name = "vcc_cam";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_mipi: vcc-mipi-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc_mipi_en>;
-+ regulator-name = "vcc_mipi";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&combphy2 {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gmac1 {
-+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
-+ clock_in_out = "input";
-+ phy-handle = <&rgmii_phy1>;
-+ phy-mode = "rgmii-id";
-+ phy-supply = <&vcc_3v3>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac1m1_miim
-+ &gmac1m1_tx_bus2
-+ &gmac1m1_rx_bus2
-+ &gmac1m1_rgmii_clk
-+ &gmac1m1_rgmii_bus
-+ &gmac1m1_clkinout>;
-+ status = "okay";
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu>;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ avdd-0v9-supply = <&vdda0v9_image>;
-+ avdd-1v8-supply = <&vcca1v8_image>;
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1150000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk809: pmic@20 {
-+ compatible = "rockchip,rk809";
-+ reg = <0x20>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
-+ system-power-controller;
-+ vcc1-supply = <&vcc3v3_sys>;
-+ vcc2-supply = <&vcc3v3_sys>;
-+ vcc3-supply = <&vcc3v3_sys>;
-+ vcc4-supply = <&vcc3v3_sys>;
-+ vcc5-supply = <&vcc3v3_sys>;
-+ vcc6-supply = <&vcc3v3_sys>;
-+ vcc7-supply = <&vcc3v3_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc3v3_sys>;
-+ wakeup-source;
-+ #clock-cells = <1>;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vdd_gpu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vdd_npu: DCDC_REG4 {
-+ regulator-name = "vdd_npu";
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG5 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_image: LDO_REG1 {
-+ regulator-name = "vdda0v9_image";
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca_1v8: LDO_REG7 {
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG8 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca1v8_image: LDO_REG9 {
-+ regulator-name = "vcca1v8_image";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3: SWITCH_REG1 {
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sd: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_sd";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+
-+ eeprom: eeprom@50 {
-+ compatible = "belling,bl24c16a", "atmel,24c16";
-+ reg = <0x50>;
-+ pagesize = <16>;
-+ };
-+};
-+
-+&i2s0_8ch {
-+ status = "okay";
-+};
-+
-+&i2s1_8ch {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
-+ rockchip,trcm-sync-tx-only;
-+ status = "okay";
-+};
-+
-+&mdio1 {
-+ rgmii_phy1: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <0x1>;
-+ reset-assert-us = <20000>;
-+ reset-deassert-us = <100000>;
-+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
-+ };
-+};
-+
-+&pcie2x1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_reset_h>;
-+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ bluetooth {
-+ bt_reg_on_h: bt-reg-on-h {
-+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ bt_wake_host_h: bt-wake-host-h {
-+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ bt_host_wake_h: bt-host-wake-h {
-+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ cam {
-+ vcc_cam_en: vcc_cam_en {
-+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ display {
-+ vcc_mipi_en: vcc_mipi_en {
-+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ leds {
-+ user_led2: user-led2 {
-+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie {
-+ pcie_pwr_en: pcie-pwr-en {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie_reset_h: pcie-reset-h {
-+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb {
-+ vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
-+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ wifi {
-+ wifi_host_wake_h: wifi-host-wake-h {
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wifi_reg_on_h: wifi-reg-on-h {
-+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcca1v8_pmu>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio2-supply = <&vcc_1v8>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcca1v8_pmu>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_3v3>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ mmc-hs200-1_8v;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&sdmmc0 {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+ sd-uhs-sdr50;
-+ vmmc-supply = <&vcc3v3_sys>;
-+ vqmmc-supply = <&vccio_sd>;
-+ status = "okay";
-+};
-+
-+&sdmmc1 {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ cap-sdio-irq;
-+ keep-power-in-suspend;
-+ mmc-pwrseq = <&sdio_pwrseq>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc3v3_sys>;
-+ vqmmc-supply = <&vcca1v8_pmu>;
-+ status = "okay";
-+};
-+
-+&sfc {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ flash@0 {
-+ compatible = "jedec,spi-nor";
-+ reg = <0x0>;
-+ spi-max-frequency = <120000000>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <1>;
-+ };
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy0_host {
-+ phy-supply = <&vcc5v0_usb30_host>;
-+ status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+ phy-supply = <&vcc5v0_usb_otg>;
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&usb2phy1_host {
-+ phy-supply = <&vcc5v0_usb30_host>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ phy-supply = <&vcc5v0_usb30_host>;
-+ status = "okay";
-+};
-+
-+&vop {
-+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
+++ /dev/null
-From 06f6dd4d607766a527e37529f2f3f90dd1464293 Mon Sep 17 00:00:00 2001
-From: FUKAUMI Naoki <naoki@radxa.com>
-Date: Sun, 23 Jun 2024 11:33:29 +0900
-Subject: [PATCH] arm64: dts: rockchip: change spi-max-frequency for Radxa ROCK
- 3C
-
-SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
-
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Link: https://lore.kernel.org/r/20240623023329.1044-3-naoki@radxa.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
-@@ -633,7 +633,7 @@
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
-- spi-max-frequency = <120000000>;
-+ spi-max-frequency = <104000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <1>;
- };
+++ /dev/null
-From 1a5c8d307c83c808a32686ed51afb4bac2092d39 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Tue, 21 May 2024 20:28:05 +0000
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa ZERO 3W/3E
-
-The Radxa ZERO 3W/3E is an ultra-small, high-performance single board
-computer based on the Rockchip RK3566, with a compact form factor and
-rich interfaces.
-
-The ZERO 3W and ZERO 3E are basically the same size and model, but
-differ only in storage and network interfaces.
-
-- eMMC (3W)
-- SD-card (both)
-- Ethernet (3E)
-- WiFi/BT (3W)
-
-Add initial support for eMMC, SD-card, Ethernet, HDMI and USB.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20240521202810.1225636-3-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 2 +
- .../dts/rockchip/rk3566-radxa-zero-3.dtsi | 463 ++++++++++++++++++
- .../dts/rockchip/rk3566-radxa-zero-3e.dts | 51 ++
- .../dts/rockchip/rk3566-radxa-zero-3w.dts | 91 ++++
- 4 files changed, 607 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -81,6 +81,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3e.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-zero-3w.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
-@@ -0,0 +1,463 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3566.dtsi"
-+
-+/ {
-+ aliases {
-+ mmc0 = &sdmmc0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ type = "d";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&user_led2>;
-+
-+ led-green {
-+ color = <LED_COLOR_ID_GREEN>;
-+ default-state = "on";
-+ function = LED_FUNCTION_HEARTBEAT;
-+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
-+ };
-+
-+ vcc_1v8: regulator-1v8-vcc {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8_p>;
-+ };
-+
-+ vcca_1v8: regulator-1v8-vcca {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8_p>;
-+ };
-+
-+ vcca1v8_image: regulator-1v8-vcca-image {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcca1v8_image";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8_p>;
-+ };
-+
-+ vcc_3v3: regulator-3v3-vcc {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ vcc_sys: regulator-5v0-vcc-sys {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu_npu>;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ avdd-0v9-supply = <&vdda_0v9>;
-+ avdd-1v8-supply = <&vcca1v8_image>;
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ rk817: pmic@20 {
-+ compatible = "rockchip,rk817";
-+ reg = <0x20>;
-+ #clock-cells = <1>;
-+ clock-output-names = "rk817-clkout1", "rk817-clkout2";
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int_l>;
-+ system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc_sys>;
-+ vcc2-supply = <&vcc_sys>;
-+ vcc3-supply = <&vcc_sys>;
-+ vcc4-supply = <&vcc_sys>;
-+ vcc5-supply = <&vcc_sys>;
-+ vcc6-supply = <&vcc_sys>;
-+ vcc7-supply = <&vcc_sys>;
-+ vcc8-supply = <&vcc_sys>;
-+ vcc9-supply = <&vcc5v_midu>;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vdd_gpu_npu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu_npu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sys: DCDC_REG4 {
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG1 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcc_1v8_p: LDO_REG7 {
-+ regulator-name = "vcc_1v8_p";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc1v8_dvp: LDO_REG8 {
-+ regulator-name = "vcc1v8_dvp";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc2v8_dvp: LDO_REG9 {
-+ regulator-name = "vcc2v8_dvp";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <2800000>;
-+ regulator-max-microvolt = <2800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc5v_midu: BOOST {
-+ regulator-name = "vcc5v_midu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vbus: OTG_SWITCH {
-+ regulator-name = "vbus";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+
-+ vdd_cpu: regulator@40 {
-+ compatible = "rockchip,rk8600";
-+ reg = <0x40>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1390000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+};
-+
-+&i2s0_8ch {
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ leds {
-+ user_led2: user-led2 {
-+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcca1v8_pmu>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio2-supply = <&vcc_1v8>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_3v3>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdmmc0 {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+ vmmc-supply = <&vcc3v3_sys>;
-+ vqmmc-supply = <&vccio_sd>;
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ dr_mode = "peripheral";
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy0_host {
-+ status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+ status = "okay";
-+};
-+
-+&vop {
-+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
-@@ -0,0 +1,51 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+
-+#include "rk3566-radxa-zero-3.dtsi"
-+
-+/ {
-+ model = "Radxa ZERO 3E";
-+ compatible = "radxa,zero-3e", "rockchip,rk3566";
-+
-+ aliases {
-+ ethernet0 = &gmac1;
-+ };
-+};
-+
-+&gmac1 {
-+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
-+ clock_in_out = "input";
-+ phy-handle = <&rgmii_phy1>;
-+ phy-mode = "rgmii-id";
-+ phy-supply = <&vcc_3v3>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac1m1_miim
-+ &gmac1m1_tx_bus2
-+ &gmac1m1_rx_bus2
-+ &gmac1m1_rgmii_clk
-+ &gmac1m1_rgmii_bus
-+ &gmac1m1_clkinout>;
-+ status = "okay";
-+};
-+
-+&mdio1 {
-+ rgmii_phy1: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac1_rstn>;
-+ reset-assert-us = <20000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
-+ };
-+};
-+
-+&pinctrl {
-+ gmac1 {
-+ gmac1_rstn: gmac1-rstn {
-+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
-@@ -0,0 +1,91 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+
-+#include "rk3566-radxa-zero-3.dtsi"
-+
-+/ {
-+ model = "Radxa ZERO 3W";
-+ compatible = "radxa,zero-3w", "rockchip,rk3566";
-+
-+ aliases {
-+ mmc1 = &sdhci;
-+ mmc2 = &sdmmc1;
-+ };
-+
-+ sdio_pwrseq: sdio-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ clocks = <&rk817 1>;
-+ clock-names = "ext_clock";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_reg_on_h>;
-+ post-power-on-delay-ms = <100>;
-+ power-off-delay-us = <5000000>;
-+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
-+ };
-+};
-+
-+&pinctrl {
-+ bluetooth {
-+ bt_reg_on_h: bt-reg-on-h {
-+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ bt_wake_host_h: bt-wake-host-h {
-+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ host_wake_bt_h: host-wake-bt-h {
-+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ wifi {
-+ wifi_reg_on_h: wifi-reg-on-h {
-+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wifi_wake_host_h: wifi-wake-host-h {
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ cap-mmc-highspeed;
-+ max-frequency = <200000000>;
-+ mmc-hs200-1_8v;
-+ no-sd;
-+ no-sdio;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&sdmmc1 {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ cap-sdio-irq;
-+ keep-power-in-suspend;
-+ mmc-pwrseq = <&sdio_pwrseq>;
-+ no-mmc;
-+ no-sd;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
-+ uart-has-rtscts;
-+ status = "okay";
-+};
+++ /dev/null
-From 060c1950037e4c54ca4d8186a8f46269e35db901 Mon Sep 17 00:00:00 2001
-From: FUKAUMI Naoki <naoki@radxa.com>
-Date: Fri, 21 Jun 2024 07:44:35 +0900
-Subject: [PATCH] arm64: dts: rockchip: fix mmc aliases for Radxa ZERO 3E/3W
-
-align with other Radxa products.
-
-- mmc0 is eMMC
-- mmc1 is microSD
-
-for ZERO 3E, there is no eMMC, but aliases should start at 0, so mmc0
-is microSD as exception.
-
-Fixes: 1a5c8d307c83 ("arm64: dts: rockchip: Add Radxa ZERO 3W/3E")
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-
-Changes in v3:
-- fix syntax error in rk3566-radxa-zero-3e.dts
-Changes in v2:
-- microSD is mmc0 instead of mmc1 for ZERO 3E
-
-Link: https://lore.kernel.org/r/20240620224435.2752-1-naoki@radxa.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi | 4 ----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts | 1 +
- arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts | 3 ++-
- 3 files changed, 3 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
-@@ -6,10 +6,6 @@
- #include "rk3566.dtsi"
-
- / {
-- aliases {
-- mmc0 = &sdmmc0;
-- };
--
- chosen {
- stdout-path = "serial2:1500000n8";
- };
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3e.dts
-@@ -10,6 +10,7 @@
-
- aliases {
- ethernet0 = &gmac1;
-+ mmc0 = &sdmmc0;
- };
- };
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3w.dts
-@@ -9,7 +9,8 @@
- compatible = "radxa,zero-3w", "rockchip,rk3566";
-
- aliases {
-- mmc1 = &sdhci;
-+ mmc0 = &sdhci;
-+ mmc1 = &sdmmc0;
- mmc2 = &sdmmc1;
- };
-
+++ /dev/null
-From f7c742cbe664ebdedc075945e75443683d1175f7 Mon Sep 17 00:00:00 2001
-From: Trevor Woerner <twoerner@gmail.com>
-Date: Wed, 19 Jun 2024 21:32:49 -0400
-Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to radxa-zero-3
-
-Add names to the pins of the general-purpose expansion header as given
-in the Radxa documentation[1] following the conventions in the kernel[2]
-to make it easier for users to correlate pins with functions when using
-utilities such as 'gpioinfo'.
-
-[1] https://docs.radxa.com/en/zero/zero3/hardware-design/hardware-interface
-[2] https://www.kernel.org/doc/Documentation/devicetree/bindings/gpio/gpio.txt
-
-Signed-off-by: Trevor Woerner <twoerner@gmail.com>
-Link: https://lore.kernel.org/r/20240620013301.33653-1-twoerner@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../dts/rockchip/rk3566-radxa-zero-3.dtsi | 72 +++++++++++++++++++
- 1 file changed, 72 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
-@@ -105,6 +105,78 @@
- cpu-supply = <&vdd_cpu>;
- };
-
-+&gpio0 {
-+ gpio-line-names =
-+ /* GPIO0_A0 - A7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO0_B0 - B7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO0_C0 - C7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO0_D0 - D7 */
-+ "pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "",
-+ "", "", "", "", "";
-+};
-+
-+&gpio1 {
-+ gpio-line-names =
-+ /* GPIO1_A0 - A7 */
-+ "pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "",
-+ "", "pin-37 [GPIO1_A4]", "",
-+ "", "",
-+ /* GPIO1_B0 - B7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO1_C0 - C7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO1_D0 - D7 */
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&gpio2 {
-+ gpio-line-names =
-+ /* GPIO2_A0 - A7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO2_B0 - B7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO2_C0 - C7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO2_D0 - D7 */
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&gpio3 {
-+ gpio-line-names =
-+ /* GPIO3_A0 - A7 */
-+ "", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]",
-+ "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]",
-+ "pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]",
-+ /* GPIO3_B0 - B7 */
-+ "pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]",
-+ "pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "",
-+ "", "",
-+ /* GPIO3_C0 - C7 */
-+ "", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]",
-+ "pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "",
-+ "", "",
-+ /* GPIO3_D0 - D7 */
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&gpio4 {
-+ gpio-line-names =
-+ /* GPIO4_A0 - A7 */
-+ "", "", "", "", "", "", "", "",
-+ /* GPIO4_B0 - B7 */
-+ "", "", "pin-27 [GPIO4_B2]",
-+ "pin-28 [GPIO4_B3]", "", "", "", "",
-+ /* GPIO4_C0 - C7 */
-+ "", "", "pin-23 [GPIO4_C2]",
-+ "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]",
-+ "pin-24 [GPIO4_C6]", "",
-+ /* GPIO4_D0 - D7 */
-+ "", "", "", "", "", "", "", "";
-+};
-+
- &gpu {
- mali-supply = <&vdd_gpu_npu>;
- status = "okay";
+++ /dev/null
-From 846ef7748fa9124c8eea76e2d5e833fa69b3ef7c Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Thu, 27 Jun 2024 21:17:31 +0000
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 3B
-
-The Radxa ROCK 3B is a single-board computer based on the Pico-ITX form
-factor (100mm x 75mm). Two versions of the ROCK 3B exists, a community
-version based on the RK3568 SoC and an industrial version based on the
-RK3568J SoC.
-
-Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20240627211737.1985549-3-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3568-rock-3b.dts | 781 ++++++++++++++++++
- 2 files changed, 782 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-od
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
-@@ -0,0 +1,781 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+ model = "Radxa ROCK 3B";
-+ compatible = "radxa,rock-3b", "rockchip,rk3568";
-+
-+ aliases {
-+ ethernet0 = &gmac0;
-+ ethernet1 = &gmac1;
-+ mmc0 = &sdhci;
-+ mmc1 = &sdmmc0;
-+ mmc2 = &sdmmc2;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ type = "a";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ ir-receiver {
-+ compatible = "gpio-ir-receiver";
-+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pwm3_ir>;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led>;
-+
-+ led-0 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ default-state = "on";
-+ function = LED_FUNCTION_HEARTBEAT;
-+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
-+ };
-+
-+ /* pi6c pcie clock generator */
-+ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_pwren_h>;
-+ regulator-name = "vcc3v3_pi6c_03";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <10000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc3v3_sys: regulator-3v3-vcc-sys {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc3v3_sys2: regulator-3v3-vcc-sys2 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys2";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_sys: regulator-5v0-vcc-sys {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc5v0_usb_host: regulator-5v0-vcc-usb-host {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb_host_pwren_h>;
-+ regulator-name = "vcc5v0_usb_host";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb_otg_pwren_h>;
-+ regulator-name = "vcc5v0_usb_otg";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ sdio_pwrseq: sdio-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ clocks = <&rk809 1>;
-+ clock-names = "ext_clock";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_reg_on_h>;
-+ post-power-on-delay-ms = <100>;
-+ power-off-delay-us = <5000000>;
-+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
-+ };
-+
-+ sound {
-+ compatible = "simple-audio-card";
-+ simple-audio-card,format = "i2s";
-+ simple-audio-card,name = "Analog RK809";
-+ simple-audio-card,mclk-fs = <256>;
-+
-+ simple-audio-card,cpu {
-+ sound-dai = <&i2s1_8ch>;
-+ };
-+
-+ simple-audio-card,codec {
-+ sound-dai = <&rk809>;
-+ };
-+ };
-+};
-+
-+&combphy0 {
-+ status = "okay";
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&combphy2 {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gmac0 {
-+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
-+ clock_in_out = "input";
-+ phy-handle = <&rgmii_phy0>;
-+ phy-mode = "rgmii-id";
-+ phy-supply = <&vcc_3v3>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac0_miim
-+ &gmac0_tx_bus2
-+ &gmac0_rx_bus2
-+ &gmac0_rgmii_clk
-+ &gmac0_rgmii_bus
-+ &gmac0_clkinout>;
-+ status = "okay";
-+};
-+
-+&gmac1 {
-+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
-+ clock_in_out = "input";
-+ phy-handle = <&rgmii_phy1>;
-+ phy-mode = "rgmii-id";
-+ phy-supply = <&vcc_3v3>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac1m1_miim
-+ &gmac1m1_tx_bus2
-+ &gmac1m1_rx_bus2
-+ &gmac1m1_rgmii_clk
-+ &gmac1m1_rgmii_bus
-+ &gmac1m1_clkinout>;
-+ status = "okay";
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu>;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ avdd-0v9-supply = <&vdda0v9_image>;
-+ avdd-1v8-supply = <&vcca1v8_image>;
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1150000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk809: pmic@20 {
-+ compatible = "rockchip,rk809";
-+ reg = <0x20>;
-+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
-+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
-+ #clock-cells = <1>;
-+ clocks = <&cru I2S1_MCLKOUT_TX>;
-+ clock-names = "mclk";
-+ clock-output-names = "rk809-clkout1", "rk809-clkout2";
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
-+ #sound-dai-cells = <0>;
-+ system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc3v3_sys>;
-+ vcc2-supply = <&vcc3v3_sys>;
-+ vcc3-supply = <&vcc3v3_sys>;
-+ vcc4-supply = <&vcc3v3_sys>;
-+ vcc5-supply = <&vcc3v3_sys>;
-+ vcc6-supply = <&vcc3v3_sys>;
-+ vcc7-supply = <&vcc3v3_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc3v3_sys>;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vdd_npu: DCDC_REG4 {
-+ regulator-name = "vdd_npu";
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG5 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_image: LDO_REG1 {
-+ regulator-name = "vdda0v9_image";
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca_1v8: LDO_REG7 {
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG8 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca1v8_image: LDO_REG9 {
-+ regulator-name = "vcca1v8_image";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3: SWITCH_REG1 {
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sd: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&i2c5 {
-+ status = "okay";
-+
-+ hym8563: rtc@51 {
-+ compatible = "haoyu,hym8563";
-+ reg = <0x51>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <0>;
-+ clock-output-names = "rtcic_32kout";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rtcic_int_l>;
-+ wakeup-source;
-+ };
-+};
-+
-+&i2s0_8ch {
-+ status = "okay";
-+};
-+
-+&i2s1_8ch {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s1m0_sclktx
-+ &i2s1m0_lrcktx
-+ &i2s1m0_sdi0
-+ &i2s1m0_sdo0>;
-+ rockchip,trcm-sync-tx-only;
-+ status = "okay";
-+};
-+
-+&mdio0 {
-+ rgmii_phy0: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ reset-assert-us = <20000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
-+ };
-+};
-+
-+&mdio1 {
-+ rgmii_phy1: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ reset-assert-us = <20000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
-+ };
-+};
-+
-+&pcie2x1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie20m1_pins>;
-+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_sys2>;
-+ status = "okay";
-+};
-+
-+&pcie30phy {
-+ status = "okay";
-+};
-+
-+&pcie3x2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie30x2m1_pins>;
-+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ bluetooth {
-+ bt_reg_on_h: bt-reg-on-h {
-+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ bt_wake_host_h: bt-wake-host-h {
-+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ host_wake_bt_h: host-wake-bt-h {
-+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ ir-receiver {
-+ pwm3_ir: pwm3-ir {
-+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ leds {
-+ led: led {
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie {
-+ pcie_pwren_h: pcie-pwren-h {
-+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie20 {
-+ pcie20m1_pins: pcie20m1-pins {
-+ rockchip,pins =
-+ <2 RK_PD0 4 &pcfg_pull_none>,
-+ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,
-+ <2 RK_PD1 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie30x2 {
-+ pcie30x2m1_pins: pcie30x2m1-pins {
-+ rockchip,pins =
-+ <2 RK_PD4 4 &pcfg_pull_none>,
-+ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>,
-+ <2 RK_PD5 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ rtc {
-+ rtcic_int_l: rtcic-int-l {
-+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb {
-+ usb_host_pwren_h: usb-host-pwren-h {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ usb_otg_pwren_h: usb-otg-pwren-h {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ wifi {
-+ wifi_reg_on_h: wifi-reg-on-h {
-+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wifi_wake_host_h: wifi-wake-host-h {
-+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcc3v3_pmu>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio2-supply = <&vcc_1v8>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_1v8>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ cap-mmc-highspeed;
-+ max-frequency = <200000000>;
-+ mmc-hs200-1_8v;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&sdmmc0 {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+ vmmc-supply = <&vcc3v3_sd>;
-+ vqmmc-supply = <&vccio_sd>;
-+ status = "okay";
-+};
-+
-+&sdmmc2 {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ cap-sdio-irq;
-+ keep-power-in-suspend;
-+ mmc-pwrseq = <&sdio_pwrseq>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc3v3_sys2>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "disabled";
-+};
-+
-+&sfc {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ flash@0 {
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <104000000>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <1>;
-+ };
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&uart8 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
-+ uart-has-rtscts;
-+ status = "disabled";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ extcon = <&usb2phy0>;
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy0_host {
-+ phy-supply = <&vcc5v0_usb_host>;
-+ status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+ phy-supply = <&vcc5v0_usb_otg>;
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ phy-supply = <&vcc5v0_usb_host>;
-+ status = "okay";
-+};
-+
-+&vop {
-+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
+++ /dev/null
-From 626a479873b6a680b3227c4852bde4a1f2c17fdf Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Fri, 19 Apr 2024 18:30:19 +0800
-Subject: [PATCH] arm64: dts: rockchip: correct the model name for Radxa ROCK
- 3A
-
-According to https://radxa.com/products/rock3/3a,
-the name of this board should be "Radxa ROCK 3A".
-
-Suggested-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Reviewed-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/20240419103019.992586-3-amadeus@jmu.edu.cn
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
-@@ -8,7 +8,7 @@
- #include "rk3568.dtsi"
-
- / {
-- model = "Radxa ROCK3 Model A";
-+ model = "Radxa ROCK 3A";
- compatible = "radxa,rock3a", "rockchip,rk3568";
-
- aliases {
+++ /dev/null
-From dcf4fef6631c302f9bdd188979fe3172e47a29c7 Mon Sep 17 00:00:00 2001
-From: Aurelien Jarno <aurelien@aurel32.net>
-Date: Tue, 30 Jul 2024 17:11:04 +0100
-Subject: [PATCH] hwrng: rockchip - add hwrng driver for Rockchip RK3568 SoC
-
-Rockchip SoCs used to have a random number generator as part of their
-crypto device, and support for it has to be added to the corresponding
-driver. However newer Rockchip SoCs like the RK3568 have an independent
-True Random Number Generator device. This patch adds a driver for it,
-greatly inspired from the downstream driver.
-
-The TRNG device does not seem to have a signal conditionner and the FIPS
-140-2 test returns a lot of failures. They can be reduced by increasing
-RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value
-has been adjusted to get ~90% of successes and the quality value has
-been set accordingly.
-
-Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-[daniel@makrotpia.org: code style fixes]
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
----
- MAINTAINERS | 1 +
- drivers/char/hw_random/Kconfig | 14 ++
- drivers/char/hw_random/Makefile | 1 +
- drivers/char/hw_random/rockchip-rng.c | 227 ++++++++++++++++++++++++++
- 4 files changed, 243 insertions(+)
- create mode 100644 drivers/char/hw_random/rockchip-rng.c
-
---- a/drivers/char/hw_random/Kconfig
-+++ b/drivers/char/hw_random/Kconfig
-@@ -573,6 +573,20 @@ config HW_RANDOM_JH7110
- To compile this driver as a module, choose M here.
- The module will be called jh7110-trng.
-
-+config HW_RANDOM_ROCKCHIP
-+ tristate "Rockchip True Random Number Generator"
-+ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
-+ depends on HAS_IOMEM
-+ default HW_RANDOM
-+ help
-+ This driver provides kernel-side support for the True Random Number
-+ Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called rockchip-rng.
-+
-+ If unsure, say Y.
-+
- endif # HW_RANDOM
-
- config UML_RANDOM
---- a/drivers/char/hw_random/Makefile
-+++ b/drivers/char/hw_random/Makefile
-@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
- obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
- obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
- obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
-+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
- obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
---- /dev/null
-+++ b/drivers/char/hw_random/rockchip-rng.c
-@@ -0,0 +1,227 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC
-+ *
-+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
-+ * Copyright (c) 2022, Aurelien Jarno
-+ * Authors:
-+ * Lin Jinhan <troy.lin@rock-chips.com>
-+ * Aurelien Jarno <aurelien@aurel32.net>
-+ */
-+#include <linux/clk.h>
-+#include <linux/hw_random.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#define RK_RNG_AUTOSUSPEND_DELAY 100
-+#define RK_RNG_MAX_BYTE 32
-+#define RK_RNG_POLL_PERIOD_US 100
-+#define RK_RNG_POLL_TIMEOUT_US 10000
-+
-+/*
-+ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
-+ * a tradeoff between speed and quality and has been adjusted to get a quality
-+ * of ~900 (~87.5% of FIPS 140-2 successes).
-+ */
-+#define RK_RNG_SAMPLE_CNT 1000
-+
-+/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
-+#define TRNG_RST_CTL 0x0004
-+#define TRNG_RNG_CTL 0x0400
-+#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4)
-+#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4)
-+#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4)
-+#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2)
-+#define TRNG_RNG_CTL_MASK GENMASK(15, 0)
-+#define TRNG_RNG_CTL_ENABLE BIT(1)
-+#define TRNG_RNG_CTL_START BIT(0)
-+#define TRNG_RNG_SAMPLE_CNT 0x0404
-+#define TRNG_RNG_DOUT 0x0410
-+
-+struct rk_rng {
-+ struct hwrng rng;
-+ void __iomem *base;
-+ struct reset_control *rst;
-+ int clk_num;
-+ struct clk_bulk_data *clk_bulks;
-+};
-+
-+/* The mask in the upper 16 bits determines the bits that are updated */
-+static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
-+{
-+ writel((mask << 16) | val, rng->base + TRNG_RNG_CTL);
-+}
-+
-+static int rk_rng_init(struct hwrng *rng)
-+{
-+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+ int ret;
-+
-+ /* start clocks */
-+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
-+ if (ret < 0) {
-+ dev_err((struct device *) rk_rng->rng.priv,
-+ "Failed to enable clks %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* set the sample period */
-+ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
-+
-+ /* set osc ring speed and enable it */
-+ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_LEN_256_BIT |
-+ TRNG_RNG_CTL_OSC_RING_SPEED_0 |
-+ TRNG_RNG_CTL_ENABLE,
-+ TRNG_RNG_CTL_MASK);
-+
-+ return 0;
-+}
-+
-+static void rk_rng_cleanup(struct hwrng *rng)
-+{
-+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+ /* stop TRNG */
-+ rk_rng_write_ctl(rk_rng, 0, TRNG_RNG_CTL_MASK);
-+
-+ /* stop clocks */
-+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
-+}
-+
-+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE);
-+ u32 reg;
-+ int ret = 0;
-+
-+ ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* Start collecting random data */
-+ rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_START, TRNG_RNG_CTL_START);
-+
-+ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
-+ !(reg & TRNG_RNG_CTL_START),
-+ RK_RNG_POLL_PERIOD_US,
-+ RK_RNG_POLL_TIMEOUT_US);
-+ if (ret < 0)
-+ goto out;
-+
-+ /* Read random data stored in the registers */
-+ memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read);
-+out:
-+ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
-+ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
-+
-+ return (ret < 0) ? ret : to_read;
-+}
-+
-+static int rk_rng_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct rk_rng *rk_rng;
-+ int ret;
-+
-+ rk_rng = devm_kzalloc(dev, sizeof(*rk_rng), GFP_KERNEL);
-+ if (!rk_rng)
-+ return -ENOMEM;
-+
-+ rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(rk_rng->base))
-+ return PTR_ERR(rk_rng->base);
-+
-+ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
-+ if (rk_rng->clk_num < 0)
-+ return dev_err_probe(dev, rk_rng->clk_num,
-+ "Failed to get clks property\n");
-+
-+ rk_rng->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
-+ if (IS_ERR(rk_rng->rst))
-+ return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
-+ "Failed to get reset property\n");
-+
-+ reset_control_assert(rk_rng->rst);
-+ udelay(2);
-+ reset_control_deassert(rk_rng->rst);
-+
-+ platform_set_drvdata(pdev, rk_rng);
-+
-+ rk_rng->rng.name = dev_driver_string(dev);
-+ if (!IS_ENABLED(CONFIG_PM)) {
-+ rk_rng->rng.init = rk_rng_init;
-+ rk_rng->rng.cleanup = rk_rng_cleanup;
-+ }
-+ rk_rng->rng.read = rk_rng_read;
-+ rk_rng->rng.priv = (unsigned long) dev;
-+ rk_rng->rng.quality = 900;
-+
-+ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
-+ pm_runtime_use_autosuspend(dev);
-+ devm_pm_runtime_enable(dev);
-+
-+ ret = devm_hwrng_register(dev, &rk_rng->rng);
-+ if (ret)
-+ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused rk_rng_runtime_suspend(struct device *dev)
-+{
-+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+ rk_rng_cleanup(&rk_rng->rng);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused rk_rng_runtime_resume(struct device *dev)
-+{
-+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+ return rk_rng_init(&rk_rng->rng);
-+}
-+
-+static const struct dev_pm_ops rk_rng_pm_ops = {
-+ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
-+ rk_rng_runtime_resume, NULL)
-+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
-+ pm_runtime_force_resume)
-+};
-+
-+static const struct of_device_id rk_rng_dt_match[] = {
-+ { .compatible = "rockchip,rk3568-rng", },
-+ { /* sentinel */ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
-+
-+static struct platform_driver rk_rng_driver = {
-+ .driver = {
-+ .name = "rockchip-rng",
-+ .pm = &rk_rng_pm_ops,
-+ .of_match_table = rk_rng_dt_match,
-+ },
-+ .probe = rk_rng_probe,
-+};
-+
-+module_platform_driver(rk_rng_driver);
-+
-+MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver");
-+MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
-+MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>");
-+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From afeccc4084963aaa932931b734c8def55613c483 Mon Sep 17 00:00:00 2001
-From: Aurelien Jarno <aurelien@aurel32.net>
-Date: Tue, 30 Jul 2024 17:11:44 +0100
-Subject: [PATCH] arm64: dts: rockchip: add DT entry for RNG to RK356x
-
-Include the just added Rockchip RNG driver for RK356x SoCs and
-enable it on RK3568.
-
-Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/d2beb15377dc8b580ca5557b1a4a6f50b74055aa.1722355365.git.daniel@makrotopia.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++++
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 ++++++++++
- 2 files changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-@@ -257,6 +257,10 @@
- };
- };
-
-+&rng {
-+ status = "okay";
-+};
-+
- &usb_host0_xhci {
- phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1106,6 +1106,16 @@
- status = "disabled";
- };
-
-+ rng: rng@fe388000 {
-+ compatible = "rockchip,rk3568-rng";
-+ reg = <0x0 0xfe388000 0x0 0x4000>;
-+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
-+ clock-names = "core", "ahb";
-+ resets = <&cru SRST_TRNG_NS>;
-+ reset-names = "reset";
-+ status = "disabled";
-+ };
-+
- i2s0_8ch: i2s@fe400000 {
- compatible = "rockchip,rk3568-i2s-tdm";
- reg = <0x0 0xfe400000 0x0 0x1000>;
+++ /dev/null
-From ec532f3591ce6e6ed5ec6c35773a66aae118e1f0 Mon Sep 17 00:00:00 2001
-From: Heiko Stuebner <heiko@sntech.de>
-Date: Thu, 15 Aug 2024 18:25:19 +0200
-Subject: [PATCH] arm64: dts: rockchip: drop obsolete reset-names from rk356x
- rng node
-
-The reset-names property is not part of the binding, so drop it.
-It is also not used by the driver, so that property was likely
-a leftover from some vendor-kernel node.
-
-Fixes: afeccc408496 ("arm64: dts: rockchip: add DT entry for RNG to RK356x")
-Reported-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-Link: https://lore.kernel.org/r/20240815162519.751193-1-heiko@sntech.de
----
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1112,7 +1112,6 @@
- clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
- clock-names = "core", "ahb";
- resets = <&cru SRST_TRNG_NS>;
-- reset-names = "reset";
- status = "disabled";
- };
-
+++ /dev/null
-From 8b9c12757f919157752646faf3821abf2b7d2a64 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Fri, 22 Nov 2024 15:30:05 +0800
-Subject: [PATCH] arm64: dts: rockchip: add reset-names for combphy on rk3568
-
-The reset-names of combphy are missing, add it.
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Fixes: fd3ac6e80497 ("dt-bindings: phy: rockchip: rk3588 has two reset lines")
-Link: https://lore.kernel.org/r/20241122073006.99309-1-amadeus@jmu.edu.cn
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 +
- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 ++
- 2 files changed, 3 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-@@ -223,6 +223,7 @@
- assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_PIPEPHY0>;
-+ reset-names = "phy";
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
- #phy-cells = <1>;
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1756,6 +1756,7 @@
- assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_PIPEPHY1>;
-+ reset-names = "phy";
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
- #phy-cells = <1>;
-@@ -1772,6 +1773,7 @@
- assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
- assigned-clock-rates = <100000000>;
- resets = <&cru SRST_PIPEPHY2>;
-+ reset-names = "phy";
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
- #phy-cells = <1>;
#include <linux/slab.h>
#include <linux/syscore_ops.h>
-@@ -163,6 +166,7 @@ struct its_device {
+@@ -166,6 +169,7 @@ struct its_device {
struct its_node *its;
struct event_lpi_map event_map;
void *itt;
u32 nr_ites;
u32 device_id;
bool shared;
-@@ -198,6 +202,87 @@ static DEFINE_IDA(its_vpeid_ida);
+@@ -201,6 +205,87 @@ static DEFINE_IDA(its_vpeid_ida);
#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
/*
* Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
* always have vSGIs mapped.
-@@ -2192,7 +2277,8 @@ static struct page *its_allocate_prop_ta
+@@ -2183,7 +2268,8 @@ static struct page *its_allocate_prop_ta
{
struct page *prop_page;
if (!prop_page)
return NULL;
-@@ -2203,8 +2289,7 @@ static struct page *its_allocate_prop_ta
+@@ -2194,8 +2280,7 @@ static struct page *its_allocate_prop_ta
static void its_free_prop_table(struct page *prop_page)
{
}
static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
-@@ -2326,7 +2411,7 @@ static int its_setup_baser(struct its_no
+@@ -2317,7 +2402,7 @@ static int its_setup_baser(struct its_no
order = get_order(GITS_BASER_PAGES_MAX * psz);
}
if (!page)
return -ENOMEM;
-@@ -2339,7 +2424,7 @@ static int its_setup_baser(struct its_no
+@@ -2330,7 +2415,7 @@ static int its_setup_baser(struct its_no
/* 52bit PA is supported only when PageSize=64K */
if (psz != SZ_64K) {
pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
return -ENXIO;
}
-@@ -2395,7 +2480,7 @@ retry_baser:
+@@ -2386,7 +2471,7 @@ retry_baser:
pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
&its->phys_base, its_base_type_string[type],
val, tmp);
return -ENXIO;
}
-@@ -2534,8 +2619,7 @@ static void its_free_tables(struct its_n
+@@ -2525,8 +2610,7 @@ static void its_free_tables(struct its_n
for (i = 0; i < GITS_BASER_NR_REGS; i++) {
if (its->tables[i].base) {
its->tables[i].base = NULL;
}
}
-@@ -2801,7 +2885,7 @@ static bool allocate_vpe_l2_table(int cp
+@@ -2792,7 +2876,7 @@ static bool allocate_vpe_l2_table(int cp
/* Allocate memory for 2nd level table */
if (!table[idx]) {
if (!page)
return false;
-@@ -2920,7 +3004,7 @@ static int allocate_vpe_l1_table(void)
+@@ -2911,7 +2995,7 @@ static int allocate_vpe_l1_table(void)
pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
np, npg, psz, epp, esz);
if (!page)
return -ENOMEM;
-@@ -2966,8 +3050,7 @@ static struct page *its_allocate_pending
+@@ -2957,8 +3041,7 @@ static struct page *its_allocate_pending
{
struct page *pend_page;
if (!pend_page)
return NULL;
-@@ -2979,7 +3062,7 @@ static struct page *its_allocate_pending
+@@ -2970,7 +3053,7 @@ static struct page *its_allocate_pending
static void its_free_pending_table(struct page *pt)
{
}
/*
-@@ -3314,8 +3397,8 @@ static bool its_alloc_table_entry(struct
+@@ -3305,8 +3388,8 @@ static bool its_alloc_table_entry(struct
/* Allocate memory for 2nd level table */
if (!table[idx]) {
if (!page)
return false;
-@@ -3410,7 +3493,6 @@ static struct its_device *its_create_dev
+@@ -3401,7 +3484,6 @@ static struct its_device *its_create_dev
if (WARN_ON(!is_power_of_2(nvecs)))
nvecs = roundup_pow_of_two(nvecs);
/*
* Even if the device wants a single LPI, the ITT must be
* sized as a power of two (and you need at least one bit...).
-@@ -3418,7 +3500,11 @@ static struct its_device *its_create_dev
+@@ -3409,7 +3491,11 @@ static struct its_device *its_create_dev
nr_ites = max(2, nvecs);
sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
if (alloc_lpis) {
lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
if (lpi_map)
-@@ -3430,9 +3516,9 @@ static struct its_device *its_create_dev
+@@ -3421,9 +3507,9 @@ static struct its_device *its_create_dev
lpi_base = 0;
}
bitmap_free(lpi_map);
kfree(col_map);
return NULL;
-@@ -3442,6 +3528,7 @@ static struct its_device *its_create_dev
+@@ -3433,6 +3519,7 @@ static struct its_device *its_create_dev
dev->its = its;
dev->itt = itt;
dev->nr_ites = nr_ites;
dev->event_map.lpi_map = lpi_map;
dev->event_map.col_map = col_map;
-@@ -3469,7 +3556,7 @@ static void its_free_device(struct its_d
+@@ -3460,7 +3547,7 @@ static void its_free_device(struct its_d
list_del(&its_dev->entry);
raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
kfree(its_dev->event_map.col_map);
kfree(its_dev);
}
-@@ -5112,8 +5199,9 @@ static int __init its_probe_one(struct i
+@@ -5160,8 +5247,9 @@ static int __init its_probe_one(struct i
}
}
if (!page) {
err = -ENOMEM;
goto out_unmap_sgir;
-@@ -5177,7 +5265,7 @@ static int __init its_probe_one(struct i
+@@ -5225,7 +5313,7 @@ static int __init its_probe_one(struct i
out_free_tables:
its_free_tables(its);
out_free_cmd:
out_unmap_sgir:
if (its->sgir_base)
iounmap(its->sgir_base);
-@@ -5659,6 +5747,10 @@ int __init its_init(struct fwnode_handle
+@@ -5711,6 +5799,10 @@ int __init its_init(struct fwnode_handle
bool has_v4_1 = false;
int err;
+
gic_rdists = rdists;
- its_parent = parent_domain;
+ lpi_prop_prio = irq_prio;
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
-@@ -260,7 +260,7 @@ static void *itt_alloc_pool(int node, in
+@@ -263,7 +263,7 @@ static void *itt_alloc_pool(int node, in
if (addr)
break;
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
-@@ -270,6 +270,8 @@ stable kernels.
+@@ -283,6 +283,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 |
+----------------+-----------------+-----------------+-----------------------------+
+| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 |
++----------------+-----------------+-----------------+-----------------------------+
-
+----------------+-----------------+-----------------+-----------------------------+
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+ +----------------+-----------------+-----------------+-----------------------------+
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
-@@ -1267,6 +1267,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM
+@@ -1295,6 +1295,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM
If unsure, say Y.
default y
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
-@@ -202,13 +202,15 @@ static DEFINE_IDA(its_vpeid_ida);
+@@ -205,13 +205,15 @@ static DEFINE_IDA(its_vpeid_ida);
#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
if (!page)
return NULL;
-@@ -4851,6 +4853,17 @@ static bool its_set_non_coherent(void *d
+@@ -4888,6 +4890,17 @@ static bool __maybe_unused its_enable_qu
return true;
}
static const struct gic_quirk its_quirks[] = {
#ifdef CONFIG_CAVIUM_ERRATUM_22375
{
-@@ -4910,6 +4923,14 @@ static const struct gic_quirk its_quirks
+@@ -4955,6 +4968,14 @@ static const struct gic_quirk its_quirks
.property = "dma-noncoherent",
.init = its_set_non_coherent,
},
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1043,7 +1043,7 @@
+@@ -1050,7 +1050,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <2>;
+++ /dev/null
-From 2dc66a5ab2c6fb532fbb16107ee7efcb0effbfa5 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 26 Jan 2024 19:18:22 +0100
-Subject: [PATCH] clk: rockchip: rk3588: fix CLK_NR_CLKS usage
-
-CLK_NR_CLKS is not part of the DT bindings and needs to be removed
-from it, just like it recently happened for other platforms. This
-takes care of it by introducing a new function identifying the
-maximum used clock ID at runtime.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/clk/rockchip/clk-rk3588.c | 5 ++++-
- drivers/clk/rockchip/clk.c | 17 +++++++++++++++++
- drivers/clk/rockchip/clk.h | 2 ++
- 3 files changed, 23 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/rockchip/clk-rk3588.c
-+++ b/drivers/clk/rockchip/clk-rk3588.c
-@@ -2458,15 +2458,18 @@ static struct rockchip_clk_branch rk3588
- static void __init rk3588_clk_init(struct device_node *np)
- {
- struct rockchip_clk_provider *ctx;
-+ unsigned long clk_nr_clks;
- void __iomem *reg_base;
-
-+ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
-+ ARRAY_SIZE(rk3588_clk_branches)) + 1;
- reg_base = of_iomap(np, 0);
- if (!reg_base) {
- pr_err("%s: could not map cru region\n", __func__);
- return;
- }
-
-- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
-+ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
- if (IS_ERR(ctx)) {
- pr_err("%s: rockchip clk init failed\n", __func__);
- iounmap(reg_base);
---- a/drivers/clk/rockchip/clk.c
-+++ b/drivers/clk/rockchip/clk.c
-@@ -429,6 +429,23 @@ void rockchip_clk_register_plls(struct r
- }
- EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
-
-+unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
-+ unsigned int nr_clk)
-+{
-+ unsigned long max = 0;
-+ unsigned int idx;
-+
-+ for (idx = 0; idx < nr_clk; idx++, list++) {
-+ if (list->id > max)
-+ max = list->id;
-+ if (list->child && list->child->id > max)
-+ max = list->id;
-+ }
-+
-+ return max;
-+}
-+EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);
-+
- void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
- struct rockchip_clk_branch *list,
- unsigned int nr_clk)
---- a/drivers/clk/rockchip/clk.h
-+++ b/drivers/clk/rockchip/clk.h
-@@ -973,6 +973,8 @@ struct rockchip_clk_provider *rockchip_c
- void __iomem *base, unsigned long nr_clks);
- void rockchip_clk_of_add_provider(struct device_node *np,
- struct rockchip_clk_provider *ctx);
-+unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
-+ unsigned int nr_clk);
- void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
- struct rockchip_clk_branch *list,
- unsigned int nr_clk);
+++ /dev/null
-From 11a29dc2e41ead2be78cfa9d532edf924b461acc Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 26 Jan 2024 19:18:23 +0100
-Subject: [PATCH] dt-bindings: clock: rk3588: drop CLK_NR_CLKS
-
-CLK_NR_CLKS should not be part of the binding. Let's drop it, since
-the kernel code no longer uses it either.
-
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240126182919.48402-3-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- include/dt-bindings/clock/rockchip,rk3588-cru.h | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
-+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
-@@ -734,8 +734,6 @@
- #define PCLK_AV1_PRE 719
- #define HCLK_SDIO_PRE 720
-
--#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
--
- /* scmi-clocks indices */
-
- #define SCMI_CLK_CPUL 0
+++ /dev/null
-From c81798cf9dd2f324934585b2b52a0398caefb88e Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 26 Jan 2024 19:18:24 +0100
-Subject: [PATCH] dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
-
-Add PCLK_VO1GRF to complement PCLK_VO0GRF. This will be needed
-for HDMI support.
-
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240126182919.48402-4-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- include/dt-bindings/clock/rockchip,rk3588-cru.h | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
-+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
-@@ -733,6 +733,7 @@
- #define ACLK_AV1_PRE 718
- #define PCLK_AV1_PRE 719
- #define HCLK_SDIO_PRE 720
-+#define PCLK_VO1GRF 721
-
- /* scmi-clocks indices */
-
+++ /dev/null
-From 326be62eaf2e89767b7b9223f88eaf3c041b98d2 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 26 Jan 2024 19:18:25 +0100
-Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
-
-Currently pclk_vo1grf is not exposed, but it should be referenced
-from the vo1_grf syscon, which needs it enabled. That syscon is
-required for HDMI RX and TX functionality among other things.
-
-Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates
-and need the VO's hclk enabled in addition to their parent clock.
-
-No Fixes tag has been added, since the logic requiring these clocks
-is not yet upstream anyways.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/clk/rockchip/clk-rk3588.c | 10 ++++------
- 1 file changed, 4 insertions(+), 6 deletions(-)
-
---- a/drivers/clk/rockchip/clk-rk3588.c
-+++ b/drivers/clk/rockchip/clk-rk3588.c
-@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588
- RK3588_CLKGATE_CON(56), 0, GFLAGS),
- GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
- RK3588_CLKGATE_CON(56), 1, GFLAGS),
-- GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
-- RK3588_CLKGATE_CON(55), 10, GFLAGS),
- COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
- RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
- RK3588_CLKGATE_CON(56), 11, GFLAGS),
-@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588
- RK3588_CLKGATE_CON(60), 9, GFLAGS),
- GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
- RK3588_CLKGATE_CON(60), 10, GFLAGS),
-- GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
-- RK3588_CLKGATE_CON(59), 12, GFLAGS),
- GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
- RK3588_CLKGATE_CON(59), 14, GFLAGS),
- GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
-@@ -2447,12 +2443,14 @@ static struct rockchip_clk_branch rk3588
- GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
- GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
- GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
-- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
-+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
- GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
-- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
-+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
- GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
- GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
- GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
-+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
-+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
- };
-
- static void __init rk3588_clk_init(struct device_node *np)
+++ /dev/null
-From 2a6e4710672242281347103b64e01693aa823a29 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 26 Jan 2024 19:18:26 +0100
-Subject: [PATCH] clk: rockchip: rk3588: fix indent
-
-pclk_mailbox2 is the only RK3588 clock indented with one tab instead of
-two tabs. Let's fix this.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/clk/rockchip/clk-rk3588.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/rockchip/clk-rk3588.c
-+++ b/drivers/clk/rockchip/clk-rk3588.c
-@@ -1004,7 +1004,7 @@ static struct rockchip_clk_branch rk3588
- GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
- RK3588_CLKGATE_CON(16), 12, GFLAGS),
- GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
-- RK3588_CLKGATE_CON(16), 13, GFLAGS),
-+ RK3588_CLKGATE_CON(16), 13, GFLAGS),
- GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
- RK3588_CLKGATE_CON(19), 3, GFLAGS),
- GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
+++ /dev/null
-From dae3e57000fb2d6f491e3ee2956f5918326d6b72 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 26 Jan 2024 19:18:27 +0100
-Subject: [PATCH] clk: rockchip: rk3588: use linked clock ID for GATE_LINK
-
-In preparation for properly supporting GATE_LINK switch the unused
-linked clock argument from the clock's name to its ID. This allows
-easy and fast lookup of the 'struct clk'.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/clk/rockchip/clk-rk3588.c | 46 +++++++++++++++----------------
- 1 file changed, 23 insertions(+), 23 deletions(-)
-
---- a/drivers/clk/rockchip/clk-rk3588.c
-+++ b/drivers/clk/rockchip/clk-rk3588.c
-@@ -29,7 +29,7 @@
- * power, but avoids leaking implementation details into DT or hanging the
- * system.
- */
--#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
-+#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
- GATE(_id, cname, pname, f, o, b, gf)
- #define RK3588_LINKED_CLK CLK_IS_CRITICAL
-
-@@ -2429,28 +2429,28 @@ static struct rockchip_clk_branch rk3588
- GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
- RK3588_CLKGATE_CON(68), 2, GFLAGS),
-
-- GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
-- GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
-- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
-- GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
-- GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
-- GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
-- GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
-- GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
-- GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
-- GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
-- GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
-- GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
-- GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
-- GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
-- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
-- GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
-- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
-- GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
-- GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
-- GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
-- GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
-- GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
-+ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
-+ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
-+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
-+ GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
-+ GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
-+ GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
-+ GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
-+ GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
-+ GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
-+ GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
-+ GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
-+ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
-+ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
-+ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
-+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
-+ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
-+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
-+ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
-+ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
-+ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
-+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
-+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
- };
-
- static void __init rk3588_clk_init(struct device_node *np)
+++ /dev/null
-From ca151fd56b5736a7adbdba5675b9d87d70f20b23 Mon Sep 17 00:00:00 2001
-From: Shreeya Patel <shreeya.patel@collabora.com>
-Date: Thu, 28 Mar 2024 04:20:52 +0530
-Subject: [PATCH] dt-bindings: reset: Define reset id used for HDMI Receiver
-
-Add reset id used for HDMI Receiver in RK3588 SoCs
-
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
-Link: https://lore.kernel.org/r/20240327225057.672304-2-shreeya.patel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- include/dt-bindings/reset/rockchip,rk3588-cru.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
-+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
-@@ -751,4 +751,6 @@
- #define SRST_P_TRNG_CHK 658
- #define SRST_TRNG_S 659
-
-+#define SRST_A_HDMIRX_BIU 660
-+
- #endif
+++ /dev/null
-From 7af67019cd78d028ef377df689ac103d51905518 Mon Sep 17 00:00:00 2001
-From: Shreeya Patel <shreeya.patel@collabora.com>
-Date: Thu, 28 Mar 2024 04:20:53 +0530
-Subject: [PATCH] clk: rockchip: rk3588: Add reset line for HDMI Receiver
-
-Export hdmirx_biu reset line required by the Synopsys
-DesignWare HDMIRX Controller.
-
-Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
-Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/clk/rockchip/rst-rk3588.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/clk/rockchip/rst-rk3588.c
-+++ b/drivers/clk/rockchip/rst-rk3588.c
-@@ -577,6 +577,7 @@ static const int rk3588_register_offset[
-
- /* SOFTRST_CON59 */
- RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
-+ RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),
- RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
- RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
- RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
+++ /dev/null
-From e781bffc296766b55dbd048890d558655031e8d1 Mon Sep 17 00:00:00 2001
-From: Elaine Zhang <zhangqing@rock-chips.com>
-Date: Wed, 28 Aug 2024 15:42:52 +0000
-Subject: [PATCH] clk: rockchip: Add new pll type pll_rk3588_ddr
-
-That PLL type is similar to the other rk3588 pll types but the actual
-rate is twice the configured rate.
-Therefore, the returned calculated rate must be multiplied by two.
-
-Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
-Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
-Acked-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/clk/rockchip/clk-pll.c | 6 +++++-
- drivers/clk/rockchip/clk.h | 1 +
- 2 files changed, 6 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/rockchip/clk-pll.c
-+++ b/drivers/clk/rockchip/clk-pll.c
-@@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll
- }
- rate64 = rate64 >> cur.s;
-
-- return (unsigned long)rate64;
-+ if (pll->type == pll_rk3588_ddr)
-+ return (unsigned long)rate64 * 2;
-+ else
-+ return (unsigned long)rate64;
- }
-
- static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
-@@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(st
- break;
- case pll_rk3588:
- case pll_rk3588_core:
-+ case pll_rk3588_ddr:
- if (!pll->rate_table)
- init.ops = &rockchip_rk3588_pll_clk_norate_ops;
- else
---- a/drivers/clk/rockchip/clk.h
-+++ b/drivers/clk/rockchip/clk.h
-@@ -287,6 +287,7 @@ enum rockchip_pll_type {
- pll_rk3399,
- pll_rk3588,
- pll_rk3588_core,
-+ pll_rk3588_ddr,
- };
-
- #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
+++ /dev/null
-From 2e7b3daa8cb1ebd17e6a7f417ef5e6553203035c Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Mon, 25 Mar 2024 20:33:32 +0100
-Subject: [PATCH] clk: rockchip: rk3588: drop unused code
-
-All clocks are registered early using CLK_OF_DECLARE(), which marks
-the DT node as processed. For the processed DT node the probe routine
-is never called. Thus this whole code is never executed. This could
-be "fixed" by using CLK_OF_DECLARE_DRIVER, which avoids marking the
-DT node as processed. But then the probe routine would re-register
-all the clocks by calling rk3588_clk_init() again.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240325193609.237182-2-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/clk/rockchip/clk-rk3588.c | 40 -------------------------------
- 1 file changed, 40 deletions(-)
-
---- a/drivers/clk/rockchip/clk-rk3588.c
-+++ b/drivers/clk/rockchip/clk-rk3588.c
-@@ -2502,43 +2502,3 @@ static void __init rk3588_clk_init(struc
- }
-
- CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
--
--struct clk_rk3588_inits {
-- void (*inits)(struct device_node *np);
--};
--
--static const struct clk_rk3588_inits clk_3588_cru_init = {
-- .inits = rk3588_clk_init,
--};
--
--static const struct of_device_id clk_rk3588_match_table[] = {
-- {
-- .compatible = "rockchip,rk3588-cru",
-- .data = &clk_3588_cru_init,
-- },
-- { }
--};
--
--static int __init clk_rk3588_probe(struct platform_device *pdev)
--{
-- const struct clk_rk3588_inits *init_data;
-- struct device *dev = &pdev->dev;
--
-- init_data = device_get_match_data(dev);
-- if (!init_data)
-- return -EINVAL;
--
-- if (init_data->inits)
-- init_data->inits(dev->of_node);
--
-- return 0;
--}
--
--static struct platform_driver clk_rk3588_driver = {
-- .driver = {
-- .name = "clk-rk3588",
-- .of_match_table = clk_rk3588_match_table,
-- .suppress_bind_attrs = true,
-- },
--};
--builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe);
+++ /dev/null
-From ad1081a0da2744141d12e94ff816ac91feb871ca Mon Sep 17 00:00:00 2001
-From: Yao Zi <ziyao@disroot.org>
-Date: Thu, 12 Sep 2024 13:32:05 +0000
-Subject: [PATCH] clk: rockchip: fix finding of maximum clock ID
-
-If an ID of a branch's child is greater than current maximum, we should
-set new maximum to the child's ID, instead of its parent's.
-
-Fixes: 2dc66a5ab2c6 ("clk: rockchip: rk3588: fix CLK_NR_CLKS usage")
-Signed-off-by: Yao Zi <ziyao@disroot.org>
-Link: https://lore.kernel.org/r/20240912133204.29089-2-ziyao@disroot.org
-Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/rockchip/clk.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/rockchip/clk.c
-+++ b/drivers/clk/rockchip/clk.c
-@@ -439,7 +439,7 @@ unsigned long rockchip_clk_find_max_clk_
- if (list->id > max)
- max = list->id;
- if (list->child && list->child->id > max)
-- max = list->id;
-+ max = list->child->id;
- }
-
- return max;
+++ /dev/null
-From 2a46cd97f401a669d71b3d36b78bd6653f8424ee Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <megi@xff.cz>
-Date: Thu, 19 Oct 2023 18:57:25 +0200
-Subject: [PATCH] mfd: rk8xx: Add support for standard system-power-controller
- property
-
-DT property rockchip,system-power-controller is now deprecated.
-
-Signed-off-by: Ondrej Jirman <megi@xff.cz>
-Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20231019165732.3818789-4-megi@xff.cz
-Signed-off-by: Lee Jones <lee@kernel.org>
----
- drivers/mfd/rk8xx-core.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/mfd/rk8xx-core.c
-+++ b/drivers/mfd/rk8xx-core.c
-@@ -677,7 +677,8 @@ int rk8xx_probe(struct device *dev, int
- if (ret)
- return dev_err_probe(dev, ret, "failed to add MFD devices\n");
-
-- if (device_property_read_bool(dev, "rockchip,system-power-controller")) {
-+ if (device_property_read_bool(dev, "rockchip,system-power-controller") ||
-+ device_property_read_bool(dev, "system-power-controller")) {
- ret = devm_register_sys_off_handler(dev,
- SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
- &rk808_power_off, rk808);
+++ /dev/null
-From b0227e7081404448a0059b8698fdffd2dec280d2 Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <megi@xff.cz>
-Date: Thu, 19 Oct 2023 18:57:26 +0200
-Subject: [PATCH] mfd: rk8xx: Add support for RK806 power off
-
-Use DEV_OFF bit to power off the RK806 PMIC, when system-power-controller
-is used in DTS.
-
-Signed-off-by: Ondrej Jirman <megi@xff.cz>
-Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20231019165732.3818789-5-megi@xff.cz
-Signed-off-by: Lee Jones <lee@kernel.org>
----
- drivers/mfd/rk8xx-core.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/mfd/rk8xx-core.c
-+++ b/drivers/mfd/rk8xx-core.c
-@@ -517,6 +517,10 @@ static int rk808_power_off(struct sys_of
- reg = RK805_DEV_CTRL_REG;
- bit = DEV_OFF;
- break;
-+ case RK806_ID:
-+ reg = RK806_SYS_CFG3;
-+ bit = DEV_OFF;
-+ break;
- case RK808_ID:
- reg = RK808_DEVCTRL_REG,
- bit = DEV_OFF_RST;
+++ /dev/null
-From 2f70bbddeb457580cef3ceb574506083b9272188 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Tue, 9 Apr 2024 00:50:29 +0200
-Subject: [PATCH] phy: rockchip: add usbdp combo phy driver
-
-This adds a new USBDP combo PHY with Samsung IP block driver.
-
-The driver get lane mux and mapping info in 2 ways, supporting
-DisplayPort alternate mode or parsing from DT. When parsing from DT,
-the property "rockchip,dp-lane-mux" provide the DP mux and mapping
-info. This is needed when the PHY is not used with TypeC Alt-Mode.
-For example if the USB3 interface of the PHY is connected to a USB
-Type A connector and the DP interface is connected to a DisplayPort
-connector.
-
-When do DP link training, need to set lane number, link rate, swing,
-and pre-emphasis via PHY configure interface.
-
-Co-developed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-Co-developed-by: Zhang Yubing <yubing.zhang@rock-chips.com>
-Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
-Co-developed-by: Frank Wang <frank.wang@rock-chips.com>
-Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240408225109.128953-3-sebastian.reichel@collabora.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/Kconfig | 12 +
- drivers/phy/rockchip/Makefile | 1 +
- drivers/phy/rockchip/phy-rockchip-usbdp.c | 1608 +++++++++++++++++++++
- 3 files changed, 1621 insertions(+)
- create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
-
---- a/drivers/phy/rockchip/Kconfig
-+++ b/drivers/phy/rockchip/Kconfig
-@@ -107,3 +107,15 @@ config PHY_ROCKCHIP_USB
- select GENERIC_PHY
- help
- Enable this to support the Rockchip USB 2.0 PHY.
-+
-+config PHY_ROCKCHIP_USBDP
-+ tristate "Rockchip USBDP COMBO PHY Driver"
-+ depends on ARCH_ROCKCHIP && OF
-+ select GENERIC_PHY
-+ select TYPEC
-+ help
-+ Enable this to support the Rockchip USB3.0/DP combo PHY with
-+ Samsung IP block. This is required for USB3 support on RK3588.
-+
-+ To compile this driver as a module, choose M here: the module
-+ will be called phy-rockchip-usbdp
---- a/drivers/phy/rockchip/Makefile
-+++ b/drivers/phy/rockchip/Makefile
-@@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-
- obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
- obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
- obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
-+obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
---- /dev/null
-+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
-@@ -0,0 +1,1608 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later
-+/*
-+ * Rockchip USBDP Combo PHY with Samsung IP block driver
-+ *
-+ * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
-+ * Copyright (C) 2024 Collabora Ltd
-+ */
-+
-+#include <dt-bindings/phy/phy.h>
-+#include <linux/bitfield.h>
-+#include <linux/bits.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/gpio.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+#include <linux/usb/ch9.h>
-+#include <linux/usb/typec_dp.h>
-+#include <linux/usb/typec_mux.h>
-+
-+/* USBDP PHY Register Definitions */
-+#define UDPHY_PCS 0x4000
-+#define UDPHY_PMA 0x8000
-+
-+/* VO0 GRF Registers */
-+#define DP_SINK_HPD_CFG BIT(11)
-+#define DP_SINK_HPD_SEL BIT(10)
-+#define DP_AUX_DIN_SEL BIT(9)
-+#define DP_AUX_DOUT_SEL BIT(8)
-+#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n))
-+#define DP_LANE_SEL_ALL GENMASK(7, 0)
-+
-+/* PMA CMN Registers */
-+#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
-+#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4)
-+#define CMN_DP_LANE_EN_N(n) BIT(n)
-+#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4)
-+#define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
-+
-+#define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */
-+#define CMN_DP_TX_LINK_BW GENMASK(6, 5)
-+#define CMN_DP_TX_LANE_SWAP_EN BIT(2)
-+
-+#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
-+#define CMN_ROPLL_SSC_EN BIT(1)
-+#define CMN_LCPLL_SSC_EN BIT(0)
-+
-+#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
-+#define CMN_ANA_LCPLL_LOCK_DONE BIT(7)
-+#define CMN_ANA_LCPLL_AFC_DONE BIT(6)
-+
-+#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
-+#define CMN_ANA_ROPLL_LOCK_DONE BIT(1)
-+#define CMN_ANA_ROPLL_AFC_DONE BIT(0)
-+
-+#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */
-+#define CMN_DP_INIT_RSTN BIT(3)
-+#define CMN_DP_CMN_RSTN BIT(2)
-+#define CMN_CDR_WTCHDG_EN BIT(1)
-+#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0)
-+
-+#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */
-+#define LN_ANA_TX_SER_TXCLK_INV BIT(1)
-+
-+#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */
-+#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0)
-+
-+#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */
-+#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0)
-+
-+#define BIT_WRITEABLE_SHIFT 16
-+#define PHY_AUX_DP_DATA_POL_NORMAL 0
-+#define PHY_AUX_DP_DATA_POL_INVERT 1
-+#define PHY_LANE_MUX_USB 0
-+#define PHY_LANE_MUX_DP 1
-+
-+enum {
-+ DP_BW_RBR,
-+ DP_BW_HBR,
-+ DP_BW_HBR2,
-+ DP_BW_HBR3,
-+};
-+
-+enum {
-+ UDPHY_MODE_NONE = 0,
-+ UDPHY_MODE_USB = BIT(0),
-+ UDPHY_MODE_DP = BIT(1),
-+ UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
-+};
-+
-+struct rk_udphy_grf_reg {
-+ unsigned int offset;
-+ unsigned int disable;
-+ unsigned int enable;
-+};
-+
-+#define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \
-+{\
-+ offset, \
-+ FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \
-+ FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \
-+}
-+
-+#define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \
-+ _RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable)
-+
-+struct rk_udphy_grf_cfg {
-+ /* u2phy-grf */
-+ struct rk_udphy_grf_reg bvalid_phy_con;
-+ struct rk_udphy_grf_reg bvalid_grf_con;
-+
-+ /* usb-grf */
-+ struct rk_udphy_grf_reg usb3otg0_cfg;
-+ struct rk_udphy_grf_reg usb3otg1_cfg;
-+
-+ /* usbdpphy-grf */
-+ struct rk_udphy_grf_reg low_pwrn;
-+ struct rk_udphy_grf_reg rx_lfps;
-+};
-+
-+struct rk_udphy_vogrf_cfg {
-+ /* vo-grf */
-+ struct rk_udphy_grf_reg hpd_trigger;
-+ u32 dp_lane_reg;
-+};
-+
-+struct rk_udphy_dp_tx_drv_ctrl {
-+ u32 trsv_reg0204;
-+ u32 trsv_reg0205;
-+ u32 trsv_reg0206;
-+ u32 trsv_reg0207;
-+};
-+
-+struct rk_udphy_cfg {
-+ unsigned int num_phys;
-+ unsigned int phy_ids[2];
-+ /* resets to be requested */
-+ const char * const *rst_list;
-+ int num_rsts;
-+
-+ struct rk_udphy_grf_cfg grfcfg;
-+ struct rk_udphy_vogrf_cfg vogrfcfg[2];
-+ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4];
-+ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4];
-+};
-+
-+struct rk_udphy {
-+ struct device *dev;
-+ struct regmap *pma_regmap;
-+ struct regmap *u2phygrf;
-+ struct regmap *udphygrf;
-+ struct regmap *usbgrf;
-+ struct regmap *vogrf;
-+ struct typec_switch_dev *sw;
-+ struct typec_mux_dev *mux;
-+ struct mutex mutex; /* mutex to protect access to individual PHYs */
-+
-+ /* clocks and rests */
-+ int num_clks;
-+ struct clk_bulk_data *clks;
-+ struct clk *refclk;
-+ int num_rsts;
-+ struct reset_control_bulk_data *rsts;
-+
-+ /* PHY status management */
-+ bool flip;
-+ bool mode_change;
-+ u8 mode;
-+ u8 status;
-+
-+ /* utilized for USB */
-+ bool hs; /* flag for high-speed */
-+
-+ /* utilized for DP */
-+ struct gpio_desc *sbu1_dc_gpio;
-+ struct gpio_desc *sbu2_dc_gpio;
-+ u32 lane_mux_sel[4];
-+ u32 dp_lane_sel[4];
-+ u32 dp_aux_dout_sel;
-+ u32 dp_aux_din_sel;
-+ bool dp_sink_hpd_sel;
-+ bool dp_sink_hpd_cfg;
-+ u8 bw;
-+ int id;
-+
-+ bool dp_in_use;
-+
-+ /* PHY const config */
-+ const struct rk_udphy_cfg *cfgs;
-+
-+ /* PHY devices */
-+ struct phy *phy_dp;
-+ struct phy *phy_u3;
-+};
-+
-+static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = {
-+ /* voltage swing 0, pre-emphasis 0->3 */
-+ {
-+ { 0x20, 0x10, 0x42, 0xe5 },
-+ { 0x26, 0x14, 0x42, 0xe5 },
-+ { 0x29, 0x18, 0x42, 0xe5 },
-+ { 0x2b, 0x1c, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 1, pre-emphasis 0->2 */
-+ {
-+ { 0x23, 0x10, 0x42, 0xe7 },
-+ { 0x2a, 0x17, 0x43, 0xe7 },
-+ { 0x2b, 0x1a, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 2, pre-emphasis 0->1 */
-+ {
-+ { 0x27, 0x10, 0x42, 0xe7 },
-+ { 0x2b, 0x17, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 3, pre-emphasis 0 */
-+ {
-+ { 0x29, 0x10, 0x43, 0xe7 },
-+ },
-+};
-+
-+static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = {
-+ /* voltage swing 0, pre-emphasis 0->3 */
-+ {
-+ { 0x20, 0x10, 0x42, 0xe5 },
-+ { 0x26, 0x14, 0x42, 0xe5 },
-+ { 0x29, 0x18, 0x42, 0xe5 },
-+ { 0x2b, 0x1c, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 1, pre-emphasis 0->2 */
-+ {
-+ { 0x23, 0x10, 0x42, 0xe7 },
-+ { 0x2a, 0x17, 0x43, 0xe7 },
-+ { 0x2b, 0x1a, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 2, pre-emphasis 0->1 */
-+ {
-+ { 0x27, 0x10, 0x43, 0x67 },
-+ { 0x2b, 0x17, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 3, pre-emphasis 0 */
-+ {
-+ { 0x29, 0x10, 0x43, 0xe7 },
-+ },
-+};
-+
-+static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = {
-+ /* voltage swing 0, pre-emphasis 0->3 */
-+ {
-+ { 0x21, 0x10, 0x42, 0xe5 },
-+ { 0x26, 0x14, 0x42, 0xe5 },
-+ { 0x26, 0x16, 0x43, 0xe5 },
-+ { 0x2a, 0x19, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 1, pre-emphasis 0->2 */
-+ {
-+ { 0x24, 0x10, 0x42, 0xe7 },
-+ { 0x2a, 0x17, 0x43, 0xe7 },
-+ { 0x2b, 0x1a, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 2, pre-emphasis 0->1 */
-+ {
-+ { 0x28, 0x10, 0x42, 0xe7 },
-+ { 0x2b, 0x17, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 3, pre-emphasis 0 */
-+ {
-+ { 0x28, 0x10, 0x43, 0xe7 },
-+ },
-+};
-+
-+static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = {
-+ /* voltage swing 0, pre-emphasis 0->3 */
-+ {
-+ { 0x21, 0x10, 0x42, 0xe5 },
-+ { 0x26, 0x14, 0x42, 0xe5 },
-+ { 0x26, 0x16, 0x43, 0xe5 },
-+ { 0x29, 0x18, 0x43, 0xe7 },
-+ },
-+
-+ /* voltage swing 1, pre-emphasis 0->2 */
-+ {
-+ { 0x24, 0x10, 0x42, 0xe7 },
-+ { 0x2a, 0x18, 0x43, 0xe7 },
-+ { 0x2b, 0x1b, 0x43, 0xe7 }
-+ },
-+
-+ /* voltage swing 2, pre-emphasis 0->1 */
-+ {
-+ { 0x27, 0x10, 0x42, 0xe7 },
-+ { 0x2b, 0x18, 0x43, 0xe7 }
-+ },
-+
-+ /* voltage swing 3, pre-emphasis 0 */
-+ {
-+ { 0x28, 0x10, 0x43, 0xe7 },
-+ },
-+};
-+
-+static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = {
-+ {0x0090, 0x68}, {0x0094, 0x68},
-+ {0x0128, 0x24}, {0x012c, 0x44},
-+ {0x0130, 0x3f}, {0x0134, 0x44},
-+ {0x015c, 0xa9}, {0x0160, 0x71},
-+ {0x0164, 0x71}, {0x0168, 0xa9},
-+ {0x0174, 0xa9}, {0x0178, 0x71},
-+ {0x017c, 0x71}, {0x0180, 0xa9},
-+ {0x018c, 0x41}, {0x0190, 0x00},
-+ {0x0194, 0x05}, {0x01ac, 0x2a},
-+ {0x01b0, 0x17}, {0x01b4, 0x17},
-+ {0x01b8, 0x2a}, {0x01c8, 0x04},
-+ {0x01cc, 0x08}, {0x01d0, 0x08},
-+ {0x01d4, 0x04}, {0x01d8, 0x20},
-+ {0x01dc, 0x01}, {0x01e0, 0x09},
-+ {0x01e4, 0x03}, {0x01f0, 0x29},
-+ {0x01f4, 0x02}, {0x01f8, 0x02},
-+ {0x01fc, 0x29}, {0x0208, 0x2a},
-+ {0x020c, 0x17}, {0x0210, 0x17},
-+ {0x0214, 0x2a}, {0x0224, 0x20},
-+ {0x03f0, 0x0a}, {0x03f4, 0x07},
-+ {0x03f8, 0x07}, {0x03fc, 0x0c},
-+ {0x0404, 0x12}, {0x0408, 0x1a},
-+ {0x040c, 0x1a}, {0x0410, 0x3f},
-+ {0x0ce0, 0x68}, {0x0ce8, 0xd0},
-+ {0x0cf0, 0x87}, {0x0cf8, 0x70},
-+ {0x0d00, 0x70}, {0x0d08, 0xa9},
-+ {0x1ce0, 0x68}, {0x1ce8, 0xd0},
-+ {0x1cf0, 0x87}, {0x1cf8, 0x70},
-+ {0x1d00, 0x70}, {0x1d08, 0xa9},
-+ {0x0a3c, 0xd0}, {0x0a44, 0xd0},
-+ {0x0a48, 0x01}, {0x0a4c, 0x0d},
-+ {0x0a54, 0xe0}, {0x0a5c, 0xe0},
-+ {0x0a64, 0xa8}, {0x1a3c, 0xd0},
-+ {0x1a44, 0xd0}, {0x1a48, 0x01},
-+ {0x1a4c, 0x0d}, {0x1a54, 0xe0},
-+ {0x1a5c, 0xe0}, {0x1a64, 0xa8}
-+};
-+
-+static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = {
-+ {0x0830, 0x07}, {0x085c, 0x80},
-+ {0x1030, 0x07}, {0x105c, 0x80},
-+ {0x1830, 0x07}, {0x185c, 0x80},
-+ {0x2030, 0x07}, {0x205c, 0x80},
-+ {0x0228, 0x38}, {0x0104, 0x44},
-+ {0x0248, 0x44}, {0x038c, 0x02},
-+ {0x0878, 0x04}, {0x1878, 0x04},
-+ {0x0898, 0x77}, {0x1898, 0x77},
-+ {0x0054, 0x01}, {0x00e0, 0x38},
-+ {0x0060, 0x24}, {0x0064, 0x77},
-+ {0x0070, 0x76}, {0x0234, 0xe8},
-+ {0x0af4, 0x15}, {0x1af4, 0x15},
-+ {0x081c, 0xe5}, {0x181c, 0xe5},
-+ {0x099c, 0x48}, {0x199c, 0x48},
-+ {0x09a4, 0x07}, {0x09a8, 0x22},
-+ {0x19a4, 0x07}, {0x19a8, 0x22},
-+ {0x09b8, 0x3e}, {0x19b8, 0x3e},
-+ {0x09e4, 0x02}, {0x19e4, 0x02},
-+ {0x0a34, 0x1e}, {0x1a34, 0x1e},
-+ {0x0a98, 0x2f}, {0x1a98, 0x2f},
-+ {0x0c30, 0x0e}, {0x0c48, 0x06},
-+ {0x1c30, 0x0e}, {0x1c48, 0x06},
-+ {0x028c, 0x18}, {0x0af0, 0x00},
-+ {0x1af0, 0x00}
-+};
-+
-+static const struct reg_sequence rk_udphy_init_sequence[] = {
-+ {0x0104, 0x44}, {0x0234, 0xe8},
-+ {0x0248, 0x44}, {0x028c, 0x18},
-+ {0x081c, 0xe5}, {0x0878, 0x00},
-+ {0x0994, 0x1c}, {0x0af0, 0x00},
-+ {0x181c, 0xe5}, {0x1878, 0x00},
-+ {0x1994, 0x1c}, {0x1af0, 0x00},
-+ {0x0428, 0x60}, {0x0d58, 0x33},
-+ {0x1d58, 0x33}, {0x0990, 0x74},
-+ {0x0d64, 0x17}, {0x08c8, 0x13},
-+ {0x1990, 0x74}, {0x1d64, 0x17},
-+ {0x18c8, 0x13}, {0x0d90, 0x40},
-+ {0x0da8, 0x40}, {0x0dc0, 0x40},
-+ {0x0dd8, 0x40}, {0x1d90, 0x40},
-+ {0x1da8, 0x40}, {0x1dc0, 0x40},
-+ {0x1dd8, 0x40}, {0x03c0, 0x30},
-+ {0x03c4, 0x06}, {0x0e10, 0x00},
-+ {0x1e10, 0x00}, {0x043c, 0x0f},
-+ {0x0d2c, 0xff}, {0x1d2c, 0xff},
-+ {0x0d34, 0x0f}, {0x1d34, 0x0f},
-+ {0x08fc, 0x2a}, {0x0914, 0x28},
-+ {0x0a30, 0x03}, {0x0e38, 0x03},
-+ {0x0ecc, 0x27}, {0x0ed0, 0x22},
-+ {0x0ed4, 0x26}, {0x18fc, 0x2a},
-+ {0x1914, 0x28}, {0x1a30, 0x03},
-+ {0x1e38, 0x03}, {0x1ecc, 0x27},
-+ {0x1ed0, 0x22}, {0x1ed4, 0x26},
-+ {0x0048, 0x0f}, {0x0060, 0x3c},
-+ {0x0064, 0xf7}, {0x006c, 0x20},
-+ {0x0070, 0x7d}, {0x0074, 0x68},
-+ {0x0af4, 0x1a}, {0x1af4, 0x1a},
-+ {0x0440, 0x3f}, {0x10d4, 0x08},
-+ {0x20d4, 0x08}, {0x00d4, 0x30},
-+ {0x0024, 0x6e},
-+};
-+
-+static inline int rk_udphy_grfreg_write(struct regmap *base,
-+ const struct rk_udphy_grf_reg *reg, bool en)
-+{
-+ return regmap_write(base, reg->offset, en ? reg->enable : reg->disable);
-+}
-+
-+static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev)
-+{
-+ int i;
-+
-+ udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks);
-+ if (udphy->num_clks < 1)
-+ return -ENODEV;
-+
-+ /* used for configure phy reference clock frequency */
-+ for (i = 0; i < udphy->num_clks; i++) {
-+ if (!strncmp(udphy->clks[i].id, "refclk", 6)) {
-+ udphy->refclk = udphy->clks[i].clk;
-+ break;
-+ }
-+ }
-+
-+ if (!udphy->refclk)
-+ return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n");
-+
-+ return 0;
-+}
-+
-+static int rk_udphy_reset_assert_all(struct rk_udphy *udphy)
-+{
-+ return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts);
-+}
-+
-+static int rk_udphy_reset_deassert_all(struct rk_udphy *udphy)
-+{
-+ return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts);
-+}
-+
-+static int rk_udphy_reset_deassert(struct rk_udphy *udphy, char *name)
-+{
-+ struct reset_control_bulk_data *list = udphy->rsts;
-+ int idx;
-+
-+ for (idx = 0; idx < udphy->num_rsts; idx++) {
-+ if (!strcmp(list[idx].id, name))
-+ return reset_control_deassert(list[idx].rstc);
-+ }
-+
-+ return -EINVAL;
-+}
-+
-+static int rk_udphy_reset_init(struct rk_udphy *udphy, struct device *dev)
-+{
-+ const struct rk_udphy_cfg *cfg = udphy->cfgs;
-+ int idx;
-+
-+ udphy->num_rsts = cfg->num_rsts;
-+ udphy->rsts = devm_kcalloc(dev, udphy->num_rsts,
-+ sizeof(*udphy->rsts), GFP_KERNEL);
-+ if (!udphy->rsts)
-+ return -ENOMEM;
-+
-+ for (idx = 0; idx < cfg->num_rsts; idx++)
-+ udphy->rsts[idx].id = cfg->rst_list[idx];
-+
-+ return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts,
-+ udphy->rsts);
-+}
-+
-+static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable)
-+{
-+ const struct rk_udphy_cfg *cfg = udphy->cfgs;
-+ const struct rk_udphy_grf_reg *preg;
-+
-+ preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
-+ rk_udphy_grfreg_write(udphy->usbgrf, preg, disable);
-+}
-+
-+static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable)
-+{
-+ const struct rk_udphy_cfg *cfg = udphy->cfgs;
-+
-+ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
-+ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
-+}
-+
-+/*
-+ * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
-+ *
-+ * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
-+ * ---------------------------------------------------------------------------
-+ * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
-+ * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
-+ * C/E(Normal) dpln3 dpln2 dpln0 dpln1
-+ * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
-+ * D/F(Normal) usbrx usbtx dpln0 dpln1
-+ * D/F(Flip ) dpln0 dpln1 usbrx usbtx
-+ * A(Normal ) dpln3 dpln1 dpln2 dpln0
-+ * A(Flip ) dpln2 dpln0 dpln3 dpln1
-+ * B(Normal ) usbrx usbtx dpln1 dpln0
-+ * B(Flip ) dpln1 dpln0 usbrx usbtx
-+ * ---------------------------------------------------------------------------
-+ *
-+ * 2 Mapping the lanes in dtsi
-+ * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
-+ * sample as follow:
-+ * ---------------------------------------------------------------------------
-+ * B11-B10 A2-A3 A11-A10 B2-B3
-+ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
-+ * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
-+ * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
-+ * ---------------------------------------------------------------------------
-+ * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
-+ * sample as follow:
-+ * ---------------------------------------------------------------------------
-+ * B11-B10 A2-A3 A11-A10 B2-B3
-+ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
-+ * <0 1> dpln0 dpln1 usbrx usbtx
-+ * <2 3> usbrx usbtx dpln0 dpln1
-+ * ---------------------------------------------------------------------------
-+ */
-+
-+static void rk_udphy_dplane_select(struct rk_udphy *udphy)
-+{
-+ const struct rk_udphy_cfg *cfg = udphy->cfgs;
-+ u32 value = 0;
-+
-+ switch (udphy->mode) {
-+ case UDPHY_MODE_DP:
-+ value |= 2 << udphy->dp_lane_sel[2] * 2;
-+ value |= 3 << udphy->dp_lane_sel[3] * 2;
-+ fallthrough;
-+
-+ case UDPHY_MODE_DP_USB:
-+ value |= 0 << udphy->dp_lane_sel[0] * 2;
-+ value |= 1 << udphy->dp_lane_sel[1] * 2;
-+ break;
-+
-+ case UDPHY_MODE_USB:
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg,
-+ ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
-+ FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
-+ FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
-+}
-+
-+static int rk_udphy_dplane_get(struct rk_udphy *udphy)
-+{
-+ int dp_lanes;
-+
-+ switch (udphy->mode) {
-+ case UDPHY_MODE_DP:
-+ dp_lanes = 4;
-+ break;
-+
-+ case UDPHY_MODE_DP_USB:
-+ dp_lanes = 2;
-+ break;
-+
-+ case UDPHY_MODE_USB:
-+ default:
-+ dp_lanes = 0;
-+ break;
-+ }
-+
-+ return dp_lanes;
-+}
-+
-+static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes)
-+{
-+ u32 val = 0;
-+ int i;
-+
-+ for (i = 0; i < dp_lanes; i++)
-+ val |= BIT(udphy->dp_lane_sel[i]);
-+
-+ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,
-+ FIELD_PREP(CMN_DP_LANE_EN_ALL, val));
-+
-+ if (!dp_lanes)
-+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
-+ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
-+}
-+
-+static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd)
-+{
-+ const struct rk_udphy_cfg *cfg = udphy->cfgs;
-+
-+ udphy->dp_sink_hpd_sel = true;
-+ udphy->dp_sink_hpd_cfg = hpd;
-+
-+ if (!udphy->dp_in_use)
-+ return;
-+
-+ rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
-+}
-+
-+static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
-+{
-+ if (udphy->flip) {
-+ udphy->dp_lane_sel[0] = 0;
-+ udphy->dp_lane_sel[1] = 1;
-+ udphy->dp_lane_sel[2] = 3;
-+ udphy->dp_lane_sel[3] = 2;
-+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
-+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
-+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
-+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
-+ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
-+ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
-+ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1);
-+ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
-+ } else {
-+ udphy->dp_lane_sel[0] = 2;
-+ udphy->dp_lane_sel[1] = 3;
-+ udphy->dp_lane_sel[2] = 1;
-+ udphy->dp_lane_sel[3] = 0;
-+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
-+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
-+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
-+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
-+ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
-+ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
-+ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
-+ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1);
-+ }
-+
-+ udphy->mode = UDPHY_MODE_DP_USB;
-+}
-+
-+static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
-+ enum typec_orientation orien)
-+{
-+ struct rk_udphy *udphy = typec_switch_get_drvdata(sw);
-+
-+ mutex_lock(&udphy->mutex);
-+
-+ if (orien == TYPEC_ORIENTATION_NONE) {
-+ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
-+ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
-+ /* unattached */
-+ rk_udphy_usb_bvalid_enable(udphy, false);
-+ goto unlock_ret;
-+ }
-+
-+ udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false;
-+ rk_udphy_set_typec_default_mapping(udphy);
-+ rk_udphy_usb_bvalid_enable(udphy, true);
-+
-+unlock_ret:
-+ mutex_unlock(&udphy->mutex);
-+ return 0;
-+}
-+
-+static void rk_udphy_orien_switch_unregister(void *data)
-+{
-+ struct rk_udphy *udphy = data;
-+
-+ typec_switch_unregister(udphy->sw);
-+}
-+
-+static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy)
-+{
-+ struct typec_switch_desc sw_desc = { };
-+
-+ sw_desc.drvdata = udphy;
-+ sw_desc.fwnode = dev_fwnode(udphy->dev);
-+ sw_desc.set = rk_udphy_orien_sw_set;
-+
-+ udphy->sw = typec_switch_register(udphy->dev, &sw_desc);
-+ if (IS_ERR(udphy->sw)) {
-+ dev_err(udphy->dev, "Error register typec orientation switch: %ld\n",
-+ PTR_ERR(udphy->sw));
-+ return PTR_ERR(udphy->sw);
-+ }
-+
-+ return devm_add_action_or_reset(udphy->dev,
-+ rk_udphy_orien_switch_unregister, udphy);
-+}
-+
-+static int rk_udphy_refclk_set(struct rk_udphy *udphy)
-+{
-+ unsigned long rate;
-+ int ret;
-+
-+ /* configure phy reference clock */
-+ rate = clk_get_rate(udphy->refclk);
-+ dev_dbg(udphy->dev, "refclk freq %ld\n", rate);
-+
-+ switch (rate) {
-+ case 24000000:
-+ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cfg,
-+ ARRAY_SIZE(rk_udphy_24m_refclk_cfg));
-+ if (ret)
-+ return ret;
-+ break;
-+
-+ case 26000000:
-+ /* register default is 26MHz */
-+ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg,
-+ ARRAY_SIZE(rk_udphy_26m_refclk_cfg));
-+ if (ret)
-+ return ret;
-+ break;
-+
-+ default:
-+ dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static int rk_udphy_status_check(struct rk_udphy *udphy)
-+{
-+ unsigned int val;
-+ int ret;
-+
-+ /* LCPLL check */
-+ if (udphy->mode & UDPHY_MODE_USB) {
-+ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,
-+ val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
-+ (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000);
-+ if (ret) {
-+ dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
-+ /*
-+ * If earlier software (U-Boot) enabled USB once already
-+ * the PLL may have problems locking on the first try.
-+ * It will be successful on the second try, so for the
-+ * time being a -EPROBE_DEFER will solve the issue.
-+ *
-+ * This requires further investigation to understand the
-+ * root cause, especially considering that the driver is
-+ * asserting all reset lines at probe time.
-+ */
-+ return -EPROBE_DEFER;
-+ }
-+
-+ if (!udphy->flip) {
-+ ret = regmap_read_poll_timeout(udphy->pma_regmap,
-+ TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val,
-+ val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
-+ 200, 100000);
-+ if (ret)
-+ dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
-+ } else {
-+ ret = regmap_read_poll_timeout(udphy->pma_regmap,
-+ TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
-+ val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
-+ 200, 100000);
-+ if (ret)
-+ dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int rk_udphy_init(struct rk_udphy *udphy)
-+{
-+ const struct rk_udphy_cfg *cfg = udphy->cfgs;
-+ int ret;
-+
-+ rk_udphy_reset_assert_all(udphy);
-+ usleep_range(10000, 11000);
-+
-+ /* enable rx lfps for usb */
-+ if (udphy->mode & UDPHY_MODE_USB)
-+ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
-+
-+ /* Step 1: power on pma and deassert apb rstn */
-+ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
-+
-+ rk_udphy_reset_deassert(udphy, "pma_apb");
-+ rk_udphy_reset_deassert(udphy, "pcs_apb");
-+
-+ /* Step 2: set init sequence and phy refclk */
-+ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence,
-+ ARRAY_SIZE(rk_udphy_init_sequence));
-+ if (ret) {
-+ dev_err(udphy->dev, "init sequence set error %d\n", ret);
-+ goto assert_resets;
-+ }
-+
-+ ret = rk_udphy_refclk_set(udphy);
-+ if (ret) {
-+ dev_err(udphy->dev, "refclk set error %d\n", ret);
-+ goto assert_resets;
-+ }
-+
-+ /* Step 3: configure lane mux */
-+ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
-+ CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
-+ FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |
-+ FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |
-+ FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |
-+ FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |
-+ FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
-+
-+ /* Step 4: deassert init rstn and wait for 200ns from datasheet */
-+ if (udphy->mode & UDPHY_MODE_USB)
-+ rk_udphy_reset_deassert(udphy, "init");
-+
-+ if (udphy->mode & UDPHY_MODE_DP) {
-+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
-+ CMN_DP_INIT_RSTN,
-+ FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
-+ }
-+
-+ udelay(1);
-+
-+ /* Step 5: deassert cmn/lane rstn */
-+ if (udphy->mode & UDPHY_MODE_USB) {
-+ rk_udphy_reset_deassert(udphy, "cmn");
-+ rk_udphy_reset_deassert(udphy, "lane");
-+ }
-+
-+ /* Step 6: wait for lock done of pll */
-+ ret = rk_udphy_status_check(udphy);
-+ if (ret)
-+ goto assert_resets;
-+
-+ return 0;
-+
-+assert_resets:
-+ rk_udphy_reset_assert_all(udphy);
-+ return ret;
-+}
-+
-+static int rk_udphy_setup(struct rk_udphy *udphy)
-+{
-+ int ret;
-+
-+ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
-+ if (ret) {
-+ dev_err(udphy->dev, "failed to enable clk\n");
-+ return ret;
-+ }
-+
-+ ret = rk_udphy_init(udphy);
-+ if (ret) {
-+ dev_err(udphy->dev, "failed to init combophy\n");
-+ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static void rk_udphy_disable(struct rk_udphy *udphy)
-+{
-+ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
-+ rk_udphy_reset_assert_all(udphy);
-+}
-+
-+static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy)
-+{
-+ int ret, i, num_lanes;
-+
-+ num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux");
-+ if (num_lanes < 0) {
-+ dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n");
-+ udphy->mode = UDPHY_MODE_USB;
-+ return 0;
-+ }
-+
-+ if (num_lanes != 2 && num_lanes != 4)
-+ return dev_err_probe(udphy->dev, -EINVAL,
-+ "invalid number of lane mux\n");
-+
-+ ret = device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux",
-+ udphy->dp_lane_sel, num_lanes);
-+ if (ret)
-+ return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n");
-+
-+ for (i = 0; i < num_lanes; i++) {
-+ int j;
-+
-+ if (udphy->dp_lane_sel[i] > 3)
-+ return dev_err_probe(udphy->dev, -EINVAL,
-+ "lane mux between 0 and 3, exceeding the range\n");
-+
-+ udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
-+
-+ for (j = i + 1; j < num_lanes; j++) {
-+ if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j])
-+ return dev_err_probe(udphy->dev, -EINVAL,
-+ "set repeat lane mux value\n");
-+ }
-+ }
-+
-+ udphy->mode = UDPHY_MODE_DP;
-+ if (num_lanes == 2) {
-+ udphy->mode |= UDPHY_MODE_USB;
-+ udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP);
-+ }
-+
-+ return 0;
-+}
-+
-+static int rk_udphy_get_initial_status(struct rk_udphy *udphy)
-+{
-+ int ret;
-+ u32 value;
-+
-+ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
-+ if (ret) {
-+ dev_err(udphy->dev, "failed to enable clk\n");
-+ return ret;
-+ }
-+
-+ rk_udphy_reset_deassert_all(udphy);
-+
-+ regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value);
-+ if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value))
-+ udphy->status = UDPHY_MODE_DP;
-+ else
-+ rk_udphy_disable(udphy);
-+
-+ return 0;
-+}
-+
-+static int rk_udphy_parse_dt(struct rk_udphy *udphy)
-+{
-+ struct device *dev = udphy->dev;
-+ struct device_node *np = dev_of_node(dev);
-+ enum usb_device_speed maximum_speed;
-+ int ret;
-+
-+ udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf");
-+ if (IS_ERR(udphy->u2phygrf))
-+ return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy-grf\n");
-+
-+ udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf");
-+ if (IS_ERR(udphy->udphygrf))
-+ return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdpphy-grf\n");
-+
-+ udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf");
-+ if (IS_ERR(udphy->usbgrf))
-+ return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf\n");
-+
-+ udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf");
-+ if (IS_ERR(udphy->vogrf))
-+ return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n");
-+
-+ ret = rk_udphy_parse_lane_mux_data(udphy);
-+ if (ret)
-+ return ret;
-+
-+ udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW);
-+ if (IS_ERR(udphy->sbu1_dc_gpio))
-+ return PTR_ERR(udphy->sbu1_dc_gpio);
-+
-+ udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW);
-+ if (IS_ERR(udphy->sbu2_dc_gpio))
-+ return PTR_ERR(udphy->sbu2_dc_gpio);
-+
-+ if (device_property_present(dev, "maximum-speed")) {
-+ maximum_speed = usb_get_maximum_speed(dev);
-+ udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
-+ }
-+
-+ ret = rk_udphy_clk_init(udphy, dev);
-+ if (ret)
-+ return ret;
-+
-+ return rk_udphy_reset_init(udphy, dev);
-+}
-+
-+static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
-+{
-+ int ret;
-+
-+ if (!(udphy->mode & mode)) {
-+ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
-+ return 0;
-+ }
-+
-+ if (udphy->status == UDPHY_MODE_NONE) {
-+ udphy->mode_change = false;
-+ ret = rk_udphy_setup(udphy);
-+ if (ret)
-+ return ret;
-+
-+ if (udphy->mode & UDPHY_MODE_USB)
-+ rk_udphy_u3_port_disable(udphy, false);
-+ } else if (udphy->mode_change) {
-+ udphy->mode_change = false;
-+ udphy->status = UDPHY_MODE_NONE;
-+ if (udphy->mode == UDPHY_MODE_DP)
-+ rk_udphy_u3_port_disable(udphy, true);
-+
-+ rk_udphy_disable(udphy);
-+ ret = rk_udphy_setup(udphy);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ udphy->status |= mode;
-+
-+ return 0;
-+}
-+
-+static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode)
-+{
-+ if (!(udphy->mode & mode)) {
-+ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
-+ return;
-+ }
-+
-+ if (!udphy->status)
-+ return;
-+
-+ udphy->status &= ~mode;
-+
-+ if (udphy->status == UDPHY_MODE_NONE)
-+ rk_udphy_disable(udphy);
-+}
-+
-+static int rk_udphy_dp_phy_init(struct phy *phy)
-+{
-+ struct rk_udphy *udphy = phy_get_drvdata(phy);
-+
-+ mutex_lock(&udphy->mutex);
-+
-+ udphy->dp_in_use = true;
-+ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
-+
-+ mutex_unlock(&udphy->mutex);
-+
-+ return 0;
-+}
-+
-+static int rk_udphy_dp_phy_exit(struct phy *phy)
-+{
-+ struct rk_udphy *udphy = phy_get_drvdata(phy);
-+
-+ mutex_lock(&udphy->mutex);
-+ udphy->dp_in_use = false;
-+ mutex_unlock(&udphy->mutex);
-+ return 0;
-+}
-+
-+static int rk_udphy_dp_phy_power_on(struct phy *phy)
-+{
-+ struct rk_udphy *udphy = phy_get_drvdata(phy);
-+ int ret, dp_lanes;
-+
-+ mutex_lock(&udphy->mutex);
-+
-+ dp_lanes = rk_udphy_dplane_get(udphy);
-+ phy_set_bus_width(phy, dp_lanes);
-+
-+ ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP);
-+ if (ret)
-+ goto unlock;
-+
-+ rk_udphy_dplane_enable(udphy, dp_lanes);
-+
-+ rk_udphy_dplane_select(udphy);
-+
-+unlock:
-+ mutex_unlock(&udphy->mutex);
-+ /*
-+ * If data send by aux channel too fast after phy power on,
-+ * the aux may be not ready which will cause aux error. Adding
-+ * delay to avoid this issue.
-+ */
-+ usleep_range(10000, 11000);
-+ return ret;
-+}
-+
-+static int rk_udphy_dp_phy_power_off(struct phy *phy)
-+{
-+ struct rk_udphy *udphy = phy_get_drvdata(phy);
-+
-+ mutex_lock(&udphy->mutex);
-+ rk_udphy_dplane_enable(udphy, 0);
-+ rk_udphy_power_off(udphy, UDPHY_MODE_DP);
-+ mutex_unlock(&udphy->mutex);
-+
-+ return 0;
-+}
-+
-+static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate)
-+{
-+ switch (link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ break;
-+
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static int rk_udphy_dp_phy_verify_config(struct rk_udphy *udphy,
-+ struct phy_configure_opts_dp *dp)
-+{
-+ int i, ret;
-+
-+ /* If changing link rate was required, verify it's supported. */
-+ ret = rk_udphy_dp_phy_verify_link_rate(dp->link_rate);
-+ if (ret)
-+ return ret;
-+
-+ /* Verify lane count. */
-+ switch (dp->lanes) {
-+ case 1:
-+ case 2:
-+ case 4:
-+ /* valid lane count. */
-+ break;
-+
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ /*
-+ * If changing voltages is required, check swing and pre-emphasis
-+ * levels, per-lane.
-+ */
-+ if (dp->set_voltages) {
-+ /* Lane count verified previously. */
-+ for (i = 0; i < dp->lanes; i++) {
-+ if (dp->voltage[i] > 3 || dp->pre[i] > 3)
-+ return -EINVAL;
-+
-+ /*
-+ * Sum of voltage swing and pre-emphasis levels cannot
-+ * exceed 3.
-+ */
-+ if (dp->voltage[i] + dp->pre[i] > 3)
-+ return -EINVAL;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void rk_udphy_dp_set_voltage(struct rk_udphy *udphy, u8 bw,
-+ u32 voltage, u32 pre, u32 lane)
-+{
-+ const struct rk_udphy_cfg *cfg = udphy->cfgs;
-+ const struct rk_udphy_dp_tx_drv_ctrl (*dp_ctrl)[4];
-+ u32 offset = 0x800 * lane;
-+ u32 val;
-+
-+ if (udphy->mux)
-+ dp_ctrl = cfg->dp_tx_ctrl_cfg_typec[bw];
-+ else
-+ dp_ctrl = cfg->dp_tx_ctrl_cfg[bw];
-+
-+ val = dp_ctrl[voltage][pre].trsv_reg0204;
-+ regmap_write(udphy->pma_regmap, 0x0810 + offset, val);
-+
-+ val = dp_ctrl[voltage][pre].trsv_reg0205;
-+ regmap_write(udphy->pma_regmap, 0x0814 + offset, val);
-+
-+ val = dp_ctrl[voltage][pre].trsv_reg0206;
-+ regmap_write(udphy->pma_regmap, 0x0818 + offset, val);
-+
-+ val = dp_ctrl[voltage][pre].trsv_reg0207;
-+ regmap_write(udphy->pma_regmap, 0x081c + offset, val);
-+}
-+
-+static int rk_udphy_dp_phy_configure(struct phy *phy,
-+ union phy_configure_opts *opts)
-+{
-+ struct rk_udphy *udphy = phy_get_drvdata(phy);
-+ struct phy_configure_opts_dp *dp = &opts->dp;
-+ u32 i, val, lane;
-+ int ret;
-+
-+ ret = rk_udphy_dp_phy_verify_config(udphy, dp);
-+ if (ret)
-+ return ret;
-+
-+ if (dp->set_rate) {
-+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
-+ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
-+
-+ switch (dp->link_rate) {
-+ case 1620:
-+ udphy->bw = DP_BW_RBR;
-+ break;
-+
-+ case 2700:
-+ udphy->bw = DP_BW_HBR;
-+ break;
-+
-+ case 5400:
-+ udphy->bw = DP_BW_HBR2;
-+ break;
-+
-+ case 8100:
-+ udphy->bw = DP_BW_HBR3;
-+ break;
-+
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,
-+ FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw));
-+ regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,
-+ FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc));
-+ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,
-+ FIELD_PREP(CMN_DP_CMN_RSTN, 0x1));
-+
-+ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,
-+ FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) &&
-+ FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val),
-+ 0, 1000);
-+ if (ret) {
-+ dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n");
-+ return ret;
-+ }
-+ }
-+
-+ if (dp->set_voltages) {
-+ for (i = 0; i < dp->lanes; i++) {
-+ lane = udphy->dp_lane_sel[i];
-+ switch (dp->link_rate) {
-+ case 1620:
-+ case 2700:
-+ regmap_update_bits(udphy->pma_regmap,
-+ TRSV_ANA_TX_CLK_OFFSET_N(lane),
-+ LN_ANA_TX_SER_TXCLK_INV,
-+ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV,
-+ udphy->lane_mux_sel[lane]));
-+ break;
-+
-+ case 5400:
-+ case 8100:
-+ regmap_update_bits(udphy->pma_regmap,
-+ TRSV_ANA_TX_CLK_OFFSET_N(lane),
-+ LN_ANA_TX_SER_TXCLK_INV,
-+ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0));
-+ break;
-+ }
-+
-+ rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i],
-+ dp->pre[i], lane);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct phy_ops rk_udphy_dp_phy_ops = {
-+ .init = rk_udphy_dp_phy_init,
-+ .exit = rk_udphy_dp_phy_exit,
-+ .power_on = rk_udphy_dp_phy_power_on,
-+ .power_off = rk_udphy_dp_phy_power_off,
-+ .configure = rk_udphy_dp_phy_configure,
-+ .owner = THIS_MODULE,
-+};
-+
-+static int rk_udphy_usb3_phy_init(struct phy *phy)
-+{
-+ struct rk_udphy *udphy = phy_get_drvdata(phy);
-+ int ret;
-+
-+ mutex_lock(&udphy->mutex);
-+ /* DP only or high-speed, disable U3 port */
-+ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
-+ rk_udphy_u3_port_disable(udphy, true);
-+ goto unlock;
-+ }
-+
-+ ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB);
-+
-+unlock:
-+ mutex_unlock(&udphy->mutex);
-+ return ret;
-+}
-+
-+static int rk_udphy_usb3_phy_exit(struct phy *phy)
-+{
-+ struct rk_udphy *udphy = phy_get_drvdata(phy);
-+
-+ mutex_lock(&udphy->mutex);
-+ /* DP only or high-speed */
-+ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
-+ goto unlock;
-+
-+ rk_udphy_power_off(udphy, UDPHY_MODE_USB);
-+
-+unlock:
-+ mutex_unlock(&udphy->mutex);
-+ return 0;
-+}
-+
-+static const struct phy_ops rk_udphy_usb3_phy_ops = {
-+ .init = rk_udphy_usb3_phy_init,
-+ .exit = rk_udphy_usb3_phy_exit,
-+ .owner = THIS_MODULE,
-+};
-+
-+static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
-+ struct typec_mux_state *state)
-+{
-+ struct rk_udphy *udphy = typec_mux_get_drvdata(mux);
-+ u8 mode;
-+
-+ mutex_lock(&udphy->mutex);
-+
-+ switch (state->mode) {
-+ case TYPEC_DP_STATE_C:
-+ case TYPEC_DP_STATE_E:
-+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
-+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
-+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
-+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
-+ mode = UDPHY_MODE_DP;
-+ break;
-+
-+ case TYPEC_DP_STATE_D:
-+ default:
-+ if (udphy->flip) {
-+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
-+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
-+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
-+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
-+ } else {
-+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
-+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
-+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
-+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
-+ }
-+ mode = UDPHY_MODE_DP_USB;
-+ break;
-+ }
-+
-+ if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) {
-+ struct typec_displayport_data *data = state->data;
-+
-+ if (!data) {
-+ rk_udphy_dp_hpd_event_trigger(udphy, false);
-+ } else if (data->status & DP_STATUS_IRQ_HPD) {
-+ rk_udphy_dp_hpd_event_trigger(udphy, false);
-+ usleep_range(750, 800);
-+ rk_udphy_dp_hpd_event_trigger(udphy, true);
-+ } else if (data->status & DP_STATUS_HPD_STATE) {
-+ if (udphy->mode != mode) {
-+ udphy->mode = mode;
-+ udphy->mode_change = true;
-+ }
-+ rk_udphy_dp_hpd_event_trigger(udphy, true);
-+ } else {
-+ rk_udphy_dp_hpd_event_trigger(udphy, false);
-+ }
-+ }
-+
-+ mutex_unlock(&udphy->mutex);
-+ return 0;
-+}
-+
-+static void rk_udphy_typec_mux_unregister(void *data)
-+{
-+ struct rk_udphy *udphy = data;
-+
-+ typec_mux_unregister(udphy->mux);
-+}
-+
-+static int rk_udphy_setup_typec_mux(struct rk_udphy *udphy)
-+{
-+ struct typec_mux_desc mux_desc = {};
-+
-+ mux_desc.drvdata = udphy;
-+ mux_desc.fwnode = dev_fwnode(udphy->dev);
-+ mux_desc.set = rk_udphy_typec_mux_set;
-+
-+ udphy->mux = typec_mux_register(udphy->dev, &mux_desc);
-+ if (IS_ERR(udphy->mux)) {
-+ dev_err(udphy->dev, "Error register typec mux: %ld\n",
-+ PTR_ERR(udphy->mux));
-+ return PTR_ERR(udphy->mux);
-+ }
-+
-+ return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister,
-+ udphy);
-+}
-+
-+static const struct regmap_config rk_udphy_pma_regmap_cfg = {
-+ .reg_bits = 32,
-+ .reg_stride = 4,
-+ .val_bits = 32,
-+ .fast_io = true,
-+ .max_register = 0x20dc,
-+};
-+
-+static struct phy *rk_udphy_phy_xlate(struct device *dev, struct of_phandle_args *args)
-+{
-+ struct rk_udphy *udphy = dev_get_drvdata(dev);
-+
-+ if (args->args_count == 0)
-+ return ERR_PTR(-EINVAL);
-+
-+ switch (args->args[0]) {
-+ case PHY_TYPE_USB3:
-+ return udphy->phy_u3;
-+ case PHY_TYPE_DP:
-+ return udphy->phy_dp;
-+ }
-+
-+ return ERR_PTR(-EINVAL);
-+}
-+
-+static int rk_udphy_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct phy_provider *phy_provider;
-+ struct resource *res;
-+ struct rk_udphy *udphy;
-+ void __iomem *base;
-+ int id, ret;
-+
-+ udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL);
-+ if (!udphy)
-+ return -ENOMEM;
-+
-+ udphy->cfgs = device_get_match_data(dev);
-+ if (!udphy->cfgs)
-+ return dev_err_probe(dev, -EINVAL, "missing match data\n");
-+
-+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ /* find the phy-id from the io address */
-+ udphy->id = -ENODEV;
-+ for (id = 0; id < udphy->cfgs->num_phys; id++) {
-+ if (res->start == udphy->cfgs->phy_ids[id]) {
-+ udphy->id = id;
-+ break;
-+ }
-+ }
-+
-+ if (udphy->id < 0)
-+ return dev_err_probe(dev, -ENODEV, "no matching device found\n");
-+
-+ udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA,
-+ &rk_udphy_pma_regmap_cfg);
-+ if (IS_ERR(udphy->pma_regmap))
-+ return PTR_ERR(udphy->pma_regmap);
-+
-+ udphy->dev = dev;
-+ ret = rk_udphy_parse_dt(udphy);
-+ if (ret)
-+ return ret;
-+
-+ ret = rk_udphy_get_initial_status(udphy);
-+ if (ret)
-+ return ret;
-+
-+ mutex_init(&udphy->mutex);
-+ platform_set_drvdata(pdev, udphy);
-+
-+ if (device_property_present(dev, "orientation-switch")) {
-+ ret = rk_udphy_setup_orien_switch(udphy);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (device_property_present(dev, "mode-switch")) {
-+ ret = rk_udphy_setup_typec_mux(udphy);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops);
-+ if (IS_ERR(udphy->phy_u3)) {
-+ ret = PTR_ERR(udphy->phy_u3);
-+ return dev_err_probe(dev, ret, "failed to create USB3 phy\n");
-+ }
-+ phy_set_drvdata(udphy->phy_u3, udphy);
-+
-+ udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops);
-+ if (IS_ERR(udphy->phy_dp)) {
-+ ret = PTR_ERR(udphy->phy_dp);
-+ return dev_err_probe(dev, ret, "failed to create DP phy\n");
-+ }
-+ phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy));
-+ udphy->phy_dp->attrs.max_link_rate = 8100;
-+ phy_set_drvdata(udphy->phy_dp, udphy);
-+
-+ phy_provider = devm_of_phy_provider_register(dev, rk_udphy_phy_xlate);
-+ if (IS_ERR(phy_provider)) {
-+ ret = PTR_ERR(phy_provider);
-+ return dev_err_probe(dev, ret, "failed to register phy provider\n");
-+ }
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused rk_udphy_resume(struct device *dev)
-+{
-+ struct rk_udphy *udphy = dev_get_drvdata(dev);
-+
-+ if (udphy->dp_sink_hpd_sel)
-+ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
-+
-+ return 0;
-+}
-+
-+static const struct dev_pm_ops rk_udphy_pm_ops = {
-+ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume)
-+};
-+
-+static const char * const rk_udphy_rst_list[] = {
-+ "init", "cmn", "lane", "pcs_apb", "pma_apb"
-+};
-+
-+static const struct rk_udphy_cfg rk3588_udphy_cfgs = {
-+ .num_phys = 2,
-+ .phy_ids = {
-+ 0xfed80000,
-+ 0xfed90000,
-+ },
-+ .num_rsts = ARRAY_SIZE(rk_udphy_rst_list),
-+ .rst_list = rk_udphy_rst_list,
-+ .grfcfg = {
-+ /* u2phy-grf */
-+ .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3),
-+ .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3),
-+
-+ /* usb-grf */
-+ .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188),
-+ .usb3otg1_cfg = RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188),
-+
-+ /* usbdpphy-grf */
-+ .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1),
-+ .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1),
-+ },
-+ .vogrfcfg = {
-+ {
-+ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
-+ .dp_lane_reg = 0x0000,
-+ },
-+ {
-+ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3),
-+ .dp_lane_reg = 0x0008,
-+ },
-+ },
-+ .dp_tx_ctrl_cfg = {
-+ rk3588_dp_tx_drv_ctrl_rbr_hbr,
-+ rk3588_dp_tx_drv_ctrl_rbr_hbr,
-+ rk3588_dp_tx_drv_ctrl_hbr2,
-+ rk3588_dp_tx_drv_ctrl_hbr3,
-+ },
-+ .dp_tx_ctrl_cfg_typec = {
-+ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
-+ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
-+ rk3588_dp_tx_drv_ctrl_hbr2,
-+ rk3588_dp_tx_drv_ctrl_hbr3,
-+ },
-+};
-+
-+static const struct of_device_id rk_udphy_dt_match[] = {
-+ {
-+ .compatible = "rockchip,rk3588-usbdp-phy",
-+ .data = &rk3588_udphy_cfgs
-+ },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, rk_udphy_dt_match);
-+
-+static struct platform_driver rk_udphy_driver = {
-+ .probe = rk_udphy_probe,
-+ .driver = {
-+ .name = "rockchip-usbdp-phy",
-+ .of_match_table = rk_udphy_dt_match,
-+ .pm = &rk_udphy_pm_ops,
-+ },
-+};
-+module_platform_driver(rk_udphy_driver);
-+
-+MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
-+MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");
-+MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From c9342d1a351ee1249fa98d936f756299a83d5684 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Tue, 16 Apr 2024 16:51:23 +0200
-Subject: [PATCH] phy: rockchip: usbdp: fix uninitialized variable
-
-The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if
-the PHY is not using USB3 mode.
-
-Since the DisplayPort part is handled separately and the PHY does not
-support USB2 (which is routed to another PHY on Rockchip RK3588), the
-right exit code for this case is 0. Thus let's initialize the variable
-accordingly.
-
-Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver")
-Reported-by: kernel test robot <lkp@intel.com>
-Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Reviewed-by: Muhammad Usama Anjum <usama.anjum@collabora.com>
-Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
-+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
-@@ -1285,7 +1285,7 @@ static const struct phy_ops rk_udphy_dp_
- static int rk_udphy_usb3_phy_init(struct phy *phy)
- {
- struct rk_udphy *udphy = phy_get_drvdata(phy);
-- int ret;
-+ int ret = 0;
-
- mutex_lock(&udphy->mutex);
- /* DP only or high-speed, disable U3 port */
+++ /dev/null
-From 9c79b779643e56d4253bd3ba6998c58c819943af Mon Sep 17 00:00:00 2001
-From: Arnd Bergmann <arnd@arndb.de>
-Date: Mon, 15 Apr 2024 19:42:25 +0200
-Subject: [PATCH] phy: rockchip: fix CONFIG_TYPEC dependency
-
-The newly added driver causes a warning about missing dependencies
-by selecting CONFIG_TYPEC unconditionally:
-
-WARNING: unmet direct dependencies detected for TYPEC
- Depends on [n]: USB_SUPPORT [=n]
- Selected by [y]:
- - PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y]
-
-WARNING: unmet direct dependencies detected for USB_COMMON
- Depends on [n]: USB_SUPPORT [=n]
- Selected by [y]:
- - EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y]
-
-Since that is a user-visible option, it should not really be selected
-in the first place. Replace the 'select' with a 'depends on' as
-we have for similar drivers.
-
-Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver")
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/phy/rockchip/Kconfig
-+++ b/drivers/phy/rockchip/Kconfig
-@@ -111,8 +111,8 @@ config PHY_ROCKCHIP_USB
- config PHY_ROCKCHIP_USBDP
- tristate "Rockchip USBDP COMBO PHY Driver"
- depends on ARCH_ROCKCHIP && OF
-+ depends on TYPEC
- select GENERIC_PHY
-- select TYPEC
- help
- Enable this to support the Rockchip USB3.0/DP combo PHY with
- Samsung IP block. This is required for USB3 support on RK3588.
+++ /dev/null
-From 9b6bfad9070a95d19973be17177e5d9220cbbf1f Mon Sep 17 00:00:00 2001
-From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
-Date: Thu, 7 Mar 2024 10:53:18 +0100
-Subject: [PATCH] phy: rockchip: Fix typo in function names
-
-Several functions had "rochchip" instead of "rockchip" in their name.
-Replace "rochchip" by "rockchip".
-
-Signed-off-By: Rick Wertenbroek <rick.wertenbroek@gmail.com>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Link: https://lore.kernel.org/r/20240307095318.3651498-1-rick.wertenbroek@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 4 ++--
- drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 12 ++++++------
- 2 files changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-@@ -248,7 +248,7 @@ static int rockchip_combphy_exit(struct
- return 0;
- }
-
--static const struct phy_ops rochchip_combphy_ops = {
-+static const struct phy_ops rockchip_combphy_ops = {
- .init = rockchip_combphy_init,
- .exit = rockchip_combphy_exit,
- .owner = THIS_MODULE,
-@@ -367,7 +367,7 @@ static int rockchip_combphy_probe(struct
- return ret;
- }
-
-- priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
-+ priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops);
- if (IS_ERR(priv->phy)) {
- dev_err(dev, "failed to create combphy\n");
- return PTR_ERR(priv->phy);
---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
-+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
-@@ -182,7 +182,7 @@ static const struct rockchip_p3phy_ops r
- .phy_init = rockchip_p3phy_rk3588_init,
- };
-
--static int rochchip_p3phy_init(struct phy *phy)
-+static int rockchip_p3phy_init(struct phy *phy)
- {
- struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
- int ret;
-@@ -205,7 +205,7 @@ static int rochchip_p3phy_init(struct ph
- return ret;
- }
-
--static int rochchip_p3phy_exit(struct phy *phy)
-+static int rockchip_p3phy_exit(struct phy *phy)
- {
- struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
-
-@@ -214,9 +214,9 @@ static int rochchip_p3phy_exit(struct ph
- return 0;
- }
-
--static const struct phy_ops rochchip_p3phy_ops = {
-- .init = rochchip_p3phy_init,
-- .exit = rochchip_p3phy_exit,
-+static const struct phy_ops rockchip_p3phy_ops = {
-+ .init = rockchip_p3phy_init,
-+ .exit = rockchip_p3phy_exit,
- .set_mode = rockchip_p3phy_set_mode,
- .owner = THIS_MODULE,
- };
-@@ -275,7 +275,7 @@ static int rockchip_p3phy_probe(struct p
- return priv->num_lanes;
- }
-
-- priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
-+ priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
- if (IS_ERR(priv->phy)) {
- dev_err(dev, "failed to create combphy\n");
- return PTR_ERR(priv->phy);
+++ /dev/null
-From a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 Mon Sep 17 00:00:00 2001
-From: Niklas Cassel <cassel@kernel.org>
-Date: Fri, 12 Apr 2024 14:58:16 +0200
-Subject: [PATCH] phy: rockchip-snps-pcie3: add support for
- rockchip,rx-common-refclk-mode
-
->From the RK3588 Technical Reference Manual, Part1,
-section 6.19 PCIe3PHY_GRF Register Description:
-"rxX_cmn_refclk_mode"
-RX common reference clock mode for lane X. This mode should be enabled
-only when the far-end and near-end devices are running with a common
-reference clock.
-
-The hardware reset value for this field is 0x1 (enabled).
-Note that this register field is only available on RK3588, not on RK3568.
-
-The link training either fails or is highly unstable (link state will jump
-continuously between L0 and recovery) when this mode is enabled while
-using an endpoint running in Separate Reference Clock with No SSC (SRNS)
-mode or Separate Reference Clock with SSC (SRIS) mode.
-(Which is usually the case when using a real SoC as endpoint, e.g. the
-RK3588 PCIe controller can run in both Root Complex and Endpoint mode.)
-
-Add support for the device tree property rockchip,rx-common-refclk-mode,
-such that the PCIe PHY can be used in configurations where the Root
-Complex and Endpoint are not using a common reference clock.
-
-Signed-off-by: Niklas Cassel <cassel@kernel.org>
-Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- .../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++
- 1 file changed, 37 insertions(+)
-
---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
-+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
-@@ -35,11 +35,17 @@
- #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
- #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
- #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
-+#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004
-+#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104
-+#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004
-+#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104
- #define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
-
- #define RK3588_BIFURCATION_LANE_0_1 BIT(0)
- #define RK3588_BIFURCATION_LANE_2_3 BIT(1)
- #define RK3588_LANE_AGGREGATION BIT(2)
-+#define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7))
-+#define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16)
- #define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)
- #define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)
-
-@@ -60,6 +66,7 @@ struct rockchip_p3phy_priv {
- int num_clks;
- int num_lanes;
- u32 lanes[4];
-+ u32 rx_cmn_refclk_mode[4];
- };
-
- struct rockchip_p3phy_ops {
-@@ -137,6 +144,19 @@ static int rockchip_p3phy_rk3588_init(st
- u8 mode = RK3588_LANE_AGGREGATION; /* default */
- int ret;
-
-+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1,
-+ priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN :
-+ RK3588_RX_CMN_REFCLK_MODE_DIS);
-+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1,
-+ priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN :
-+ RK3588_RX_CMN_REFCLK_MODE_DIS);
-+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1,
-+ priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN :
-+ RK3588_RX_CMN_REFCLK_MODE_DIS);
-+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1,
-+ priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN :
-+ RK3588_RX_CMN_REFCLK_MODE_DIS);
-+
- /* Deassert PCIe PMA output clamp mode */
- regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
-
-@@ -275,6 +295,23 @@ static int rockchip_p3phy_probe(struct p
- return priv->num_lanes;
- }
-
-+ ret = of_property_read_variable_u32_array(dev->of_node,
-+ "rockchip,rx-common-refclk-mode",
-+ priv->rx_cmn_refclk_mode, 1,
-+ ARRAY_SIZE(priv->rx_cmn_refclk_mode));
-+ /*
-+ * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in
-+ * order to be DT backwards compatible. (Since HW reset val is enabled.)
-+ */
-+ if (ret == -EINVAL) {
-+ for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++)
-+ priv->rx_cmn_refclk_mode[i] = 1;
-+ } else if (ret < 0) {
-+ dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n",
-+ ret);
-+ return ret;
-+ }
-+
- priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
- if (IS_ERR(priv->phy)) {
- dev_err(dev, "failed to create combphy\n");
+++ /dev/null
-From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 20 Oct 2023 16:11:41 +0200
-Subject: [PATCH] usb: dwc3: add optional PHY interface clocks
-
-On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
-requires two extra clocks to be enabled. Without these extra clocks
-hot-plugging USB devices is broken.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
-Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
- drivers/usb/dwc3/core.h | 4 ++++
- 2 files changed, 32 insertions(+)
-
---- a/drivers/usb/dwc3/core.c
-+++ b/drivers/usb/dwc3/core.c
-@@ -860,8 +860,20 @@ static int dwc3_clk_enable(struct dwc3 *
- if (ret)
- goto disable_ref_clk;
-
-+ ret = clk_prepare_enable(dwc->utmi_clk);
-+ if (ret)
-+ goto disable_susp_clk;
-+
-+ ret = clk_prepare_enable(dwc->pipe_clk);
-+ if (ret)
-+ goto disable_utmi_clk;
-+
- return 0;
-
-+disable_utmi_clk:
-+ clk_disable_unprepare(dwc->utmi_clk);
-+disable_susp_clk:
-+ clk_disable_unprepare(dwc->susp_clk);
- disable_ref_clk:
- clk_disable_unprepare(dwc->ref_clk);
- disable_bus_clk:
-@@ -871,6 +883,8 @@ disable_bus_clk:
-
- static void dwc3_clk_disable(struct dwc3 *dwc)
- {
-+ clk_disable_unprepare(dwc->pipe_clk);
-+ clk_disable_unprepare(dwc->utmi_clk);
- clk_disable_unprepare(dwc->susp_clk);
- clk_disable_unprepare(dwc->ref_clk);
- clk_disable_unprepare(dwc->bus_clk);
-@@ -1886,6 +1900,20 @@ static int dwc3_get_clocks(struct dwc3 *
- }
- }
-
-+ /* specific to Rockchip RK3588 */
-+ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
-+ if (IS_ERR(dwc->utmi_clk)) {
-+ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
-+ "could not get utmi clock\n");
-+ }
-+
-+ /* specific to Rockchip RK3588 */
-+ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
-+ if (IS_ERR(dwc->pipe_clk)) {
-+ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
-+ "could not get pipe clock\n");
-+ }
-+
- return 0;
- }
-
---- a/drivers/usb/dwc3/core.h
-+++ b/drivers/usb/dwc3/core.h
-@@ -1003,6 +1003,8 @@ struct dwc3_scratchpad_array {
- * @bus_clk: clock for accessing the registers
- * @ref_clk: reference clock
- * @susp_clk: clock used when the SS phy is in low power (S3) state
-+ * @utmi_clk: clock used for USB2 PHY communication
-+ * @pipe_clk: clock used for USB3 PHY communication
- * @reset: reset control
- * @regs: base address for our registers
- * @regs_size: address space size
-@@ -1175,6 +1177,8 @@ struct dwc3 {
- struct clk *bus_clk;
- struct clk *ref_clk;
- struct clk *susp_clk;
-+ struct clk *utmi_clk;
-+ struct clk *pipe_clk;
-
- struct reset_control *reset;
-
+++ /dev/null
-From 3eaf2abd11aa7f3b2fb04d60c64b2c756fe030eb Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@6tel.net>
-Date: Mon, 9 Oct 2023 22:27:26 +0300
-Subject: [PATCH] arm64: dts: rockchip: Add sfc node to rk3588s
-
-Add SFC (SPI Flash) to RK3588S SOC.
-
-Reviewed-by: Dhruva Gole <d-gole@ti.com>
-Signed-off-by: Muhammed Efe Cetin <efectn@6tel.net>
-Link: https://lore.kernel.org/r/d36a64edfaede92ce2e158b0d9dc4f5998e019e3.1696878787.git.efectn@6tel.net
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1425,6 +1425,17 @@
- };
- };
-
-+ sfc: spi@fe2b0000 {
-+ compatible = "rockchip,sfc";
-+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
-+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
-+ clock-names = "clk_sfc", "hclk_sfc";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
- sdmmc: mmc@fe2c0000 {
- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xfe2c0000 0x0 0x4000>;
+++ /dev/null
-From bf012368bb0ab69167d49715789fac34dfcd457e Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <megi@xff.cz>
-Date: Sun, 8 Oct 2023 15:04:59 +0200
-Subject: [PATCH] arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s
-
-This is used on Orange Pi 5 Plus.
-
-Signed-off-by: Ondrej Jirman <megi@xff.cz>
-Link: https://lore.kernel.org/r/20231008130515.1155664-2-megi@xff.cz
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 35 +++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
-@@ -1350,6 +1350,41 @@
-
- i2s2 {
- /omit-if-no-ref/
-+ i2s2m0_lrck: i2s2m0-lrck {
-+ rockchip,pins =
-+ /* i2s2m0_lrck */
-+ <2 RK_PC0 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_mclk: i2s2m0-mclk {
-+ rockchip,pins =
-+ /* i2s2m0_mclk */
-+ <2 RK_PB6 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_sclk: i2s2m0-sclk {
-+ rockchip,pins =
-+ /* i2s2m0_sclk */
-+ <2 RK_PB7 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_sdi: i2s2m0-sdi {
-+ rockchip,pins =
-+ /* i2s2m0_sdi */
-+ <2 RK_PC3 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_sdo: i2s2m0-sdo {
-+ rockchip,pins =
-+ /* i2s2m0_sdo */
-+ <4 RK_PC3 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
- i2s2m1_lrck: i2s2m1-lrck {
- rockchip,pins =
- /* i2s2m1_lrck */
+++ /dev/null
-From 3d77a3e51b0faed820a8db985dce5af1cc4eae32 Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <megi@xff.cz>
-Date: Sun, 8 Oct 2023 15:05:00 +0200
-Subject: [PATCH] arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s
-
-This is used on Orange Pi 5 Plus.
-
-Signed-off-by: Ondrej Jirman <megi@xff.cz>
-Link: https://lore.kernel.org/r/20231008130515.1155664-3-megi@xff.cz
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
-@@ -3343,6 +3343,15 @@
-
- uart9 {
- /omit-if-no-ref/
-+ uart9m0_xfer: uart9m0-xfer {
-+ rockchip,pins =
-+ /* uart9_rx_m0 */
-+ <2 RK_PC4 10 &pcfg_pull_up>,
-+ /* uart9_tx_m0 */
-+ <2 RK_PC2 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
- uart9m1_xfer: uart9m1-xfer {
- rockchip,pins =
- /* uart9_rx_m1 */
+++ /dev/null
-From dd6dc0c4c1265129c229e26917bf4de1d97ff91f Mon Sep 17 00:00:00 2001
-From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-Date: Fri, 6 Oct 2023 08:53:34 +0200
-Subject: [PATCH] arm64: dts: rockchip: Add AV1 decoder node to rk3588s
-
-Add node for AV1 video decoder.
-
-Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20231006065334.8117-1-benjamin.gaignard@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -2314,6 +2314,19 @@
- #interrupt-cells = <2>;
- };
- };
-+
-+ av1d: video-codec@fdc70000 {
-+ compatible = "rockchip,rk3588-av1-vpu";
-+ reg = <0x0 0xfdc70000 0x0 0x800>;
-+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "vdpu";
-+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-+ assigned-clock-rates = <400000000>, <400000000>;
-+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-+ clock-names = "aclk", "hclk";
-+ power-domains = <&power RK3588_PD_AV1>;
-+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
-+ };
- };
-
- #include "rk3588s-pinctrl.dtsi"
+++ /dev/null
-From 5a6976b1040a2f99ab84eddbfa7cd072ac5d10fc Mon Sep 17 00:00:00 2001
-From: Sascha Hauer <s.hauer@pengutronix.de>
-Date: Wed, 18 Oct 2023 08:17:14 +0200
-Subject: [PATCH] arm64: dts: rockchip: Add DFI to rk3588s
-
-The DFI unit can be used to measure DRAM utilization using perf. Add the
-node to the device tree. The DFI needs a rockchip,pmu phandle to the pmu
-containing registers for SDRAM configuration details. This is added in
-this patch as well.
-
-Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-Link: https://lore.kernel.org/r/20231018061714.3553817-27-s.hauer@pengutronix.de
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -443,6 +443,11 @@
- status = "disabled";
- };
-
-+ pmu1grf: syscon@fd58a000 {
-+ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
-+ reg = <0x0 0xfd58a000 0x0 0x10000>;
-+ };
-+
- sys_grf: syscon@fd58c000 {
- compatible = "rockchip,rk3588-sys-grf", "syscon";
- reg = <0x0 0xfd58c000 0x0 0x1000>;
-@@ -1330,6 +1335,17 @@
- };
- };
-
-+ dfi: dfi@fe060000 {
-+ reg = <0x00 0xfe060000 0x00 0x10000>;
-+ compatible = "rockchip,rk3588-dfi";
-+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "ch0", "ch1", "ch2", "ch3";
-+ rockchip,pmu = <&pmu1grf>;
-+ };
-+
- gmac1: ethernet@fe1c0000 {
- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
- reg = <0x0 0xfe1c0000 0x0 0x10000>;
+++ /dev/null
-From bbd3778da16b3d448832b843f80bcde1aff26290 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Fri, 20 Oct 2023 16:11:42 +0200
-Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 host controller
-
-RK3588 has three USB3 controllers. This adds the host-only controller,
-which is using the naneng-combphy shared with PCIe and SATA.
-
-The other two are dual-role and using a different PHY that is not yet
-supported upstream.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20231020150022.48725-4-sebastian.reichel@collabora.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -443,6 +443,27 @@
- status = "disabled";
- };
-
-+ usb_host2_xhci: usb@fcd00000 {
-+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
-+ reg = <0x0 0xfcd00000 0x0 0x400000>;
-+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
-+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
-+ <&cru CLK_PIPEPHY2_PIPE_U3_G>;
-+ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
-+ dr_mode = "host";
-+ phys = <&combphy2_psu PHY_TYPE_USB3>;
-+ phy-names = "usb3-phy";
-+ phy_type = "utmi_wide";
-+ resets = <&cru SRST_A_USB3OTG2>;
-+ snps,dis_enblslpm_quirk;
-+ snps,dis-u2-freeclk-exists-quirk;
-+ snps,dis-del-phy-power-chg-quirk;
-+ snps,dis-tx-ipgap-linecheck-quirk;
-+ snps,dis_rxdet_inp3_quirk;
-+ status = "disabled";
-+ };
-+
- pmu1grf: syscon@fd58a000 {
- compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
- reg = <0x0 0xfd58a000 0x0 0x10000>;
+++ /dev/null
-From 815f986f33eeb06652d59d8a4d405d4fdb4e59a8 Mon Sep 17 00:00:00 2001
-From: Heiko Stuebner <heiko.stuebner@cherry.de>
-Date: Fri, 1 Dec 2023 14:48:59 +0100
-Subject: [PATCH] arm64: dts: rockchip: drop interrupt-names property from
- rk3588s dfi
-
-The dfi binding does not specify interrupt names, with the interrupts
-just specifying channels 0-x. So drop the unspecified property.
-
-Fixes: 5a6976b1040a ("arm64: dts: rockchip: Add DFI to rk3588s")
-Reported-by: Jagan Teki <jagan@edgeble.ai>
-Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
-Link: https://lore.kernel.org/r/20231201134859.322491-1-heiko@sntech.de
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1363,7 +1363,6 @@
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "ch0", "ch1", "ch2", "ch3";
- rockchip,pmu = <&pmu1grf>;
- };
-
+++ /dev/null
-From 9918d10d16665527e59fdb87c5acac70cc1cfe8f Mon Sep 17 00:00:00 2001
-From: Heiko Stuebner <heiko.stuebner@cherry.de>
-Date: Tue, 5 Dec 2023 17:48:39 +0100
-Subject: [PATCH] arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi
-
-The serial ports on rk3588 are named uart0 - uart9. Board schematics
-also use these exact numbers and we want those names to also reflect
-in the OS devices because everything else would just cause confusion.
-
-To prevent each board repeating their list of serial aliases, move them
-to the soc dtsi, as all previous Rockchip soc do already.
-
-Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
-Reviewed-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/20231205164842.556684-2-heiko@sntech.de
----
- .../boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts | 4 ----
- .../boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts | 4 ----
- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 1 -
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 -
- .../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 1 -
- arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 -
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 -
- arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 --
- .../boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 1 -
- .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 1 -
- arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 1 -
- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 -
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++
- 13 files changed, 13 insertions(+), 19 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts
-@@ -12,10 +12,6 @@
- compatible = "edgeble,neural-compute-module-6a-io",
- "edgeble,neural-compute-module-6a", "rockchip,rk3588";
-
-- aliases {
-- serial2 = &uart2;
-- };
--
- chosen {
- stdout-path = "serial2:1500000n8";
- };
---- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts
-@@ -12,10 +12,6 @@
- compatible = "edgeble,neural-compute-module-6b-io",
- "edgeble,neural-compute-module-6b", "rockchip,rk3588";
-
-- aliases {
-- serial2 = &uart2;
-- };
--
- chosen {
- stdout-path = "serial2:1500000n8";
- };
---- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-@@ -16,7 +16,6 @@
-
- aliases {
- mmc0 = &sdhci;
-- serial2 = &uart2;
- };
-
- chosen {
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -19,7 +19,6 @@
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
-- serial2 = &uart2;
- };
-
- chosen {
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -12,7 +12,6 @@
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
-- serial2 = &uart2;
- };
-
- chosen {
---- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
-@@ -15,7 +15,6 @@
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
- mmc2 = &sdio;
-- serial2 = &uart2;
- };
-
- chosen {
---- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
-@@ -12,7 +12,6 @@
-
- aliases {
- mmc0 = &sdhci;
-- serial2 = &uart2;
- };
-
- chosen {
---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -14,7 +14,6 @@
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
-- serial2 = &uart2;
- };
-
- analog-sound {
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -18,6 +18,19 @@
- #address-cells = <2>;
- #size-cells = <2>;
-
-+ aliases {
-+ serial0 = &uart0;
-+ serial1 = &uart1;
-+ serial2 = &uart2;
-+ serial3 = &uart3;
-+ serial4 = &uart4;
-+ serial5 = &uart5;
-+ serial6 = &uart6;
-+ serial7 = &uart7;
-+ serial8 = &uart8;
-+ serial9 = &uart9;
-+ };
-+
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+++ /dev/null
-From 328e901b7b03d292c1520ffb38e9164feef4f1ea Mon Sep 17 00:00:00 2001
-From: Heiko Stuebner <heiko.stuebner@cherry.de>
-Date: Tue, 5 Dec 2023 17:48:40 +0100
-Subject: [PATCH] arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi
-
-The i2c controllers on rk3588 are named i2c0 - i2c8. Board schematics
-also use these exact numbers and we want those names to also reflect
-in the OS devices because everything else would just cause confusion.
-Userspace i2c access is a thing afterall.
-
-To prevent each board repeating their list of i2c aliases, define them
-in the soc dtsi, as all previous Rockchip soc do already.
-
-Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
-Reviewed-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/20231205164842.556684-3-heiko@sntech.de
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -19,6 +19,15 @@
- #size-cells = <2>;
-
- aliases {
-+ i2c0 = &i2c0;
-+ i2c1 = &i2c1;
-+ i2c2 = &i2c2;
-+ i2c3 = &i2c3;
-+ i2c4 = &i2c4;
-+ i2c5 = &i2c5;
-+ i2c6 = &i2c6;
-+ i2c7 = &i2c7;
-+ i2c8 = &i2c8;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
+++ /dev/null
-From a024abedbca99a20aeb96f5beec9ded13c85dcb3 Mon Sep 17 00:00:00 2001
-From: Heiko Stuebner <heiko.stuebner@cherry.de>
-Date: Tue, 5 Dec 2023 17:48:41 +0100
-Subject: [PATCH] arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi
-
-The gpio controllers on rk3588 are named gpio0 - gpio4. Board schematics
-also use these exact numbers and we want those names to also reflect
-in the OS devices because everything else would just cause confusion.
-Userspace gpio access is a thing afterall.
-
-To prevent each board repeating their list of gpio aliases, define them
-in the soc dtsi, as previous Rockchip soc like the rk356x do already.
-
-Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
-Reviewed-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/20231205164842.556684-4-heiko@sntech.de
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -19,6 +19,11 @@
- #size-cells = <2>;
-
- aliases {
-+ gpio0 = &gpio0;
-+ gpio1 = &gpio1;
-+ gpio2 = &gpio2;
-+ gpio3 = &gpio3;
-+ gpio4 = &gpio4;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
+++ /dev/null
-From a86e88043de929da76f7f6cf0990ba92aed8391a Mon Sep 17 00:00:00 2001
-From: Heiko Stuebner <heiko.stuebner@cherry.de>
-Date: Tue, 5 Dec 2023 17:48:42 +0100
-Subject: [PATCH] arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi
-
-The spi controllers on rk3588 are named spi0 - spi4. Board schematics
-also use these exact numbers and we want those names to also reflect
-in the OS devices because everything else would just cause confusion.
-Userspace spi access is a thing afterall.
-
-To prevent each board repeating their list of spi aliases, define them
-in the soc dtsi, as previous Rockchip soc like the rk356x do already.
-
-Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
-Reviewed-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/20231205164842.556684-5-heiko@sntech.de
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -43,6 +43,11 @@
- serial7 = &uart7;
- serial8 = &uart8;
- serial9 = &uart9;
-+ spi0 = &spi0;
-+ spi1 = &spi1;
-+ spi2 = &spi2;
-+ spi3 = &spi3;
-+ spi4 = &spi4;
- };
-
- cpus {
+++ /dev/null
-From d895dbef3f3a31ab50491bb48552e798cf555987 Mon Sep 17 00:00:00 2001
-From: Andy Yan <andy.yan@rock-chips.com>
-Date: Mon, 11 Dec 2023 20:00:04 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add vop on rk3588
-
-Add vop dt node for rk3588.
-
-Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
-Link: https://lore.kernel.org/r/20231211120004.1785616-1-andyshrk@163.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 83 +++++++++++++++++++++++
- 1 file changed, 83 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -394,6 +394,11 @@
- #clock-cells = <0>;
- };
-
-+ display_subsystem: display-subsystem {
-+ compatible = "rockchip,display-subsystem";
-+ ports = <&vop_out>;
-+ };
-+
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
-@@ -506,6 +511,16 @@
- reg = <0x0 0xfd58c000 0x0 0x1000>;
- };
-
-+ vop_grf: syscon@fd5a4000 {
-+ compatible = "rockchip,rk3588-vop-grf", "syscon";
-+ reg = <0x0 0xfd5a4000 0x0 0x2000>;
-+ };
-+
-+ vo1_grf: syscon@fd5a8000 {
-+ compatible = "rockchip,rk3588-vo-grf", "syscon";
-+ reg = <0x0 0xfd5a8000 0x0 0x100>;
-+ };
-+
- php_grf: syscon@fd5b0000 {
- compatible = "rockchip,rk3588-php-grf", "syscon";
- reg = <0x0 0xfd5b0000 0x0 0x1000>;
-@@ -625,6 +640,74 @@
- status = "disabled";
- };
-
-+ vop: vop@fdd90000 {
-+ compatible = "rockchip,rk3588-vop";
-+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
-+ reg-names = "vop", "gamma-lut";
-+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru ACLK_VOP>,
-+ <&cru HCLK_VOP>,
-+ <&cru DCLK_VOP0>,
-+ <&cru DCLK_VOP1>,
-+ <&cru DCLK_VOP2>,
-+ <&cru DCLK_VOP3>,
-+ <&cru PCLK_VOP_ROOT>;
-+ clock-names = "aclk",
-+ "hclk",
-+ "dclk_vp0",
-+ "dclk_vp1",
-+ "dclk_vp2",
-+ "dclk_vp3",
-+ "pclk_vop";
-+ iommus = <&vop_mmu>;
-+ power-domains = <&power RK3588_PD_VOP>;
-+ rockchip,grf = <&sys_grf>;
-+ rockchip,vop-grf = <&vop_grf>;
-+ rockchip,vo1-grf = <&vo1_grf>;
-+ rockchip,pmu = <&pmu>;
-+ status = "disabled";
-+
-+ vop_out: ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ vp0: port@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0>;
-+ };
-+
-+ vp1: port@1 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <1>;
-+ };
-+
-+ vp2: port@2 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <2>;
-+ };
-+
-+ vp3: port@3 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <3>;
-+ };
-+ };
-+ };
-+
-+ vop_mmu: iommu@fdd97e00 {
-+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
-+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
-+ clock-names = "aclk", "iface";
-+ #iommu-cells = <0>;
-+ power-domains = <&power RK3588_PD_VOP>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@fd890000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfd890000 0x0 0x100>;
+++ /dev/null
-From 11d28971aaaf5de6f50790fb21f1113fee21d320 Mon Sep 17 00:00:00 2001
-From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
-Date: Mon, 19 Feb 2024 22:46:25 +0200
-Subject: [PATCH] arm64: dts: rockchip: Add HDMI0 PHY to rk3588
-
-Add DT nodes for HDMI0 PHY and related syscon found on RK3588 SoC.
-
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
-Link: https://lore.kernel.org/r/20240219204626.284399-1-cristian.ciocaltea@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -586,6 +586,11 @@
- };
- };
-
-+ hdptxphy0_grf: syscon@fd5e0000 {
-+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
-+ reg = <0x0 0xfd5e0000 0x0 0x100>;
-+ };
-+
- ioc: syscon@fd5f0000 {
- compatible = "rockchip,rk3588-ioc", "syscon";
- reg = <0x0 0xfd5f0000 0x0 0x10000>;
-@@ -2358,6 +2363,22 @@
- #dma-cells = <1>;
- };
-
-+ hdptxphy_hdmi0: phy@fed60000 {
-+ compatible = "rockchip,rk3588-hdptx-phy";
-+ reg = <0x0 0xfed60000 0x0 0x2000>;
-+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
-+ clock-names = "ref", "apb";
-+ #phy-cells = <0>;
-+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
-+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
-+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
-+ <&cru SRST_HDPTX0_LCPLL>;
-+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
-+ "lcpll";
-+ rockchip,grf = <&hdptxphy0_grf>;
-+ status = "disabled";
-+ };
-+
- combphy0_ps: phy@fee00000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee00000 0x0 0x100>;
+++ /dev/null
-From 2047366b9eff8fada2a118588b0478de6e92d02c Mon Sep 17 00:00:00 2001
-From: Heiko Stuebner <heiko@sntech.de>
-Date: Tue, 27 Feb 2024 22:05:21 +0100
-Subject: [PATCH] arm64: dts: rockchip: add clock to vo1-grf syscon on rk3588
-
-The VO*-general-register-files need a clock, so add the correct one.
-
-Cc: Sebastian Reichel <sebastian.reichel@collabora.com>
-Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-Link: https://lore.kernel.org/r/20240227210521.724754-1-heiko@sntech.de
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -519,6 +519,7 @@
- vo1_grf: syscon@fd5a8000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a8000 0x0 0x100>;
-+ clocks = <&cru PCLK_VO1GRF>;
- };
-
- php_grf: syscon@fd5b0000 {
+++ /dev/null
-From 6fca4edb93d335f29f81e484936f38a5eed6a9b1 Mon Sep 17 00:00:00 2001
-From: Boris Brezillon <boris.brezillon@collabora.com>
-Date: Tue, 26 Mar 2024 17:52:06 +0100
-Subject: [PATCH] arm64: dts: rockchip: Add rk3588 GPU node
-
-Add Mali GPU Node to the RK3588 SoC DT including GPU clock
-operating points
-
-Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 56 +++++++++++++++++++++++
- 1 file changed, 56 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -501,6 +501,62 @@
- status = "disabled";
- };
-
-+ gpu: gpu@fb000000 {
-+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
-+ reg = <0x0 0xfb000000 0x0 0x200000>;
-+ #cooling-cells = <2>;
-+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
-+ assigned-clock-rates = <200000000>;
-+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
-+ <&cru CLK_GPU_STACKS>;
-+ clock-names = "core", "coregroup", "stacks";
-+ dynamic-power-coefficient = <2982>;
-+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "job", "mmu", "gpu";
-+ operating-points-v2 = <&gpu_opp_table>;
-+ power-domains = <&power RK3588_PD_GPU>;
-+ status = "disabled";
-+
-+ gpu_opp_table: opp-table {
-+ compatible = "operating-points-v2";
-+
-+ opp-300000000 {
-+ opp-hz = /bits/ 64 <300000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-400000000 {
-+ opp-hz = /bits/ 64 <400000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-500000000 {
-+ opp-hz = /bits/ 64 <500000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-600000000 {
-+ opp-hz = /bits/ 64 <600000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-700000000 {
-+ opp-hz = /bits/ 64 <700000000>;
-+ opp-microvolt = <700000 700000 850000>;
-+ };
-+ opp-800000000 {
-+ opp-hz = /bits/ 64 <800000000>;
-+ opp-microvolt = <750000 750000 850000>;
-+ };
-+ opp-900000000 {
-+ opp-hz = /bits/ 64 <900000000>;
-+ opp-microvolt = <800000 800000 850000>;
-+ };
-+ opp-1000000000 {
-+ opp-hz = /bits/ 64 <1000000000>;
-+ opp-microvolt = <850000 850000 850000>;
-+ };
-+ };
-+ };
-+
- pmu1grf: syscon@fd58a000 {
- compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
- reg = <0x0 0xfd58a000 0x0 0x10000>;
+++ /dev/null
-From cbb97fe18e299ece1c0074924c630de6a19b320f Mon Sep 17 00:00:00 2001
-From: Diederik de Haas <didi.debian@cknow.org>
-Date: Sat, 6 Apr 2024 19:28:04 +0200
-Subject: [PATCH] arm64: dts: rockchip: Fix ordering of nodes on rk3588s
-
-Fix the ordering of the main nodes by sorting them alphabetically and
-then the ones with a memory address sequentially by that address.
-
-Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
-Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 304 +++++++++++-----------
- 1 file changed, 152 insertions(+), 152 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -347,6 +347,11 @@
- };
- };
-
-+ display_subsystem: display-subsystem {
-+ compatible = "rockchip,display-subsystem";
-+ ports = <&vop_out>;
-+ };
-+
- firmware {
- optee: optee {
- compatible = "linaro,optee-tz";
-@@ -394,11 +399,6 @@
- #clock-cells = <0>;
- };
-
-- display_subsystem: display-subsystem {
-- compatible = "rockchip,display-subsystem";
-- ports = <&vop_out>;
-- };
--
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
-@@ -436,6 +436,62 @@
- };
- };
-
-+ gpu: gpu@fb000000 {
-+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
-+ reg = <0x0 0xfb000000 0x0 0x200000>;
-+ #cooling-cells = <2>;
-+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
-+ assigned-clock-rates = <200000000>;
-+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
-+ <&cru CLK_GPU_STACKS>;
-+ clock-names = "core", "coregroup", "stacks";
-+ dynamic-power-coefficient = <2982>;
-+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "job", "mmu", "gpu";
-+ operating-points-v2 = <&gpu_opp_table>;
-+ power-domains = <&power RK3588_PD_GPU>;
-+ status = "disabled";
-+
-+ gpu_opp_table: opp-table {
-+ compatible = "operating-points-v2";
-+
-+ opp-300000000 {
-+ opp-hz = /bits/ 64 <300000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-400000000 {
-+ opp-hz = /bits/ 64 <400000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-500000000 {
-+ opp-hz = /bits/ 64 <500000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-600000000 {
-+ opp-hz = /bits/ 64 <600000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-700000000 {
-+ opp-hz = /bits/ 64 <700000000>;
-+ opp-microvolt = <700000 700000 850000>;
-+ };
-+ opp-800000000 {
-+ opp-hz = /bits/ 64 <800000000>;
-+ opp-microvolt = <750000 750000 850000>;
-+ };
-+ opp-900000000 {
-+ opp-hz = /bits/ 64 <900000000>;
-+ opp-microvolt = <800000 800000 850000>;
-+ };
-+ opp-1000000000 {
-+ opp-hz = /bits/ 64 <1000000000>;
-+ opp-microvolt = <850000 850000 850000>;
-+ };
-+ };
-+ };
-+
- usb_host0_ehci: usb@fc800000 {
- compatible = "rockchip,rk3588-ehci", "generic-ehci";
- reg = <0x0 0xfc800000 0x0 0x40000>;
-@@ -501,62 +557,6 @@
- status = "disabled";
- };
-
-- gpu: gpu@fb000000 {
-- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
-- reg = <0x0 0xfb000000 0x0 0x200000>;
-- #cooling-cells = <2>;
-- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
-- assigned-clock-rates = <200000000>;
-- clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
-- <&cru CLK_GPU_STACKS>;
-- clock-names = "core", "coregroup", "stacks";
-- dynamic-power-coefficient = <2982>;
-- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "job", "mmu", "gpu";
-- operating-points-v2 = <&gpu_opp_table>;
-- power-domains = <&power RK3588_PD_GPU>;
-- status = "disabled";
--
-- gpu_opp_table: opp-table {
-- compatible = "operating-points-v2";
--
-- opp-300000000 {
-- opp-hz = /bits/ 64 <300000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-400000000 {
-- opp-hz = /bits/ 64 <400000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-500000000 {
-- opp-hz = /bits/ 64 <500000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-600000000 {
-- opp-hz = /bits/ 64 <600000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-700000000 {
-- opp-hz = /bits/ 64 <700000000>;
-- opp-microvolt = <700000 700000 850000>;
-- };
-- opp-800000000 {
-- opp-hz = /bits/ 64 <800000000>;
-- opp-microvolt = <750000 750000 850000>;
-- };
-- opp-900000000 {
-- opp-hz = /bits/ 64 <900000000>;
-- opp-microvolt = <800000 800000 850000>;
-- };
-- opp-1000000000 {
-- opp-hz = /bits/ 64 <1000000000>;
-- opp-microvolt = <850000 850000 850000>;
-- };
-- };
-- };
--
- pmu1grf: syscon@fd58a000 {
- compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
- reg = <0x0 0xfd58a000 0x0 0x10000>;
-@@ -702,74 +702,6 @@
- status = "disabled";
- };
-
-- vop: vop@fdd90000 {
-- compatible = "rockchip,rk3588-vop";
-- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
-- reg-names = "vop", "gamma-lut";
-- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru ACLK_VOP>,
-- <&cru HCLK_VOP>,
-- <&cru DCLK_VOP0>,
-- <&cru DCLK_VOP1>,
-- <&cru DCLK_VOP2>,
-- <&cru DCLK_VOP3>,
-- <&cru PCLK_VOP_ROOT>;
-- clock-names = "aclk",
-- "hclk",
-- "dclk_vp0",
-- "dclk_vp1",
-- "dclk_vp2",
-- "dclk_vp3",
-- "pclk_vop";
-- iommus = <&vop_mmu>;
-- power-domains = <&power RK3588_PD_VOP>;
-- rockchip,grf = <&sys_grf>;
-- rockchip,vop-grf = <&vop_grf>;
-- rockchip,vo1-grf = <&vo1_grf>;
-- rockchip,pmu = <&pmu>;
-- status = "disabled";
--
-- vop_out: ports {
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- vp0: port@0 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <0>;
-- };
--
-- vp1: port@1 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <1>;
-- };
--
-- vp2: port@2 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <2>;
-- };
--
-- vp3: port@3 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <3>;
-- };
-- };
-- };
--
-- vop_mmu: iommu@fdd97e00 {
-- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
-- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
-- clock-names = "aclk", "iface";
-- #iommu-cells = <0>;
-- power-domains = <&power RK3588_PD_VOP>;
-- status = "disabled";
-- };
--
- uart0: serial@fd890000 {
- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
- reg = <0x0 0xfd890000 0x0 0x100>;
-@@ -1140,6 +1072,87 @@
- };
- };
-
-+ av1d: video-codec@fdc70000 {
-+ compatible = "rockchip,rk3588-av1-vpu";
-+ reg = <0x0 0xfdc70000 0x0 0x800>;
-+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "vdpu";
-+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-+ assigned-clock-rates = <400000000>, <400000000>;
-+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-+ clock-names = "aclk", "hclk";
-+ power-domains = <&power RK3588_PD_AV1>;
-+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
-+ };
-+
-+ vop: vop@fdd90000 {
-+ compatible = "rockchip,rk3588-vop";
-+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
-+ reg-names = "vop", "gamma-lut";
-+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru ACLK_VOP>,
-+ <&cru HCLK_VOP>,
-+ <&cru DCLK_VOP0>,
-+ <&cru DCLK_VOP1>,
-+ <&cru DCLK_VOP2>,
-+ <&cru DCLK_VOP3>,
-+ <&cru PCLK_VOP_ROOT>;
-+ clock-names = "aclk",
-+ "hclk",
-+ "dclk_vp0",
-+ "dclk_vp1",
-+ "dclk_vp2",
-+ "dclk_vp3",
-+ "pclk_vop";
-+ iommus = <&vop_mmu>;
-+ power-domains = <&power RK3588_PD_VOP>;
-+ rockchip,grf = <&sys_grf>;
-+ rockchip,vop-grf = <&vop_grf>;
-+ rockchip,vo1-grf = <&vo1_grf>;
-+ rockchip,pmu = <&pmu>;
-+ status = "disabled";
-+
-+ vop_out: ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ vp0: port@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0>;
-+ };
-+
-+ vp1: port@1 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <1>;
-+ };
-+
-+ vp2: port@2 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <2>;
-+ };
-+
-+ vp3: port@3 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <3>;
-+ };
-+ };
-+ };
-+
-+ vop_mmu: iommu@fdd97e00 {
-+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
-+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
-+ clock-names = "aclk", "iface";
-+ #iommu-cells = <0>;
-+ power-domains = <&power RK3588_PD_VOP>;
-+ status = "disabled";
-+ };
-+
- i2s4_8ch: i2s@fddc0000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddc0000 0x0 0x1000>;
-@@ -1431,6 +1444,16 @@
- reg = <0x0 0xfdf82200 0x0 0x20>;
- };
-
-+ dfi: dfi@fe060000 {
-+ reg = <0x00 0xfe060000 0x00 0x10000>;
-+ compatible = "rockchip,rk3588-dfi";
-+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
-+ rockchip,pmu = <&pmu1grf>;
-+ };
-+
- pcie2x1l1: pcie@fe180000 {
- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
- bus-range = <0x30 0x3f>;
-@@ -1533,16 +1556,6 @@
- };
- };
-
-- dfi: dfi@fe060000 {
-- reg = <0x00 0xfe060000 0x00 0x10000>;
-- compatible = "rockchip,rk3588-dfi";
-- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
-- rockchip,pmu = <&pmu1grf>;
-- };
--
- gmac1: ethernet@fe1c0000 {
- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
- reg = <0x0 0xfe1c0000 0x0 0x10000>;
-@@ -2543,19 +2556,6 @@
- #interrupt-cells = <2>;
- };
- };
--
-- av1d: video-codec@fdc70000 {
-- compatible = "rockchip,rk3588-av1-vpu";
-- reg = <0x0 0xfdc70000 0x0 0x800>;
-- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "vdpu";
-- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-- assigned-clock-rates = <400000000>, <400000000>;
-- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-- clock-names = "aclk", "hclk";
-- power-domains = <&power RK3588_PD_AV1>;
-- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
-- };
- };
-
- #include "rk3588s-pinctrl.dtsi"
+++ /dev/null
-From 4e07a95f7402de092cd71b2cb96c69f85c98f251 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Tue, 9 Apr 2024 00:50:31 +0200
-Subject: [PATCH] arm64: dts: rockchip: fix usb2phy nodename for rk3588
-
-usb2-phy should be named usb2phy according to the DT binding,
-so let's fix it up accordingly.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -599,7 +599,7 @@
- #address-cells = <1>;
- #size-cells = <1>;
-
-- u2phy2: usb2-phy@8000 {
-+ u2phy2: usb2phy@8000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x8000 0x10>;
- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
-@@ -624,7 +624,7 @@
- #address-cells = <1>;
- #size-cells = <1>;
-
-- u2phy3: usb2-phy@c000 {
-+ u2phy3: usb2phy@c000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0xc000 0x10>;
- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
+++ /dev/null
-From abe68e0ca71dddce0e5419e35507cb464d61870d Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Tue, 9 Apr 2024 00:50:32 +0200
-Subject: [PATCH] arm64: dts: rockchip: reorder usb2phy properties for rk3588
-
-Reorder common DT properties alphabetically for usb2phy, according
-to latest DT style rules.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -602,13 +602,13 @@
- u2phy2: usb2phy@8000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0x8000 0x10>;
-- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
-- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
-- reset-names = "phy", "apb";
-+ #clock-cells = <0>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy2";
-- #clock-cells = <0>;
-+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
-+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
-+ reset-names = "phy", "apb";
- status = "disabled";
-
- u2phy2_host: host-port {
-@@ -627,13 +627,13 @@
- u2phy3: usb2phy@c000 {
- compatible = "rockchip,rk3588-usb2phy";
- reg = <0xc000 0x10>;
-- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
-- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
-- reset-names = "phy", "apb";
-+ #clock-cells = <0>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
- clock-names = "phyclk";
- clock-output-names = "usb480m_phy3";
-- #clock-cells = <0>;
-+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
-+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
-+ reset-names = "phy", "apb";
- status = "disabled";
-
- u2phy3_host: host-port {
+++ /dev/null
-From e18e5e8188f2671abf63abe7db5f21555705130f Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Tue, 9 Apr 2024 00:50:33 +0200
-Subject: [PATCH] arm64: dts: rockchip: add USBDP phys on rk3588
-
-Add both USB3-DisplayPort PHYs to RK3588 SoC DT.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 52 +++++++++++++++++++
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 63 +++++++++++++++++++++++
- 2 files changed, 115 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
-@@ -17,6 +17,36 @@
- reg = <0x0 0xfd5c0000 0x0 0x100>;
- };
-
-+ usbdpphy1_grf: syscon@fd5cc000 {
-+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
-+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
-+ };
-+
-+ usb2phy1_grf: syscon@fd5d4000 {
-+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ u2phy1: usb2phy@4000 {
-+ compatible = "rockchip,rk3588-usb2phy";
-+ reg = <0x4000 0x10>;
-+ #clock-cells = <0>;
-+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-+ clock-names = "phyclk";
-+ clock-output-names = "usb480m_phy1";
-+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
-+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
-+ reset-names = "phy", "apb";
-+ status = "disabled";
-+
-+ u2phy1_otg: otg-port {
-+ #phy-cells = <0>;
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
- i2s8_8ch: i2s@fddc8000 {
- compatible = "rockchip,rk3588-i2s-tdm";
- reg = <0x0 0xfddc8000 0x0 0x1000>;
-@@ -310,6 +340,28 @@
- };
- };
-
-+ usbdp_phy1: phy@fed90000 {
-+ compatible = "rockchip,rk3588-usbdp-phy";
-+ reg = <0x0 0xfed90000 0x0 0x10000>;
-+ #phy-cells = <1>;
-+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
-+ <&cru CLK_USBDP_PHY1_IMMORTAL>,
-+ <&cru PCLK_USBDPPHY1>,
-+ <&u2phy1>;
-+ clock-names = "refclk", "immortal", "pclk", "utmi";
-+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
-+ <&cru SRST_USBDP_COMBO_PHY1_CMN>,
-+ <&cru SRST_USBDP_COMBO_PHY1_LANE>,
-+ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
-+ <&cru SRST_P_USBDPPHY1>;
-+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
-+ rockchip,u2phy-grf = <&usb2phy1_grf>;
-+ rockchip,usb-grf = <&usb_grf>;
-+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
-+ rockchip,vo-grf = <&vo0_grf>;
-+ status = "disabled";
-+ };
-+
- combphy1_ps: phy@fee10000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee10000 0x0 0x100>;
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -572,12 +572,23 @@
- reg = <0x0 0xfd5a4000 0x0 0x2000>;
- };
-
-+ vo0_grf: syscon@fd5a6000 {
-+ compatible = "rockchip,rk3588-vo-grf", "syscon";
-+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
-+ clocks = <&cru PCLK_VO0GRF>;
-+ };
-+
- vo1_grf: syscon@fd5a8000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a8000 0x0 0x100>;
- clocks = <&cru PCLK_VO1GRF>;
- };
-
-+ usb_grf: syscon@fd5ac000 {
-+ compatible = "rockchip,rk3588-usb-grf", "syscon";
-+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
-+ };
-+
- php_grf: syscon@fd5b0000 {
- compatible = "rockchip,rk3588-php-grf", "syscon";
- reg = <0x0 0xfd5b0000 0x0 0x1000>;
-@@ -593,6 +604,36 @@
- reg = <0x0 0xfd5c4000 0x0 0x100>;
- };
-
-+ usbdpphy0_grf: syscon@fd5c8000 {
-+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
-+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
-+ };
-+
-+ usb2phy0_grf: syscon@fd5d0000 {
-+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-+ reg = <0x0 0xfd5d0000 0x0 0x4000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ u2phy0: usb2phy@0 {
-+ compatible = "rockchip,rk3588-usb2phy";
-+ reg = <0x0 0x10>;
-+ #clock-cells = <0>;
-+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-+ clock-names = "phyclk";
-+ clock-output-names = "usb480m_phy0";
-+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
-+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
-+ reset-names = "phy", "apb";
-+ status = "disabled";
-+
-+ u2phy0_otg: otg-port {
-+ #phy-cells = <0>;
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
- usb2phy2_grf: syscon@fd5d8000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
- reg = <0x0 0xfd5d8000 0x0 0x4000>;
-@@ -2449,6 +2490,28 @@
- status = "disabled";
- };
-
-+ usbdp_phy0: phy@fed80000 {
-+ compatible = "rockchip,rk3588-usbdp-phy";
-+ reg = <0x0 0xfed80000 0x0 0x10000>;
-+ #phy-cells = <1>;
-+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
-+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
-+ <&cru PCLK_USBDPPHY0>,
-+ <&u2phy0>;
-+ clock-names = "refclk", "immortal", "pclk", "utmi";
-+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
-+ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
-+ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
-+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
-+ <&cru SRST_P_USBDPPHY0>;
-+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
-+ rockchip,u2phy-grf = <&usb2phy0_grf>;
-+ rockchip,usb-grf = <&usb_grf>;
-+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
-+ rockchip,vo-grf = <&vo0_grf>;
-+ status = "disabled";
-+ };
-+
- combphy0_ps: phy@fee00000 {
- compatible = "rockchip,rk3588-naneng-combphy";
- reg = <0x0 0xfee00000 0x0 0x100>;
+++ /dev/null
-From 33f393a2a990e16f56931ca708295f31d2b44415 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Tue, 9 Apr 2024 00:50:34 +0200
-Subject: [PATCH] arm64: dts: rockchip: add USB3 DRD controllers on rk3588
-
-Add both USB3 dual-role controllers to the RK3588 devicetree.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 ++++++++++++++++++++
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++
- 2 files changed, 42 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
-@@ -7,6 +7,26 @@
- #include "rk3588-pinctrl.dtsi"
-
- / {
-+ usb_host1_xhci: usb@fc400000 {
-+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
-+ reg = <0x0 0xfc400000 0x0 0x400000>;
-+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
-+ <&cru ACLK_USB3OTG1>;
-+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
-+ dr_mode = "otg";
-+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ phy_type = "utmi_wide";
-+ power-domains = <&power RK3588_PD_USB>;
-+ resets = <&cru SRST_A_USB3OTG1>;
-+ snps,dis_enblslpm_quirk;
-+ snps,dis-u2-freeclk-exists-quirk;
-+ snps,dis-del-phy-power-chg-quirk;
-+ snps,dis-tx-ipgap-linecheck-quirk;
-+ status = "disabled";
-+ };
-+
- pcie30_phy_grf: syscon@fd5b8000 {
- compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
- reg = <0x0 0xfd5b8000 0x0 0x10000>;
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -492,6 +492,28 @@
- };
- };
-
-+ usb_host0_xhci: usb@fc000000 {
-+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
-+ reg = <0x0 0xfc000000 0x0 0x400000>;
-+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
-+ <&cru ACLK_USB3OTG0>;
-+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
-+ dr_mode = "otg";
-+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ phy_type = "utmi_wide";
-+ power-domains = <&power RK3588_PD_USB>;
-+ resets = <&cru SRST_A_USB3OTG0>;
-+ snps,dis_enblslpm_quirk;
-+ snps,dis-u1-entry-quirk;
-+ snps,dis-u2-entry-quirk;
-+ snps,dis-u2-freeclk-exists-quirk;
-+ snps,dis-del-phy-power-chg-quirk;
-+ snps,dis-tx-ipgap-linecheck-quirk;
-+ status = "disabled";
-+ };
-+
- usb_host0_ehci: usb@fc800000 {
- compatible = "rockchip,rk3588-ehci", "generic-ehci";
- reg = <0x0 0xfc800000 0x0 0x40000>;
+++ /dev/null
-From cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 Mon Sep 17 00:00:00 2001
-From: Niklas Cassel <cassel@kernel.org>
-Date: Thu, 2 May 2024 16:02:32 +0200
-Subject: [PATCH] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs
-
-The mmu600_pcie is connected with the five PCIe controllers.
-The mmu600_php is connected with the USB3 controller, the GMAC
-controllers, and the SATA controllers.
-
-See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual).
-
-The IOMMUs are disabled by default, as further patches are needed to
-program the SID/SSIDs in to the IOMMUs.
-
-iommu: Default domain type: Translated
-iommu: DMA domain TLB invalidation policy: strict mode
-arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf)
-arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq
-arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq
-arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs
-
-Additionally, the IOMMU correctly triggers an IOMMU fault when
-a PCIe device performs a write (since the device hasn't been
-assigned a SID/SSID):
-arm-smmu-v3 fc900000.iommu: event 0x02 received:
-arm-smmu-v3 fc900000.iommu: 0x0000010000000002
-arm-smmu-v3 fc900000.iommu: 0x0000000000000000
-arm-smmu-v3 fc900000.iommu: 0x0000000000000000
-arm-smmu-v3 fc900000.iommu: 0x0000000000000000
-
-While this doesn't provide much value as is, having the devices as
-disabled in the device tree will allow developers to see that the rk3588
-actually has IOMMUs on the SoC.
-
-Signed-off-by: Niklas Cassel <cassel@kernel.org>
-Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 24 +++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -579,6 +579,30 @@
- status = "disabled";
- };
-
-+ mmu600_pcie: iommu@fc900000 {
-+ compatible = "arm,smmu-v3";
-+ reg = <0x0 0xfc900000 0x0 0x200000>;
-+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
-+ #iommu-cells = <1>;
-+ status = "disabled";
-+ };
-+
-+ mmu600_php: iommu@fcb00000 {
-+ compatible = "arm,smmu-v3";
-+ reg = <0x0 0xfcb00000 0x0 0x200000>;
-+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
-+ #iommu-cells = <1>;
-+ status = "disabled";
-+ };
-+
- pmu1grf: syscon@fd58a000 {
- compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
- reg = <0x0 0xfd58a000 0x0 0x10000>;
+++ /dev/null
-From def88eb4d8365a4aa064d28405d03550a9d0a3be Mon Sep 17 00:00:00 2001
-From: Dragan Simic <dsimic@manjaro.org>
-Date: Sun, 9 Jun 2024 10:58:19 +0200
-Subject: [PATCH] arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for
- per-variant OPPs
-
-Rename the Rockchip RK3588 SoC dtsi files and, consequently, adjust their
-contents appropriately, to prepare them for the ability to specify different
-CPU and GPU OPPs for each of the supported RK3588 SoC variants.
-
-As already discussed, [1][2][3][4] some of the RK3588 SoC variants require
-different OPPs, and it makes more sense to have the OPPs already defined when
-a board dts(i) file includes one of the SoC variant dtsi files (rk3588.dtsi,
-rk3588j.dtsi or rk3588s.dtsi), rather than requiring the board dts(i) file
-to also include a separate rk3588*-opp.dtsi file. The choice of the SoC
-variant is already made by the inclusion of the SoC dtsi file into the board
-dts(i) file, and it doesn't make much sense to, effectively, allow the board
-dts(i) file to include and use an incompatible set of OPPs for the already
-selected RK3588 SoC variant.
-
-The new naming scheme for the RK3588 SoC dtsi files uses "-base" and "-extra"
-suffixes to denote the DT data shared between all RK5588 SoC variants, and
-the DT data shared between the unrestricted SoC variants, respectively.
-For example, the DT data for the RK3588 includes both rk3588-base.dtsi and
-rk3588-extra.dtsi, because it's an unrestricted SoC variant, while the DT
-data for the RK3588S variant includes rk3588-base.dtsi only, because it's
-a restricted SoC variant, feature- and interface-wise. This achieves a more
-logical naming of the RK3588 SoC dtsi files, which reflects the way DT data
-for the SoC variants is built by "stacking" the SoC variant features made
-available through the "-base" and "-extra" SoC dtsi files. Additionally,
-the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi and rk3588s.dtsi) are
-no longer parents to any other SoC variant dtsi files, which should help with
-making the new "stacking" approach cleaner and easier to follow.
-
-The RK3588 pinctrl dtsi files are also renamed in the same way, for the sake
-of consistency. This also keeps the "-base" and "-extra" groups of the dtsi
-files together when looked at in a directory listing, which is helpful.
-
-The per-SoC-variant OPPs should go directly into the SoC dtsi files, if no
-more than one SoC variant uses those OPPs, or be put into a separate "-opp"
-dtsi file that's shared between and included from two or more SoC variant
-dtsi files. An example for the former is the non-shared OPP data that should
-go directly into the RK3588J SoC variant dtsi file (i.e. rk3588j.dtsi), and
-an example for the latter is the shared OPP data that should be put into
-rk3588-opp.dtsi and be included from the RK3588 and RK3588S SoC variant dtsi
-files (i.e. rk3588.dtsi and rk3588s.dtsi, respectively). Consequently, if
-the OPPs for the RK3588 and RK3588S SoC variants are ever made different,
-the shared rk3588-opp.dtsi file should be deleted and the new OPPs should
-be put directly into rk3588.dtsi and rk3588s.dtsi. [4]
-
-No functional changes are introduced, which was validated by decompiling and
-comparing all affected dtb files before and after these changes.
-
-As a side note, due to the nature of introduced changes, this commit is best
-viewed using the --break-rewrites option for git-log(1).
-
-[1] https://lore.kernel.org/linux-rockchip/646a33e0-5c1b-471c-8183-2c0df40ea51a@cherry.de/
-[2] https://lore.kernel.org/linux-rockchip/CABjd4Yxi=+3gkNnH3BysUzzYsji-=-yROtzEc8jM_g0roKB0-w@mail.gmail.com/
-[3] https://lore.kernel.org/linux-rockchip/035a274be262528012173d463e25b55f@manjaro.org/
-[4] https://lore.kernel.org/linux-rockchip/673dcf47596e7bc8ba065034e339bb1bbf9cdcb0.1716948159.git.dsimic@manjaro.org/T/#u
-
-Signed-off-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/9ffedc0e2ca7f167d9d795b2a8f43cb9f56a653b.1717923308.git.dsimic@manjaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- ...-pinctrl.dtsi => rk3588-base-pinctrl.dtsi} | 0
- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2670 +++++++++++++++++
- ...pinctrl.dtsi => rk3588-extra-pinctrl.dtsi} | 0
- .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 413 +++
- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 412 +--
- arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 2 +-
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2669 +---------------
- 7 files changed, 3090 insertions(+), 3076 deletions(-)
- rename arch/arm64/boot/dts/rockchip/{rk3588s-pinctrl.dtsi => rk3588-base-pinctrl.dtsi} (100%)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
- rename arch/arm64/boot/dts/rockchip/{rk3588-pinctrl.dtsi => rk3588-extra-pinctrl.dtsi} (100%)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-@@ -0,0 +1,2670 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+ */
-+
-+#include <dt-bindings/clock/rockchip,rk3588-cru.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/power/rk3588-power.h>
-+#include <dt-bindings/reset/rockchip,rk3588-cru.h>
-+#include <dt-bindings/phy/phy.h>
-+#include <dt-bindings/ata/ahci.h>
-+
-+/ {
-+ compatible = "rockchip,rk3588";
-+
-+ interrupt-parent = <&gic>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ aliases {
-+ gpio0 = &gpio0;
-+ gpio1 = &gpio1;
-+ gpio2 = &gpio2;
-+ gpio3 = &gpio3;
-+ gpio4 = &gpio4;
-+ i2c0 = &i2c0;
-+ i2c1 = &i2c1;
-+ i2c2 = &i2c2;
-+ i2c3 = &i2c3;
-+ i2c4 = &i2c4;
-+ i2c5 = &i2c5;
-+ i2c6 = &i2c6;
-+ i2c7 = &i2c7;
-+ i2c8 = &i2c8;
-+ serial0 = &uart0;
-+ serial1 = &uart1;
-+ serial2 = &uart2;
-+ serial3 = &uart3;
-+ serial4 = &uart4;
-+ serial5 = &uart5;
-+ serial6 = &uart6;
-+ serial7 = &uart7;
-+ serial8 = &uart8;
-+ serial9 = &uart9;
-+ spi0 = &spi0;
-+ spi1 = &spi1;
-+ spi2 = &spi2;
-+ spi3 = &spi3;
-+ spi4 = &spi4;
-+ };
-+
-+ cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ cpu-map {
-+ cluster0 {
-+ core0 {
-+ cpu = <&cpu_l0>;
-+ };
-+ core1 {
-+ cpu = <&cpu_l1>;
-+ };
-+ core2 {
-+ cpu = <&cpu_l2>;
-+ };
-+ core3 {
-+ cpu = <&cpu_l3>;
-+ };
-+ };
-+ cluster1 {
-+ core0 {
-+ cpu = <&cpu_b0>;
-+ };
-+ core1 {
-+ cpu = <&cpu_b1>;
-+ };
-+ };
-+ cluster2 {
-+ core0 {
-+ cpu = <&cpu_b2>;
-+ };
-+ core1 {
-+ cpu = <&cpu_b3>;
-+ };
-+ };
-+ };
-+
-+ cpu_l0: cpu@0 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a55";
-+ reg = <0x0>;
-+ enable-method = "psci";
-+ capacity-dmips-mhz = <530>;
-+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
-+ assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
-+ assigned-clock-rates = <816000000>;
-+ cpu-idle-states = <&CPU_SLEEP>;
-+ i-cache-size = <32768>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <128>;
-+ d-cache-size = <32768>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ next-level-cache = <&l2_cache_l0>;
-+ dynamic-power-coefficient = <228>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ cpu_l1: cpu@100 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a55";
-+ reg = <0x100>;
-+ enable-method = "psci";
-+ capacity-dmips-mhz = <530>;
-+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
-+ cpu-idle-states = <&CPU_SLEEP>;
-+ i-cache-size = <32768>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <128>;
-+ d-cache-size = <32768>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ next-level-cache = <&l2_cache_l1>;
-+ dynamic-power-coefficient = <228>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ cpu_l2: cpu@200 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a55";
-+ reg = <0x200>;
-+ enable-method = "psci";
-+ capacity-dmips-mhz = <530>;
-+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
-+ cpu-idle-states = <&CPU_SLEEP>;
-+ i-cache-size = <32768>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <128>;
-+ d-cache-size = <32768>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ next-level-cache = <&l2_cache_l2>;
-+ dynamic-power-coefficient = <228>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ cpu_l3: cpu@300 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a55";
-+ reg = <0x300>;
-+ enable-method = "psci";
-+ capacity-dmips-mhz = <530>;
-+ clocks = <&scmi_clk SCMI_CLK_CPUL>;
-+ cpu-idle-states = <&CPU_SLEEP>;
-+ i-cache-size = <32768>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <128>;
-+ d-cache-size = <32768>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <128>;
-+ next-level-cache = <&l2_cache_l3>;
-+ dynamic-power-coefficient = <228>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ cpu_b0: cpu@400 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a76";
-+ reg = <0x400>;
-+ enable-method = "psci";
-+ capacity-dmips-mhz = <1024>;
-+ clocks = <&scmi_clk SCMI_CLK_CPUB01>;
-+ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
-+ assigned-clock-rates = <816000000>;
-+ cpu-idle-states = <&CPU_SLEEP>;
-+ i-cache-size = <65536>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <256>;
-+ d-cache-size = <65536>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <256>;
-+ next-level-cache = <&l2_cache_b0>;
-+ dynamic-power-coefficient = <416>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ cpu_b1: cpu@500 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a76";
-+ reg = <0x500>;
-+ enable-method = "psci";
-+ capacity-dmips-mhz = <1024>;
-+ clocks = <&scmi_clk SCMI_CLK_CPUB01>;
-+ cpu-idle-states = <&CPU_SLEEP>;
-+ i-cache-size = <65536>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <256>;
-+ d-cache-size = <65536>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <256>;
-+ next-level-cache = <&l2_cache_b1>;
-+ dynamic-power-coefficient = <416>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ cpu_b2: cpu@600 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a76";
-+ reg = <0x600>;
-+ enable-method = "psci";
-+ capacity-dmips-mhz = <1024>;
-+ clocks = <&scmi_clk SCMI_CLK_CPUB23>;
-+ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
-+ assigned-clock-rates = <816000000>;
-+ cpu-idle-states = <&CPU_SLEEP>;
-+ i-cache-size = <65536>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <256>;
-+ d-cache-size = <65536>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <256>;
-+ next-level-cache = <&l2_cache_b2>;
-+ dynamic-power-coefficient = <416>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ cpu_b3: cpu@700 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a76";
-+ reg = <0x700>;
-+ enable-method = "psci";
-+ capacity-dmips-mhz = <1024>;
-+ clocks = <&scmi_clk SCMI_CLK_CPUB23>;
-+ cpu-idle-states = <&CPU_SLEEP>;
-+ i-cache-size = <65536>;
-+ i-cache-line-size = <64>;
-+ i-cache-sets = <256>;
-+ d-cache-size = <65536>;
-+ d-cache-line-size = <64>;
-+ d-cache-sets = <256>;
-+ next-level-cache = <&l2_cache_b3>;
-+ dynamic-power-coefficient = <416>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ idle-states {
-+ entry-method = "psci";
-+ CPU_SLEEP: cpu-sleep {
-+ compatible = "arm,idle-state";
-+ local-timer-stop;
-+ arm,psci-suspend-param = <0x0010000>;
-+ entry-latency-us = <100>;
-+ exit-latency-us = <120>;
-+ min-residency-us = <1000>;
-+ };
-+ };
-+
-+ l2_cache_l0: l2-cache-l0 {
-+ compatible = "cache";
-+ cache-size = <131072>;
-+ cache-line-size = <64>;
-+ cache-sets = <512>;
-+ cache-level = <2>;
-+ cache-unified;
-+ next-level-cache = <&l3_cache>;
-+ };
-+
-+ l2_cache_l1: l2-cache-l1 {
-+ compatible = "cache";
-+ cache-size = <131072>;
-+ cache-line-size = <64>;
-+ cache-sets = <512>;
-+ cache-level = <2>;
-+ cache-unified;
-+ next-level-cache = <&l3_cache>;
-+ };
-+
-+ l2_cache_l2: l2-cache-l2 {
-+ compatible = "cache";
-+ cache-size = <131072>;
-+ cache-line-size = <64>;
-+ cache-sets = <512>;
-+ cache-level = <2>;
-+ cache-unified;
-+ next-level-cache = <&l3_cache>;
-+ };
-+
-+ l2_cache_l3: l2-cache-l3 {
-+ compatible = "cache";
-+ cache-size = <131072>;
-+ cache-line-size = <64>;
-+ cache-sets = <512>;
-+ cache-level = <2>;
-+ cache-unified;
-+ next-level-cache = <&l3_cache>;
-+ };
-+
-+ l2_cache_b0: l2-cache-b0 {
-+ compatible = "cache";
-+ cache-size = <524288>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ cache-unified;
-+ next-level-cache = <&l3_cache>;
-+ };
-+
-+ l2_cache_b1: l2-cache-b1 {
-+ compatible = "cache";
-+ cache-size = <524288>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ cache-unified;
-+ next-level-cache = <&l3_cache>;
-+ };
-+
-+ l2_cache_b2: l2-cache-b2 {
-+ compatible = "cache";
-+ cache-size = <524288>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ cache-unified;
-+ next-level-cache = <&l3_cache>;
-+ };
-+
-+ l2_cache_b3: l2-cache-b3 {
-+ compatible = "cache";
-+ cache-size = <524288>;
-+ cache-line-size = <64>;
-+ cache-sets = <1024>;
-+ cache-level = <2>;
-+ cache-unified;
-+ next-level-cache = <&l3_cache>;
-+ };
-+
-+ l3_cache: l3-cache {
-+ compatible = "cache";
-+ cache-size = <3145728>;
-+ cache-line-size = <64>;
-+ cache-sets = <4096>;
-+ cache-level = <3>;
-+ cache-unified;
-+ };
-+ };
-+
-+ display_subsystem: display-subsystem {
-+ compatible = "rockchip,display-subsystem";
-+ ports = <&vop_out>;
-+ };
-+
-+ firmware {
-+ optee: optee {
-+ compatible = "linaro,optee-tz";
-+ method = "smc";
-+ };
-+
-+ scmi: scmi {
-+ compatible = "arm,scmi-smc";
-+ arm,smc-id = <0x82000010>;
-+ shmem = <&scmi_shmem>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ scmi_clk: protocol@14 {
-+ reg = <0x14>;
-+ #clock-cells = <1>;
-+ };
-+
-+ scmi_reset: protocol@16 {
-+ reg = <0x16>;
-+ #reset-cells = <1>;
-+ };
-+ };
-+ };
-+
-+ pmu-a55 {
-+ compatible = "arm,cortex-a55-pmu";
-+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
-+ };
-+
-+ pmu-a76 {
-+ compatible = "arm,cortex-a76-pmu";
-+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
-+ };
-+
-+ psci {
-+ compatible = "arm,psci-1.0";
-+ method = "smc";
-+ };
-+
-+ spll: clock-0 {
-+ compatible = "fixed-clock";
-+ clock-frequency = <702000000>;
-+ clock-output-names = "spll";
-+ #clock-cells = <0>;
-+ };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
-+ };
-+
-+ xin24m: clock-1 {
-+ compatible = "fixed-clock";
-+ clock-frequency = <24000000>;
-+ clock-output-names = "xin24m";
-+ #clock-cells = <0>;
-+ };
-+
-+ xin32k: clock-2 {
-+ compatible = "fixed-clock";
-+ clock-frequency = <32768>;
-+ clock-output-names = "xin32k";
-+ #clock-cells = <0>;
-+ };
-+
-+ pmu_sram: sram@10f000 {
-+ compatible = "mmio-sram";
-+ reg = <0x0 0x0010f000 0x0 0x100>;
-+ ranges = <0 0x0 0x0010f000 0x100>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ scmi_shmem: sram@0 {
-+ compatible = "arm,scmi-shmem";
-+ reg = <0x0 0x100>;
-+ };
-+ };
-+
-+ gpu: gpu@fb000000 {
-+ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
-+ reg = <0x0 0xfb000000 0x0 0x200000>;
-+ #cooling-cells = <2>;
-+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
-+ assigned-clock-rates = <200000000>;
-+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
-+ <&cru CLK_GPU_STACKS>;
-+ clock-names = "core", "coregroup", "stacks";
-+ dynamic-power-coefficient = <2982>;
-+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "job", "mmu", "gpu";
-+ operating-points-v2 = <&gpu_opp_table>;
-+ power-domains = <&power RK3588_PD_GPU>;
-+ status = "disabled";
-+
-+ gpu_opp_table: opp-table {
-+ compatible = "operating-points-v2";
-+
-+ opp-300000000 {
-+ opp-hz = /bits/ 64 <300000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-400000000 {
-+ opp-hz = /bits/ 64 <400000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-500000000 {
-+ opp-hz = /bits/ 64 <500000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-600000000 {
-+ opp-hz = /bits/ 64 <600000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-700000000 {
-+ opp-hz = /bits/ 64 <700000000>;
-+ opp-microvolt = <700000 700000 850000>;
-+ };
-+ opp-800000000 {
-+ opp-hz = /bits/ 64 <800000000>;
-+ opp-microvolt = <750000 750000 850000>;
-+ };
-+ opp-900000000 {
-+ opp-hz = /bits/ 64 <900000000>;
-+ opp-microvolt = <800000 800000 850000>;
-+ };
-+ opp-1000000000 {
-+ opp-hz = /bits/ 64 <1000000000>;
-+ opp-microvolt = <850000 850000 850000>;
-+ };
-+ };
-+ };
-+
-+ usb_host0_xhci: usb@fc000000 {
-+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
-+ reg = <0x0 0xfc000000 0x0 0x400000>;
-+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
-+ <&cru ACLK_USB3OTG0>;
-+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
-+ dr_mode = "otg";
-+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ phy_type = "utmi_wide";
-+ power-domains = <&power RK3588_PD_USB>;
-+ resets = <&cru SRST_A_USB3OTG0>;
-+ snps,dis_enblslpm_quirk;
-+ snps,dis-u1-entry-quirk;
-+ snps,dis-u2-entry-quirk;
-+ snps,dis-u2-freeclk-exists-quirk;
-+ snps,dis-del-phy-power-chg-quirk;
-+ snps,dis-tx-ipgap-linecheck-quirk;
-+ status = "disabled";
-+ };
-+
-+ usb_host0_ehci: usb@fc800000 {
-+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
-+ reg = <0x0 0xfc800000 0x0 0x40000>;
-+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
-+ phys = <&u2phy2_host>;
-+ phy-names = "usb";
-+ power-domains = <&power RK3588_PD_USB>;
-+ status = "disabled";
-+ };
-+
-+ usb_host0_ohci: usb@fc840000 {
-+ compatible = "rockchip,rk3588-ohci", "generic-ohci";
-+ reg = <0x0 0xfc840000 0x0 0x40000>;
-+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
-+ phys = <&u2phy2_host>;
-+ phy-names = "usb";
-+ power-domains = <&power RK3588_PD_USB>;
-+ status = "disabled";
-+ };
-+
-+ usb_host1_ehci: usb@fc880000 {
-+ compatible = "rockchip,rk3588-ehci", "generic-ehci";
-+ reg = <0x0 0xfc880000 0x0 0x40000>;
-+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
-+ phys = <&u2phy3_host>;
-+ phy-names = "usb";
-+ power-domains = <&power RK3588_PD_USB>;
-+ status = "disabled";
-+ };
-+
-+ usb_host1_ohci: usb@fc8c0000 {
-+ compatible = "rockchip,rk3588-ohci", "generic-ohci";
-+ reg = <0x0 0xfc8c0000 0x0 0x40000>;
-+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
-+ phys = <&u2phy3_host>;
-+ phy-names = "usb";
-+ power-domains = <&power RK3588_PD_USB>;
-+ status = "disabled";
-+ };
-+
-+ usb_host2_xhci: usb@fcd00000 {
-+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
-+ reg = <0x0 0xfcd00000 0x0 0x400000>;
-+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
-+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
-+ <&cru CLK_PIPEPHY2_PIPE_U3_G>;
-+ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
-+ dr_mode = "host";
-+ phys = <&combphy2_psu PHY_TYPE_USB3>;
-+ phy-names = "usb3-phy";
-+ phy_type = "utmi_wide";
-+ resets = <&cru SRST_A_USB3OTG2>;
-+ snps,dis_enblslpm_quirk;
-+ snps,dis-u2-freeclk-exists-quirk;
-+ snps,dis-del-phy-power-chg-quirk;
-+ snps,dis-tx-ipgap-linecheck-quirk;
-+ snps,dis_rxdet_inp3_quirk;
-+ status = "disabled";
-+ };
-+
-+ mmu600_pcie: iommu@fc900000 {
-+ compatible = "arm,smmu-v3";
-+ reg = <0x0 0xfc900000 0x0 0x200000>;
-+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
-+ #iommu-cells = <1>;
-+ status = "disabled";
-+ };
-+
-+ mmu600_php: iommu@fcb00000 {
-+ compatible = "arm,smmu-v3";
-+ reg = <0x0 0xfcb00000 0x0 0x200000>;
-+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
-+ #iommu-cells = <1>;
-+ status = "disabled";
-+ };
-+
-+ pmu1grf: syscon@fd58a000 {
-+ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
-+ reg = <0x0 0xfd58a000 0x0 0x10000>;
-+ };
-+
-+ sys_grf: syscon@fd58c000 {
-+ compatible = "rockchip,rk3588-sys-grf", "syscon";
-+ reg = <0x0 0xfd58c000 0x0 0x1000>;
-+ };
-+
-+ vop_grf: syscon@fd5a4000 {
-+ compatible = "rockchip,rk3588-vop-grf", "syscon";
-+ reg = <0x0 0xfd5a4000 0x0 0x2000>;
-+ };
-+
-+ vo0_grf: syscon@fd5a6000 {
-+ compatible = "rockchip,rk3588-vo-grf", "syscon";
-+ reg = <0x0 0xfd5a6000 0x0 0x2000>;
-+ clocks = <&cru PCLK_VO0GRF>;
-+ };
-+
-+ vo1_grf: syscon@fd5a8000 {
-+ compatible = "rockchip,rk3588-vo-grf", "syscon";
-+ reg = <0x0 0xfd5a8000 0x0 0x100>;
-+ clocks = <&cru PCLK_VO1GRF>;
-+ };
-+
-+ usb_grf: syscon@fd5ac000 {
-+ compatible = "rockchip,rk3588-usb-grf", "syscon";
-+ reg = <0x0 0xfd5ac000 0x0 0x4000>;
-+ };
-+
-+ php_grf: syscon@fd5b0000 {
-+ compatible = "rockchip,rk3588-php-grf", "syscon";
-+ reg = <0x0 0xfd5b0000 0x0 0x1000>;
-+ };
-+
-+ pipe_phy0_grf: syscon@fd5bc000 {
-+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
-+ reg = <0x0 0xfd5bc000 0x0 0x100>;
-+ };
-+
-+ pipe_phy2_grf: syscon@fd5c4000 {
-+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
-+ reg = <0x0 0xfd5c4000 0x0 0x100>;
-+ };
-+
-+ usbdpphy0_grf: syscon@fd5c8000 {
-+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
-+ reg = <0x0 0xfd5c8000 0x0 0x4000>;
-+ };
-+
-+ usb2phy0_grf: syscon@fd5d0000 {
-+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-+ reg = <0x0 0xfd5d0000 0x0 0x4000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ u2phy0: usb2phy@0 {
-+ compatible = "rockchip,rk3588-usb2phy";
-+ reg = <0x0 0x10>;
-+ #clock-cells = <0>;
-+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-+ clock-names = "phyclk";
-+ clock-output-names = "usb480m_phy0";
-+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
-+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
-+ reset-names = "phy", "apb";
-+ status = "disabled";
-+
-+ u2phy0_otg: otg-port {
-+ #phy-cells = <0>;
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ usb2phy2_grf: syscon@fd5d8000 {
-+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-+ reg = <0x0 0xfd5d8000 0x0 0x4000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ u2phy2: usb2phy@8000 {
-+ compatible = "rockchip,rk3588-usb2phy";
-+ reg = <0x8000 0x10>;
-+ #clock-cells = <0>;
-+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-+ clock-names = "phyclk";
-+ clock-output-names = "usb480m_phy2";
-+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
-+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
-+ reset-names = "phy", "apb";
-+ status = "disabled";
-+
-+ u2phy2_host: host-port {
-+ #phy-cells = <0>;
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ usb2phy3_grf: syscon@fd5dc000 {
-+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-+ reg = <0x0 0xfd5dc000 0x0 0x4000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ u2phy3: usb2phy@c000 {
-+ compatible = "rockchip,rk3588-usb2phy";
-+ reg = <0xc000 0x10>;
-+ #clock-cells = <0>;
-+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-+ clock-names = "phyclk";
-+ clock-output-names = "usb480m_phy3";
-+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
-+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
-+ reset-names = "phy", "apb";
-+ status = "disabled";
-+
-+ u2phy3_host: host-port {
-+ #phy-cells = <0>;
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ hdptxphy0_grf: syscon@fd5e0000 {
-+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
-+ reg = <0x0 0xfd5e0000 0x0 0x100>;
-+ };
-+
-+ ioc: syscon@fd5f0000 {
-+ compatible = "rockchip,rk3588-ioc", "syscon";
-+ reg = <0x0 0xfd5f0000 0x0 0x10000>;
-+ };
-+
-+ system_sram1: sram@fd600000 {
-+ compatible = "mmio-sram";
-+ reg = <0x0 0xfd600000 0x0 0x100000>;
-+ ranges = <0x0 0x0 0xfd600000 0x100000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ };
-+
-+ cru: clock-controller@fd7c0000 {
-+ compatible = "rockchip,rk3588-cru";
-+ reg = <0x0 0xfd7c0000 0x0 0x5c000>;
-+ assigned-clocks =
-+ <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
-+ <&cru PLL_NPLL>, <&cru PLL_GPLL>,
-+ <&cru ACLK_CENTER_ROOT>,
-+ <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
-+ <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
-+ <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
-+ <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
-+ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
-+ <&cru CLK_GPU>;
-+ assigned-clock-rates =
-+ <1100000000>, <786432000>,
-+ <850000000>, <1188000000>,
-+ <702000000>,
-+ <400000000>, <500000000>,
-+ <800000000>, <100000000>,
-+ <400000000>, <100000000>,
-+ <200000000>, <500000000>,
-+ <375000000>, <150000000>,
-+ <200000000>;
-+ rockchip,grf = <&php_grf>;
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ };
-+
-+ i2c0: i2c@fd880000 {
-+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-+ reg = <0x0 0xfd880000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
-+ clock-names = "i2c", "pclk";
-+ pinctrl-0 = <&i2c0m0_xfer>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ uart0: serial@fd890000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfd890000 0x0 0x100>;
-+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac0 6>, <&dmac0 7>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart0m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-shift = <2>;
-+ reg-io-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ pwm0: pwm@fd8b0000 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfd8b0000 0x0 0x10>;
-+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm0m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm1: pwm@fd8b0010 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfd8b0010 0x0 0x10>;
-+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm1m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm2: pwm@fd8b0020 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfd8b0020 0x0 0x10>;
-+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm2m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm3: pwm@fd8b0030 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfd8b0030 0x0 0x10>;
-+ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm3m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pmu: power-management@fd8d8000 {
-+ compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
-+ reg = <0x0 0xfd8d8000 0x0 0x400>;
-+
-+ power: power-controller {
-+ compatible = "rockchip,rk3588-power-controller";
-+ #address-cells = <1>;
-+ #power-domain-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ /* These power domains are grouped by VD_NPU */
-+ power-domain@RK3588_PD_NPU {
-+ reg = <RK3588_PD_NPU>;
-+ #power-domain-cells = <0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ power-domain@RK3588_PD_NPUTOP {
-+ reg = <RK3588_PD_NPUTOP>;
-+ clocks = <&cru HCLK_NPU_ROOT>,
-+ <&cru PCLK_NPU_ROOT>,
-+ <&cru CLK_NPU_DSU0>,
-+ <&cru HCLK_NPU_CM0_ROOT>;
-+ pm_qos = <&qos_npu0_mwr>,
-+ <&qos_npu0_mro>,
-+ <&qos_mcu_npu>;
-+ #power-domain-cells = <0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ power-domain@RK3588_PD_NPU1 {
-+ reg = <RK3588_PD_NPU1>;
-+ clocks = <&cru HCLK_NPU_ROOT>,
-+ <&cru PCLK_NPU_ROOT>,
-+ <&cru CLK_NPU_DSU0>;
-+ pm_qos = <&qos_npu1>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_NPU2 {
-+ reg = <RK3588_PD_NPU2>;
-+ clocks = <&cru HCLK_NPU_ROOT>,
-+ <&cru PCLK_NPU_ROOT>,
-+ <&cru CLK_NPU_DSU0>;
-+ pm_qos = <&qos_npu2>;
-+ #power-domain-cells = <0>;
-+ };
-+ };
-+ };
-+ /* These power domains are grouped by VD_GPU */
-+ power-domain@RK3588_PD_GPU {
-+ reg = <RK3588_PD_GPU>;
-+ clocks = <&cru CLK_GPU>,
-+ <&cru CLK_GPU_COREGROUP>,
-+ <&cru CLK_GPU_STACKS>;
-+ pm_qos = <&qos_gpu_m0>,
-+ <&qos_gpu_m1>,
-+ <&qos_gpu_m2>,
-+ <&qos_gpu_m3>;
-+ #power-domain-cells = <0>;
-+ };
-+ /* These power domains are grouped by VD_VCODEC */
-+ power-domain@RK3588_PD_VCODEC {
-+ reg = <RK3588_PD_VCODEC>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ #power-domain-cells = <0>;
-+
-+ power-domain@RK3588_PD_RKVDEC0 {
-+ reg = <RK3588_PD_RKVDEC0>;
-+ clocks = <&cru HCLK_RKVDEC0>,
-+ <&cru HCLK_VDPU_ROOT>,
-+ <&cru ACLK_VDPU_ROOT>,
-+ <&cru ACLK_RKVDEC0>,
-+ <&cru ACLK_RKVDEC_CCU>;
-+ pm_qos = <&qos_rkvdec0>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_RKVDEC1 {
-+ reg = <RK3588_PD_RKVDEC1>;
-+ clocks = <&cru HCLK_RKVDEC1>,
-+ <&cru HCLK_VDPU_ROOT>,
-+ <&cru ACLK_VDPU_ROOT>,
-+ <&cru ACLK_RKVDEC1>;
-+ pm_qos = <&qos_rkvdec1>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_VENC0 {
-+ reg = <RK3588_PD_VENC0>;
-+ clocks = <&cru HCLK_RKVENC0>,
-+ <&cru ACLK_RKVENC0>;
-+ pm_qos = <&qos_rkvenc0_m0ro>,
-+ <&qos_rkvenc0_m1ro>,
-+ <&qos_rkvenc0_m2wo>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ #power-domain-cells = <0>;
-+
-+ power-domain@RK3588_PD_VENC1 {
-+ reg = <RK3588_PD_VENC1>;
-+ clocks = <&cru HCLK_RKVENC1>,
-+ <&cru HCLK_RKVENC0>,
-+ <&cru ACLK_RKVENC0>,
-+ <&cru ACLK_RKVENC1>;
-+ pm_qos = <&qos_rkvenc1_m0ro>,
-+ <&qos_rkvenc1_m1ro>,
-+ <&qos_rkvenc1_m2wo>;
-+ #power-domain-cells = <0>;
-+ };
-+ };
-+ };
-+ /* These power domains are grouped by VD_LOGIC */
-+ power-domain@RK3588_PD_VDPU {
-+ reg = <RK3588_PD_VDPU>;
-+ clocks = <&cru HCLK_VDPU_ROOT>,
-+ <&cru ACLK_VDPU_LOW_ROOT>,
-+ <&cru ACLK_VDPU_ROOT>,
-+ <&cru ACLK_JPEG_DECODER_ROOT>,
-+ <&cru ACLK_IEP2P0>,
-+ <&cru HCLK_IEP2P0>,
-+ <&cru ACLK_JPEG_ENCODER0>,
-+ <&cru HCLK_JPEG_ENCODER0>,
-+ <&cru ACLK_JPEG_ENCODER1>,
-+ <&cru HCLK_JPEG_ENCODER1>,
-+ <&cru ACLK_JPEG_ENCODER2>,
-+ <&cru HCLK_JPEG_ENCODER2>,
-+ <&cru ACLK_JPEG_ENCODER3>,
-+ <&cru HCLK_JPEG_ENCODER3>,
-+ <&cru ACLK_JPEG_DECODER>,
-+ <&cru HCLK_JPEG_DECODER>,
-+ <&cru ACLK_RGA2>,
-+ <&cru HCLK_RGA2>;
-+ pm_qos = <&qos_iep>,
-+ <&qos_jpeg_dec>,
-+ <&qos_jpeg_enc0>,
-+ <&qos_jpeg_enc1>,
-+ <&qos_jpeg_enc2>,
-+ <&qos_jpeg_enc3>,
-+ <&qos_rga2_mro>,
-+ <&qos_rga2_mwo>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ #power-domain-cells = <0>;
-+
-+
-+ power-domain@RK3588_PD_AV1 {
-+ reg = <RK3588_PD_AV1>;
-+ clocks = <&cru PCLK_AV1>,
-+ <&cru ACLK_AV1>,
-+ <&cru HCLK_VDPU_ROOT>;
-+ pm_qos = <&qos_av1>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_RKVDEC0 {
-+ reg = <RK3588_PD_RKVDEC0>;
-+ clocks = <&cru HCLK_RKVDEC0>,
-+ <&cru HCLK_VDPU_ROOT>,
-+ <&cru ACLK_VDPU_ROOT>,
-+ <&cru ACLK_RKVDEC0>;
-+ pm_qos = <&qos_rkvdec0>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_RKVDEC1 {
-+ reg = <RK3588_PD_RKVDEC1>;
-+ clocks = <&cru HCLK_RKVDEC1>,
-+ <&cru HCLK_VDPU_ROOT>,
-+ <&cru ACLK_VDPU_ROOT>;
-+ pm_qos = <&qos_rkvdec1>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_RGA30 {
-+ reg = <RK3588_PD_RGA30>;
-+ clocks = <&cru ACLK_RGA3_0>,
-+ <&cru HCLK_RGA3_0>;
-+ pm_qos = <&qos_rga3_0>;
-+ #power-domain-cells = <0>;
-+ };
-+ };
-+ power-domain@RK3588_PD_VOP {
-+ reg = <RK3588_PD_VOP>;
-+ clocks = <&cru PCLK_VOP_ROOT>,
-+ <&cru HCLK_VOP_ROOT>,
-+ <&cru ACLK_VOP>;
-+ pm_qos = <&qos_vop_m0>,
-+ <&qos_vop_m1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ #power-domain-cells = <0>;
-+
-+ power-domain@RK3588_PD_VO0 {
-+ reg = <RK3588_PD_VO0>;
-+ clocks = <&cru PCLK_VO0_ROOT>,
-+ <&cru PCLK_VO0_S_ROOT>,
-+ <&cru HCLK_VO0_S_ROOT>,
-+ <&cru ACLK_VO0_ROOT>,
-+ <&cru HCLK_HDCP0>,
-+ <&cru ACLK_HDCP0>,
-+ <&cru HCLK_VOP_ROOT>;
-+ pm_qos = <&qos_hdcp0>;
-+ #power-domain-cells = <0>;
-+ };
-+ };
-+ power-domain@RK3588_PD_VO1 {
-+ reg = <RK3588_PD_VO1>;
-+ clocks = <&cru PCLK_VO1_ROOT>,
-+ <&cru PCLK_VO1_S_ROOT>,
-+ <&cru HCLK_VO1_S_ROOT>,
-+ <&cru HCLK_HDCP1>,
-+ <&cru ACLK_HDCP1>,
-+ <&cru ACLK_HDMIRX_ROOT>,
-+ <&cru HCLK_VO1USB_TOP_ROOT>;
-+ pm_qos = <&qos_hdcp1>,
-+ <&qos_hdmirx>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_VI {
-+ reg = <RK3588_PD_VI>;
-+ clocks = <&cru HCLK_VI_ROOT>,
-+ <&cru PCLK_VI_ROOT>,
-+ <&cru HCLK_ISP0>,
-+ <&cru ACLK_ISP0>,
-+ <&cru HCLK_VICAP>,
-+ <&cru ACLK_VICAP>;
-+ pm_qos = <&qos_isp0_mro>,
-+ <&qos_isp0_mwo>,
-+ <&qos_vicap_m0>,
-+ <&qos_vicap_m1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ #power-domain-cells = <0>;
-+
-+ power-domain@RK3588_PD_ISP1 {
-+ reg = <RK3588_PD_ISP1>;
-+ clocks = <&cru HCLK_ISP1>,
-+ <&cru ACLK_ISP1>,
-+ <&cru HCLK_VI_ROOT>,
-+ <&cru PCLK_VI_ROOT>;
-+ pm_qos = <&qos_isp1_mwo>,
-+ <&qos_isp1_mro>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_FEC {
-+ reg = <RK3588_PD_FEC>;
-+ clocks = <&cru HCLK_FISHEYE0>,
-+ <&cru ACLK_FISHEYE0>,
-+ <&cru HCLK_FISHEYE1>,
-+ <&cru ACLK_FISHEYE1>,
-+ <&cru PCLK_VI_ROOT>;
-+ pm_qos = <&qos_fisheye0>,
-+ <&qos_fisheye1>;
-+ #power-domain-cells = <0>;
-+ };
-+ };
-+ power-domain@RK3588_PD_RGA31 {
-+ reg = <RK3588_PD_RGA31>;
-+ clocks = <&cru HCLK_RGA3_1>,
-+ <&cru ACLK_RGA3_1>;
-+ pm_qos = <&qos_rga3_1>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_USB {
-+ reg = <RK3588_PD_USB>;
-+ clocks = <&cru PCLK_PHP_ROOT>,
-+ <&cru ACLK_USB_ROOT>,
-+ <&cru ACLK_USB>,
-+ <&cru HCLK_USB_ROOT>,
-+ <&cru HCLK_HOST0>,
-+ <&cru HCLK_HOST_ARB0>,
-+ <&cru HCLK_HOST1>,
-+ <&cru HCLK_HOST_ARB1>;
-+ pm_qos = <&qos_usb3_0>,
-+ <&qos_usb3_1>,
-+ <&qos_usb2host_0>,
-+ <&qos_usb2host_1>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_GMAC {
-+ reg = <RK3588_PD_GMAC>;
-+ clocks = <&cru PCLK_PHP_ROOT>,
-+ <&cru ACLK_PCIE_ROOT>,
-+ <&cru ACLK_PHP_ROOT>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_PCIE {
-+ reg = <RK3588_PD_PCIE>;
-+ clocks = <&cru PCLK_PHP_ROOT>,
-+ <&cru ACLK_PCIE_ROOT>,
-+ <&cru ACLK_PHP_ROOT>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_SDIO {
-+ reg = <RK3588_PD_SDIO>;
-+ clocks = <&cru HCLK_SDIO>,
-+ <&cru HCLK_NVM_ROOT>;
-+ pm_qos = <&qos_sdio>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_AUDIO {
-+ reg = <RK3588_PD_AUDIO>;
-+ clocks = <&cru HCLK_AUDIO_ROOT>,
-+ <&cru PCLK_AUDIO_ROOT>;
-+ #power-domain-cells = <0>;
-+ };
-+ power-domain@RK3588_PD_SDMMC {
-+ reg = <RK3588_PD_SDMMC>;
-+ pm_qos = <&qos_sdmmc>;
-+ #power-domain-cells = <0>;
-+ };
-+ };
-+ };
-+
-+ av1d: video-codec@fdc70000 {
-+ compatible = "rockchip,rk3588-av1-vpu";
-+ reg = <0x0 0xfdc70000 0x0 0x800>;
-+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "vdpu";
-+ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-+ assigned-clock-rates = <400000000>, <400000000>;
-+ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-+ clock-names = "aclk", "hclk";
-+ power-domains = <&power RK3588_PD_AV1>;
-+ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
-+ };
-+
-+ vop: vop@fdd90000 {
-+ compatible = "rockchip,rk3588-vop";
-+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
-+ reg-names = "vop", "gamma-lut";
-+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru ACLK_VOP>,
-+ <&cru HCLK_VOP>,
-+ <&cru DCLK_VOP0>,
-+ <&cru DCLK_VOP1>,
-+ <&cru DCLK_VOP2>,
-+ <&cru DCLK_VOP3>,
-+ <&cru PCLK_VOP_ROOT>;
-+ clock-names = "aclk",
-+ "hclk",
-+ "dclk_vp0",
-+ "dclk_vp1",
-+ "dclk_vp2",
-+ "dclk_vp3",
-+ "pclk_vop";
-+ iommus = <&vop_mmu>;
-+ power-domains = <&power RK3588_PD_VOP>;
-+ rockchip,grf = <&sys_grf>;
-+ rockchip,vop-grf = <&vop_grf>;
-+ rockchip,vo1-grf = <&vo1_grf>;
-+ rockchip,pmu = <&pmu>;
-+ status = "disabled";
-+
-+ vop_out: ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ vp0: port@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0>;
-+ };
-+
-+ vp1: port@1 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <1>;
-+ };
-+
-+ vp2: port@2 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <2>;
-+ };
-+
-+ vp3: port@3 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <3>;
-+ };
-+ };
-+ };
-+
-+ vop_mmu: iommu@fdd97e00 {
-+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
-+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
-+ clock-names = "aclk", "iface";
-+ #iommu-cells = <0>;
-+ power-domains = <&power RK3588_PD_VOP>;
-+ status = "disabled";
-+ };
-+
-+ i2s4_8ch: i2s@fddc0000 {
-+ compatible = "rockchip,rk3588-i2s-tdm";
-+ reg = <0x0 0xfddc0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
-+ clock-names = "mclk_tx", "mclk_rx", "hclk";
-+ assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>;
-+ dmas = <&dmac2 0>;
-+ dma-names = "tx";
-+ power-domains = <&power RK3588_PD_VO0>;
-+ resets = <&cru SRST_M_I2S4_8CH_TX>;
-+ reset-names = "tx-m";
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2s5_8ch: i2s@fddf0000 {
-+ compatible = "rockchip,rk3588-i2s-tdm";
-+ reg = <0x0 0xfddf0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
-+ clock-names = "mclk_tx", "mclk_rx", "hclk";
-+ assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>;
-+ dmas = <&dmac2 2>;
-+ dma-names = "tx";
-+ power-domains = <&power RK3588_PD_VO1>;
-+ resets = <&cru SRST_M_I2S5_8CH_TX>;
-+ reset-names = "tx-m";
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2s9_8ch: i2s@fddfc000 {
-+ compatible = "rockchip,rk3588-i2s-tdm";
-+ reg = <0x0 0xfddfc000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
-+ clock-names = "mclk_tx", "mclk_rx", "hclk";
-+ assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>;
-+ dmas = <&dmac2 23>;
-+ dma-names = "rx";
-+ power-domains = <&power RK3588_PD_VO1>;
-+ resets = <&cru SRST_M_I2S9_8CH_RX>;
-+ reset-names = "rx-m";
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ qos_gpu_m0: qos@fdf35000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf35000 0x0 0x20>;
-+ };
-+
-+ qos_gpu_m1: qos@fdf35200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf35200 0x0 0x20>;
-+ };
-+
-+ qos_gpu_m2: qos@fdf35400 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf35400 0x0 0x20>;
-+ };
-+
-+ qos_gpu_m3: qos@fdf35600 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf35600 0x0 0x20>;
-+ };
-+
-+ qos_rga3_1: qos@fdf36000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf36000 0x0 0x20>;
-+ };
-+
-+ qos_sdio: qos@fdf39000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf39000 0x0 0x20>;
-+ };
-+
-+ qos_sdmmc: qos@fdf3d800 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf3d800 0x0 0x20>;
-+ };
-+
-+ qos_usb3_1: qos@fdf3e000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf3e000 0x0 0x20>;
-+ };
-+
-+ qos_usb3_0: qos@fdf3e200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf3e200 0x0 0x20>;
-+ };
-+
-+ qos_usb2host_0: qos@fdf3e400 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf3e400 0x0 0x20>;
-+ };
-+
-+ qos_usb2host_1: qos@fdf3e600 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf3e600 0x0 0x20>;
-+ };
-+
-+ qos_fisheye0: qos@fdf40000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf40000 0x0 0x20>;
-+ };
-+
-+ qos_fisheye1: qos@fdf40200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf40200 0x0 0x20>;
-+ };
-+
-+ qos_isp0_mro: qos@fdf40400 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf40400 0x0 0x20>;
-+ };
-+
-+ qos_isp0_mwo: qos@fdf40500 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf40500 0x0 0x20>;
-+ };
-+
-+ qos_vicap_m0: qos@fdf40600 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf40600 0x0 0x20>;
-+ };
-+
-+ qos_vicap_m1: qos@fdf40800 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf40800 0x0 0x20>;
-+ };
-+
-+ qos_isp1_mwo: qos@fdf41000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf41000 0x0 0x20>;
-+ };
-+
-+ qos_isp1_mro: qos@fdf41100 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf41100 0x0 0x20>;
-+ };
-+
-+ qos_rkvenc0_m0ro: qos@fdf60000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf60000 0x0 0x20>;
-+ };
-+
-+ qos_rkvenc0_m1ro: qos@fdf60200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf60200 0x0 0x20>;
-+ };
-+
-+ qos_rkvenc0_m2wo: qos@fdf60400 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf60400 0x0 0x20>;
-+ };
-+
-+ qos_rkvenc1_m0ro: qos@fdf61000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf61000 0x0 0x20>;
-+ };
-+
-+ qos_rkvenc1_m1ro: qos@fdf61200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf61200 0x0 0x20>;
-+ };
-+
-+ qos_rkvenc1_m2wo: qos@fdf61400 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf61400 0x0 0x20>;
-+ };
-+
-+ qos_rkvdec0: qos@fdf62000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf62000 0x0 0x20>;
-+ };
-+
-+ qos_rkvdec1: qos@fdf63000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf63000 0x0 0x20>;
-+ };
-+
-+ qos_av1: qos@fdf64000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf64000 0x0 0x20>;
-+ };
-+
-+ qos_iep: qos@fdf66000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf66000 0x0 0x20>;
-+ };
-+
-+ qos_jpeg_dec: qos@fdf66200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf66200 0x0 0x20>;
-+ };
-+
-+ qos_jpeg_enc0: qos@fdf66400 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf66400 0x0 0x20>;
-+ };
-+
-+ qos_jpeg_enc1: qos@fdf66600 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf66600 0x0 0x20>;
-+ };
-+
-+ qos_jpeg_enc2: qos@fdf66800 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf66800 0x0 0x20>;
-+ };
-+
-+ qos_jpeg_enc3: qos@fdf66a00 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf66a00 0x0 0x20>;
-+ };
-+
-+ qos_rga2_mro: qos@fdf66c00 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf66c00 0x0 0x20>;
-+ };
-+
-+ qos_rga2_mwo: qos@fdf66e00 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf66e00 0x0 0x20>;
-+ };
-+
-+ qos_rga3_0: qos@fdf67000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf67000 0x0 0x20>;
-+ };
-+
-+ qos_vdpu: qos@fdf67200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf67200 0x0 0x20>;
-+ };
-+
-+ qos_npu1: qos@fdf70000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf70000 0x0 0x20>;
-+ };
-+
-+ qos_npu2: qos@fdf71000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf71000 0x0 0x20>;
-+ };
-+
-+ qos_npu0_mwr: qos@fdf72000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf72000 0x0 0x20>;
-+ };
-+
-+ qos_npu0_mro: qos@fdf72200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf72200 0x0 0x20>;
-+ };
-+
-+ qos_mcu_npu: qos@fdf72400 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf72400 0x0 0x20>;
-+ };
-+
-+ qos_hdcp0: qos@fdf80000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf80000 0x0 0x20>;
-+ };
-+
-+ qos_hdcp1: qos@fdf81000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf81000 0x0 0x20>;
-+ };
-+
-+ qos_hdmirx: qos@fdf81200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf81200 0x0 0x20>;
-+ };
-+
-+ qos_vop_m0: qos@fdf82000 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf82000 0x0 0x20>;
-+ };
-+
-+ qos_vop_m1: qos@fdf82200 {
-+ compatible = "rockchip,rk3588-qos", "syscon";
-+ reg = <0x0 0xfdf82200 0x0 0x20>;
-+ };
-+
-+ dfi: dfi@fe060000 {
-+ reg = <0x00 0xfe060000 0x00 0x10000>;
-+ compatible = "rockchip,rk3588-dfi";
-+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
-+ rockchip,pmu = <&pmu1grf>;
-+ };
-+
-+ pcie2x1l1: pcie@fe180000 {
-+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-+ bus-range = <0x30 0x3f>;
-+ clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
-+ <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
-+ <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
-+ clock-names = "aclk_mst", "aclk_slv",
-+ "aclk_dbi", "pclk",
-+ "aux", "pipe";
-+ device_type = "pci";
-+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
-+ <0 0 0 2 &pcie2x1l1_intc 1>,
-+ <0 0 0 3 &pcie2x1l1_intc 2>,
-+ <0 0 0 4 &pcie2x1l1_intc 3>;
-+ linux,pci-domain = <3>;
-+ max-link-speed = <2>;
-+ msi-map = <0x3000 &its0 0x3000 0x1000>;
-+ num-lanes = <1>;
-+ phys = <&combphy2_psu PHY_TYPE_PCIE>;
-+ phy-names = "pcie-phy";
-+ power-domains = <&power RK3588_PD_PCIE>;
-+ ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
-+ <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
-+ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
-+ reg = <0xa 0x40c00000 0x0 0x00400000>,
-+ <0x0 0xfe180000 0x0 0x00010000>,
-+ <0x0 0xf3000000 0x0 0x00100000>;
-+ reg-names = "dbi", "apb", "config";
-+ resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
-+ reset-names = "pwr", "pipe";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ status = "disabled";
-+
-+ pcie2x1l1_intc: legacy-interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
-+ };
-+ };
-+
-+ pcie2x1l2: pcie@fe190000 {
-+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-+ bus-range = <0x40 0x4f>;
-+ clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
-+ <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
-+ <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
-+ clock-names = "aclk_mst", "aclk_slv",
-+ "aclk_dbi", "pclk",
-+ "aux", "pipe";
-+ device_type = "pci";
-+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
-+ <0 0 0 2 &pcie2x1l2_intc 1>,
-+ <0 0 0 3 &pcie2x1l2_intc 2>,
-+ <0 0 0 4 &pcie2x1l2_intc 3>;
-+ linux,pci-domain = <4>;
-+ max-link-speed = <2>;
-+ msi-map = <0x4000 &its0 0x4000 0x1000>;
-+ num-lanes = <1>;
-+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
-+ phy-names = "pcie-phy";
-+ power-domains = <&power RK3588_PD_PCIE>;
-+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
-+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
-+ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
-+ reg = <0xa 0x41000000 0x0 0x00400000>,
-+ <0x0 0xfe190000 0x0 0x00010000>,
-+ <0x0 0xf4000000 0x0 0x00100000>;
-+ reg-names = "dbi", "apb", "config";
-+ resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
-+ reset-names = "pwr", "pipe";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ status = "disabled";
-+
-+ pcie2x1l2_intc: legacy-interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
-+ };
-+ };
-+
-+ gmac1: ethernet@fe1c0000 {
-+ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
-+ reg = <0x0 0xfe1c0000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "macirq", "eth_wake_irq";
-+ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
-+ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
-+ <&cru CLK_GMAC1_PTP_REF>;
-+ clock-names = "stmmaceth", "clk_mac_ref",
-+ "pclk_mac", "aclk_mac",
-+ "ptp_ref";
-+ power-domains = <&power RK3588_PD_GMAC>;
-+ resets = <&cru SRST_A_GMAC1>;
-+ reset-names = "stmmaceth";
-+ rockchip,grf = <&sys_grf>;
-+ rockchip,php-grf = <&php_grf>;
-+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
-+ snps,mixed-burst;
-+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
-+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
-+ snps,tso;
-+ status = "disabled";
-+
-+ mdio1: mdio {
-+ compatible = "snps,dwmac-mdio";
-+ #address-cells = <0x1>;
-+ #size-cells = <0x0>;
-+ };
-+
-+ gmac1_stmmac_axi_setup: stmmac-axi-config {
-+ snps,blen = <0 0 0 0 16 8 4>;
-+ snps,wr_osr_lmt = <4>;
-+ snps,rd_osr_lmt = <8>;
-+ };
-+
-+ gmac1_mtl_rx_setup: rx-queues-config {
-+ snps,rx-queues-to-use = <2>;
-+ queue0 {};
-+ queue1 {};
-+ };
-+
-+ gmac1_mtl_tx_setup: tx-queues-config {
-+ snps,tx-queues-to-use = <2>;
-+ queue0 {};
-+ queue1 {};
-+ };
-+ };
-+
-+ sata0: sata@fe210000 {
-+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
-+ reg = <0 0xfe210000 0 0x1000>;
-+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
-+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
-+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
-+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
-+ ports-implemented = <0x1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ sata-port@0 {
-+ reg = <0>;
-+ hba-port-cap = <HBA_PORT_FBSCP>;
-+ phys = <&combphy0_ps PHY_TYPE_SATA>;
-+ phy-names = "sata-phy";
-+ snps,rx-ts-max = <32>;
-+ snps,tx-ts-max = <32>;
-+ };
-+ };
-+
-+ sata2: sata@fe230000 {
-+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
-+ reg = <0 0xfe230000 0 0x1000>;
-+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
-+ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
-+ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
-+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
-+ ports-implemented = <0x1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ sata-port@0 {
-+ reg = <0>;
-+ hba-port-cap = <HBA_PORT_FBSCP>;
-+ phys = <&combphy2_psu PHY_TYPE_SATA>;
-+ phy-names = "sata-phy";
-+ snps,rx-ts-max = <32>;
-+ snps,tx-ts-max = <32>;
-+ };
-+ };
-+
-+ sfc: spi@fe2b0000 {
-+ compatible = "rockchip,sfc";
-+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
-+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
-+ clock-names = "clk_sfc", "hclk_sfc";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ sdmmc: mmc@fe2c0000 {
-+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
-+ reg = <0x0 0xfe2c0000 0x0 0x4000>;
-+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
-+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-+ fifo-depth = <0x100>;
-+ max-frequency = <200000000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
-+ power-domains = <&power RK3588_PD_SDMMC>;
-+ status = "disabled";
-+ };
-+
-+ sdio: mmc@fe2d0000 {
-+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
-+ reg = <0x00 0xfe2d0000 0x00 0x4000>;
-+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
-+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-+ fifo-depth = <0x100>;
-+ max-frequency = <200000000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdiom1_pins>;
-+ power-domains = <&power RK3588_PD_SDIO>;
-+ status = "disabled";
-+ };
-+
-+ sdhci: mmc@fe2e0000 {
-+ compatible = "rockchip,rk3588-dwcmshc";
-+ reg = <0x0 0xfe2e0000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
-+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
-+ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
-+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
-+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
-+ <&cru TMCLK_EMMC>;
-+ clock-names = "core", "bus", "axi", "block", "timer";
-+ max-frequency = <200000000>;
-+ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
-+ <&emmc_cmd>, <&emmc_data_strobe>;
-+ pinctrl-names = "default";
-+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
-+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
-+ <&cru SRST_T_EMMC>;
-+ reset-names = "core", "bus", "axi", "block", "timer";
-+ status = "disabled";
-+ };
-+
-+ i2s0_8ch: i2s@fe470000 {
-+ compatible = "rockchip,rk3588-i2s-tdm";
-+ reg = <0x0 0xfe470000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
-+ clock-names = "mclk_tx", "mclk_rx", "hclk";
-+ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
-+ dmas = <&dmac0 0>, <&dmac0 1>;
-+ dma-names = "tx", "rx";
-+ power-domains = <&power RK3588_PD_AUDIO>;
-+ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
-+ reset-names = "tx-m", "rx-m";
-+ rockchip,trcm-sync-tx-only;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s0_lrck
-+ &i2s0_sclk
-+ &i2s0_sdi0
-+ &i2s0_sdi1
-+ &i2s0_sdi2
-+ &i2s0_sdi3
-+ &i2s0_sdo0
-+ &i2s0_sdo1
-+ &i2s0_sdo2
-+ &i2s0_sdo3>;
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2s1_8ch: i2s@fe480000 {
-+ compatible = "rockchip,rk3588-i2s-tdm";
-+ reg = <0x0 0xfe480000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
-+ clock-names = "mclk_tx", "mclk_rx", "hclk";
-+ dmas = <&dmac0 2>, <&dmac0 3>;
-+ dma-names = "tx", "rx";
-+ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
-+ reset-names = "tx-m", "rx-m";
-+ rockchip,trcm-sync-tx-only;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s1m0_lrck
-+ &i2s1m0_sclk
-+ &i2s1m0_sdi0
-+ &i2s1m0_sdi1
-+ &i2s1m0_sdi2
-+ &i2s1m0_sdi3
-+ &i2s1m0_sdo0
-+ &i2s1m0_sdo1
-+ &i2s1m0_sdo2
-+ &i2s1m0_sdo3>;
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2s2_2ch: i2s@fe490000 {
-+ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
-+ reg = <0x0 0xfe490000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
-+ clock-names = "i2s_clk", "i2s_hclk";
-+ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>;
-+ dmas = <&dmac1 0>, <&dmac1 1>;
-+ dma-names = "tx", "rx";
-+ power-domains = <&power RK3588_PD_AUDIO>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s2m1_lrck
-+ &i2s2m1_sclk
-+ &i2s2m1_sdi
-+ &i2s2m1_sdo>;
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2s3_2ch: i2s@fe4a0000 {
-+ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
-+ reg = <0x0 0xfe4a0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
-+ clock-names = "i2s_clk", "i2s_hclk";
-+ assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>;
-+ dmas = <&dmac1 2>, <&dmac1 3>;
-+ dma-names = "tx", "rx";
-+ power-domains = <&power RK3588_PD_AUDIO>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s3_lrck
-+ &i2s3_sclk
-+ &i2s3_sdi
-+ &i2s3_sdo>;
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ gic: interrupt-controller@fe600000 {
-+ compatible = "arm,gic-v3";
-+ reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
-+ <0x0 0xfe680000 0 0x100000>; /* GICR */
-+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-controller;
-+ mbi-alias = <0x0 0xfe610000>;
-+ mbi-ranges = <424 56>;
-+ msi-controller;
-+ ranges;
-+ #address-cells = <2>;
-+ #interrupt-cells = <4>;
-+ #size-cells = <2>;
-+
-+ its0: msi-controller@fe640000 {
-+ compatible = "arm,gic-v3-its";
-+ reg = <0x0 0xfe640000 0x0 0x20000>;
-+ msi-controller;
-+ #msi-cells = <1>;
-+ };
-+
-+ its1: msi-controller@fe660000 {
-+ compatible = "arm,gic-v3-its";
-+ reg = <0x0 0xfe660000 0x0 0x20000>;
-+ msi-controller;
-+ #msi-cells = <1>;
-+ };
-+
-+ ppi-partitions {
-+ ppi_partition0: interrupt-partition-0 {
-+ affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
-+ };
-+
-+ ppi_partition1: interrupt-partition-1 {
-+ affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
-+ };
-+ };
-+ };
-+
-+ dmac0: dma-controller@fea10000 {
-+ compatible = "arm,pl330", "arm,primecell";
-+ reg = <0x0 0xfea10000 0x0 0x4000>;
-+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
-+ arm,pl330-periph-burst;
-+ clocks = <&cru ACLK_DMAC0>;
-+ clock-names = "apb_pclk";
-+ #dma-cells = <1>;
-+ };
-+
-+ dmac1: dma-controller@fea30000 {
-+ compatible = "arm,pl330", "arm,primecell";
-+ reg = <0x0 0xfea30000 0x0 0x4000>;
-+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
-+ arm,pl330-periph-burst;
-+ clocks = <&cru ACLK_DMAC1>;
-+ clock-names = "apb_pclk";
-+ #dma-cells = <1>;
-+ };
-+
-+ i2c1: i2c@fea90000 {
-+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-+ reg = <0x0 0xfea90000 0x0 0x1000>;
-+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
-+ clock-names = "i2c", "pclk";
-+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
-+ pinctrl-0 = <&i2c1m0_xfer>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c2: i2c@feaa0000 {
-+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-+ reg = <0x0 0xfeaa0000 0x0 0x1000>;
-+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
-+ clock-names = "i2c", "pclk";
-+ interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
-+ pinctrl-0 = <&i2c2m0_xfer>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c3: i2c@feab0000 {
-+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-+ reg = <0x0 0xfeab0000 0x0 0x1000>;
-+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
-+ clock-names = "i2c", "pclk";
-+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
-+ pinctrl-0 = <&i2c3m0_xfer>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c4: i2c@feac0000 {
-+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-+ reg = <0x0 0xfeac0000 0x0 0x1000>;
-+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
-+ clock-names = "i2c", "pclk";
-+ interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
-+ pinctrl-0 = <&i2c4m0_xfer>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c5: i2c@fead0000 {
-+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-+ reg = <0x0 0xfead0000 0x0 0x1000>;
-+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
-+ clock-names = "i2c", "pclk";
-+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
-+ pinctrl-0 = <&i2c5m0_xfer>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ timer0: timer@feae0000 {
-+ compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
-+ reg = <0x0 0xfeae0000 0x0 0x20>;
-+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
-+ clock-names = "pclk", "timer";
-+ };
-+
-+ wdt: watchdog@feaf0000 {
-+ compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
-+ reg = <0x0 0xfeaf0000 0x0 0x100>;
-+ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
-+ clock-names = "tclk", "pclk";
-+ interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
-+ };
-+
-+ spi0: spi@feb00000 {
-+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-+ reg = <0x0 0xfeb00000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
-+ clock-names = "spiclk", "apb_pclk";
-+ dmas = <&dmac0 14>, <&dmac0 15>;
-+ dma-names = "tx", "rx";
-+ num-cs = <2>;
-+ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ spi1: spi@feb10000 {
-+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-+ reg = <0x0 0xfeb10000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
-+ clock-names = "spiclk", "apb_pclk";
-+ dmas = <&dmac0 16>, <&dmac0 17>;
-+ dma-names = "tx", "rx";
-+ num-cs = <2>;
-+ pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ spi2: spi@feb20000 {
-+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-+ reg = <0x0 0xfeb20000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
-+ clock-names = "spiclk", "apb_pclk";
-+ dmas = <&dmac1 15>, <&dmac1 16>;
-+ dma-names = "tx", "rx";
-+ num-cs = <2>;
-+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ spi3: spi@feb30000 {
-+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-+ reg = <0x0 0xfeb30000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
-+ clock-names = "spiclk", "apb_pclk";
-+ dmas = <&dmac1 17>, <&dmac1 18>;
-+ dma-names = "tx", "rx";
-+ num-cs = <2>;
-+ pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ uart1: serial@feb40000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfeb40000 0x0 0x100>;
-+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac0 8>, <&dmac0 9>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart1m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ status = "disabled";
-+ };
-+
-+ uart2: serial@feb50000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfeb50000 0x0 0x100>;
-+ interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac0 10>, <&dmac0 11>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart2m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ status = "disabled";
-+ };
-+
-+ uart3: serial@feb60000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfeb60000 0x0 0x100>;
-+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac0 12>, <&dmac0 13>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart3m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ status = "disabled";
-+ };
-+
-+ uart4: serial@feb70000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfeb70000 0x0 0x100>;
-+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac1 9>, <&dmac1 10>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart4m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ status = "disabled";
-+ };
-+
-+ uart5: serial@feb80000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfeb80000 0x0 0x100>;
-+ interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac1 11>, <&dmac1 12>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart5m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ status = "disabled";
-+ };
-+
-+ uart6: serial@feb90000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfeb90000 0x0 0x100>;
-+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac1 13>, <&dmac1 14>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart6m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ status = "disabled";
-+ };
-+
-+ uart7: serial@feba0000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfeba0000 0x0 0x100>;
-+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac2 7>, <&dmac2 8>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart7m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ status = "disabled";
-+ };
-+
-+ uart8: serial@febb0000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfebb0000 0x0 0x100>;
-+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac2 9>, <&dmac2 10>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart8m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ status = "disabled";
-+ };
-+
-+ uart9: serial@febc0000 {
-+ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-+ reg = <0x0 0xfebc0000 0x0 0x100>;
-+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
-+ clock-names = "baudclk", "apb_pclk";
-+ dmas = <&dmac2 11>, <&dmac2 12>;
-+ dma-names = "tx", "rx";
-+ pinctrl-0 = <&uart9m1_xfer>;
-+ pinctrl-names = "default";
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ status = "disabled";
-+ };
-+
-+ pwm4: pwm@febd0000 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebd0000 0x0 0x10>;
-+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm4m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm5: pwm@febd0010 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebd0010 0x0 0x10>;
-+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm5m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm6: pwm@febd0020 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebd0020 0x0 0x10>;
-+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm6m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm7: pwm@febd0030 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebd0030 0x0 0x10>;
-+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm7m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm8: pwm@febe0000 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebe0000 0x0 0x10>;
-+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm8m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm9: pwm@febe0010 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebe0010 0x0 0x10>;
-+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm9m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm10: pwm@febe0020 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebe0020 0x0 0x10>;
-+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm10m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm11: pwm@febe0030 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebe0030 0x0 0x10>;
-+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm11m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm12: pwm@febf0000 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebf0000 0x0 0x10>;
-+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm12m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm13: pwm@febf0010 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebf0010 0x0 0x10>;
-+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm13m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm14: pwm@febf0020 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebf0020 0x0 0x10>;
-+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm14m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ pwm15: pwm@febf0030 {
-+ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-+ reg = <0x0 0xfebf0030 0x0 0x10>;
-+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
-+ clock-names = "pwm", "pclk";
-+ pinctrl-0 = <&pwm15m0_pins>;
-+ pinctrl-names = "default";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ tsadc: tsadc@fec00000 {
-+ compatible = "rockchip,rk3588-tsadc";
-+ reg = <0x0 0xfec00000 0x0 0x400>;
-+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
-+ clock-names = "tsadc", "apb_pclk";
-+ assigned-clocks = <&cru CLK_TSADC>;
-+ assigned-clock-rates = <2000000>;
-+ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
-+ reset-names = "tsadc-apb", "tsadc";
-+ rockchip,hw-tshut-temp = <120000>;
-+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
-+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
-+ pinctrl-0 = <&tsadc_gpio_func>;
-+ pinctrl-1 = <&tsadc_shut>;
-+ pinctrl-names = "gpio", "otpout";
-+ #thermal-sensor-cells = <1>;
-+ status = "disabled";
-+ };
-+
-+ saradc: adc@fec10000 {
-+ compatible = "rockchip,rk3588-saradc";
-+ reg = <0x0 0xfec10000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
-+ #io-channel-cells = <1>;
-+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
-+ clock-names = "saradc", "apb_pclk";
-+ resets = <&cru SRST_P_SARADC>;
-+ reset-names = "saradc-apb";
-+ status = "disabled";
-+ };
-+
-+ i2c6: i2c@fec80000 {
-+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-+ reg = <0x0 0xfec80000 0x0 0x1000>;
-+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
-+ clock-names = "i2c", "pclk";
-+ interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
-+ pinctrl-0 = <&i2c6m0_xfer>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c7: i2c@fec90000 {
-+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-+ reg = <0x0 0xfec90000 0x0 0x1000>;
-+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
-+ clock-names = "i2c", "pclk";
-+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
-+ pinctrl-0 = <&i2c7m0_xfer>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c8: i2c@feca0000 {
-+ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-+ reg = <0x0 0xfeca0000 0x0 0x1000>;
-+ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
-+ clock-names = "i2c", "pclk";
-+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
-+ pinctrl-0 = <&i2c8m0_xfer>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ spi4: spi@fecb0000 {
-+ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-+ reg = <0x0 0xfecb0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
-+ clock-names = "spiclk", "apb_pclk";
-+ dmas = <&dmac2 13>, <&dmac2 14>;
-+ dma-names = "tx", "rx";
-+ num-cs = <2>;
-+ pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
-+ pinctrl-names = "default";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ otp: efuse@fecc0000 {
-+ compatible = "rockchip,rk3588-otp";
-+ reg = <0x0 0xfecc0000 0x0 0x400>;
-+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
-+ <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
-+ clock-names = "otp", "apb_pclk", "phy", "arb";
-+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
-+ <&cru SRST_OTPC_ARB>;
-+ reset-names = "otp", "apb", "arb";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ cpu_code: cpu-code@2 {
-+ reg = <0x02 0x2>;
-+ };
-+
-+ otp_id: id@7 {
-+ reg = <0x07 0x10>;
-+ };
-+
-+ cpub0_leakage: cpu-leakage@17 {
-+ reg = <0x17 0x1>;
-+ };
-+
-+ cpub1_leakage: cpu-leakage@18 {
-+ reg = <0x18 0x1>;
-+ };
-+
-+ cpul_leakage: cpu-leakage@19 {
-+ reg = <0x19 0x1>;
-+ };
-+
-+ log_leakage: log-leakage@1a {
-+ reg = <0x1a 0x1>;
-+ };
-+
-+ gpu_leakage: gpu-leakage@1b {
-+ reg = <0x1b 0x1>;
-+ };
-+
-+ otp_cpu_version: cpu-version@1c {
-+ reg = <0x1c 0x1>;
-+ bits = <3 3>;
-+ };
-+
-+ npu_leakage: npu-leakage@28 {
-+ reg = <0x28 0x1>;
-+ };
-+
-+ codec_leakage: codec-leakage@29 {
-+ reg = <0x29 0x1>;
-+ };
-+ };
-+
-+ dmac2: dma-controller@fed10000 {
-+ compatible = "arm,pl330", "arm,primecell";
-+ reg = <0x0 0xfed10000 0x0 0x4000>;
-+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
-+ arm,pl330-periph-burst;
-+ clocks = <&cru ACLK_DMAC2>;
-+ clock-names = "apb_pclk";
-+ #dma-cells = <1>;
-+ };
-+
-+ hdptxphy_hdmi0: phy@fed60000 {
-+ compatible = "rockchip,rk3588-hdptx-phy";
-+ reg = <0x0 0xfed60000 0x0 0x2000>;
-+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
-+ clock-names = "ref", "apb";
-+ #phy-cells = <0>;
-+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
-+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
-+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
-+ <&cru SRST_HDPTX0_LCPLL>;
-+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
-+ "lcpll";
-+ rockchip,grf = <&hdptxphy0_grf>;
-+ status = "disabled";
-+ };
-+
-+ usbdp_phy0: phy@fed80000 {
-+ compatible = "rockchip,rk3588-usbdp-phy";
-+ reg = <0x0 0xfed80000 0x0 0x10000>;
-+ #phy-cells = <1>;
-+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
-+ <&cru CLK_USBDP_PHY0_IMMORTAL>,
-+ <&cru PCLK_USBDPPHY0>,
-+ <&u2phy0>;
-+ clock-names = "refclk", "immortal", "pclk", "utmi";
-+ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
-+ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
-+ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
-+ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
-+ <&cru SRST_P_USBDPPHY0>;
-+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
-+ rockchip,u2phy-grf = <&usb2phy0_grf>;
-+ rockchip,usb-grf = <&usb_grf>;
-+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
-+ rockchip,vo-grf = <&vo0_grf>;
-+ status = "disabled";
-+ };
-+
-+ combphy0_ps: phy@fee00000 {
-+ compatible = "rockchip,rk3588-naneng-combphy";
-+ reg = <0x0 0xfee00000 0x0 0x100>;
-+ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
-+ <&cru PCLK_PHP_ROOT>;
-+ clock-names = "ref", "apb", "pipe";
-+ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
-+ assigned-clock-rates = <100000000>;
-+ #phy-cells = <1>;
-+ resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
-+ reset-names = "phy", "apb";
-+ rockchip,pipe-grf = <&php_grf>;
-+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
-+ status = "disabled";
-+ };
-+
-+ combphy2_psu: phy@fee20000 {
-+ compatible = "rockchip,rk3588-naneng-combphy";
-+ reg = <0x0 0xfee20000 0x0 0x100>;
-+ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
-+ <&cru PCLK_PHP_ROOT>;
-+ clock-names = "ref", "apb", "pipe";
-+ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
-+ assigned-clock-rates = <100000000>;
-+ #phy-cells = <1>;
-+ resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
-+ reset-names = "phy", "apb";
-+ rockchip,pipe-grf = <&php_grf>;
-+ rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
-+ status = "disabled";
-+ };
-+
-+ system_sram2: sram@ff001000 {
-+ compatible = "mmio-sram";
-+ reg = <0x0 0xff001000 0x0 0xef000>;
-+ ranges = <0x0 0x0 0xff001000 0xef000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ };
-+
-+ pinctrl: pinctrl {
-+ compatible = "rockchip,rk3588-pinctrl";
-+ ranges;
-+ rockchip,grf = <&ioc>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ gpio0: gpio@fd8a0000 {
-+ compatible = "rockchip,gpio-bank";
-+ reg = <0x0 0xfd8a0000 0x0 0x100>;
-+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
-+ gpio-controller;
-+ gpio-ranges = <&pinctrl 0 0 32>;
-+ interrupt-controller;
-+ #gpio-cells = <2>;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ gpio1: gpio@fec20000 {
-+ compatible = "rockchip,gpio-bank";
-+ reg = <0x0 0xfec20000 0x0 0x100>;
-+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
-+ gpio-controller;
-+ gpio-ranges = <&pinctrl 0 32 32>;
-+ interrupt-controller;
-+ #gpio-cells = <2>;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ gpio2: gpio@fec30000 {
-+ compatible = "rockchip,gpio-bank";
-+ reg = <0x0 0xfec30000 0x0 0x100>;
-+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
-+ gpio-controller;
-+ gpio-ranges = <&pinctrl 0 64 32>;
-+ interrupt-controller;
-+ #gpio-cells = <2>;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ gpio3: gpio@fec40000 {
-+ compatible = "rockchip,gpio-bank";
-+ reg = <0x0 0xfec40000 0x0 0x100>;
-+ interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
-+ gpio-controller;
-+ gpio-ranges = <&pinctrl 0 96 32>;
-+ interrupt-controller;
-+ #gpio-cells = <2>;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ gpio4: gpio@fec50000 {
-+ compatible = "rockchip,gpio-bank";
-+ reg = <0x0 0xfec50000 0x0 0x100>;
-+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
-+ gpio-controller;
-+ gpio-ranges = <&pinctrl 0 128 32>;
-+ interrupt-controller;
-+ #gpio-cells = <2>;
-+ #interrupt-cells = <2>;
-+ };
-+ };
-+};
-+
-+#include "rk3588-base-pinctrl.dtsi"
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
-@@ -0,0 +1,413 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+ */
-+
-+#include "rk3588-base.dtsi"
-+#include "rk3588-extra-pinctrl.dtsi"
-+
-+/ {
-+ usb_host1_xhci: usb@fc400000 {
-+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
-+ reg = <0x0 0xfc400000 0x0 0x400000>;
-+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
-+ <&cru ACLK_USB3OTG1>;
-+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
-+ dr_mode = "otg";
-+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ phy_type = "utmi_wide";
-+ power-domains = <&power RK3588_PD_USB>;
-+ resets = <&cru SRST_A_USB3OTG1>;
-+ snps,dis_enblslpm_quirk;
-+ snps,dis-u2-freeclk-exists-quirk;
-+ snps,dis-del-phy-power-chg-quirk;
-+ snps,dis-tx-ipgap-linecheck-quirk;
-+ status = "disabled";
-+ };
-+
-+ pcie30_phy_grf: syscon@fd5b8000 {
-+ compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
-+ reg = <0x0 0xfd5b8000 0x0 0x10000>;
-+ };
-+
-+ pipe_phy1_grf: syscon@fd5c0000 {
-+ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
-+ reg = <0x0 0xfd5c0000 0x0 0x100>;
-+ };
-+
-+ usbdpphy1_grf: syscon@fd5cc000 {
-+ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
-+ reg = <0x0 0xfd5cc000 0x0 0x4000>;
-+ };
-+
-+ usb2phy1_grf: syscon@fd5d4000 {
-+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-+ reg = <0x0 0xfd5d4000 0x0 0x4000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ u2phy1: usb2phy@4000 {
-+ compatible = "rockchip,rk3588-usb2phy";
-+ reg = <0x4000 0x10>;
-+ #clock-cells = <0>;
-+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-+ clock-names = "phyclk";
-+ clock-output-names = "usb480m_phy1";
-+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
-+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
-+ reset-names = "phy", "apb";
-+ status = "disabled";
-+
-+ u2phy1_otg: otg-port {
-+ #phy-cells = <0>;
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ i2s8_8ch: i2s@fddc8000 {
-+ compatible = "rockchip,rk3588-i2s-tdm";
-+ reg = <0x0 0xfddc8000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
-+ clock-names = "mclk_tx", "mclk_rx", "hclk";
-+ assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>;
-+ dmas = <&dmac2 22>;
-+ dma-names = "tx";
-+ power-domains = <&power RK3588_PD_VO0>;
-+ resets = <&cru SRST_M_I2S8_8CH_TX>;
-+ reset-names = "tx-m";
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2s6_8ch: i2s@fddf4000 {
-+ compatible = "rockchip,rk3588-i2s-tdm";
-+ reg = <0x0 0xfddf4000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
-+ clock-names = "mclk_tx", "mclk_rx", "hclk";
-+ assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>;
-+ dmas = <&dmac2 4>;
-+ dma-names = "tx";
-+ power-domains = <&power RK3588_PD_VO1>;
-+ resets = <&cru SRST_M_I2S6_8CH_TX>;
-+ reset-names = "tx-m";
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2s7_8ch: i2s@fddf8000 {
-+ compatible = "rockchip,rk3588-i2s-tdm";
-+ reg = <0x0 0xfddf8000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
-+ clock-names = "mclk_tx", "mclk_rx", "hclk";
-+ assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>;
-+ dmas = <&dmac2 21>;
-+ dma-names = "rx";
-+ power-domains = <&power RK3588_PD_VO1>;
-+ resets = <&cru SRST_M_I2S7_8CH_RX>;
-+ reset-names = "rx-m";
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2s10_8ch: i2s@fde00000 {
-+ compatible = "rockchip,rk3588-i2s-tdm";
-+ reg = <0x0 0xfde00000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
-+ clock-names = "mclk_tx", "mclk_rx", "hclk";
-+ assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
-+ assigned-clock-parents = <&cru PLL_AUPLL>;
-+ dmas = <&dmac2 24>;
-+ dma-names = "rx";
-+ power-domains = <&power RK3588_PD_VO1>;
-+ resets = <&cru SRST_M_I2S10_8CH_RX>;
-+ reset-names = "rx-m";
-+ #sound-dai-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ pcie3x4: pcie@fe150000 {
-+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ bus-range = <0x00 0x0f>;
-+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
-+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
-+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
-+ clock-names = "aclk_mst", "aclk_slv",
-+ "aclk_dbi", "pclk",
-+ "aux", "pipe";
-+ device_type = "pci";
-+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
-+ <0 0 0 2 &pcie3x4_intc 1>,
-+ <0 0 0 3 &pcie3x4_intc 2>,
-+ <0 0 0 4 &pcie3x4_intc 3>;
-+ linux,pci-domain = <0>;
-+ max-link-speed = <3>;
-+ msi-map = <0x0000 &its1 0x0000 0x1000>;
-+ num-lanes = <4>;
-+ phys = <&pcie30phy>;
-+ phy-names = "pcie-phy";
-+ power-domains = <&power RK3588_PD_PCIE>;
-+ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
-+ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
-+ <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
-+ reg = <0xa 0x40000000 0x0 0x00400000>,
-+ <0x0 0xfe150000 0x0 0x00010000>,
-+ <0x0 0xf0000000 0x0 0x00100000>;
-+ reg-names = "dbi", "apb", "config";
-+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
-+ reset-names = "pwr", "pipe";
-+ status = "disabled";
-+
-+ pcie3x4_intc: legacy-interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
-+ };
-+ };
-+
-+ pcie3x2: pcie@fe160000 {
-+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ bus-range = <0x10 0x1f>;
-+ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
-+ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
-+ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
-+ clock-names = "aclk_mst", "aclk_slv",
-+ "aclk_dbi", "pclk",
-+ "aux", "pipe";
-+ device_type = "pci";
-+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
-+ <0 0 0 2 &pcie3x2_intc 1>,
-+ <0 0 0 3 &pcie3x2_intc 2>,
-+ <0 0 0 4 &pcie3x2_intc 3>;
-+ linux,pci-domain = <1>;
-+ max-link-speed = <3>;
-+ msi-map = <0x1000 &its1 0x1000 0x1000>;
-+ num-lanes = <2>;
-+ phys = <&pcie30phy>;
-+ phy-names = "pcie-phy";
-+ power-domains = <&power RK3588_PD_PCIE>;
-+ ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
-+ <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
-+ <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
-+ reg = <0xa 0x40400000 0x0 0x00400000>,
-+ <0x0 0xfe160000 0x0 0x00010000>,
-+ <0x0 0xf1000000 0x0 0x00100000>;
-+ reg-names = "dbi", "apb", "config";
-+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
-+ reset-names = "pwr", "pipe";
-+ status = "disabled";
-+
-+ pcie3x2_intc: legacy-interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
-+ };
-+ };
-+
-+ pcie2x1l0: pcie@fe170000 {
-+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-+ bus-range = <0x20 0x2f>;
-+ clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
-+ <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
-+ <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
-+ clock-names = "aclk_mst", "aclk_slv",
-+ "aclk_dbi", "pclk",
-+ "aux", "pipe";
-+ device_type = "pci";
-+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
-+ <0 0 0 2 &pcie2x1l0_intc 1>,
-+ <0 0 0 3 &pcie2x1l0_intc 2>,
-+ <0 0 0 4 &pcie2x1l0_intc 3>;
-+ linux,pci-domain = <2>;
-+ max-link-speed = <2>;
-+ msi-map = <0x2000 &its0 0x2000 0x1000>;
-+ num-lanes = <1>;
-+ phys = <&combphy1_ps PHY_TYPE_PCIE>;
-+ phy-names = "pcie-phy";
-+ power-domains = <&power RK3588_PD_PCIE>;
-+ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
-+ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
-+ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
-+ reg = <0xa 0x40800000 0x0 0x00400000>,
-+ <0x0 0xfe170000 0x0 0x00010000>,
-+ <0x0 0xf2000000 0x0 0x00100000>;
-+ reg-names = "dbi", "apb", "config";
-+ resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
-+ reset-names = "pwr", "pipe";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ status = "disabled";
-+
-+ pcie2x1l0_intc: legacy-interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
-+ };
-+ };
-+
-+ gmac0: ethernet@fe1b0000 {
-+ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
-+ reg = <0x0 0xfe1b0000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
-+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
-+ interrupt-names = "macirq", "eth_wake_irq";
-+ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
-+ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
-+ <&cru CLK_GMAC0_PTP_REF>;
-+ clock-names = "stmmaceth", "clk_mac_ref",
-+ "pclk_mac", "aclk_mac",
-+ "ptp_ref";
-+ power-domains = <&power RK3588_PD_GMAC>;
-+ resets = <&cru SRST_A_GMAC0>;
-+ reset-names = "stmmaceth";
-+ rockchip,grf = <&sys_grf>;
-+ rockchip,php-grf = <&php_grf>;
-+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
-+ snps,mixed-burst;
-+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
-+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
-+ snps,tso;
-+ status = "disabled";
-+
-+ mdio0: mdio {
-+ compatible = "snps,dwmac-mdio";
-+ #address-cells = <0x1>;
-+ #size-cells = <0x0>;
-+ };
-+
-+ gmac0_stmmac_axi_setup: stmmac-axi-config {
-+ snps,blen = <0 0 0 0 16 8 4>;
-+ snps,wr_osr_lmt = <4>;
-+ snps,rd_osr_lmt = <8>;
-+ };
-+
-+ gmac0_mtl_rx_setup: rx-queues-config {
-+ snps,rx-queues-to-use = <2>;
-+ queue0 {};
-+ queue1 {};
-+ };
-+
-+ gmac0_mtl_tx_setup: tx-queues-config {
-+ snps,tx-queues-to-use = <2>;
-+ queue0 {};
-+ queue1 {};
-+ };
-+ };
-+
-+ sata1: sata@fe220000 {
-+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
-+ reg = <0 0xfe220000 0 0x1000>;
-+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
-+ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
-+ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
-+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
-+ ports-implemented = <0x1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ sata-port@0 {
-+ reg = <0>;
-+ hba-port-cap = <HBA_PORT_FBSCP>;
-+ phys = <&combphy1_ps PHY_TYPE_SATA>;
-+ phy-names = "sata-phy";
-+ snps,rx-ts-max = <32>;
-+ snps,tx-ts-max = <32>;
-+ };
-+ };
-+
-+ usbdp_phy1: phy@fed90000 {
-+ compatible = "rockchip,rk3588-usbdp-phy";
-+ reg = <0x0 0xfed90000 0x0 0x10000>;
-+ #phy-cells = <1>;
-+ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
-+ <&cru CLK_USBDP_PHY1_IMMORTAL>,
-+ <&cru PCLK_USBDPPHY1>,
-+ <&u2phy1>;
-+ clock-names = "refclk", "immortal", "pclk", "utmi";
-+ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
-+ <&cru SRST_USBDP_COMBO_PHY1_CMN>,
-+ <&cru SRST_USBDP_COMBO_PHY1_LANE>,
-+ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
-+ <&cru SRST_P_USBDPPHY1>;
-+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
-+ rockchip,u2phy-grf = <&usb2phy1_grf>;
-+ rockchip,usb-grf = <&usb_grf>;
-+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
-+ rockchip,vo-grf = <&vo0_grf>;
-+ status = "disabled";
-+ };
-+
-+ combphy1_ps: phy@fee10000 {
-+ compatible = "rockchip,rk3588-naneng-combphy";
-+ reg = <0x0 0xfee10000 0x0 0x100>;
-+ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
-+ <&cru PCLK_PHP_ROOT>;
-+ clock-names = "ref", "apb", "pipe";
-+ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
-+ assigned-clock-rates = <100000000>;
-+ #phy-cells = <1>;
-+ resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
-+ reset-names = "phy", "apb";
-+ rockchip,pipe-grf = <&php_grf>;
-+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
-+ status = "disabled";
-+ };
-+
-+ pcie30phy: phy@fee80000 {
-+ compatible = "rockchip,rk3588-pcie3-phy";
-+ reg = <0x0 0xfee80000 0x0 0x20000>;
-+ #phy-cells = <0>;
-+ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
-+ clock-names = "pclk";
-+ resets = <&cru SRST_PCIE30_PHY>;
-+ reset-names = "phy";
-+ rockchip,pipe-grf = <&php_grf>;
-+ rockchip,phy-grf = <&pcie30_phy_grf>;
-+ status = "disabled";
-+ };
-+};
---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
-@@ -1,413 +1,7 @@
- // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
-+ *
- */
-
--#include "rk3588s.dtsi"
--#include "rk3588-pinctrl.dtsi"
--
--/ {
-- usb_host1_xhci: usb@fc400000 {
-- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
-- reg = <0x0 0xfc400000 0x0 0x400000>;
-- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
-- <&cru ACLK_USB3OTG1>;
-- clock-names = "ref_clk", "suspend_clk", "bus_clk";
-- dr_mode = "otg";
-- phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
-- phy-names = "usb2-phy", "usb3-phy";
-- phy_type = "utmi_wide";
-- power-domains = <&power RK3588_PD_USB>;
-- resets = <&cru SRST_A_USB3OTG1>;
-- snps,dis_enblslpm_quirk;
-- snps,dis-u2-freeclk-exists-quirk;
-- snps,dis-del-phy-power-chg-quirk;
-- snps,dis-tx-ipgap-linecheck-quirk;
-- status = "disabled";
-- };
--
-- pcie30_phy_grf: syscon@fd5b8000 {
-- compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
-- reg = <0x0 0xfd5b8000 0x0 0x10000>;
-- };
--
-- pipe_phy1_grf: syscon@fd5c0000 {
-- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
-- reg = <0x0 0xfd5c0000 0x0 0x100>;
-- };
--
-- usbdpphy1_grf: syscon@fd5cc000 {
-- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
-- reg = <0x0 0xfd5cc000 0x0 0x4000>;
-- };
--
-- usb2phy1_grf: syscon@fd5d4000 {
-- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-- reg = <0x0 0xfd5d4000 0x0 0x4000>;
-- #address-cells = <1>;
-- #size-cells = <1>;
--
-- u2phy1: usb2phy@4000 {
-- compatible = "rockchip,rk3588-usb2phy";
-- reg = <0x4000 0x10>;
-- #clock-cells = <0>;
-- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-- clock-names = "phyclk";
-- clock-output-names = "usb480m_phy1";
-- interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
-- resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
-- reset-names = "phy", "apb";
-- status = "disabled";
--
-- u2phy1_otg: otg-port {
-- #phy-cells = <0>;
-- status = "disabled";
-- };
-- };
-- };
--
-- i2s8_8ch: i2s@fddc8000 {
-- compatible = "rockchip,rk3588-i2s-tdm";
-- reg = <0x0 0xfddc8000 0x0 0x1000>;
-- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
-- clock-names = "mclk_tx", "mclk_rx", "hclk";
-- assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>;
-- dmas = <&dmac2 22>;
-- dma-names = "tx";
-- power-domains = <&power RK3588_PD_VO0>;
-- resets = <&cru SRST_M_I2S8_8CH_TX>;
-- reset-names = "tx-m";
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- i2s6_8ch: i2s@fddf4000 {
-- compatible = "rockchip,rk3588-i2s-tdm";
-- reg = <0x0 0xfddf4000 0x0 0x1000>;
-- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
-- clock-names = "mclk_tx", "mclk_rx", "hclk";
-- assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>;
-- dmas = <&dmac2 4>;
-- dma-names = "tx";
-- power-domains = <&power RK3588_PD_VO1>;
-- resets = <&cru SRST_M_I2S6_8CH_TX>;
-- reset-names = "tx-m";
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- i2s7_8ch: i2s@fddf8000 {
-- compatible = "rockchip,rk3588-i2s-tdm";
-- reg = <0x0 0xfddf8000 0x0 0x1000>;
-- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
-- clock-names = "mclk_tx", "mclk_rx", "hclk";
-- assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>;
-- dmas = <&dmac2 21>;
-- dma-names = "rx";
-- power-domains = <&power RK3588_PD_VO1>;
-- resets = <&cru SRST_M_I2S7_8CH_RX>;
-- reset-names = "rx-m";
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- i2s10_8ch: i2s@fde00000 {
-- compatible = "rockchip,rk3588-i2s-tdm";
-- reg = <0x0 0xfde00000 0x0 0x1000>;
-- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
-- clock-names = "mclk_tx", "mclk_rx", "hclk";
-- assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>;
-- dmas = <&dmac2 24>;
-- dma-names = "rx";
-- power-domains = <&power RK3588_PD_VO1>;
-- resets = <&cru SRST_M_I2S10_8CH_RX>;
-- reset-names = "rx-m";
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- pcie3x4: pcie@fe150000 {
-- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-- #address-cells = <3>;
-- #size-cells = <2>;
-- bus-range = <0x00 0x0f>;
-- clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
-- <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
-- <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
-- clock-names = "aclk_mst", "aclk_slv",
-- "aclk_dbi", "pclk",
-- "aux", "pipe";
-- device_type = "pci";
-- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-- #interrupt-cells = <1>;
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
-- <0 0 0 2 &pcie3x4_intc 1>,
-- <0 0 0 3 &pcie3x4_intc 2>,
-- <0 0 0 4 &pcie3x4_intc 3>;
-- linux,pci-domain = <0>;
-- max-link-speed = <3>;
-- msi-map = <0x0000 &its1 0x0000 0x1000>;
-- num-lanes = <4>;
-- phys = <&pcie30phy>;
-- phy-names = "pcie-phy";
-- power-domains = <&power RK3588_PD_PCIE>;
-- ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
-- <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
-- <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
-- reg = <0xa 0x40000000 0x0 0x00400000>,
-- <0x0 0xfe150000 0x0 0x00010000>,
-- <0x0 0xf0000000 0x0 0x00100000>;
-- reg-names = "dbi", "apb", "config";
-- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
-- reset-names = "pwr", "pipe";
-- status = "disabled";
--
-- pcie3x4_intc: legacy-interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- interrupt-parent = <&gic>;
-- interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
-- };
-- };
--
-- pcie3x2: pcie@fe160000 {
-- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-- #address-cells = <3>;
-- #size-cells = <2>;
-- bus-range = <0x10 0x1f>;
-- clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
-- <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
-- <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
-- clock-names = "aclk_mst", "aclk_slv",
-- "aclk_dbi", "pclk",
-- "aux", "pipe";
-- device_type = "pci";
-- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-- #interrupt-cells = <1>;
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
-- <0 0 0 2 &pcie3x2_intc 1>,
-- <0 0 0 3 &pcie3x2_intc 2>,
-- <0 0 0 4 &pcie3x2_intc 3>;
-- linux,pci-domain = <1>;
-- max-link-speed = <3>;
-- msi-map = <0x1000 &its1 0x1000 0x1000>;
-- num-lanes = <2>;
-- phys = <&pcie30phy>;
-- phy-names = "pcie-phy";
-- power-domains = <&power RK3588_PD_PCIE>;
-- ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
-- <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
-- <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
-- reg = <0xa 0x40400000 0x0 0x00400000>,
-- <0x0 0xfe160000 0x0 0x00010000>,
-- <0x0 0xf1000000 0x0 0x00100000>;
-- reg-names = "dbi", "apb", "config";
-- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
-- reset-names = "pwr", "pipe";
-- status = "disabled";
--
-- pcie3x2_intc: legacy-interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- interrupt-parent = <&gic>;
-- interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
-- };
-- };
--
-- pcie2x1l0: pcie@fe170000 {
-- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-- bus-range = <0x20 0x2f>;
-- clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
-- <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
-- <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
-- clock-names = "aclk_mst", "aclk_slv",
-- "aclk_dbi", "pclk",
-- "aux", "pipe";
-- device_type = "pci";
-- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-- #interrupt-cells = <1>;
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
-- <0 0 0 2 &pcie2x1l0_intc 1>,
-- <0 0 0 3 &pcie2x1l0_intc 2>,
-- <0 0 0 4 &pcie2x1l0_intc 3>;
-- linux,pci-domain = <2>;
-- max-link-speed = <2>;
-- msi-map = <0x2000 &its0 0x2000 0x1000>;
-- num-lanes = <1>;
-- phys = <&combphy1_ps PHY_TYPE_PCIE>;
-- phy-names = "pcie-phy";
-- power-domains = <&power RK3588_PD_PCIE>;
-- ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
-- <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
-- <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
-- reg = <0xa 0x40800000 0x0 0x00400000>,
-- <0x0 0xfe170000 0x0 0x00010000>,
-- <0x0 0xf2000000 0x0 0x00100000>;
-- reg-names = "dbi", "apb", "config";
-- resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
-- reset-names = "pwr", "pipe";
-- #address-cells = <3>;
-- #size-cells = <2>;
-- status = "disabled";
--
-- pcie2x1l0_intc: legacy-interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- interrupt-parent = <&gic>;
-- interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
-- };
-- };
--
-- gmac0: ethernet@fe1b0000 {
-- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
-- reg = <0x0 0xfe1b0000 0x0 0x10000>;
-- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "macirq", "eth_wake_irq";
-- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
-- <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
-- <&cru CLK_GMAC0_PTP_REF>;
-- clock-names = "stmmaceth", "clk_mac_ref",
-- "pclk_mac", "aclk_mac",
-- "ptp_ref";
-- power-domains = <&power RK3588_PD_GMAC>;
-- resets = <&cru SRST_A_GMAC0>;
-- reset-names = "stmmaceth";
-- rockchip,grf = <&sys_grf>;
-- rockchip,php-grf = <&php_grf>;
-- snps,axi-config = <&gmac0_stmmac_axi_setup>;
-- snps,mixed-burst;
-- snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
-- snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
-- snps,tso;
-- status = "disabled";
--
-- mdio0: mdio {
-- compatible = "snps,dwmac-mdio";
-- #address-cells = <0x1>;
-- #size-cells = <0x0>;
-- };
--
-- gmac0_stmmac_axi_setup: stmmac-axi-config {
-- snps,blen = <0 0 0 0 16 8 4>;
-- snps,wr_osr_lmt = <4>;
-- snps,rd_osr_lmt = <8>;
-- };
--
-- gmac0_mtl_rx_setup: rx-queues-config {
-- snps,rx-queues-to-use = <2>;
-- queue0 {};
-- queue1 {};
-- };
--
-- gmac0_mtl_tx_setup: tx-queues-config {
-- snps,tx-queues-to-use = <2>;
-- queue0 {};
-- queue1 {};
-- };
-- };
--
-- sata1: sata@fe220000 {
-- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
-- reg = <0 0xfe220000 0 0x1000>;
-- interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
-- <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
-- <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
-- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
-- ports-implemented = <0x1>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
--
-- sata-port@0 {
-- reg = <0>;
-- hba-port-cap = <HBA_PORT_FBSCP>;
-- phys = <&combphy1_ps PHY_TYPE_SATA>;
-- phy-names = "sata-phy";
-- snps,rx-ts-max = <32>;
-- snps,tx-ts-max = <32>;
-- };
-- };
--
-- usbdp_phy1: phy@fed90000 {
-- compatible = "rockchip,rk3588-usbdp-phy";
-- reg = <0x0 0xfed90000 0x0 0x10000>;
-- #phy-cells = <1>;
-- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
-- <&cru CLK_USBDP_PHY1_IMMORTAL>,
-- <&cru PCLK_USBDPPHY1>,
-- <&u2phy1>;
-- clock-names = "refclk", "immortal", "pclk", "utmi";
-- resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
-- <&cru SRST_USBDP_COMBO_PHY1_CMN>,
-- <&cru SRST_USBDP_COMBO_PHY1_LANE>,
-- <&cru SRST_USBDP_COMBO_PHY1_PCS>,
-- <&cru SRST_P_USBDPPHY1>;
-- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
-- rockchip,u2phy-grf = <&usb2phy1_grf>;
-- rockchip,usb-grf = <&usb_grf>;
-- rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
-- rockchip,vo-grf = <&vo0_grf>;
-- status = "disabled";
-- };
--
-- combphy1_ps: phy@fee10000 {
-- compatible = "rockchip,rk3588-naneng-combphy";
-- reg = <0x0 0xfee10000 0x0 0x100>;
-- clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
-- <&cru PCLK_PHP_ROOT>;
-- clock-names = "ref", "apb", "pipe";
-- assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
-- assigned-clock-rates = <100000000>;
-- #phy-cells = <1>;
-- resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
-- reset-names = "phy", "apb";
-- rockchip,pipe-grf = <&php_grf>;
-- rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
-- status = "disabled";
-- };
--
-- pcie30phy: phy@fee80000 {
-- compatible = "rockchip,rk3588-pcie3-phy";
-- reg = <0x0 0xfee80000 0x0 0x20000>;
-- #phy-cells = <0>;
-- clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
-- clock-names = "pclk";
-- resets = <&cru SRST_PCIE30_PHY>;
-- reset-names = "phy";
-- rockchip,pipe-grf = <&php_grf>;
-- rockchip,phy-grf = <&pcie30_phy_grf>;
-- status = "disabled";
-- };
--};
-+#include "rk3588-extra.dtsi"
---- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
-@@ -4,4 +4,4 @@
- *
- */
-
--#include "rk3588.dtsi"
-+#include "rk3588-extra.dtsi"
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1,2670 +1,7 @@
- // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
-+ *
- */
-
--#include <dt-bindings/clock/rockchip,rk3588-cru.h>
--#include <dt-bindings/interrupt-controller/arm-gic.h>
--#include <dt-bindings/interrupt-controller/irq.h>
--#include <dt-bindings/power/rk3588-power.h>
--#include <dt-bindings/reset/rockchip,rk3588-cru.h>
--#include <dt-bindings/phy/phy.h>
--#include <dt-bindings/ata/ahci.h>
--
--/ {
-- compatible = "rockchip,rk3588";
--
-- interrupt-parent = <&gic>;
-- #address-cells = <2>;
-- #size-cells = <2>;
--
-- aliases {
-- gpio0 = &gpio0;
-- gpio1 = &gpio1;
-- gpio2 = &gpio2;
-- gpio3 = &gpio3;
-- gpio4 = &gpio4;
-- i2c0 = &i2c0;
-- i2c1 = &i2c1;
-- i2c2 = &i2c2;
-- i2c3 = &i2c3;
-- i2c4 = &i2c4;
-- i2c5 = &i2c5;
-- i2c6 = &i2c6;
-- i2c7 = &i2c7;
-- i2c8 = &i2c8;
-- serial0 = &uart0;
-- serial1 = &uart1;
-- serial2 = &uart2;
-- serial3 = &uart3;
-- serial4 = &uart4;
-- serial5 = &uart5;
-- serial6 = &uart6;
-- serial7 = &uart7;
-- serial8 = &uart8;
-- serial9 = &uart9;
-- spi0 = &spi0;
-- spi1 = &spi1;
-- spi2 = &spi2;
-- spi3 = &spi3;
-- spi4 = &spi4;
-- };
--
-- cpus {
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- cpu-map {
-- cluster0 {
-- core0 {
-- cpu = <&cpu_l0>;
-- };
-- core1 {
-- cpu = <&cpu_l1>;
-- };
-- core2 {
-- cpu = <&cpu_l2>;
-- };
-- core3 {
-- cpu = <&cpu_l3>;
-- };
-- };
-- cluster1 {
-- core0 {
-- cpu = <&cpu_b0>;
-- };
-- core1 {
-- cpu = <&cpu_b1>;
-- };
-- };
-- cluster2 {
-- core0 {
-- cpu = <&cpu_b2>;
-- };
-- core1 {
-- cpu = <&cpu_b3>;
-- };
-- };
-- };
--
-- cpu_l0: cpu@0 {
-- device_type = "cpu";
-- compatible = "arm,cortex-a55";
-- reg = <0x0>;
-- enable-method = "psci";
-- capacity-dmips-mhz = <530>;
-- clocks = <&scmi_clk SCMI_CLK_CPUL>;
-- assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
-- assigned-clock-rates = <816000000>;
-- cpu-idle-states = <&CPU_SLEEP>;
-- i-cache-size = <32768>;
-- i-cache-line-size = <64>;
-- i-cache-sets = <128>;
-- d-cache-size = <32768>;
-- d-cache-line-size = <64>;
-- d-cache-sets = <128>;
-- next-level-cache = <&l2_cache_l0>;
-- dynamic-power-coefficient = <228>;
-- #cooling-cells = <2>;
-- };
--
-- cpu_l1: cpu@100 {
-- device_type = "cpu";
-- compatible = "arm,cortex-a55";
-- reg = <0x100>;
-- enable-method = "psci";
-- capacity-dmips-mhz = <530>;
-- clocks = <&scmi_clk SCMI_CLK_CPUL>;
-- cpu-idle-states = <&CPU_SLEEP>;
-- i-cache-size = <32768>;
-- i-cache-line-size = <64>;
-- i-cache-sets = <128>;
-- d-cache-size = <32768>;
-- d-cache-line-size = <64>;
-- d-cache-sets = <128>;
-- next-level-cache = <&l2_cache_l1>;
-- dynamic-power-coefficient = <228>;
-- #cooling-cells = <2>;
-- };
--
-- cpu_l2: cpu@200 {
-- device_type = "cpu";
-- compatible = "arm,cortex-a55";
-- reg = <0x200>;
-- enable-method = "psci";
-- capacity-dmips-mhz = <530>;
-- clocks = <&scmi_clk SCMI_CLK_CPUL>;
-- cpu-idle-states = <&CPU_SLEEP>;
-- i-cache-size = <32768>;
-- i-cache-line-size = <64>;
-- i-cache-sets = <128>;
-- d-cache-size = <32768>;
-- d-cache-line-size = <64>;
-- d-cache-sets = <128>;
-- next-level-cache = <&l2_cache_l2>;
-- dynamic-power-coefficient = <228>;
-- #cooling-cells = <2>;
-- };
--
-- cpu_l3: cpu@300 {
-- device_type = "cpu";
-- compatible = "arm,cortex-a55";
-- reg = <0x300>;
-- enable-method = "psci";
-- capacity-dmips-mhz = <530>;
-- clocks = <&scmi_clk SCMI_CLK_CPUL>;
-- cpu-idle-states = <&CPU_SLEEP>;
-- i-cache-size = <32768>;
-- i-cache-line-size = <64>;
-- i-cache-sets = <128>;
-- d-cache-size = <32768>;
-- d-cache-line-size = <64>;
-- d-cache-sets = <128>;
-- next-level-cache = <&l2_cache_l3>;
-- dynamic-power-coefficient = <228>;
-- #cooling-cells = <2>;
-- };
--
-- cpu_b0: cpu@400 {
-- device_type = "cpu";
-- compatible = "arm,cortex-a76";
-- reg = <0x400>;
-- enable-method = "psci";
-- capacity-dmips-mhz = <1024>;
-- clocks = <&scmi_clk SCMI_CLK_CPUB01>;
-- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
-- assigned-clock-rates = <816000000>;
-- cpu-idle-states = <&CPU_SLEEP>;
-- i-cache-size = <65536>;
-- i-cache-line-size = <64>;
-- i-cache-sets = <256>;
-- d-cache-size = <65536>;
-- d-cache-line-size = <64>;
-- d-cache-sets = <256>;
-- next-level-cache = <&l2_cache_b0>;
-- dynamic-power-coefficient = <416>;
-- #cooling-cells = <2>;
-- };
--
-- cpu_b1: cpu@500 {
-- device_type = "cpu";
-- compatible = "arm,cortex-a76";
-- reg = <0x500>;
-- enable-method = "psci";
-- capacity-dmips-mhz = <1024>;
-- clocks = <&scmi_clk SCMI_CLK_CPUB01>;
-- cpu-idle-states = <&CPU_SLEEP>;
-- i-cache-size = <65536>;
-- i-cache-line-size = <64>;
-- i-cache-sets = <256>;
-- d-cache-size = <65536>;
-- d-cache-line-size = <64>;
-- d-cache-sets = <256>;
-- next-level-cache = <&l2_cache_b1>;
-- dynamic-power-coefficient = <416>;
-- #cooling-cells = <2>;
-- };
--
-- cpu_b2: cpu@600 {
-- device_type = "cpu";
-- compatible = "arm,cortex-a76";
-- reg = <0x600>;
-- enable-method = "psci";
-- capacity-dmips-mhz = <1024>;
-- clocks = <&scmi_clk SCMI_CLK_CPUB23>;
-- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
-- assigned-clock-rates = <816000000>;
-- cpu-idle-states = <&CPU_SLEEP>;
-- i-cache-size = <65536>;
-- i-cache-line-size = <64>;
-- i-cache-sets = <256>;
-- d-cache-size = <65536>;
-- d-cache-line-size = <64>;
-- d-cache-sets = <256>;
-- next-level-cache = <&l2_cache_b2>;
-- dynamic-power-coefficient = <416>;
-- #cooling-cells = <2>;
-- };
--
-- cpu_b3: cpu@700 {
-- device_type = "cpu";
-- compatible = "arm,cortex-a76";
-- reg = <0x700>;
-- enable-method = "psci";
-- capacity-dmips-mhz = <1024>;
-- clocks = <&scmi_clk SCMI_CLK_CPUB23>;
-- cpu-idle-states = <&CPU_SLEEP>;
-- i-cache-size = <65536>;
-- i-cache-line-size = <64>;
-- i-cache-sets = <256>;
-- d-cache-size = <65536>;
-- d-cache-line-size = <64>;
-- d-cache-sets = <256>;
-- next-level-cache = <&l2_cache_b3>;
-- dynamic-power-coefficient = <416>;
-- #cooling-cells = <2>;
-- };
--
-- idle-states {
-- entry-method = "psci";
-- CPU_SLEEP: cpu-sleep {
-- compatible = "arm,idle-state";
-- local-timer-stop;
-- arm,psci-suspend-param = <0x0010000>;
-- entry-latency-us = <100>;
-- exit-latency-us = <120>;
-- min-residency-us = <1000>;
-- };
-- };
--
-- l2_cache_l0: l2-cache-l0 {
-- compatible = "cache";
-- cache-size = <131072>;
-- cache-line-size = <64>;
-- cache-sets = <512>;
-- cache-level = <2>;
-- cache-unified;
-- next-level-cache = <&l3_cache>;
-- };
--
-- l2_cache_l1: l2-cache-l1 {
-- compatible = "cache";
-- cache-size = <131072>;
-- cache-line-size = <64>;
-- cache-sets = <512>;
-- cache-level = <2>;
-- cache-unified;
-- next-level-cache = <&l3_cache>;
-- };
--
-- l2_cache_l2: l2-cache-l2 {
-- compatible = "cache";
-- cache-size = <131072>;
-- cache-line-size = <64>;
-- cache-sets = <512>;
-- cache-level = <2>;
-- cache-unified;
-- next-level-cache = <&l3_cache>;
-- };
--
-- l2_cache_l3: l2-cache-l3 {
-- compatible = "cache";
-- cache-size = <131072>;
-- cache-line-size = <64>;
-- cache-sets = <512>;
-- cache-level = <2>;
-- cache-unified;
-- next-level-cache = <&l3_cache>;
-- };
--
-- l2_cache_b0: l2-cache-b0 {
-- compatible = "cache";
-- cache-size = <524288>;
-- cache-line-size = <64>;
-- cache-sets = <1024>;
-- cache-level = <2>;
-- cache-unified;
-- next-level-cache = <&l3_cache>;
-- };
--
-- l2_cache_b1: l2-cache-b1 {
-- compatible = "cache";
-- cache-size = <524288>;
-- cache-line-size = <64>;
-- cache-sets = <1024>;
-- cache-level = <2>;
-- cache-unified;
-- next-level-cache = <&l3_cache>;
-- };
--
-- l2_cache_b2: l2-cache-b2 {
-- compatible = "cache";
-- cache-size = <524288>;
-- cache-line-size = <64>;
-- cache-sets = <1024>;
-- cache-level = <2>;
-- cache-unified;
-- next-level-cache = <&l3_cache>;
-- };
--
-- l2_cache_b3: l2-cache-b3 {
-- compatible = "cache";
-- cache-size = <524288>;
-- cache-line-size = <64>;
-- cache-sets = <1024>;
-- cache-level = <2>;
-- cache-unified;
-- next-level-cache = <&l3_cache>;
-- };
--
-- l3_cache: l3-cache {
-- compatible = "cache";
-- cache-size = <3145728>;
-- cache-line-size = <64>;
-- cache-sets = <4096>;
-- cache-level = <3>;
-- cache-unified;
-- };
-- };
--
-- display_subsystem: display-subsystem {
-- compatible = "rockchip,display-subsystem";
-- ports = <&vop_out>;
-- };
--
-- firmware {
-- optee: optee {
-- compatible = "linaro,optee-tz";
-- method = "smc";
-- };
--
-- scmi: scmi {
-- compatible = "arm,scmi-smc";
-- arm,smc-id = <0x82000010>;
-- shmem = <&scmi_shmem>;
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- scmi_clk: protocol@14 {
-- reg = <0x14>;
-- #clock-cells = <1>;
-- };
--
-- scmi_reset: protocol@16 {
-- reg = <0x16>;
-- #reset-cells = <1>;
-- };
-- };
-- };
--
-- pmu-a55 {
-- compatible = "arm,cortex-a55-pmu";
-- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
-- };
--
-- pmu-a76 {
-- compatible = "arm,cortex-a76-pmu";
-- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
-- };
--
-- psci {
-- compatible = "arm,psci-1.0";
-- method = "smc";
-- };
--
-- spll: clock-0 {
-- compatible = "fixed-clock";
-- clock-frequency = <702000000>;
-- clock-output-names = "spll";
-- #clock-cells = <0>;
-- };
--
-- timer {
-- compatible = "arm,armv8-timer";
-- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
-- };
--
-- xin24m: clock-1 {
-- compatible = "fixed-clock";
-- clock-frequency = <24000000>;
-- clock-output-names = "xin24m";
-- #clock-cells = <0>;
-- };
--
-- xin32k: clock-2 {
-- compatible = "fixed-clock";
-- clock-frequency = <32768>;
-- clock-output-names = "xin32k";
-- #clock-cells = <0>;
-- };
--
-- pmu_sram: sram@10f000 {
-- compatible = "mmio-sram";
-- reg = <0x0 0x0010f000 0x0 0x100>;
-- ranges = <0 0x0 0x0010f000 0x100>;
-- #address-cells = <1>;
-- #size-cells = <1>;
--
-- scmi_shmem: sram@0 {
-- compatible = "arm,scmi-shmem";
-- reg = <0x0 0x100>;
-- };
-- };
--
-- gpu: gpu@fb000000 {
-- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
-- reg = <0x0 0xfb000000 0x0 0x200000>;
-- #cooling-cells = <2>;
-- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
-- assigned-clock-rates = <200000000>;
-- clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
-- <&cru CLK_GPU_STACKS>;
-- clock-names = "core", "coregroup", "stacks";
-- dynamic-power-coefficient = <2982>;
-- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "job", "mmu", "gpu";
-- operating-points-v2 = <&gpu_opp_table>;
-- power-domains = <&power RK3588_PD_GPU>;
-- status = "disabled";
--
-- gpu_opp_table: opp-table {
-- compatible = "operating-points-v2";
--
-- opp-300000000 {
-- opp-hz = /bits/ 64 <300000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-400000000 {
-- opp-hz = /bits/ 64 <400000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-500000000 {
-- opp-hz = /bits/ 64 <500000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-600000000 {
-- opp-hz = /bits/ 64 <600000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-700000000 {
-- opp-hz = /bits/ 64 <700000000>;
-- opp-microvolt = <700000 700000 850000>;
-- };
-- opp-800000000 {
-- opp-hz = /bits/ 64 <800000000>;
-- opp-microvolt = <750000 750000 850000>;
-- };
-- opp-900000000 {
-- opp-hz = /bits/ 64 <900000000>;
-- opp-microvolt = <800000 800000 850000>;
-- };
-- opp-1000000000 {
-- opp-hz = /bits/ 64 <1000000000>;
-- opp-microvolt = <850000 850000 850000>;
-- };
-- };
-- };
--
-- usb_host0_xhci: usb@fc000000 {
-- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
-- reg = <0x0 0xfc000000 0x0 0x400000>;
-- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
-- <&cru ACLK_USB3OTG0>;
-- clock-names = "ref_clk", "suspend_clk", "bus_clk";
-- dr_mode = "otg";
-- phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
-- phy-names = "usb2-phy", "usb3-phy";
-- phy_type = "utmi_wide";
-- power-domains = <&power RK3588_PD_USB>;
-- resets = <&cru SRST_A_USB3OTG0>;
-- snps,dis_enblslpm_quirk;
-- snps,dis-u1-entry-quirk;
-- snps,dis-u2-entry-quirk;
-- snps,dis-u2-freeclk-exists-quirk;
-- snps,dis-del-phy-power-chg-quirk;
-- snps,dis-tx-ipgap-linecheck-quirk;
-- status = "disabled";
-- };
--
-- usb_host0_ehci: usb@fc800000 {
-- compatible = "rockchip,rk3588-ehci", "generic-ehci";
-- reg = <0x0 0xfc800000 0x0 0x40000>;
-- interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
-- phys = <&u2phy2_host>;
-- phy-names = "usb";
-- power-domains = <&power RK3588_PD_USB>;
-- status = "disabled";
-- };
--
-- usb_host0_ohci: usb@fc840000 {
-- compatible = "rockchip,rk3588-ohci", "generic-ohci";
-- reg = <0x0 0xfc840000 0x0 0x40000>;
-- interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
-- phys = <&u2phy2_host>;
-- phy-names = "usb";
-- power-domains = <&power RK3588_PD_USB>;
-- status = "disabled";
-- };
--
-- usb_host1_ehci: usb@fc880000 {
-- compatible = "rockchip,rk3588-ehci", "generic-ehci";
-- reg = <0x0 0xfc880000 0x0 0x40000>;
-- interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
-- phys = <&u2phy3_host>;
-- phy-names = "usb";
-- power-domains = <&power RK3588_PD_USB>;
-- status = "disabled";
-- };
--
-- usb_host1_ohci: usb@fc8c0000 {
-- compatible = "rockchip,rk3588-ohci", "generic-ohci";
-- reg = <0x0 0xfc8c0000 0x0 0x40000>;
-- interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
-- phys = <&u2phy3_host>;
-- phy-names = "usb";
-- power-domains = <&power RK3588_PD_USB>;
-- status = "disabled";
-- };
--
-- usb_host2_xhci: usb@fcd00000 {
-- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
-- reg = <0x0 0xfcd00000 0x0 0x400000>;
-- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
-- <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
-- <&cru CLK_PIPEPHY2_PIPE_U3_G>;
-- clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
-- dr_mode = "host";
-- phys = <&combphy2_psu PHY_TYPE_USB3>;
-- phy-names = "usb3-phy";
-- phy_type = "utmi_wide";
-- resets = <&cru SRST_A_USB3OTG2>;
-- snps,dis_enblslpm_quirk;
-- snps,dis-u2-freeclk-exists-quirk;
-- snps,dis-del-phy-power-chg-quirk;
-- snps,dis-tx-ipgap-linecheck-quirk;
-- snps,dis_rxdet_inp3_quirk;
-- status = "disabled";
-- };
--
-- mmu600_pcie: iommu@fc900000 {
-- compatible = "arm,smmu-v3";
-- reg = <0x0 0xfc900000 0x0 0x200000>;
-- interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
-- #iommu-cells = <1>;
-- status = "disabled";
-- };
--
-- mmu600_php: iommu@fcb00000 {
-- compatible = "arm,smmu-v3";
-- reg = <0x0 0xfcb00000 0x0 0x200000>;
-- interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
-- #iommu-cells = <1>;
-- status = "disabled";
-- };
--
-- pmu1grf: syscon@fd58a000 {
-- compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
-- reg = <0x0 0xfd58a000 0x0 0x10000>;
-- };
--
-- sys_grf: syscon@fd58c000 {
-- compatible = "rockchip,rk3588-sys-grf", "syscon";
-- reg = <0x0 0xfd58c000 0x0 0x1000>;
-- };
--
-- vop_grf: syscon@fd5a4000 {
-- compatible = "rockchip,rk3588-vop-grf", "syscon";
-- reg = <0x0 0xfd5a4000 0x0 0x2000>;
-- };
--
-- vo0_grf: syscon@fd5a6000 {
-- compatible = "rockchip,rk3588-vo-grf", "syscon";
-- reg = <0x0 0xfd5a6000 0x0 0x2000>;
-- clocks = <&cru PCLK_VO0GRF>;
-- };
--
-- vo1_grf: syscon@fd5a8000 {
-- compatible = "rockchip,rk3588-vo-grf", "syscon";
-- reg = <0x0 0xfd5a8000 0x0 0x100>;
-- clocks = <&cru PCLK_VO1GRF>;
-- };
--
-- usb_grf: syscon@fd5ac000 {
-- compatible = "rockchip,rk3588-usb-grf", "syscon";
-- reg = <0x0 0xfd5ac000 0x0 0x4000>;
-- };
--
-- php_grf: syscon@fd5b0000 {
-- compatible = "rockchip,rk3588-php-grf", "syscon";
-- reg = <0x0 0xfd5b0000 0x0 0x1000>;
-- };
--
-- pipe_phy0_grf: syscon@fd5bc000 {
-- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
-- reg = <0x0 0xfd5bc000 0x0 0x100>;
-- };
--
-- pipe_phy2_grf: syscon@fd5c4000 {
-- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
-- reg = <0x0 0xfd5c4000 0x0 0x100>;
-- };
--
-- usbdpphy0_grf: syscon@fd5c8000 {
-- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
-- reg = <0x0 0xfd5c8000 0x0 0x4000>;
-- };
--
-- usb2phy0_grf: syscon@fd5d0000 {
-- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-- reg = <0x0 0xfd5d0000 0x0 0x4000>;
-- #address-cells = <1>;
-- #size-cells = <1>;
--
-- u2phy0: usb2phy@0 {
-- compatible = "rockchip,rk3588-usb2phy";
-- reg = <0x0 0x10>;
-- #clock-cells = <0>;
-- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-- clock-names = "phyclk";
-- clock-output-names = "usb480m_phy0";
-- interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
-- resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
-- reset-names = "phy", "apb";
-- status = "disabled";
--
-- u2phy0_otg: otg-port {
-- #phy-cells = <0>;
-- status = "disabled";
-- };
-- };
-- };
--
-- usb2phy2_grf: syscon@fd5d8000 {
-- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-- reg = <0x0 0xfd5d8000 0x0 0x4000>;
-- #address-cells = <1>;
-- #size-cells = <1>;
--
-- u2phy2: usb2phy@8000 {
-- compatible = "rockchip,rk3588-usb2phy";
-- reg = <0x8000 0x10>;
-- #clock-cells = <0>;
-- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-- clock-names = "phyclk";
-- clock-output-names = "usb480m_phy2";
-- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
-- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
-- reset-names = "phy", "apb";
-- status = "disabled";
--
-- u2phy2_host: host-port {
-- #phy-cells = <0>;
-- status = "disabled";
-- };
-- };
-- };
--
-- usb2phy3_grf: syscon@fd5dc000 {
-- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
-- reg = <0x0 0xfd5dc000 0x0 0x4000>;
-- #address-cells = <1>;
-- #size-cells = <1>;
--
-- u2phy3: usb2phy@c000 {
-- compatible = "rockchip,rk3588-usb2phy";
-- reg = <0xc000 0x10>;
-- #clock-cells = <0>;
-- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
-- clock-names = "phyclk";
-- clock-output-names = "usb480m_phy3";
-- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
-- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
-- reset-names = "phy", "apb";
-- status = "disabled";
--
-- u2phy3_host: host-port {
-- #phy-cells = <0>;
-- status = "disabled";
-- };
-- };
-- };
--
-- hdptxphy0_grf: syscon@fd5e0000 {
-- compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
-- reg = <0x0 0xfd5e0000 0x0 0x100>;
-- };
--
-- ioc: syscon@fd5f0000 {
-- compatible = "rockchip,rk3588-ioc", "syscon";
-- reg = <0x0 0xfd5f0000 0x0 0x10000>;
-- };
--
-- system_sram1: sram@fd600000 {
-- compatible = "mmio-sram";
-- reg = <0x0 0xfd600000 0x0 0x100000>;
-- ranges = <0x0 0x0 0xfd600000 0x100000>;
-- #address-cells = <1>;
-- #size-cells = <1>;
-- };
--
-- cru: clock-controller@fd7c0000 {
-- compatible = "rockchip,rk3588-cru";
-- reg = <0x0 0xfd7c0000 0x0 0x5c000>;
-- assigned-clocks =
-- <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
-- <&cru PLL_NPLL>, <&cru PLL_GPLL>,
-- <&cru ACLK_CENTER_ROOT>,
-- <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
-- <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
-- <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
-- <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
-- <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
-- <&cru CLK_GPU>;
-- assigned-clock-rates =
-- <1100000000>, <786432000>,
-- <850000000>, <1188000000>,
-- <702000000>,
-- <400000000>, <500000000>,
-- <800000000>, <100000000>,
-- <400000000>, <100000000>,
-- <200000000>, <500000000>,
-- <375000000>, <150000000>,
-- <200000000>;
-- rockchip,grf = <&php_grf>;
-- #clock-cells = <1>;
-- #reset-cells = <1>;
-- };
--
-- i2c0: i2c@fd880000 {
-- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-- reg = <0x0 0xfd880000 0x0 0x1000>;
-- interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
-- clock-names = "i2c", "pclk";
-- pinctrl-0 = <&i2c0m0_xfer>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- uart0: serial@fd890000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfd890000 0x0 0x100>;
-- interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac0 6>, <&dmac0 7>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart0m1_xfer>;
-- pinctrl-names = "default";
-- reg-shift = <2>;
-- reg-io-width = <4>;
-- status = "disabled";
-- };
--
-- pwm0: pwm@fd8b0000 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfd8b0000 0x0 0x10>;
-- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm0m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm1: pwm@fd8b0010 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfd8b0010 0x0 0x10>;
-- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm1m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm2: pwm@fd8b0020 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfd8b0020 0x0 0x10>;
-- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm2m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm3: pwm@fd8b0030 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfd8b0030 0x0 0x10>;
-- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm3m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pmu: power-management@fd8d8000 {
-- compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
-- reg = <0x0 0xfd8d8000 0x0 0x400>;
--
-- power: power-controller {
-- compatible = "rockchip,rk3588-power-controller";
-- #address-cells = <1>;
-- #power-domain-cells = <1>;
-- #size-cells = <0>;
-- status = "okay";
--
-- /* These power domains are grouped by VD_NPU */
-- power-domain@RK3588_PD_NPU {
-- reg = <RK3588_PD_NPU>;
-- #power-domain-cells = <0>;
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- power-domain@RK3588_PD_NPUTOP {
-- reg = <RK3588_PD_NPUTOP>;
-- clocks = <&cru HCLK_NPU_ROOT>,
-- <&cru PCLK_NPU_ROOT>,
-- <&cru CLK_NPU_DSU0>,
-- <&cru HCLK_NPU_CM0_ROOT>;
-- pm_qos = <&qos_npu0_mwr>,
-- <&qos_npu0_mro>,
-- <&qos_mcu_npu>;
-- #power-domain-cells = <0>;
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- power-domain@RK3588_PD_NPU1 {
-- reg = <RK3588_PD_NPU1>;
-- clocks = <&cru HCLK_NPU_ROOT>,
-- <&cru PCLK_NPU_ROOT>,
-- <&cru CLK_NPU_DSU0>;
-- pm_qos = <&qos_npu1>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_NPU2 {
-- reg = <RK3588_PD_NPU2>;
-- clocks = <&cru HCLK_NPU_ROOT>,
-- <&cru PCLK_NPU_ROOT>,
-- <&cru CLK_NPU_DSU0>;
-- pm_qos = <&qos_npu2>;
-- #power-domain-cells = <0>;
-- };
-- };
-- };
-- /* These power domains are grouped by VD_GPU */
-- power-domain@RK3588_PD_GPU {
-- reg = <RK3588_PD_GPU>;
-- clocks = <&cru CLK_GPU>,
-- <&cru CLK_GPU_COREGROUP>,
-- <&cru CLK_GPU_STACKS>;
-- pm_qos = <&qos_gpu_m0>,
-- <&qos_gpu_m1>,
-- <&qos_gpu_m2>,
-- <&qos_gpu_m3>;
-- #power-domain-cells = <0>;
-- };
-- /* These power domains are grouped by VD_VCODEC */
-- power-domain@RK3588_PD_VCODEC {
-- reg = <RK3588_PD_VCODEC>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- #power-domain-cells = <0>;
--
-- power-domain@RK3588_PD_RKVDEC0 {
-- reg = <RK3588_PD_RKVDEC0>;
-- clocks = <&cru HCLK_RKVDEC0>,
-- <&cru HCLK_VDPU_ROOT>,
-- <&cru ACLK_VDPU_ROOT>,
-- <&cru ACLK_RKVDEC0>,
-- <&cru ACLK_RKVDEC_CCU>;
-- pm_qos = <&qos_rkvdec0>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_RKVDEC1 {
-- reg = <RK3588_PD_RKVDEC1>;
-- clocks = <&cru HCLK_RKVDEC1>,
-- <&cru HCLK_VDPU_ROOT>,
-- <&cru ACLK_VDPU_ROOT>,
-- <&cru ACLK_RKVDEC1>;
-- pm_qos = <&qos_rkvdec1>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_VENC0 {
-- reg = <RK3588_PD_VENC0>;
-- clocks = <&cru HCLK_RKVENC0>,
-- <&cru ACLK_RKVENC0>;
-- pm_qos = <&qos_rkvenc0_m0ro>,
-- <&qos_rkvenc0_m1ro>,
-- <&qos_rkvenc0_m2wo>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- #power-domain-cells = <0>;
--
-- power-domain@RK3588_PD_VENC1 {
-- reg = <RK3588_PD_VENC1>;
-- clocks = <&cru HCLK_RKVENC1>,
-- <&cru HCLK_RKVENC0>,
-- <&cru ACLK_RKVENC0>,
-- <&cru ACLK_RKVENC1>;
-- pm_qos = <&qos_rkvenc1_m0ro>,
-- <&qos_rkvenc1_m1ro>,
-- <&qos_rkvenc1_m2wo>;
-- #power-domain-cells = <0>;
-- };
-- };
-- };
-- /* These power domains are grouped by VD_LOGIC */
-- power-domain@RK3588_PD_VDPU {
-- reg = <RK3588_PD_VDPU>;
-- clocks = <&cru HCLK_VDPU_ROOT>,
-- <&cru ACLK_VDPU_LOW_ROOT>,
-- <&cru ACLK_VDPU_ROOT>,
-- <&cru ACLK_JPEG_DECODER_ROOT>,
-- <&cru ACLK_IEP2P0>,
-- <&cru HCLK_IEP2P0>,
-- <&cru ACLK_JPEG_ENCODER0>,
-- <&cru HCLK_JPEG_ENCODER0>,
-- <&cru ACLK_JPEG_ENCODER1>,
-- <&cru HCLK_JPEG_ENCODER1>,
-- <&cru ACLK_JPEG_ENCODER2>,
-- <&cru HCLK_JPEG_ENCODER2>,
-- <&cru ACLK_JPEG_ENCODER3>,
-- <&cru HCLK_JPEG_ENCODER3>,
-- <&cru ACLK_JPEG_DECODER>,
-- <&cru HCLK_JPEG_DECODER>,
-- <&cru ACLK_RGA2>,
-- <&cru HCLK_RGA2>;
-- pm_qos = <&qos_iep>,
-- <&qos_jpeg_dec>,
-- <&qos_jpeg_enc0>,
-- <&qos_jpeg_enc1>,
-- <&qos_jpeg_enc2>,
-- <&qos_jpeg_enc3>,
-- <&qos_rga2_mro>,
-- <&qos_rga2_mwo>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- #power-domain-cells = <0>;
--
--
-- power-domain@RK3588_PD_AV1 {
-- reg = <RK3588_PD_AV1>;
-- clocks = <&cru PCLK_AV1>,
-- <&cru ACLK_AV1>,
-- <&cru HCLK_VDPU_ROOT>;
-- pm_qos = <&qos_av1>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_RKVDEC0 {
-- reg = <RK3588_PD_RKVDEC0>;
-- clocks = <&cru HCLK_RKVDEC0>,
-- <&cru HCLK_VDPU_ROOT>,
-- <&cru ACLK_VDPU_ROOT>,
-- <&cru ACLK_RKVDEC0>;
-- pm_qos = <&qos_rkvdec0>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_RKVDEC1 {
-- reg = <RK3588_PD_RKVDEC1>;
-- clocks = <&cru HCLK_RKVDEC1>,
-- <&cru HCLK_VDPU_ROOT>,
-- <&cru ACLK_VDPU_ROOT>;
-- pm_qos = <&qos_rkvdec1>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_RGA30 {
-- reg = <RK3588_PD_RGA30>;
-- clocks = <&cru ACLK_RGA3_0>,
-- <&cru HCLK_RGA3_0>;
-- pm_qos = <&qos_rga3_0>;
-- #power-domain-cells = <0>;
-- };
-- };
-- power-domain@RK3588_PD_VOP {
-- reg = <RK3588_PD_VOP>;
-- clocks = <&cru PCLK_VOP_ROOT>,
-- <&cru HCLK_VOP_ROOT>,
-- <&cru ACLK_VOP>;
-- pm_qos = <&qos_vop_m0>,
-- <&qos_vop_m1>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- #power-domain-cells = <0>;
--
-- power-domain@RK3588_PD_VO0 {
-- reg = <RK3588_PD_VO0>;
-- clocks = <&cru PCLK_VO0_ROOT>,
-- <&cru PCLK_VO0_S_ROOT>,
-- <&cru HCLK_VO0_S_ROOT>,
-- <&cru ACLK_VO0_ROOT>,
-- <&cru HCLK_HDCP0>,
-- <&cru ACLK_HDCP0>,
-- <&cru HCLK_VOP_ROOT>;
-- pm_qos = <&qos_hdcp0>;
-- #power-domain-cells = <0>;
-- };
-- };
-- power-domain@RK3588_PD_VO1 {
-- reg = <RK3588_PD_VO1>;
-- clocks = <&cru PCLK_VO1_ROOT>,
-- <&cru PCLK_VO1_S_ROOT>,
-- <&cru HCLK_VO1_S_ROOT>,
-- <&cru HCLK_HDCP1>,
-- <&cru ACLK_HDCP1>,
-- <&cru ACLK_HDMIRX_ROOT>,
-- <&cru HCLK_VO1USB_TOP_ROOT>;
-- pm_qos = <&qos_hdcp1>,
-- <&qos_hdmirx>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_VI {
-- reg = <RK3588_PD_VI>;
-- clocks = <&cru HCLK_VI_ROOT>,
-- <&cru PCLK_VI_ROOT>,
-- <&cru HCLK_ISP0>,
-- <&cru ACLK_ISP0>,
-- <&cru HCLK_VICAP>,
-- <&cru ACLK_VICAP>;
-- pm_qos = <&qos_isp0_mro>,
-- <&qos_isp0_mwo>,
-- <&qos_vicap_m0>,
-- <&qos_vicap_m1>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- #power-domain-cells = <0>;
--
-- power-domain@RK3588_PD_ISP1 {
-- reg = <RK3588_PD_ISP1>;
-- clocks = <&cru HCLK_ISP1>,
-- <&cru ACLK_ISP1>,
-- <&cru HCLK_VI_ROOT>,
-- <&cru PCLK_VI_ROOT>;
-- pm_qos = <&qos_isp1_mwo>,
-- <&qos_isp1_mro>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_FEC {
-- reg = <RK3588_PD_FEC>;
-- clocks = <&cru HCLK_FISHEYE0>,
-- <&cru ACLK_FISHEYE0>,
-- <&cru HCLK_FISHEYE1>,
-- <&cru ACLK_FISHEYE1>,
-- <&cru PCLK_VI_ROOT>;
-- pm_qos = <&qos_fisheye0>,
-- <&qos_fisheye1>;
-- #power-domain-cells = <0>;
-- };
-- };
-- power-domain@RK3588_PD_RGA31 {
-- reg = <RK3588_PD_RGA31>;
-- clocks = <&cru HCLK_RGA3_1>,
-- <&cru ACLK_RGA3_1>;
-- pm_qos = <&qos_rga3_1>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_USB {
-- reg = <RK3588_PD_USB>;
-- clocks = <&cru PCLK_PHP_ROOT>,
-- <&cru ACLK_USB_ROOT>,
-- <&cru ACLK_USB>,
-- <&cru HCLK_USB_ROOT>,
-- <&cru HCLK_HOST0>,
-- <&cru HCLK_HOST_ARB0>,
-- <&cru HCLK_HOST1>,
-- <&cru HCLK_HOST_ARB1>;
-- pm_qos = <&qos_usb3_0>,
-- <&qos_usb3_1>,
-- <&qos_usb2host_0>,
-- <&qos_usb2host_1>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_GMAC {
-- reg = <RK3588_PD_GMAC>;
-- clocks = <&cru PCLK_PHP_ROOT>,
-- <&cru ACLK_PCIE_ROOT>,
-- <&cru ACLK_PHP_ROOT>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_PCIE {
-- reg = <RK3588_PD_PCIE>;
-- clocks = <&cru PCLK_PHP_ROOT>,
-- <&cru ACLK_PCIE_ROOT>,
-- <&cru ACLK_PHP_ROOT>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_SDIO {
-- reg = <RK3588_PD_SDIO>;
-- clocks = <&cru HCLK_SDIO>,
-- <&cru HCLK_NVM_ROOT>;
-- pm_qos = <&qos_sdio>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_AUDIO {
-- reg = <RK3588_PD_AUDIO>;
-- clocks = <&cru HCLK_AUDIO_ROOT>,
-- <&cru PCLK_AUDIO_ROOT>;
-- #power-domain-cells = <0>;
-- };
-- power-domain@RK3588_PD_SDMMC {
-- reg = <RK3588_PD_SDMMC>;
-- pm_qos = <&qos_sdmmc>;
-- #power-domain-cells = <0>;
-- };
-- };
-- };
--
-- av1d: video-codec@fdc70000 {
-- compatible = "rockchip,rk3588-av1-vpu";
-- reg = <0x0 0xfdc70000 0x0 0x800>;
-- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "vdpu";
-- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-- assigned-clock-rates = <400000000>, <400000000>;
-- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
-- clock-names = "aclk", "hclk";
-- power-domains = <&power RK3588_PD_AV1>;
-- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
-- };
--
-- vop: vop@fdd90000 {
-- compatible = "rockchip,rk3588-vop";
-- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
-- reg-names = "vop", "gamma-lut";
-- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru ACLK_VOP>,
-- <&cru HCLK_VOP>,
-- <&cru DCLK_VOP0>,
-- <&cru DCLK_VOP1>,
-- <&cru DCLK_VOP2>,
-- <&cru DCLK_VOP3>,
-- <&cru PCLK_VOP_ROOT>;
-- clock-names = "aclk",
-- "hclk",
-- "dclk_vp0",
-- "dclk_vp1",
-- "dclk_vp2",
-- "dclk_vp3",
-- "pclk_vop";
-- iommus = <&vop_mmu>;
-- power-domains = <&power RK3588_PD_VOP>;
-- rockchip,grf = <&sys_grf>;
-- rockchip,vop-grf = <&vop_grf>;
-- rockchip,vo1-grf = <&vo1_grf>;
-- rockchip,pmu = <&pmu>;
-- status = "disabled";
--
-- vop_out: ports {
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- vp0: port@0 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <0>;
-- };
--
-- vp1: port@1 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <1>;
-- };
--
-- vp2: port@2 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <2>;
-- };
--
-- vp3: port@3 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <3>;
-- };
-- };
-- };
--
-- vop_mmu: iommu@fdd97e00 {
-- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
-- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
-- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
-- clock-names = "aclk", "iface";
-- #iommu-cells = <0>;
-- power-domains = <&power RK3588_PD_VOP>;
-- status = "disabled";
-- };
--
-- i2s4_8ch: i2s@fddc0000 {
-- compatible = "rockchip,rk3588-i2s-tdm";
-- reg = <0x0 0xfddc0000 0x0 0x1000>;
-- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
-- clock-names = "mclk_tx", "mclk_rx", "hclk";
-- assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>;
-- dmas = <&dmac2 0>;
-- dma-names = "tx";
-- power-domains = <&power RK3588_PD_VO0>;
-- resets = <&cru SRST_M_I2S4_8CH_TX>;
-- reset-names = "tx-m";
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- i2s5_8ch: i2s@fddf0000 {
-- compatible = "rockchip,rk3588-i2s-tdm";
-- reg = <0x0 0xfddf0000 0x0 0x1000>;
-- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
-- clock-names = "mclk_tx", "mclk_rx", "hclk";
-- assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>;
-- dmas = <&dmac2 2>;
-- dma-names = "tx";
-- power-domains = <&power RK3588_PD_VO1>;
-- resets = <&cru SRST_M_I2S5_8CH_TX>;
-- reset-names = "tx-m";
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- i2s9_8ch: i2s@fddfc000 {
-- compatible = "rockchip,rk3588-i2s-tdm";
-- reg = <0x0 0xfddfc000 0x0 0x1000>;
-- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
-- clock-names = "mclk_tx", "mclk_rx", "hclk";
-- assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>;
-- dmas = <&dmac2 23>;
-- dma-names = "rx";
-- power-domains = <&power RK3588_PD_VO1>;
-- resets = <&cru SRST_M_I2S9_8CH_RX>;
-- reset-names = "rx-m";
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- qos_gpu_m0: qos@fdf35000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf35000 0x0 0x20>;
-- };
--
-- qos_gpu_m1: qos@fdf35200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf35200 0x0 0x20>;
-- };
--
-- qos_gpu_m2: qos@fdf35400 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf35400 0x0 0x20>;
-- };
--
-- qos_gpu_m3: qos@fdf35600 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf35600 0x0 0x20>;
-- };
--
-- qos_rga3_1: qos@fdf36000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf36000 0x0 0x20>;
-- };
--
-- qos_sdio: qos@fdf39000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf39000 0x0 0x20>;
-- };
--
-- qos_sdmmc: qos@fdf3d800 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf3d800 0x0 0x20>;
-- };
--
-- qos_usb3_1: qos@fdf3e000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf3e000 0x0 0x20>;
-- };
--
-- qos_usb3_0: qos@fdf3e200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf3e200 0x0 0x20>;
-- };
--
-- qos_usb2host_0: qos@fdf3e400 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf3e400 0x0 0x20>;
-- };
--
-- qos_usb2host_1: qos@fdf3e600 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf3e600 0x0 0x20>;
-- };
--
-- qos_fisheye0: qos@fdf40000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf40000 0x0 0x20>;
-- };
--
-- qos_fisheye1: qos@fdf40200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf40200 0x0 0x20>;
-- };
--
-- qos_isp0_mro: qos@fdf40400 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf40400 0x0 0x20>;
-- };
--
-- qos_isp0_mwo: qos@fdf40500 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf40500 0x0 0x20>;
-- };
--
-- qos_vicap_m0: qos@fdf40600 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf40600 0x0 0x20>;
-- };
--
-- qos_vicap_m1: qos@fdf40800 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf40800 0x0 0x20>;
-- };
--
-- qos_isp1_mwo: qos@fdf41000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf41000 0x0 0x20>;
-- };
--
-- qos_isp1_mro: qos@fdf41100 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf41100 0x0 0x20>;
-- };
--
-- qos_rkvenc0_m0ro: qos@fdf60000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf60000 0x0 0x20>;
-- };
--
-- qos_rkvenc0_m1ro: qos@fdf60200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf60200 0x0 0x20>;
-- };
--
-- qos_rkvenc0_m2wo: qos@fdf60400 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf60400 0x0 0x20>;
-- };
--
-- qos_rkvenc1_m0ro: qos@fdf61000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf61000 0x0 0x20>;
-- };
--
-- qos_rkvenc1_m1ro: qos@fdf61200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf61200 0x0 0x20>;
-- };
--
-- qos_rkvenc1_m2wo: qos@fdf61400 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf61400 0x0 0x20>;
-- };
--
-- qos_rkvdec0: qos@fdf62000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf62000 0x0 0x20>;
-- };
--
-- qos_rkvdec1: qos@fdf63000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf63000 0x0 0x20>;
-- };
--
-- qos_av1: qos@fdf64000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf64000 0x0 0x20>;
-- };
--
-- qos_iep: qos@fdf66000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf66000 0x0 0x20>;
-- };
--
-- qos_jpeg_dec: qos@fdf66200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf66200 0x0 0x20>;
-- };
--
-- qos_jpeg_enc0: qos@fdf66400 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf66400 0x0 0x20>;
-- };
--
-- qos_jpeg_enc1: qos@fdf66600 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf66600 0x0 0x20>;
-- };
--
-- qos_jpeg_enc2: qos@fdf66800 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf66800 0x0 0x20>;
-- };
--
-- qos_jpeg_enc3: qos@fdf66a00 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf66a00 0x0 0x20>;
-- };
--
-- qos_rga2_mro: qos@fdf66c00 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf66c00 0x0 0x20>;
-- };
--
-- qos_rga2_mwo: qos@fdf66e00 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf66e00 0x0 0x20>;
-- };
--
-- qos_rga3_0: qos@fdf67000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf67000 0x0 0x20>;
-- };
--
-- qos_vdpu: qos@fdf67200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf67200 0x0 0x20>;
-- };
--
-- qos_npu1: qos@fdf70000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf70000 0x0 0x20>;
-- };
--
-- qos_npu2: qos@fdf71000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf71000 0x0 0x20>;
-- };
--
-- qos_npu0_mwr: qos@fdf72000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf72000 0x0 0x20>;
-- };
--
-- qos_npu0_mro: qos@fdf72200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf72200 0x0 0x20>;
-- };
--
-- qos_mcu_npu: qos@fdf72400 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf72400 0x0 0x20>;
-- };
--
-- qos_hdcp0: qos@fdf80000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf80000 0x0 0x20>;
-- };
--
-- qos_hdcp1: qos@fdf81000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf81000 0x0 0x20>;
-- };
--
-- qos_hdmirx: qos@fdf81200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf81200 0x0 0x20>;
-- };
--
-- qos_vop_m0: qos@fdf82000 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf82000 0x0 0x20>;
-- };
--
-- qos_vop_m1: qos@fdf82200 {
-- compatible = "rockchip,rk3588-qos", "syscon";
-- reg = <0x0 0xfdf82200 0x0 0x20>;
-- };
--
-- dfi: dfi@fe060000 {
-- reg = <0x00 0xfe060000 0x00 0x10000>;
-- compatible = "rockchip,rk3588-dfi";
-- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
-- rockchip,pmu = <&pmu1grf>;
-- };
--
-- pcie2x1l1: pcie@fe180000 {
-- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-- bus-range = <0x30 0x3f>;
-- clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
-- <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
-- <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
-- clock-names = "aclk_mst", "aclk_slv",
-- "aclk_dbi", "pclk",
-- "aux", "pipe";
-- device_type = "pci";
-- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-- #interrupt-cells = <1>;
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
-- <0 0 0 2 &pcie2x1l1_intc 1>,
-- <0 0 0 3 &pcie2x1l1_intc 2>,
-- <0 0 0 4 &pcie2x1l1_intc 3>;
-- linux,pci-domain = <3>;
-- max-link-speed = <2>;
-- msi-map = <0x3000 &its0 0x3000 0x1000>;
-- num-lanes = <1>;
-- phys = <&combphy2_psu PHY_TYPE_PCIE>;
-- phy-names = "pcie-phy";
-- power-domains = <&power RK3588_PD_PCIE>;
-- ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
-- <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
-- <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
-- reg = <0xa 0x40c00000 0x0 0x00400000>,
-- <0x0 0xfe180000 0x0 0x00010000>,
-- <0x0 0xf3000000 0x0 0x00100000>;
-- reg-names = "dbi", "apb", "config";
-- resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
-- reset-names = "pwr", "pipe";
-- #address-cells = <3>;
-- #size-cells = <2>;
-- status = "disabled";
--
-- pcie2x1l1_intc: legacy-interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- interrupt-parent = <&gic>;
-- interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
-- };
-- };
--
-- pcie2x1l2: pcie@fe190000 {
-- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
-- bus-range = <0x40 0x4f>;
-- clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
-- <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
-- <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
-- clock-names = "aclk_mst", "aclk_slv",
-- "aclk_dbi", "pclk",
-- "aux", "pipe";
-- device_type = "pci";
-- interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-- #interrupt-cells = <1>;
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
-- <0 0 0 2 &pcie2x1l2_intc 1>,
-- <0 0 0 3 &pcie2x1l2_intc 2>,
-- <0 0 0 4 &pcie2x1l2_intc 3>;
-- linux,pci-domain = <4>;
-- max-link-speed = <2>;
-- msi-map = <0x4000 &its0 0x4000 0x1000>;
-- num-lanes = <1>;
-- phys = <&combphy0_ps PHY_TYPE_PCIE>;
-- phy-names = "pcie-phy";
-- power-domains = <&power RK3588_PD_PCIE>;
-- ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
-- <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
-- <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
-- reg = <0xa 0x41000000 0x0 0x00400000>,
-- <0x0 0xfe190000 0x0 0x00010000>,
-- <0x0 0xf4000000 0x0 0x00100000>;
-- reg-names = "dbi", "apb", "config";
-- resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
-- reset-names = "pwr", "pipe";
-- #address-cells = <3>;
-- #size-cells = <2>;
-- status = "disabled";
--
-- pcie2x1l2_intc: legacy-interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- interrupt-parent = <&gic>;
-- interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
-- };
-- };
--
-- gmac1: ethernet@fe1c0000 {
-- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
-- reg = <0x0 0xfe1c0000 0x0 0x10000>;
-- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-names = "macirq", "eth_wake_irq";
-- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
-- <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
-- <&cru CLK_GMAC1_PTP_REF>;
-- clock-names = "stmmaceth", "clk_mac_ref",
-- "pclk_mac", "aclk_mac",
-- "ptp_ref";
-- power-domains = <&power RK3588_PD_GMAC>;
-- resets = <&cru SRST_A_GMAC1>;
-- reset-names = "stmmaceth";
-- rockchip,grf = <&sys_grf>;
-- rockchip,php-grf = <&php_grf>;
-- snps,axi-config = <&gmac1_stmmac_axi_setup>;
-- snps,mixed-burst;
-- snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
-- snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
-- snps,tso;
-- status = "disabled";
--
-- mdio1: mdio {
-- compatible = "snps,dwmac-mdio";
-- #address-cells = <0x1>;
-- #size-cells = <0x0>;
-- };
--
-- gmac1_stmmac_axi_setup: stmmac-axi-config {
-- snps,blen = <0 0 0 0 16 8 4>;
-- snps,wr_osr_lmt = <4>;
-- snps,rd_osr_lmt = <8>;
-- };
--
-- gmac1_mtl_rx_setup: rx-queues-config {
-- snps,rx-queues-to-use = <2>;
-- queue0 {};
-- queue1 {};
-- };
--
-- gmac1_mtl_tx_setup: tx-queues-config {
-- snps,tx-queues-to-use = <2>;
-- queue0 {};
-- queue1 {};
-- };
-- };
--
-- sata0: sata@fe210000 {
-- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
-- reg = <0 0xfe210000 0 0x1000>;
-- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
-- <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
-- <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
-- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
-- ports-implemented = <0x1>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
--
-- sata-port@0 {
-- reg = <0>;
-- hba-port-cap = <HBA_PORT_FBSCP>;
-- phys = <&combphy0_ps PHY_TYPE_SATA>;
-- phy-names = "sata-phy";
-- snps,rx-ts-max = <32>;
-- snps,tx-ts-max = <32>;
-- };
-- };
--
-- sata2: sata@fe230000 {
-- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
-- reg = <0 0xfe230000 0 0x1000>;
-- interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
-- <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
-- <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
-- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
-- ports-implemented = <0x1>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
--
-- sata-port@0 {
-- reg = <0>;
-- hba-port-cap = <HBA_PORT_FBSCP>;
-- phys = <&combphy2_psu PHY_TYPE_SATA>;
-- phy-names = "sata-phy";
-- snps,rx-ts-max = <32>;
-- snps,tx-ts-max = <32>;
-- };
-- };
--
-- sfc: spi@fe2b0000 {
-- compatible = "rockchip,sfc";
-- reg = <0x0 0xfe2b0000 0x0 0x4000>;
-- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
-- clock-names = "clk_sfc", "hclk_sfc";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- sdmmc: mmc@fe2c0000 {
-- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
-- reg = <0x0 0xfe2c0000 0x0 0x4000>;
-- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
-- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-- fifo-depth = <0x100>;
-- max-frequency = <200000000>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
-- power-domains = <&power RK3588_PD_SDMMC>;
-- status = "disabled";
-- };
--
-- sdio: mmc@fe2d0000 {
-- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
-- reg = <0x00 0xfe2d0000 0x00 0x4000>;
-- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
-- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-- fifo-depth = <0x100>;
-- max-frequency = <200000000>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&sdiom1_pins>;
-- power-domains = <&power RK3588_PD_SDIO>;
-- status = "disabled";
-- };
--
-- sdhci: mmc@fe2e0000 {
-- compatible = "rockchip,rk3588-dwcmshc";
-- reg = <0x0 0xfe2e0000 0x0 0x10000>;
-- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
-- assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
-- assigned-clock-rates = <200000000>, <24000000>, <200000000>;
-- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
-- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
-- <&cru TMCLK_EMMC>;
-- clock-names = "core", "bus", "axi", "block", "timer";
-- max-frequency = <200000000>;
-- pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
-- <&emmc_cmd>, <&emmc_data_strobe>;
-- pinctrl-names = "default";
-- resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
-- <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
-- <&cru SRST_T_EMMC>;
-- reset-names = "core", "bus", "axi", "block", "timer";
-- status = "disabled";
-- };
--
-- i2s0_8ch: i2s@fe470000 {
-- compatible = "rockchip,rk3588-i2s-tdm";
-- reg = <0x0 0xfe470000 0x0 0x1000>;
-- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
-- clock-names = "mclk_tx", "mclk_rx", "hclk";
-- assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
-- dmas = <&dmac0 0>, <&dmac0 1>;
-- dma-names = "tx", "rx";
-- power-domains = <&power RK3588_PD_AUDIO>;
-- resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
-- reset-names = "tx-m", "rx-m";
-- rockchip,trcm-sync-tx-only;
-- pinctrl-names = "default";
-- pinctrl-0 = <&i2s0_lrck
-- &i2s0_sclk
-- &i2s0_sdi0
-- &i2s0_sdi1
-- &i2s0_sdi2
-- &i2s0_sdi3
-- &i2s0_sdo0
-- &i2s0_sdo1
-- &i2s0_sdo2
-- &i2s0_sdo3>;
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- i2s1_8ch: i2s@fe480000 {
-- compatible = "rockchip,rk3588-i2s-tdm";
-- reg = <0x0 0xfe480000 0x0 0x1000>;
-- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
-- clock-names = "mclk_tx", "mclk_rx", "hclk";
-- dmas = <&dmac0 2>, <&dmac0 3>;
-- dma-names = "tx", "rx";
-- resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
-- reset-names = "tx-m", "rx-m";
-- rockchip,trcm-sync-tx-only;
-- pinctrl-names = "default";
-- pinctrl-0 = <&i2s1m0_lrck
-- &i2s1m0_sclk
-- &i2s1m0_sdi0
-- &i2s1m0_sdi1
-- &i2s1m0_sdi2
-- &i2s1m0_sdi3
-- &i2s1m0_sdo0
-- &i2s1m0_sdo1
-- &i2s1m0_sdo2
-- &i2s1m0_sdo3>;
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- i2s2_2ch: i2s@fe490000 {
-- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
-- reg = <0x0 0xfe490000 0x0 0x1000>;
-- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
-- clock-names = "i2s_clk", "i2s_hclk";
-- assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>;
-- dmas = <&dmac1 0>, <&dmac1 1>;
-- dma-names = "tx", "rx";
-- power-domains = <&power RK3588_PD_AUDIO>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&i2s2m1_lrck
-- &i2s2m1_sclk
-- &i2s2m1_sdi
-- &i2s2m1_sdo>;
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- i2s3_2ch: i2s@fe4a0000 {
-- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
-- reg = <0x0 0xfe4a0000 0x0 0x1000>;
-- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
-- clock-names = "i2s_clk", "i2s_hclk";
-- assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
-- assigned-clock-parents = <&cru PLL_AUPLL>;
-- dmas = <&dmac1 2>, <&dmac1 3>;
-- dma-names = "tx", "rx";
-- power-domains = <&power RK3588_PD_AUDIO>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&i2s3_lrck
-- &i2s3_sclk
-- &i2s3_sdi
-- &i2s3_sdo>;
-- #sound-dai-cells = <0>;
-- status = "disabled";
-- };
--
-- gic: interrupt-controller@fe600000 {
-- compatible = "arm,gic-v3";
-- reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
-- <0x0 0xfe680000 0 0x100000>; /* GICR */
-- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
-- interrupt-controller;
-- mbi-alias = <0x0 0xfe610000>;
-- mbi-ranges = <424 56>;
-- msi-controller;
-- ranges;
-- #address-cells = <2>;
-- #interrupt-cells = <4>;
-- #size-cells = <2>;
--
-- its0: msi-controller@fe640000 {
-- compatible = "arm,gic-v3-its";
-- reg = <0x0 0xfe640000 0x0 0x20000>;
-- msi-controller;
-- #msi-cells = <1>;
-- };
--
-- its1: msi-controller@fe660000 {
-- compatible = "arm,gic-v3-its";
-- reg = <0x0 0xfe660000 0x0 0x20000>;
-- msi-controller;
-- #msi-cells = <1>;
-- };
--
-- ppi-partitions {
-- ppi_partition0: interrupt-partition-0 {
-- affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
-- };
--
-- ppi_partition1: interrupt-partition-1 {
-- affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
-- };
-- };
-- };
--
-- dmac0: dma-controller@fea10000 {
-- compatible = "arm,pl330", "arm,primecell";
-- reg = <0x0 0xfea10000 0x0 0x4000>;
-- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
-- arm,pl330-periph-burst;
-- clocks = <&cru ACLK_DMAC0>;
-- clock-names = "apb_pclk";
-- #dma-cells = <1>;
-- };
--
-- dmac1: dma-controller@fea30000 {
-- compatible = "arm,pl330", "arm,primecell";
-- reg = <0x0 0xfea30000 0x0 0x4000>;
-- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
-- arm,pl330-periph-burst;
-- clocks = <&cru ACLK_DMAC1>;
-- clock-names = "apb_pclk";
-- #dma-cells = <1>;
-- };
--
-- i2c1: i2c@fea90000 {
-- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-- reg = <0x0 0xfea90000 0x0 0x1000>;
-- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
-- clock-names = "i2c", "pclk";
-- interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
-- pinctrl-0 = <&i2c1m0_xfer>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- i2c2: i2c@feaa0000 {
-- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-- reg = <0x0 0xfeaa0000 0x0 0x1000>;
-- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
-- clock-names = "i2c", "pclk";
-- interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
-- pinctrl-0 = <&i2c2m0_xfer>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- i2c3: i2c@feab0000 {
-- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-- reg = <0x0 0xfeab0000 0x0 0x1000>;
-- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
-- clock-names = "i2c", "pclk";
-- interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
-- pinctrl-0 = <&i2c3m0_xfer>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- i2c4: i2c@feac0000 {
-- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-- reg = <0x0 0xfeac0000 0x0 0x1000>;
-- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
-- clock-names = "i2c", "pclk";
-- interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
-- pinctrl-0 = <&i2c4m0_xfer>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- i2c5: i2c@fead0000 {
-- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-- reg = <0x0 0xfead0000 0x0 0x1000>;
-- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
-- clock-names = "i2c", "pclk";
-- interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
-- pinctrl-0 = <&i2c5m0_xfer>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- timer0: timer@feae0000 {
-- compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
-- reg = <0x0 0xfeae0000 0x0 0x20>;
-- interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
-- clock-names = "pclk", "timer";
-- };
--
-- wdt: watchdog@feaf0000 {
-- compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
-- reg = <0x0 0xfeaf0000 0x0 0x100>;
-- clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
-- clock-names = "tclk", "pclk";
-- interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
-- };
--
-- spi0: spi@feb00000 {
-- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-- reg = <0x0 0xfeb00000 0x0 0x1000>;
-- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
-- clock-names = "spiclk", "apb_pclk";
-- dmas = <&dmac0 14>, <&dmac0 15>;
-- dma-names = "tx", "rx";
-- num-cs = <2>;
-- pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- spi1: spi@feb10000 {
-- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-- reg = <0x0 0xfeb10000 0x0 0x1000>;
-- interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
-- clock-names = "spiclk", "apb_pclk";
-- dmas = <&dmac0 16>, <&dmac0 17>;
-- dma-names = "tx", "rx";
-- num-cs = <2>;
-- pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- spi2: spi@feb20000 {
-- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-- reg = <0x0 0xfeb20000 0x0 0x1000>;
-- interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
-- clock-names = "spiclk", "apb_pclk";
-- dmas = <&dmac1 15>, <&dmac1 16>;
-- dma-names = "tx", "rx";
-- num-cs = <2>;
-- pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- spi3: spi@feb30000 {
-- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-- reg = <0x0 0xfeb30000 0x0 0x1000>;
-- interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
-- clock-names = "spiclk", "apb_pclk";
-- dmas = <&dmac1 17>, <&dmac1 18>;
-- dma-names = "tx", "rx";
-- num-cs = <2>;
-- pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- uart1: serial@feb40000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfeb40000 0x0 0x100>;
-- interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac0 8>, <&dmac0 9>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart1m1_xfer>;
-- pinctrl-names = "default";
-- reg-io-width = <4>;
-- reg-shift = <2>;
-- status = "disabled";
-- };
--
-- uart2: serial@feb50000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfeb50000 0x0 0x100>;
-- interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac0 10>, <&dmac0 11>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart2m1_xfer>;
-- pinctrl-names = "default";
-- reg-io-width = <4>;
-- reg-shift = <2>;
-- status = "disabled";
-- };
--
-- uart3: serial@feb60000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfeb60000 0x0 0x100>;
-- interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac0 12>, <&dmac0 13>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart3m1_xfer>;
-- pinctrl-names = "default";
-- reg-io-width = <4>;
-- reg-shift = <2>;
-- status = "disabled";
-- };
--
-- uart4: serial@feb70000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfeb70000 0x0 0x100>;
-- interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac1 9>, <&dmac1 10>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart4m1_xfer>;
-- pinctrl-names = "default";
-- reg-io-width = <4>;
-- reg-shift = <2>;
-- status = "disabled";
-- };
--
-- uart5: serial@feb80000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfeb80000 0x0 0x100>;
-- interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac1 11>, <&dmac1 12>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart5m1_xfer>;
-- pinctrl-names = "default";
-- reg-io-width = <4>;
-- reg-shift = <2>;
-- status = "disabled";
-- };
--
-- uart6: serial@feb90000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfeb90000 0x0 0x100>;
-- interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac1 13>, <&dmac1 14>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart6m1_xfer>;
-- pinctrl-names = "default";
-- reg-io-width = <4>;
-- reg-shift = <2>;
-- status = "disabled";
-- };
--
-- uart7: serial@feba0000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfeba0000 0x0 0x100>;
-- interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac2 7>, <&dmac2 8>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart7m1_xfer>;
-- pinctrl-names = "default";
-- reg-io-width = <4>;
-- reg-shift = <2>;
-- status = "disabled";
-- };
--
-- uart8: serial@febb0000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfebb0000 0x0 0x100>;
-- interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac2 9>, <&dmac2 10>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart8m1_xfer>;
-- pinctrl-names = "default";
-- reg-io-width = <4>;
-- reg-shift = <2>;
-- status = "disabled";
-- };
--
-- uart9: serial@febc0000 {
-- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
-- reg = <0x0 0xfebc0000 0x0 0x100>;
-- interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
-- clock-names = "baudclk", "apb_pclk";
-- dmas = <&dmac2 11>, <&dmac2 12>;
-- dma-names = "tx", "rx";
-- pinctrl-0 = <&uart9m1_xfer>;
-- pinctrl-names = "default";
-- reg-io-width = <4>;
-- reg-shift = <2>;
-- status = "disabled";
-- };
--
-- pwm4: pwm@febd0000 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebd0000 0x0 0x10>;
-- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm4m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm5: pwm@febd0010 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebd0010 0x0 0x10>;
-- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm5m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm6: pwm@febd0020 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebd0020 0x0 0x10>;
-- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm6m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm7: pwm@febd0030 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebd0030 0x0 0x10>;
-- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm7m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm8: pwm@febe0000 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebe0000 0x0 0x10>;
-- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm8m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm9: pwm@febe0010 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebe0010 0x0 0x10>;
-- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm9m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm10: pwm@febe0020 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebe0020 0x0 0x10>;
-- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm10m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm11: pwm@febe0030 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebe0030 0x0 0x10>;
-- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm11m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm12: pwm@febf0000 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebf0000 0x0 0x10>;
-- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm12m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm13: pwm@febf0010 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebf0010 0x0 0x10>;
-- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm13m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm14: pwm@febf0020 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebf0020 0x0 0x10>;
-- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm14m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- pwm15: pwm@febf0030 {
-- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
-- reg = <0x0 0xfebf0030 0x0 0x10>;
-- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
-- clock-names = "pwm", "pclk";
-- pinctrl-0 = <&pwm15m0_pins>;
-- pinctrl-names = "default";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- tsadc: tsadc@fec00000 {
-- compatible = "rockchip,rk3588-tsadc";
-- reg = <0x0 0xfec00000 0x0 0x400>;
-- interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
-- clock-names = "tsadc", "apb_pclk";
-- assigned-clocks = <&cru CLK_TSADC>;
-- assigned-clock-rates = <2000000>;
-- resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
-- reset-names = "tsadc-apb", "tsadc";
-- rockchip,hw-tshut-temp = <120000>;
-- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
-- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
-- pinctrl-0 = <&tsadc_gpio_func>;
-- pinctrl-1 = <&tsadc_shut>;
-- pinctrl-names = "gpio", "otpout";
-- #thermal-sensor-cells = <1>;
-- status = "disabled";
-- };
--
-- saradc: adc@fec10000 {
-- compatible = "rockchip,rk3588-saradc";
-- reg = <0x0 0xfec10000 0x0 0x10000>;
-- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
-- #io-channel-cells = <1>;
-- clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
-- clock-names = "saradc", "apb_pclk";
-- resets = <&cru SRST_P_SARADC>;
-- reset-names = "saradc-apb";
-- status = "disabled";
-- };
--
-- i2c6: i2c@fec80000 {
-- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-- reg = <0x0 0xfec80000 0x0 0x1000>;
-- clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
-- clock-names = "i2c", "pclk";
-- interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
-- pinctrl-0 = <&i2c6m0_xfer>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- i2c7: i2c@fec90000 {
-- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-- reg = <0x0 0xfec90000 0x0 0x1000>;
-- clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
-- clock-names = "i2c", "pclk";
-- interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
-- pinctrl-0 = <&i2c7m0_xfer>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- i2c8: i2c@feca0000 {
-- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
-- reg = <0x0 0xfeca0000 0x0 0x1000>;
-- clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
-- clock-names = "i2c", "pclk";
-- interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
-- pinctrl-0 = <&i2c8m0_xfer>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- spi4: spi@fecb0000 {
-- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
-- reg = <0x0 0xfecb0000 0x0 0x1000>;
-- interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
-- clock-names = "spiclk", "apb_pclk";
-- dmas = <&dmac2 13>, <&dmac2 14>;
-- dma-names = "tx", "rx";
-- num-cs = <2>;
-- pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
-- pinctrl-names = "default";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
-- };
--
-- otp: efuse@fecc0000 {
-- compatible = "rockchip,rk3588-otp";
-- reg = <0x0 0xfecc0000 0x0 0x400>;
-- clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
-- <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
-- clock-names = "otp", "apb_pclk", "phy", "arb";
-- resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
-- <&cru SRST_OTPC_ARB>;
-- reset-names = "otp", "apb", "arb";
-- #address-cells = <1>;
-- #size-cells = <1>;
--
-- cpu_code: cpu-code@2 {
-- reg = <0x02 0x2>;
-- };
--
-- otp_id: id@7 {
-- reg = <0x07 0x10>;
-- };
--
-- cpub0_leakage: cpu-leakage@17 {
-- reg = <0x17 0x1>;
-- };
--
-- cpub1_leakage: cpu-leakage@18 {
-- reg = <0x18 0x1>;
-- };
--
-- cpul_leakage: cpu-leakage@19 {
-- reg = <0x19 0x1>;
-- };
--
-- log_leakage: log-leakage@1a {
-- reg = <0x1a 0x1>;
-- };
--
-- gpu_leakage: gpu-leakage@1b {
-- reg = <0x1b 0x1>;
-- };
--
-- otp_cpu_version: cpu-version@1c {
-- reg = <0x1c 0x1>;
-- bits = <3 3>;
-- };
--
-- npu_leakage: npu-leakage@28 {
-- reg = <0x28 0x1>;
-- };
--
-- codec_leakage: codec-leakage@29 {
-- reg = <0x29 0x1>;
-- };
-- };
--
-- dmac2: dma-controller@fed10000 {
-- compatible = "arm,pl330", "arm,primecell";
-- reg = <0x0 0xfed10000 0x0 0x4000>;
-- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
-- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
-- arm,pl330-periph-burst;
-- clocks = <&cru ACLK_DMAC2>;
-- clock-names = "apb_pclk";
-- #dma-cells = <1>;
-- };
--
-- hdptxphy_hdmi0: phy@fed60000 {
-- compatible = "rockchip,rk3588-hdptx-phy";
-- reg = <0x0 0xfed60000 0x0 0x2000>;
-- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
-- clock-names = "ref", "apb";
-- #phy-cells = <0>;
-- resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
-- <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
-- <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
-- <&cru SRST_HDPTX0_LCPLL>;
-- reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
-- "lcpll";
-- rockchip,grf = <&hdptxphy0_grf>;
-- status = "disabled";
-- };
--
-- usbdp_phy0: phy@fed80000 {
-- compatible = "rockchip,rk3588-usbdp-phy";
-- reg = <0x0 0xfed80000 0x0 0x10000>;
-- #phy-cells = <1>;
-- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
-- <&cru CLK_USBDP_PHY0_IMMORTAL>,
-- <&cru PCLK_USBDPPHY0>,
-- <&u2phy0>;
-- clock-names = "refclk", "immortal", "pclk", "utmi";
-- resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
-- <&cru SRST_USBDP_COMBO_PHY0_CMN>,
-- <&cru SRST_USBDP_COMBO_PHY0_LANE>,
-- <&cru SRST_USBDP_COMBO_PHY0_PCS>,
-- <&cru SRST_P_USBDPPHY0>;
-- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
-- rockchip,u2phy-grf = <&usb2phy0_grf>;
-- rockchip,usb-grf = <&usb_grf>;
-- rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
-- rockchip,vo-grf = <&vo0_grf>;
-- status = "disabled";
-- };
--
-- combphy0_ps: phy@fee00000 {
-- compatible = "rockchip,rk3588-naneng-combphy";
-- reg = <0x0 0xfee00000 0x0 0x100>;
-- clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
-- <&cru PCLK_PHP_ROOT>;
-- clock-names = "ref", "apb", "pipe";
-- assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
-- assigned-clock-rates = <100000000>;
-- #phy-cells = <1>;
-- resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
-- reset-names = "phy", "apb";
-- rockchip,pipe-grf = <&php_grf>;
-- rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
-- status = "disabled";
-- };
--
-- combphy2_psu: phy@fee20000 {
-- compatible = "rockchip,rk3588-naneng-combphy";
-- reg = <0x0 0xfee20000 0x0 0x100>;
-- clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
-- <&cru PCLK_PHP_ROOT>;
-- clock-names = "ref", "apb", "pipe";
-- assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
-- assigned-clock-rates = <100000000>;
-- #phy-cells = <1>;
-- resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
-- reset-names = "phy", "apb";
-- rockchip,pipe-grf = <&php_grf>;
-- rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
-- status = "disabled";
-- };
--
-- system_sram2: sram@ff001000 {
-- compatible = "mmio-sram";
-- reg = <0x0 0xff001000 0x0 0xef000>;
-- ranges = <0x0 0x0 0xff001000 0xef000>;
-- #address-cells = <1>;
-- #size-cells = <1>;
-- };
--
-- pinctrl: pinctrl {
-- compatible = "rockchip,rk3588-pinctrl";
-- ranges;
-- rockchip,grf = <&ioc>;
-- #address-cells = <2>;
-- #size-cells = <2>;
--
-- gpio0: gpio@fd8a0000 {
-- compatible = "rockchip,gpio-bank";
-- reg = <0x0 0xfd8a0000 0x0 0x100>;
-- interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
-- gpio-controller;
-- gpio-ranges = <&pinctrl 0 0 32>;
-- interrupt-controller;
-- #gpio-cells = <2>;
-- #interrupt-cells = <2>;
-- };
--
-- gpio1: gpio@fec20000 {
-- compatible = "rockchip,gpio-bank";
-- reg = <0x0 0xfec20000 0x0 0x100>;
-- interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
-- gpio-controller;
-- gpio-ranges = <&pinctrl 0 32 32>;
-- interrupt-controller;
-- #gpio-cells = <2>;
-- #interrupt-cells = <2>;
-- };
--
-- gpio2: gpio@fec30000 {
-- compatible = "rockchip,gpio-bank";
-- reg = <0x0 0xfec30000 0x0 0x100>;
-- interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
-- gpio-controller;
-- gpio-ranges = <&pinctrl 0 64 32>;
-- interrupt-controller;
-- #gpio-cells = <2>;
-- #interrupt-cells = <2>;
-- };
--
-- gpio3: gpio@fec40000 {
-- compatible = "rockchip,gpio-bank";
-- reg = <0x0 0xfec40000 0x0 0x100>;
-- interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
-- gpio-controller;
-- gpio-ranges = <&pinctrl 0 96 32>;
-- interrupt-controller;
-- #gpio-cells = <2>;
-- #interrupt-cells = <2>;
-- };
--
-- gpio4: gpio@fec50000 {
-- compatible = "rockchip,gpio-bank";
-- reg = <0x0 0xfec50000 0x0 0x100>;
-- interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
-- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
-- gpio-controller;
-- gpio-ranges = <&pinctrl 0 128 32>;
-- interrupt-controller;
-- #gpio-cells = <2>;
-- #interrupt-cells = <2>;
-- };
-- };
--};
--
--#include "rk3588s-pinctrl.dtsi"
-+#include "rk3588-base.dtsi"
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
-@@ -0,0 +1,3447 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+ */
-+
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rockchip-pinconf.dtsi"
-+
-+/*
-+ * This file is auto generated by pin2dts tool, please keep these code
-+ * by adding changes at end of this file.
-+ */
-+&pinctrl {
-+ auddsm {
-+ /omit-if-no-ref/
-+ auddsm_pins: auddsm-pins {
-+ rockchip,pins =
-+ /* auddsm_ln */
-+ <3 RK_PA1 4 &pcfg_pull_none>,
-+ /* auddsm_lp */
-+ <3 RK_PA2 4 &pcfg_pull_none>,
-+ /* auddsm_rn */
-+ <3 RK_PA3 4 &pcfg_pull_none>,
-+ /* auddsm_rp */
-+ <3 RK_PA4 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ bt1120 {
-+ /omit-if-no-ref/
-+ bt1120_pins: bt1120-pins {
-+ rockchip,pins =
-+ /* bt1120_clkout */
-+ <4 RK_PB0 2 &pcfg_pull_none>,
-+ /* bt1120_d0 */
-+ <4 RK_PA0 2 &pcfg_pull_none>,
-+ /* bt1120_d1 */
-+ <4 RK_PA1 2 &pcfg_pull_none>,
-+ /* bt1120_d2 */
-+ <4 RK_PA2 2 &pcfg_pull_none>,
-+ /* bt1120_d3 */
-+ <4 RK_PA3 2 &pcfg_pull_none>,
-+ /* bt1120_d4 */
-+ <4 RK_PA4 2 &pcfg_pull_none>,
-+ /* bt1120_d5 */
-+ <4 RK_PA5 2 &pcfg_pull_none>,
-+ /* bt1120_d6 */
-+ <4 RK_PA6 2 &pcfg_pull_none>,
-+ /* bt1120_d7 */
-+ <4 RK_PA7 2 &pcfg_pull_none>,
-+ /* bt1120_d8 */
-+ <4 RK_PB2 2 &pcfg_pull_none>,
-+ /* bt1120_d9 */
-+ <4 RK_PB3 2 &pcfg_pull_none>,
-+ /* bt1120_d10 */
-+ <4 RK_PB4 2 &pcfg_pull_none>,
-+ /* bt1120_d11 */
-+ <4 RK_PB5 2 &pcfg_pull_none>,
-+ /* bt1120_d12 */
-+ <4 RK_PB6 2 &pcfg_pull_none>,
-+ /* bt1120_d13 */
-+ <4 RK_PB7 2 &pcfg_pull_none>,
-+ /* bt1120_d14 */
-+ <4 RK_PC0 2 &pcfg_pull_none>,
-+ /* bt1120_d15 */
-+ <4 RK_PC1 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ can0 {
-+ /omit-if-no-ref/
-+ can0m0_pins: can0m0-pins {
-+ rockchip,pins =
-+ /* can0_rx_m0 */
-+ <0 RK_PC0 11 &pcfg_pull_none>,
-+ /* can0_tx_m0 */
-+ <0 RK_PB7 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ can0m1_pins: can0m1-pins {
-+ rockchip,pins =
-+ /* can0_rx_m1 */
-+ <4 RK_PD5 9 &pcfg_pull_none>,
-+ /* can0_tx_m1 */
-+ <4 RK_PD4 9 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ can1 {
-+ /omit-if-no-ref/
-+ can1m0_pins: can1m0-pins {
-+ rockchip,pins =
-+ /* can1_rx_m0 */
-+ <3 RK_PB5 9 &pcfg_pull_none>,
-+ /* can1_tx_m0 */
-+ <3 RK_PB6 9 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ can1m1_pins: can1m1-pins {
-+ rockchip,pins =
-+ /* can1_rx_m1 */
-+ <4 RK_PB2 12 &pcfg_pull_none>,
-+ /* can1_tx_m1 */
-+ <4 RK_PB3 12 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ can2 {
-+ /omit-if-no-ref/
-+ can2m0_pins: can2m0-pins {
-+ rockchip,pins =
-+ /* can2_rx_m0 */
-+ <3 RK_PC4 9 &pcfg_pull_none>,
-+ /* can2_tx_m0 */
-+ <3 RK_PC5 9 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ can2m1_pins: can2m1-pins {
-+ rockchip,pins =
-+ /* can2_rx_m1 */
-+ <0 RK_PD4 10 &pcfg_pull_none>,
-+ /* can2_tx_m1 */
-+ <0 RK_PD5 10 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ cif {
-+ /omit-if-no-ref/
-+ cif_clk: cif-clk {
-+ rockchip,pins =
-+ /* cif_clkout */
-+ <4 RK_PB4 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ cif_dvp_clk: cif-dvp-clk {
-+ rockchip,pins =
-+ /* cif_clkin */
-+ <4 RK_PB0 1 &pcfg_pull_none>,
-+ /* cif_href */
-+ <4 RK_PB2 1 &pcfg_pull_none>,
-+ /* cif_vsync */
-+ <4 RK_PB3 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ cif_dvp_bus16: cif-dvp-bus16 {
-+ rockchip,pins =
-+ /* cif_d8 */
-+ <3 RK_PC4 1 &pcfg_pull_none>,
-+ /* cif_d9 */
-+ <3 RK_PC5 1 &pcfg_pull_none>,
-+ /* cif_d10 */
-+ <3 RK_PC6 1 &pcfg_pull_none>,
-+ /* cif_d11 */
-+ <3 RK_PC7 1 &pcfg_pull_none>,
-+ /* cif_d12 */
-+ <3 RK_PD0 1 &pcfg_pull_none>,
-+ /* cif_d13 */
-+ <3 RK_PD1 1 &pcfg_pull_none>,
-+ /* cif_d14 */
-+ <3 RK_PD2 1 &pcfg_pull_none>,
-+ /* cif_d15 */
-+ <3 RK_PD3 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ cif_dvp_bus8: cif-dvp-bus8 {
-+ rockchip,pins =
-+ /* cif_d0 */
-+ <4 RK_PA0 1 &pcfg_pull_none>,
-+ /* cif_d1 */
-+ <4 RK_PA1 1 &pcfg_pull_none>,
-+ /* cif_d2 */
-+ <4 RK_PA2 1 &pcfg_pull_none>,
-+ /* cif_d3 */
-+ <4 RK_PA3 1 &pcfg_pull_none>,
-+ /* cif_d4 */
-+ <4 RK_PA4 1 &pcfg_pull_none>,
-+ /* cif_d5 */
-+ <4 RK_PA5 1 &pcfg_pull_none>,
-+ /* cif_d6 */
-+ <4 RK_PA6 1 &pcfg_pull_none>,
-+ /* cif_d7 */
-+ <4 RK_PA7 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ clk32k {
-+ /omit-if-no-ref/
-+ clk32k_in: clk32k-in {
-+ rockchip,pins =
-+ /* clk32k_in */
-+ <0 RK_PB2 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ clk32k_out0: clk32k-out0 {
-+ rockchip,pins =
-+ /* clk32k_out0 */
-+ <0 RK_PB2 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ cpu {
-+ /omit-if-no-ref/
-+ cpu_pins: cpu-pins {
-+ rockchip,pins =
-+ /* cpu_big0_avs */
-+ <0 RK_PD1 2 &pcfg_pull_none>,
-+ /* cpu_big1_avs */
-+ <0 RK_PD5 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ ddrphych0 {
-+ /omit-if-no-ref/
-+ ddrphych0_pins: ddrphych0-pins {
-+ rockchip,pins =
-+ /* ddrphych0_dtb0 */
-+ <4 RK_PA0 7 &pcfg_pull_none>,
-+ /* ddrphych0_dtb1 */
-+ <4 RK_PA1 7 &pcfg_pull_none>,
-+ /* ddrphych0_dtb2 */
-+ <4 RK_PA2 7 &pcfg_pull_none>,
-+ /* ddrphych0_dtb3 */
-+ <4 RK_PA3 7 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ ddrphych1 {
-+ /omit-if-no-ref/
-+ ddrphych1_pins: ddrphych1-pins {
-+ rockchip,pins =
-+ /* ddrphych1_dtb0 */
-+ <4 RK_PA4 7 &pcfg_pull_none>,
-+ /* ddrphych1_dtb1 */
-+ <4 RK_PA5 7 &pcfg_pull_none>,
-+ /* ddrphych1_dtb2 */
-+ <4 RK_PA6 7 &pcfg_pull_none>,
-+ /* ddrphych1_dtb3 */
-+ <4 RK_PA7 7 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ ddrphych2 {
-+ /omit-if-no-ref/
-+ ddrphych2_pins: ddrphych2-pins {
-+ rockchip,pins =
-+ /* ddrphych2_dtb0 */
-+ <4 RK_PB0 7 &pcfg_pull_none>,
-+ /* ddrphych2_dtb1 */
-+ <4 RK_PB1 7 &pcfg_pull_none>,
-+ /* ddrphych2_dtb2 */
-+ <4 RK_PB2 7 &pcfg_pull_none>,
-+ /* ddrphych2_dtb3 */
-+ <4 RK_PB3 7 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ ddrphych3 {
-+ /omit-if-no-ref/
-+ ddrphych3_pins: ddrphych3-pins {
-+ rockchip,pins =
-+ /* ddrphych3_dtb0 */
-+ <4 RK_PB4 7 &pcfg_pull_none>,
-+ /* ddrphych3_dtb1 */
-+ <4 RK_PB5 7 &pcfg_pull_none>,
-+ /* ddrphych3_dtb2 */
-+ <4 RK_PB6 7 &pcfg_pull_none>,
-+ /* ddrphych3_dtb3 */
-+ <4 RK_PB7 7 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ dp0 {
-+ /omit-if-no-ref/
-+ dp0m0_pins: dp0m0-pins {
-+ rockchip,pins =
-+ /* dp0_hpdin_m0 */
-+ <4 RK_PB4 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ dp0m1_pins: dp0m1-pins {
-+ rockchip,pins =
-+ /* dp0_hpdin_m1 */
-+ <0 RK_PC4 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ dp0m2_pins: dp0m2-pins {
-+ rockchip,pins =
-+ /* dp0_hpdin_m2 */
-+ <1 RK_PA0 5 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ dp1 {
-+ /omit-if-no-ref/
-+ dp1m0_pins: dp1m0-pins {
-+ rockchip,pins =
-+ /* dp1_hpdin_m0 */
-+ <3 RK_PD5 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ dp1m1_pins: dp1m1-pins {
-+ rockchip,pins =
-+ /* dp1_hpdin_m1 */
-+ <0 RK_PC5 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ dp1m2_pins: dp1m2-pins {
-+ rockchip,pins =
-+ /* dp1_hpdin_m2 */
-+ <1 RK_PA1 5 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ emmc {
-+ /omit-if-no-ref/
-+ emmc_rstnout: emmc-rstnout {
-+ rockchip,pins =
-+ /* emmc_rstn */
-+ <2 RK_PA3 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ emmc_bus8: emmc-bus8 {
-+ rockchip,pins =
-+ /* emmc_d0 */
-+ <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
-+ /* emmc_d1 */
-+ <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
-+ /* emmc_d2 */
-+ <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
-+ /* emmc_d3 */
-+ <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
-+ /* emmc_d4 */
-+ <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
-+ /* emmc_d5 */
-+ <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
-+ /* emmc_d6 */
-+ <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
-+ /* emmc_d7 */
-+ <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ emmc_clk: emmc-clk {
-+ rockchip,pins =
-+ /* emmc_clkout */
-+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ emmc_cmd: emmc-cmd {
-+ rockchip,pins =
-+ /* emmc_cmd */
-+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ emmc_data_strobe: emmc-data-strobe {
-+ rockchip,pins =
-+ /* emmc_data_strobe */
-+ <2 RK_PA2 1 &pcfg_pull_down>;
-+ };
-+ };
-+
-+ eth1 {
-+ /omit-if-no-ref/
-+ eth1_pins: eth1-pins {
-+ rockchip,pins =
-+ /* eth1_refclko_25m */
-+ <3 RK_PA6 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ fspi {
-+ /omit-if-no-ref/
-+ fspim0_pins: fspim0-pins {
-+ rockchip,pins =
-+ /* fspi_clk_m0 */
-+ <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_cs0n_m0 */
-+ <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d0_m0 */
-+ <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d1_m0 */
-+ <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d2_m0 */
-+ <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d3_m0 */
-+ <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ fspim0_cs1: fspim0-cs1 {
-+ rockchip,pins =
-+ /* fspi_cs1n_m0 */
-+ <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ fspim2_pins: fspim2-pins {
-+ rockchip,pins =
-+ /* fspi_clk_m2 */
-+ <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_cs0n_m2 */
-+ <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d0_m2 */
-+ <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d1_m2 */
-+ <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d2_m2 */
-+ <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d3_m2 */
-+ <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ fspim2_cs1: fspim2-cs1 {
-+ rockchip,pins =
-+ /* fspi_cs1n_m2 */
-+ <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
-+ };
-+ };
-+
-+ gmac1 {
-+ /omit-if-no-ref/
-+ gmac1_miim: gmac1-miim {
-+ rockchip,pins =
-+ /* gmac1_mdc */
-+ <3 RK_PC2 1 &pcfg_pull_none>,
-+ /* gmac1_mdio */
-+ <3 RK_PC3 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac1_clkinout: gmac1-clkinout {
-+ rockchip,pins =
-+ /* gmac1_mclkinout */
-+ <3 RK_PB6 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac1_rx_bus2: gmac1-rx-bus2 {
-+ rockchip,pins =
-+ /* gmac1_rxd0 */
-+ <3 RK_PA7 1 &pcfg_pull_none>,
-+ /* gmac1_rxd1 */
-+ <3 RK_PB0 1 &pcfg_pull_none>,
-+ /* gmac1_rxdv_crs */
-+ <3 RK_PB1 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac1_tx_bus2: gmac1-tx-bus2 {
-+ rockchip,pins =
-+ /* gmac1_txd0 */
-+ <3 RK_PB3 1 &pcfg_pull_none>,
-+ /* gmac1_txd1 */
-+ <3 RK_PB4 1 &pcfg_pull_none>,
-+ /* gmac1_txen */
-+ <3 RK_PB5 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac1_rgmii_clk: gmac1-rgmii-clk {
-+ rockchip,pins =
-+ /* gmac1_rxclk */
-+ <3 RK_PA5 1 &pcfg_pull_none>,
-+ /* gmac1_txclk */
-+ <3 RK_PA4 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac1_rgmii_bus: gmac1-rgmii-bus {
-+ rockchip,pins =
-+ /* gmac1_rxd2 */
-+ <3 RK_PA2 1 &pcfg_pull_none>,
-+ /* gmac1_rxd3 */
-+ <3 RK_PA3 1 &pcfg_pull_none>,
-+ /* gmac1_txd2 */
-+ <3 RK_PA0 1 &pcfg_pull_none>,
-+ /* gmac1_txd3 */
-+ <3 RK_PA1 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac1_ppsclk: gmac1-ppsclk {
-+ rockchip,pins =
-+ /* gmac1_ppsclk */
-+ <3 RK_PC1 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac1_ppstrig: gmac1-ppstrig {
-+ rockchip,pins =
-+ /* gmac1_ppstrig */
-+ <3 RK_PC0 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
-+ rockchip,pins =
-+ /* gmac1_ptp_ref_clk */
-+ <3 RK_PB7 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac1_txer: gmac1-txer {
-+ rockchip,pins =
-+ /* gmac1_txer */
-+ <3 RK_PB2 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ gpu {
-+ /omit-if-no-ref/
-+ gpu_pins: gpu-pins {
-+ rockchip,pins =
-+ /* gpu_avs */
-+ <0 RK_PC5 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ hdmi {
-+ /omit-if-no-ref/
-+ hdmim0_rx_cec: hdmim0-rx-cec {
-+ rockchip,pins =
-+ /* hdmim0_rx_cec */
-+ <4 RK_PB5 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_rx_hpdin: hdmim0-rx-hpdin {
-+ rockchip,pins =
-+ /* hdmim0_rx_hpdin */
-+ <4 RK_PB6 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_rx_scl: hdmim0-rx-scl {
-+ rockchip,pins =
-+ /* hdmim0_rx_scl */
-+ <0 RK_PD2 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_rx_sda: hdmim0-rx-sda {
-+ rockchip,pins =
-+ /* hdmim0_rx_sda */
-+ <0 RK_PD1 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_tx0_cec: hdmim0-tx0-cec {
-+ rockchip,pins =
-+ /* hdmim0_tx0_cec */
-+ <4 RK_PC1 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_tx0_hpd: hdmim0-tx0-hpd {
-+ rockchip,pins =
-+ /* hdmim0_tx0_hpd */
-+ <1 RK_PA5 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_tx0_scl: hdmim0-tx0-scl {
-+ rockchip,pins =
-+ /* hdmim0_tx0_scl */
-+ <4 RK_PB7 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_tx0_sda: hdmim0-tx0-sda {
-+ rockchip,pins =
-+ /* hdmim0_tx0_sda */
-+ <4 RK_PC0 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_tx1_hpd: hdmim0-tx1-hpd {
-+ rockchip,pins =
-+ /* hdmim0_tx1_hpd */
-+ <1 RK_PA6 5 &pcfg_pull_none>;
-+ };
-+ /omit-if-no-ref/
-+ hdmim1_rx_cec: hdmim1-rx-cec {
-+ rockchip,pins =
-+ /* hdmim1_rx_cec */
-+ <3 RK_PD1 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_rx_hpdin: hdmim1-rx-hpdin {
-+ rockchip,pins =
-+ /* hdmim1_rx_hpdin */
-+ <3 RK_PD4 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_rx_scl: hdmim1-rx-scl {
-+ rockchip,pins =
-+ /* hdmim1_rx_scl */
-+ <3 RK_PD2 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_rx_sda: hdmim1-rx-sda {
-+ rockchip,pins =
-+ /* hdmim1_rx_sda */
-+ <3 RK_PD3 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_tx0_cec: hdmim1-tx0-cec {
-+ rockchip,pins =
-+ /* hdmim1_tx0_cec */
-+ <0 RK_PD1 13 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_tx0_hpd: hdmim1-tx0-hpd {
-+ rockchip,pins =
-+ /* hdmim1_tx0_hpd */
-+ <3 RK_PD4 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_tx0_scl: hdmim1-tx0-scl {
-+ rockchip,pins =
-+ /* hdmim1_tx0_scl */
-+ <0 RK_PD5 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_tx0_sda: hdmim1-tx0-sda {
-+ rockchip,pins =
-+ /* hdmim1_tx0_sda */
-+ <0 RK_PD4 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_tx1_cec: hdmim1-tx1-cec {
-+ rockchip,pins =
-+ /* hdmim1_tx1_cec */
-+ <0 RK_PD2 13 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_tx1_hpd: hdmim1-tx1-hpd {
-+ rockchip,pins =
-+ /* hdmim1_tx1_hpd */
-+ <3 RK_PB7 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_tx1_scl: hdmim1-tx1-scl {
-+ rockchip,pins =
-+ /* hdmim1_tx1_scl */
-+ <3 RK_PC6 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim1_tx1_sda: hdmim1-tx1-sda {
-+ rockchip,pins =
-+ /* hdmim1_tx1_sda */
-+ <3 RK_PC5 5 &pcfg_pull_none>;
-+ };
-+ /omit-if-no-ref/
-+ hdmim2_rx_cec: hdmim2-rx-cec {
-+ rockchip,pins =
-+ /* hdmim2_rx_cec */
-+ <1 RK_PB7 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim2_rx_hpdin: hdmim2-rx-hpdin {
-+ rockchip,pins =
-+ /* hdmim2_rx_hpdin */
-+ <1 RK_PB6 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim2_rx_scl: hdmim2-rx-scl {
-+ rockchip,pins =
-+ /* hdmim2_rx_scl */
-+ <1 RK_PD6 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim2_rx_sda: hdmim2-rx-sda {
-+ rockchip,pins =
-+ /* hdmim2_rx_sda */
-+ <1 RK_PD7 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim2_tx0_scl: hdmim2-tx0-scl {
-+ rockchip,pins =
-+ /* hdmim2_tx0_scl */
-+ <3 RK_PC7 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim2_tx0_sda: hdmim2-tx0-sda {
-+ rockchip,pins =
-+ /* hdmim2_tx0_sda */
-+ <3 RK_PD0 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim2_tx1_cec: hdmim2-tx1-cec {
-+ rockchip,pins =
-+ /* hdmim2_tx1_cec */
-+ <3 RK_PC4 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim2_tx1_scl: hdmim2-tx1-scl {
-+ rockchip,pins =
-+ /* hdmim2_tx1_scl */
-+ <1 RK_PA4 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim2_tx1_sda: hdmim2-tx1-sda {
-+ rockchip,pins =
-+ /* hdmim2_tx1_sda */
-+ <1 RK_PA3 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmi_debug0: hdmi-debug0 {
-+ rockchip,pins =
-+ /* hdmi_debug0 */
-+ <1 RK_PA7 7 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmi_debug1: hdmi-debug1 {
-+ rockchip,pins =
-+ /* hdmi_debug1 */
-+ <1 RK_PB0 7 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmi_debug2: hdmi-debug2 {
-+ rockchip,pins =
-+ /* hdmi_debug2 */
-+ <1 RK_PB1 7 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmi_debug3: hdmi-debug3 {
-+ rockchip,pins =
-+ /* hdmi_debug3 */
-+ <1 RK_PB2 7 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmi_debug4: hdmi-debug4 {
-+ rockchip,pins =
-+ /* hdmi_debug4 */
-+ <1 RK_PB3 7 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmi_debug5: hdmi-debug5 {
-+ rockchip,pins =
-+ /* hdmi_debug5 */
-+ <1 RK_PB4 7 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmi_debug6: hdmi-debug6 {
-+ rockchip,pins =
-+ /* hdmi_debug6 */
-+ <1 RK_PA0 7 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ i2c0 {
-+ /omit-if-no-ref/
-+ i2c0m0_xfer: i2c0m0-xfer {
-+ rockchip,pins =
-+ /* i2c0_scl_m0 */
-+ <0 RK_PB3 2 &pcfg_pull_none_smt>,
-+ /* i2c0_sda_m0 */
-+ <0 RK_PA6 2 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c0m2_xfer: i2c0m2-xfer {
-+ rockchip,pins =
-+ /* i2c0_scl_m2 */
-+ <0 RK_PD1 3 &pcfg_pull_none_smt>,
-+ /* i2c0_sda_m2 */
-+ <0 RK_PD2 3 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c1 {
-+ /omit-if-no-ref/
-+ i2c1m0_xfer: i2c1m0-xfer {
-+ rockchip,pins =
-+ /* i2c1_scl_m0 */
-+ <0 RK_PB5 9 &pcfg_pull_none_smt>,
-+ /* i2c1_sda_m0 */
-+ <0 RK_PB6 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c1m1_xfer: i2c1m1-xfer {
-+ rockchip,pins =
-+ /* i2c1_scl_m1 */
-+ <0 RK_PB0 2 &pcfg_pull_none_smt>,
-+ /* i2c1_sda_m1 */
-+ <0 RK_PB1 2 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c1m2_xfer: i2c1m2-xfer {
-+ rockchip,pins =
-+ /* i2c1_scl_m2 */
-+ <0 RK_PD4 9 &pcfg_pull_none_smt>,
-+ /* i2c1_sda_m2 */
-+ <0 RK_PD5 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c1m3_xfer: i2c1m3-xfer {
-+ rockchip,pins =
-+ /* i2c1_scl_m3 */
-+ <2 RK_PD4 9 &pcfg_pull_none_smt>,
-+ /* i2c1_sda_m3 */
-+ <2 RK_PD5 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c1m4_xfer: i2c1m4-xfer {
-+ rockchip,pins =
-+ /* i2c1_scl_m4 */
-+ <1 RK_PD2 9 &pcfg_pull_none_smt>,
-+ /* i2c1_sda_m4 */
-+ <1 RK_PD3 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c2 {
-+ /omit-if-no-ref/
-+ i2c2m0_xfer: i2c2m0-xfer {
-+ rockchip,pins =
-+ /* i2c2_scl_m0 */
-+ <0 RK_PB7 9 &pcfg_pull_none_smt>,
-+ /* i2c2_sda_m0 */
-+ <0 RK_PC0 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c2m2_xfer: i2c2m2-xfer {
-+ rockchip,pins =
-+ /* i2c2_scl_m2 */
-+ <2 RK_PA3 9 &pcfg_pull_none_smt>,
-+ /* i2c2_sda_m2 */
-+ <2 RK_PA2 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c2m3_xfer: i2c2m3-xfer {
-+ rockchip,pins =
-+ /* i2c2_scl_m3 */
-+ <1 RK_PC5 9 &pcfg_pull_none_smt>,
-+ /* i2c2_sda_m3 */
-+ <1 RK_PC4 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c2m4_xfer: i2c2m4-xfer {
-+ rockchip,pins =
-+ /* i2c2_scl_m4 */
-+ <1 RK_PA1 9 &pcfg_pull_none_smt>,
-+ /* i2c2_sda_m4 */
-+ <1 RK_PA0 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c3 {
-+ /omit-if-no-ref/
-+ i2c3m0_xfer: i2c3m0-xfer {
-+ rockchip,pins =
-+ /* i2c3_scl_m0 */
-+ <1 RK_PC1 9 &pcfg_pull_none_smt>,
-+ /* i2c3_sda_m0 */
-+ <1 RK_PC0 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c3m1_xfer: i2c3m1-xfer {
-+ rockchip,pins =
-+ /* i2c3_scl_m1 */
-+ <3 RK_PB7 9 &pcfg_pull_none_smt>,
-+ /* i2c3_sda_m1 */
-+ <3 RK_PC0 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c3m2_xfer: i2c3m2-xfer {
-+ rockchip,pins =
-+ /* i2c3_scl_m2 */
-+ <4 RK_PA4 9 &pcfg_pull_none_smt>,
-+ /* i2c3_sda_m2 */
-+ <4 RK_PA5 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c3m4_xfer: i2c3m4-xfer {
-+ rockchip,pins =
-+ /* i2c3_scl_m4 */
-+ <4 RK_PD0 9 &pcfg_pull_none_smt>,
-+ /* i2c3_sda_m4 */
-+ <4 RK_PD1 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c4 {
-+ /omit-if-no-ref/
-+ i2c4m0_xfer: i2c4m0-xfer {
-+ rockchip,pins =
-+ /* i2c4_scl_m0 */
-+ <3 RK_PA6 9 &pcfg_pull_none_smt>,
-+ /* i2c4_sda_m0 */
-+ <3 RK_PA5 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c4m2_xfer: i2c4m2-xfer {
-+ rockchip,pins =
-+ /* i2c4_scl_m2 */
-+ <0 RK_PC5 9 &pcfg_pull_none_smt>,
-+ /* i2c4_sda_m2 */
-+ <0 RK_PC4 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c4m3_xfer: i2c4m3-xfer {
-+ rockchip,pins =
-+ /* i2c4_scl_m3 */
-+ <1 RK_PA3 9 &pcfg_pull_none_smt>,
-+ /* i2c4_sda_m3 */
-+ <1 RK_PA2 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c4m4_xfer: i2c4m4-xfer {
-+ rockchip,pins =
-+ /* i2c4_scl_m4 */
-+ <1 RK_PC7 9 &pcfg_pull_none_smt>,
-+ /* i2c4_sda_m4 */
-+ <1 RK_PC6 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c5 {
-+ /omit-if-no-ref/
-+ i2c5m0_xfer: i2c5m0-xfer {
-+ rockchip,pins =
-+ /* i2c5_scl_m0 */
-+ <3 RK_PC7 9 &pcfg_pull_none_smt>,
-+ /* i2c5_sda_m0 */
-+ <3 RK_PD0 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c5m1_xfer: i2c5m1-xfer {
-+ rockchip,pins =
-+ /* i2c5_scl_m1 */
-+ <4 RK_PB6 9 &pcfg_pull_none_smt>,
-+ /* i2c5_sda_m1 */
-+ <4 RK_PB7 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c5m2_xfer: i2c5m2-xfer {
-+ rockchip,pins =
-+ /* i2c5_scl_m2 */
-+ <4 RK_PA6 9 &pcfg_pull_none_smt>,
-+ /* i2c5_sda_m2 */
-+ <4 RK_PA7 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c5m3_xfer: i2c5m3-xfer {
-+ rockchip,pins =
-+ /* i2c5_scl_m3 */
-+ <1 RK_PB6 9 &pcfg_pull_none_smt>,
-+ /* i2c5_sda_m3 */
-+ <1 RK_PB7 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c6 {
-+ /omit-if-no-ref/
-+ i2c6m0_xfer: i2c6m0-xfer {
-+ rockchip,pins =
-+ /* i2c6_scl_m0 */
-+ <0 RK_PD0 9 &pcfg_pull_none_smt>,
-+ /* i2c6_sda_m0 */
-+ <0 RK_PC7 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c6m1_xfer: i2c6m1-xfer {
-+ rockchip,pins =
-+ /* i2c6_scl_m1 */
-+ <1 RK_PC3 9 &pcfg_pull_none_smt>,
-+ /* i2c6_sda_m1 */
-+ <1 RK_PC2 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c6m3_xfer: i2c6m3-xfer {
-+ rockchip,pins =
-+ /* i2c6_scl_m3 */
-+ <4 RK_PB1 9 &pcfg_pull_none_smt>,
-+ /* i2c6_sda_m3 */
-+ <4 RK_PB0 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c6m4_xfer: i2c6m4-xfer {
-+ rockchip,pins =
-+ /* i2c6_scl_m4 */
-+ <3 RK_PA1 9 &pcfg_pull_none_smt>,
-+ /* i2c6_sda_m4 */
-+ <3 RK_PA0 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c7 {
-+ /omit-if-no-ref/
-+ i2c7m0_xfer: i2c7m0-xfer {
-+ rockchip,pins =
-+ /* i2c7_scl_m0 */
-+ <1 RK_PD0 9 &pcfg_pull_none_smt>,
-+ /* i2c7_sda_m0 */
-+ <1 RK_PD1 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c7m2_xfer: i2c7m2-xfer {
-+ rockchip,pins =
-+ /* i2c7_scl_m2 */
-+ <3 RK_PD2 9 &pcfg_pull_none_smt>,
-+ /* i2c7_sda_m2 */
-+ <3 RK_PD3 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c7m3_xfer: i2c7m3-xfer {
-+ rockchip,pins =
-+ /* i2c7_scl_m3 */
-+ <4 RK_PB2 9 &pcfg_pull_none_smt>,
-+ /* i2c7_sda_m3 */
-+ <4 RK_PB3 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c8 {
-+ /omit-if-no-ref/
-+ i2c8m0_xfer: i2c8m0-xfer {
-+ rockchip,pins =
-+ /* i2c8_scl_m0 */
-+ <4 RK_PD2 9 &pcfg_pull_none_smt>,
-+ /* i2c8_sda_m0 */
-+ <4 RK_PD3 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c8m2_xfer: i2c8m2-xfer {
-+ rockchip,pins =
-+ /* i2c8_scl_m2 */
-+ <1 RK_PD6 9 &pcfg_pull_none_smt>,
-+ /* i2c8_sda_m2 */
-+ <1 RK_PD7 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c8m3_xfer: i2c8m3-xfer {
-+ rockchip,pins =
-+ /* i2c8_scl_m3 */
-+ <4 RK_PC0 9 &pcfg_pull_none_smt>,
-+ /* i2c8_sda_m3 */
-+ <4 RK_PC1 9 &pcfg_pull_none_smt>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c8m4_xfer: i2c8m4-xfer {
-+ rockchip,pins =
-+ /* i2c8_scl_m4 */
-+ <3 RK_PC2 9 &pcfg_pull_none_smt>,
-+ /* i2c8_sda_m4 */
-+ <3 RK_PC3 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2s0 {
-+ /omit-if-no-ref/
-+ i2s0_lrck: i2s0-lrck {
-+ rockchip,pins =
-+ /* i2s0_lrck */
-+ <1 RK_PC5 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_mclk: i2s0-mclk {
-+ rockchip,pins =
-+ /* i2s0_mclk */
-+ <1 RK_PC2 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_sclk: i2s0-sclk {
-+ rockchip,pins =
-+ /* i2s0_sclk */
-+ <1 RK_PC3 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_sdi0: i2s0-sdi0 {
-+ rockchip,pins =
-+ /* i2s0_sdi0 */
-+ <1 RK_PD4 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_sdi1: i2s0-sdi1 {
-+ rockchip,pins =
-+ /* i2s0_sdi1 */
-+ <1 RK_PD3 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_sdi2: i2s0-sdi2 {
-+ rockchip,pins =
-+ /* i2s0_sdi2 */
-+ <1 RK_PD2 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_sdi3: i2s0-sdi3 {
-+ rockchip,pins =
-+ /* i2s0_sdi3 */
-+ <1 RK_PD1 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_sdo0: i2s0-sdo0 {
-+ rockchip,pins =
-+ /* i2s0_sdo0 */
-+ <1 RK_PC7 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_sdo1: i2s0-sdo1 {
-+ rockchip,pins =
-+ /* i2s0_sdo1 */
-+ <1 RK_PD0 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_sdo2: i2s0-sdo2 {
-+ rockchip,pins =
-+ /* i2s0_sdo2 */
-+ <1 RK_PD1 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s0_sdo3: i2s0-sdo3 {
-+ rockchip,pins =
-+ /* i2s0_sdo3 */
-+ <1 RK_PD2 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ i2s1 {
-+ /omit-if-no-ref/
-+ i2s1m0_lrck: i2s1m0-lrck {
-+ rockchip,pins =
-+ /* i2s1m0_lrck */
-+ <4 RK_PA2 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_mclk: i2s1m0-mclk {
-+ rockchip,pins =
-+ /* i2s1m0_mclk */
-+ <4 RK_PA0 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_sclk: i2s1m0-sclk {
-+ rockchip,pins =
-+ /* i2s1m0_sclk */
-+ <4 RK_PA1 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_sdi0: i2s1m0-sdi0 {
-+ rockchip,pins =
-+ /* i2s1m0_sdi0 */
-+ <4 RK_PA5 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_sdi1: i2s1m0-sdi1 {
-+ rockchip,pins =
-+ /* i2s1m0_sdi1 */
-+ <4 RK_PA6 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_sdi2: i2s1m0-sdi2 {
-+ rockchip,pins =
-+ /* i2s1m0_sdi2 */
-+ <4 RK_PA7 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_sdi3: i2s1m0-sdi3 {
-+ rockchip,pins =
-+ /* i2s1m0_sdi3 */
-+ <4 RK_PB0 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_sdo0: i2s1m0-sdo0 {
-+ rockchip,pins =
-+ /* i2s1m0_sdo0 */
-+ <4 RK_PB1 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_sdo1: i2s1m0-sdo1 {
-+ rockchip,pins =
-+ /* i2s1m0_sdo1 */
-+ <4 RK_PB2 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_sdo2: i2s1m0-sdo2 {
-+ rockchip,pins =
-+ /* i2s1m0_sdo2 */
-+ <4 RK_PB3 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m0_sdo3: i2s1m0-sdo3 {
-+ rockchip,pins =
-+ /* i2s1m0_sdo3 */
-+ <4 RK_PB4 3 &pcfg_pull_none>;
-+ };
-+ /omit-if-no-ref/
-+ i2s1m1_lrck: i2s1m1-lrck {
-+ rockchip,pins =
-+ /* i2s1m1_lrck */
-+ <0 RK_PB7 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_mclk: i2s1m1-mclk {
-+ rockchip,pins =
-+ /* i2s1m1_mclk */
-+ <0 RK_PB5 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_sclk: i2s1m1-sclk {
-+ rockchip,pins =
-+ /* i2s1m1_sclk */
-+ <0 RK_PB6 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_sdi0: i2s1m1-sdi0 {
-+ rockchip,pins =
-+ /* i2s1m1_sdi0 */
-+ <0 RK_PC5 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_sdi1: i2s1m1-sdi1 {
-+ rockchip,pins =
-+ /* i2s1m1_sdi1 */
-+ <0 RK_PC6 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_sdi2: i2s1m1-sdi2 {
-+ rockchip,pins =
-+ /* i2s1m1_sdi2 */
-+ <0 RK_PC7 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_sdi3: i2s1m1-sdi3 {
-+ rockchip,pins =
-+ /* i2s1m1_sdi3 */
-+ <0 RK_PD0 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_sdo0: i2s1m1-sdo0 {
-+ rockchip,pins =
-+ /* i2s1m1_sdo0 */
-+ <0 RK_PD1 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_sdo1: i2s1m1-sdo1 {
-+ rockchip,pins =
-+ /* i2s1m1_sdo1 */
-+ <0 RK_PD2 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_sdo2: i2s1m1-sdo2 {
-+ rockchip,pins =
-+ /* i2s1m1_sdo2 */
-+ <0 RK_PD4 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s1m1_sdo3: i2s1m1-sdo3 {
-+ rockchip,pins =
-+ /* i2s1m1_sdo3 */
-+ <0 RK_PD5 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ i2s2 {
-+ /omit-if-no-ref/
-+ i2s2m0_lrck: i2s2m0-lrck {
-+ rockchip,pins =
-+ /* i2s2m0_lrck */
-+ <2 RK_PC0 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_mclk: i2s2m0-mclk {
-+ rockchip,pins =
-+ /* i2s2m0_mclk */
-+ <2 RK_PB6 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_sclk: i2s2m0-sclk {
-+ rockchip,pins =
-+ /* i2s2m0_sclk */
-+ <2 RK_PB7 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_sdi: i2s2m0-sdi {
-+ rockchip,pins =
-+ /* i2s2m0_sdi */
-+ <2 RK_PC3 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_sdo: i2s2m0-sdo {
-+ rockchip,pins =
-+ /* i2s2m0_sdo */
-+ <4 RK_PC3 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m1_lrck: i2s2m1-lrck {
-+ rockchip,pins =
-+ /* i2s2m1_lrck */
-+ <3 RK_PB6 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m1_mclk: i2s2m1-mclk {
-+ rockchip,pins =
-+ /* i2s2m1_mclk */
-+ <3 RK_PB4 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m1_sclk: i2s2m1-sclk {
-+ rockchip,pins =
-+ /* i2s2m1_sclk */
-+ <3 RK_PB5 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m1_sdi: i2s2m1-sdi {
-+ rockchip,pins =
-+ /* i2s2m1_sdi */
-+ <3 RK_PB2 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m1_sdo: i2s2m1-sdo {
-+ rockchip,pins =
-+ /* i2s2m1_sdo */
-+ <3 RK_PB3 3 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ i2s3 {
-+ /omit-if-no-ref/
-+ i2s3_lrck: i2s3-lrck {
-+ rockchip,pins =
-+ /* i2s3_lrck */
-+ <3 RK_PA2 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s3_mclk: i2s3-mclk {
-+ rockchip,pins =
-+ /* i2s3_mclk */
-+ <3 RK_PA0 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s3_sclk: i2s3-sclk {
-+ rockchip,pins =
-+ /* i2s3_sclk */
-+ <3 RK_PA1 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s3_sdi: i2s3-sdi {
-+ rockchip,pins =
-+ /* i2s3_sdi */
-+ <3 RK_PA4 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s3_sdo: i2s3-sdo {
-+ rockchip,pins =
-+ /* i2s3_sdo */
-+ <3 RK_PA3 3 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ jtag {
-+ /omit-if-no-ref/
-+ jtagm0_pins: jtagm0-pins {
-+ rockchip,pins =
-+ /* jtag_tck_m0 */
-+ <4 RK_PD2 5 &pcfg_pull_none>,
-+ /* jtag_tms_m0 */
-+ <4 RK_PD3 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ jtagm1_pins: jtagm1-pins {
-+ rockchip,pins =
-+ /* jtag_tck_m1 */
-+ <4 RK_PD0 5 &pcfg_pull_none>,
-+ /* jtag_tms_m1 */
-+ <4 RK_PD1 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ jtagm2_pins: jtagm2-pins {
-+ rockchip,pins =
-+ /* jtag_tck_m2 */
-+ <0 RK_PB5 2 &pcfg_pull_none>,
-+ /* jtag_tms_m2 */
-+ <0 RK_PB6 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ litcpu {
-+ /omit-if-no-ref/
-+ litcpu_pins: litcpu-pins {
-+ rockchip,pins =
-+ /* litcpu_avs */
-+ <0 RK_PD3 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ mcu {
-+ /omit-if-no-ref/
-+ mcum0_pins: mcum0-pins {
-+ rockchip,pins =
-+ /* mcu_jtag_tck_m0 */
-+ <4 RK_PD4 5 &pcfg_pull_none>,
-+ /* mcu_jtag_tms_m0 */
-+ <4 RK_PD5 5 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mcum1_pins: mcum1-pins {
-+ rockchip,pins =
-+ /* mcu_jtag_tck_m1 */
-+ <3 RK_PD4 6 &pcfg_pull_none>,
-+ /* mcu_jtag_tms_m1 */
-+ <3 RK_PD5 6 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ mipi {
-+ /omit-if-no-ref/
-+ mipim0_camera0_clk: mipim0-camera0-clk {
-+ rockchip,pins =
-+ /* mipim0_camera0_clk */
-+ <4 RK_PB1 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipim0_camera1_clk: mipim0-camera1-clk {
-+ rockchip,pins =
-+ /* mipim0_camera1_clk */
-+ <1 RK_PB6 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipim0_camera2_clk: mipim0-camera2-clk {
-+ rockchip,pins =
-+ /* mipim0_camera2_clk */
-+ <1 RK_PB7 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipim0_camera3_clk: mipim0-camera3-clk {
-+ rockchip,pins =
-+ /* mipim0_camera3_clk */
-+ <1 RK_PD6 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipim0_camera4_clk: mipim0-camera4-clk {
-+ rockchip,pins =
-+ /* mipim0_camera4_clk */
-+ <1 RK_PD7 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipim1_camera0_clk: mipim1-camera0-clk {
-+ rockchip,pins =
-+ /* mipim1_camera0_clk */
-+ <3 RK_PA5 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipim1_camera1_clk: mipim1-camera1-clk {
-+ rockchip,pins =
-+ /* mipim1_camera1_clk */
-+ <3 RK_PA6 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipim1_camera2_clk: mipim1-camera2-clk {
-+ rockchip,pins =
-+ /* mipim1_camera2_clk */
-+ <3 RK_PA7 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipim1_camera3_clk: mipim1-camera3-clk {
-+ rockchip,pins =
-+ /* mipim1_camera3_clk */
-+ <3 RK_PB0 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipim1_camera4_clk: mipim1-camera4-clk {
-+ rockchip,pins =
-+ /* mipim1_camera4_clk */
-+ <3 RK_PB1 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipi_te0: mipi-te0 {
-+ rockchip,pins =
-+ /* mipi_te0 */
-+ <3 RK_PC2 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ mipi_te1: mipi-te1 {
-+ rockchip,pins =
-+ /* mipi_te1 */
-+ <3 RK_PC3 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ npu {
-+ /omit-if-no-ref/
-+ npu_pins: npu-pins {
-+ rockchip,pins =
-+ /* npu_avs */
-+ <0 RK_PC6 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie20x1 {
-+ /omit-if-no-ref/
-+ pcie20x1m0_pins: pcie20x1m0-pins {
-+ rockchip,pins =
-+ /* pcie20x1_2_clkreqn_m0 */
-+ <3 RK_PC7 4 &pcfg_pull_none>,
-+ /* pcie20x1_2_perstn_m0 */
-+ <3 RK_PD1 4 &pcfg_pull_none>,
-+ /* pcie20x1_2_waken_m0 */
-+ <3 RK_PD0 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie20x1m1_pins: pcie20x1m1-pins {
-+ rockchip,pins =
-+ /* pcie20x1_2_clkreqn_m1 */
-+ <4 RK_PB7 4 &pcfg_pull_none>,
-+ /* pcie20x1_2_perstn_m1 */
-+ <4 RK_PC1 4 &pcfg_pull_none>,
-+ /* pcie20x1_2_waken_m1 */
-+ <4 RK_PC0 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
-+ rockchip,pins =
-+ /* pcie20x1_2_button_rstn */
-+ <4 RK_PB3 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie30phy {
-+ /omit-if-no-ref/
-+ pcie30phy_pins: pcie30phy-pins {
-+ rockchip,pins =
-+ /* pcie30phy_dtb0 */
-+ <1 RK_PC4 4 &pcfg_pull_none>,
-+ /* pcie30phy_dtb1 */
-+ <1 RK_PD1 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie30x1 {
-+ /omit-if-no-ref/
-+ pcie30x1m0_pins: pcie30x1m0-pins {
-+ rockchip,pins =
-+ /* pcie30x1_0_clkreqn_m0 */
-+ <0 RK_PC0 12 &pcfg_pull_none>,
-+ /* pcie30x1_0_perstn_m0 */
-+ <0 RK_PC5 12 &pcfg_pull_none>,
-+ /* pcie30x1_0_waken_m0 */
-+ <0 RK_PC4 12 &pcfg_pull_none>,
-+ /* pcie30x1_1_clkreqn_m0 */
-+ <0 RK_PB5 12 &pcfg_pull_none>,
-+ /* pcie30x1_1_perstn_m0 */
-+ <0 RK_PB7 12 &pcfg_pull_none>,
-+ /* pcie30x1_1_waken_m0 */
-+ <0 RK_PB6 12 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x1m1_pins: pcie30x1m1-pins {
-+ rockchip,pins =
-+ /* pcie30x1_0_clkreqn_m1 */
-+ <4 RK_PA3 4 &pcfg_pull_none>,
-+ /* pcie30x1_0_perstn_m1 */
-+ <4 RK_PA5 4 &pcfg_pull_none>,
-+ /* pcie30x1_0_waken_m1 */
-+ <4 RK_PA4 4 &pcfg_pull_none>,
-+ /* pcie30x1_1_clkreqn_m1 */
-+ <4 RK_PA0 4 &pcfg_pull_none>,
-+ /* pcie30x1_1_perstn_m1 */
-+ <4 RK_PA2 4 &pcfg_pull_none>,
-+ /* pcie30x1_1_waken_m1 */
-+ <4 RK_PA1 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x1m2_pins: pcie30x1m2-pins {
-+ rockchip,pins =
-+ /* pcie30x1_0_clkreqn_m2 */
-+ <1 RK_PB5 4 &pcfg_pull_none>,
-+ /* pcie30x1_0_perstn_m2 */
-+ <1 RK_PB4 4 &pcfg_pull_none>,
-+ /* pcie30x1_0_waken_m2 */
-+ <1 RK_PB3 4 &pcfg_pull_none>,
-+ /* pcie30x1_1_clkreqn_m2 */
-+ <1 RK_PA0 4 &pcfg_pull_none>,
-+ /* pcie30x1_1_perstn_m2 */
-+ <1 RK_PA7 4 &pcfg_pull_none>,
-+ /* pcie30x1_1_waken_m2 */
-+ <1 RK_PA1 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
-+ rockchip,pins =
-+ /* pcie30x1_0_button_rstn */
-+ <4 RK_PB1 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
-+ rockchip,pins =
-+ /* pcie30x1_1_button_rstn */
-+ <4 RK_PB2 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie30x2 {
-+ /omit-if-no-ref/
-+ pcie30x2m0_pins: pcie30x2m0-pins {
-+ rockchip,pins =
-+ /* pcie30x2_clkreqn_m0 */
-+ <0 RK_PD1 12 &pcfg_pull_none>,
-+ /* pcie30x2_perstn_m0 */
-+ <0 RK_PD4 12 &pcfg_pull_none>,
-+ /* pcie30x2_waken_m0 */
-+ <0 RK_PD2 12 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x2m1_pins: pcie30x2m1-pins {
-+ rockchip,pins =
-+ /* pcie30x2_clkreqn_m1 */
-+ <4 RK_PA6 4 &pcfg_pull_none>,
-+ /* pcie30x2_perstn_m1 */
-+ <4 RK_PB0 4 &pcfg_pull_none>,
-+ /* pcie30x2_waken_m1 */
-+ <4 RK_PA7 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x2m2_pins: pcie30x2m2-pins {
-+ rockchip,pins =
-+ /* pcie30x2_clkreqn_m2 */
-+ <3 RK_PD2 4 &pcfg_pull_none>,
-+ /* pcie30x2_perstn_m2 */
-+ <3 RK_PD4 4 &pcfg_pull_none>,
-+ /* pcie30x2_waken_m2 */
-+ <3 RK_PD3 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x2m3_pins: pcie30x2m3-pins {
-+ rockchip,pins =
-+ /* pcie30x2_clkreqn_m3 */
-+ <1 RK_PD7 4 &pcfg_pull_none>,
-+ /* pcie30x2_perstn_m3 */
-+ <1 RK_PB7 4 &pcfg_pull_none>,
-+ /* pcie30x2_waken_m3 */
-+ <1 RK_PB6 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x2_button_rstn: pcie30x2-button-rstn {
-+ rockchip,pins =
-+ /* pcie30x2_button_rstn */
-+ <3 RK_PC1 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie30x4 {
-+ /omit-if-no-ref/
-+ pcie30x4m0_pins: pcie30x4m0-pins {
-+ rockchip,pins =
-+ /* pcie30x4_clkreqn_m0 */
-+ <0 RK_PC6 12 &pcfg_pull_none>,
-+ /* pcie30x4_perstn_m0 */
-+ <0 RK_PD0 12 &pcfg_pull_none>,
-+ /* pcie30x4_waken_m0 */
-+ <0 RK_PC7 12 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x4m1_pins: pcie30x4m1-pins {
-+ rockchip,pins =
-+ /* pcie30x4_clkreqn_m1 */
-+ <4 RK_PB4 4 &pcfg_pull_none>,
-+ /* pcie30x4_perstn_m1 */
-+ <4 RK_PB6 4 &pcfg_pull_none>,
-+ /* pcie30x4_waken_m1 */
-+ <4 RK_PB5 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x4m2_pins: pcie30x4m2-pins {
-+ rockchip,pins =
-+ /* pcie30x4_clkreqn_m2 */
-+ <3 RK_PC4 4 &pcfg_pull_none>,
-+ /* pcie30x4_perstn_m2 */
-+ <3 RK_PC6 4 &pcfg_pull_none>,
-+ /* pcie30x4_waken_m2 */
-+ <3 RK_PC5 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x4m3_pins: pcie30x4m3-pins {
-+ rockchip,pins =
-+ /* pcie30x4_clkreqn_m3 */
-+ <1 RK_PB0 4 &pcfg_pull_none>,
-+ /* pcie30x4_perstn_m3 */
-+ <1 RK_PB2 4 &pcfg_pull_none>,
-+ /* pcie30x4_waken_m3 */
-+ <1 RK_PB1 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pcie30x4_button_rstn: pcie30x4-button-rstn {
-+ rockchip,pins =
-+ /* pcie30x4_button_rstn */
-+ <3 RK_PD5 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pdm0 {
-+ /omit-if-no-ref/
-+ pdm0m0_clk: pdm0m0-clk {
-+ rockchip,pins =
-+ /* pdm0_clk0_m0 */
-+ <1 RK_PC6 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m0_clk1: pdm0m0-clk1 {
-+ rockchip,pins =
-+ /* pdm0m0_clk1 */
-+ <1 RK_PC4 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m0_sdi0: pdm0m0-sdi0 {
-+ rockchip,pins =
-+ /* pdm0m0_sdi0 */
-+ <1 RK_PD5 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m0_sdi1: pdm0m0-sdi1 {
-+ rockchip,pins =
-+ /* pdm0m0_sdi1 */
-+ <1 RK_PD1 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m0_sdi2: pdm0m0-sdi2 {
-+ rockchip,pins =
-+ /* pdm0m0_sdi2 */
-+ <1 RK_PD2 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m0_sdi3: pdm0m0-sdi3 {
-+ rockchip,pins =
-+ /* pdm0m0_sdi3 */
-+ <1 RK_PD3 3 &pcfg_pull_none>;
-+ };
-+ /omit-if-no-ref/
-+ pdm0m1_clk: pdm0m1-clk {
-+ rockchip,pins =
-+ /* pdm0_clk0_m1 */
-+ <0 RK_PC0 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m1_clk1: pdm0m1-clk1 {
-+ rockchip,pins =
-+ /* pdm0m1_clk1 */
-+ <0 RK_PC4 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m1_sdi0: pdm0m1-sdi0 {
-+ rockchip,pins =
-+ /* pdm0m1_sdi0 */
-+ <0 RK_PC7 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m1_sdi1: pdm0m1-sdi1 {
-+ rockchip,pins =
-+ /* pdm0m1_sdi1 */
-+ <0 RK_PD0 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m1_sdi2: pdm0m1-sdi2 {
-+ rockchip,pins =
-+ /* pdm0m1_sdi2 */
-+ <0 RK_PD4 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm0m1_sdi3: pdm0m1-sdi3 {
-+ rockchip,pins =
-+ /* pdm0m1_sdi3 */
-+ <0 RK_PD6 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pdm1 {
-+ /omit-if-no-ref/
-+ pdm1m0_clk: pdm1m0-clk {
-+ rockchip,pins =
-+ /* pdm1_clk0_m0 */
-+ <4 RK_PD5 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m0_clk1: pdm1m0-clk1 {
-+ rockchip,pins =
-+ /* pdm1m0_clk1 */
-+ <4 RK_PD4 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m0_sdi0: pdm1m0-sdi0 {
-+ rockchip,pins =
-+ /* pdm1m0_sdi0 */
-+ <4 RK_PD3 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m0_sdi1: pdm1m0-sdi1 {
-+ rockchip,pins =
-+ /* pdm1m0_sdi1 */
-+ <4 RK_PD2 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m0_sdi2: pdm1m0-sdi2 {
-+ rockchip,pins =
-+ /* pdm1m0_sdi2 */
-+ <4 RK_PD1 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m0_sdi3: pdm1m0-sdi3 {
-+ rockchip,pins =
-+ /* pdm1m0_sdi3 */
-+ <4 RK_PD0 2 &pcfg_pull_none>;
-+ };
-+ /omit-if-no-ref/
-+ pdm1m1_clk: pdm1m1-clk {
-+ rockchip,pins =
-+ /* pdm1_clk0_m1 */
-+ <1 RK_PB4 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m1_clk1: pdm1m1-clk1 {
-+ rockchip,pins =
-+ /* pdm1m1_clk1 */
-+ <1 RK_PB3 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m1_sdi0: pdm1m1-sdi0 {
-+ rockchip,pins =
-+ /* pdm1m1_sdi0 */
-+ <1 RK_PA7 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m1_sdi1: pdm1m1-sdi1 {
-+ rockchip,pins =
-+ /* pdm1m1_sdi1 */
-+ <1 RK_PB0 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m1_sdi2: pdm1m1-sdi2 {
-+ rockchip,pins =
-+ /* pdm1m1_sdi2 */
-+ <1 RK_PB1 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pdm1m1_sdi3: pdm1m1-sdi3 {
-+ rockchip,pins =
-+ /* pdm1m1_sdi3 */
-+ <1 RK_PB2 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ /omit-if-no-ref/
-+ pmic_pins: pmic-pins {
-+ rockchip,pins =
-+ /* pmic_int_l */
-+ <0 RK_PA7 0 &pcfg_pull_up>,
-+ /* pmic_sleep1 */
-+ <0 RK_PA2 1 &pcfg_pull_none>,
-+ /* pmic_sleep2 */
-+ <0 RK_PA3 1 &pcfg_pull_none>,
-+ /* pmic_sleep3 */
-+ <0 RK_PC1 1 &pcfg_pull_none>,
-+ /* pmic_sleep4 */
-+ <0 RK_PC2 1 &pcfg_pull_none>,
-+ /* pmic_sleep5 */
-+ <0 RK_PC3 1 &pcfg_pull_none>,
-+ /* pmic_sleep6 */
-+ <0 RK_PD6 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmu {
-+ /omit-if-no-ref/
-+ pmu_pins: pmu-pins {
-+ rockchip,pins =
-+ /* pmu_debug */
-+ <0 RK_PA5 3 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm0 {
-+ /omit-if-no-ref/
-+ pwm0m0_pins: pwm0m0-pins {
-+ rockchip,pins =
-+ /* pwm0_m0 */
-+ <0 RK_PB7 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm0m1_pins: pwm0m1-pins {
-+ rockchip,pins =
-+ /* pwm0_m1 */
-+ <1 RK_PD2 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm0m2_pins: pwm0m2-pins {
-+ rockchip,pins =
-+ /* pwm0_m2 */
-+ <1 RK_PA2 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm1 {
-+ /omit-if-no-ref/
-+ pwm1m0_pins: pwm1m0-pins {
-+ rockchip,pins =
-+ /* pwm1_m0 */
-+ <0 RK_PC0 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm1m1_pins: pwm1m1-pins {
-+ rockchip,pins =
-+ /* pwm1_m1 */
-+ <1 RK_PD3 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm1m2_pins: pwm1m2-pins {
-+ rockchip,pins =
-+ /* pwm1_m2 */
-+ <1 RK_PA3 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm2 {
-+ /omit-if-no-ref/
-+ pwm2m0_pins: pwm2m0-pins {
-+ rockchip,pins =
-+ /* pwm2_m0 */
-+ <0 RK_PC4 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm2m1_pins: pwm2m1-pins {
-+ rockchip,pins =
-+ /* pwm2_m1 */
-+ <3 RK_PB1 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm3 {
-+ /omit-if-no-ref/
-+ pwm3m0_pins: pwm3m0-pins {
-+ rockchip,pins =
-+ /* pwm3_ir_m0 */
-+ <0 RK_PD4 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm3m1_pins: pwm3m1-pins {
-+ rockchip,pins =
-+ /* pwm3_ir_m1 */
-+ <3 RK_PB2 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm3m2_pins: pwm3m2-pins {
-+ rockchip,pins =
-+ /* pwm3_ir_m2 */
-+ <1 RK_PC2 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm3m3_pins: pwm3m3-pins {
-+ rockchip,pins =
-+ /* pwm3_ir_m3 */
-+ <1 RK_PA7 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm4 {
-+ /omit-if-no-ref/
-+ pwm4m0_pins: pwm4m0-pins {
-+ rockchip,pins =
-+ /* pwm4_m0 */
-+ <0 RK_PC5 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm5 {
-+ /omit-if-no-ref/
-+ pwm5m0_pins: pwm5m0-pins {
-+ rockchip,pins =
-+ /* pwm5_m0 */
-+ <0 RK_PB1 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm5m1_pins: pwm5m1-pins {
-+ rockchip,pins =
-+ /* pwm5_m1 */
-+ <0 RK_PC6 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm6 {
-+ /omit-if-no-ref/
-+ pwm6m0_pins: pwm6m0-pins {
-+ rockchip,pins =
-+ /* pwm6_m0 */
-+ <0 RK_PC7 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm6m1_pins: pwm6m1-pins {
-+ rockchip,pins =
-+ /* pwm6_m1 */
-+ <4 RK_PC1 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm7 {
-+ /omit-if-no-ref/
-+ pwm7m0_pins: pwm7m0-pins {
-+ rockchip,pins =
-+ /* pwm7_ir_m0 */
-+ <0 RK_PD0 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm7m1_pins: pwm7m1-pins {
-+ rockchip,pins =
-+ /* pwm7_ir_m1 */
-+ <4 RK_PD4 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm7m2_pins: pwm7m2-pins {
-+ rockchip,pins =
-+ /* pwm7_ir_m2 */
-+ <1 RK_PC3 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm8 {
-+ /omit-if-no-ref/
-+ pwm8m0_pins: pwm8m0-pins {
-+ rockchip,pins =
-+ /* pwm8_m0 */
-+ <3 RK_PA7 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm8m1_pins: pwm8m1-pins {
-+ rockchip,pins =
-+ /* pwm8_m1 */
-+ <4 RK_PD0 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm8m2_pins: pwm8m2-pins {
-+ rockchip,pins =
-+ /* pwm8_m2 */
-+ <3 RK_PD0 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm9 {
-+ /omit-if-no-ref/
-+ pwm9m0_pins: pwm9m0-pins {
-+ rockchip,pins =
-+ /* pwm9_m0 */
-+ <3 RK_PB0 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm9m1_pins: pwm9m1-pins {
-+ rockchip,pins =
-+ /* pwm9_m1 */
-+ <4 RK_PD1 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm9m2_pins: pwm9m2-pins {
-+ rockchip,pins =
-+ /* pwm9_m2 */
-+ <3 RK_PD1 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm10 {
-+ /omit-if-no-ref/
-+ pwm10m0_pins: pwm10m0-pins {
-+ rockchip,pins =
-+ /* pwm10_m0 */
-+ <3 RK_PA0 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm10m1_pins: pwm10m1-pins {
-+ rockchip,pins =
-+ /* pwm10_m1 */
-+ <4 RK_PD3 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm10m2_pins: pwm10m2-pins {
-+ rockchip,pins =
-+ /* pwm10_m2 */
-+ <3 RK_PD3 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm11 {
-+ /omit-if-no-ref/
-+ pwm11m0_pins: pwm11m0-pins {
-+ rockchip,pins =
-+ /* pwm11_ir_m0 */
-+ <3 RK_PA1 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm11m1_pins: pwm11m1-pins {
-+ rockchip,pins =
-+ /* pwm11_ir_m1 */
-+ <4 RK_PB4 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm11m2_pins: pwm11m2-pins {
-+ rockchip,pins =
-+ /* pwm11_ir_m2 */
-+ <1 RK_PC4 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm11m3_pins: pwm11m3-pins {
-+ rockchip,pins =
-+ /* pwm11_ir_m3 */
-+ <3 RK_PD5 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm12 {
-+ /omit-if-no-ref/
-+ pwm12m0_pins: pwm12m0-pins {
-+ rockchip,pins =
-+ /* pwm12_m0 */
-+ <3 RK_PB5 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm12m1_pins: pwm12m1-pins {
-+ rockchip,pins =
-+ /* pwm12_m1 */
-+ <4 RK_PB5 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm13 {
-+ /omit-if-no-ref/
-+ pwm13m0_pins: pwm13m0-pins {
-+ rockchip,pins =
-+ /* pwm13_m0 */
-+ <3 RK_PB6 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm13m1_pins: pwm13m1-pins {
-+ rockchip,pins =
-+ /* pwm13_m1 */
-+ <4 RK_PB6 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm13m2_pins: pwm13m2-pins {
-+ rockchip,pins =
-+ /* pwm13_m2 */
-+ <1 RK_PB7 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm14 {
-+ /omit-if-no-ref/
-+ pwm14m0_pins: pwm14m0-pins {
-+ rockchip,pins =
-+ /* pwm14_m0 */
-+ <3 RK_PC2 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm14m1_pins: pwm14m1-pins {
-+ rockchip,pins =
-+ /* pwm14_m1 */
-+ <4 RK_PB2 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm14m2_pins: pwm14m2-pins {
-+ rockchip,pins =
-+ /* pwm14_m2 */
-+ <1 RK_PD6 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm15 {
-+ /omit-if-no-ref/
-+ pwm15m0_pins: pwm15m0-pins {
-+ rockchip,pins =
-+ /* pwm15_ir_m0 */
-+ <3 RK_PC3 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm15m1_pins: pwm15m1-pins {
-+ rockchip,pins =
-+ /* pwm15_ir_m1 */
-+ <4 RK_PB3 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm15m2_pins: pwm15m2-pins {
-+ rockchip,pins =
-+ /* pwm15_ir_m2 */
-+ <1 RK_PC6 11 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm15m3_pins: pwm15m3-pins {
-+ rockchip,pins =
-+ /* pwm15_ir_m3 */
-+ <1 RK_PD7 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ refclk {
-+ /omit-if-no-ref/
-+ refclk_pins: refclk-pins {
-+ rockchip,pins =
-+ /* refclk_out */
-+ <0 RK_PA0 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sata {
-+ /omit-if-no-ref/
-+ sata_pins: sata-pins {
-+ rockchip,pins =
-+ /* sata_cp_pod */
-+ <0 RK_PC6 13 &pcfg_pull_none>,
-+ /* sata_cpdet */
-+ <0 RK_PD4 13 &pcfg_pull_none>,
-+ /* sata_mp_switch */
-+ <0 RK_PD5 13 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sata0 {
-+ /omit-if-no-ref/
-+ sata0m0_pins: sata0m0-pins {
-+ rockchip,pins =
-+ /* sata0_act_led_m0 */
-+ <4 RK_PB6 6 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ sata0m1_pins: sata0m1-pins {
-+ rockchip,pins =
-+ /* sata0_act_led_m1 */
-+ <1 RK_PB3 6 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sata1 {
-+ /omit-if-no-ref/
-+ sata1m0_pins: sata1m0-pins {
-+ rockchip,pins =
-+ /* sata1_act_led_m0 */
-+ <4 RK_PB5 6 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ sata1m1_pins: sata1m1-pins {
-+ rockchip,pins =
-+ /* sata1_act_led_m1 */
-+ <1 RK_PA1 6 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sata2 {
-+ /omit-if-no-ref/
-+ sata2m0_pins: sata2m0-pins {
-+ rockchip,pins =
-+ /* sata2_act_led_m0 */
-+ <4 RK_PB1 6 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ sata2m1_pins: sata2m1-pins {
-+ rockchip,pins =
-+ /* sata2_act_led_m1 */
-+ <1 RK_PB7 6 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sdio {
-+ /omit-if-no-ref/
-+ sdiom1_pins: sdiom1-pins {
-+ rockchip,pins =
-+ /* sdio_clk_m1 */
-+ <3 RK_PA5 2 &pcfg_pull_none>,
-+ /* sdio_cmd_m1 */
-+ <3 RK_PA4 2 &pcfg_pull_none>,
-+ /* sdio_d0_m1 */
-+ <3 RK_PA0 2 &pcfg_pull_none>,
-+ /* sdio_d1_m1 */
-+ <3 RK_PA1 2 &pcfg_pull_none>,
-+ /* sdio_d2_m1 */
-+ <3 RK_PA2 2 &pcfg_pull_none>,
-+ /* sdio_d3_m1 */
-+ <3 RK_PA3 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sdmmc {
-+ /omit-if-no-ref/
-+ sdmmc_bus4: sdmmc-bus4 {
-+ rockchip,pins =
-+ /* sdmmc_d0 */
-+ <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
-+ /* sdmmc_d1 */
-+ <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
-+ /* sdmmc_d2 */
-+ <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
-+ /* sdmmc_d3 */
-+ <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ sdmmc_clk: sdmmc-clk {
-+ rockchip,pins =
-+ /* sdmmc_clk */
-+ <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ sdmmc_cmd: sdmmc-cmd {
-+ rockchip,pins =
-+ /* sdmmc_cmd */
-+ <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ sdmmc_det: sdmmc-det {
-+ rockchip,pins =
-+ /* sdmmc_det */
-+ <0 RK_PA4 1 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ sdmmc_pwren: sdmmc-pwren {
-+ rockchip,pins =
-+ /* sdmmc_pwren */
-+ <0 RK_PA5 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ spdif0 {
-+ /omit-if-no-ref/
-+ spdif0m0_tx: spdif0m0-tx {
-+ rockchip,pins =
-+ /* spdif0m0_tx */
-+ <1 RK_PB6 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spdif0m1_tx: spdif0m1-tx {
-+ rockchip,pins =
-+ /* spdif0m1_tx */
-+ <4 RK_PB4 6 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ spdif1 {
-+ /omit-if-no-ref/
-+ spdif1m0_tx: spdif1m0-tx {
-+ rockchip,pins =
-+ /* spdif1m0_tx */
-+ <1 RK_PB7 3 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spdif1m1_tx: spdif1m1-tx {
-+ rockchip,pins =
-+ /* spdif1m1_tx */
-+ <4 RK_PB1 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spdif1m2_tx: spdif1m2-tx {
-+ rockchip,pins =
-+ /* spdif1m2_tx */
-+ <4 RK_PC1 3 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ spi0 {
-+ /omit-if-no-ref/
-+ spi0m0_pins: spi0m0-pins {
-+ rockchip,pins =
-+ /* spi0_clk_m0 */
-+ <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi0_miso_m0 */
-+ <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi0_mosi_m0 */
-+ <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi0m0_cs0: spi0m0-cs0 {
-+ rockchip,pins =
-+ /* spi0_cs0_m0 */
-+ <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi0m0_cs1: spi0m0-cs1 {
-+ rockchip,pins =
-+ /* spi0_cs1_m0 */
-+ <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+ /omit-if-no-ref/
-+ spi0m1_pins: spi0m1-pins {
-+ rockchip,pins =
-+ /* spi0_clk_m1 */
-+ <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi0_miso_m1 */
-+ <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi0_mosi_m1 */
-+ <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi0m1_cs0: spi0m1-cs0 {
-+ rockchip,pins =
-+ /* spi0_cs0_m1 */
-+ <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi0m1_cs1: spi0m1-cs1 {
-+ rockchip,pins =
-+ /* spi0_cs1_m1 */
-+ <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+ /omit-if-no-ref/
-+ spi0m2_pins: spi0m2-pins {
-+ rockchip,pins =
-+ /* spi0_clk_m2 */
-+ <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi0_miso_m2 */
-+ <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi0_mosi_m2 */
-+ <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi0m2_cs0: spi0m2-cs0 {
-+ rockchip,pins =
-+ /* spi0_cs0_m2 */
-+ <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi0m2_cs1: spi0m2-cs1 {
-+ rockchip,pins =
-+ /* spi0_cs1_m2 */
-+ <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+ /omit-if-no-ref/
-+ spi0m3_pins: spi0m3-pins {
-+ rockchip,pins =
-+ /* spi0_clk_m3 */
-+ <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi0_miso_m3 */
-+ <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi0_mosi_m3 */
-+ <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi0m3_cs0: spi0m3-cs0 {
-+ rockchip,pins =
-+ /* spi0_cs0_m3 */
-+ <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi0m3_cs1: spi0m3-cs1 {
-+ rockchip,pins =
-+ /* spi0_cs1_m3 */
-+ <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+ };
-+
-+ spi1 {
-+ /omit-if-no-ref/
-+ spi1m1_pins: spi1m1-pins {
-+ rockchip,pins =
-+ /* spi1_clk_m1 */
-+ <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi1_miso_m1 */
-+ <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi1_mosi_m1 */
-+ <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi1m1_cs0: spi1m1-cs0 {
-+ rockchip,pins =
-+ /* spi1_cs0_m1 */
-+ <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi1m1_cs1: spi1m1-cs1 {
-+ rockchip,pins =
-+ /* spi1_cs1_m1 */
-+ <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi1m2_pins: spi1m2-pins {
-+ rockchip,pins =
-+ /* spi1_clk_m2 */
-+ <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi1_miso_m2 */
-+ <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi1_mosi_m2 */
-+ <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi1m2_cs0: spi1m2-cs0 {
-+ rockchip,pins =
-+ /* spi1_cs0_m2 */
-+ <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi1m2_cs1: spi1m2-cs1 {
-+ rockchip,pins =
-+ /* spi1_cs1_m2 */
-+ <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+ };
-+
-+ spi2 {
-+ /omit-if-no-ref/
-+ spi2m0_pins: spi2m0-pins {
-+ rockchip,pins =
-+ /* spi2_clk_m0 */
-+ <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi2_miso_m0 */
-+ <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi2_mosi_m0 */
-+ <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi2m0_cs0: spi2m0-cs0 {
-+ rockchip,pins =
-+ /* spi2_cs0_m0 */
-+ <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi2m0_cs1: spi2m0-cs1 {
-+ rockchip,pins =
-+ /* spi2_cs1_m0 */
-+ <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi2m1_pins: spi2m1-pins {
-+ rockchip,pins =
-+ /* spi2_clk_m1 */
-+ <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi2_miso_m1 */
-+ <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi2_mosi_m1 */
-+ <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi2m1_cs0: spi2m1-cs0 {
-+ rockchip,pins =
-+ /* spi2_cs0_m1 */
-+ <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi2m1_cs1: spi2m1-cs1 {
-+ rockchip,pins =
-+ /* spi2_cs1_m1 */
-+ <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi2m2_pins: spi2m2-pins {
-+ rockchip,pins =
-+ /* spi2_clk_m2 */
-+ <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
-+ /* spi2_miso_m2 */
-+ <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
-+ /* spi2_mosi_m2 */
-+ <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi2m2_cs0: spi2m2-cs0 {
-+ rockchip,pins =
-+ /* spi2_cs0_m2 */
-+ <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi2m2_cs1: spi2m2-cs1 {
-+ rockchip,pins =
-+ /* spi2_cs1_m2 */
-+ <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
-+ };
-+ };
-+
-+ spi3 {
-+ /omit-if-no-ref/
-+ spi3m1_pins: spi3m1-pins {
-+ rockchip,pins =
-+ /* spi3_clk_m1 */
-+ <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi3_miso_m1 */
-+ <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi3_mosi_m1 */
-+ <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m1_cs0: spi3m1-cs0 {
-+ rockchip,pins =
-+ /* spi3_cs0_m1 */
-+ <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m1_cs1: spi3m1-cs1 {
-+ rockchip,pins =
-+ /* spi3_cs1_m1 */
-+ <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m2_pins: spi3m2-pins {
-+ rockchip,pins =
-+ /* spi3_clk_m2 */
-+ <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi3_miso_m2 */
-+ <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi3_mosi_m2 */
-+ <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m2_cs0: spi3m2-cs0 {
-+ rockchip,pins =
-+ /* spi3_cs0_m2 */
-+ <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m2_cs1: spi3m2-cs1 {
-+ rockchip,pins =
-+ /* spi3_cs1_m2 */
-+ <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m3_pins: spi3m3-pins {
-+ rockchip,pins =
-+ /* spi3_clk_m3 */
-+ <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi3_miso_m3 */
-+ <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi3_mosi_m3 */
-+ <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m3_cs0: spi3m3-cs0 {
-+ rockchip,pins =
-+ /* spi3_cs0_m3 */
-+ <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m3_cs1: spi3m3-cs1 {
-+ rockchip,pins =
-+ /* spi3_cs1_m3 */
-+ <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+ };
-+
-+ spi4 {
-+ /omit-if-no-ref/
-+ spi4m0_pins: spi4m0-pins {
-+ rockchip,pins =
-+ /* spi4_clk_m0 */
-+ <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi4_miso_m0 */
-+ <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi4_mosi_m0 */
-+ <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi4m0_cs0: spi4m0-cs0 {
-+ rockchip,pins =
-+ /* spi4_cs0_m0 */
-+ <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi4m0_cs1: spi4m0-cs1 {
-+ rockchip,pins =
-+ /* spi4_cs1_m0 */
-+ <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi4m1_pins: spi4m1-pins {
-+ rockchip,pins =
-+ /* spi4_clk_m1 */
-+ <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi4_miso_m1 */
-+ <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi4_mosi_m1 */
-+ <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi4m1_cs0: spi4m1-cs0 {
-+ rockchip,pins =
-+ /* spi4_cs0_m1 */
-+ <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi4m1_cs1: spi4m1-cs1 {
-+ rockchip,pins =
-+ /* spi4_cs1_m1 */
-+ <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi4m2_pins: spi4m2-pins {
-+ rockchip,pins =
-+ /* spi4_clk_m2 */
-+ <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi4_miso_m2 */
-+ <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi4_mosi_m2 */
-+ <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi4m2_cs0: spi4m2-cs0 {
-+ rockchip,pins =
-+ /* spi4_cs0_m2 */
-+ <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+ };
-+
-+ tsadc {
-+ /omit-if-no-ref/
-+ tsadcm1_shut: tsadcm1-shut {
-+ rockchip,pins =
-+ /* tsadcm1_shut */
-+ <0 RK_PA2 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ tsadc_shut: tsadc-shut {
-+ rockchip,pins =
-+ /* tsadc_shut */
-+ <0 RK_PA1 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ tsadc_shut_org: tsadc-shut-org {
-+ rockchip,pins =
-+ /* tsadc_shut_org */
-+ <0 RK_PA1 1 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ uart0 {
-+ /omit-if-no-ref/
-+ uart0m0_xfer: uart0m0-xfer {
-+ rockchip,pins =
-+ /* uart0_rx_m0 */
-+ <0 RK_PC4 4 &pcfg_pull_up>,
-+ /* uart0_tx_m0 */
-+ <0 RK_PC5 4 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart0m1_xfer: uart0m1-xfer {
-+ rockchip,pins =
-+ /* uart0_rx_m1 */
-+ <0 RK_PB0 4 &pcfg_pull_up>,
-+ /* uart0_tx_m1 */
-+ <0 RK_PB1 4 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart0m2_xfer: uart0m2-xfer {
-+ rockchip,pins =
-+ /* uart0_rx_m2 */
-+ <4 RK_PA4 10 &pcfg_pull_up>,
-+ /* uart0_tx_m2 */
-+ <4 RK_PA3 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart0_ctsn: uart0-ctsn {
-+ rockchip,pins =
-+ /* uart0_ctsn */
-+ <0 RK_PD1 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart0_rtsn: uart0-rtsn {
-+ rockchip,pins =
-+ /* uart0_rtsn */
-+ <0 RK_PC6 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ uart1 {
-+ /omit-if-no-ref/
-+ uart1m1_xfer: uart1m1-xfer {
-+ rockchip,pins =
-+ /* uart1_rx_m1 */
-+ <1 RK_PB7 10 &pcfg_pull_up>,
-+ /* uart1_tx_m1 */
-+ <1 RK_PB6 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart1m1_ctsn: uart1m1-ctsn {
-+ rockchip,pins =
-+ /* uart1m1_ctsn */
-+ <1 RK_PD7 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart1m1_rtsn: uart1m1-rtsn {
-+ rockchip,pins =
-+ /* uart1m1_rtsn */
-+ <1 RK_PD6 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart1m2_xfer: uart1m2-xfer {
-+ rockchip,pins =
-+ /* uart1_rx_m2 */
-+ <0 RK_PD2 10 &pcfg_pull_up>,
-+ /* uart1_tx_m2 */
-+ <0 RK_PD1 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart1m2_ctsn: uart1m2-ctsn {
-+ rockchip,pins =
-+ /* uart1m2_ctsn */
-+ <0 RK_PD0 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart1m2_rtsn: uart1m2-rtsn {
-+ rockchip,pins =
-+ /* uart1m2_rtsn */
-+ <0 RK_PC7 10 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ uart2 {
-+ /omit-if-no-ref/
-+ uart2m0_xfer: uart2m0-xfer {
-+ rockchip,pins =
-+ /* uart2_rx_m0 */
-+ <0 RK_PB6 10 &pcfg_pull_up>,
-+ /* uart2_tx_m0 */
-+ <0 RK_PB5 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart2m1_xfer: uart2m1-xfer {
-+ rockchip,pins =
-+ /* uart2_rx_m1 */
-+ <4 RK_PD1 10 &pcfg_pull_up>,
-+ /* uart2_tx_m1 */
-+ <4 RK_PD0 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart2m2_xfer: uart2m2-xfer {
-+ rockchip,pins =
-+ /* uart2_rx_m2 */
-+ <3 RK_PB2 10 &pcfg_pull_up>,
-+ /* uart2_tx_m2 */
-+ <3 RK_PB1 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart2_ctsn: uart2-ctsn {
-+ rockchip,pins =
-+ /* uart2_ctsn */
-+ <3 RK_PB4 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart2_rtsn: uart2-rtsn {
-+ rockchip,pins =
-+ /* uart2_rtsn */
-+ <3 RK_PB3 10 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ uart3 {
-+ /omit-if-no-ref/
-+ uart3m0_xfer: uart3m0-xfer {
-+ rockchip,pins =
-+ /* uart3_rx_m0 */
-+ <1 RK_PC0 10 &pcfg_pull_up>,
-+ /* uart3_tx_m0 */
-+ <1 RK_PC1 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart3m1_xfer: uart3m1-xfer {
-+ rockchip,pins =
-+ /* uart3_rx_m1 */
-+ <3 RK_PB6 10 &pcfg_pull_up>,
-+ /* uart3_tx_m1 */
-+ <3 RK_PB5 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart3m2_xfer: uart3m2-xfer {
-+ rockchip,pins =
-+ /* uart3_rx_m2 */
-+ <4 RK_PA6 10 &pcfg_pull_up>,
-+ /* uart3_tx_m2 */
-+ <4 RK_PA5 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart3_ctsn: uart3-ctsn {
-+ rockchip,pins =
-+ /* uart3_ctsn */
-+ <1 RK_PC3 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart3_rtsn: uart3-rtsn {
-+ rockchip,pins =
-+ /* uart3_rtsn */
-+ <1 RK_PC2 10 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ uart4 {
-+ /omit-if-no-ref/
-+ uart4m0_xfer: uart4m0-xfer {
-+ rockchip,pins =
-+ /* uart4_rx_m0 */
-+ <1 RK_PD3 10 &pcfg_pull_up>,
-+ /* uart4_tx_m0 */
-+ <1 RK_PD2 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart4m1_xfer: uart4m1-xfer {
-+ rockchip,pins =
-+ /* uart4_rx_m1 */
-+ <3 RK_PD0 10 &pcfg_pull_up>,
-+ /* uart4_tx_m1 */
-+ <3 RK_PD1 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart4m2_xfer: uart4m2-xfer {
-+ rockchip,pins =
-+ /* uart4_rx_m2 */
-+ <1 RK_PB2 10 &pcfg_pull_up>,
-+ /* uart4_tx_m2 */
-+ <1 RK_PB3 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart4_ctsn: uart4-ctsn {
-+ rockchip,pins =
-+ /* uart4_ctsn */
-+ <1 RK_PC7 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart4_rtsn: uart4-rtsn {
-+ rockchip,pins =
-+ /* uart4_rtsn */
-+ <1 RK_PC5 10 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ uart5 {
-+ /omit-if-no-ref/
-+ uart5m0_xfer: uart5m0-xfer {
-+ rockchip,pins =
-+ /* uart5_rx_m0 */
-+ <4 RK_PD4 10 &pcfg_pull_up>,
-+ /* uart5_tx_m0 */
-+ <4 RK_PD5 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart5m0_ctsn: uart5m0-ctsn {
-+ rockchip,pins =
-+ /* uart5m0_ctsn */
-+ <4 RK_PD2 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart5m0_rtsn: uart5m0-rtsn {
-+ rockchip,pins =
-+ /* uart5m0_rtsn */
-+ <4 RK_PD3 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart5m1_xfer: uart5m1-xfer {
-+ rockchip,pins =
-+ /* uart5_rx_m1 */
-+ <3 RK_PC5 10 &pcfg_pull_up>,
-+ /* uart5_tx_m1 */
-+ <3 RK_PC4 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart5m1_ctsn: uart5m1-ctsn {
-+ rockchip,pins =
-+ /* uart5m1_ctsn */
-+ <2 RK_PA2 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart5m1_rtsn: uart5m1-rtsn {
-+ rockchip,pins =
-+ /* uart5m1_rtsn */
-+ <2 RK_PA3 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart5m2_xfer: uart5m2-xfer {
-+ rockchip,pins =
-+ /* uart5_rx_m2 */
-+ <2 RK_PD4 10 &pcfg_pull_up>,
-+ /* uart5_tx_m2 */
-+ <2 RK_PD5 10 &pcfg_pull_up>;
-+ };
-+ };
-+
-+ uart6 {
-+ /omit-if-no-ref/
-+ uart6m1_xfer: uart6m1-xfer {
-+ rockchip,pins =
-+ /* uart6_rx_m1 */
-+ <1 RK_PA0 10 &pcfg_pull_up>,
-+ /* uart6_tx_m1 */
-+ <1 RK_PA1 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart6m1_ctsn: uart6m1-ctsn {
-+ rockchip,pins =
-+ /* uart6m1_ctsn */
-+ <1 RK_PA3 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart6m1_rtsn: uart6m1-rtsn {
-+ rockchip,pins =
-+ /* uart6m1_rtsn */
-+ <1 RK_PA2 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart6m2_xfer: uart6m2-xfer {
-+ rockchip,pins =
-+ /* uart6_rx_m2 */
-+ <1 RK_PD1 10 &pcfg_pull_up>,
-+ /* uart6_tx_m2 */
-+ <1 RK_PD0 10 &pcfg_pull_up>;
-+ };
-+ };
-+
-+ uart7 {
-+ /omit-if-no-ref/
-+ uart7m1_xfer: uart7m1-xfer {
-+ rockchip,pins =
-+ /* uart7_rx_m1 */
-+ <3 RK_PC1 10 &pcfg_pull_up>,
-+ /* uart7_tx_m1 */
-+ <3 RK_PC0 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart7m1_ctsn: uart7m1-ctsn {
-+ rockchip,pins =
-+ /* uart7m1_ctsn */
-+ <3 RK_PC3 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart7m1_rtsn: uart7m1-rtsn {
-+ rockchip,pins =
-+ /* uart7m1_rtsn */
-+ <3 RK_PC2 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart7m2_xfer: uart7m2-xfer {
-+ rockchip,pins =
-+ /* uart7_rx_m2 */
-+ <1 RK_PB4 10 &pcfg_pull_up>,
-+ /* uart7_tx_m2 */
-+ <1 RK_PB5 10 &pcfg_pull_up>;
-+ };
-+ };
-+
-+ uart8 {
-+ /omit-if-no-ref/
-+ uart8m0_xfer: uart8m0-xfer {
-+ rockchip,pins =
-+ /* uart8_rx_m0 */
-+ <4 RK_PB1 10 &pcfg_pull_up>,
-+ /* uart8_tx_m0 */
-+ <4 RK_PB0 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart8m0_ctsn: uart8m0-ctsn {
-+ rockchip,pins =
-+ /* uart8m0_ctsn */
-+ <4 RK_PB3 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart8m0_rtsn: uart8m0-rtsn {
-+ rockchip,pins =
-+ /* uart8m0_rtsn */
-+ <4 RK_PB2 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart8m1_xfer: uart8m1-xfer {
-+ rockchip,pins =
-+ /* uart8_rx_m1 */
-+ <3 RK_PA3 10 &pcfg_pull_up>,
-+ /* uart8_tx_m1 */
-+ <3 RK_PA2 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart8m1_ctsn: uart8m1-ctsn {
-+ rockchip,pins =
-+ /* uart8m1_ctsn */
-+ <3 RK_PA5 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart8m1_rtsn: uart8m1-rtsn {
-+ rockchip,pins =
-+ /* uart8m1_rtsn */
-+ <3 RK_PA4 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart8_xfer: uart8-xfer {
-+ rockchip,pins =
-+ /* uart8_rx_ */
-+ <4 RK_PB1 10 &pcfg_pull_up>;
-+ };
-+ };
-+
-+ uart9 {
-+ /omit-if-no-ref/
-+ uart9m0_xfer: uart9m0-xfer {
-+ rockchip,pins =
-+ /* uart9_rx_m0 */
-+ <2 RK_PC4 10 &pcfg_pull_up>,
-+ /* uart9_tx_m0 */
-+ <2 RK_PC2 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart9m1_xfer: uart9m1-xfer {
-+ rockchip,pins =
-+ /* uart9_rx_m1 */
-+ <4 RK_PB5 10 &pcfg_pull_up>,
-+ /* uart9_tx_m1 */
-+ <4 RK_PB4 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart9m1_ctsn: uart9m1-ctsn {
-+ rockchip,pins =
-+ /* uart9m1_ctsn */
-+ <4 RK_PA1 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart9m1_rtsn: uart9m1-rtsn {
-+ rockchip,pins =
-+ /* uart9m1_rtsn */
-+ <4 RK_PA0 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart9m2_xfer: uart9m2-xfer {
-+ rockchip,pins =
-+ /* uart9_rx_m2 */
-+ <3 RK_PD4 10 &pcfg_pull_up>,
-+ /* uart9_tx_m2 */
-+ <3 RK_PD5 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart9m2_ctsn: uart9m2-ctsn {
-+ rockchip,pins =
-+ /* uart9m2_ctsn */
-+ <3 RK_PD3 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart9m2_rtsn: uart9m2-rtsn {
-+ rockchip,pins =
-+ /* uart9m2_rtsn */
-+ <3 RK_PD2 10 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ vop {
-+ /omit-if-no-ref/
-+ vop_pins: vop-pins {
-+ rockchip,pins =
-+ /* vop_post_empty */
-+ <1 RK_PA2 1 &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+/*
-+ * This part is edited handly.
-+ */
-+&pinctrl {
-+ bt656 {
-+ /omit-if-no-ref/
-+ bt656_pins: bt656-pins {
-+ rockchip,pins =
-+ /* bt1120_clkout */
-+ <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
-+ /* bt1120_d0 */
-+ <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
-+ /* bt1120_d1 */
-+ <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
-+ /* bt1120_d2 */
-+ <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
-+ /* bt1120_d3 */
-+ <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
-+ /* bt1120_d4 */
-+ <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
-+ /* bt1120_d5 */
-+ <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
-+ /* bt1120_d6 */
-+ <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
-+ /* bt1120_d7 */
-+ <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
-+ };
-+ };
-+
-+ gpio-func {
-+ /omit-if-no-ref/
-+ tsadc_gpio_func: tsadc-gpio-func {
-+ rockchip,pins =
-+ <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi
-@@ -0,0 +1,516 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+ */
-+
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rockchip-pinconf.dtsi"
-+
-+/*
-+ * This file is auto generated by pin2dts tool, please keep these code
-+ * by adding changes at end of this file.
-+ */
-+&pinctrl {
-+ clk32k {
-+ /omit-if-no-ref/
-+ clk32k_out1: clk32k-out1 {
-+ rockchip,pins =
-+ /* clk32k_out1 */
-+ <2 RK_PC5 1 &pcfg_pull_none>;
-+ };
-+
-+ };
-+
-+ eth0 {
-+ /omit-if-no-ref/
-+ eth0_pins: eth0-pins {
-+ rockchip,pins =
-+ /* eth0_refclko_25m */
-+ <2 RK_PC3 1 &pcfg_pull_none>;
-+ };
-+
-+ };
-+
-+ fspi {
-+ /omit-if-no-ref/
-+ fspim1_pins: fspim1-pins {
-+ rockchip,pins =
-+ /* fspi_clk_m1 */
-+ <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_cs0n_m1 */
-+ <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d0_m1 */
-+ <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d1_m1 */
-+ <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d2_m1 */
-+ <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
-+ /* fspi_d3_m1 */
-+ <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
-+ };
-+
-+ /omit-if-no-ref/
-+ fspim1_cs1: fspim1-cs1 {
-+ rockchip,pins =
-+ /* fspi_cs1n_m1 */
-+ <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
-+ };
-+ };
-+
-+ gmac0 {
-+ /omit-if-no-ref/
-+ gmac0_miim: gmac0-miim {
-+ rockchip,pins =
-+ /* gmac0_mdc */
-+ <4 RK_PC4 1 &pcfg_pull_none>,
-+ /* gmac0_mdio */
-+ <4 RK_PC5 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac0_clkinout: gmac0-clkinout {
-+ rockchip,pins =
-+ /* gmac0_mclkinout */
-+ <4 RK_PC3 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac0_rx_bus2: gmac0-rx-bus2 {
-+ rockchip,pins =
-+ /* gmac0_rxd0 */
-+ <2 RK_PC1 1 &pcfg_pull_none>,
-+ /* gmac0_rxd1 */
-+ <2 RK_PC2 1 &pcfg_pull_none>,
-+ /* gmac0_rxdv_crs */
-+ <4 RK_PC2 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac0_tx_bus2: gmac0-tx-bus2 {
-+ rockchip,pins =
-+ /* gmac0_txd0 */
-+ <2 RK_PB6 1 &pcfg_pull_none>,
-+ /* gmac0_txd1 */
-+ <2 RK_PB7 1 &pcfg_pull_none>,
-+ /* gmac0_txen */
-+ <2 RK_PC0 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac0_rgmii_clk: gmac0-rgmii-clk {
-+ rockchip,pins =
-+ /* gmac0_rxclk */
-+ <2 RK_PB0 1 &pcfg_pull_none>,
-+ /* gmac0_txclk */
-+ <2 RK_PB3 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac0_rgmii_bus: gmac0-rgmii-bus {
-+ rockchip,pins =
-+ /* gmac0_rxd2 */
-+ <2 RK_PA6 1 &pcfg_pull_none>,
-+ /* gmac0_rxd3 */
-+ <2 RK_PA7 1 &pcfg_pull_none>,
-+ /* gmac0_txd2 */
-+ <2 RK_PB1 1 &pcfg_pull_none>,
-+ /* gmac0_txd3 */
-+ <2 RK_PB2 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac0_ppsclk: gmac0-ppsclk {
-+ rockchip,pins =
-+ /* gmac0_ppsclk */
-+ <2 RK_PC4 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac0_ppstring: gmac0-ppstring {
-+ rockchip,pins =
-+ /* gmac0_ppstring */
-+ <2 RK_PB5 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac0_ptp_refclk: gmac0-ptp-refclk {
-+ rockchip,pins =
-+ /* gmac0_ptp_refclk */
-+ <2 RK_PB4 1 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ gmac0_txer: gmac0-txer {
-+ rockchip,pins =
-+ /* gmac0_txer */
-+ <4 RK_PC6 1 &pcfg_pull_none>;
-+ };
-+
-+ };
-+
-+ hdmi {
-+ /omit-if-no-ref/
-+ hdmim0_tx1_cec: hdmim0-tx1-cec {
-+ rockchip,pins =
-+ /* hdmim0_tx1_cec */
-+ <2 RK_PC4 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_tx1_scl: hdmim0-tx1-scl {
-+ rockchip,pins =
-+ /* hdmim0_tx1_scl */
-+ <2 RK_PB5 4 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ hdmim0_tx1_sda: hdmim0-tx1-sda {
-+ rockchip,pins =
-+ /* hdmim0_tx1_sda */
-+ <2 RK_PB4 4 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ i2c0 {
-+ /omit-if-no-ref/
-+ i2c0m1_xfer: i2c0m1-xfer {
-+ rockchip,pins =
-+ /* i2c0_scl_m1 */
-+ <4 RK_PC5 9 &pcfg_pull_none_smt>,
-+ /* i2c0_sda_m1 */
-+ <4 RK_PC6 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c2 {
-+ /omit-if-no-ref/
-+ i2c2m1_xfer: i2c2m1-xfer {
-+ rockchip,pins =
-+ /* i2c2_scl_m1 */
-+ <2 RK_PC1 9 &pcfg_pull_none_smt>,
-+ /* i2c2_sda_m1 */
-+ <2 RK_PC0 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c3 {
-+ /omit-if-no-ref/
-+ i2c3m3_xfer: i2c3m3-xfer {
-+ rockchip,pins =
-+ /* i2c3_scl_m3 */
-+ <2 RK_PB2 9 &pcfg_pull_none_smt>,
-+ /* i2c3_sda_m3 */
-+ <2 RK_PB3 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c4 {
-+ /omit-if-no-ref/
-+ i2c4m1_xfer: i2c4m1-xfer {
-+ rockchip,pins =
-+ /* i2c4_scl_m1 */
-+ <2 RK_PB5 9 &pcfg_pull_none_smt>,
-+ /* i2c4_sda_m1 */
-+ <2 RK_PB4 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c5 {
-+ /omit-if-no-ref/
-+ i2c5m4_xfer: i2c5m4-xfer {
-+ rockchip,pins =
-+ /* i2c5_scl_m4 */
-+ <2 RK_PB6 9 &pcfg_pull_none_smt>,
-+ /* i2c5_sda_m4 */
-+ <2 RK_PB7 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c6 {
-+ /omit-if-no-ref/
-+ i2c6m2_xfer: i2c6m2-xfer {
-+ rockchip,pins =
-+ /* i2c6_scl_m2 */
-+ <2 RK_PC3 9 &pcfg_pull_none_smt>,
-+ /* i2c6_sda_m2 */
-+ <2 RK_PC2 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c7 {
-+ /omit-if-no-ref/
-+ i2c7m1_xfer: i2c7m1-xfer {
-+ rockchip,pins =
-+ /* i2c7_scl_m1 */
-+ <4 RK_PC3 9 &pcfg_pull_none_smt>,
-+ /* i2c7_sda_m1 */
-+ <4 RK_PC4 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2c8 {
-+ /omit-if-no-ref/
-+ i2c8m1_xfer: i2c8m1-xfer {
-+ rockchip,pins =
-+ /* i2c8_scl_m1 */
-+ <2 RK_PB0 9 &pcfg_pull_none_smt>,
-+ /* i2c8_sda_m1 */
-+ <2 RK_PB1 9 &pcfg_pull_none_smt>;
-+ };
-+ };
-+
-+ i2s2 {
-+ /omit-if-no-ref/
-+ i2s2m0_lrck: i2s2m0-lrck {
-+ rockchip,pins =
-+ /* i2s2m0_lrck */
-+ <2 RK_PC0 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_mclk: i2s2m0-mclk {
-+ rockchip,pins =
-+ /* i2s2m0_mclk */
-+ <2 RK_PB6 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_sclk: i2s2m0-sclk {
-+ rockchip,pins =
-+ /* i2s2m0_sclk */
-+ <2 RK_PB7 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_sdi: i2s2m0-sdi {
-+ rockchip,pins =
-+ /* i2s2m0_sdi */
-+ <2 RK_PC3 2 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ i2s2m0_sdo: i2s2m0-sdo {
-+ rockchip,pins =
-+ /* i2s2m0_sdo */
-+ <4 RK_PC3 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm2 {
-+ /omit-if-no-ref/
-+ pwm2m2_pins: pwm2m2-pins {
-+ rockchip,pins =
-+ /* pwm2_m2 */
-+ <4 RK_PC2 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm4 {
-+ /omit-if-no-ref/
-+ pwm4m1_pins: pwm4m1-pins {
-+ rockchip,pins =
-+ /* pwm4_m1 */
-+ <4 RK_PC3 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm5 {
-+ /omit-if-no-ref/
-+ pwm5m2_pins: pwm5m2-pins {
-+ rockchip,pins =
-+ /* pwm5_m2 */
-+ <4 RK_PC4 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm6 {
-+ /omit-if-no-ref/
-+ pwm6m2_pins: pwm6m2-pins {
-+ rockchip,pins =
-+ /* pwm6_m2 */
-+ <4 RK_PC5 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pwm7 {
-+ /omit-if-no-ref/
-+ pwm7m3_pins: pwm7m3-pins {
-+ rockchip,pins =
-+ /* pwm7_ir_m3 */
-+ <4 RK_PC6 11 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sdio {
-+ /omit-if-no-ref/
-+ sdiom0_pins: sdiom0-pins {
-+ rockchip,pins =
-+ /* sdio_clk_m0 */
-+ <2 RK_PB3 2 &pcfg_pull_none>,
-+ /* sdio_cmd_m0 */
-+ <2 RK_PB2 2 &pcfg_pull_none>,
-+ /* sdio_d0_m0 */
-+ <2 RK_PA6 2 &pcfg_pull_none>,
-+ /* sdio_d1_m0 */
-+ <2 RK_PA7 2 &pcfg_pull_none>,
-+ /* sdio_d2_m0 */
-+ <2 RK_PB0 2 &pcfg_pull_none>,
-+ /* sdio_d3_m0 */
-+ <2 RK_PB1 2 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ spi1 {
-+ /omit-if-no-ref/
-+ spi1m0_pins: spi1m0-pins {
-+ rockchip,pins =
-+ /* spi1_clk_m0 */
-+ <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi1_miso_m0 */
-+ <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi1_mosi_m0 */
-+ <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi1m0_cs0: spi1m0-cs0 {
-+ rockchip,pins =
-+ /* spi1_cs0_m0 */
-+ <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi1m0_cs1: spi1m0-cs1 {
-+ rockchip,pins =
-+ /* spi1_cs1_m0 */
-+ <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+ };
-+
-+ spi3 {
-+ /omit-if-no-ref/
-+ spi3m0_pins: spi3m0-pins {
-+ rockchip,pins =
-+ /* spi3_clk_m0 */
-+ <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi3_miso_m0 */
-+ <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
-+ /* spi3_mosi_m0 */
-+ <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m0_cs0: spi3m0-cs0 {
-+ rockchip,pins =
-+ /* spi3_cs0_m0 */
-+ <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+
-+ /omit-if-no-ref/
-+ spi3m0_cs1: spi3m0-cs1 {
-+ rockchip,pins =
-+ /* spi3_cs1_m0 */
-+ <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
-+ };
-+ };
-+
-+ uart1 {
-+ /omit-if-no-ref/
-+ uart1m0_xfer: uart1m0-xfer {
-+ rockchip,pins =
-+ /* uart1_rx_m0 */
-+ <2 RK_PB6 10 &pcfg_pull_up>,
-+ /* uart1_tx_m0 */
-+ <2 RK_PB7 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart1m0_ctsn: uart1m0-ctsn {
-+ rockchip,pins =
-+ /* uart1m0_ctsn */
-+ <2 RK_PC1 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart1m0_rtsn: uart1m0-rtsn {
-+ rockchip,pins =
-+ /* uart1m0_rtsn */
-+ <2 RK_PC0 10 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ uart6 {
-+ /omit-if-no-ref/
-+ uart6m0_xfer: uart6m0-xfer {
-+ rockchip,pins =
-+ /* uart6_rx_m0 */
-+ <2 RK_PA6 10 &pcfg_pull_up>,
-+ /* uart6_tx_m0 */
-+ <2 RK_PA7 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart6m0_ctsn: uart6m0-ctsn {
-+ rockchip,pins =
-+ /* uart6m0_ctsn */
-+ <2 RK_PB1 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart6m0_rtsn: uart6m0-rtsn {
-+ rockchip,pins =
-+ /* uart6m0_rtsn */
-+ <2 RK_PB0 10 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ uart7 {
-+ /omit-if-no-ref/
-+ uart7m0_xfer: uart7m0-xfer {
-+ rockchip,pins =
-+ /* uart7_rx_m0 */
-+ <2 RK_PB4 10 &pcfg_pull_up>,
-+ /* uart7_tx_m0 */
-+ <2 RK_PB5 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart7m0_ctsn: uart7m0-ctsn {
-+ rockchip,pins =
-+ /* uart7m0_ctsn */
-+ <4 RK_PC6 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart7m0_rtsn: uart7m0-rtsn {
-+ rockchip,pins =
-+ /* uart7m0_rtsn */
-+ <4 RK_PC2 10 &pcfg_pull_none>;
-+ };
-+ };
-+
-+ uart9 {
-+ /omit-if-no-ref/
-+ uart9m0_xfer: uart9m0-xfer {
-+ rockchip,pins =
-+ /* uart9_rx_m0 */
-+ <2 RK_PC4 10 &pcfg_pull_up>,
-+ /* uart9_tx_m0 */
-+ <2 RK_PC2 10 &pcfg_pull_up>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart9m0_ctsn: uart9m0-ctsn {
-+ rockchip,pins =
-+ /* uart9m0_ctsn */
-+ <4 RK_PC5 10 &pcfg_pull_none>;
-+ };
-+
-+ /omit-if-no-ref/
-+ uart9m0_rtsn: uart9m0-rtsn {
-+ rockchip,pins =
-+ /* uart9m0_rtsn */
-+ <4 RK_PC4 10 &pcfg_pull_none>;
-+ };
-+ };
-+};
---- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
-+++ /dev/null
-@@ -1,516 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
--/*
-- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-- */
--
--#include <dt-bindings/pinctrl/rockchip.h>
--#include "rockchip-pinconf.dtsi"
--
--/*
-- * This file is auto generated by pin2dts tool, please keep these code
-- * by adding changes at end of this file.
-- */
--&pinctrl {
-- clk32k {
-- /omit-if-no-ref/
-- clk32k_out1: clk32k-out1 {
-- rockchip,pins =
-- /* clk32k_out1 */
-- <2 RK_PC5 1 &pcfg_pull_none>;
-- };
--
-- };
--
-- eth0 {
-- /omit-if-no-ref/
-- eth0_pins: eth0-pins {
-- rockchip,pins =
-- /* eth0_refclko_25m */
-- <2 RK_PC3 1 &pcfg_pull_none>;
-- };
--
-- };
--
-- fspi {
-- /omit-if-no-ref/
-- fspim1_pins: fspim1-pins {
-- rockchip,pins =
-- /* fspi_clk_m1 */
-- <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
-- /* fspi_cs0n_m1 */
-- <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d0_m1 */
-- <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d1_m1 */
-- <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d2_m1 */
-- <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d3_m1 */
-- <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- fspim1_cs1: fspim1-cs1 {
-- rockchip,pins =
-- /* fspi_cs1n_m1 */
-- <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
-- };
-- };
--
-- gmac0 {
-- /omit-if-no-ref/
-- gmac0_miim: gmac0-miim {
-- rockchip,pins =
-- /* gmac0_mdc */
-- <4 RK_PC4 1 &pcfg_pull_none>,
-- /* gmac0_mdio */
-- <4 RK_PC5 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac0_clkinout: gmac0-clkinout {
-- rockchip,pins =
-- /* gmac0_mclkinout */
-- <4 RK_PC3 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac0_rx_bus2: gmac0-rx-bus2 {
-- rockchip,pins =
-- /* gmac0_rxd0 */
-- <2 RK_PC1 1 &pcfg_pull_none>,
-- /* gmac0_rxd1 */
-- <2 RK_PC2 1 &pcfg_pull_none>,
-- /* gmac0_rxdv_crs */
-- <4 RK_PC2 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac0_tx_bus2: gmac0-tx-bus2 {
-- rockchip,pins =
-- /* gmac0_txd0 */
-- <2 RK_PB6 1 &pcfg_pull_none>,
-- /* gmac0_txd1 */
-- <2 RK_PB7 1 &pcfg_pull_none>,
-- /* gmac0_txen */
-- <2 RK_PC0 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac0_rgmii_clk: gmac0-rgmii-clk {
-- rockchip,pins =
-- /* gmac0_rxclk */
-- <2 RK_PB0 1 &pcfg_pull_none>,
-- /* gmac0_txclk */
-- <2 RK_PB3 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac0_rgmii_bus: gmac0-rgmii-bus {
-- rockchip,pins =
-- /* gmac0_rxd2 */
-- <2 RK_PA6 1 &pcfg_pull_none>,
-- /* gmac0_rxd3 */
-- <2 RK_PA7 1 &pcfg_pull_none>,
-- /* gmac0_txd2 */
-- <2 RK_PB1 1 &pcfg_pull_none>,
-- /* gmac0_txd3 */
-- <2 RK_PB2 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac0_ppsclk: gmac0-ppsclk {
-- rockchip,pins =
-- /* gmac0_ppsclk */
-- <2 RK_PC4 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac0_ppstring: gmac0-ppstring {
-- rockchip,pins =
-- /* gmac0_ppstring */
-- <2 RK_PB5 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac0_ptp_refclk: gmac0-ptp-refclk {
-- rockchip,pins =
-- /* gmac0_ptp_refclk */
-- <2 RK_PB4 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac0_txer: gmac0-txer {
-- rockchip,pins =
-- /* gmac0_txer */
-- <4 RK_PC6 1 &pcfg_pull_none>;
-- };
--
-- };
--
-- hdmi {
-- /omit-if-no-ref/
-- hdmim0_tx1_cec: hdmim0-tx1-cec {
-- rockchip,pins =
-- /* hdmim0_tx1_cec */
-- <2 RK_PC4 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_tx1_scl: hdmim0-tx1-scl {
-- rockchip,pins =
-- /* hdmim0_tx1_scl */
-- <2 RK_PB5 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_tx1_sda: hdmim0-tx1-sda {
-- rockchip,pins =
-- /* hdmim0_tx1_sda */
-- <2 RK_PB4 4 &pcfg_pull_none>;
-- };
-- };
--
-- i2c0 {
-- /omit-if-no-ref/
-- i2c0m1_xfer: i2c0m1-xfer {
-- rockchip,pins =
-- /* i2c0_scl_m1 */
-- <4 RK_PC5 9 &pcfg_pull_none_smt>,
-- /* i2c0_sda_m1 */
-- <4 RK_PC6 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c2 {
-- /omit-if-no-ref/
-- i2c2m1_xfer: i2c2m1-xfer {
-- rockchip,pins =
-- /* i2c2_scl_m1 */
-- <2 RK_PC1 9 &pcfg_pull_none_smt>,
-- /* i2c2_sda_m1 */
-- <2 RK_PC0 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c3 {
-- /omit-if-no-ref/
-- i2c3m3_xfer: i2c3m3-xfer {
-- rockchip,pins =
-- /* i2c3_scl_m3 */
-- <2 RK_PB2 9 &pcfg_pull_none_smt>,
-- /* i2c3_sda_m3 */
-- <2 RK_PB3 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c4 {
-- /omit-if-no-ref/
-- i2c4m1_xfer: i2c4m1-xfer {
-- rockchip,pins =
-- /* i2c4_scl_m1 */
-- <2 RK_PB5 9 &pcfg_pull_none_smt>,
-- /* i2c4_sda_m1 */
-- <2 RK_PB4 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c5 {
-- /omit-if-no-ref/
-- i2c5m4_xfer: i2c5m4-xfer {
-- rockchip,pins =
-- /* i2c5_scl_m4 */
-- <2 RK_PB6 9 &pcfg_pull_none_smt>,
-- /* i2c5_sda_m4 */
-- <2 RK_PB7 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c6 {
-- /omit-if-no-ref/
-- i2c6m2_xfer: i2c6m2-xfer {
-- rockchip,pins =
-- /* i2c6_scl_m2 */
-- <2 RK_PC3 9 &pcfg_pull_none_smt>,
-- /* i2c6_sda_m2 */
-- <2 RK_PC2 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c7 {
-- /omit-if-no-ref/
-- i2c7m1_xfer: i2c7m1-xfer {
-- rockchip,pins =
-- /* i2c7_scl_m1 */
-- <4 RK_PC3 9 &pcfg_pull_none_smt>,
-- /* i2c7_sda_m1 */
-- <4 RK_PC4 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c8 {
-- /omit-if-no-ref/
-- i2c8m1_xfer: i2c8m1-xfer {
-- rockchip,pins =
-- /* i2c8_scl_m1 */
-- <2 RK_PB0 9 &pcfg_pull_none_smt>,
-- /* i2c8_sda_m1 */
-- <2 RK_PB1 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2s2 {
-- /omit-if-no-ref/
-- i2s2m0_lrck: i2s2m0-lrck {
-- rockchip,pins =
-- /* i2s2m0_lrck */
-- <2 RK_PC0 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m0_mclk: i2s2m0-mclk {
-- rockchip,pins =
-- /* i2s2m0_mclk */
-- <2 RK_PB6 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m0_sclk: i2s2m0-sclk {
-- rockchip,pins =
-- /* i2s2m0_sclk */
-- <2 RK_PB7 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m0_sdi: i2s2m0-sdi {
-- rockchip,pins =
-- /* i2s2m0_sdi */
-- <2 RK_PC3 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m0_sdo: i2s2m0-sdo {
-- rockchip,pins =
-- /* i2s2m0_sdo */
-- <4 RK_PC3 2 &pcfg_pull_none>;
-- };
-- };
--
-- pwm2 {
-- /omit-if-no-ref/
-- pwm2m2_pins: pwm2m2-pins {
-- rockchip,pins =
-- /* pwm2_m2 */
-- <4 RK_PC2 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm4 {
-- /omit-if-no-ref/
-- pwm4m1_pins: pwm4m1-pins {
-- rockchip,pins =
-- /* pwm4_m1 */
-- <4 RK_PC3 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm5 {
-- /omit-if-no-ref/
-- pwm5m2_pins: pwm5m2-pins {
-- rockchip,pins =
-- /* pwm5_m2 */
-- <4 RK_PC4 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm6 {
-- /omit-if-no-ref/
-- pwm6m2_pins: pwm6m2-pins {
-- rockchip,pins =
-- /* pwm6_m2 */
-- <4 RK_PC5 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm7 {
-- /omit-if-no-ref/
-- pwm7m3_pins: pwm7m3-pins {
-- rockchip,pins =
-- /* pwm7_ir_m3 */
-- <4 RK_PC6 11 &pcfg_pull_none>;
-- };
-- };
--
-- sdio {
-- /omit-if-no-ref/
-- sdiom0_pins: sdiom0-pins {
-- rockchip,pins =
-- /* sdio_clk_m0 */
-- <2 RK_PB3 2 &pcfg_pull_none>,
-- /* sdio_cmd_m0 */
-- <2 RK_PB2 2 &pcfg_pull_none>,
-- /* sdio_d0_m0 */
-- <2 RK_PA6 2 &pcfg_pull_none>,
-- /* sdio_d1_m0 */
-- <2 RK_PA7 2 &pcfg_pull_none>,
-- /* sdio_d2_m0 */
-- <2 RK_PB0 2 &pcfg_pull_none>,
-- /* sdio_d3_m0 */
-- <2 RK_PB1 2 &pcfg_pull_none>;
-- };
-- };
--
-- spi1 {
-- /omit-if-no-ref/
-- spi1m0_pins: spi1m0-pins {
-- rockchip,pins =
-- /* spi1_clk_m0 */
-- <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
-- /* spi1_miso_m0 */
-- <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
-- /* spi1_mosi_m0 */
-- <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi1m0_cs0: spi1m0-cs0 {
-- rockchip,pins =
-- /* spi1_cs0_m0 */
-- <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi1m0_cs1: spi1m0-cs1 {
-- rockchip,pins =
-- /* spi1_cs1_m0 */
-- <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
-- };
-- };
--
-- spi3 {
-- /omit-if-no-ref/
-- spi3m0_pins: spi3m0-pins {
-- rockchip,pins =
-- /* spi3_clk_m0 */
-- <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
-- /* spi3_miso_m0 */
-- <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
-- /* spi3_mosi_m0 */
-- <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m0_cs0: spi3m0-cs0 {
-- rockchip,pins =
-- /* spi3_cs0_m0 */
-- <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m0_cs1: spi3m0-cs1 {
-- rockchip,pins =
-- /* spi3_cs1_m0 */
-- <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
-- };
-- };
--
-- uart1 {
-- /omit-if-no-ref/
-- uart1m0_xfer: uart1m0-xfer {
-- rockchip,pins =
-- /* uart1_rx_m0 */
-- <2 RK_PB6 10 &pcfg_pull_up>,
-- /* uart1_tx_m0 */
-- <2 RK_PB7 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart1m0_ctsn: uart1m0-ctsn {
-- rockchip,pins =
-- /* uart1m0_ctsn */
-- <2 RK_PC1 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart1m0_rtsn: uart1m0-rtsn {
-- rockchip,pins =
-- /* uart1m0_rtsn */
-- <2 RK_PC0 10 &pcfg_pull_none>;
-- };
-- };
--
-- uart6 {
-- /omit-if-no-ref/
-- uart6m0_xfer: uart6m0-xfer {
-- rockchip,pins =
-- /* uart6_rx_m0 */
-- <2 RK_PA6 10 &pcfg_pull_up>,
-- /* uart6_tx_m0 */
-- <2 RK_PA7 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart6m0_ctsn: uart6m0-ctsn {
-- rockchip,pins =
-- /* uart6m0_ctsn */
-- <2 RK_PB1 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart6m0_rtsn: uart6m0-rtsn {
-- rockchip,pins =
-- /* uart6m0_rtsn */
-- <2 RK_PB0 10 &pcfg_pull_none>;
-- };
-- };
--
-- uart7 {
-- /omit-if-no-ref/
-- uart7m0_xfer: uart7m0-xfer {
-- rockchip,pins =
-- /* uart7_rx_m0 */
-- <2 RK_PB4 10 &pcfg_pull_up>,
-- /* uart7_tx_m0 */
-- <2 RK_PB5 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart7m0_ctsn: uart7m0-ctsn {
-- rockchip,pins =
-- /* uart7m0_ctsn */
-- <4 RK_PC6 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart7m0_rtsn: uart7m0-rtsn {
-- rockchip,pins =
-- /* uart7m0_rtsn */
-- <4 RK_PC2 10 &pcfg_pull_none>;
-- };
-- };
--
-- uart9 {
-- /omit-if-no-ref/
-- uart9m0_xfer: uart9m0-xfer {
-- rockchip,pins =
-- /* uart9_rx_m0 */
-- <2 RK_PC4 10 &pcfg_pull_up>,
-- /* uart9_tx_m0 */
-- <2 RK_PC2 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart9m0_ctsn: uart9m0-ctsn {
-- rockchip,pins =
-- /* uart9m0_ctsn */
-- <4 RK_PC5 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart9m0_rtsn: uart9m0-rtsn {
-- rockchip,pins =
-- /* uart9m0_rtsn */
-- <4 RK_PC4 10 &pcfg_pull_none>;
-- };
-- };
--};
---- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
-+++ /dev/null
-@@ -1,3447 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
--/*
-- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-- */
--
--#include <dt-bindings/pinctrl/rockchip.h>
--#include "rockchip-pinconf.dtsi"
--
--/*
-- * This file is auto generated by pin2dts tool, please keep these code
-- * by adding changes at end of this file.
-- */
--&pinctrl {
-- auddsm {
-- /omit-if-no-ref/
-- auddsm_pins: auddsm-pins {
-- rockchip,pins =
-- /* auddsm_ln */
-- <3 RK_PA1 4 &pcfg_pull_none>,
-- /* auddsm_lp */
-- <3 RK_PA2 4 &pcfg_pull_none>,
-- /* auddsm_rn */
-- <3 RK_PA3 4 &pcfg_pull_none>,
-- /* auddsm_rp */
-- <3 RK_PA4 4 &pcfg_pull_none>;
-- };
-- };
--
-- bt1120 {
-- /omit-if-no-ref/
-- bt1120_pins: bt1120-pins {
-- rockchip,pins =
-- /* bt1120_clkout */
-- <4 RK_PB0 2 &pcfg_pull_none>,
-- /* bt1120_d0 */
-- <4 RK_PA0 2 &pcfg_pull_none>,
-- /* bt1120_d1 */
-- <4 RK_PA1 2 &pcfg_pull_none>,
-- /* bt1120_d2 */
-- <4 RK_PA2 2 &pcfg_pull_none>,
-- /* bt1120_d3 */
-- <4 RK_PA3 2 &pcfg_pull_none>,
-- /* bt1120_d4 */
-- <4 RK_PA4 2 &pcfg_pull_none>,
-- /* bt1120_d5 */
-- <4 RK_PA5 2 &pcfg_pull_none>,
-- /* bt1120_d6 */
-- <4 RK_PA6 2 &pcfg_pull_none>,
-- /* bt1120_d7 */
-- <4 RK_PA7 2 &pcfg_pull_none>,
-- /* bt1120_d8 */
-- <4 RK_PB2 2 &pcfg_pull_none>,
-- /* bt1120_d9 */
-- <4 RK_PB3 2 &pcfg_pull_none>,
-- /* bt1120_d10 */
-- <4 RK_PB4 2 &pcfg_pull_none>,
-- /* bt1120_d11 */
-- <4 RK_PB5 2 &pcfg_pull_none>,
-- /* bt1120_d12 */
-- <4 RK_PB6 2 &pcfg_pull_none>,
-- /* bt1120_d13 */
-- <4 RK_PB7 2 &pcfg_pull_none>,
-- /* bt1120_d14 */
-- <4 RK_PC0 2 &pcfg_pull_none>,
-- /* bt1120_d15 */
-- <4 RK_PC1 2 &pcfg_pull_none>;
-- };
-- };
--
-- can0 {
-- /omit-if-no-ref/
-- can0m0_pins: can0m0-pins {
-- rockchip,pins =
-- /* can0_rx_m0 */
-- <0 RK_PC0 11 &pcfg_pull_none>,
-- /* can0_tx_m0 */
-- <0 RK_PB7 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- can0m1_pins: can0m1-pins {
-- rockchip,pins =
-- /* can0_rx_m1 */
-- <4 RK_PD5 9 &pcfg_pull_none>,
-- /* can0_tx_m1 */
-- <4 RK_PD4 9 &pcfg_pull_none>;
-- };
-- };
--
-- can1 {
-- /omit-if-no-ref/
-- can1m0_pins: can1m0-pins {
-- rockchip,pins =
-- /* can1_rx_m0 */
-- <3 RK_PB5 9 &pcfg_pull_none>,
-- /* can1_tx_m0 */
-- <3 RK_PB6 9 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- can1m1_pins: can1m1-pins {
-- rockchip,pins =
-- /* can1_rx_m1 */
-- <4 RK_PB2 12 &pcfg_pull_none>,
-- /* can1_tx_m1 */
-- <4 RK_PB3 12 &pcfg_pull_none>;
-- };
-- };
--
-- can2 {
-- /omit-if-no-ref/
-- can2m0_pins: can2m0-pins {
-- rockchip,pins =
-- /* can2_rx_m0 */
-- <3 RK_PC4 9 &pcfg_pull_none>,
-- /* can2_tx_m0 */
-- <3 RK_PC5 9 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- can2m1_pins: can2m1-pins {
-- rockchip,pins =
-- /* can2_rx_m1 */
-- <0 RK_PD4 10 &pcfg_pull_none>,
-- /* can2_tx_m1 */
-- <0 RK_PD5 10 &pcfg_pull_none>;
-- };
-- };
--
-- cif {
-- /omit-if-no-ref/
-- cif_clk: cif-clk {
-- rockchip,pins =
-- /* cif_clkout */
-- <4 RK_PB4 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- cif_dvp_clk: cif-dvp-clk {
-- rockchip,pins =
-- /* cif_clkin */
-- <4 RK_PB0 1 &pcfg_pull_none>,
-- /* cif_href */
-- <4 RK_PB2 1 &pcfg_pull_none>,
-- /* cif_vsync */
-- <4 RK_PB3 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- cif_dvp_bus16: cif-dvp-bus16 {
-- rockchip,pins =
-- /* cif_d8 */
-- <3 RK_PC4 1 &pcfg_pull_none>,
-- /* cif_d9 */
-- <3 RK_PC5 1 &pcfg_pull_none>,
-- /* cif_d10 */
-- <3 RK_PC6 1 &pcfg_pull_none>,
-- /* cif_d11 */
-- <3 RK_PC7 1 &pcfg_pull_none>,
-- /* cif_d12 */
-- <3 RK_PD0 1 &pcfg_pull_none>,
-- /* cif_d13 */
-- <3 RK_PD1 1 &pcfg_pull_none>,
-- /* cif_d14 */
-- <3 RK_PD2 1 &pcfg_pull_none>,
-- /* cif_d15 */
-- <3 RK_PD3 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- cif_dvp_bus8: cif-dvp-bus8 {
-- rockchip,pins =
-- /* cif_d0 */
-- <4 RK_PA0 1 &pcfg_pull_none>,
-- /* cif_d1 */
-- <4 RK_PA1 1 &pcfg_pull_none>,
-- /* cif_d2 */
-- <4 RK_PA2 1 &pcfg_pull_none>,
-- /* cif_d3 */
-- <4 RK_PA3 1 &pcfg_pull_none>,
-- /* cif_d4 */
-- <4 RK_PA4 1 &pcfg_pull_none>,
-- /* cif_d5 */
-- <4 RK_PA5 1 &pcfg_pull_none>,
-- /* cif_d6 */
-- <4 RK_PA6 1 &pcfg_pull_none>,
-- /* cif_d7 */
-- <4 RK_PA7 1 &pcfg_pull_none>;
-- };
-- };
--
-- clk32k {
-- /omit-if-no-ref/
-- clk32k_in: clk32k-in {
-- rockchip,pins =
-- /* clk32k_in */
-- <0 RK_PB2 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- clk32k_out0: clk32k-out0 {
-- rockchip,pins =
-- /* clk32k_out0 */
-- <0 RK_PB2 2 &pcfg_pull_none>;
-- };
-- };
--
-- cpu {
-- /omit-if-no-ref/
-- cpu_pins: cpu-pins {
-- rockchip,pins =
-- /* cpu_big0_avs */
-- <0 RK_PD1 2 &pcfg_pull_none>,
-- /* cpu_big1_avs */
-- <0 RK_PD5 2 &pcfg_pull_none>;
-- };
-- };
--
-- ddrphych0 {
-- /omit-if-no-ref/
-- ddrphych0_pins: ddrphych0-pins {
-- rockchip,pins =
-- /* ddrphych0_dtb0 */
-- <4 RK_PA0 7 &pcfg_pull_none>,
-- /* ddrphych0_dtb1 */
-- <4 RK_PA1 7 &pcfg_pull_none>,
-- /* ddrphych0_dtb2 */
-- <4 RK_PA2 7 &pcfg_pull_none>,
-- /* ddrphych0_dtb3 */
-- <4 RK_PA3 7 &pcfg_pull_none>;
-- };
-- };
--
-- ddrphych1 {
-- /omit-if-no-ref/
-- ddrphych1_pins: ddrphych1-pins {
-- rockchip,pins =
-- /* ddrphych1_dtb0 */
-- <4 RK_PA4 7 &pcfg_pull_none>,
-- /* ddrphych1_dtb1 */
-- <4 RK_PA5 7 &pcfg_pull_none>,
-- /* ddrphych1_dtb2 */
-- <4 RK_PA6 7 &pcfg_pull_none>,
-- /* ddrphych1_dtb3 */
-- <4 RK_PA7 7 &pcfg_pull_none>;
-- };
-- };
--
-- ddrphych2 {
-- /omit-if-no-ref/
-- ddrphych2_pins: ddrphych2-pins {
-- rockchip,pins =
-- /* ddrphych2_dtb0 */
-- <4 RK_PB0 7 &pcfg_pull_none>,
-- /* ddrphych2_dtb1 */
-- <4 RK_PB1 7 &pcfg_pull_none>,
-- /* ddrphych2_dtb2 */
-- <4 RK_PB2 7 &pcfg_pull_none>,
-- /* ddrphych2_dtb3 */
-- <4 RK_PB3 7 &pcfg_pull_none>;
-- };
-- };
--
-- ddrphych3 {
-- /omit-if-no-ref/
-- ddrphych3_pins: ddrphych3-pins {
-- rockchip,pins =
-- /* ddrphych3_dtb0 */
-- <4 RK_PB4 7 &pcfg_pull_none>,
-- /* ddrphych3_dtb1 */
-- <4 RK_PB5 7 &pcfg_pull_none>,
-- /* ddrphych3_dtb2 */
-- <4 RK_PB6 7 &pcfg_pull_none>,
-- /* ddrphych3_dtb3 */
-- <4 RK_PB7 7 &pcfg_pull_none>;
-- };
-- };
--
-- dp0 {
-- /omit-if-no-ref/
-- dp0m0_pins: dp0m0-pins {
-- rockchip,pins =
-- /* dp0_hpdin_m0 */
-- <4 RK_PB4 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- dp0m1_pins: dp0m1-pins {
-- rockchip,pins =
-- /* dp0_hpdin_m1 */
-- <0 RK_PC4 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- dp0m2_pins: dp0m2-pins {
-- rockchip,pins =
-- /* dp0_hpdin_m2 */
-- <1 RK_PA0 5 &pcfg_pull_none>;
-- };
-- };
--
-- dp1 {
-- /omit-if-no-ref/
-- dp1m0_pins: dp1m0-pins {
-- rockchip,pins =
-- /* dp1_hpdin_m0 */
-- <3 RK_PD5 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- dp1m1_pins: dp1m1-pins {
-- rockchip,pins =
-- /* dp1_hpdin_m1 */
-- <0 RK_PC5 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- dp1m2_pins: dp1m2-pins {
-- rockchip,pins =
-- /* dp1_hpdin_m2 */
-- <1 RK_PA1 5 &pcfg_pull_none>;
-- };
-- };
--
-- emmc {
-- /omit-if-no-ref/
-- emmc_rstnout: emmc-rstnout {
-- rockchip,pins =
-- /* emmc_rstn */
-- <2 RK_PA3 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- emmc_bus8: emmc-bus8 {
-- rockchip,pins =
-- /* emmc_d0 */
-- <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
-- /* emmc_d1 */
-- <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
-- /* emmc_d2 */
-- <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
-- /* emmc_d3 */
-- <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
-- /* emmc_d4 */
-- <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
-- /* emmc_d5 */
-- <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
-- /* emmc_d6 */
-- <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
-- /* emmc_d7 */
-- <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- emmc_clk: emmc-clk {
-- rockchip,pins =
-- /* emmc_clkout */
-- <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- emmc_cmd: emmc-cmd {
-- rockchip,pins =
-- /* emmc_cmd */
-- <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- emmc_data_strobe: emmc-data-strobe {
-- rockchip,pins =
-- /* emmc_data_strobe */
-- <2 RK_PA2 1 &pcfg_pull_down>;
-- };
-- };
--
-- eth1 {
-- /omit-if-no-ref/
-- eth1_pins: eth1-pins {
-- rockchip,pins =
-- /* eth1_refclko_25m */
-- <3 RK_PA6 1 &pcfg_pull_none>;
-- };
-- };
--
-- fspi {
-- /omit-if-no-ref/
-- fspim0_pins: fspim0-pins {
-- rockchip,pins =
-- /* fspi_clk_m0 */
-- <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
-- /* fspi_cs0n_m0 */
-- <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d0_m0 */
-- <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d1_m0 */
-- <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d2_m0 */
-- <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d3_m0 */
-- <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- fspim0_cs1: fspim0-cs1 {
-- rockchip,pins =
-- /* fspi_cs1n_m0 */
-- <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- fspim2_pins: fspim2-pins {
-- rockchip,pins =
-- /* fspi_clk_m2 */
-- <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
-- /* fspi_cs0n_m2 */
-- <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d0_m2 */
-- <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d1_m2 */
-- <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d2_m2 */
-- <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
-- /* fspi_d3_m2 */
-- <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- fspim2_cs1: fspim2-cs1 {
-- rockchip,pins =
-- /* fspi_cs1n_m2 */
-- <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
-- };
-- };
--
-- gmac1 {
-- /omit-if-no-ref/
-- gmac1_miim: gmac1-miim {
-- rockchip,pins =
-- /* gmac1_mdc */
-- <3 RK_PC2 1 &pcfg_pull_none>,
-- /* gmac1_mdio */
-- <3 RK_PC3 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac1_clkinout: gmac1-clkinout {
-- rockchip,pins =
-- /* gmac1_mclkinout */
-- <3 RK_PB6 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac1_rx_bus2: gmac1-rx-bus2 {
-- rockchip,pins =
-- /* gmac1_rxd0 */
-- <3 RK_PA7 1 &pcfg_pull_none>,
-- /* gmac1_rxd1 */
-- <3 RK_PB0 1 &pcfg_pull_none>,
-- /* gmac1_rxdv_crs */
-- <3 RK_PB1 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac1_tx_bus2: gmac1-tx-bus2 {
-- rockchip,pins =
-- /* gmac1_txd0 */
-- <3 RK_PB3 1 &pcfg_pull_none>,
-- /* gmac1_txd1 */
-- <3 RK_PB4 1 &pcfg_pull_none>,
-- /* gmac1_txen */
-- <3 RK_PB5 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac1_rgmii_clk: gmac1-rgmii-clk {
-- rockchip,pins =
-- /* gmac1_rxclk */
-- <3 RK_PA5 1 &pcfg_pull_none>,
-- /* gmac1_txclk */
-- <3 RK_PA4 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac1_rgmii_bus: gmac1-rgmii-bus {
-- rockchip,pins =
-- /* gmac1_rxd2 */
-- <3 RK_PA2 1 &pcfg_pull_none>,
-- /* gmac1_rxd3 */
-- <3 RK_PA3 1 &pcfg_pull_none>,
-- /* gmac1_txd2 */
-- <3 RK_PA0 1 &pcfg_pull_none>,
-- /* gmac1_txd3 */
-- <3 RK_PA1 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac1_ppsclk: gmac1-ppsclk {
-- rockchip,pins =
-- /* gmac1_ppsclk */
-- <3 RK_PC1 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac1_ppstrig: gmac1-ppstrig {
-- rockchip,pins =
-- /* gmac1_ppstrig */
-- <3 RK_PC0 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
-- rockchip,pins =
-- /* gmac1_ptp_ref_clk */
-- <3 RK_PB7 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- gmac1_txer: gmac1-txer {
-- rockchip,pins =
-- /* gmac1_txer */
-- <3 RK_PB2 1 &pcfg_pull_none>;
-- };
-- };
--
-- gpu {
-- /omit-if-no-ref/
-- gpu_pins: gpu-pins {
-- rockchip,pins =
-- /* gpu_avs */
-- <0 RK_PC5 2 &pcfg_pull_none>;
-- };
-- };
--
-- hdmi {
-- /omit-if-no-ref/
-- hdmim0_rx_cec: hdmim0-rx-cec {
-- rockchip,pins =
-- /* hdmim0_rx_cec */
-- <4 RK_PB5 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_rx_hpdin: hdmim0-rx-hpdin {
-- rockchip,pins =
-- /* hdmim0_rx_hpdin */
-- <4 RK_PB6 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_rx_scl: hdmim0-rx-scl {
-- rockchip,pins =
-- /* hdmim0_rx_scl */
-- <0 RK_PD2 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_rx_sda: hdmim0-rx-sda {
-- rockchip,pins =
-- /* hdmim0_rx_sda */
-- <0 RK_PD1 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_tx0_cec: hdmim0-tx0-cec {
-- rockchip,pins =
-- /* hdmim0_tx0_cec */
-- <4 RK_PC1 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_tx0_hpd: hdmim0-tx0-hpd {
-- rockchip,pins =
-- /* hdmim0_tx0_hpd */
-- <1 RK_PA5 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_tx0_scl: hdmim0-tx0-scl {
-- rockchip,pins =
-- /* hdmim0_tx0_scl */
-- <4 RK_PB7 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_tx0_sda: hdmim0-tx0-sda {
-- rockchip,pins =
-- /* hdmim0_tx0_sda */
-- <4 RK_PC0 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim0_tx1_hpd: hdmim0-tx1-hpd {
-- rockchip,pins =
-- /* hdmim0_tx1_hpd */
-- <1 RK_PA6 5 &pcfg_pull_none>;
-- };
-- /omit-if-no-ref/
-- hdmim1_rx_cec: hdmim1-rx-cec {
-- rockchip,pins =
-- /* hdmim1_rx_cec */
-- <3 RK_PD1 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_rx_hpdin: hdmim1-rx-hpdin {
-- rockchip,pins =
-- /* hdmim1_rx_hpdin */
-- <3 RK_PD4 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_rx_scl: hdmim1-rx-scl {
-- rockchip,pins =
-- /* hdmim1_rx_scl */
-- <3 RK_PD2 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_rx_sda: hdmim1-rx-sda {
-- rockchip,pins =
-- /* hdmim1_rx_sda */
-- <3 RK_PD3 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_tx0_cec: hdmim1-tx0-cec {
-- rockchip,pins =
-- /* hdmim1_tx0_cec */
-- <0 RK_PD1 13 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_tx0_hpd: hdmim1-tx0-hpd {
-- rockchip,pins =
-- /* hdmim1_tx0_hpd */
-- <3 RK_PD4 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_tx0_scl: hdmim1-tx0-scl {
-- rockchip,pins =
-- /* hdmim1_tx0_scl */
-- <0 RK_PD5 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_tx0_sda: hdmim1-tx0-sda {
-- rockchip,pins =
-- /* hdmim1_tx0_sda */
-- <0 RK_PD4 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_tx1_cec: hdmim1-tx1-cec {
-- rockchip,pins =
-- /* hdmim1_tx1_cec */
-- <0 RK_PD2 13 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_tx1_hpd: hdmim1-tx1-hpd {
-- rockchip,pins =
-- /* hdmim1_tx1_hpd */
-- <3 RK_PB7 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_tx1_scl: hdmim1-tx1-scl {
-- rockchip,pins =
-- /* hdmim1_tx1_scl */
-- <3 RK_PC6 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim1_tx1_sda: hdmim1-tx1-sda {
-- rockchip,pins =
-- /* hdmim1_tx1_sda */
-- <3 RK_PC5 5 &pcfg_pull_none>;
-- };
-- /omit-if-no-ref/
-- hdmim2_rx_cec: hdmim2-rx-cec {
-- rockchip,pins =
-- /* hdmim2_rx_cec */
-- <1 RK_PB7 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim2_rx_hpdin: hdmim2-rx-hpdin {
-- rockchip,pins =
-- /* hdmim2_rx_hpdin */
-- <1 RK_PB6 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim2_rx_scl: hdmim2-rx-scl {
-- rockchip,pins =
-- /* hdmim2_rx_scl */
-- <1 RK_PD6 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim2_rx_sda: hdmim2-rx-sda {
-- rockchip,pins =
-- /* hdmim2_rx_sda */
-- <1 RK_PD7 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim2_tx0_scl: hdmim2-tx0-scl {
-- rockchip,pins =
-- /* hdmim2_tx0_scl */
-- <3 RK_PC7 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim2_tx0_sda: hdmim2-tx0-sda {
-- rockchip,pins =
-- /* hdmim2_tx0_sda */
-- <3 RK_PD0 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim2_tx1_cec: hdmim2-tx1-cec {
-- rockchip,pins =
-- /* hdmim2_tx1_cec */
-- <3 RK_PC4 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim2_tx1_scl: hdmim2-tx1-scl {
-- rockchip,pins =
-- /* hdmim2_tx1_scl */
-- <1 RK_PA4 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmim2_tx1_sda: hdmim2-tx1-sda {
-- rockchip,pins =
-- /* hdmim2_tx1_sda */
-- <1 RK_PA3 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmi_debug0: hdmi-debug0 {
-- rockchip,pins =
-- /* hdmi_debug0 */
-- <1 RK_PA7 7 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmi_debug1: hdmi-debug1 {
-- rockchip,pins =
-- /* hdmi_debug1 */
-- <1 RK_PB0 7 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmi_debug2: hdmi-debug2 {
-- rockchip,pins =
-- /* hdmi_debug2 */
-- <1 RK_PB1 7 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmi_debug3: hdmi-debug3 {
-- rockchip,pins =
-- /* hdmi_debug3 */
-- <1 RK_PB2 7 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmi_debug4: hdmi-debug4 {
-- rockchip,pins =
-- /* hdmi_debug4 */
-- <1 RK_PB3 7 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmi_debug5: hdmi-debug5 {
-- rockchip,pins =
-- /* hdmi_debug5 */
-- <1 RK_PB4 7 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- hdmi_debug6: hdmi-debug6 {
-- rockchip,pins =
-- /* hdmi_debug6 */
-- <1 RK_PA0 7 &pcfg_pull_none>;
-- };
-- };
--
-- i2c0 {
-- /omit-if-no-ref/
-- i2c0m0_xfer: i2c0m0-xfer {
-- rockchip,pins =
-- /* i2c0_scl_m0 */
-- <0 RK_PB3 2 &pcfg_pull_none_smt>,
-- /* i2c0_sda_m0 */
-- <0 RK_PA6 2 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c0m2_xfer: i2c0m2-xfer {
-- rockchip,pins =
-- /* i2c0_scl_m2 */
-- <0 RK_PD1 3 &pcfg_pull_none_smt>,
-- /* i2c0_sda_m2 */
-- <0 RK_PD2 3 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c1 {
-- /omit-if-no-ref/
-- i2c1m0_xfer: i2c1m0-xfer {
-- rockchip,pins =
-- /* i2c1_scl_m0 */
-- <0 RK_PB5 9 &pcfg_pull_none_smt>,
-- /* i2c1_sda_m0 */
-- <0 RK_PB6 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c1m1_xfer: i2c1m1-xfer {
-- rockchip,pins =
-- /* i2c1_scl_m1 */
-- <0 RK_PB0 2 &pcfg_pull_none_smt>,
-- /* i2c1_sda_m1 */
-- <0 RK_PB1 2 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c1m2_xfer: i2c1m2-xfer {
-- rockchip,pins =
-- /* i2c1_scl_m2 */
-- <0 RK_PD4 9 &pcfg_pull_none_smt>,
-- /* i2c1_sda_m2 */
-- <0 RK_PD5 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c1m3_xfer: i2c1m3-xfer {
-- rockchip,pins =
-- /* i2c1_scl_m3 */
-- <2 RK_PD4 9 &pcfg_pull_none_smt>,
-- /* i2c1_sda_m3 */
-- <2 RK_PD5 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c1m4_xfer: i2c1m4-xfer {
-- rockchip,pins =
-- /* i2c1_scl_m4 */
-- <1 RK_PD2 9 &pcfg_pull_none_smt>,
-- /* i2c1_sda_m4 */
-- <1 RK_PD3 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c2 {
-- /omit-if-no-ref/
-- i2c2m0_xfer: i2c2m0-xfer {
-- rockchip,pins =
-- /* i2c2_scl_m0 */
-- <0 RK_PB7 9 &pcfg_pull_none_smt>,
-- /* i2c2_sda_m0 */
-- <0 RK_PC0 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c2m2_xfer: i2c2m2-xfer {
-- rockchip,pins =
-- /* i2c2_scl_m2 */
-- <2 RK_PA3 9 &pcfg_pull_none_smt>,
-- /* i2c2_sda_m2 */
-- <2 RK_PA2 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c2m3_xfer: i2c2m3-xfer {
-- rockchip,pins =
-- /* i2c2_scl_m3 */
-- <1 RK_PC5 9 &pcfg_pull_none_smt>,
-- /* i2c2_sda_m3 */
-- <1 RK_PC4 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c2m4_xfer: i2c2m4-xfer {
-- rockchip,pins =
-- /* i2c2_scl_m4 */
-- <1 RK_PA1 9 &pcfg_pull_none_smt>,
-- /* i2c2_sda_m4 */
-- <1 RK_PA0 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c3 {
-- /omit-if-no-ref/
-- i2c3m0_xfer: i2c3m0-xfer {
-- rockchip,pins =
-- /* i2c3_scl_m0 */
-- <1 RK_PC1 9 &pcfg_pull_none_smt>,
-- /* i2c3_sda_m0 */
-- <1 RK_PC0 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c3m1_xfer: i2c3m1-xfer {
-- rockchip,pins =
-- /* i2c3_scl_m1 */
-- <3 RK_PB7 9 &pcfg_pull_none_smt>,
-- /* i2c3_sda_m1 */
-- <3 RK_PC0 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c3m2_xfer: i2c3m2-xfer {
-- rockchip,pins =
-- /* i2c3_scl_m2 */
-- <4 RK_PA4 9 &pcfg_pull_none_smt>,
-- /* i2c3_sda_m2 */
-- <4 RK_PA5 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c3m4_xfer: i2c3m4-xfer {
-- rockchip,pins =
-- /* i2c3_scl_m4 */
-- <4 RK_PD0 9 &pcfg_pull_none_smt>,
-- /* i2c3_sda_m4 */
-- <4 RK_PD1 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c4 {
-- /omit-if-no-ref/
-- i2c4m0_xfer: i2c4m0-xfer {
-- rockchip,pins =
-- /* i2c4_scl_m0 */
-- <3 RK_PA6 9 &pcfg_pull_none_smt>,
-- /* i2c4_sda_m0 */
-- <3 RK_PA5 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c4m2_xfer: i2c4m2-xfer {
-- rockchip,pins =
-- /* i2c4_scl_m2 */
-- <0 RK_PC5 9 &pcfg_pull_none_smt>,
-- /* i2c4_sda_m2 */
-- <0 RK_PC4 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c4m3_xfer: i2c4m3-xfer {
-- rockchip,pins =
-- /* i2c4_scl_m3 */
-- <1 RK_PA3 9 &pcfg_pull_none_smt>,
-- /* i2c4_sda_m3 */
-- <1 RK_PA2 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c4m4_xfer: i2c4m4-xfer {
-- rockchip,pins =
-- /* i2c4_scl_m4 */
-- <1 RK_PC7 9 &pcfg_pull_none_smt>,
-- /* i2c4_sda_m4 */
-- <1 RK_PC6 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c5 {
-- /omit-if-no-ref/
-- i2c5m0_xfer: i2c5m0-xfer {
-- rockchip,pins =
-- /* i2c5_scl_m0 */
-- <3 RK_PC7 9 &pcfg_pull_none_smt>,
-- /* i2c5_sda_m0 */
-- <3 RK_PD0 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c5m1_xfer: i2c5m1-xfer {
-- rockchip,pins =
-- /* i2c5_scl_m1 */
-- <4 RK_PB6 9 &pcfg_pull_none_smt>,
-- /* i2c5_sda_m1 */
-- <4 RK_PB7 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c5m2_xfer: i2c5m2-xfer {
-- rockchip,pins =
-- /* i2c5_scl_m2 */
-- <4 RK_PA6 9 &pcfg_pull_none_smt>,
-- /* i2c5_sda_m2 */
-- <4 RK_PA7 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c5m3_xfer: i2c5m3-xfer {
-- rockchip,pins =
-- /* i2c5_scl_m3 */
-- <1 RK_PB6 9 &pcfg_pull_none_smt>,
-- /* i2c5_sda_m3 */
-- <1 RK_PB7 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c6 {
-- /omit-if-no-ref/
-- i2c6m0_xfer: i2c6m0-xfer {
-- rockchip,pins =
-- /* i2c6_scl_m0 */
-- <0 RK_PD0 9 &pcfg_pull_none_smt>,
-- /* i2c6_sda_m0 */
-- <0 RK_PC7 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c6m1_xfer: i2c6m1-xfer {
-- rockchip,pins =
-- /* i2c6_scl_m1 */
-- <1 RK_PC3 9 &pcfg_pull_none_smt>,
-- /* i2c6_sda_m1 */
-- <1 RK_PC2 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c6m3_xfer: i2c6m3-xfer {
-- rockchip,pins =
-- /* i2c6_scl_m3 */
-- <4 RK_PB1 9 &pcfg_pull_none_smt>,
-- /* i2c6_sda_m3 */
-- <4 RK_PB0 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c6m4_xfer: i2c6m4-xfer {
-- rockchip,pins =
-- /* i2c6_scl_m4 */
-- <3 RK_PA1 9 &pcfg_pull_none_smt>,
-- /* i2c6_sda_m4 */
-- <3 RK_PA0 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c7 {
-- /omit-if-no-ref/
-- i2c7m0_xfer: i2c7m0-xfer {
-- rockchip,pins =
-- /* i2c7_scl_m0 */
-- <1 RK_PD0 9 &pcfg_pull_none_smt>,
-- /* i2c7_sda_m0 */
-- <1 RK_PD1 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c7m2_xfer: i2c7m2-xfer {
-- rockchip,pins =
-- /* i2c7_scl_m2 */
-- <3 RK_PD2 9 &pcfg_pull_none_smt>,
-- /* i2c7_sda_m2 */
-- <3 RK_PD3 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c7m3_xfer: i2c7m3-xfer {
-- rockchip,pins =
-- /* i2c7_scl_m3 */
-- <4 RK_PB2 9 &pcfg_pull_none_smt>,
-- /* i2c7_sda_m3 */
-- <4 RK_PB3 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2c8 {
-- /omit-if-no-ref/
-- i2c8m0_xfer: i2c8m0-xfer {
-- rockchip,pins =
-- /* i2c8_scl_m0 */
-- <4 RK_PD2 9 &pcfg_pull_none_smt>,
-- /* i2c8_sda_m0 */
-- <4 RK_PD3 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c8m2_xfer: i2c8m2-xfer {
-- rockchip,pins =
-- /* i2c8_scl_m2 */
-- <1 RK_PD6 9 &pcfg_pull_none_smt>,
-- /* i2c8_sda_m2 */
-- <1 RK_PD7 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c8m3_xfer: i2c8m3-xfer {
-- rockchip,pins =
-- /* i2c8_scl_m3 */
-- <4 RK_PC0 9 &pcfg_pull_none_smt>,
-- /* i2c8_sda_m3 */
-- <4 RK_PC1 9 &pcfg_pull_none_smt>;
-- };
--
-- /omit-if-no-ref/
-- i2c8m4_xfer: i2c8m4-xfer {
-- rockchip,pins =
-- /* i2c8_scl_m4 */
-- <3 RK_PC2 9 &pcfg_pull_none_smt>,
-- /* i2c8_sda_m4 */
-- <3 RK_PC3 9 &pcfg_pull_none_smt>;
-- };
-- };
--
-- i2s0 {
-- /omit-if-no-ref/
-- i2s0_lrck: i2s0-lrck {
-- rockchip,pins =
-- /* i2s0_lrck */
-- <1 RK_PC5 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_mclk: i2s0-mclk {
-- rockchip,pins =
-- /* i2s0_mclk */
-- <1 RK_PC2 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_sclk: i2s0-sclk {
-- rockchip,pins =
-- /* i2s0_sclk */
-- <1 RK_PC3 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_sdi0: i2s0-sdi0 {
-- rockchip,pins =
-- /* i2s0_sdi0 */
-- <1 RK_PD4 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_sdi1: i2s0-sdi1 {
-- rockchip,pins =
-- /* i2s0_sdi1 */
-- <1 RK_PD3 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_sdi2: i2s0-sdi2 {
-- rockchip,pins =
-- /* i2s0_sdi2 */
-- <1 RK_PD2 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_sdi3: i2s0-sdi3 {
-- rockchip,pins =
-- /* i2s0_sdi3 */
-- <1 RK_PD1 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_sdo0: i2s0-sdo0 {
-- rockchip,pins =
-- /* i2s0_sdo0 */
-- <1 RK_PC7 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_sdo1: i2s0-sdo1 {
-- rockchip,pins =
-- /* i2s0_sdo1 */
-- <1 RK_PD0 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_sdo2: i2s0-sdo2 {
-- rockchip,pins =
-- /* i2s0_sdo2 */
-- <1 RK_PD1 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s0_sdo3: i2s0-sdo3 {
-- rockchip,pins =
-- /* i2s0_sdo3 */
-- <1 RK_PD2 1 &pcfg_pull_none>;
-- };
-- };
--
-- i2s1 {
-- /omit-if-no-ref/
-- i2s1m0_lrck: i2s1m0-lrck {
-- rockchip,pins =
-- /* i2s1m0_lrck */
-- <4 RK_PA2 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_mclk: i2s1m0-mclk {
-- rockchip,pins =
-- /* i2s1m0_mclk */
-- <4 RK_PA0 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_sclk: i2s1m0-sclk {
-- rockchip,pins =
-- /* i2s1m0_sclk */
-- <4 RK_PA1 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_sdi0: i2s1m0-sdi0 {
-- rockchip,pins =
-- /* i2s1m0_sdi0 */
-- <4 RK_PA5 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_sdi1: i2s1m0-sdi1 {
-- rockchip,pins =
-- /* i2s1m0_sdi1 */
-- <4 RK_PA6 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_sdi2: i2s1m0-sdi2 {
-- rockchip,pins =
-- /* i2s1m0_sdi2 */
-- <4 RK_PA7 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_sdi3: i2s1m0-sdi3 {
-- rockchip,pins =
-- /* i2s1m0_sdi3 */
-- <4 RK_PB0 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_sdo0: i2s1m0-sdo0 {
-- rockchip,pins =
-- /* i2s1m0_sdo0 */
-- <4 RK_PB1 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_sdo1: i2s1m0-sdo1 {
-- rockchip,pins =
-- /* i2s1m0_sdo1 */
-- <4 RK_PB2 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_sdo2: i2s1m0-sdo2 {
-- rockchip,pins =
-- /* i2s1m0_sdo2 */
-- <4 RK_PB3 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m0_sdo3: i2s1m0-sdo3 {
-- rockchip,pins =
-- /* i2s1m0_sdo3 */
-- <4 RK_PB4 3 &pcfg_pull_none>;
-- };
-- /omit-if-no-ref/
-- i2s1m1_lrck: i2s1m1-lrck {
-- rockchip,pins =
-- /* i2s1m1_lrck */
-- <0 RK_PB7 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_mclk: i2s1m1-mclk {
-- rockchip,pins =
-- /* i2s1m1_mclk */
-- <0 RK_PB5 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_sclk: i2s1m1-sclk {
-- rockchip,pins =
-- /* i2s1m1_sclk */
-- <0 RK_PB6 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_sdi0: i2s1m1-sdi0 {
-- rockchip,pins =
-- /* i2s1m1_sdi0 */
-- <0 RK_PC5 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_sdi1: i2s1m1-sdi1 {
-- rockchip,pins =
-- /* i2s1m1_sdi1 */
-- <0 RK_PC6 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_sdi2: i2s1m1-sdi2 {
-- rockchip,pins =
-- /* i2s1m1_sdi2 */
-- <0 RK_PC7 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_sdi3: i2s1m1-sdi3 {
-- rockchip,pins =
-- /* i2s1m1_sdi3 */
-- <0 RK_PD0 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_sdo0: i2s1m1-sdo0 {
-- rockchip,pins =
-- /* i2s1m1_sdo0 */
-- <0 RK_PD1 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_sdo1: i2s1m1-sdo1 {
-- rockchip,pins =
-- /* i2s1m1_sdo1 */
-- <0 RK_PD2 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_sdo2: i2s1m1-sdo2 {
-- rockchip,pins =
-- /* i2s1m1_sdo2 */
-- <0 RK_PD4 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s1m1_sdo3: i2s1m1-sdo3 {
-- rockchip,pins =
-- /* i2s1m1_sdo3 */
-- <0 RK_PD5 1 &pcfg_pull_none>;
-- };
-- };
--
-- i2s2 {
-- /omit-if-no-ref/
-- i2s2m0_lrck: i2s2m0-lrck {
-- rockchip,pins =
-- /* i2s2m0_lrck */
-- <2 RK_PC0 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m0_mclk: i2s2m0-mclk {
-- rockchip,pins =
-- /* i2s2m0_mclk */
-- <2 RK_PB6 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m0_sclk: i2s2m0-sclk {
-- rockchip,pins =
-- /* i2s2m0_sclk */
-- <2 RK_PB7 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m0_sdi: i2s2m0-sdi {
-- rockchip,pins =
-- /* i2s2m0_sdi */
-- <2 RK_PC3 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m0_sdo: i2s2m0-sdo {
-- rockchip,pins =
-- /* i2s2m0_sdo */
-- <4 RK_PC3 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m1_lrck: i2s2m1-lrck {
-- rockchip,pins =
-- /* i2s2m1_lrck */
-- <3 RK_PB6 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m1_mclk: i2s2m1-mclk {
-- rockchip,pins =
-- /* i2s2m1_mclk */
-- <3 RK_PB4 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m1_sclk: i2s2m1-sclk {
-- rockchip,pins =
-- /* i2s2m1_sclk */
-- <3 RK_PB5 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m1_sdi: i2s2m1-sdi {
-- rockchip,pins =
-- /* i2s2m1_sdi */
-- <3 RK_PB2 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s2m1_sdo: i2s2m1-sdo {
-- rockchip,pins =
-- /* i2s2m1_sdo */
-- <3 RK_PB3 3 &pcfg_pull_none>;
-- };
-- };
--
-- i2s3 {
-- /omit-if-no-ref/
-- i2s3_lrck: i2s3-lrck {
-- rockchip,pins =
-- /* i2s3_lrck */
-- <3 RK_PA2 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s3_mclk: i2s3-mclk {
-- rockchip,pins =
-- /* i2s3_mclk */
-- <3 RK_PA0 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s3_sclk: i2s3-sclk {
-- rockchip,pins =
-- /* i2s3_sclk */
-- <3 RK_PA1 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s3_sdi: i2s3-sdi {
-- rockchip,pins =
-- /* i2s3_sdi */
-- <3 RK_PA4 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- i2s3_sdo: i2s3-sdo {
-- rockchip,pins =
-- /* i2s3_sdo */
-- <3 RK_PA3 3 &pcfg_pull_none>;
-- };
-- };
--
-- jtag {
-- /omit-if-no-ref/
-- jtagm0_pins: jtagm0-pins {
-- rockchip,pins =
-- /* jtag_tck_m0 */
-- <4 RK_PD2 5 &pcfg_pull_none>,
-- /* jtag_tms_m0 */
-- <4 RK_PD3 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- jtagm1_pins: jtagm1-pins {
-- rockchip,pins =
-- /* jtag_tck_m1 */
-- <4 RK_PD0 5 &pcfg_pull_none>,
-- /* jtag_tms_m1 */
-- <4 RK_PD1 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- jtagm2_pins: jtagm2-pins {
-- rockchip,pins =
-- /* jtag_tck_m2 */
-- <0 RK_PB5 2 &pcfg_pull_none>,
-- /* jtag_tms_m2 */
-- <0 RK_PB6 2 &pcfg_pull_none>;
-- };
-- };
--
-- litcpu {
-- /omit-if-no-ref/
-- litcpu_pins: litcpu-pins {
-- rockchip,pins =
-- /* litcpu_avs */
-- <0 RK_PD3 1 &pcfg_pull_none>;
-- };
-- };
--
-- mcu {
-- /omit-if-no-ref/
-- mcum0_pins: mcum0-pins {
-- rockchip,pins =
-- /* mcu_jtag_tck_m0 */
-- <4 RK_PD4 5 &pcfg_pull_none>,
-- /* mcu_jtag_tms_m0 */
-- <4 RK_PD5 5 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mcum1_pins: mcum1-pins {
-- rockchip,pins =
-- /* mcu_jtag_tck_m1 */
-- <3 RK_PD4 6 &pcfg_pull_none>,
-- /* mcu_jtag_tms_m1 */
-- <3 RK_PD5 6 &pcfg_pull_none>;
-- };
-- };
--
-- mipi {
-- /omit-if-no-ref/
-- mipim0_camera0_clk: mipim0-camera0-clk {
-- rockchip,pins =
-- /* mipim0_camera0_clk */
-- <4 RK_PB1 1 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipim0_camera1_clk: mipim0-camera1-clk {
-- rockchip,pins =
-- /* mipim0_camera1_clk */
-- <1 RK_PB6 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipim0_camera2_clk: mipim0-camera2-clk {
-- rockchip,pins =
-- /* mipim0_camera2_clk */
-- <1 RK_PB7 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipim0_camera3_clk: mipim0-camera3-clk {
-- rockchip,pins =
-- /* mipim0_camera3_clk */
-- <1 RK_PD6 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipim0_camera4_clk: mipim0-camera4-clk {
-- rockchip,pins =
-- /* mipim0_camera4_clk */
-- <1 RK_PD7 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipim1_camera0_clk: mipim1-camera0-clk {
-- rockchip,pins =
-- /* mipim1_camera0_clk */
-- <3 RK_PA5 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipim1_camera1_clk: mipim1-camera1-clk {
-- rockchip,pins =
-- /* mipim1_camera1_clk */
-- <3 RK_PA6 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipim1_camera2_clk: mipim1-camera2-clk {
-- rockchip,pins =
-- /* mipim1_camera2_clk */
-- <3 RK_PA7 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipim1_camera3_clk: mipim1-camera3-clk {
-- rockchip,pins =
-- /* mipim1_camera3_clk */
-- <3 RK_PB0 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipim1_camera4_clk: mipim1-camera4-clk {
-- rockchip,pins =
-- /* mipim1_camera4_clk */
-- <3 RK_PB1 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipi_te0: mipi-te0 {
-- rockchip,pins =
-- /* mipi_te0 */
-- <3 RK_PC2 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- mipi_te1: mipi-te1 {
-- rockchip,pins =
-- /* mipi_te1 */
-- <3 RK_PC3 2 &pcfg_pull_none>;
-- };
-- };
--
-- npu {
-- /omit-if-no-ref/
-- npu_pins: npu-pins {
-- rockchip,pins =
-- /* npu_avs */
-- <0 RK_PC6 2 &pcfg_pull_none>;
-- };
-- };
--
-- pcie20x1 {
-- /omit-if-no-ref/
-- pcie20x1m0_pins: pcie20x1m0-pins {
-- rockchip,pins =
-- /* pcie20x1_2_clkreqn_m0 */
-- <3 RK_PC7 4 &pcfg_pull_none>,
-- /* pcie20x1_2_perstn_m0 */
-- <3 RK_PD1 4 &pcfg_pull_none>,
-- /* pcie20x1_2_waken_m0 */
-- <3 RK_PD0 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie20x1m1_pins: pcie20x1m1-pins {
-- rockchip,pins =
-- /* pcie20x1_2_clkreqn_m1 */
-- <4 RK_PB7 4 &pcfg_pull_none>,
-- /* pcie20x1_2_perstn_m1 */
-- <4 RK_PC1 4 &pcfg_pull_none>,
-- /* pcie20x1_2_waken_m1 */
-- <4 RK_PC0 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
-- rockchip,pins =
-- /* pcie20x1_2_button_rstn */
-- <4 RK_PB3 4 &pcfg_pull_none>;
-- };
-- };
--
-- pcie30phy {
-- /omit-if-no-ref/
-- pcie30phy_pins: pcie30phy-pins {
-- rockchip,pins =
-- /* pcie30phy_dtb0 */
-- <1 RK_PC4 4 &pcfg_pull_none>,
-- /* pcie30phy_dtb1 */
-- <1 RK_PD1 4 &pcfg_pull_none>;
-- };
-- };
--
-- pcie30x1 {
-- /omit-if-no-ref/
-- pcie30x1m0_pins: pcie30x1m0-pins {
-- rockchip,pins =
-- /* pcie30x1_0_clkreqn_m0 */
-- <0 RK_PC0 12 &pcfg_pull_none>,
-- /* pcie30x1_0_perstn_m0 */
-- <0 RK_PC5 12 &pcfg_pull_none>,
-- /* pcie30x1_0_waken_m0 */
-- <0 RK_PC4 12 &pcfg_pull_none>,
-- /* pcie30x1_1_clkreqn_m0 */
-- <0 RK_PB5 12 &pcfg_pull_none>,
-- /* pcie30x1_1_perstn_m0 */
-- <0 RK_PB7 12 &pcfg_pull_none>,
-- /* pcie30x1_1_waken_m0 */
-- <0 RK_PB6 12 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x1m1_pins: pcie30x1m1-pins {
-- rockchip,pins =
-- /* pcie30x1_0_clkreqn_m1 */
-- <4 RK_PA3 4 &pcfg_pull_none>,
-- /* pcie30x1_0_perstn_m1 */
-- <4 RK_PA5 4 &pcfg_pull_none>,
-- /* pcie30x1_0_waken_m1 */
-- <4 RK_PA4 4 &pcfg_pull_none>,
-- /* pcie30x1_1_clkreqn_m1 */
-- <4 RK_PA0 4 &pcfg_pull_none>,
-- /* pcie30x1_1_perstn_m1 */
-- <4 RK_PA2 4 &pcfg_pull_none>,
-- /* pcie30x1_1_waken_m1 */
-- <4 RK_PA1 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x1m2_pins: pcie30x1m2-pins {
-- rockchip,pins =
-- /* pcie30x1_0_clkreqn_m2 */
-- <1 RK_PB5 4 &pcfg_pull_none>,
-- /* pcie30x1_0_perstn_m2 */
-- <1 RK_PB4 4 &pcfg_pull_none>,
-- /* pcie30x1_0_waken_m2 */
-- <1 RK_PB3 4 &pcfg_pull_none>,
-- /* pcie30x1_1_clkreqn_m2 */
-- <1 RK_PA0 4 &pcfg_pull_none>,
-- /* pcie30x1_1_perstn_m2 */
-- <1 RK_PA7 4 &pcfg_pull_none>,
-- /* pcie30x1_1_waken_m2 */
-- <1 RK_PA1 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
-- rockchip,pins =
-- /* pcie30x1_0_button_rstn */
-- <4 RK_PB1 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
-- rockchip,pins =
-- /* pcie30x1_1_button_rstn */
-- <4 RK_PB2 4 &pcfg_pull_none>;
-- };
-- };
--
-- pcie30x2 {
-- /omit-if-no-ref/
-- pcie30x2m0_pins: pcie30x2m0-pins {
-- rockchip,pins =
-- /* pcie30x2_clkreqn_m0 */
-- <0 RK_PD1 12 &pcfg_pull_none>,
-- /* pcie30x2_perstn_m0 */
-- <0 RK_PD4 12 &pcfg_pull_none>,
-- /* pcie30x2_waken_m0 */
-- <0 RK_PD2 12 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x2m1_pins: pcie30x2m1-pins {
-- rockchip,pins =
-- /* pcie30x2_clkreqn_m1 */
-- <4 RK_PA6 4 &pcfg_pull_none>,
-- /* pcie30x2_perstn_m1 */
-- <4 RK_PB0 4 &pcfg_pull_none>,
-- /* pcie30x2_waken_m1 */
-- <4 RK_PA7 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x2m2_pins: pcie30x2m2-pins {
-- rockchip,pins =
-- /* pcie30x2_clkreqn_m2 */
-- <3 RK_PD2 4 &pcfg_pull_none>,
-- /* pcie30x2_perstn_m2 */
-- <3 RK_PD4 4 &pcfg_pull_none>,
-- /* pcie30x2_waken_m2 */
-- <3 RK_PD3 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x2m3_pins: pcie30x2m3-pins {
-- rockchip,pins =
-- /* pcie30x2_clkreqn_m3 */
-- <1 RK_PD7 4 &pcfg_pull_none>,
-- /* pcie30x2_perstn_m3 */
-- <1 RK_PB7 4 &pcfg_pull_none>,
-- /* pcie30x2_waken_m3 */
-- <1 RK_PB6 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x2_button_rstn: pcie30x2-button-rstn {
-- rockchip,pins =
-- /* pcie30x2_button_rstn */
-- <3 RK_PC1 4 &pcfg_pull_none>;
-- };
-- };
--
-- pcie30x4 {
-- /omit-if-no-ref/
-- pcie30x4m0_pins: pcie30x4m0-pins {
-- rockchip,pins =
-- /* pcie30x4_clkreqn_m0 */
-- <0 RK_PC6 12 &pcfg_pull_none>,
-- /* pcie30x4_perstn_m0 */
-- <0 RK_PD0 12 &pcfg_pull_none>,
-- /* pcie30x4_waken_m0 */
-- <0 RK_PC7 12 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x4m1_pins: pcie30x4m1-pins {
-- rockchip,pins =
-- /* pcie30x4_clkreqn_m1 */
-- <4 RK_PB4 4 &pcfg_pull_none>,
-- /* pcie30x4_perstn_m1 */
-- <4 RK_PB6 4 &pcfg_pull_none>,
-- /* pcie30x4_waken_m1 */
-- <4 RK_PB5 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x4m2_pins: pcie30x4m2-pins {
-- rockchip,pins =
-- /* pcie30x4_clkreqn_m2 */
-- <3 RK_PC4 4 &pcfg_pull_none>,
-- /* pcie30x4_perstn_m2 */
-- <3 RK_PC6 4 &pcfg_pull_none>,
-- /* pcie30x4_waken_m2 */
-- <3 RK_PC5 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x4m3_pins: pcie30x4m3-pins {
-- rockchip,pins =
-- /* pcie30x4_clkreqn_m3 */
-- <1 RK_PB0 4 &pcfg_pull_none>,
-- /* pcie30x4_perstn_m3 */
-- <1 RK_PB2 4 &pcfg_pull_none>,
-- /* pcie30x4_waken_m3 */
-- <1 RK_PB1 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pcie30x4_button_rstn: pcie30x4-button-rstn {
-- rockchip,pins =
-- /* pcie30x4_button_rstn */
-- <3 RK_PD5 4 &pcfg_pull_none>;
-- };
-- };
--
-- pdm0 {
-- /omit-if-no-ref/
-- pdm0m0_clk: pdm0m0-clk {
-- rockchip,pins =
-- /* pdm0_clk0_m0 */
-- <1 RK_PC6 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m0_clk1: pdm0m0-clk1 {
-- rockchip,pins =
-- /* pdm0m0_clk1 */
-- <1 RK_PC4 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m0_sdi0: pdm0m0-sdi0 {
-- rockchip,pins =
-- /* pdm0m0_sdi0 */
-- <1 RK_PD5 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m0_sdi1: pdm0m0-sdi1 {
-- rockchip,pins =
-- /* pdm0m0_sdi1 */
-- <1 RK_PD1 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m0_sdi2: pdm0m0-sdi2 {
-- rockchip,pins =
-- /* pdm0m0_sdi2 */
-- <1 RK_PD2 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m0_sdi3: pdm0m0-sdi3 {
-- rockchip,pins =
-- /* pdm0m0_sdi3 */
-- <1 RK_PD3 3 &pcfg_pull_none>;
-- };
-- /omit-if-no-ref/
-- pdm0m1_clk: pdm0m1-clk {
-- rockchip,pins =
-- /* pdm0_clk0_m1 */
-- <0 RK_PC0 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m1_clk1: pdm0m1-clk1 {
-- rockchip,pins =
-- /* pdm0m1_clk1 */
-- <0 RK_PC4 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m1_sdi0: pdm0m1-sdi0 {
-- rockchip,pins =
-- /* pdm0m1_sdi0 */
-- <0 RK_PC7 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m1_sdi1: pdm0m1-sdi1 {
-- rockchip,pins =
-- /* pdm0m1_sdi1 */
-- <0 RK_PD0 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m1_sdi2: pdm0m1-sdi2 {
-- rockchip,pins =
-- /* pdm0m1_sdi2 */
-- <0 RK_PD4 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm0m1_sdi3: pdm0m1-sdi3 {
-- rockchip,pins =
-- /* pdm0m1_sdi3 */
-- <0 RK_PD6 2 &pcfg_pull_none>;
-- };
-- };
--
-- pdm1 {
-- /omit-if-no-ref/
-- pdm1m0_clk: pdm1m0-clk {
-- rockchip,pins =
-- /* pdm1_clk0_m0 */
-- <4 RK_PD5 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m0_clk1: pdm1m0-clk1 {
-- rockchip,pins =
-- /* pdm1m0_clk1 */
-- <4 RK_PD4 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m0_sdi0: pdm1m0-sdi0 {
-- rockchip,pins =
-- /* pdm1m0_sdi0 */
-- <4 RK_PD3 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m0_sdi1: pdm1m0-sdi1 {
-- rockchip,pins =
-- /* pdm1m0_sdi1 */
-- <4 RK_PD2 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m0_sdi2: pdm1m0-sdi2 {
-- rockchip,pins =
-- /* pdm1m0_sdi2 */
-- <4 RK_PD1 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m0_sdi3: pdm1m0-sdi3 {
-- rockchip,pins =
-- /* pdm1m0_sdi3 */
-- <4 RK_PD0 2 &pcfg_pull_none>;
-- };
-- /omit-if-no-ref/
-- pdm1m1_clk: pdm1m1-clk {
-- rockchip,pins =
-- /* pdm1_clk0_m1 */
-- <1 RK_PB4 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m1_clk1: pdm1m1-clk1 {
-- rockchip,pins =
-- /* pdm1m1_clk1 */
-- <1 RK_PB3 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m1_sdi0: pdm1m1-sdi0 {
-- rockchip,pins =
-- /* pdm1m1_sdi0 */
-- <1 RK_PA7 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m1_sdi1: pdm1m1-sdi1 {
-- rockchip,pins =
-- /* pdm1m1_sdi1 */
-- <1 RK_PB0 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m1_sdi2: pdm1m1-sdi2 {
-- rockchip,pins =
-- /* pdm1m1_sdi2 */
-- <1 RK_PB1 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pdm1m1_sdi3: pdm1m1-sdi3 {
-- rockchip,pins =
-- /* pdm1m1_sdi3 */
-- <1 RK_PB2 2 &pcfg_pull_none>;
-- };
-- };
--
-- pmic {
-- /omit-if-no-ref/
-- pmic_pins: pmic-pins {
-- rockchip,pins =
-- /* pmic_int_l */
-- <0 RK_PA7 0 &pcfg_pull_up>,
-- /* pmic_sleep1 */
-- <0 RK_PA2 1 &pcfg_pull_none>,
-- /* pmic_sleep2 */
-- <0 RK_PA3 1 &pcfg_pull_none>,
-- /* pmic_sleep3 */
-- <0 RK_PC1 1 &pcfg_pull_none>,
-- /* pmic_sleep4 */
-- <0 RK_PC2 1 &pcfg_pull_none>,
-- /* pmic_sleep5 */
-- <0 RK_PC3 1 &pcfg_pull_none>,
-- /* pmic_sleep6 */
-- <0 RK_PD6 1 &pcfg_pull_none>;
-- };
-- };
--
-- pmu {
-- /omit-if-no-ref/
-- pmu_pins: pmu-pins {
-- rockchip,pins =
-- /* pmu_debug */
-- <0 RK_PA5 3 &pcfg_pull_none>;
-- };
-- };
--
-- pwm0 {
-- /omit-if-no-ref/
-- pwm0m0_pins: pwm0m0-pins {
-- rockchip,pins =
-- /* pwm0_m0 */
-- <0 RK_PB7 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm0m1_pins: pwm0m1-pins {
-- rockchip,pins =
-- /* pwm0_m1 */
-- <1 RK_PD2 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm0m2_pins: pwm0m2-pins {
-- rockchip,pins =
-- /* pwm0_m2 */
-- <1 RK_PA2 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm1 {
-- /omit-if-no-ref/
-- pwm1m0_pins: pwm1m0-pins {
-- rockchip,pins =
-- /* pwm1_m0 */
-- <0 RK_PC0 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm1m1_pins: pwm1m1-pins {
-- rockchip,pins =
-- /* pwm1_m1 */
-- <1 RK_PD3 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm1m2_pins: pwm1m2-pins {
-- rockchip,pins =
-- /* pwm1_m2 */
-- <1 RK_PA3 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm2 {
-- /omit-if-no-ref/
-- pwm2m0_pins: pwm2m0-pins {
-- rockchip,pins =
-- /* pwm2_m0 */
-- <0 RK_PC4 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm2m1_pins: pwm2m1-pins {
-- rockchip,pins =
-- /* pwm2_m1 */
-- <3 RK_PB1 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm3 {
-- /omit-if-no-ref/
-- pwm3m0_pins: pwm3m0-pins {
-- rockchip,pins =
-- /* pwm3_ir_m0 */
-- <0 RK_PD4 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm3m1_pins: pwm3m1-pins {
-- rockchip,pins =
-- /* pwm3_ir_m1 */
-- <3 RK_PB2 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm3m2_pins: pwm3m2-pins {
-- rockchip,pins =
-- /* pwm3_ir_m2 */
-- <1 RK_PC2 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm3m3_pins: pwm3m3-pins {
-- rockchip,pins =
-- /* pwm3_ir_m3 */
-- <1 RK_PA7 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm4 {
-- /omit-if-no-ref/
-- pwm4m0_pins: pwm4m0-pins {
-- rockchip,pins =
-- /* pwm4_m0 */
-- <0 RK_PC5 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm5 {
-- /omit-if-no-ref/
-- pwm5m0_pins: pwm5m0-pins {
-- rockchip,pins =
-- /* pwm5_m0 */
-- <0 RK_PB1 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm5m1_pins: pwm5m1-pins {
-- rockchip,pins =
-- /* pwm5_m1 */
-- <0 RK_PC6 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm6 {
-- /omit-if-no-ref/
-- pwm6m0_pins: pwm6m0-pins {
-- rockchip,pins =
-- /* pwm6_m0 */
-- <0 RK_PC7 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm6m1_pins: pwm6m1-pins {
-- rockchip,pins =
-- /* pwm6_m1 */
-- <4 RK_PC1 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm7 {
-- /omit-if-no-ref/
-- pwm7m0_pins: pwm7m0-pins {
-- rockchip,pins =
-- /* pwm7_ir_m0 */
-- <0 RK_PD0 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm7m1_pins: pwm7m1-pins {
-- rockchip,pins =
-- /* pwm7_ir_m1 */
-- <4 RK_PD4 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm7m2_pins: pwm7m2-pins {
-- rockchip,pins =
-- /* pwm7_ir_m2 */
-- <1 RK_PC3 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm8 {
-- /omit-if-no-ref/
-- pwm8m0_pins: pwm8m0-pins {
-- rockchip,pins =
-- /* pwm8_m0 */
-- <3 RK_PA7 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm8m1_pins: pwm8m1-pins {
-- rockchip,pins =
-- /* pwm8_m1 */
-- <4 RK_PD0 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm8m2_pins: pwm8m2-pins {
-- rockchip,pins =
-- /* pwm8_m2 */
-- <3 RK_PD0 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm9 {
-- /omit-if-no-ref/
-- pwm9m0_pins: pwm9m0-pins {
-- rockchip,pins =
-- /* pwm9_m0 */
-- <3 RK_PB0 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm9m1_pins: pwm9m1-pins {
-- rockchip,pins =
-- /* pwm9_m1 */
-- <4 RK_PD1 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm9m2_pins: pwm9m2-pins {
-- rockchip,pins =
-- /* pwm9_m2 */
-- <3 RK_PD1 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm10 {
-- /omit-if-no-ref/
-- pwm10m0_pins: pwm10m0-pins {
-- rockchip,pins =
-- /* pwm10_m0 */
-- <3 RK_PA0 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm10m1_pins: pwm10m1-pins {
-- rockchip,pins =
-- /* pwm10_m1 */
-- <4 RK_PD3 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm10m2_pins: pwm10m2-pins {
-- rockchip,pins =
-- /* pwm10_m2 */
-- <3 RK_PD3 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm11 {
-- /omit-if-no-ref/
-- pwm11m0_pins: pwm11m0-pins {
-- rockchip,pins =
-- /* pwm11_ir_m0 */
-- <3 RK_PA1 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm11m1_pins: pwm11m1-pins {
-- rockchip,pins =
-- /* pwm11_ir_m1 */
-- <4 RK_PB4 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm11m2_pins: pwm11m2-pins {
-- rockchip,pins =
-- /* pwm11_ir_m2 */
-- <1 RK_PC4 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm11m3_pins: pwm11m3-pins {
-- rockchip,pins =
-- /* pwm11_ir_m3 */
-- <3 RK_PD5 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm12 {
-- /omit-if-no-ref/
-- pwm12m0_pins: pwm12m0-pins {
-- rockchip,pins =
-- /* pwm12_m0 */
-- <3 RK_PB5 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm12m1_pins: pwm12m1-pins {
-- rockchip,pins =
-- /* pwm12_m1 */
-- <4 RK_PB5 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm13 {
-- /omit-if-no-ref/
-- pwm13m0_pins: pwm13m0-pins {
-- rockchip,pins =
-- /* pwm13_m0 */
-- <3 RK_PB6 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm13m1_pins: pwm13m1-pins {
-- rockchip,pins =
-- /* pwm13_m1 */
-- <4 RK_PB6 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm13m2_pins: pwm13m2-pins {
-- rockchip,pins =
-- /* pwm13_m2 */
-- <1 RK_PB7 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm14 {
-- /omit-if-no-ref/
-- pwm14m0_pins: pwm14m0-pins {
-- rockchip,pins =
-- /* pwm14_m0 */
-- <3 RK_PC2 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm14m1_pins: pwm14m1-pins {
-- rockchip,pins =
-- /* pwm14_m1 */
-- <4 RK_PB2 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm14m2_pins: pwm14m2-pins {
-- rockchip,pins =
-- /* pwm14_m2 */
-- <1 RK_PD6 11 &pcfg_pull_none>;
-- };
-- };
--
-- pwm15 {
-- /omit-if-no-ref/
-- pwm15m0_pins: pwm15m0-pins {
-- rockchip,pins =
-- /* pwm15_ir_m0 */
-- <3 RK_PC3 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm15m1_pins: pwm15m1-pins {
-- rockchip,pins =
-- /* pwm15_ir_m1 */
-- <4 RK_PB3 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm15m2_pins: pwm15m2-pins {
-- rockchip,pins =
-- /* pwm15_ir_m2 */
-- <1 RK_PC6 11 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- pwm15m3_pins: pwm15m3-pins {
-- rockchip,pins =
-- /* pwm15_ir_m3 */
-- <1 RK_PD7 11 &pcfg_pull_none>;
-- };
-- };
--
-- refclk {
-- /omit-if-no-ref/
-- refclk_pins: refclk-pins {
-- rockchip,pins =
-- /* refclk_out */
-- <0 RK_PA0 1 &pcfg_pull_none>;
-- };
-- };
--
-- sata {
-- /omit-if-no-ref/
-- sata_pins: sata-pins {
-- rockchip,pins =
-- /* sata_cp_pod */
-- <0 RK_PC6 13 &pcfg_pull_none>,
-- /* sata_cpdet */
-- <0 RK_PD4 13 &pcfg_pull_none>,
-- /* sata_mp_switch */
-- <0 RK_PD5 13 &pcfg_pull_none>;
-- };
-- };
--
-- sata0 {
-- /omit-if-no-ref/
-- sata0m0_pins: sata0m0-pins {
-- rockchip,pins =
-- /* sata0_act_led_m0 */
-- <4 RK_PB6 6 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- sata0m1_pins: sata0m1-pins {
-- rockchip,pins =
-- /* sata0_act_led_m1 */
-- <1 RK_PB3 6 &pcfg_pull_none>;
-- };
-- };
--
-- sata1 {
-- /omit-if-no-ref/
-- sata1m0_pins: sata1m0-pins {
-- rockchip,pins =
-- /* sata1_act_led_m0 */
-- <4 RK_PB5 6 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- sata1m1_pins: sata1m1-pins {
-- rockchip,pins =
-- /* sata1_act_led_m1 */
-- <1 RK_PA1 6 &pcfg_pull_none>;
-- };
-- };
--
-- sata2 {
-- /omit-if-no-ref/
-- sata2m0_pins: sata2m0-pins {
-- rockchip,pins =
-- /* sata2_act_led_m0 */
-- <4 RK_PB1 6 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- sata2m1_pins: sata2m1-pins {
-- rockchip,pins =
-- /* sata2_act_led_m1 */
-- <1 RK_PB7 6 &pcfg_pull_none>;
-- };
-- };
--
-- sdio {
-- /omit-if-no-ref/
-- sdiom1_pins: sdiom1-pins {
-- rockchip,pins =
-- /* sdio_clk_m1 */
-- <3 RK_PA5 2 &pcfg_pull_none>,
-- /* sdio_cmd_m1 */
-- <3 RK_PA4 2 &pcfg_pull_none>,
-- /* sdio_d0_m1 */
-- <3 RK_PA0 2 &pcfg_pull_none>,
-- /* sdio_d1_m1 */
-- <3 RK_PA1 2 &pcfg_pull_none>,
-- /* sdio_d2_m1 */
-- <3 RK_PA2 2 &pcfg_pull_none>,
-- /* sdio_d3_m1 */
-- <3 RK_PA3 2 &pcfg_pull_none>;
-- };
-- };
--
-- sdmmc {
-- /omit-if-no-ref/
-- sdmmc_bus4: sdmmc-bus4 {
-- rockchip,pins =
-- /* sdmmc_d0 */
-- <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
-- /* sdmmc_d1 */
-- <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
-- /* sdmmc_d2 */
-- <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
-- /* sdmmc_d3 */
-- <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- sdmmc_clk: sdmmc-clk {
-- rockchip,pins =
-- /* sdmmc_clk */
-- <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- sdmmc_cmd: sdmmc-cmd {
-- rockchip,pins =
-- /* sdmmc_cmd */
-- <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
-- };
--
-- /omit-if-no-ref/
-- sdmmc_det: sdmmc-det {
-- rockchip,pins =
-- /* sdmmc_det */
-- <0 RK_PA4 1 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- sdmmc_pwren: sdmmc-pwren {
-- rockchip,pins =
-- /* sdmmc_pwren */
-- <0 RK_PA5 2 &pcfg_pull_none>;
-- };
-- };
--
-- spdif0 {
-- /omit-if-no-ref/
-- spdif0m0_tx: spdif0m0-tx {
-- rockchip,pins =
-- /* spdif0m0_tx */
-- <1 RK_PB6 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- spdif0m1_tx: spdif0m1-tx {
-- rockchip,pins =
-- /* spdif0m1_tx */
-- <4 RK_PB4 6 &pcfg_pull_none>;
-- };
-- };
--
-- spdif1 {
-- /omit-if-no-ref/
-- spdif1m0_tx: spdif1m0-tx {
-- rockchip,pins =
-- /* spdif1m0_tx */
-- <1 RK_PB7 3 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- spdif1m1_tx: spdif1m1-tx {
-- rockchip,pins =
-- /* spdif1m1_tx */
-- <4 RK_PB1 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- spdif1m2_tx: spdif1m2-tx {
-- rockchip,pins =
-- /* spdif1m2_tx */
-- <4 RK_PC1 3 &pcfg_pull_none>;
-- };
-- };
--
-- spi0 {
-- /omit-if-no-ref/
-- spi0m0_pins: spi0m0-pins {
-- rockchip,pins =
-- /* spi0_clk_m0 */
-- <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
-- /* spi0_miso_m0 */
-- <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
-- /* spi0_mosi_m0 */
-- <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi0m0_cs0: spi0m0-cs0 {
-- rockchip,pins =
-- /* spi0_cs0_m0 */
-- <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi0m0_cs1: spi0m0-cs1 {
-- rockchip,pins =
-- /* spi0_cs1_m0 */
-- <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
-- };
-- /omit-if-no-ref/
-- spi0m1_pins: spi0m1-pins {
-- rockchip,pins =
-- /* spi0_clk_m1 */
-- <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
-- /* spi0_miso_m1 */
-- <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
-- /* spi0_mosi_m1 */
-- <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi0m1_cs0: spi0m1-cs0 {
-- rockchip,pins =
-- /* spi0_cs0_m1 */
-- <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi0m1_cs1: spi0m1-cs1 {
-- rockchip,pins =
-- /* spi0_cs1_m1 */
-- <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
-- };
-- /omit-if-no-ref/
-- spi0m2_pins: spi0m2-pins {
-- rockchip,pins =
-- /* spi0_clk_m2 */
-- <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
-- /* spi0_miso_m2 */
-- <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
-- /* spi0_mosi_m2 */
-- <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi0m2_cs0: spi0m2-cs0 {
-- rockchip,pins =
-- /* spi0_cs0_m2 */
-- <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi0m2_cs1: spi0m2-cs1 {
-- rockchip,pins =
-- /* spi0_cs1_m2 */
-- <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
-- };
-- /omit-if-no-ref/
-- spi0m3_pins: spi0m3-pins {
-- rockchip,pins =
-- /* spi0_clk_m3 */
-- <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
-- /* spi0_miso_m3 */
-- <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
-- /* spi0_mosi_m3 */
-- <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi0m3_cs0: spi0m3-cs0 {
-- rockchip,pins =
-- /* spi0_cs0_m3 */
-- <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi0m3_cs1: spi0m3-cs1 {
-- rockchip,pins =
-- /* spi0_cs1_m3 */
-- <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
-- };
-- };
--
-- spi1 {
-- /omit-if-no-ref/
-- spi1m1_pins: spi1m1-pins {
-- rockchip,pins =
-- /* spi1_clk_m1 */
-- <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
-- /* spi1_miso_m1 */
-- <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
-- /* spi1_mosi_m1 */
-- <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi1m1_cs0: spi1m1-cs0 {
-- rockchip,pins =
-- /* spi1_cs0_m1 */
-- <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi1m1_cs1: spi1m1-cs1 {
-- rockchip,pins =
-- /* spi1_cs1_m1 */
-- <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi1m2_pins: spi1m2-pins {
-- rockchip,pins =
-- /* spi1_clk_m2 */
-- <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
-- /* spi1_miso_m2 */
-- <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
-- /* spi1_mosi_m2 */
-- <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi1m2_cs0: spi1m2-cs0 {
-- rockchip,pins =
-- /* spi1_cs0_m2 */
-- <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi1m2_cs1: spi1m2-cs1 {
-- rockchip,pins =
-- /* spi1_cs1_m2 */
-- <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
-- };
-- };
--
-- spi2 {
-- /omit-if-no-ref/
-- spi2m0_pins: spi2m0-pins {
-- rockchip,pins =
-- /* spi2_clk_m0 */
-- <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
-- /* spi2_miso_m0 */
-- <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
-- /* spi2_mosi_m0 */
-- <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi2m0_cs0: spi2m0-cs0 {
-- rockchip,pins =
-- /* spi2_cs0_m0 */
-- <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi2m0_cs1: spi2m0-cs1 {
-- rockchip,pins =
-- /* spi2_cs1_m0 */
-- <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi2m1_pins: spi2m1-pins {
-- rockchip,pins =
-- /* spi2_clk_m1 */
-- <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
-- /* spi2_miso_m1 */
-- <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
-- /* spi2_mosi_m1 */
-- <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi2m1_cs0: spi2m1-cs0 {
-- rockchip,pins =
-- /* spi2_cs0_m1 */
-- <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi2m1_cs1: spi2m1-cs1 {
-- rockchip,pins =
-- /* spi2_cs1_m1 */
-- <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi2m2_pins: spi2m2-pins {
-- rockchip,pins =
-- /* spi2_clk_m2 */
-- <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
-- /* spi2_miso_m2 */
-- <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
-- /* spi2_mosi_m2 */
-- <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi2m2_cs0: spi2m2-cs0 {
-- rockchip,pins =
-- /* spi2_cs0_m2 */
-- <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi2m2_cs1: spi2m2-cs1 {
-- rockchip,pins =
-- /* spi2_cs1_m2 */
-- <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
-- };
-- };
--
-- spi3 {
-- /omit-if-no-ref/
-- spi3m1_pins: spi3m1-pins {
-- rockchip,pins =
-- /* spi3_clk_m1 */
-- <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
-- /* spi3_miso_m1 */
-- <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
-- /* spi3_mosi_m1 */
-- <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m1_cs0: spi3m1-cs0 {
-- rockchip,pins =
-- /* spi3_cs0_m1 */
-- <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m1_cs1: spi3m1-cs1 {
-- rockchip,pins =
-- /* spi3_cs1_m1 */
-- <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m2_pins: spi3m2-pins {
-- rockchip,pins =
-- /* spi3_clk_m2 */
-- <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
-- /* spi3_miso_m2 */
-- <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
-- /* spi3_mosi_m2 */
-- <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m2_cs0: spi3m2-cs0 {
-- rockchip,pins =
-- /* spi3_cs0_m2 */
-- <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m2_cs1: spi3m2-cs1 {
-- rockchip,pins =
-- /* spi3_cs1_m2 */
-- <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m3_pins: spi3m3-pins {
-- rockchip,pins =
-- /* spi3_clk_m3 */
-- <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
-- /* spi3_miso_m3 */
-- <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
-- /* spi3_mosi_m3 */
-- <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m3_cs0: spi3m3-cs0 {
-- rockchip,pins =
-- /* spi3_cs0_m3 */
-- <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi3m3_cs1: spi3m3-cs1 {
-- rockchip,pins =
-- /* spi3_cs1_m3 */
-- <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
-- };
-- };
--
-- spi4 {
-- /omit-if-no-ref/
-- spi4m0_pins: spi4m0-pins {
-- rockchip,pins =
-- /* spi4_clk_m0 */
-- <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
-- /* spi4_miso_m0 */
-- <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
-- /* spi4_mosi_m0 */
-- <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi4m0_cs0: spi4m0-cs0 {
-- rockchip,pins =
-- /* spi4_cs0_m0 */
-- <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi4m0_cs1: spi4m0-cs1 {
-- rockchip,pins =
-- /* spi4_cs1_m0 */
-- <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi4m1_pins: spi4m1-pins {
-- rockchip,pins =
-- /* spi4_clk_m1 */
-- <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
-- /* spi4_miso_m1 */
-- <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
-- /* spi4_mosi_m1 */
-- <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi4m1_cs0: spi4m1-cs0 {
-- rockchip,pins =
-- /* spi4_cs0_m1 */
-- <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi4m1_cs1: spi4m1-cs1 {
-- rockchip,pins =
-- /* spi4_cs1_m1 */
-- <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi4m2_pins: spi4m2-pins {
-- rockchip,pins =
-- /* spi4_clk_m2 */
-- <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
-- /* spi4_miso_m2 */
-- <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
-- /* spi4_mosi_m2 */
-- <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
-- };
--
-- /omit-if-no-ref/
-- spi4m2_cs0: spi4m2-cs0 {
-- rockchip,pins =
-- /* spi4_cs0_m2 */
-- <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
-- };
-- };
--
-- tsadc {
-- /omit-if-no-ref/
-- tsadcm1_shut: tsadcm1-shut {
-- rockchip,pins =
-- /* tsadcm1_shut */
-- <0 RK_PA2 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- tsadc_shut: tsadc-shut {
-- rockchip,pins =
-- /* tsadc_shut */
-- <0 RK_PA1 2 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- tsadc_shut_org: tsadc-shut-org {
-- rockchip,pins =
-- /* tsadc_shut_org */
-- <0 RK_PA1 1 &pcfg_pull_none>;
-- };
-- };
--
-- uart0 {
-- /omit-if-no-ref/
-- uart0m0_xfer: uart0m0-xfer {
-- rockchip,pins =
-- /* uart0_rx_m0 */
-- <0 RK_PC4 4 &pcfg_pull_up>,
-- /* uart0_tx_m0 */
-- <0 RK_PC5 4 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart0m1_xfer: uart0m1-xfer {
-- rockchip,pins =
-- /* uart0_rx_m1 */
-- <0 RK_PB0 4 &pcfg_pull_up>,
-- /* uart0_tx_m1 */
-- <0 RK_PB1 4 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart0m2_xfer: uart0m2-xfer {
-- rockchip,pins =
-- /* uart0_rx_m2 */
-- <4 RK_PA4 10 &pcfg_pull_up>,
-- /* uart0_tx_m2 */
-- <4 RK_PA3 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart0_ctsn: uart0-ctsn {
-- rockchip,pins =
-- /* uart0_ctsn */
-- <0 RK_PD1 4 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart0_rtsn: uart0-rtsn {
-- rockchip,pins =
-- /* uart0_rtsn */
-- <0 RK_PC6 4 &pcfg_pull_none>;
-- };
-- };
--
-- uart1 {
-- /omit-if-no-ref/
-- uart1m1_xfer: uart1m1-xfer {
-- rockchip,pins =
-- /* uart1_rx_m1 */
-- <1 RK_PB7 10 &pcfg_pull_up>,
-- /* uart1_tx_m1 */
-- <1 RK_PB6 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart1m1_ctsn: uart1m1-ctsn {
-- rockchip,pins =
-- /* uart1m1_ctsn */
-- <1 RK_PD7 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart1m1_rtsn: uart1m1-rtsn {
-- rockchip,pins =
-- /* uart1m1_rtsn */
-- <1 RK_PD6 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart1m2_xfer: uart1m2-xfer {
-- rockchip,pins =
-- /* uart1_rx_m2 */
-- <0 RK_PD2 10 &pcfg_pull_up>,
-- /* uart1_tx_m2 */
-- <0 RK_PD1 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart1m2_ctsn: uart1m2-ctsn {
-- rockchip,pins =
-- /* uart1m2_ctsn */
-- <0 RK_PD0 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart1m2_rtsn: uart1m2-rtsn {
-- rockchip,pins =
-- /* uart1m2_rtsn */
-- <0 RK_PC7 10 &pcfg_pull_none>;
-- };
-- };
--
-- uart2 {
-- /omit-if-no-ref/
-- uart2m0_xfer: uart2m0-xfer {
-- rockchip,pins =
-- /* uart2_rx_m0 */
-- <0 RK_PB6 10 &pcfg_pull_up>,
-- /* uart2_tx_m0 */
-- <0 RK_PB5 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart2m1_xfer: uart2m1-xfer {
-- rockchip,pins =
-- /* uart2_rx_m1 */
-- <4 RK_PD1 10 &pcfg_pull_up>,
-- /* uart2_tx_m1 */
-- <4 RK_PD0 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart2m2_xfer: uart2m2-xfer {
-- rockchip,pins =
-- /* uart2_rx_m2 */
-- <3 RK_PB2 10 &pcfg_pull_up>,
-- /* uart2_tx_m2 */
-- <3 RK_PB1 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart2_ctsn: uart2-ctsn {
-- rockchip,pins =
-- /* uart2_ctsn */
-- <3 RK_PB4 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart2_rtsn: uart2-rtsn {
-- rockchip,pins =
-- /* uart2_rtsn */
-- <3 RK_PB3 10 &pcfg_pull_none>;
-- };
-- };
--
-- uart3 {
-- /omit-if-no-ref/
-- uart3m0_xfer: uart3m0-xfer {
-- rockchip,pins =
-- /* uart3_rx_m0 */
-- <1 RK_PC0 10 &pcfg_pull_up>,
-- /* uart3_tx_m0 */
-- <1 RK_PC1 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart3m1_xfer: uart3m1-xfer {
-- rockchip,pins =
-- /* uart3_rx_m1 */
-- <3 RK_PB6 10 &pcfg_pull_up>,
-- /* uart3_tx_m1 */
-- <3 RK_PB5 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart3m2_xfer: uart3m2-xfer {
-- rockchip,pins =
-- /* uart3_rx_m2 */
-- <4 RK_PA6 10 &pcfg_pull_up>,
-- /* uart3_tx_m2 */
-- <4 RK_PA5 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart3_ctsn: uart3-ctsn {
-- rockchip,pins =
-- /* uart3_ctsn */
-- <1 RK_PC3 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart3_rtsn: uart3-rtsn {
-- rockchip,pins =
-- /* uart3_rtsn */
-- <1 RK_PC2 10 &pcfg_pull_none>;
-- };
-- };
--
-- uart4 {
-- /omit-if-no-ref/
-- uart4m0_xfer: uart4m0-xfer {
-- rockchip,pins =
-- /* uart4_rx_m0 */
-- <1 RK_PD3 10 &pcfg_pull_up>,
-- /* uart4_tx_m0 */
-- <1 RK_PD2 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart4m1_xfer: uart4m1-xfer {
-- rockchip,pins =
-- /* uart4_rx_m1 */
-- <3 RK_PD0 10 &pcfg_pull_up>,
-- /* uart4_tx_m1 */
-- <3 RK_PD1 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart4m2_xfer: uart4m2-xfer {
-- rockchip,pins =
-- /* uart4_rx_m2 */
-- <1 RK_PB2 10 &pcfg_pull_up>,
-- /* uart4_tx_m2 */
-- <1 RK_PB3 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart4_ctsn: uart4-ctsn {
-- rockchip,pins =
-- /* uart4_ctsn */
-- <1 RK_PC7 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart4_rtsn: uart4-rtsn {
-- rockchip,pins =
-- /* uart4_rtsn */
-- <1 RK_PC5 10 &pcfg_pull_none>;
-- };
-- };
--
-- uart5 {
-- /omit-if-no-ref/
-- uart5m0_xfer: uart5m0-xfer {
-- rockchip,pins =
-- /* uart5_rx_m0 */
-- <4 RK_PD4 10 &pcfg_pull_up>,
-- /* uart5_tx_m0 */
-- <4 RK_PD5 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart5m0_ctsn: uart5m0-ctsn {
-- rockchip,pins =
-- /* uart5m0_ctsn */
-- <4 RK_PD2 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart5m0_rtsn: uart5m0-rtsn {
-- rockchip,pins =
-- /* uart5m0_rtsn */
-- <4 RK_PD3 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart5m1_xfer: uart5m1-xfer {
-- rockchip,pins =
-- /* uart5_rx_m1 */
-- <3 RK_PC5 10 &pcfg_pull_up>,
-- /* uart5_tx_m1 */
-- <3 RK_PC4 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart5m1_ctsn: uart5m1-ctsn {
-- rockchip,pins =
-- /* uart5m1_ctsn */
-- <2 RK_PA2 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart5m1_rtsn: uart5m1-rtsn {
-- rockchip,pins =
-- /* uart5m1_rtsn */
-- <2 RK_PA3 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart5m2_xfer: uart5m2-xfer {
-- rockchip,pins =
-- /* uart5_rx_m2 */
-- <2 RK_PD4 10 &pcfg_pull_up>,
-- /* uart5_tx_m2 */
-- <2 RK_PD5 10 &pcfg_pull_up>;
-- };
-- };
--
-- uart6 {
-- /omit-if-no-ref/
-- uart6m1_xfer: uart6m1-xfer {
-- rockchip,pins =
-- /* uart6_rx_m1 */
-- <1 RK_PA0 10 &pcfg_pull_up>,
-- /* uart6_tx_m1 */
-- <1 RK_PA1 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart6m1_ctsn: uart6m1-ctsn {
-- rockchip,pins =
-- /* uart6m1_ctsn */
-- <1 RK_PA3 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart6m1_rtsn: uart6m1-rtsn {
-- rockchip,pins =
-- /* uart6m1_rtsn */
-- <1 RK_PA2 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart6m2_xfer: uart6m2-xfer {
-- rockchip,pins =
-- /* uart6_rx_m2 */
-- <1 RK_PD1 10 &pcfg_pull_up>,
-- /* uart6_tx_m2 */
-- <1 RK_PD0 10 &pcfg_pull_up>;
-- };
-- };
--
-- uart7 {
-- /omit-if-no-ref/
-- uart7m1_xfer: uart7m1-xfer {
-- rockchip,pins =
-- /* uart7_rx_m1 */
-- <3 RK_PC1 10 &pcfg_pull_up>,
-- /* uart7_tx_m1 */
-- <3 RK_PC0 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart7m1_ctsn: uart7m1-ctsn {
-- rockchip,pins =
-- /* uart7m1_ctsn */
-- <3 RK_PC3 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart7m1_rtsn: uart7m1-rtsn {
-- rockchip,pins =
-- /* uart7m1_rtsn */
-- <3 RK_PC2 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart7m2_xfer: uart7m2-xfer {
-- rockchip,pins =
-- /* uart7_rx_m2 */
-- <1 RK_PB4 10 &pcfg_pull_up>,
-- /* uart7_tx_m2 */
-- <1 RK_PB5 10 &pcfg_pull_up>;
-- };
-- };
--
-- uart8 {
-- /omit-if-no-ref/
-- uart8m0_xfer: uart8m0-xfer {
-- rockchip,pins =
-- /* uart8_rx_m0 */
-- <4 RK_PB1 10 &pcfg_pull_up>,
-- /* uart8_tx_m0 */
-- <4 RK_PB0 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart8m0_ctsn: uart8m0-ctsn {
-- rockchip,pins =
-- /* uart8m0_ctsn */
-- <4 RK_PB3 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart8m0_rtsn: uart8m0-rtsn {
-- rockchip,pins =
-- /* uart8m0_rtsn */
-- <4 RK_PB2 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart8m1_xfer: uart8m1-xfer {
-- rockchip,pins =
-- /* uart8_rx_m1 */
-- <3 RK_PA3 10 &pcfg_pull_up>,
-- /* uart8_tx_m1 */
-- <3 RK_PA2 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart8m1_ctsn: uart8m1-ctsn {
-- rockchip,pins =
-- /* uart8m1_ctsn */
-- <3 RK_PA5 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart8m1_rtsn: uart8m1-rtsn {
-- rockchip,pins =
-- /* uart8m1_rtsn */
-- <3 RK_PA4 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart8_xfer: uart8-xfer {
-- rockchip,pins =
-- /* uart8_rx_ */
-- <4 RK_PB1 10 &pcfg_pull_up>;
-- };
-- };
--
-- uart9 {
-- /omit-if-no-ref/
-- uart9m0_xfer: uart9m0-xfer {
-- rockchip,pins =
-- /* uart9_rx_m0 */
-- <2 RK_PC4 10 &pcfg_pull_up>,
-- /* uart9_tx_m0 */
-- <2 RK_PC2 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart9m1_xfer: uart9m1-xfer {
-- rockchip,pins =
-- /* uart9_rx_m1 */
-- <4 RK_PB5 10 &pcfg_pull_up>,
-- /* uart9_tx_m1 */
-- <4 RK_PB4 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart9m1_ctsn: uart9m1-ctsn {
-- rockchip,pins =
-- /* uart9m1_ctsn */
-- <4 RK_PA1 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart9m1_rtsn: uart9m1-rtsn {
-- rockchip,pins =
-- /* uart9m1_rtsn */
-- <4 RK_PA0 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart9m2_xfer: uart9m2-xfer {
-- rockchip,pins =
-- /* uart9_rx_m2 */
-- <3 RK_PD4 10 &pcfg_pull_up>,
-- /* uart9_tx_m2 */
-- <3 RK_PD5 10 &pcfg_pull_up>;
-- };
--
-- /omit-if-no-ref/
-- uart9m2_ctsn: uart9m2-ctsn {
-- rockchip,pins =
-- /* uart9m2_ctsn */
-- <3 RK_PD3 10 &pcfg_pull_none>;
-- };
--
-- /omit-if-no-ref/
-- uart9m2_rtsn: uart9m2-rtsn {
-- rockchip,pins =
-- /* uart9m2_rtsn */
-- <3 RK_PD2 10 &pcfg_pull_none>;
-- };
-- };
--
-- vop {
-- /omit-if-no-ref/
-- vop_pins: vop-pins {
-- rockchip,pins =
-- /* vop_post_empty */
-- <1 RK_PA2 1 &pcfg_pull_none>;
-- };
-- };
--};
--
--/*
-- * This part is edited handly.
-- */
--&pinctrl {
-- bt656 {
-- /omit-if-no-ref/
-- bt656_pins: bt656-pins {
-- rockchip,pins =
-- /* bt1120_clkout */
-- <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
-- /* bt1120_d0 */
-- <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
-- /* bt1120_d1 */
-- <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
-- /* bt1120_d2 */
-- <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
-- /* bt1120_d3 */
-- <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
-- /* bt1120_d4 */
-- <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
-- /* bt1120_d5 */
-- <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
-- /* bt1120_d6 */
-- <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
-- /* bt1120_d7 */
-- <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
-- };
-- };
--
-- gpio-func {
-- /omit-if-no-ref/
-- tsadc_gpio_func: tsadc-gpio-func {
-- rockchip,pins =
-- <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
-- };
--};
+++ /dev/null
-From 510cd9e688453166b2bff3999ed21cac97385bb5 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 17 Jun 2024 22:28:51 +0400
-Subject: [PATCH] arm64: dts: rockchip: add thermal zones information on RK3588
-
-This includes the necessary device tree data to allow thermal
-monitoring on RK3588(s) using the on-chip TSADC device, along with
-trip points for automatic thermal management.
-
-Each of the CPU clusters (one for the little cores and two for
-the big cores) get a passive cooling trip point at 85C, which
-will trigger DVFS throttling of the respective cluster upon
-reaching a high temperature condition.
-
-All zones also have a critical trip point at 115C, which will
-trigger a reset.
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
-Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 153 ++++++++++++++++++
- 1 file changed, 153 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-@@ -10,6 +10,7 @@
- #include <dt-bindings/reset/rockchip,rk3588-cru.h>
- #include <dt-bindings/phy/phy.h>
- #include <dt-bindings/ata/ahci.h>
-+#include <dt-bindings/thermal/thermal.h>
-
- / {
- compatible = "rockchip,rk3588";
-@@ -2368,6 +2369,158 @@
- status = "disabled";
- };
-
-+ thermal_zones: thermal-zones {
-+ /* sensor near the center of the SoC */
-+ package_thermal: package-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsadc 0>;
-+
-+ trips {
-+ package_crit: package-crit {
-+ temperature = <115000>;
-+ hysteresis = <0>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ /* sensor between A76 cores 0 and 1 */
-+ bigcore0_thermal: bigcore0-thermal {
-+ polling-delay-passive = <100>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsadc 1>;
-+
-+ trips {
-+ bigcore0_alert: bigcore0-alert {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ bigcore0_crit: bigcore0-crit {
-+ temperature = <115000>;
-+ hysteresis = <0>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&bigcore0_alert>;
-+ cooling-device =
-+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ /* sensor between A76 cores 2 and 3 */
-+ bigcore2_thermal: bigcore2-thermal {
-+ polling-delay-passive = <100>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsadc 2>;
-+
-+ trips {
-+ bigcore2_alert: bigcore2-alert {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ bigcore2_crit: bigcore2-crit {
-+ temperature = <115000>;
-+ hysteresis = <0>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&bigcore2_alert>;
-+ cooling-device =
-+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ /* sensor between the four A55 cores */
-+ little_core_thermal: littlecore-thermal {
-+ polling-delay-passive = <100>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsadc 3>;
-+
-+ trips {
-+ littlecore_alert: littlecore-alert {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ littlecore_crit: littlecore-crit {
-+ temperature = <115000>;
-+ hysteresis = <0>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&littlecore_alert>;
-+ cooling-device =
-+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ /* sensor near the PD_CENTER power domain */
-+ center_thermal: center-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsadc 4>;
-+
-+ trips {
-+ center_crit: center-crit {
-+ temperature = <115000>;
-+ hysteresis = <0>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ gpu_thermal: gpu-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsadc 5>;
-+
-+ trips {
-+ gpu_crit: gpu-crit {
-+ temperature = <115000>;
-+ hysteresis = <0>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ npu_thermal: npu-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&tsadc 6>;
-+
-+ trips {
-+ npu_crit: npu-crit {
-+ temperature = <115000>;
-+ hysteresis = <0>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+ };
-+
- tsadc: tsadc@fec00000 {
- compatible = "rockchip,rk3588-tsadc";
- reg = <0x0 0xfec00000 0x0 0x400>;
+++ /dev/null
-From b78f87940a79321a444083aca46ac3e8e53d1a90 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 17 Jun 2024 22:28:53 +0400
-Subject: [PATCH] arm64: dts: rockchip: add passive GPU cooling on RK3588
-
-As the GPU support on RK3588 has been merged upstream, along with OPP
-values, add a corresponding cooling map for passive cooling using the GPU.
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
-Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-3-c1f5f3267f1e@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 16 +++++++++++++++-
- 1 file changed, 15 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-@@ -2493,17 +2493,31 @@
- };
-
- gpu_thermal: gpu-thermal {
-- polling-delay-passive = <0>;
-+ polling-delay-passive = <100>;
- polling-delay = <0>;
- thermal-sensors = <&tsadc 5>;
-
- trips {
-+ gpu_alert: gpu-alert {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
- gpu_crit: gpu-crit {
- temperature = <115000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&gpu_alert>;
-+ cooling-device =
-+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ };
-+ };
- };
-
- npu_thermal: npu-thermal {
+++ /dev/null
-From 276856db91b46eaa7a4c19226c096a9dc899a3e9 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 17 Jun 2024 22:28:56 +0400
-Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588
-
-By default the CPUs on RK3588 start up in a conservative performance
-mode. Add frequency and voltage mappings to the device tree to enable
-dynamic scaling via cpufreq.
-
-OPP values are adapted from Radxa's downstream kernel for Rock 5B [1],
-stripping them down to the minimum frequency and voltage combinations
-as expected by the generic upstream cpufreq-dt driver, and also dropping
-those OPPs that don't differ in voltage but only in frequency (keeping
-the top frequency OPP in each case).
-
-Note that this patch ignores voltage scaling for the CPU memory
-interface which the downstream kernel does through a custom cpufreq
-driver, and which is why the downstream version has two sets of voltage
-values for each OPP (the second one being meant for the memory
-interface supply regulator). This is done instead via regulator
-coupling between CPU and memory interface supplies on affected boards.
-
-This has been tested on Rock 5B with u-boot 2023.11 compiled from
-Collabora's integration tree [2] with binary bl31 and appears to be
-stable both under active cooling and passive cooling (with throttling)
-
-[1] https://github.com/radxa/kernel/blob/stable-5.10-rock5/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-[2] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
-Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-6-c1f5f3267f1e@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 149 +++++++++++++++++++
- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 +
- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 +
- 3 files changed, 151 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
-@@ -0,0 +1,149 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/ {
-+ cluster0_opp_table: opp-table-cluster0 {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-1008000000 {
-+ opp-hz = /bits/ 64 <1008000000>;
-+ opp-microvolt = <675000 675000 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1200000000 {
-+ opp-hz = /bits/ 64 <1200000000>;
-+ opp-microvolt = <712500 712500 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1416000000 {
-+ opp-hz = /bits/ 64 <1416000000>;
-+ opp-microvolt = <762500 762500 950000>;
-+ clock-latency-ns = <40000>;
-+ opp-suspend;
-+ };
-+ opp-1608000000 {
-+ opp-hz = /bits/ 64 <1608000000>;
-+ opp-microvolt = <850000 850000 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1800000000 {
-+ opp-hz = /bits/ 64 <1800000000>;
-+ opp-microvolt = <950000 950000 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ };
-+
-+ cluster1_opp_table: opp-table-cluster1 {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-1200000000 {
-+ opp-hz = /bits/ 64 <1200000000>;
-+ opp-microvolt = <675000 675000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1416000000 {
-+ opp-hz = /bits/ 64 <1416000000>;
-+ opp-microvolt = <725000 725000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1608000000 {
-+ opp-hz = /bits/ 64 <1608000000>;
-+ opp-microvolt = <762500 762500 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1800000000 {
-+ opp-hz = /bits/ 64 <1800000000>;
-+ opp-microvolt = <850000 850000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-2016000000 {
-+ opp-hz = /bits/ 64 <2016000000>;
-+ opp-microvolt = <925000 925000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-2208000000 {
-+ opp-hz = /bits/ 64 <2208000000>;
-+ opp-microvolt = <987500 987500 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-2400000000 {
-+ opp-hz = /bits/ 64 <2400000000>;
-+ opp-microvolt = <1000000 1000000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ };
-+
-+ cluster2_opp_table: opp-table-cluster2 {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-1200000000 {
-+ opp-hz = /bits/ 64 <1200000000>;
-+ opp-microvolt = <675000 675000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1416000000 {
-+ opp-hz = /bits/ 64 <1416000000>;
-+ opp-microvolt = <725000 725000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1608000000 {
-+ opp-hz = /bits/ 64 <1608000000>;
-+ opp-microvolt = <762500 762500 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1800000000 {
-+ opp-hz = /bits/ 64 <1800000000>;
-+ opp-microvolt = <850000 850000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-2016000000 {
-+ opp-hz = /bits/ 64 <2016000000>;
-+ opp-microvolt = <925000 925000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-2208000000 {
-+ opp-hz = /bits/ 64 <2208000000>;
-+ opp-microvolt = <987500 987500 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-2400000000 {
-+ opp-hz = /bits/ 64 <2400000000>;
-+ opp-microvolt = <1000000 1000000 1000000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ };
-+};
-+
-+&cpu_b0 {
-+ operating-points-v2 = <&cluster1_opp_table>;
-+};
-+
-+&cpu_b1 {
-+ operating-points-v2 = <&cluster1_opp_table>;
-+};
-+
-+&cpu_b2 {
-+ operating-points-v2 = <&cluster2_opp_table>;
-+};
-+
-+&cpu_b3 {
-+ operating-points-v2 = <&cluster2_opp_table>;
-+};
-+
-+&cpu_l0 {
-+ operating-points-v2 = <&cluster0_opp_table>;
-+};
-+
-+&cpu_l1 {
-+ operating-points-v2 = <&cluster0_opp_table>;
-+};
-+
-+&cpu_l2 {
-+ operating-points-v2 = <&cluster0_opp_table>;
-+};
-+
-+&cpu_l3 {
-+ operating-points-v2 = <&cluster0_opp_table>;
-+};
---- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
-@@ -5,3 +5,4 @@
- */
-
- #include "rk3588-extra.dtsi"
-+#include "rk3588-opp.dtsi"
---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -5,3 +5,4 @@
- */
-
- #include "rk3588-base.dtsi"
-+#include "rk3588-opp.dtsi"
+++ /dev/null
-From 667885a6865832eb0678c7e02e47a3392f177ecb Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 17 Jun 2024 22:28:57 +0400
-Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j
-
-RK3588j is the 'industrial' variant of RK3588, and it uses a different
-set of OPPs both in terms of allowed frequencies and in terms of
-applicable voltages at each frequency setpoint.
-
-Add the OPPs that apply to RK3588j (and apparently RK3588m too) to
-enable dynamic CPU frequency scaling.
-
-OPP values are derived from Rockchip downstream sources [1] by taking
-only those OPPs which have the highest frequency for a given voltage
-level and dropping the rest (if they are included, the kernel complains
-at boot time about them being inefficient)
-
-[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
-Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 108 ++++++++++++++++++++++
- 1 file changed, 108 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
-@@ -5,3 +5,111 @@
- */
-
- #include "rk3588-extra.dtsi"
-+
-+/ {
-+ cluster0_opp_table: opp-table-cluster0 {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-1416000000 {
-+ opp-hz = /bits/ 64 <1416000000>;
-+ opp-microvolt = <750000 750000 950000>;
-+ clock-latency-ns = <40000>;
-+ opp-suspend;
-+ };
-+ opp-1608000000 {
-+ opp-hz = /bits/ 64 <1608000000>;
-+ opp-microvolt = <887500 887500 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1704000000 {
-+ opp-hz = /bits/ 64 <1704000000>;
-+ opp-microvolt = <937500 937500 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ };
-+
-+ cluster1_opp_table: opp-table-cluster1 {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-1416000000 {
-+ opp-hz = /bits/ 64 <1416000000>;
-+ opp-microvolt = <750000 750000 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1608000000 {
-+ opp-hz = /bits/ 64 <1608000000>;
-+ opp-microvolt = <787500 787500 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1800000000 {
-+ opp-hz = /bits/ 64 <1800000000>;
-+ opp-microvolt = <875000 875000 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-2016000000 {
-+ opp-hz = /bits/ 64 <2016000000>;
-+ opp-microvolt = <950000 950000 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ };
-+
-+ cluster2_opp_table: opp-table-cluster2 {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-1416000000 {
-+ opp-hz = /bits/ 64 <1416000000>;
-+ opp-microvolt = <750000 750000 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1608000000 {
-+ opp-hz = /bits/ 64 <1608000000>;
-+ opp-microvolt = <787500 787500 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-1800000000 {
-+ opp-hz = /bits/ 64 <1800000000>;
-+ opp-microvolt = <875000 875000 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ opp-2016000000 {
-+ opp-hz = /bits/ 64 <2016000000>;
-+ opp-microvolt = <950000 950000 950000>;
-+ clock-latency-ns = <40000>;
-+ };
-+ };
-+};
-+
-+&cpu_b0 {
-+ operating-points-v2 = <&cluster1_opp_table>;
-+};
-+
-+&cpu_b1 {
-+ operating-points-v2 = <&cluster1_opp_table>;
-+};
-+
-+&cpu_b2 {
-+ operating-points-v2 = <&cluster2_opp_table>;
-+};
-+
-+&cpu_b3 {
-+ operating-points-v2 = <&cluster2_opp_table>;
-+};
-+
-+&cpu_l0 {
-+ operating-points-v2 = <&cluster0_opp_table>;
-+};
-+
-+&cpu_l1 {
-+ operating-points-v2 = <&cluster0_opp_table>;
-+};
-+
-+&cpu_l2 {
-+ operating-points-v2 = <&cluster0_opp_table>;
-+};
-+
-+&cpu_l3 {
-+ operating-points-v2 = <&cluster0_opp_table>;
-+};
+++ /dev/null
-From a7b2070505a2a09ea65fa0c8c480c97f62d1978d Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 17 Jun 2024 22:28:58 +0400
-Subject: [PATCH] arm64: dts: rockchip: Split GPU OPPs of RK3588 and RK3588j
-
-RK3588j uses a different set of OPPs for its GPU, both in terms of
-allowed frequencies and in terms of voltages.
-
-Move the GPU OPPs table into per-variant .dtsi files to accommodate
-for this difference.
-
-The table for RK3588j is adapted from Rockchip downstream sources [1],
-while RK3588 one is moved verbatim into the per-variant .dtsi file.
-The values provided for RK3588 in the downstream sources match those
-in the original commit.
-
-[1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-
-Fixes: 6fca4edb93d3 ("arm64: dts: rockchip: Add rk3588 GPU node")
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
-Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-8-c1f5f3267f1e@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 38 -----------------
- arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi | 41 +++++++++++++++++++
- arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 33 +++++++++++++++
- 3 files changed, 74 insertions(+), 38 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-@@ -451,46 +451,8 @@
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "job", "mmu", "gpu";
-- operating-points-v2 = <&gpu_opp_table>;
- power-domains = <&power RK3588_PD_GPU>;
- status = "disabled";
--
-- gpu_opp_table: opp-table {
-- compatible = "operating-points-v2";
--
-- opp-300000000 {
-- opp-hz = /bits/ 64 <300000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-400000000 {
-- opp-hz = /bits/ 64 <400000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-500000000 {
-- opp-hz = /bits/ 64 <500000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-600000000 {
-- opp-hz = /bits/ 64 <600000000>;
-- opp-microvolt = <675000 675000 850000>;
-- };
-- opp-700000000 {
-- opp-hz = /bits/ 64 <700000000>;
-- opp-microvolt = <700000 700000 850000>;
-- };
-- opp-800000000 {
-- opp-hz = /bits/ 64 <800000000>;
-- opp-microvolt = <750000 750000 850000>;
-- };
-- opp-900000000 {
-- opp-hz = /bits/ 64 <900000000>;
-- opp-microvolt = <800000 800000 850000>;
-- };
-- opp-1000000000 {
-- opp-hz = /bits/ 64 <1000000000>;
-- opp-microvolt = <850000 850000 850000>;
-- };
-- };
- };
-
- usb_host0_xhci: usb@fc000000 {
---- a/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-opp.dtsi
-@@ -114,6 +114,43 @@
- clock-latency-ns = <40000>;
- };
- };
-+
-+ gpu_opp_table: opp-table {
-+ compatible = "operating-points-v2";
-+
-+ opp-300000000 {
-+ opp-hz = /bits/ 64 <300000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-400000000 {
-+ opp-hz = /bits/ 64 <400000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-500000000 {
-+ opp-hz = /bits/ 64 <500000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-600000000 {
-+ opp-hz = /bits/ 64 <600000000>;
-+ opp-microvolt = <675000 675000 850000>;
-+ };
-+ opp-700000000 {
-+ opp-hz = /bits/ 64 <700000000>;
-+ opp-microvolt = <700000 700000 850000>;
-+ };
-+ opp-800000000 {
-+ opp-hz = /bits/ 64 <800000000>;
-+ opp-microvolt = <750000 750000 850000>;
-+ };
-+ opp-900000000 {
-+ opp-hz = /bits/ 64 <900000000>;
-+ opp-microvolt = <800000 800000 850000>;
-+ };
-+ opp-1000000000 {
-+ opp-hz = /bits/ 64 <1000000000>;
-+ opp-microvolt = <850000 850000 850000>;
-+ };
-+ };
- };
-
- &cpu_b0 {
-@@ -147,3 +184,7 @@
- &cpu_l3 {
- operating-points-v2 = <&cluster0_opp_table>;
- };
-+
-+&gpu {
-+ operating-points-v2 = <&gpu_opp_table>;
-+};
---- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
-@@ -80,6 +80,35 @@
- clock-latency-ns = <40000>;
- };
- };
-+
-+ gpu_opp_table: opp-table {
-+ compatible = "operating-points-v2";
-+
-+ opp-300000000 {
-+ opp-hz = /bits/ 64 <300000000>;
-+ opp-microvolt = <750000 750000 850000>;
-+ };
-+ opp-400000000 {
-+ opp-hz = /bits/ 64 <400000000>;
-+ opp-microvolt = <750000 750000 850000>;
-+ };
-+ opp-500000000 {
-+ opp-hz = /bits/ 64 <500000000>;
-+ opp-microvolt = <750000 750000 850000>;
-+ };
-+ opp-600000000 {
-+ opp-hz = /bits/ 64 <600000000>;
-+ opp-microvolt = <750000 750000 850000>;
-+ };
-+ opp-700000000 {
-+ opp-hz = /bits/ 64 <700000000>;
-+ opp-microvolt = <750000 750000 850000>;
-+ };
-+ opp-850000000 {
-+ opp-hz = /bits/ 64 <800000000>;
-+ opp-microvolt = <787500 787500 850000>;
-+ };
-+ };
- };
-
- &cpu_b0 {
-@@ -113,3 +142,7 @@
- &cpu_l3 {
- operating-points-v2 = <&cluster0_opp_table>;
- };
-+
-+&gpu {
-+ operating-points-v2 = <&gpu_opp_table>;
-+};
+++ /dev/null
-From 0773a4a199aabb60afe50f5a19a6772abf4ad0bf Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Mon, 6 Nov 2023 16:54:32 +0100
-Subject: [PATCH] arm64: dts: rockchip: add USB3 host to rock-5a
-
-Enable USB3 host controller for the Radxa ROCK 5 Model A. This adds
-USB3 for the lower USB3 port (the one closer to the PCB).
-
-The upper USB3 port uses the RK3588 USB TypeC host controller, which
-use a different PHY without upstream support.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20231106155934.80838-2-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -113,6 +113,10 @@
- };
- };
-
-+&combphy2_psu {
-+ status = "okay";
-+};
-+
- &cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
- };
-@@ -734,3 +738,7 @@
- &usb_host1_ohci {
- status = "okay";
- };
-+
-+&usb_host2_xhci {
-+ status = "okay";
-+};
+++ /dev/null
-From af7ec140ddc1815bc462109792d95bcad05cfbc4 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Tue, 9 Apr 2024 00:50:36 +0200
-Subject: [PATCH] arm64: dts: rockchip: add upper USB3 port to rock-5a
-
-Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from
-Radxa Rock 5 Model A. The lower one is already supported.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240408225109.128953-10-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588s-rock-5a.dts | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -698,6 +698,14 @@
- };
- };
-
-+&u2phy0 {
-+ status = "okay";
-+};
-+
-+&u2phy0_otg {
-+ status = "okay";
-+};
-+
- &u2phy2 {
- status = "okay";
- };
-@@ -721,6 +729,11 @@
- status = "okay";
- };
-
-+&usbdp_phy0 {
-+ status = "okay";
-+ rockchip,dp-lane-mux = <2 3>;
-+};
-+
- &usb_host0_ehci {
- status = "okay";
- pinctrl-names = "default";
-@@ -731,6 +744,11 @@
- status = "okay";
- };
-
-+&usb_host0_xhci {
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
- &usb_host1_ehci {
- status = "okay";
- };
+++ /dev/null
-From 00224650dd45e166ea6eb1593f5f064583963ccf Mon Sep 17 00:00:00 2001
-From: FUKAUMI Naoki <naoki@radxa.com>
-Date: Sun, 23 Jun 2024 11:33:28 +0900
-Subject: [PATCH] arm64: dts: rockchip: add (but disabled) SFC node for Radxa
- ROCK 5A
-
-This commit adds SFC node for Radxa ROCK 5A.
-
-since sdhci and sfc on RK3588s share pins(i.e. exclusive), it cannot
-be enabled both nodes at the same time. so status = "okay" is omitted
-here.
-
-you may be able to enable sfc (and disable sdhci) by fdt overlay.
-
-SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
-
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Link: https://lore.kernel.org/r/20240623023329.1044-2-naoki@radxa.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -376,6 +376,19 @@
- status = "okay";
- };
-
-+&sfc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&fspim0_pins>;
-+
-+ flash@0 {
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <104000000>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <1>;
-+ };
-+};
-+
- &spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
+++ /dev/null
-From b728d4c51f0ce9207daf502f3a85073785c46319 Mon Sep 17 00:00:00 2001
-From: FUKAUMI Naoki <naoki@radxa.com>
-Date: Mon, 26 Aug 2024 17:04:56 +0900
-Subject: [PATCH] arm64: dts: rockchip: enable PCIe on M.2 E key for Radxa ROCK
- 5A
-
-Enable pcie2x1l2 and related combphy/regulator routed to M.2 E key
-connector on Radxa ROCK 5A.
-
-Tested with Radxa Wireless Module A8:
-
-$ lspci
-0004:40:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3588 (rev 01)
-0004:41:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8852BE PCIe 802.11ax Wireless Network Controller
-
-$ ip l
-1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
- link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
-2: end0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether c2:58:fc:70:55:86 brd ff:ff:ff:ff:ff:ff
-3: wlP4p65s0: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
- link/ether 2c:05:47:65:5b:ed brd ff:ff:ff:ff:ff:ff
-
-$ lsusb
-Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
-Bus 001 Device 002: ID 1a40:0101 Terminus Technology Inc. Hub
-Bus 001 Device 003: ID 0bda:b85b Realtek Semiconductor Corp. Bluetooth Radio
-Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
-Bus 003 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
-Bus 004 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
-Bus 005 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
-Bus 006 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
-Bus 006 Device 002: ID 0789:0336 Logitec Corp. LMD USB Device
-Bus 007 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
-Bus 008 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
-
-$ hciconfig
-hci0: Type: Primary Bus: USB
- BD Address: 2C:05:47:65:5B:EE ACL MTU: 1021:6 SCO MTU: 255:12
- UP RUNNING
- RX bytes:2698 acl:0 sco:0 events:329 errors:0
- TX bytes:69393 acl:0 sco:0 commands:329 errors:0
-
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Link: https://lore.kernel.org/r/20240826080456.525-1-naoki@radxa.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588s-rock-5a.dts | 30 +++++++++++++++++++
- 1 file changed, 30 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -64,6 +64,18 @@
- regulator-max-microvolt = <12000000>;
- };
-
-+ vcc3v3_wf: vcc3v3-wf-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_wf";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-0 = <&pow_en>;
-+ pinctrl-names = "default";
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
-@@ -113,6 +125,10 @@
- };
- };
-
-+&combphy0_ps {
-+ status = "okay";
-+};
-+
- &combphy2_psu {
- status = "okay";
- };
-@@ -292,6 +308,14 @@
- };
- };
-
-+&pcie2x1l2 {
-+ pinctrl-0 = <&pcie20x1m0_pins>;
-+ pinctrl-names = "default";
-+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_wf>;
-+ status = "okay";
-+};
-+
- &pinctrl {
- leds {
- io_led: io-led {
-@@ -299,6 +323,12 @@
- };
- };
-
-+ pcie {
-+ pow_en: pow-en {
-+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
- power {
- vcc_5v0_en: vcc-5v0-en {
- rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+++ /dev/null
-From 42145b7a823530f57983fb6e6897f40c0be278d5 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Mon, 18 Sep 2023 16:14:49 +0200
-Subject: [PATCH] arm64: dts: rockchip: add PCIe network controller to rock-5b
-
-Enable the RTL8125 network controller, which is connected via
-PCIe.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20230918141451.131247-2-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-rock-5b.dts | 27 +++++++++++++++++++
- 1 file changed, 27 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -43,6 +43,15 @@
- #cooling-cells = <2>;
- };
-
-+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_pcie2x1l2";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <5000>;
-+ vin-supply = <&vcc_3v3_s3>;
-+ };
-+
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
-@@ -77,6 +86,10 @@
- };
- };
-
-+&combphy0_ps {
-+ status = "okay";
-+};
-+
- &cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
- };
-@@ -203,6 +216,14 @@
- };
- };
-
-+&pcie2x1l2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie2_2_rst>;
-+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
-+ status = "okay";
-+};
-+
- &pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
-@@ -216,6 +237,12 @@
- };
- };
-
-+ pcie2 {
-+ pcie2_2_rst: pcie2-2-rst {
-+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+++ /dev/null
-From 199cbd5f195adbc0e70ad218cdba82f45750f11b Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Mon, 18 Sep 2023 16:14:50 +0200
-Subject: [PATCH] arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b
-
-The Radxa Rock 5B has PCIe 3x4 routed to its M.2 M-key connector
-on the board's back.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20230918141451.131247-3-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -52,6 +52,19 @@
- vin-supply = <&vcc_3v3_s3>;
- };
-
-+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie3_vcc3v3_en>;
-+ regulator-name = "vcc3v3_pcie30";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <5000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
-@@ -224,6 +237,18 @@
- status = "okay";
- };
-
-+&pcie30phy {
-+ status = "okay";
-+};
-+
-+&pcie3x4 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie3_rst>;
-+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie30>;
-+ status = "okay";
-+};
-+
- &pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
-@@ -243,6 +268,16 @@
- };
- };
-
-+ pcie3 {
-+ pcie3_rst: pcie3-rst {
-+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie3_vcc3v3_en: pcie3-vcc3v3-en {
-+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+++ /dev/null
-From da447ec387800bdf2df1fb1d8c1522991d025952 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Mon, 18 Sep 2023 16:14:51 +0200
-Subject: [PATCH] arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b
-
-Enable PCIe2_0 controller and its voltage supply, which is routed
-to the M.2 E-Key on the upper side of the Radxa Rock 5B.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20230918141451.131247-4-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -43,6 +43,21 @@
- #cooling-cells = <2>;
- };
-
-+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
-+ regulator-name = "vcc3v3_pcie2x1l0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <50000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
- vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie2x1l2";
-@@ -103,6 +118,10 @@
- status = "okay";
- };
-
-+&combphy1_ps {
-+ status = "okay";
-+};
-+
- &cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
- };
-@@ -229,6 +248,14 @@
- };
- };
-
-+&pcie2x1l0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie2_0_rst>;
-+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
-+ status = "okay";
-+};
-+
- &pcie2x1l2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_2_rst>;
-@@ -263,6 +290,14 @@
- };
-
- pcie2 {
-+ pcie2_0_rst: pcie2-0-rst {
-+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
-+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
- pcie2_2_rst: pcie2-2-rst {
- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
+++ /dev/null
-From 1c9a53ff7ece056eb995332f0d9523ca43fdcb5a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= <tszucs@protonmail.ch>
-Date: Sun, 24 Sep 2023 20:37:45 +0000
-Subject: [PATCH] arm64: dts: rockchip: Add sdio node to rock-5b
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Enable SDIO on Radxa ROCK 5 Model B M.2 Key E. Add sdio node and alias as mmc2.
-Add regulator for the 3.3 V rail bringing it up during boot. Make sure EKEY_EN
-is muxed as GPIO.
-
-Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch>
-Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20230924203740.65744-1-tszucs@protonmail.ch
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-rock-5b.dts | 43 +++++++++++++++++++
- 1 file changed, 43 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -12,6 +12,7 @@
- aliases {
- mmc0 = &sdhci;
- mmc1 = &sdmmc;
-+ mmc2 = &sdio;
- };
-
- chosen {
-@@ -112,6 +113,21 @@
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
- };
-+
-+ vcc3v3_wf: vcc3v3-wf-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_wf";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ enable-active-high;
-+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc3v3_wf_en>;
-+ startup-delay-us = <50000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
- };
-
- &combphy0_ps {
-@@ -318,6 +334,12 @@
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-+
-+ m2e {
-+ vcc3v3_wf_en: vcc3v3-wf-en {
-+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
- };
-
- &pwm1 {
-@@ -354,6 +376,27 @@
- status = "okay";
- };
-
-+&sdio {
-+ max-frequency = <200000000>;
-+ no-sd;
-+ no-mmc;
-+ non-removable;
-+ bus-width = <4>;
-+ cap-sdio-irq;
-+ disable-wp;
-+ keep-power-in-suspend;
-+ wakeup-source;
-+ sd-uhs-sdr12;
-+ sd-uhs-sdr25;
-+ sd-uhs-sdr50;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc3v3_wf>;
-+ vqmmc-supply = <&vcc_1v8_s3>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdiom0_pins>;
-+ status = "okay";
-+};
-+
- &spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
+++ /dev/null
-From 0002c377e862140ad65b67b8b9dbf086d4578f95 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= <tszucs@protonmail.ch>
-Date: Wed, 11 Oct 2023 18:18:05 +0000
-Subject: [PATCH] arm64: dts: rockchip: Remove duplicate regulator vcc3v3_wf
- from rock-5b
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Regulator for VCC3V3_WF has been added as vcc3v3_pcie2x1l0 first. Clean this up.
-
-Fixes: 1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b")
-Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch>
-Link: https://lore.kernel.org/r/20231011181757.58047-1-tszucs@protonmail.ch
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-rock-5b.dts | 23 +------------------
- 1 file changed, 1 insertion(+), 22 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -113,21 +113,6 @@
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vcc5v0_sys>;
- };
--
-- vcc3v3_wf: vcc3v3-wf-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc3v3_wf";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- enable-active-high;
-- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&vcc3v3_wf_en>;
-- startup-delay-us = <50000>;
-- vin-supply = <&vcc5v0_sys>;
-- };
- };
-
- &combphy0_ps {
-@@ -334,12 +319,6 @@
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
--
-- m2e {
-- vcc3v3_wf_en: vcc3v3-wf-en {
-- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
-- };
- };
-
- &pwm1 {
-@@ -390,7 +369,7 @@
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
-- vmmc-supply = <&vcc3v3_wf>;
-+ vmmc-supply = <&vcc3v3_pcie2x1l0>;
- vqmmc-supply = <&vcc_1v8_s3>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdiom0_pins>;
+++ /dev/null
-From a6169ab369236f15c79b45037074a2567d30b037 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= <szucst@iit.uni-miskolc.hu>
-Date: Fri, 13 Oct 2023 23:51:53 +0200
-Subject: [PATCH] arm64: dts: rockchip: Enable UART6 on rock-5b
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Enable UART lines on Radxa ROCK 5 Model B M.2 Key E.
-
-Signed-off-by: Tamás Szűcs <szucst@iit.uni-miskolc.hu>
-Link: https://lore.kernel.org/r/20231013215208.81345-1-szucst@iit.uni-miskolc.hu
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -376,6 +376,12 @@
- status = "okay";
- };
-
-+&uart6 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
-+ status = "okay";
-+};
-+
- &spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
+++ /dev/null
-From 7952cbbda301f7d297c6ac761f9dfafb90205358 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Thu, 5 Oct 2023 15:40:37 +0200
-Subject: [PATCH] arm64: dts: rockchip: add status LED to rock-5b
-
-Describe the Rock 5B status LED in its device tree.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20231005134037.33231-1-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-rock-5b.dts | 20 +++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -3,6 +3,7 @@
- /dts-v1/;
-
- #include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
- #include "rk3588.dtsi"
-
- / {
-@@ -36,6 +37,19 @@
- pinctrl-0 = <&hp_detect>;
- };
-
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led_rgb_b>;
-+
-+ led_rgb_b {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_BLUE>;
-+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
-+ };
-+
- fan: pwm-fan {
- compatible = "pwm-fan";
- cooling-levels = <0 95 145 195 255>;
-@@ -284,6 +298,12 @@
- };
- };
-
-+ leds {
-+ led_rgb_b: led-rgb-b {
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
- sound {
- hp_detect: hp-detect {
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+++ /dev/null
-From f97d78b9f6cff4c680206a8c8b03f726f0dc2c8b Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Mon, 6 Nov 2023 16:54:31 +0100
-Subject: [PATCH] arm64: dts: rockchip: add USB3 host to rock-5b
-
-Enable USB3 host controller for the Radxa ROCK 5 Model B. This adds
-USB3 for the upper USB3 port (the one further away from the PCB).
-
-The lower USB3 and the USB-C ports use the RK3588 USB TypeC host
-controller, which use a different PHY without upstream support.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20231106155934.80838-1-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -137,6 +137,10 @@
- status = "okay";
- };
-
-+&combphy2_psu {
-+ status = "okay";
-+};
-+
- &cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
- };
-@@ -764,3 +768,7 @@
- &usb_host1_ohci {
- status = "okay";
- };
-+
-+&usb_host2_xhci {
-+ status = "okay";
-+};
+++ /dev/null
-From 7738f551173540b3daa63a91b384b167eacd24fd Mon Sep 17 00:00:00 2001
-From: John Clark <inindev@gmail.com>
-Date: Mon, 25 Dec 2023 22:28:19 +0000
-Subject: [PATCH] arm64: dts: rockchip: support poweroff on the rock-5b
-
-Allow the rock-5b to poweroff its pmic. When issuing a "shutdown -h now"
-on the rock-5b it reboots instead. Defining 'system-power-controller'
-allows the rk806 to power down.
-
-Commit c699fbfdfd54 ("arm64: dts: rockchip: Support poweroff on
-NanoPC-T6") similarly resolves this issue for the nanopc-t6.
-
-Signed-off-by: John Clark <inindev@gmail.com>
-Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20231225222859.17153-1-inindev@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -426,6 +426,8 @@
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-
-+ system-power-controller;
-+
- vcc1-supply = <&vcc5v0_sys>;
- vcc2-supply = <&vcc5v0_sys>;
- vcc3-supply = <&vcc5v0_sys>;
+++ /dev/null
-From aed6514c4e3aee843385ded4c5ee0921b51c30fa Mon Sep 17 00:00:00 2001
-From: John Clark <inindev@gmail.com>
-Date: Mon, 25 Dec 2023 22:28:20 +0000
-Subject: [PATCH] arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b
-
-Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and
-gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1.
-
-Signed-off-by: John Clark <inindev@gmail.com>
-Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20231225222859.17153-2-inindev@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -448,7 +448,7 @@
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
-- pins = "gpio_pwrctrl2";
-+ pins = "gpio_pwrctrl1";
- function = "pin_fun0";
- };
-
+++ /dev/null
-From 82d40b141a4c7ab6608a84a5ce0c58b747cb7163 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Sun, 7 Jan 2024 00:26:45 +0400
-Subject: [PATCH] arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b
-
-By default the GPIO pin that connects to the WiFi enable signal
-inside the M.2 Key E slot is driven low, resulting in impossibility
-to connect to any network. Add a DT node to expose it as an RFKILL
-device, which lets the WiFi driver or userspace toggle it as
-required.
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
-Link: https://lore.kernel.org/r/20240106202650.22310-1-alchark@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -58,6 +58,13 @@
- #cooling-cells = <2>;
- };
-
-+ rfkill {
-+ compatible = "rfkill-gpio";
-+ label = "rfkill-pcie-wlan";
-+ radio-type = "wlan";
-+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
-+ };
-+
- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
+++ /dev/null
-From 038347286941148b6fd0cc2c40afcd540315aa6f Mon Sep 17 00:00:00 2001
-From: Boris Brezillon <boris.brezillon@collabora.com>
-Date: Tue, 26 Mar 2024 17:52:07 +0100
-Subject: [PATCH] arm64: dts: rockchip: Enable GPU on rk3588-rock5b
-
-Enable the Mali GPU in the Rock 5B.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240326165232.73585-4-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -180,6 +180,11 @@
- cpu-supply = <&vdd_cpu_lit_s0>;
- };
-
-+&gpu {
-+ mali-supply = <&vdd_gpu_s0>;
-+ status = "okay";
-+};
-+
- &i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
+++ /dev/null
-From 45e831033f7a00a14f64afa1e34c476a9ff0f9f0 Mon Sep 17 00:00:00 2001
-From: Dragan Simic <dsimic@manjaro.org>
-Date: Thu, 18 Apr 2024 18:26:20 +0200
-Subject: [PATCH] arm64: dts: rockchip: Correct the model names for Radxa ROCK
- 5 boards
-
-Correct the descriptions of a few Radxa boards, according to the up-to-date
-documentation from Radxa and the detailed explanation from Naoki. [1] To sum
-it up, the short naming, as specified by Radxa, is preferred.
-
-[1] https://lore.kernel.org/linux-rockchip/B26C732A4DCEA9B3+282b8775-601b-4d4a-a513-4924b7940076@radxa.com/
-
-Suggested-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/6931289a252dc2d6c7bfd2388835c5e98ba0d8c9.1713457260.git.dsimic@manjaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +-
- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -7,7 +7,7 @@
- #include "rk3588.dtsi"
-
- / {
-- model = "Radxa ROCK 5 Model B";
-+ model = "Radxa ROCK 5B";
- compatible = "radxa,rock-5b", "rockchip,rk3588";
-
- aliases {
---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -8,7 +8,7 @@
- #include "rk3588s.dtsi"
-
- / {
-- model = "Radxa ROCK 5 Model A";
-+ model = "Radxa ROCK 5A";
- compatible = "radxa,rock-5a", "rockchip,rk3588s";
-
- aliases {
+++ /dev/null
-From 494532921aacb496529d544fedfdb3a7b43dfef0 Mon Sep 17 00:00:00 2001
-From: Sebastian Reichel <sebastian.reichel@collabora.com>
-Date: Tue, 9 Apr 2024 00:50:37 +0200
-Subject: [PATCH] arm64: dts: rockchip: add lower USB3 port to rock-5b
-
-Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from
-Radxa Rock 5 Model B. The upper one is already supported.
-
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20240408225109.128953-11-sebastian.reichel@collabora.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -748,6 +748,14 @@
- status = "okay";
- };
-
-+&u2phy1 {
-+ status = "okay";
-+};
-+
-+&u2phy1_otg {
-+ status = "okay";
-+};
-+
- &u2phy2 {
- status = "okay";
- };
-@@ -767,6 +775,10 @@
- status = "okay";
- };
-
-+&usbdp_phy1 {
-+ status = "okay";
-+};
-+
- &usb_host0_ehci {
- status = "okay";
- };
-@@ -783,6 +795,11 @@
- status = "okay";
- };
-
-+&usb_host1_xhci {
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
- &usb_host2_xhci {
- status = "okay";
- };
+++ /dev/null
-From 4a152231b050590af771fa3cc8462ed08b691a24 Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 17 Jun 2024 22:28:54 +0400
-Subject: [PATCH] arm64: dts: rockchip: enable automatic fan control on Rock 5B
-
-This links the PWM fan on Radxa Rock 5B as an active cooling device
-managed automatically by the thermal subsystem, with a target SoC
-temperature of 65C and a minimum-spin interval from 55C to 65C to
-ensure airflow when the system gets warm
-
-Helped-by: Dragan Simic <dsimic@manjaro.org>
-Reviewed-by: Dragan Simic <dsimic@manjaro.org>
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
-Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-4-c1f5f3267f1e@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-rock-5b.dts | 32 ++++++++++++++++++-
- 1 file changed, 31 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -52,7 +52,7 @@
-
- fan: pwm-fan {
- compatible = "pwm-fan";
-- cooling-levels = <0 95 145 195 255>;
-+ cooling-levels = <0 120 150 180 210 240 255>;
- fan-supply = <&vcc5v0_sys>;
- pwms = <&pwm1 0 50000 0>;
- #cooling-cells = <2>;
-@@ -278,6 +278,36 @@
- };
- };
- };
-+
-+&package_thermal {
-+ polling-delay = <1000>;
-+
-+ trips {
-+ package_fan0: package-fan0 {
-+ temperature = <55000>;
-+ hysteresis = <2000>;
-+ type = "active";
-+ };
-+
-+ package_fan1: package-fan1 {
-+ temperature = <65000>;
-+ hysteresis = <2000>;
-+ type = "active";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map1 {
-+ trip = <&package_fan0>;
-+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
-+ };
-+
-+ map2 {
-+ trip = <&package_fan1>;
-+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
-+ };
-+ };
-+};
-
- &pcie2x1l0 {
- pinctrl-names = "default";
+++ /dev/null
-From 9204a7ecca96403ee3d61c14cb9eb87ec89b0fcd Mon Sep 17 00:00:00 2001
-From: FUKAUMI Naoki <naoki@radxa.com>
-Date: Sun, 23 Jun 2024 11:33:27 +0900
-Subject: [PATCH] arm64: dts: rockchip: add SFC support for Radxa ROCK 5B
-
-This commit adds support for SPI NOR flash on Radxa ROCK 5B.
-
-SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency.
-
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Link: https://lore.kernel.org/r/20240623023329.1044-1-naoki@radxa.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -442,6 +442,20 @@
- status = "okay";
- };
-
-+&sfc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&fspim2_pins>;
-+ status = "okay";
-+
-+ flash@0 {
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <104000000>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <1>;
-+ };
-+};
-+
- &uart6 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
+++ /dev/null
-From f1b11f43b3e983b26d8010fc43ba6c2b979826f2 Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Sat, 30 Dec 2023 14:18:00 +0300
-Subject: [PATCH] arm64: dts: rockchip: Add support for NanoPi R6S
-
-Add basic NanoPi R6S support that comes with USB2, PCIe, SD card, eMMC
-support.
-
-Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com>
-Link: https://lore.kernel.org/r/6db3b653efc6f0a2dca8e96fdd0503906db72fb6.1703934548.git.efectn@protonmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 764 ++++++++++++++++++
- 2 files changed, 765 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -109,4 +109,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-na
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
-@@ -0,0 +1,764 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include "rk3588s.dtsi"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R6S";
-+ compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s";
-+
-+ aliases {
-+ ethernet0 = &gmac1;
-+ mmc0 = &sdmmc;
-+ mmc1 = &sdhci;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ adc-keys {
-+ compatible = "adc-keys";
-+ io-channels = <&saradc 0>;
-+ io-channel-names = "buttons";
-+ keyup-threshold-microvolt = <1800000>;
-+ poll-interval = <100>;
-+
-+ button-maskrom {
-+ label = "Maskrom";
-+ linux,code = <KEY_VENDOR>;
-+ press-threshold-microvolt = <1800>;
-+ };
-+ };
-+
-+ gpio-keys {
-+ compatible = "gpio-keys";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&key1_pin>;
-+
-+ button-user {
-+ label = "User";
-+ linux,code = <BTN_1>;
-+ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
-+ debounce-interval = <50>;
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ sys_led: led-0 {
-+ label = "sys_led";
-+ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sys_led_pin>;
-+ };
-+
-+ wan_led: led-1 {
-+ label = "wan_led";
-+ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wan_led_pin>;
-+ };
-+
-+ lan1_led: led-2 {
-+ label = "lan1_led";
-+ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lan1_led_pin>;
-+ };
-+
-+ lan2_led: led-3 {
-+ label = "lan2_led";
-+ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lan2_led_pin>;
-+ };
-+ };
-+
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_1v1_nldo_s3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1100000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc_3v3_s0: vcc-3v3-s0-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vcc_3v3_s0";
-+ vin-supply = <&vcc_3v3_s3>;
-+ };
-+
-+ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sd_s0_pwr>;
-+ regulator-name = "vcc_3v3_sd_s0";
-+ regulator-boot-on;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-min-microvolt = <3000000>;
-+ vin-supply = <&vcc_3v3_s3>;
-+ };
-+
-+ vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_3v3_pcie20";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc_3v3_s3>;
-+ };
-+
-+ vcc5v0_usb: vcc5v0-usb-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_usb";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&typec5v_pwren>;
-+ regulator-name = "vcc5v0_usb_otg0";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+
-+ vcc5v0_host_20: vcc5v0-host-20-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_host20_en>;
-+ regulator-name = "vcc5v0_host_20";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+};
-+
-+&combphy0_ps {
-+ status = "okay";
-+};
-+
-+&combphy2_psu {
-+ status = "okay";
-+};
-+
-+&cpu_b0 {
-+ cpu-supply = <&vdd_cpu_big0_s0>;
-+};
-+
-+&cpu_b1 {
-+ cpu-supply = <&vdd_cpu_big0_s0>;
-+};
-+
-+&cpu_b2 {
-+ cpu-supply = <&vdd_cpu_big1_s0>;
-+};
-+
-+&cpu_b3 {
-+ cpu-supply = <&vdd_cpu_big1_s0>;
-+};
-+
-+&cpu_l0 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l1 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l2 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l3 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&gmac1 {
-+ clock_in_out = "output";
-+ phy-handle = <&rgmii_phy1>;
-+ phy-mode = "rgmii-rxid";
-+ pinctrl-0 = <&gmac1_miim
-+ &gmac1_tx_bus2
-+ &gmac1_rx_bus2
-+ &gmac1_rgmii_clk
-+ &gmac1_rgmii_bus>;
-+ pinctrl-names = "default";
-+ tx_delay = <0x42>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0m2_xfer>;
-+ status = "okay";
-+
-+ vdd_cpu_big0_s0: regulator@42 {
-+ compatible = "rockchip,rk8602";
-+ reg = <0x42>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu_big0_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <1050000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_cpu_big1_s0: regulator@43 {
-+ compatible = "rockchip,rk8603", "rockchip,rk8602";
-+ reg = <0x43>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu_big1_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <1050000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+};
-+
-+&i2c2 {
-+ status = "okay";
-+
-+ vdd_npu_s0: regulator@42 {
-+ compatible = "rockchip,rk8602";
-+ reg = <0x42>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_npu_s0";
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <2300>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+};
-+
-+&i2c6 {
-+ clock-frequency = <200000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c6m0_xfer>;
-+ status = "okay";
-+
-+ hym8563: rtc@51 {
-+ compatible = "haoyu,hym8563";
-+ reg = <0x51>;
-+ #clock-cells = <0>;
-+ clock-output-names = "hym8563";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rtc_int>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
-+ wakeup-source;
-+ };
-+};
-+
-+&mdio1 {
-+ rgmii_phy1: ethernet-phy@1 {
-+ compatible = "ethernet-phy-id001c.c916";
-+ reg = <0x1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rtl8211f_rst>;
-+ reset-assert-us = <20000>;
-+ reset-deassert-us = <100000>;
-+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
-+ };
-+};
-+
-+&pcie2x1l1 {
-+ reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
-+ status = "okay";
-+};
-+
-+&pcie2x1l2 {
-+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ gpio-key {
-+ key1_pin: key1-pin {
-+ rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ gpio-leds {
-+ sys_led_pin: sys-led-pin {
-+ rockchip,pins =
-+ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wan_led_pin: wan-led-pin {
-+ rockchip,pins =
-+ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ lan1_led_pin: lan1-led-pin {
-+ rockchip,pins =
-+ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ lan2_led_pin: lan2-led-pin {
-+ rockchip,pins =
-+ <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ hym8563 {
-+ rtc_int: rtc-int {
-+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ sdmmc {
-+ sd_s0_pwr: sd-s0-pwr {
-+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb {
-+ typec5v_pwren: typec5v-pwren {
-+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ vcc5v0_host20_en: vcc5v0-host20-en {
-+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ rtl8211f {
-+ rtl8211f_rst: rtl8211f-rst {
-+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&saradc {
-+ vref-supply = <&avcc_1v8_s0>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ no-sdio;
-+ no-sd;
-+ non-removable;
-+ mmc-hs200-1_8v;
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ max-frequency = <150000000>;
-+ no-mmc;
-+ no-sdio;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc_3v3_sd_s0>;
-+ vqmmc-supply = <&vccio_sd_s0>;
-+ status = "okay";
-+};
-+
-+&spi2 {
-+ status = "okay";
-+ assigned-clocks = <&cru CLK_SPI2>;
-+ assigned-clock-rates = <200000000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
-+ num-cs = <1>;
-+
-+ pmic@0 {
-+ compatible = "rockchip,rk806";
-+ spi-max-frequency = <1000000>;
-+ reg = <0x0>;
-+
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-+
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
-+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-+
-+ system-power-controller;
-+
-+ vcc1-supply = <&vcc5v0_sys>;
-+ vcc2-supply = <&vcc5v0_sys>;
-+ vcc3-supply = <&vcc5v0_sys>;
-+ vcc4-supply = <&vcc5v0_sys>;
-+ vcc5-supply = <&vcc5v0_sys>;
-+ vcc6-supply = <&vcc5v0_sys>;
-+ vcc7-supply = <&vcc5v0_sys>;
-+ vcc8-supply = <&vcc5v0_sys>;
-+ vcc9-supply = <&vcc5v0_sys>;
-+ vcc10-supply = <&vcc5v0_sys>;
-+ vcc11-supply = <&vcc_2v0_pldo_s3>;
-+ vcc12-supply = <&vcc5v0_sys>;
-+ vcc13-supply = <&vcc_1v1_nldo_s3>;
-+ vcc14-supply = <&vcc_1v1_nldo_s3>;
-+ vcca-supply = <&vcc5v0_sys>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ rk806_dvs1_null: dvs1-null-pins {
-+ pins = "gpio_pwrctrl1";
-+ function = "pin_fun0";
-+ };
-+
-+ rk806_dvs2_null: dvs2-null-pins {
-+ pins = "gpio_pwrctrl2";
-+ function = "pin_fun0";
-+ };
-+
-+ rk806_dvs3_null: dvs3-null-pins {
-+ pins = "gpio_pwrctrl3";
-+ function = "pin_fun0";
-+ };
-+
-+ regulators {
-+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_gpu_s0";
-+ regulator-enable-ramp-delay = <400>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_cpu_lit_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_log_s0: dcdc-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <675000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_log_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <750000>;
-+ };
-+ };
-+
-+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_vdenc_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_ddr_s0: dcdc-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <675000>;
-+ regulator-max-microvolt = <900000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_ddr_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <850000>;
-+ };
-+ };
-+
-+ vdd2_ddr_s3: dcdc-reg6 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-name = "vdd2_ddr_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc_2v0_pldo_s3: dcdc-reg7 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <2000000>;
-+ regulator-max-microvolt = <2000000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_2v0_pldo_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <2000000>;
-+ };
-+ };
-+
-+ vcc_3v3_s3: dcdc-reg8 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vcc_3v3_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vddq_ddr_s0: dcdc-reg9 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-name = "vddq_ddr_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8_s3: dcdc-reg10 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcc_1v8_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ avcc_1v8_s0: pldo-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "avcc_1v8_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcc_1v8_s0: pldo-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcc_1v8_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ avdd_1v2_s0: pldo-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1200000>;
-+ regulator-max-microvolt = <1200000>;
-+ regulator-name = "avdd_1v2_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ avcc_3v3_s0: pldo-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "avcc_3v3_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd_s0: pldo-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vccio_sd_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ pldo6_s3: pldo-reg6 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "pldo6_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdd_0v75_s3: nldo-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "vdd_0v75_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <750000>;
-+ };
-+ };
-+
-+ avdd_ddr_pll_s0: nldo-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <850000>;
-+ regulator-max-microvolt = <850000>;
-+ regulator-name = "avdd_ddr_pll_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <850000>;
-+ };
-+ };
-+
-+ avdd_0v75_s0: nldo-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "avdd_0v75_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ avdd_0v85_s0: nldo-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <850000>;
-+ regulator-max-microvolt = <850000>;
-+ regulator-name = "avdd_0v85_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_0v75_s0: nldo-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "vdd_0v75_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&tsadc {
-+ status = "okay";
-+};
-+
-+&u2phy2 {
-+ status = "okay";
-+};
-+
-+&u2phy2_host {
-+ phy-supply = <&vcc5v0_host_20>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ pinctrl-0 = <&uart2m0_xfer>;
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
+++ /dev/null
-From d5f1d7437451dbd86a91747793ecd7842e0ce88f Mon Sep 17 00:00:00 2001
-From: Muhammed Efe Cetin <efectn@protonmail.com>
-Date: Sat, 30 Dec 2023 14:18:01 +0300
-Subject: [PATCH] arm64: dts: rockchip: Add support for NanoPi R6C
-
-NanoPi R6C is mostly same as R6S variant. It has M2 port instead of a
-NIC port and different led labeling.
-
-Signed-off-by: Muhammed Efe Cetin <efectn@protonmail.com>
-Link: https://lore.kernel.org/r/0f9ee0baa6c9de4d54dd6d13957ca15a63ec934f.1703934548.git.efectn@protonmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 14 ++++++++++++++
- 2 files changed, 15 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -110,4 +110,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
-@@ -0,0 +1,14 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+
-+#include "rk3588s-nanopi-r6s.dts"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R6C";
-+ compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s";
-+};
-+
-+&lan2_led {
-+ label = "user_led";
-+};
+++ /dev/null
-From c699fbfdfd54630fc51b96da577f02e7b772eb37 Mon Sep 17 00:00:00 2001
-From: Hugh Cole-Baker <sigmaris@gmail.com>
-Date: Sat, 16 Dec 2023 21:21:34 +0000
-Subject: [PATCH] arm64: dts: rockchip: Support poweroff on NanoPC-T6
-
-The RK806 on the NanoPC-T6 can be used to power on/off the whole board.
-Mark it as the system power controller.
-
-Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
-Link: https://lore.kernel.org/r/20231216212134.23314-1-sigmaris@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -569,6 +569,8 @@
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-
-+ system-power-controller;
-+
- vcc1-supply = <&vcc4v0_sys>;
- vcc2-supply = <&vcc4v0_sys>;
- vcc3-supply = <&vcc4v0_sys>;
+++ /dev/null
-From 9e1faff1cbc877903d019a7943d37ddc5042704d Mon Sep 17 00:00:00 2001
-From: John Clark <inindev@gmail.com>
-Date: Thu, 28 Dec 2023 17:29:35 +0000
-Subject: [PATCH] arm64: dts: rockchip: nanopc-t6 sdmmc beautification
-
-drop max-frequency = <200000000> as it is already defined in rk3588s.dtsi
-order no-sdio & no-mmc properties while we are here
-
-Signed-off-by: John Clark <inindev@gmail.com>
-Link: https://lore.kernel.org/r/20231228173011.2863-1-inindev@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 5 ++---
- 1 file changed, 2 insertions(+), 3 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -536,13 +536,12 @@
- };
-
- &sdmmc {
-- max-frequency = <200000000>;
-- no-sdio;
-- no-mmc;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
-+ no-mmc;
-+ no-sdio;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
+++ /dev/null
-From 24559788384916041a0bbf54c32e2a16b612d247 Mon Sep 17 00:00:00 2001
-From: John Clark <inindev@gmail.com>
-Date: Mon, 25 Dec 2023 22:32:16 +0000
-Subject: [PATCH] arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6
-
-Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and
-gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1.
-
-Signed-off-by: John Clark <inindev@gmail.com>
-Link: https://lore.kernel.org/r/20231225223226.17690-1-inindev@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -590,7 +590,7 @@
- #gpio-cells = <2>;
-
- rk806_dvs1_null: dvs1-null-pins {
-- pins = "gpio_pwrctrl2";
-+ pins = "gpio_pwrctrl1";
- function = "pin_fun0";
- };
-
+++ /dev/null
-From d235e65adf00f6db09331874c5a987b7fe18023b Mon Sep 17 00:00:00 2001
-From: Hugh Cole-Baker <sigmaris@gmail.com>
-Date: Tue, 9 Jan 2024 20:27:28 +0000
-Subject: [PATCH] arm64: dts: rockchip: enable NanoPC-T6 MiniPCIe power
-
-The NanoPC-T6 has a Mini PCIe slot intended to be used for a 4G or LTE
-modem. This slot has no PCIe functionality, only USB 2.0 pins are wired
-to the SoC, and USIM pins are wired to a SIM card slot on the board.
-Define the 3.3v supply for the slot so it can be used.
-
-Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
-Link: https://lore.kernel.org/r/20240109202729.54292-1-sigmaris@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -159,6 +159,18 @@
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
- };
-+
-+ vdd_4g_3v3: vdd-4g-3v3-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pin_4g_lte_pwren>;
-+ regulator-name = "vdd_4g_3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
- };
-
- &combphy0_ps {
-@@ -504,6 +516,10 @@
- };
-
- usb {
-+ pin_4g_lte_pwren: 4g-lte-pwren {
-+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
- typec5v_pwren: typec5v-pwren {
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-@@ -884,6 +900,7 @@
- };
-
- &u2phy2_host {
-+ phy-supply = <&vdd_4g_3v3>;
- status = "okay";
- };
-
+++ /dev/null
-From d8bb6c2311b6b2aad11b937f96db1d6c3393246a Mon Sep 17 00:00:00 2001
-From: John Clark <inindev@gmail.com>
-Date: Sat, 30 Dec 2023 11:50:53 -0500
-Subject: [PATCH] arm64: dts: rockchip: add sdmmc card detect to the nanopc-t6
-
-The nanopc-t6 has an sdmmc card detect connected to gpio0_a4 which is
-active low.
-
-Signed-off-by: John Clark <inindev@gmail.com>
-Link: https://lore.kernel.org/r/20231230165053.3781-1-inindev@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -555,6 +555,7 @@
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
-+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- no-mmc;
- no-sdio;
+++ /dev/null
-From 6cb02674a061e4ef4f437ab60c91038d4c0d85ef Mon Sep 17 00:00:00 2001
-From: John Clark <inindev@gmail.com>
-Date: Tue, 2 Jan 2024 02:40:53 +0000
-Subject: [PATCH] arm64: dts: rockchip: fix nanopc-t6 sdmmc regulator
-
-sdmmc on the nanopc-t6 is powered by vcc3v3_sd_s0, not vcc_3v3_s3
-add the vcc3v3_sd_s0 regulator, and control it with gpio4_a5
-
-Signed-off-by: John Clark <inindev@gmail.com>
-Link: https://lore.kernel.org/r/20240102024054.1030313-1-inindev@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -160,6 +160,17 @@
- vin-supply = <&vcc5v0_sys>;
- };
-
-+ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-low;
-+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>;
-+ regulator-boot-on;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-name = "vcc3v3_sd_s0";
-+ vin-supply = <&vcc_3v3_s3>;
-+ };
-+
- vdd_4g_3v3: vdd-4g-3v3-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
-@@ -560,7 +571,7 @@
- no-mmc;
- no-sdio;
- sd-uhs-sdr104;
-- vmmc-supply = <&vcc_3v3_s3>;
-+ vmmc-supply = <&vcc3v3_sd_s0>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
- };
+++ /dev/null
-From d14f3a4f1feabb6bb5935bf3b275a1e6bf2208eb Mon Sep 17 00:00:00 2001
-From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Date: Thu, 29 Aug 2024 14:26:53 +0200
-Subject: [PATCH] arm64: dts: rockchip: prepare NanoPC-T6 for LTS board
-
-FriendlyELEC introduced a second version of NanoPC-T6 SBC.
-
-Create common include file and make NanoPC-T6 use it. Following
-patches will add LTS version.
-
-Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-2-edff247e8c02@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-nanopc-t6.dts | 932 +----------------
- .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 945 ++++++++++++++++++
- 2 files changed, 947 insertions(+), 930 deletions(-)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -2,944 +2,16 @@
- /*
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2023 Thomas McKahan
-+ * Copyright (c) 2024 Linaro Ltd.
- *
- */
-
- /dts-v1/;
-
--#include <dt-bindings/gpio/gpio.h>
--#include <dt-bindings/pinctrl/rockchip.h>
--#include <dt-bindings/usb/pd.h>
--#include "rk3588.dtsi"
-+#include "rk3588-nanopc-t6.dtsi"
-
- / {
- model = "FriendlyElec NanoPC-T6";
- compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
-
-- aliases {
-- mmc0 = &sdhci;
-- mmc1 = &sdmmc;
-- };
--
-- chosen {
-- stdout-path = "serial2:1500000n8";
-- };
--
-- leds {
-- compatible = "gpio-leds";
--
-- sys_led: led-0 {
-- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-- label = "system-led";
-- linux,default-trigger = "heartbeat";
-- pinctrl-names = "default";
-- pinctrl-0 = <&sys_led_pin>;
-- };
--
-- usr_led: led-1 {
-- gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
-- label = "user-led";
-- pinctrl-names = "default";
-- pinctrl-0 = <&usr_led_pin>;
-- };
-- };
--
-- sound {
-- compatible = "simple-audio-card";
-- pinctrl-names = "default";
-- pinctrl-0 = <&hp_det>;
--
-- simple-audio-card,name = "realtek,rt5616-codec";
-- simple-audio-card,format = "i2s";
-- simple-audio-card,mclk-fs = <256>;
--
-- simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
-- simple-audio-card,hp-pin-name = "Headphones";
--
-- simple-audio-card,widgets =
-- "Headphone", "Headphones",
-- "Microphone", "Microphone Jack";
-- simple-audio-card,routing =
-- "Headphones", "HPOL",
-- "Headphones", "HPOR",
-- "MIC1", "Microphone Jack",
-- "Microphone Jack", "micbias1";
--
-- simple-audio-card,cpu {
-- sound-dai = <&i2s0_8ch>;
-- };
-- simple-audio-card,codec {
-- sound-dai = <&rt5616>;
-- };
-- };
--
-- vcc12v_dcin: vcc12v-dcin-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc12v_dcin";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <12000000>;
-- regulator-max-microvolt = <12000000>;
-- };
--
-- /* vcc5v0_sys powers peripherals */
-- vcc5v0_sys: vcc5v0-sys-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc5v0_sys";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vcc12v_dcin>;
-- };
--
-- /* vcc4v0_sys powers the RK806, RK860's */
-- vcc4v0_sys: vcc4v0-sys-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc4v0_sys";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <4000000>;
-- regulator-max-microvolt = <4000000>;
-- vin-supply = <&vcc12v_dcin>;
-- };
--
-- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc-1v1-nldo-s3";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1100000>;
-- regulator-max-microvolt = <1100000>;
-- vin-supply = <&vcc4v0_sys>;
-- };
--
-- vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc_3v3_pcie20";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- vin-supply = <&vcc_3v3_s3>;
-- };
--
-- vbus5v0_typec: vbus5v0-typec-regulator {
-- compatible = "regulator-fixed";
-- enable-active-high;
-- gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&typec5v_pwren>;
-- regulator-name = "vbus5v0_typec";
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vcc5v0_sys>;
-- };
--
-- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
-- compatible = "regulator-fixed";
-- enable-active-high;
-- gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pcie_m2_1_pwren>;
-- regulator-name = "vcc3v3_pcie2x1l0";
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- vin-supply = <&vcc5v0_sys>;
-- };
--
-- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
-- compatible = "regulator-fixed";
-- enable-active-high;
-- gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pcie_m2_0_pwren>;
-- regulator-name = "vcc3v3_pcie30";
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- vin-supply = <&vcc5v0_sys>;
-- };
--
-- vcc3v3_sd_s0: vcc3v3-sd-s0-regulator {
-- compatible = "regulator-fixed";
-- enable-active-low;
-- gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>;
-- regulator-boot-on;
-- regulator-max-microvolt = <3300000>;
-- regulator-min-microvolt = <3300000>;
-- regulator-name = "vcc3v3_sd_s0";
-- vin-supply = <&vcc_3v3_s3>;
-- };
--
-- vdd_4g_3v3: vdd-4g-3v3-regulator {
-- compatible = "regulator-fixed";
-- enable-active-high;
-- gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pin_4g_lte_pwren>;
-- regulator-name = "vdd_4g_3v3";
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- vin-supply = <&vcc5v0_sys>;
-- };
--};
--
--&combphy0_ps {
-- status = "okay";
--};
--
--&combphy1_ps {
-- status = "okay";
--};
--
--&combphy2_psu {
-- status = "okay";
--};
--
--&cpu_l0 {
-- cpu-supply = <&vdd_cpu_lit_s0>;
--};
--
--&cpu_l1 {
-- cpu-supply = <&vdd_cpu_lit_s0>;
--};
--
--&cpu_l2 {
-- cpu-supply = <&vdd_cpu_lit_s0>;
--};
--
--&cpu_l3 {
-- cpu-supply = <&vdd_cpu_lit_s0>;
--};
--
--&cpu_b0{
-- cpu-supply = <&vdd_cpu_big0_s0>;
--};
--
--&cpu_b1{
-- cpu-supply = <&vdd_cpu_big0_s0>;
--};
--
--&cpu_b2{
-- cpu-supply = <&vdd_cpu_big1_s0>;
--};
--
--&cpu_b3{
-- cpu-supply = <&vdd_cpu_big1_s0>;
--};
--
--&gpio0 {
-- gpio-line-names = /* GPIO0 A0-A7 */
-- "", "", "", "",
-- "", "", "", "",
-- /* GPIO0 B0-B7 */
-- "", "", "", "",
-- "", "", "", "",
-- /* GPIO0 C0-C7 */
-- "", "", "", "",
-- "HEADER_10", "HEADER_08", "HEADER_32", "",
-- /* GPIO0 D0-D7 */
-- "", "", "", "",
-- "", "", "", "";
--};
--
--&gpio1 {
-- gpio-line-names = /* GPIO1 A0-A7 */
-- "HEADER_27", "HEADER_28", "", "",
-- "", "", "", "HEADER_15",
-- /* GPIO1 B0-B7 */
-- "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23",
-- "HEADER_24", "HEADER_22", "", "",
-- /* GPIO1 C0-C7 */
-- "", "", "", "",
-- "", "", "", "",
-- /* GPIO1 D0-D7 */
-- "", "", "", "",
-- "", "", "HEADER_05", "HEADER_03";
--};
--
--&gpio2 {
-- gpio-line-names = /* GPIO2 A0-A7 */
-- "", "", "", "",
-- "", "", "", "",
-- /* GPIO2 B0-B7 */
-- "", "", "", "",
-- "", "", "", "",
-- /* GPIO2 C0-C7 */
-- "", "CSI1_11", "CSI1_12", "",
-- "", "", "", "",
-- /* GPIO2 D0-D7 */
-- "", "", "", "",
-- "", "", "", "";
--};
--
--&gpio3 {
-- gpio-line-names = /* GPIO3 A0-A7 */
-- "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36",
-- "HEADER_37", "", "DSI0_12", "",
-- /* GPIO3 B0-B7 */
-- "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16",
-- "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12",
-- /* GPIO3 C0-C7 */
-- "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13",
-- "", "", "", "",
-- /* GPIO3 D0-D7 */
-- "", "", "", "",
-- "", "DSI1_10", "", "";
--};
--
--&gpio4 {
-- gpio-line-names = /* GPIO4 A0-A7 */
-- "DSI1_08", "DSI1_14", "", "DSI1_12",
-- "", "", "", "",
-- /* GPIO4 B0-B7 */
-- "", "", "", "",
-- "", "", "", "",
-- /* GPIO4 C0-C7 */
-- "", "", "", "",
-- "CSI0_11", "CSI0_12", "", "",
-- /* GPIO4 D0-D7 */
-- "", "", "", "",
-- "", "", "", "";
--};
--
--&i2c0 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&i2c0m2_xfer>;
-- status = "okay";
--
-- vdd_cpu_big0_s0: regulator@42 {
-- compatible = "rockchip,rk8602";
-- reg = <0x42>;
-- fcs,suspend-voltage-selector = <1>;
-- regulator-name = "vdd_cpu_big0_s0";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <550000>;
-- regulator-max-microvolt = <1050000>;
-- regulator-ramp-delay = <2300>;
-- vin-supply = <&vcc4v0_sys>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_cpu_big1_s0: regulator@43 {
-- compatible = "rockchip,rk8603", "rockchip,rk8602";
-- reg = <0x43>;
-- fcs,suspend-voltage-selector = <1>;
-- regulator-name = "vdd_cpu_big1_s0";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <550000>;
-- regulator-max-microvolt = <1050000>;
-- regulator-ramp-delay = <2300>;
-- vin-supply = <&vcc4v0_sys>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--};
--
--&i2c2 {
-- status = "okay";
--
-- vdd_npu_s0: regulator@42 {
-- compatible = "rockchip,rk8602";
-- reg = <0x42>;
-- rockchip,suspend-voltage-selector = <1>;
-- regulator-name = "vdd_npu_s0";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <550000>;
-- regulator-max-microvolt = <950000>;
-- regulator-ramp-delay = <2300>;
-- vin-supply = <&vcc4v0_sys>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--};
--
--&i2c6 {
-- clock-frequency = <200000>;
-- status = "okay";
--
-- fusb302: typec-portc@22 {
-- compatible = "fcs,fusb302";
-- reg = <0x22>;
-- interrupt-parent = <&gpio0>;
-- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-- pinctrl-0 = <&usbc0_int>;
-- pinctrl-names = "default";
-- vbus-supply = <&vbus5v0_typec>;
--
-- connector {
-- compatible = "usb-c-connector";
-- data-role = "dual";
-- label = "USB-C";
-- power-role = "dual";
-- try-power-role = "sink";
-- source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
-- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-- op-sink-microwatt = <1000000>;
-- };
-- };
--
-- hym8563: rtc@51 {
-- compatible = "haoyu,hym8563";
-- reg = <0x51>;
-- #clock-cells = <0>;
-- clock-output-names = "hym8563";
-- pinctrl-names = "default";
-- pinctrl-0 = <&hym8563_int>;
-- interrupt-parent = <&gpio0>;
-- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
-- wakeup-source;
-- };
--};
--
--&i2c7 {
-- clock-frequency = <200000>;
-- status = "okay";
--
-- rt5616: codec@1b {
-- compatible = "realtek,rt5616";
-- reg = <0x1b>;
-- clocks = <&cru I2S0_8CH_MCLKOUT>;
-- clock-names = "mclk";
-- #sound-dai-cells = <0>;
-- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
-- assigned-clock-rates = <12288000>;
--
-- port {
-- rt5616_p0_0: endpoint {
-- remote-endpoint = <&i2s0_8ch_p0_0>;
-- };
-- };
-- };
--
-- /* connected with MIPI-CSI1 */
--};
--
--&i2c8 {
-- pinctrl-0 = <&i2c8m2_xfer>;
--};
--
--&i2s0_8ch {
-- pinctrl-names = "default";
-- pinctrl-0 = <&i2s0_lrck
-- &i2s0_mclk
-- &i2s0_sclk
-- &i2s0_sdi0
-- &i2s0_sdo0>;
-- status = "okay";
--
-- i2s0_8ch_p0: port {
-- i2s0_8ch_p0_0: endpoint {
-- dai-format = "i2s";
-- mclk-fs = <256>;
-- remote-endpoint = <&rt5616_p0_0>;
-- };
-- };
--};
--
--&pcie2x1l0 {
-- reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
-- vpcie3v3-supply = <&vcc_3v3_pcie20>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pcie2_0_rst>;
-- status = "okay";
--};
--
--&pcie2x1l1 {
-- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
-- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pcie2_1_rst>;
-- status = "okay";
--};
--
--&pcie2x1l2 {
-- reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
-- vpcie3v3-supply = <&vcc_3v3_pcie20>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pcie2_2_rst>;
-- status = "okay";
--};
--
--&pcie30phy {
-- status = "okay";
--};
--
--&pcie3x4 {
-- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
-- vpcie3v3-supply = <&vcc3v3_pcie30>;
-- status = "okay";
--};
--
--&pinctrl {
-- gpio-leds {
-- sys_led_pin: sys-led-pin {
-- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
-- usr_led_pin: usr-led-pin {
-- rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
-- };
--
-- headphone {
-- hp_det: hp-det {
-- rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
-- };
--
-- hym8563 {
-- hym8563_int: hym8563-int {
-- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
-- };
-- };
--
-- pcie {
-- pcie2_0_rst: pcie2-0-rst {
-- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
-- pcie2_1_rst: pcie2-1-rst {
-- rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
-- pcie2_2_rst: pcie2-2-rst {
-- rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
-- pcie_m2_0_pwren: pcie-m20-pwren {
-- rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
-- pcie_m2_1_pwren: pcie-m21-pwren {
-- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
-- };
--
-- usb {
-- pin_4g_lte_pwren: 4g-lte-pwren {
-- rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
-- typec5v_pwren: typec5v-pwren {
-- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
-- usbc0_int: usbc0-int {
-- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-- };
-- };
--};
--
--&pwm1 {
-- pinctrl-0 = <&pwm1m1_pins>;
-- status = "okay";
--};
--
--&saradc {
-- vref-supply = <&avcc_1v8_s0>;
-- status = "okay";
--};
--
--&sdhci {
-- bus-width = <8>;
-- no-sdio;
-- no-sd;
-- non-removable;
-- max-frequency = <200000000>;
-- mmc-hs400-1_8v;
-- mmc-hs400-enhanced-strobe;
-- status = "okay";
--};
--
--&sdmmc {
-- bus-width = <4>;
-- cap-mmc-highspeed;
-- cap-sd-highspeed;
-- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-- disable-wp;
-- no-mmc;
-- no-sdio;
-- sd-uhs-sdr104;
-- vmmc-supply = <&vcc3v3_sd_s0>;
-- vqmmc-supply = <&vccio_sd_s0>;
-- status = "okay";
--};
--
--&spi2 {
-- status = "okay";
-- assigned-clocks = <&cru CLK_SPI2>;
-- assigned-clock-rates = <200000000>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
-- num-cs = <1>;
--
-- pmic@0 {
-- compatible = "rockchip,rk806";
-- spi-max-frequency = <1000000>;
-- reg = <0x0>;
--
-- interrupt-parent = <&gpio0>;
-- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
--
-- pinctrl-names = "default";
-- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
-- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
--
-- system-power-controller;
--
-- vcc1-supply = <&vcc4v0_sys>;
-- vcc2-supply = <&vcc4v0_sys>;
-- vcc3-supply = <&vcc4v0_sys>;
-- vcc4-supply = <&vcc4v0_sys>;
-- vcc5-supply = <&vcc4v0_sys>;
-- vcc6-supply = <&vcc4v0_sys>;
-- vcc7-supply = <&vcc4v0_sys>;
-- vcc8-supply = <&vcc4v0_sys>;
-- vcc9-supply = <&vcc4v0_sys>;
-- vcc10-supply = <&vcc4v0_sys>;
-- vcc11-supply = <&vcc_2v0_pldo_s3>;
-- vcc12-supply = <&vcc4v0_sys>;
-- vcc13-supply = <&vcc_1v1_nldo_s3>;
-- vcc14-supply = <&vcc_1v1_nldo_s3>;
-- vcca-supply = <&vcc4v0_sys>;
--
-- gpio-controller;
-- #gpio-cells = <2>;
--
-- rk806_dvs1_null: dvs1-null-pins {
-- pins = "gpio_pwrctrl1";
-- function = "pin_fun0";
-- };
--
-- rk806_dvs2_null: dvs2-null-pins {
-- pins = "gpio_pwrctrl2";
-- function = "pin_fun0";
-- };
--
-- rk806_dvs3_null: dvs3-null-pins {
-- pins = "gpio_pwrctrl3";
-- function = "pin_fun0";
-- };
--
-- regulators {
-- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
-- regulator-boot-on;
-- regulator-min-microvolt = <550000>;
-- regulator-max-microvolt = <950000>;
-- regulator-ramp-delay = <12500>;
-- regulator-name = "vdd_gpu_s0";
-- regulator-enable-ramp-delay = <400>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <550000>;
-- regulator-max-microvolt = <950000>;
-- regulator-ramp-delay = <12500>;
-- regulator-name = "vdd_cpu_lit_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_log_s0: dcdc-reg3 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <675000>;
-- regulator-max-microvolt = <750000>;
-- regulator-ramp-delay = <12500>;
-- regulator-name = "vdd_log_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- regulator-suspend-microvolt = <750000>;
-- };
-- };
--
-- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <550000>;
-- regulator-max-microvolt = <950000>;
-- regulator-init-microvolt = <750000>;
-- regulator-ramp-delay = <12500>;
-- regulator-name = "vdd_vdenc_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_ddr_s0: dcdc-reg5 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <675000>;
-- regulator-max-microvolt = <900000>;
-- regulator-ramp-delay = <12500>;
-- regulator-name = "vdd_ddr_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- regulator-suspend-microvolt = <850000>;
-- };
-- };
--
-- vdd2_ddr_s3: dcdc-reg6 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-name = "vdd2_ddr_s3";
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- };
-- };
--
-- vcc_2v0_pldo_s3: dcdc-reg7 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <2000000>;
-- regulator-max-microvolt = <2000000>;
-- regulator-ramp-delay = <12500>;
-- regulator-name = "vdd_2v0_pldo_s3";
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <2000000>;
-- };
-- };
--
-- vcc_3v3_s3: dcdc-reg8 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- regulator-name = "vcc_3v3_s3";
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <3300000>;
-- };
-- };
--
-- vddq_ddr_s0: dcdc-reg9 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-name = "vddq_ddr_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_1v8_s3: dcdc-reg10 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- regulator-name = "vcc_1v8_s3";
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <1800000>;
-- };
-- };
--
-- avcc_1v8_s0: pldo-reg1 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- regulator-name = "avcc_1v8_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_1v8_s0: pldo-reg2 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- regulator-name = "vcc_1v8_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- regulator-suspend-microvolt = <1800000>;
-- };
-- };
--
-- avdd_1v2_s0: pldo-reg3 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1200000>;
-- regulator-max-microvolt = <1200000>;
-- regulator-name = "avdd_1v2_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_3v3_s0: pldo-reg4 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- regulator-ramp-delay = <12500>;
-- regulator-name = "vcc_3v3_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vccio_sd_s0: pldo-reg5 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <3300000>;
-- regulator-ramp-delay = <12500>;
-- regulator-name = "vccio_sd_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- pldo6_s3: pldo-reg6 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- regulator-name = "pldo6_s3";
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <1800000>;
-- };
-- };
--
-- vdd_0v75_s3: nldo-reg1 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <750000>;
-- regulator-max-microvolt = <750000>;
-- regulator-name = "vdd_0v75_s3";
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <750000>;
-- };
-- };
--
-- vdd_ddr_pll_s0: nldo-reg2 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <850000>;
-- regulator-max-microvolt = <850000>;
-- regulator-name = "vdd_ddr_pll_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- regulator-suspend-microvolt = <850000>;
-- };
-- };
--
-- avdd_0v75_s0: nldo-reg3 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <750000>;
-- regulator-max-microvolt = <750000>;
-- regulator-name = "avdd_0v75_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_0v85_s0: nldo-reg4 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <850000>;
-- regulator-max-microvolt = <850000>;
-- regulator-name = "vdd_0v85_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_0v75_s0: nldo-reg5 {
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <750000>;
-- regulator-max-microvolt = <750000>;
-- regulator-name = "vdd_0v75_s0";
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
-- };
-- };
--};
--
--&tsadc {
-- status = "okay";
--};
--
--&uart2 {
-- pinctrl-0 = <&uart2m0_xfer>;
-- status = "okay";
--};
--
--&u2phy2_host {
-- phy-supply = <&vdd_4g_3v3>;
-- status = "okay";
--};
--
--&u2phy3_host {
-- status = "okay";
--};
--
--&u2phy2 {
-- status = "okay";
--};
--
--&u2phy3 {
-- status = "okay";
--};
--
--&usb_host0_ehci {
-- status = "okay";
--};
--
--&usb_host0_ohci {
-- status = "okay";
--};
--
--&usb_host1_ehci {
-- status = "okay";
--};
--
--&usb_host1_ohci {
-- status = "okay";
- };
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -0,0 +1,945 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+ * Copyright (c) 2023 Thomas McKahan
-+ *
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/usb/pd.h>
-+#include "rk3588.dtsi"
-+
-+/ {
-+ model = "FriendlyElec NanoPC-T6";
-+ compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
-+
-+ aliases {
-+ mmc0 = &sdhci;
-+ mmc1 = &sdmmc;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ sys_led: led-0 {
-+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+ label = "system-led";
-+ linux,default-trigger = "heartbeat";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sys_led_pin>;
-+ };
-+
-+ usr_led: led-1 {
-+ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
-+ label = "user-led";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usr_led_pin>;
-+ };
-+ };
-+
-+ sound {
-+ compatible = "simple-audio-card";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hp_det>;
-+
-+ simple-audio-card,name = "realtek,rt5616-codec";
-+ simple-audio-card,format = "i2s";
-+ simple-audio-card,mclk-fs = <256>;
-+
-+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
-+ simple-audio-card,hp-pin-name = "Headphones";
-+
-+ simple-audio-card,widgets =
-+ "Headphone", "Headphones",
-+ "Microphone", "Microphone Jack";
-+ simple-audio-card,routing =
-+ "Headphones", "HPOL",
-+ "Headphones", "HPOR",
-+ "MIC1", "Microphone Jack",
-+ "Microphone Jack", "micbias1";
-+
-+ simple-audio-card,cpu {
-+ sound-dai = <&i2s0_8ch>;
-+ };
-+ simple-audio-card,codec {
-+ sound-dai = <&rt5616>;
-+ };
-+ };
-+
-+ vcc12v_dcin: vcc12v-dcin-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc12v_dcin";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <12000000>;
-+ regulator-max-microvolt = <12000000>;
-+ };
-+
-+ /* vcc5v0_sys powers peripherals */
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc12v_dcin>;
-+ };
-+
-+ /* vcc4v0_sys powers the RK806, RK860's */
-+ vcc4v0_sys: vcc4v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc4v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <4000000>;
-+ regulator-max-microvolt = <4000000>;
-+ vin-supply = <&vcc12v_dcin>;
-+ };
-+
-+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc-1v1-nldo-s3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1100000>;
-+ vin-supply = <&vcc4v0_sys>;
-+ };
-+
-+ vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_3v3_pcie20";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc_3v3_s3>;
-+ };
-+
-+ vbus5v0_typec: vbus5v0-typec-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&typec5v_pwren>;
-+ regulator-name = "vbus5v0_typec";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_m2_1_pwren>;
-+ regulator-name = "vcc3v3_pcie2x1l0";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_m2_0_pwren>;
-+ regulator-name = "vcc3v3_pcie30";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-low;
-+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>;
-+ regulator-boot-on;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-name = "vcc3v3_sd_s0";
-+ vin-supply = <&vcc_3v3_s3>;
-+ };
-+
-+ vdd_4g_3v3: vdd-4g-3v3-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pin_4g_lte_pwren>;
-+ regulator-name = "vdd_4g_3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+};
-+
-+&combphy0_ps {
-+ status = "okay";
-+};
-+
-+&combphy1_ps {
-+ status = "okay";
-+};
-+
-+&combphy2_psu {
-+ status = "okay";
-+};
-+
-+&cpu_l0 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l1 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l2 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l3 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_b0 {
-+ cpu-supply = <&vdd_cpu_big0_s0>;
-+};
-+
-+&cpu_b1 {
-+ cpu-supply = <&vdd_cpu_big0_s0>;
-+};
-+
-+&cpu_b2 {
-+ cpu-supply = <&vdd_cpu_big1_s0>;
-+};
-+
-+&cpu_b3 {
-+ cpu-supply = <&vdd_cpu_big1_s0>;
-+};
-+
-+&gpio0 {
-+ gpio-line-names = /* GPIO0 A0-A7 */
-+ "", "", "", "",
-+ "", "", "", "",
-+ /* GPIO0 B0-B7 */
-+ "", "", "", "",
-+ "", "", "", "",
-+ /* GPIO0 C0-C7 */
-+ "", "", "", "",
-+ "HEADER_10", "HEADER_08", "HEADER_32", "",
-+ /* GPIO0 D0-D7 */
-+ "", "", "", "",
-+ "", "", "", "";
-+};
-+
-+&gpio1 {
-+ gpio-line-names = /* GPIO1 A0-A7 */
-+ "HEADER_27", "HEADER_28", "", "",
-+ "", "", "", "HEADER_15",
-+ /* GPIO1 B0-B7 */
-+ "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23",
-+ "HEADER_24", "HEADER_22", "", "",
-+ /* GPIO1 C0-C7 */
-+ "", "", "", "",
-+ "", "", "", "",
-+ /* GPIO1 D0-D7 */
-+ "", "", "", "",
-+ "", "", "HEADER_05", "HEADER_03";
-+};
-+
-+&gpio2 {
-+ gpio-line-names = /* GPIO2 A0-A7 */
-+ "", "", "", "",
-+ "", "", "", "",
-+ /* GPIO2 B0-B7 */
-+ "", "", "", "",
-+ "", "", "", "",
-+ /* GPIO2 C0-C7 */
-+ "", "CSI1_11", "CSI1_12", "",
-+ "", "", "", "",
-+ /* GPIO2 D0-D7 */
-+ "", "", "", "",
-+ "", "", "", "";
-+};
-+
-+&gpio3 {
-+ gpio-line-names = /* GPIO3 A0-A7 */
-+ "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36",
-+ "HEADER_37", "", "DSI0_12", "",
-+ /* GPIO3 B0-B7 */
-+ "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16",
-+ "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12",
-+ /* GPIO3 C0-C7 */
-+ "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13",
-+ "", "", "", "",
-+ /* GPIO3 D0-D7 */
-+ "", "", "", "",
-+ "", "DSI1_10", "", "";
-+};
-+
-+&gpio4 {
-+ gpio-line-names = /* GPIO4 A0-A7 */
-+ "DSI1_08", "DSI1_14", "", "DSI1_12",
-+ "", "", "", "",
-+ /* GPIO4 B0-B7 */
-+ "", "", "", "",
-+ "", "", "", "",
-+ /* GPIO4 C0-C7 */
-+ "", "", "", "",
-+ "CSI0_11", "CSI0_12", "", "",
-+ /* GPIO4 D0-D7 */
-+ "", "", "", "",
-+ "", "", "", "";
-+};
-+
-+&i2c0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0m2_xfer>;
-+ status = "okay";
-+
-+ vdd_cpu_big0_s0: regulator@42 {
-+ compatible = "rockchip,rk8602";
-+ reg = <0x42>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu_big0_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <1050000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc4v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_cpu_big1_s0: regulator@43 {
-+ compatible = "rockchip,rk8603", "rockchip,rk8602";
-+ reg = <0x43>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu_big1_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <1050000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc4v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+};
-+
-+&i2c2 {
-+ status = "okay";
-+
-+ vdd_npu_s0: regulator@42 {
-+ compatible = "rockchip,rk8602";
-+ reg = <0x42>;
-+ rockchip,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_npu_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc4v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+};
-+
-+&i2c6 {
-+ clock-frequency = <200000>;
-+ status = "okay";
-+
-+ fusb302: typec-portc@22 {
-+ compatible = "fcs,fusb302";
-+ reg = <0x22>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-0 = <&usbc0_int>;
-+ pinctrl-names = "default";
-+ vbus-supply = <&vbus5v0_typec>;
-+
-+ connector {
-+ compatible = "usb-c-connector";
-+ data-role = "dual";
-+ label = "USB-C";
-+ power-role = "dual";
-+ try-power-role = "sink";
-+ source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
-+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-+ op-sink-microwatt = <1000000>;
-+ };
-+ };
-+
-+ hym8563: rtc@51 {
-+ compatible = "haoyu,hym8563";
-+ reg = <0x51>;
-+ #clock-cells = <0>;
-+ clock-output-names = "hym8563";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hym8563_int>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
-+ wakeup-source;
-+ };
-+};
-+
-+&i2c7 {
-+ clock-frequency = <200000>;
-+ status = "okay";
-+
-+ rt5616: codec@1b {
-+ compatible = "realtek,rt5616";
-+ reg = <0x1b>;
-+ clocks = <&cru I2S0_8CH_MCLKOUT>;
-+ clock-names = "mclk";
-+ #sound-dai-cells = <0>;
-+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
-+ assigned-clock-rates = <12288000>;
-+
-+ port {
-+ rt5616_p0_0: endpoint {
-+ remote-endpoint = <&i2s0_8ch_p0_0>;
-+ };
-+ };
-+ };
-+
-+ /* connected with MIPI-CSI1 */
-+};
-+
-+&i2c8 {
-+ pinctrl-0 = <&i2c8m2_xfer>;
-+};
-+
-+&i2s0_8ch {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s0_lrck
-+ &i2s0_mclk
-+ &i2s0_sclk
-+ &i2s0_sdi0
-+ &i2s0_sdo0>;
-+ status = "okay";
-+
-+ i2s0_8ch_p0: port {
-+ i2s0_8ch_p0_0: endpoint {
-+ dai-format = "i2s";
-+ mclk-fs = <256>;
-+ remote-endpoint = <&rt5616_p0_0>;
-+ };
-+ };
-+};
-+
-+&pcie2x1l0 {
-+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie2_0_rst>;
-+ status = "okay";
-+};
-+
-+&pcie2x1l1 {
-+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie2_1_rst>;
-+ status = "okay";
-+};
-+
-+&pcie2x1l2 {
-+ reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc_3v3_pcie20>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie2_2_rst>;
-+ status = "okay";
-+};
-+
-+&pcie30phy {
-+ status = "okay";
-+};
-+
-+&pcie3x4 {
-+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie30>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ gpio-leds {
-+ sys_led_pin: sys-led-pin {
-+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ usr_led_pin: usr-led-pin {
-+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ headphone {
-+ hp_det: hp-det {
-+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ hym8563 {
-+ hym8563_int: hym8563-int {
-+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ pcie {
-+ pcie2_0_rst: pcie2-0-rst {
-+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie2_1_rst: pcie2-1-rst {
-+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie2_2_rst: pcie2-2-rst {
-+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie_m2_0_pwren: pcie-m20-pwren {
-+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie_m2_1_pwren: pcie-m21-pwren {
-+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb {
-+ pin_4g_lte_pwren: 4g-lte-pwren {
-+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ typec5v_pwren: typec5v-pwren {
-+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ usbc0_int: usbc0-int {
-+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+};
-+
-+&pwm1 {
-+ pinctrl-0 = <&pwm1m1_pins>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&avcc_1v8_s0>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ no-sdio;
-+ no-sd;
-+ non-removable;
-+ max-frequency = <200000000>;
-+ mmc-hs400-1_8v;
-+ mmc-hs400-enhanced-strobe;
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-+ disable-wp;
-+ no-mmc;
-+ no-sdio;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc3v3_sd_s0>;
-+ vqmmc-supply = <&vccio_sd_s0>;
-+ status = "okay";
-+};
-+
-+&spi2 {
-+ status = "okay";
-+ assigned-clocks = <&cru CLK_SPI2>;
-+ assigned-clock-rates = <200000000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
-+ num-cs = <1>;
-+
-+ pmic@0 {
-+ compatible = "rockchip,rk806";
-+ spi-max-frequency = <1000000>;
-+ reg = <0x0>;
-+
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-+
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
-+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-+
-+ system-power-controller;
-+
-+ vcc1-supply = <&vcc4v0_sys>;
-+ vcc2-supply = <&vcc4v0_sys>;
-+ vcc3-supply = <&vcc4v0_sys>;
-+ vcc4-supply = <&vcc4v0_sys>;
-+ vcc5-supply = <&vcc4v0_sys>;
-+ vcc6-supply = <&vcc4v0_sys>;
-+ vcc7-supply = <&vcc4v0_sys>;
-+ vcc8-supply = <&vcc4v0_sys>;
-+ vcc9-supply = <&vcc4v0_sys>;
-+ vcc10-supply = <&vcc4v0_sys>;
-+ vcc11-supply = <&vcc_2v0_pldo_s3>;
-+ vcc12-supply = <&vcc4v0_sys>;
-+ vcc13-supply = <&vcc_1v1_nldo_s3>;
-+ vcc14-supply = <&vcc_1v1_nldo_s3>;
-+ vcca-supply = <&vcc4v0_sys>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ rk806_dvs1_null: dvs1-null-pins {
-+ pins = "gpio_pwrctrl1";
-+ function = "pin_fun0";
-+ };
-+
-+ rk806_dvs2_null: dvs2-null-pins {
-+ pins = "gpio_pwrctrl2";
-+ function = "pin_fun0";
-+ };
-+
-+ rk806_dvs3_null: dvs3-null-pins {
-+ pins = "gpio_pwrctrl3";
-+ function = "pin_fun0";
-+ };
-+
-+ regulators {
-+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_gpu_s0";
-+ regulator-enable-ramp-delay = <400>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_cpu_lit_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_log_s0: dcdc-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <675000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_log_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <750000>;
-+ };
-+ };
-+
-+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-init-microvolt = <750000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_vdenc_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_ddr_s0: dcdc-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <675000>;
-+ regulator-max-microvolt = <900000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_ddr_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <850000>;
-+ };
-+ };
-+
-+ vdd2_ddr_s3: dcdc-reg6 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-name = "vdd2_ddr_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc_2v0_pldo_s3: dcdc-reg7 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <2000000>;
-+ regulator-max-microvolt = <2000000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_2v0_pldo_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <2000000>;
-+ };
-+ };
-+
-+ vcc_3v3_s3: dcdc-reg8 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vcc_3v3_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vddq_ddr_s0: dcdc-reg9 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-name = "vddq_ddr_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8_s3: dcdc-reg10 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcc_1v8_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ avcc_1v8_s0: pldo-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "avcc_1v8_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8_s0: pldo-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcc_1v8_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ avdd_1v2_s0: pldo-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1200000>;
-+ regulator-max-microvolt = <1200000>;
-+ regulator-name = "avdd_1v2_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3_s0: pldo-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vcc_3v3_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd_s0: pldo-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vccio_sd_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ pldo6_s3: pldo-reg6 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "pldo6_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdd_0v75_s3: nldo-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "vdd_0v75_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <750000>;
-+ };
-+ };
-+
-+ vdd_ddr_pll_s0: nldo-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <850000>;
-+ regulator-max-microvolt = <850000>;
-+ regulator-name = "vdd_ddr_pll_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <850000>;
-+ };
-+ };
-+
-+ avdd_0v75_s0: nldo-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "avdd_0v75_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_0v85_s0: nldo-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <850000>;
-+ regulator-max-microvolt = <850000>;
-+ regulator-name = "vdd_0v85_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_0v75_s0: nldo-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "vdd_0v75_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&tsadc {
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ pinctrl-0 = <&uart2m0_xfer>;
-+ status = "okay";
-+};
-+
-+&u2phy2_host {
-+ phy-supply = <&vdd_4g_3v3>;
-+ status = "okay";
-+};
-+
-+&u2phy3_host {
-+ status = "okay";
-+};
-+
-+&u2phy2 {
-+ status = "okay";
-+};
-+
-+&u2phy3 {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
+++ /dev/null
-From aea8d84070fe0846961deb23228d9dd3f8caefb3 Mon Sep 17 00:00:00 2001
-From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Date: Thu, 29 Aug 2024 14:26:54 +0200
-Subject: [PATCH] arm64: dts: rockchip: move NanoPC-T6 parts to DTS
-
-MiniPCIe slot is present only in first version of NanoPC-T6 (2301).
-
-Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-3-edff247e8c02@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-nanopc-t6.dts | 23 +++++++++++++++++++
- .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 17 --------------
- 2 files changed, 23 insertions(+), 17 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts
-@@ -14,4 +14,27 @@
- model = "FriendlyElec NanoPC-T6";
- compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
-
-+ vdd_4g_3v3: vdd-4g-3v3-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pin_4g_lte_pwren>;
-+ regulator-name = "vdd_4g_3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+};
-+
-+&pinctrl {
-+ usb {
-+ pin_4g_lte_pwren: 4g-lte-pwren {
-+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&u2phy2_host {
-+ phy-supply = <&vdd_4g_3v3>;
- };
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -170,18 +170,6 @@
- regulator-name = "vcc3v3_sd_s0";
- vin-supply = <&vcc_3v3_s3>;
- };
--
-- vdd_4g_3v3: vdd-4g-3v3-regulator {
-- compatible = "regulator-fixed";
-- enable-active-high;
-- gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pin_4g_lte_pwren>;
-- regulator-name = "vdd_4g_3v3";
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- vin-supply = <&vcc5v0_sys>;
-- };
- };
-
- &combphy0_ps {
-@@ -527,10 +515,6 @@
- };
-
- usb {
-- pin_4g_lte_pwren: 4g-lte-pwren {
-- rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
- typec5v_pwren: typec5v-pwren {
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-@@ -912,7 +896,6 @@
- };
-
- &u2phy2_host {
-- phy-supply = <&vdd_4g_3v3>;
- status = "okay";
- };
-
+++ /dev/null
-From a22a629c63b1addcf2d81eaf30383c1deca5b7a9 Mon Sep 17 00:00:00 2001
-From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Date: Thu, 29 Aug 2024 14:26:56 +0200
-Subject: [PATCH] arm64: dts: rockchip: add SPI flash on NanoPC-T6
-
-FriendlyELEC NanoPC-T6 has optional SPI flash chip on-board.
-It is populated with 32MB one on LTS version.
-
-Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-5-edff247e8c02@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -560,6 +560,21 @@
- status = "okay";
- };
-
-+/* optional on non-LTS, populated on LTS version */
-+&sfc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&fspim1_pins>;
-+ status = "okay";
-+
-+ flash@0 {
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <104000000>;
-+ spi-rx-bus-width = <4>;
-+ spi-tx-bus-width = <1>;
-+ };
-+};
-+
- &spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
+++ /dev/null
-From b70caff0f9592719b6c977e291c33192e959c9d4 Mon Sep 17 00:00:00 2001
-From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Date: Thu, 29 Aug 2024 14:26:57 +0200
-Subject: [PATCH] arm64: dts: rockchip: add IR-receiver to NanoPC-T6
-
-FriendlyELEC NanoPC-T6 has IR receiver connected to PWM3_IR_M0 line
-which ends as GPIO0_D4.
-
-Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-6-edff247e8c02@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 ++++++++++++++-
- 1 file changed, 14 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -25,6 +25,13 @@
- stdout-path = "serial2:1500000n8";
- };
-
-+ ir-receiver {
-+ compatible = "gpio-ir-receiver";
-+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&ir_receiver_pin>;
-+ };
-+
- leds {
- compatible = "gpio-leds";
-
-@@ -228,7 +235,7 @@
- "HEADER_10", "HEADER_08", "HEADER_32", "",
- /* GPIO0 D0-D7 */
- "", "", "", "",
-- "", "", "", "";
-+ "IR receiver [PWM3_IR_M0]", "", "", "";
- };
-
- &gpio1 {
-@@ -492,6 +499,12 @@
- };
- };
-
-+ ir-receiver {
-+ ir_receiver_pin: ir-receiver-pin {
-+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
- pcie {
- pcie2_0_rst: pcie2-0-rst {
- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+++ /dev/null
-From e86cbf999cda2d44f32ec622537024e3b923080d Mon Sep 17 00:00:00 2001
-From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Date: Thu, 29 Aug 2024 14:26:58 +0200
-Subject: [PATCH] arm64: dts: rockchip: enable GPU on NanoPC-T6
-
-Enable the Mali GPU on FriendlyELEC NanoPC-T6
-
-Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-7-edff247e8c02@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -298,6 +298,11 @@
- "", "", "", "";
- };
-
-+&gpu {
-+ mali-supply = <&vdd_gpu_s0>;
-+ status = "okay";
-+};
-+
- &i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
+++ /dev/null
-From c9ba75320e5a12dc9d574603acf29b38a920b40c Mon Sep 17 00:00:00 2001
-From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Date: Thu, 29 Aug 2024 14:26:59 +0200
-Subject: [PATCH] arm64: dts: rockchip: enable USB-C on NanoPC-T6
-
-Enable the USB-C port on FriendlyELEC NanoPC-T6.
-
-Works one way so far but still better than before.
-
-Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-8-edff247e8c02@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 76 ++++++++++++++++++-
- 1 file changed, 72 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -137,6 +137,8 @@
- gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&typec5v_pwren>;
-+ regulator-always-on;
-+ regulator-boot-on;
- regulator-name = "vbus5v0_typec";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-@@ -381,11 +383,34 @@
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
-- power-role = "dual";
-- try-power-role = "sink";
-+ power-role = "source";
- source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
-- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
-- op-sink-microwatt = <1000000>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 {
-+ reg = <0>;
-+ usbc0_hs: endpoint {
-+ remote-endpoint = <&usb_host0_xhci_drd_sw>;
-+ };
-+ };
-+
-+ port@1 {
-+ reg = <1>;
-+ usbc0_ss: endpoint {
-+ remote-endpoint = <&usbdp_phy0_typec_ss>;
-+ };
-+ };
-+
-+ port@2 {
-+ reg = <2>;
-+ usbc0_sbu: endpoint {
-+ remote-endpoint = <&usbdp_phy0_typec_sbu>;
-+ };
-+ };
-+ };
- };
- };
-
-@@ -928,6 +953,14 @@
- status = "okay";
- };
-
-+&u2phy0 {
-+ status = "okay";
-+};
-+
-+&u2phy0_otg {
-+ status = "okay";
-+};
-+
- &u2phy2_host {
- status = "okay";
- };
-@@ -944,6 +977,29 @@
- status = "okay";
- };
-
-+&usbdp_phy0 {
-+ mode-switch;
-+ orientation-switch;
-+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+
-+ port {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ usbdp_phy0_typec_ss: endpoint@0 {
-+ reg = <0>;
-+ remote-endpoint = <&usbc0_ss>;
-+ };
-+
-+ usbdp_phy0_typec_sbu: endpoint@1 {
-+ reg = <1>;
-+ remote-endpoint = <&usbc0_sbu>;
-+ };
-+ };
-+};
-+
- &usb_host0_ehci {
- status = "okay";
- };
-@@ -952,6 +1008,18 @@
- status = "okay";
- };
-
-+&usb_host0_xhci {
-+ dr_mode = "host";
-+ status = "okay";
-+ usb-role-switch;
-+
-+ port {
-+ usb_host0_xhci_drd_sw: endpoint {
-+ remote-endpoint = <&usbc0_hs>;
-+ };
-+ };
-+};
-+
- &usb_host1_ehci {
- status = "okay";
- };
+++ /dev/null
-From da439eed06ff6806f22341ab0468226afc555305 Mon Sep 17 00:00:00 2001
-From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Date: Thu, 29 Aug 2024 14:27:00 +0200
-Subject: [PATCH] arm64: dts: rockchip: add Mask Rom key on NanoPC-T6
-
-Mask Rom key is connected to SARADC and can be read from OS.
-
-Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-9-edff247e8c02@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -8,6 +8,7 @@
- /dts-v1/;
-
- #include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
- #include <dt-bindings/pinctrl/rockchip.h>
- #include <dt-bindings/usb/pd.h>
- #include "rk3588.dtsi"
-@@ -21,6 +22,20 @@
- mmc1 = &sdmmc;
- };
-
-+ adc-keys-0 {
-+ compatible = "adc-keys";
-+ io-channels = <&saradc 0>;
-+ io-channel-names = "buttons";
-+ keyup-threshold-microvolt = <1800000>;
-+ poll-interval = <100>;
-+
-+ button-maskrom {
-+ label = "Mask Rom";
-+ linux,code = <KEY_SETUP>;
-+ press-threshold-microvolt = <2000>;
-+ };
-+ };
-+
- chosen {
- stdout-path = "serial2:1500000n8";
- };
+++ /dev/null
-From 170c77276d470a63d22a2634a38846dd88538637 Mon Sep 17 00:00:00 2001
-From: Heiko Stuebner <heiko@sntech.de>
-Date: Thu, 29 Aug 2024 15:20:58 +0200
-Subject: [PATCH] arm64: dts: rockchip: use correct
- fcs,suspend-voltage-selector on NanoPC-T6
-
-A remant from moving from the vendor kernel, the regulator is using
-a fairchild fcs prefix instead of rockchip,* in the mainline kernel
-according to its binding.
-
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-Link: https://lore.kernel.org/r/20240829132100.1723127-2-heiko@sntech.de
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -366,7 +366,7 @@
- vdd_npu_s0: regulator@42 {
- compatible = "rockchip,rk8602";
- reg = <0x42>;
-- rockchip,suspend-voltage-selector = <1>;
-+ fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_npu_s0";
- regulator-always-on;
- regulator-boot-on;
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -160,6 +160,20 @@
+@@ -159,6 +159,20 @@
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
compatible = "regulator-fixed";
enable-active-high;
-@@ -577,6 +591,10 @@
+@@ -575,6 +589,10 @@
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
usbc0_int: usbc0-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
-@@ -976,6 +994,14 @@
+@@ -973,6 +991,14 @@
status = "okay";
};
&u2phy2_host {
status = "okay";
};
-@@ -1015,6 +1041,11 @@
+@@ -1012,6 +1038,11 @@
};
};
&usb_host0_ehci {
status = "okay";
};
-@@ -1035,6 +1066,11 @@
+@@ -1032,6 +1063,11 @@
};
};
+++ /dev/null
-From 81c828a67c78bb03ea75819c417c93c7f3d637b5 Mon Sep 17 00:00:00 2001
-From: Jianfeng Liu <liujianfeng1994@gmail.com>
-Date: Sat, 20 Apr 2024 11:43:00 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add ArmSom Sige7 board
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Specification:
- Rockchip Rk3588 SoC
- 4x ARM Cortex-A76, 4x ARM Cortex-A55
- 8/16/32GB Memory LPDDR4/LPDDR4x
- Mali G610MP4 GPU
- 2× MIPI-CSI Connector
- 1× MIPI-DSI Connector
- 1x M.2 Key M (PCIe 3.0 4-lanes)
- 2x RTL8125 2.5G Ethernet
- Onboard AP6275P for WIFI6/BT5
- 32GB/64GB/128GB eMMC
- MicroSD card slot
- 1x USB2.0, 1x USB3.0 Type-A, 1x US3.0 Type-C
- 1x HDMI Output, 1x type-C DP Output
-
-Functions work normally:
- USB2.0 Host
- USB3.0 Type-A Host
- M.2 Key M (PCIe 3.0 4-lanes)
- 2x RTL8125 2.5G Ethernet
- eMMC
- MicroSD card
-
-More information can be obtained from the following website
- https://docs.armsom.org/armsom-sige7
-
-Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
-Reviewed-by: Weizhao Ouyang <weizhao.ouyang@arm.com>
-Link: https://lore.kernel.org/r/20240420034300.176920-4-liujianfeng1994@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3588-armsom-sige7.dts | 721 ++++++++++++++++++
- 2 files changed, 722 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ra
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-@@ -0,0 +1,721 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include "rk3588.dtsi"
-+
-+/ {
-+ model = "ArmSoM Sige7";
-+ compatible = "armsom,sige7", "rockchip,rk3588";
-+
-+ aliases {
-+ mmc0 = &sdhci;
-+ mmc1 = &sdmmc;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ analog-sound {
-+ compatible = "audio-graph-card";
-+ dais = <&i2s0_8ch_p0>;
-+ label = "rk3588-es8316";
-+ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hp_detect>;
-+ routing = "MIC2", "Mic Jack",
-+ "Headphones", "HPOL",
-+ "Headphones", "HPOR";
-+ widgets = "Microphone", "Mic Jack",
-+ "Headphone", "Headphones";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led_rgb_g>;
-+
-+ led_green: led-0 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_STATUS;
-+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
-+
-+ led_red: led-1 {
-+ color = <LED_COLOR_ID_RED>;
-+ function = LED_FUNCTION_STATUS;
-+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "none";
-+ };
-+ };
-+
-+ fan: pwm-fan {
-+ compatible = "pwm-fan";
-+ cooling-levels = <0 95 145 195 255>;
-+ fan-supply = <&vcc5v0_sys>;
-+ pwms = <&pwm1 0 50000 0>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_pcie2x1l2";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <5000>;
-+ vin-supply = <&vcc_3v3_s3>;
-+ };
-+
-+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
-+ regulator-name = "vcc3v3_pcie30";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <5000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_host: vcc5v0-host-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_host";
-+ regulator-boot-on;
-+ regulator-always-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_host_en>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_1v1_nldo_s3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1100000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+};
-+
-+&combphy0_ps {
-+ status = "okay";
-+};
-+
-+&combphy1_ps {
-+ status = "okay";
-+};
-+
-+&combphy2_psu {
-+ status = "okay";
-+};
-+
-+&cpu_b0 {
-+ cpu-supply = <&vdd_cpu_big0_s0>;
-+};
-+
-+&cpu_b1 {
-+ cpu-supply = <&vdd_cpu_big0_s0>;
-+};
-+
-+&cpu_b2 {
-+ cpu-supply = <&vdd_cpu_big1_s0>;
-+};
-+
-+&cpu_b3 {
-+ cpu-supply = <&vdd_cpu_big1_s0>;
-+};
-+
-+&cpu_l0 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l1 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l2 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&cpu_l3 {
-+ cpu-supply = <&vdd_cpu_lit_s0>;
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu_s0>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0m2_xfer>;
-+ status = "okay";
-+
-+ vdd_cpu_big0_s0: regulator@42 {
-+ compatible = "rockchip,rk8602";
-+ reg = <0x42>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu_big0_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <1050000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_cpu_big1_s0: regulator@43 {
-+ compatible = "rockchip,rk8603", "rockchip,rk8602";
-+ reg = <0x43>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu_big1_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <1050000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+};
-+
-+&i2c6 {
-+ status = "okay";
-+
-+ hym8563: rtc@51 {
-+ compatible = "haoyu,hym8563";
-+ reg = <0x51>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <0>;
-+ clock-output-names = "hym8563";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hym8563_int>;
-+ wakeup-source;
-+ };
-+};
-+
-+&i2c7 {
-+ status = "okay";
-+
-+ es8316: audio-codec@11 {
-+ compatible = "everest,es8316";
-+ reg = <0x11>;
-+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
-+ assigned-clock-rates = <12288000>;
-+ clocks = <&cru I2S0_8CH_MCLKOUT>;
-+ clock-names = "mclk";
-+ #sound-dai-cells = <0>;
-+
-+ port {
-+ es8316_p0_0: endpoint {
-+ remote-endpoint = <&i2s0_8ch_p0_0>;
-+ };
-+ };
-+ };
-+};
-+
-+&i2s0_8ch {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s0_lrck
-+ &i2s0_mclk
-+ &i2s0_sclk
-+ &i2s0_sdi0
-+ &i2s0_sdo0>;
-+ status = "okay";
-+
-+ i2s0_8ch_p0: port {
-+ i2s0_8ch_p0_0: endpoint {
-+ dai-format = "i2s";
-+ mclk-fs = <256>;
-+ remote-endpoint = <&es8316_p0_0>;
-+ };
-+ };
-+};
-+
-+/* phy1 - right ethernet port */
-+&pcie2x1l0 {
-+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+/* phy2 - WiFi */
-+&pcie2x1l1 {
-+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+/* phy0 - left ethernet port */
-+&pcie2x1l2 {
-+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+&pcie30phy {
-+ status = "okay";
-+};
-+
-+&pcie3x4 {
-+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie30>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ hym8563 {
-+ hym8563_int: hym8563-int {
-+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ leds {
-+ led_rgb_g: led-rgb-g {
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ led_rgb_r: led-rgb-r {
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sound {
-+ hp_detect: hp-detect {
-+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb {
-+ vcc5v0_host_en: vcc5v0-host-en {
-+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pwm1 {
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&avcc_1v8_s0>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ no-sdio;
-+ no-sd;
-+ non-removable;
-+ mmc-hs200-1_8v;
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ max-frequency = <200000000>;
-+ no-sdio;
-+ no-mmc;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc_3v3_s3>;
-+ vqmmc-supply = <&vccio_sd_s0>;
-+ status = "okay";
-+};
-+
-+&spi2 {
-+ assigned-clocks = <&cru CLK_SPI2>;
-+ assigned-clock-rates = <200000000>;
-+ num-cs = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
-+ status = "okay";
-+
-+ pmic@0 {
-+ compatible = "rockchip,rk806";
-+ spi-max-frequency = <1000000>;
-+ reg = <0x0>;
-+
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
-+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-+
-+ system-power-controller;
-+
-+ vcc1-supply = <&vcc5v0_sys>;
-+ vcc2-supply = <&vcc5v0_sys>;
-+ vcc3-supply = <&vcc5v0_sys>;
-+ vcc4-supply = <&vcc5v0_sys>;
-+ vcc5-supply = <&vcc5v0_sys>;
-+ vcc6-supply = <&vcc5v0_sys>;
-+ vcc7-supply = <&vcc5v0_sys>;
-+ vcc8-supply = <&vcc5v0_sys>;
-+ vcc9-supply = <&vcc5v0_sys>;
-+ vcc10-supply = <&vcc5v0_sys>;
-+ vcc11-supply = <&vcc_2v0_pldo_s3>;
-+ vcc12-supply = <&vcc5v0_sys>;
-+ vcc13-supply = <&vcc_1v1_nldo_s3>;
-+ vcc14-supply = <&vcc_1v1_nldo_s3>;
-+ vcca-supply = <&vcc5v0_sys>;
-+
-+ rk806_dvs1_null: dvs1-null-pins {
-+ pins = "gpio_pwrctrl1";
-+ function = "pin_fun0";
-+ };
-+
-+ rk806_dvs2_null: dvs2-null-pins {
-+ pins = "gpio_pwrctrl2";
-+ function = "pin_fun0";
-+ };
-+
-+ rk806_dvs3_null: dvs3-null-pins {
-+ pins = "gpio_pwrctrl3";
-+ function = "pin_fun0";
-+ };
-+
-+ regulators {
-+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_gpu_s0";
-+ regulator-enable-ramp-delay = <400>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_cpu_lit_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_log_s0: dcdc-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <675000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_log_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <750000>;
-+ };
-+ };
-+
-+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <550000>;
-+ regulator-max-microvolt = <950000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_vdenc_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_ddr_s0: dcdc-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <675000>;
-+ regulator-max-microvolt = <900000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_ddr_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <850000>;
-+ };
-+ };
-+
-+ vdd2_ddr_s3: dcdc-reg6 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-name = "vdd2_ddr_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc_2v0_pldo_s3: dcdc-reg7 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <2000000>;
-+ regulator-max-microvolt = <2000000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vdd_2v0_pldo_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <2000000>;
-+ };
-+ };
-+
-+ vcc_3v3_s3: dcdc-reg8 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vcc_3v3_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vddq_ddr_s0: dcdc-reg9 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-name = "vddq_ddr_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8_s3: dcdc-reg10 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcc_1v8_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ avcc_1v8_s0: pldo-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "avcc_1v8_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8_s0: pldo-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcc_1v8_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ avdd_1v2_s0: pldo-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1200000>;
-+ regulator-max-microvolt = <1200000>;
-+ regulator-name = "avdd_1v2_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3_s0: pldo-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vcc_3v3_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd_s0: pldo-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-ramp-delay = <12500>;
-+ regulator-name = "vccio_sd_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ pldo6_s3: pldo-reg6 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "pldo6_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdd_0v75_s3: nldo-reg1 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "vdd_0v75_s3";
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <750000>;
-+ };
-+ };
-+
-+ vdd_ddr_pll_s0: nldo-reg2 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <850000>;
-+ regulator-max-microvolt = <850000>;
-+ regulator-name = "vdd_ddr_pll_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ regulator-suspend-microvolt = <850000>;
-+ };
-+ };
-+
-+ avdd_0v75_s0: nldo-reg3 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "avdd_0v75_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_0v85_s0: nldo-reg4 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <850000>;
-+ regulator-max-microvolt = <850000>;
-+ regulator-name = "vdd_0v85_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_0v75_s0: nldo-reg5 {
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <750000>;
-+ regulator-name = "vdd_0v75_s0";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&u2phy0 {
-+ status = "okay";
-+};
-+
-+&u2phy0_otg {
-+ status = "okay";
-+};
-+
-+&u2phy1 {
-+ status = "okay";
-+};
-+
-+&u2phy1_otg {
-+ status = "okay";
-+};
-+
-+&u2phy3 {
-+ status = "okay";
-+};
-+
-+&u2phy3_host {
-+ phy-supply = <&vcc5v0_host>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ pinctrl-0 = <&uart2m0_xfer>;
-+ status = "okay";
-+};
-+
-+&usbdp_phy1 {
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ dr_mode = "host";
-+ status = "okay";
-+};
+++ /dev/null
-From 2f8064b9c4a012b4d4e8383818f13b682b6c156a Mon Sep 17 00:00:00 2001
-From: Alexey Charkov <alchark@gmail.com>
-Date: Mon, 17 Jun 2024 22:28:52 +0400
-Subject: [PATCH] arm64: dts: rockchip: enable thermal management on all RK3588
- boards
-
-This enables the on-chip thermal monitoring sensor (TSADC) on all
-RK3588(s) boards that don't have it enabled yet. It provides temperature
-monitoring for the SoC and emergency thermal shutdowns, and is thus
-important to have in place before CPU DVFS is enabled, as high CPU
-operating performance points can overheat the chip quickly in the
-absence of thermal management.
-
-Signed-off-by: Alexey Charkov <alchark@gmail.com>
-Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-2-c1f5f3267f1e@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 4 ++++
- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 4 ++++
- 8 files changed, 32 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
-@@ -673,6 +673,10 @@
- };
- };
-
-+&tsadc {
-+ status = "okay";
-+};
-+
- &u2phy0 {
- status = "okay";
- };
---- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
-@@ -807,6 +807,10 @@
- status = "okay";
- };
-
-+&tsadc {
-+ status = "okay";
-+};
-+
- &u2phy2 {
- status = "okay";
- };
---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -787,6 +787,10 @@
- };
- };
-
-+&tsadc {
-+ status = "okay";
-+};
-+
- &uart2 {
- pinctrl-0 = <&uart2m0_xfer>;
- status = "okay";
---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -741,6 +741,10 @@
- };
- };
-
-+&tsadc {
-+ status = "okay";
-+};
-+
- &u2phy0 {
- status = "okay";
- };
#include <dt-bindings/gpio/gpio.h>
#include "rk3328.dtsi"
-@@ -16,6 +17,11 @@
- aliases {
+@@ -17,6 +18,11 @@
+ ethernet0 = &gmac2io;
ethernet1 = &rtl8153;
mmc0 = &sdmmc;
+
};
chosen {
-@@ -48,19 +54,22 @@
+@@ -49,19 +55,22 @@
pinctrl-names = "default";
lan_led: led-0 {
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-@@ -13,6 +13,11 @@
- aliases {
+@@ -14,6 +14,11 @@
+ ethernet0 = &gmac2io;
mmc0 = &sdmmc;
mmc1 = &emmc;
+
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -406,6 +406,7 @@
+@@ -407,6 +407,7 @@
rtl8153: device@2 {
compatible = "usbbda,8153";
reg = <2>;
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-@@ -335,7 +335,6 @@
+@@ -336,7 +336,6 @@
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -17,6 +17,11 @@
- aliases {
+@@ -18,6 +18,11 @@
+ ethernet0 = &gmac2io;
ethernet1 = &rtl8153;
mmc0 = &sdmmc;
+
};
chosen {
-@@ -41,11 +46,10 @@
+@@ -42,11 +47,10 @@
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
};
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -365,6 +365,7 @@
+@@ -366,6 +366,7 @@
rtl8153: device@2 {
compatible = "usbbda,8153";
reg = <2>;
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
-@@ -23,6 +23,10 @@
- aliases {
+@@ -25,6 +25,10 @@
+ ethernet1 = &gmac2phy;
mmc0 = &sdmmc;
mmc1 = &emmc;
+ led-boot = &led_blue;
};
chosen {
-@@ -55,10 +59,11 @@
+@@ -57,10 +61,11 @@
pinctrl-0 = <&led_pin>;
pinctrl-names = "default";
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
-@@ -15,6 +15,10 @@
- ethernet0 = &gmac1;
+@@ -16,6 +16,10 @@
mmc0 = &sdhci;
mmc1 = &sdmmc0;
+ mmc2 = &sdmmc2;
+ led-boot = &led_blue;
+ led-failsafe = &led_blue;
+ led-running = &led_blue;
};
chosen: chosen {
-@@ -42,11 +46,11 @@
+@@ -43,11 +47,11 @@
leds {
compatible = "gpio-leds";
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -14,6 +14,11 @@
- aliases {
+@@ -15,6 +15,11 @@
+ ethernet0 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc;
+
};
analog-sound {
-@@ -39,11 +44,10 @@
+@@ -40,11 +45,10 @@
pinctrl-names = "default";
pinctrl-0 = <&io_led>;
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
-@@ -404,7 +404,7 @@
+@@ -383,7 +383,7 @@
max-frequency = <150000000>;
no-sdio;
no-mmc;
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
-@@ -419,7 +419,7 @@
+@@ -426,7 +426,7 @@
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
-@@ -634,7 +634,7 @@
+@@ -632,7 +632,7 @@
disable-wp;
no-mmc;
no-sdio;
+};
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-an
+@@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-an
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-odroid-m1s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
@@ -17,6 +17,10 @@
- aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
+ led-boot = &led_blue;
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-@@ -14,6 +14,10 @@
- aliases {
+@@ -13,6 +13,10 @@
+ ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
+ led-boot = &led_blue;
};
chosen {
-@@ -33,11 +37,11 @@
+@@ -32,11 +36,11 @@
pinctrl-0 = <&user_led2>;
/* USER_LED2 */
projects / openwrt / staging / blocktrron.git / commitdiff