*/
#include <platform_def.h>
+#include <xlat_tables_defs.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
SECTIONS
{
. = BL1_RO_BASE;
- ASSERT(. == ALIGN(4096),
+ ASSERT(. == ALIGN(PAGE_SIZE),
"BL1_RO_BASE address is not aligned on a page boundary.")
#if SEPARATE_CODE_AND_RODATA
*bl1_entrypoint.o(.text*)
*(.text*)
*(.vectors)
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__TEXT_END__ = .;
} >ROM
"cpu_ops not defined for this platform.")
. = BL1_RW_BASE;
- ASSERT(BL1_RW_BASE == ALIGN(4096),
+ ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
"BL1_RW_BASE address is not aligned on a page boundary.")
/*
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
- coherent_ram (NOLOAD) : ALIGN(4096) {
+ coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
__COHERENT_RAM_START__ = .;
*(tzfw_coherent_mem)
__COHERENT_RAM_END_UNALIGNED__ = .;
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__COHERENT_RAM_END__ = .;
} >RAM
#endif
*/
#include <platform_def.h>
+#include <xlat_tables_defs.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
SECTIONS
{
. = BL2_BASE;
- ASSERT(. == ALIGN(4096),
+ ASSERT(. == ALIGN(PAGE_SIZE),
"BL2_BASE address is not aligned on a page boundary.")
#if SEPARATE_CODE_AND_RODATA
*bl2_entrypoint.o(.text*)
*(.text*)
*(.vectors)
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__TEXT_END__ = .;
} >RAM
KEEP(*(.img_parser_lib_descs))
__PARSER_LIB_DESCS_END__ = .;
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RODATA_END__ = .;
} >RAM
#else
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RO_END__ = .;
} >RAM
#endif
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
- coherent_ram (NOLOAD) : ALIGN(4096) {
+ coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
__COHERENT_RAM_START__ = .;
*(tzfw_coherent_mem)
__COHERENT_RAM_END_UNALIGNED__ = .;
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__COHERENT_RAM_END__ = .;
} >RAM
#endif
*/
#include <platform_def.h>
+#include <xlat_tables_defs.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
SECTIONS
{
. = BL2U_BASE;
- ASSERT(. == ALIGN(4096),
+ ASSERT(. == ALIGN(PAGE_SIZE),
"BL2U_BASE address is not aligned on a page boundary.")
#if SEPARATE_CODE_AND_RODATA
*bl2u_entrypoint.o(.text*)
*(.text*)
*(.vectors)
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__TEXT_END__ = .;
} >RAM
.rodata . : {
__RODATA_START__ = .;
*(.rodata*)
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RODATA_END__ = .;
} >RAM
#else
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RO_END__ = .;
} >RAM
#endif
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
- coherent_ram (NOLOAD) : ALIGN(4096) {
+ coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
__COHERENT_RAM_START__ = .;
*(tzfw_coherent_mem)
__COHERENT_RAM_END_UNALIGNED__ = .;
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__COHERENT_RAM_END__ = .;
} >RAM
#endif
*/
#include <platform_def.h>
+#include <xlat_tables_defs.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
SECTIONS
{
. = BL31_BASE;
- ASSERT(. == ALIGN(4096),
+ ASSERT(. == ALIGN(PAGE_SIZE),
"BL31_BASE address is not aligned on a page boundary.")
#if SEPARATE_CODE_AND_RODATA
*bl31_entrypoint.o(.text*)
*(.text*)
*(.vectors)
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__TEXT_END__ = .;
} >RAM
. = ALIGN(8);
#include <pubsub_events.h>
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RODATA_END__ = .;
} >RAM
#else
* executable. No RW data from the next section must creep in.
* Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RO_END__ = .;
} >RAM
#endif
* There's no need to include this into the RO section of BL31 because it
* doesn't need to be accessed by BL31.
*/
- spm_shim_exceptions : ALIGN(4096) {
+ spm_shim_exceptions : ALIGN(PAGE_SIZE) {
__SPM_SHIM_EXCEPTIONS_START__ = .;
*(.spm_shim_exceptions)
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__SPM_SHIM_EXCEPTIONS_END__ = .;
} >RAM
#endif
__SP_IMAGE_XLAT_TABLES_START__ = .;
*secure_partition*.o(xlat_table)
/* Make sure that the rest of the page is empty. */
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__SP_IMAGE_XLAT_TABLES_END__ = .;
#endif
*(xlat_table)
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
- coherent_ram (NOLOAD) : ALIGN(4096) {
+ coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
__COHERENT_RAM_START__ = .;
/*
* Bakery locks are stored in coherent memory
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__COHERENT_RAM_END__ = .;
} >RAM
#endif
*/
#include <platform_def.h>
+#include <xlat_tables_defs.h>
OUTPUT_FORMAT(elf32-littlearm)
OUTPUT_ARCH(arm)
SECTIONS
{
. = BL32_BASE;
- ASSERT(. == ALIGN(4096),
+ ASSERT(. == ALIGN(PAGE_SIZE),
"BL32_BASE address is not aligned on a page boundary.")
#if SEPARATE_CODE_AND_RODATA
*entrypoint.o(.text*)
*(.text*)
*(.vectors)
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__TEXT_END__ = .;
} >RAM
. = ALIGN(8);
#include <pubsub_events.h>
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RODATA_END__ = .;
} >RAM
#else
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory block is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RO_END__ = .;
} >RAM
#endif
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
- coherent_ram (NOLOAD) : ALIGN(4096) {
+ coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
__COHERENT_RAM_START__ = .;
/*
* Bakery locks are stored in coherent memory
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__COHERENT_RAM_END__ = .;
} >RAM
*/
#include <platform_def.h>
+#include <xlat_tables_defs.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
SECTIONS
{
. = BL32_BASE;
- ASSERT(. == ALIGN(4096),
+ ASSERT(. == ALIGN(PAGE_SIZE),
"BL32_BASE address is not aligned on a page boundary.")
#if SEPARATE_CODE_AND_RODATA
*tsp_entrypoint.o(.text*)
*(.text*)
*(.vectors)
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__TEXT_END__ = .;
} >RAM
.rodata . : {
__RODATA_START__ = .;
*(.rodata*)
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RODATA_END__ = .;
} >RAM
#else
* read-only, executable. No RW data from the next section must
* creep in. Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RO_END__ = .;
} >RAM
#endif
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
- coherent_ram (NOLOAD) : ALIGN(4096) {
+ coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
__COHERENT_RAM_START__ = .;
*(tzfw_coherent_mem)
__COHERENT_RAM_END_UNALIGNED__ = .;
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__COHERENT_RAM_END__ = .;
} >RAM
#endif
#ifndef __ARM_COMMON_LD_S__
#define __ARM_COMMON_LD_S__
+#include <xlat_tables_defs.h>
+
MEMORY {
EL3_SEC_DRAM (rw): ORIGIN = ARM_EL3_TZC_DRAM1_BASE, LENGTH = ARM_EL3_TZC_DRAM1_SIZE
}
SECTIONS
{
. = ARM_EL3_TZC_DRAM1_BASE;
- ASSERT(. == ALIGN(4096),
+ ASSERT(. == ALIGN(PAGE_SIZE),
"ARM_EL3_TZC_DRAM_BASE address is not aligned on a page boundary.")
- el3_tzc_dram (NOLOAD) : ALIGN(4096) {
+ el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) {
__EL3_SEC_DRAM_START__ = .;
*(arm_el3_tzc_dram)
__EL3_SEC_DRAM_UNALIGNED_END__ = .;
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__EL3_SEC_DRAM_END__ = .;
} >EL3_SEC_DRAM
}
*/
#include <platform_def.h>
+#include <xlat_tables_defs.h>
OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
*(.vectors)
} >RAM
- ASSERT(. == ALIGN(4096),
+ ASSERT(. == ALIGN(PAGE_SIZE),
"BL31_BASE address is not aligned on a page boundary.")
ro . : {
* executable. No RW data from the next section must creep in.
* Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__RO_END__ = .;
} >RAM
* are not mixed with normal data. This is required to set up the correct
* memory attributes for the coherent data page tables.
*/
- coherent_ram (NOLOAD) : ALIGN(4096) {
+ coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
__COHERENT_RAM_START__ = .;
/*
* Bakery locks are stored in coherent memory
* as device memory. No other unexpected data must creep in.
* Ensure the rest of the current memory page is unused.
*/
- . = NEXT(4096);
+ . = NEXT(PAGE_SIZE);
__COHERENT_RAM_END__ = .;
} >RAM2
#endif
#ifndef __ROCKCHIP_PLAT_LD_S__
#define __ROCKCHIP_PLAT_LD_S__
+#include <xlat_tables_defs.h>
+
MEMORY {
SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE
PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
SECTIONS
{
. = SRAM_BASE;
- ASSERT(. == ALIGN(4096),
+ ASSERT(. == ALIGN(PAGE_SIZE),
"SRAM_BASE address is not aligned on a page boundary.")
/*
* | sram data
* ----------------
*/
- .incbin_sram : ALIGN(4096) {
+ .incbin_sram : ALIGN(PAGE_SIZE) {
__sram_incbin_start = .;
*(.sram.incbin)
__sram_incbin_real_end = .;
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
__sram_incbin_end = .;
} >SRAM
ASSERT((__sram_incbin_real_end - __sram_incbin_start) <=
SRAM_BIN_LIMIT, ".incbin_sram has exceeded its limit")
- .text_sram : ALIGN(4096) {
+ .text_sram : ALIGN(PAGE_SIZE) {
__bl31_sram_text_start = .;
*(.sram.text)
*(.sram.rodata)
__bl31_sram_text_real_end = .;
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
__bl31_sram_text_end = .;
} >SRAM
ASSERT((__bl31_sram_text_real_end - __bl31_sram_text_start) <=
SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit")
- .data_sram : ALIGN(4096) {
+ .data_sram : ALIGN(PAGE_SIZE) {
__bl31_sram_data_start = .;
*(.sram.data)
__bl31_sram_data_real_end = .;
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
__bl31_sram_data_end = .;
} >SRAM
ASSERT((__bl31_sram_data_real_end - __bl31_sram_data_start) <=
SRAM_DATA_LIMIT, ".data_sram has exceeded its limit")
- .stack_sram : ALIGN(4096) {
+ .stack_sram : ALIGN(PAGE_SIZE) {
__bl31_sram_stack_start = .;
- . += 4096;
+ . += PAGE_SIZE;
__bl31_sram_stack_end = .;
} >SRAM