diff options
| author | Shiji Yang | 2025-06-01 04:56:09 +0000 |
|---|---|---|
| committer | Christian Marangi | 2025-10-14 08:27:28 +0000 |
| commit | a4c654b27cfd08583d058445695f64d32e91fb95 (patch) | |
| tree | becc3b6b9597faaf2681e6dc23602495118bff09 | |
| parent | b56c7731766a94a7f324acfcf64e24a9a56d9720 (diff) | |
| download | openwrt-a4c654b27cfd08583d058445695f64d32e91fb95.tar.gz | |
ipq806x: dts: rework PCIe nodes for Chromium OnHub
- Reuse the bridges node defined on "qcom-ipq8064.dtsi".
- Rename PCIe device nodes to unified "wifi@0,0".
- Add the missing "qcom,ath10k" compatibles.
- Remove unseless property "interrupt-controller". There are no
consumers use these PCIe devices as interrupt controllers.
- Change bus number from 0 to 1, just like other ipq806x devices.
The valid PCIe bus range on this platform is 1 - 255.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18989
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
| -rw-r--r-- | target/linux/ipq806x/files-6.12/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi | 59 |
1 files changed, 19 insertions, 40 deletions
diff --git a/target/linux/ipq806x/files-6.12/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi b/target/linux/ipq806x/files-6.12/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi index 08f5a4487c..14c12ba053 100644 --- a/target/linux/ipq806x/files-6.12/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi +++ b/target/linux/ipq806x/files-6.12/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi @@ -452,59 +452,38 @@ &pcie0 { status = "okay"; +}; - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - interrupt-controller; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - qcom,ath10k-sa-gpio = <2 3 4 0>; - qcom,ath10k-sa-gpio-func = <5 5 5 0>; - }; +&pcie_bridge0 { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-sa-gpio = <2 3 4 0>; + qcom,ath10k-sa-gpio-func = <5 5 5 0>; }; }; &pcie1 { status = "okay"; +}; - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - interrupt-controller; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - qcom,ath10k-sa-gpio = <2 3 4 0>; - qcom,ath10k-sa-gpio-func = <5 5 5 0>; - }; +&pcie_bridge1 { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-sa-gpio = <2 3 4 0>; + qcom,ath10k-sa-gpio-func = <5 5 5 0>; }; }; &pcie2 { status = "okay"; +}; - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - interrupt-controller; - - ath10k@0,0 { - reg = <0 0 0 0 0>; - device_type = "pci"; - }; +&pcie_bridge2 { + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; }; }; |