CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \
-Wmissing-include-dirs $(ERRORS) $(WARNINGS)
ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \
- -D__ASSEMBLY__ -ffreestanding \
- -Wa,--fatal-warnings
+ -ffreestanding -Wa,--fatal-warnings
TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \
-ffreestanding -fno-builtin -Wall -std=gnu99 \
-Os -ffunction-sections -fdata-sections
$(eval $(call add_define,PRELOADED_BL33_BASE))
endif
endif
-# Define the AARCH32/AARCH64 flag based on the ARCH flag
-ifeq (${ARCH},aarch32)
- $(eval $(call add_define,AARCH32))
-else
- $(eval $(call add_define,AARCH64))
-endif
# Define the DYN_DISABLE_AUTH flag only if set.
ifeq (${DYN_DISABLE_AUTH},1)
msg_start:
@echo "Building ${PLAT}"
-# Check if deprecated declarations and cpp warnings should be treated as error or not.
ifeq (${ERROR_DEPRECATED},0)
+# Check if deprecated declarations and cpp warnings should be treated as error or not.
ifneq ($(findstring clang,$(notdir $(CC))),)
CPPFLAGS += -Wno-error=deprecated-declarations
else
CPPFLAGS += -Wno-error=deprecated-declarations -Wno-error=cpp
endif
+# __ASSEMBLY__ is deprecated in favor of the compiler-builtin __ASSEMBLER__.
+ASFLAGS += -D__ASSEMBLY__
+# AARCH32/AARCH64 macros are deprecated in favor of the compiler-builtin __aarch64__.
+ifeq (${ARCH},aarch32)
+ $(eval $(call add_define,AARCH32))
+else
+ $(eval $(call add_define,AARCH64))
endif
+endif # !ERROR_DEPRECATED
$(eval $(call MAKE_LIB_DIRS))
$(eval $(call MAKE_LIB,c))
INFO("BL1-FWU: Executing Secure image\n");
-#ifdef AARCH64
+#ifdef __aarch64__
/* Save NS-EL1 system registers. */
cm_el1_sysregs_context_save(NON_SECURE);
#endif
/* Update the secure image id. */
sec_exec_image_id = image_id;
-#ifdef AARCH64
+#ifdef __aarch64__
*handle = cm_get_context(SECURE);
#else
*handle = smc_get_ctx(SECURE);
INFO("BL1-FWU: Resuming %s world context\n",
(resume_sec_state == SECURE) ? "secure" : "normal");
-#ifdef AARCH64
+#ifdef __aarch64__
/* Save the EL1 system registers of calling world. */
cm_el1_sysregs_context_save(caller_sec_state);
sec_exec_image_id = INVALID_IMAGE_ID;
INFO("BL1-FWU: Resuming Normal world context\n");
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* Secure world is done so no need to save the context.
* Just restore the Non-Secure context.
/* Perform early platform-specific setup */
bl1_early_platform_setup();
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* Update pointer authentication key before the MMU is enabled. It is
* saved in the rodata section, that can be writen before enabling the
* in the early platform setup.
*/
bl_handle_pauth();
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
/* Perform late platform-specific setup */
bl1_plat_arch_setup();
/*
* Ensure that MMU/Caches and coherency are turned on
*/
-#ifdef AARCH32
- val = read_sctlr();
-#else
+#ifdef __aarch64__
val = read_sctlr_el3();
+#else
+ val = read_sctlr();
#endif
assert(val & SCTLR_M_BIT);
assert(val & SCTLR_C_BIT);
******************************************************************************/
void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
{
-#ifdef AARCH32
- NOTICE("BL1: Booting BL32\n");
-#else
+#ifdef __aarch64__
NOTICE("BL1: Booting BL31\n");
-#endif /* AARCH32 */
+#else
+ NOTICE("BL1: Booting BL32\n");
+#endif /* __aarch64__ */
print_entry_point_info(bl_ep_info);
}
#include "bl2_private.h"
-#ifdef AARCH32
-#define NEXT_IMAGE "BL32"
-#else
+#ifdef __aarch64__
#define NEXT_IMAGE "BL31"
+#else
+#define NEXT_IMAGE "BL32"
#endif
#if !BL2_AT_EL3
/* Perform early platform-specific setup */
bl2_early_platform_setup2(arg0, arg1, arg2, arg3);
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* Update pointer authentication key before the MMU is enabled. It is
* saved in the rodata section, that can be writen before enabling the
* in the early platform setup.
*/
bl_handle_pauth();
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
/* Perform late platform-specific setup */
bl2_plat_arch_setup();
/* Perform early platform-specific setup */
bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3);
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* Update pointer authentication key before the MMU is enabled. It is
* saved in the rodata section, that can be writen before enabling the
* in the early platform setup.
*/
bl_handle_pauth();
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
/* Perform late platform-specific setup */
bl2_el3_plat_arch_setup();
next_bl_ep_info = bl2_load_images();
#if !BL2_AT_EL3
-#ifdef AARCH32
+#ifndef __aarch64__
/*
* For AArch32 state BL1 and BL2 share the MMU setup.
* Given that BL2 does not map BL1 regions, MMU needs
* to be disabled in order to go back to BL1.
*/
disable_mmu_icache_secure();
-#endif /* AARCH32 */
+#endif /* !__aarch64__ */
console_flush();
console_flush();
-#ifdef AARCH32
+#ifndef __aarch64__
/*
* For AArch32 state BL1 and BL2U share the MMU setup.
* Given that BL2U does not map BL1 regions, MMU needs
* to be disabled in order to go back to BL1.
*/
disable_mmu_icache_secure();
-#endif /* AARCH32 */
+#endif /* !__aarch64__ */
/*
* Indicate that BL2U is done and resume back to
#define TSP_ARGS_END 0x40
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
uint64_t arg7);
uint64_t tsp_main(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TSP_PRIVATE_H */
* Returns true if the address points to a virtual address that can be read at
* the current EL, false otherwise.
*/
-#ifdef AARCH64
+#ifdef __aarch64__
static bool is_address_readable(uintptr_t addr)
{
unsigned int el = get_current_el();
return true;
}
-#else /* if AARCH32 */
+#else /* !__aarch64__ */
static bool is_address_readable(uintptr_t addr)
{
unsigned int el = get_current_el();
return true;
}
-#endif
+#endif /* __aarch64__ */
/*
* Returns true if all the bytes in a given object are in mapped memory and an
*/
static struct frame_record *adjust_frame_record(struct frame_record *fr)
{
-#ifdef AARCH64
+#ifdef __aarch64__
return fr;
#else
return (struct frame_record *)((uintptr_t)fr - 4U);
PRINT_IMAGE_ARG(1);
PRINT_IMAGE_ARG(2);
PRINT_IMAGE_ARG(3);
-#ifndef AARCH32
+#ifdef __aarch64__
PRINT_IMAGE_ARG(4);
PRINT_IMAGE_ARG(5);
PRINT_IMAGE_ARG(6);
#undef PRINT_IMAGE_ARG
}
-#ifdef AARCH64
+#ifdef __aarch64__
/*******************************************************************************
* Handle all possible cases regarding ARMv8.3-PAuth.
******************************************************************************/
#endif /* ENABLE_PAUTH */
}
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
TF-A has been tested with Linaro Release 18.04.
-Download and install the AArch32 or AArch64 little-endian GCC cross compiler. If
-you would like to use the latest features available, download GCC 8.2-2019.01
-compiler from `arm Developer page`_. Otherwise, the `Linaro Release Notes`_
-documents which version of the compiler to use for a given Linaro Release. Also,
-these `Linaro instructions`_ provide further guidance and a script, which can be
-used to download Linaro deliverables automatically.
+Download and install the AArch32 (arm-eabi) or AArch64 little-endian
+(aarch64-linux-gnu) GCC cross compiler. If you would like to use the latest
+features available, download GCC 8.3-2019.03 compiler from
+`arm Developer page`_. Otherwise, the `Linaro Release Notes`_ documents which
+version of the compiler to use for a given Linaro Release. Also, these
+`Linaro instructions`_ provide further guidance and a script, which can be used
+to download Linaro deliverables automatically.
Optionally, TF-A can be built using clang version 4.0 or newer or Arm
Compiler 6. See instructions below on how to switch the default compiler.
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
+ export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
It is possible to build TF-A using Clang or Arm Compiler 6. To do so
``CC`` needs to point to the clang or armclang binary, which will
#include "ccn_private.h"
static const ccn_desc_t *ccn_plat_desc;
-#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
+#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
DEFINE_BAKERY_LOCK(ccn_lock);
#endif
assert(ccn_plat_desc);
assert(ccn_plat_desc->periphbase);
-#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
+#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
bakery_lock_get(&ccn_lock);
#endif
start_region_id = region_id;
rn_id_map);
}
-#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
+#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
bakery_lock_release(&ccn_lock);
#endif
}
#define SDS_REGION_REGIONSIZE_OFFSET 0x4
#define SDS_REGION_DESC_SIZE 0x8
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
& SDS_REGION_SCH_VERSION_MASK)
#define GET_SDS_REGION_SIZE(region) ((((region_desc_t *)(region))->reg[1]))
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SDS_PRIVATE_H */
plat_driver_data->interrupt_props != NULL : 1);
/* Check for system register support */
-#ifdef AARCH32
- assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
-#else
+#ifdef __aarch64__
assert((read_id_aa64pfr0_el1() &
(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
-#endif /* AARCH32 */
+#else
+ assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
+#endif /* __aarch64__ */
/* The GIC version should be 3.0 */
gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
* Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
* are zeroes.
*/
-#ifdef AARCH32
+#ifdef __aarch64__
static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
{
- return (((typer_val) >> 32) & U(0xffffff));
+ return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) |
+ ((typer_val >> 32) & U(0xffffff));
}
#else
static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
{
- return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) |
- ((typer_val >> 32) & U(0xffffff));
+ return (((typer_val) >> 32) & U(0xffffff));
}
#endif
#define IMX_UART_TS_RXFULL BIT(3)
#define IMX_UART_TS_SOFTRST BIT(0)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
typedef struct {
console_t console;
uint32_t clock,
uint32_t baud,
console_imx_uart_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* IMX_UART_H */
#ifndef MICRO_DELAY_H
#define MICRO_DELAY_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
void rcar_micro_delay(uint64_t micro_sec);
#endif
#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
#define RCAR_CLUSTER_CA53 (1U)
#define RCAR_CLUSTER_CA57 (2U)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr);
void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr);
void rcar_pwrc_clusteroff(uint64_t mpidr);
#define SMC_CTX_PMCR U(0x88)
#define SMC_CTX_SIZE U(0x90)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */
void *smc_get_next_ctx(void);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* SMCCC_HELPERS_H */
#include <lib/smccc.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdbool.h>
_x4 = read_ctx_reg(regs, CTX_GPREG_X4); \
} while (false)
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* SMCCC_HELPERS_H */
#define is_fwu_fid(_fid) \
((_fid >= FWU_SMC_FID_START) && (_fid <= FWU_SMC_FID_END))
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <lib/cassert.h>
void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
meminfo_t *bl2_mem_layout);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* BL1_H */
#ifndef EHF_H
#define EHF_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdint.h>
void ehf_allow_ns_preemption(uint64_t preempt_ret_code);
unsigned int ehf_is_ns_preemption_allowed(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* EHF_H */
#define get_interrupt_src_ss(flag) (((flag) >> INTR_SRC_SS_FLAG_SHIFT) & \
INTR_SRC_SS_FLAG_MASK)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <errno.h>
#include <stdint.h>
int disable_intr_rm_local(uint32_t type, uint32_t security_state);
int enable_intr_rm_local(uint32_t type, uint32_t security_state);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* INTERRUPT_MGMT_H */
#define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
void tsp_setup(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TSP_H */
#include <common/param_header.h>
#include <lib/utils_def.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
#include <lib/cassert.h>
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#include <export/common/bl_common_exp.h>
#define __TEXT_END__ Load$$__TEXT_EPILOGUE__$$Base
#endif /* USE_ARM_LINK */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/*
* Declarations of linker defined symbols to help determine memory layout of
void bl_handle_pauth(void);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* BL_COMMON_H */
#define LOG_LEVEL_INFO U(40)
#define LOG_LEVEL_VERBOSE U(50)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdarg.h>
void tf_log(const char *fmt, ...) __printflike(1, 2);
void tf_log_set_max_level(unsigned int log_level);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* DEBUG_H */
#include <common/param_header.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
#include <lib/cassert.h>
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#include <export/common/ep_info_exp.h>
#define SET_SECURITY_STATE(x, security) \
((x) = ((x) & ~EP_SECURITY_MASK) | (security))
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/*
* Compile time assertions related to the 'entry_point_info' structure to
__builtin_offsetof(entry_point_info_t, pc), \
assert_BL31_pc_offset_mismatch);
-#ifdef AARCH32
+#ifndef __aarch64__
CASSERT(ENTRY_POINT_INFO_LR_SVC_OFFSET ==
__builtin_offsetof(entry_point_info_t, lr_svc),
assert_entrypoint_lr_offset_error);
__builtin_offsetof(entry_point_info_t, pc), \
assert_entrypoint_and_spsr_should_be_adjacent);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* EP_INFO_H */
#ifndef INTERRUPT_PROPS_H
#define INTERRUPT_PROPS_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* Create an interrupt property descriptor from various interrupt properties */
#define INTR_PROP_DESC(num, pri, grp, cfg) \
unsigned int intr_cfg:2;
} interrupt_prop_t;
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* INTERRUPT_PROPS_H */
#include <stdbool.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#include <export/common/param_header_exp.h>
* Constants to allow the assembler access a runtime service
* descriptor
*/
-#ifdef AARCH32
-#define RT_SVC_SIZE_LOG2 U(4)
-#define RT_SVC_DESC_INIT U(8)
-#define RT_SVC_DESC_HANDLE U(12)
-#else
+#ifdef __aarch64__
#define RT_SVC_SIZE_LOG2 U(5)
#define RT_SVC_DESC_INIT U(16)
#define RT_SVC_DESC_HANDLE U(24)
-#endif /* AARCH32 */
+#else
+#define RT_SVC_SIZE_LOG2 U(4)
+#define RT_SVC_DESC_INIT U(8)
+#define RT_SVC_DESC_HANDLE U(12)
+#endif /* __aarch64__ */
#define SIZEOF_RT_SVC_DESC (U(1) << RT_SVC_SIZE_LOG2)
*/
#define MAX_RT_SVCS U(128)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* Prototype for runtime service initializing function */
typedef int32_t (*rt_svc_init_t)(void);
extern uint8_t rt_svc_descs_indices[MAX_RT_SVCS];
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* RUNTIME_SVC_H */
#define SLAVE_IF_UNUSED -1
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
void cci_enable_snoop_dvm_reqs(unsigned int master_id);
void cci_disable_snoop_dvm_reqs(unsigned int master_id);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CCI_H */
*/
#define CCN_GET_RUN_STATE(pstate) (pstate & 0xf)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
/*
unsigned int node_id,
unsigned int reg_offset);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CCN_H */
#define SDS_ERR_STRUCT_NOT_FOUND -3
#define SDS_ERR_STRUCT_NOT_FINALIZED -4
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
size_t size, sds_access_mode_t mode);
int sds_struct_write(uint32_t structure_id, unsigned int fld_off, void *data,
size_t size, sds_access_mode_t mode);
-#endif /*__ASSEMBLY__ */
+#endif /*__ASSEMBLER__ */
#endif /* SDS_H */
#define PSYSR_INVALID U(0xffffffff)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
unsigned int fvp_pwrc_read_psysr(u_register_t mpidr);
unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* FVP_PWRC_H */
/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
#define INT_ID_MASK U(0x3ff)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdint.h>
unsigned int gicv2_set_pmr(unsigned int mask);
void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* GICV2_H */
#define GITS_CTLR_QUIESCENT_SHIFT 31
#define GITS_CTLR_QUIESCENT_BIT BIT_32(GITS_CTLR_QUIESCENT_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdbool.h>
#include <stdint.h>
void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num);
unsigned int gicv3_set_pmr(unsigned int mask);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* GICV3_H */
#define CONSOLE_T_PL011_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int console_pl011_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_pl011_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* PL011_H */
#define SP805_CTR_RESEN (U(1) << 1)
#define SP805_CTR_INTEN (U(1) << 0)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
void sp805_stop(uintptr_t base);
void sp805_refresh(uintptr_t base, unsigned int ticks);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SP805_H */
#define TZC_400_REGION_SIZE U(0x20)
#define TZC_400_ACTION_OFF U(0x4)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdint.h>
tzc400_disable_filters();
}
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TZC400_H */
/* Length of registers for configuring each region */
#define TZC_DMC500_REGION_SIZE U(0x018)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int tzc_dmc500_verify_complete(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TZC_DMC500_H */
/* Memory buffer allocator options */
#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* System headers required to build mbed TLS with the current configuration */
#include <stdlib.h>
#include "mbedtls/check_config.h"
#define CONSOLE_T_CDNS_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int console_cdns_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_cdns_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* CDNS_UART_H */
/* Returned by console_xxx() if no registered console implements xxx. */
#define ERROR_NO_VALID_CONSOLE (-128)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
/* Flush all consoles registered for the current state. */
int console_flush(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CONSOLE_H */
#define LLC_EXCLUSIVE_EN 0x100
#define LLC_WAY_MASK 0xFFFFFFFF
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void llc_cache_sync(int ap_index);
void llc_flush_all(int ap_index);
void llc_clean_all(int ap_index);
#ifndef CCU_H
#define CCU_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <drivers/marvell/addr_map.h>
#endif
#define CCU_SRAM_WIN_CR CCU_WIN_CR_OFFSET(MVEBU_AP0, 1)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
int init_ccu(int);
void ccu_win_check(struct addr_map_win *win);
void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
#define CONSOLE_T_A3700_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int console_a3700_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_a3700_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* A3700_CONSOLE_H */
#define CONSOLE_T_MESON_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int console_meson_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_meson_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* MESON_CONSOLE_H */
#define CONSOLE_T_RCAR_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int console_rcar_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_rcar_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* RCAR_PRINTF_H */
#define CONSOLE_T_STM32_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int console_stm32_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
struct console_stm32 *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* STM32_CONSOLE_H */
#define GPIO_PULL_DOWN 0x02
#define GPIO_PULL_MASK U(0x03)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int dt_set_pinctrl_config(int node);
void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
uint32_t pull, uint32_t alternate, uint8_t status);
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* STM32_GPIO_H */
#define CONSOLE_T_16550_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_16550_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* UART_16550_H */
#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdbool.h>
#include <stdint.h>
#define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* BAKERY_LOCK_H */
******************************************************************************/
#define PCR p15, 0, c15, c0, 0
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <arch_helpers.h>
DEFINE_COPROCR_RW_FUNCS(pcr, PCR)
#endif
#define CORTEX_A75_AMU_GROUP0_MASK U(0x7)
#define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
uint64_t cortex_a75_amu_cnt_read(int idx);
unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CORTEX_A75_H */
#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
+
+/*******************************************************************************
+ * CPU Activity Monitor Unit register specific definitions.
+ ******************************************************************************/
+#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
+#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
+#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
+#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
+
+#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF)
+#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7)
+
#endif /* CORTEX_HERCULES_H */
#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3
#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
uint64_t cpuamu_cnt_read(unsigned int idx);
void cpuamu_context_save(unsigned int nr_counters);
void cpuamu_context_restore(unsigned int nr_counters);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CPUAMU_H */
#define DENVER_CPU_PMSTATE_C7 U(0x7)
#define DENVER_CPU_PMSTATE_MASK U(0xF)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* Disable Dynamic Code Optimisation */
void denver_disable_dco(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* DENVER_H */
#ifndef ERRATA_REPORT_H
#define ERRATA_REPORT_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <arch.h>
#include <arch_helpers.h>
void errata_print_msg(unsigned int status, const char *cpu, const char *id);
int errata_needs_reporting(spinlock_t *lock, uint32_t *reported);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/* Errata status */
#define ERRATA_NOT_APPLIES 0
#define CTX_NS_SCTLR U(0x1C)
#define CTX_REGS_END U(0x20)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx), \
assert_core_context_regs_offset_mismatch);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CONTEXT_H */
#define CTX_PAUTH_REGS_END U(0)
#endif /* CTX_INCLUDE_PAUTH_REGS */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
void fpregs_context_restore(fp_regs_t *regs);
#endif
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CONTEXT_H */
void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep);
void cm_prepare_el3_exit(uint32_t security_state);
-#ifndef AARCH32
+#ifdef __aarch64__
void cm_el1_sysregs_context_save(uint32_t security_state);
void cm_el1_sysregs_context_restore(uint32_t security_state);
void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint);
#else
void *cm_get_next_context(void);
void cm_set_next_context(void *context);
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
#endif /* CONTEXT_MGMT_H */
#include <bl31/ehf.h>
-#ifdef AARCH32
-
-#if CRASH_REPORTING
-#error "Crash reporting is not supported in AArch32"
-#endif
-#define CPU_DATA_CPU_OPS_PTR 0x0
-#define CPU_DATA_CRASH_BUF_OFFSET 0x4
-
-#else /* AARCH32 */
+#ifdef __aarch64__
/* Offsets for the cpu_data structure */
#define CPU_DATA_CRASH_BUF_OFFSET 0x18
#define CPU_DATA_CRASH_BUF_SIZE 64
#define CPU_DATA_CPU_OPS_PTR 0x10
-#endif /* AARCH32 */
+#else /* __aarch64__ */
+
+#if CRASH_REPORTING
+#error "Crash reporting is not supported in AArch32"
+#endif
+#define CPU_DATA_CPU_OPS_PTR 0x0
+#define CPU_DATA_CRASH_BUF_OFFSET 0x4
+
+#endif /* __aarch64__ */
#if CRASH_REPORTING
#define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \
#define CPU_DATA_PMF_TS0_IDX 0
#endif
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <arch_helpers.h>
#include <lib/cassert.h>
* used for this.
******************************************************************************/
typedef struct cpu_data {
-#ifndef AARCH32
+#ifdef __aarch64__
void *cpu_context[2];
#endif
uintptr_t cpu_ops_ptr;
struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
-#ifndef AARCH32
+#ifdef __aarch64__
/* Return the cpu_data structure for the current CPU. */
static inline struct cpu_data *_cpu_data(void)
{
sizeof(((cpu_data_t *)0)->_m))
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CPU_DATA_H */
REGISTER_PUBSUB_EVENT(psci_suspend_pwrdown_start);
REGISTER_PUBSUB_EVENT(psci_suspend_pwrdown_finish);
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* These events are published by the AArch64 context management framework
* after the secure context is restored/saved via
*/
REGISTER_PUBSUB_EVENT(cm_entering_normal_world);
REGISTER_PUBSUB_EVENT(cm_exited_normal_world);
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
.num_intrs = ARRAY_SIZE(_array), \
}
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <assert.h>
void *handle, uint64_t flags);
void ras_init(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* RAS_H */
/* I/DFSC code for synchronous external abort */
#define SYNC_EA_FSC 0x10
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <arch.h>
#include <arch_helpers.h>
/* Library functions to probe Standard Error Record */
int ser_probe_memmap(uintptr_t base, unsigned int size_num_k, int *probe_data);
int ser_probe_sysreg(unsigned int idx_start, unsigned int num_idx, int *probe_data);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* RAS_ARCH_H */
#define JMP_SIZE (JMP_CTX_END >> 3)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
/* Jump buffer hosting x18 - x30 and sp_el0 registers */
typedef uint64_t jmp_buf[JMP_SIZE] __aligned(16);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SETJMP__H */
#include <setjmp_.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
int setjmp(jmp_buf env);
__dead2 void longjmp(jmp_buf env, int val);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SETJMP_H */
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct fdt_header {
fdt32_t magic; /* magic word FDT_MAGIC */
char data[0];
};
-#endif /* !__ASSEMBLY */
+#endif /* !__ASSEMBLER__ */
#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */
#define FDT_TAGSIZE sizeof(fdt32_t)
#define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT)
#define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0))
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
void __dead2 psci_power_down_wfi(void);
void psci_arch_setup(void);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* PSCI_H */
#include <common/ep_info.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <cdefs.h>
#include <stdint.h>
void psci_register_spd_pm_hook(const spd_pm_ops_t *pm);
void psci_prepare_next_non_secure_ctx(
entry_point_info_t *next_image_info);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* PSCI_LIB_H */
#define RT_INSTR_EXIT_CFLUSH U(5)
#define RT_INSTR_TOTAL_IDS U(6)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
PMF_DECLARE_CAPTURE_TIMESTAMP(rt_instr_svc)
PMF_DECLARE_GET_TIMESTAMP(rt_instr_svc)
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* RUNTIME_INSTR_H */
#define SMC_FROM_SECURE (U(0) << 0)
#define SMC_FROM_NON_SECURE (U(1) << 0)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
smc_uuid_word((_uuid).node[2], (_uuid).node[3], \
(_uuid).node[4], (_uuid).node[5]))
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* SMCCC_H */
#ifndef SPINLOCK_H
#define SPINLOCK_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
* C code should be put in this part of the header to avoid breaking ASM files
* or linker scripts including it.
*/
-#if !(defined(__LINKER__) || defined(__ASSEMBLY__))
+#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
#include <stddef.h>
#include <stdint.h>
/* Helper to invoke the function defined by DEFINE_LOAD_SYM_ADDR() */
#define LOAD_ADDR_OF(_name) (typeof(_name) *) load_addr_## _name()
-#endif /* !(defined(__LINKER__) || defined(__ASSEMBLY__)) */
+#endif /* !(defined(__LINKER__) || defined(__ASSEMBLER__)) */
#endif /* UTILS_H */
#define BIT_32(nr) (U(1) << (nr))
#define BIT_64(nr) (ULL(1) << (nr))
-#ifdef AARCH32
-#define BIT BIT_32
-#else
+#ifdef __aarch64__
#define BIT BIT_64
+#else
+#define BIT BIT_32
#endif
/*
* position @h. For example
* GENMASK_64(39, 21) gives us the 64bit vector 0x000000ffffe00000.
*/
-#if defined(__LINKER__) || defined(__ASSEMBLY__)
+#if defined(__LINKER__) || defined(__ASSEMBLER__)
#define GENMASK_32(h, l) \
(((0xFFFFFFFF) << (l)) & (0xFFFFFFFF >> (32 - 1 - (h))))
(((~UINT64_C(0)) << (l)) & (~UINT64_C(0) >> (64 - 1 - (h))))
#endif
-#ifdef AARCH32
-#define GENMASK GENMASK_32
-#else
+#ifdef __aarch64__
#define GENMASK GENMASK_64
+#else
+#define GENMASK GENMASK_32
#endif
/*
((_u32) > (UINT32_MAX - (_inc)))
/* Register size of the current architecture. */
-#ifdef AARCH32
-#define REGSZ U(4)
-#else
+#ifdef __aarch64__
#define REGSZ U(8)
+#else
+#define REGSZ U(4)
#endif
/*
#define MMU_CFG_TTBR0 2
#define MMU_CFG_PARAM_MAX 3
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdbool.h>
#include <stdint.h>
const uint64_t *base_table, unsigned long long max_pa,
uintptr_t max_va, int xlat_regime);
-#ifdef AARCH32
-/* AArch32 specific translation table API */
-void enable_mmu_svc_mon(unsigned int flags);
-void enable_mmu_hyp(unsigned int flags);
-
-void enable_mmu_direct_svc_mon(unsigned int flags);
-void enable_mmu_direct_hyp(unsigned int flags);
-#else
+#ifdef __aarch64__
/* AArch64 specific translation table APIs */
void enable_mmu_el1(unsigned int flags);
void enable_mmu_el2(unsigned int flags);
void enable_mmu_direct_el1(unsigned int flags);
void enable_mmu_direct_el2(unsigned int flags);
void enable_mmu_direct_el3(unsigned int flags);
-#endif /* AARCH32 */
+#else
+/* AArch32 specific translation table API */
+void enable_mmu_svc_mon(unsigned int flags);
+void enable_mmu_hyp(unsigned int flags);
+
+void enable_mmu_direct_svc_mon(unsigned int flags);
+void enable_mmu_direct_hyp(unsigned int flags);
+#endif /* __aarch64__ */
bool xlat_arch_is_granule_size_supported(size_t size);
size_t xlat_arch_get_max_supported_granule_size(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* XLAT_MMU_HELPERS_H */
#include <lib/xlat_tables/xlat_tables_defs.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
size_t size, unsigned int attr);
void mmap_add(const mmap_region_t *mm);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* XLAT_TABLES_H */
#ifndef XLAT_TABLES_ARCH_H
#define XLAT_TABLES_ARCH_H
-#ifdef AARCH32
-#include "aarch32/xlat_tables_aarch32.h"
-#else
+#ifdef __aarch64__
#include "aarch64/xlat_tables_aarch64.h"
+#else
+#include "aarch32/xlat_tables_aarch32.h"
#endif
/*
#define OSH (U(0x2) << 6)
#define ISH (U(0x3) << 6)
-#ifdef AARCH64
+#ifdef __aarch64__
/* Guarded Page bit */
#define GP (ULL(1) << 50)
#endif
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <lib/xlat_tables/xlat_tables_v2_helpers.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stddef.h>
#include <stdint.h>
uint32_t *attr);
int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* XLAT_TABLES_V2_H */
#error "Do not include this header file directly. Include xlat_tables_v2.h instead."
#endif
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdbool.h>
#include <stddef.h>
.initialized = false, \
}
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* XLAT_TABLES_V2_HELPERS_H */
#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
#define BOARD_CSS_PLAT_TYPE_FVP 0x03
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <lib/mmio.h>
((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#define MAX_IO_DEVICES 3
#endif
#endif
-#if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME
+#if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME
/*******************************************************************************
* BL32 specific defines for EL3 runtime in AArch32 mode
******************************************************************************/
# else
# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
# endif
-#endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */
+#endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */
/*
* BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
* SPD and no SPM, as they are the only ones that can be used as BL32.
*/
-#if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME)
+#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME
# if defined(SPD_none) && !ENABLE_SPM
# undef BL32_BASE
# endif /* defined(SPD_none) && !ENABLE_SPM */
-#endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */
+#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */
/*******************************************************************************
* FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
void arm_setup_romlib(void);
-#if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
+#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
/*
* Use this macro to instantiate lock before it is used in below
* arm_lock_xxx() macros
#define arm_lock_get()
#define arm_lock_release()
-#endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */
+#endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */
#if ARM_RECOM_STATE_ID_ENC
/*
#define SPIDEN_INT_CLR_SHIFT 6
#define SPIDEN_SEL_SET_SHIFT 7
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* SSC_VERSION related accessors */
(((val) >> SSC_VERSION_CONFIG_SHIFT) & \
SSC_VERSION_CONFIG_MASK)
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/*************************************************************************
* Required platform porting definitions common to all
/*
* Platform binary types for linking
*/
-#ifdef AARCH32
-#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
-#define PLATFORM_LINKER_ARCH arm
-#else
+#ifdef __aarch64__
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
-#endif /* AARCH32 */
+#else
+#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
+#define PLATFORM_LINKER_ARCH arm
+#endif /* __aarch64__ */
/*
* Generic platform constants
#endif /* SPM_MM */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
#endif /* SPM_MM */
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SPM_SVC_H */
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-Hercules
+ * -------------------------------------------------
+ */
+#if ENABLE_AMU
+func cortex_hercules_reset_func
+ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
+ mrs x0, actlr_el3
+ bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ msr actlr_el3, x0
+
+ /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
+ mrs x0, actlr_el2
+ bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
+ msr actlr_el2, x0
+
+ /* Enable group0 counters */
+ mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
+ msr CPUAMCNTENSET0_EL0, x0
+
+ /* Enable group1 counters */
+ mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
+ msr CPUAMCNTENSET1_EL0, x0
+ isb
+
+ ret
+endfunc cortex_hercules_reset_func
#endif
/* ---------------------------------------------
ret
endfunc cortex_hercules_cpu_reg_dump
+#if ENABLE_AMU
+#define HERCULES_RESET_FUNC cortex_hercules_reset_func
+#else
+#define HERCULES_RESET_FUNC CPU_NO_RESET_FUNC
+#endif
+
declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
- CPU_NO_RESET_FUNC, \
+ HERCULES_RESET_FUNC, \
cortex_hercules_core_pwr_dwn
#ifdef IMAGE_BL1
# define BL_STRING "BL1"
-#elif defined(AARCH64) && defined(IMAGE_BL31)
+#elif defined(__aarch64__) && defined(IMAGE_BL31)
# define BL_STRING "BL31"
-#elif defined(AARCH32) && defined(IMAGE_BL32)
+#elif !defined(__arch64__) && defined(IMAGE_BL32)
# define BL_STRING "BL32"
#elif defined(IMAGE_BL2) && BL2_AT_EL3
# define BL_STRING "BL2"
unsigned int their_bakery_data;
me = plat_my_core_pos();
-#ifdef AARCH32
- is_cached = read_sctlr() & SCTLR_C_BIT;
-#else
+#ifdef __aarch64__
is_cached = read_sctlr_el3() & SCTLR_C_BIT;
+#else
+ is_cached = read_sctlr() & SCTLR_C_BIT;
#endif
/* Get a ticket */
void bakery_lock_release(bakery_lock_t *lock)
{
bakery_info_t *my_bakery_info;
-#ifdef AARCH32
- unsigned int is_cached = read_sctlr() & SCTLR_C_BIT;
-#else
+#ifdef __aarch64__
unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT;
+#else
+ unsigned int is_cached = read_sctlr() & SCTLR_C_BIT;
#endif
my_bakery_info = get_bakery_info(plat_my_core_pos(), lock);
*/
if (!tee_validate_header(header)) {
INFO("Invalid OPTEE header, set legacy mode.\n");
-#ifdef AARCH64
+#ifdef __aarch64__
header_ep->args.arg0 = MODE_RW_64;
#else
header_ep->args.arg0 = MODE_RW_32;
if (header->arch == 0) {
header_ep->args.arg0 = MODE_RW_32;
} else {
-#ifdef AARCH64
+#ifdef __aarch64__
header_ep->args.arg0 = MODE_RW_64;
#else
ERROR("Cannot boot an AArch64 OP-TEE\n");
* This function determines the full entrypoint information for the requested
* PSCI entrypoint on power on/resume and returns it.
******************************************************************************/
-#ifdef AARCH32
-static int psci_get_ns_ep_info(entry_point_info_t *ep,
- uintptr_t entrypoint,
- u_register_t context_id)
-{
- u_register_t ep_attr;
- unsigned int aif, ee, mode;
- u_register_t scr = read_scr();
- u_register_t ns_sctlr, sctlr;
-
- /* Switch to non secure state */
- write_scr(scr | SCR_NS_BIT);
- isb();
- ns_sctlr = read_sctlr();
-
- sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr;
-
- /* Return to original state */
- write_scr(scr);
- isb();
- ee = 0;
-
- ep_attr = NON_SECURE | EP_ST_DISABLE;
- if (sctlr & SCTLR_EE_BIT) {
- ep_attr |= EP_EE_BIG;
- ee = 1;
- }
- SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
-
- ep->pc = entrypoint;
- zeromem(&ep->args, sizeof(ep->args));
- ep->args.arg0 = context_id;
-
- mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
-
- /*
- * TODO: Choose async. exception bits if HYP mode is not
- * implemented according to the values of SCR.{AW, FW} bits
- */
- aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT;
-
- ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif);
-
- return PSCI_E_SUCCESS;
-}
-
-#else
+#ifdef __aarch64__
static int psci_get_ns_ep_info(entry_point_info_t *ep,
uintptr_t entrypoint,
u_register_t context_id)
return PSCI_E_SUCCESS;
}
-#endif
+#else /* !__aarch64__ */
+static int psci_get_ns_ep_info(entry_point_info_t *ep,
+ uintptr_t entrypoint,
+ u_register_t context_id)
+{
+ u_register_t ep_attr;
+ unsigned int aif, ee, mode;
+ u_register_t scr = read_scr();
+ u_register_t ns_sctlr, sctlr;
+
+ /* Switch to non secure state */
+ write_scr(scr | SCR_NS_BIT);
+ isb();
+ ns_sctlr = read_sctlr();
+
+ sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr;
+
+ /* Return to original state */
+ write_scr(scr);
+ isb();
+ ee = 0;
+
+ ep_attr = NON_SECURE | EP_ST_DISABLE;
+ if (sctlr & SCTLR_EE_BIT) {
+ ep_attr |= EP_EE_BIG;
+ ee = 1;
+ }
+ SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
+
+ ep->pc = entrypoint;
+ zeromem(&ep->args, sizeof(ep->args));
+ ep->args.arg0 = context_id;
+
+ mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
+
+ /*
+ * TODO: Choose async. exception bits if HYP mode is not
+ * implemented according to the values of SCR.{AW, FW} bits
+ */
+ aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT;
+
+ ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif);
+
+ return PSCI_E_SUCCESS;
+}
+
+#endif /* __aarch64__ */
/*******************************************************************************
* This function validates the entrypoint with the platform layer if the
WRAPPER_DIR = ../../$(BUILD_PLAT)/libwrapper
LIBS = -lmbedtls -lfdt -lc
INC = $(INCLUDES:-I%=-I../../%)
-PPFLAGS = $(INC) $(DEFINES) -P -D__ASSEMBLY__ -D__LINKER__ -MD -MP -MT $(BUILD_DIR)/romlib.ld
+PPFLAGS = $(INC) $(DEFINES) -P -x assembler-with-cpp -D__LINKER__ -MD -MP -MT $(BUILD_DIR)/romlib.ld
OBJS = $(BUILD_DIR)/jmptbl.o $(BUILD_DIR)/init.o
MAPFILE = ../../$(BUILD_PLAT)/romlib/romlib.map
#define MAX_PHYS_ADDR tf_xlat_ctx.max_pa
#endif
-#ifdef AARCH32
+#ifdef __aarch64__
-void enable_mmu_svc_mon(unsigned int flags)
+void enable_mmu_el1(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
- enable_mmu_direct_svc_mon(flags);
+ enable_mmu_direct_el1(flags);
}
-void enable_mmu_hyp(unsigned int flags)
+void enable_mmu_el2(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
tf_xlat_ctx.va_max_address, EL2_REGIME);
- enable_mmu_direct_hyp(flags);
+ enable_mmu_direct_el2(flags);
}
-#else
-
-void enable_mmu_el1(unsigned int flags)
+void enable_mmu_el3(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
- tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
- enable_mmu_direct_el1(flags);
+ tf_xlat_ctx.va_max_address, EL3_REGIME);
+ enable_mmu_direct_el3(flags);
}
-void enable_mmu_el2(unsigned int flags)
+#else /* !__aarch64__ */
+
+void enable_mmu_svc_mon(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
- tf_xlat_ctx.va_max_address, EL2_REGIME);
- enable_mmu_direct_el2(flags);
+ tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
+ enable_mmu_direct_svc_mon(flags);
}
-void enable_mmu_el3(unsigned int flags)
+void enable_mmu_hyp(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
- tf_xlat_ctx.va_max_address, EL3_REGIME);
- enable_mmu_direct_el3(flags);
+ tf_xlat_ctx.va_max_address, EL2_REGIME);
+ enable_mmu_direct_hyp(flags);
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
-#ifdef AARCH64
+#ifdef __aarch64__
/* Check Guarded Page bit */
if ((desc & GP) != 0ULL) {
printf("-GP");
$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
$$(ECHO) " PP $$<"
- $$(Q)$$(CPP) $$(CPPFLAGS) -P -D__ASSEMBLY__ -D__LINKER__ $(MAKE_DEP) -D$(IMAGE) -o $$@ $$<
+ $$(Q)$$(CPP) $$(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) -P -x assembler-with-cpp -D__LINKER__ $(MAKE_DEP) -D$(IMAGE) -o $$@ $$<
-include $(DEP)
MAP_DEVICE0,
MAP_DEVICE1,
ARM_MAP_NS_DRAM1,
-#ifdef AARCH64
+#ifdef __aarch64__
ARM_MAP_DRAM2,
#endif
#ifdef SPD_tspd
#endif
#ifdef IMAGE_BL32
const mmap_region_t plat_arm_mmap[] = {
-#ifdef AARCH32
+#ifndef __aarch64__
ARM_MAP_SHARED_RAM,
ARM_V2M_MAP_MEM_PROTECT,
#endif
#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
#endif
-#ifdef AARCH32
+#ifndef __aarch64__
/*
* Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifdef AARCH64
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifdef AARCH64
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifdef AARCH64
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
CSS_MAP_DEVICE,
SOC_CSS_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
-#ifdef AARCH64
+#ifdef __aarch64__
ARM_MAP_DRAM2,
#endif
#ifdef SPD_tspd
#endif
#ifdef IMAGE_BL32
const mmap_region_t plat_arm_mmap[] = {
-#ifdef AARCH32
+#ifndef __aarch64__
ARM_MAP_SHARED_RAM,
#ifdef PLAT_ARM_MEM_PROT_ADDR
ARM_V2M_MAP_MEM_PROTECT,
* space the physical & virtual address space limits are extended to
* 40-bits.
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
#else
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
-#ifndef AARCH32
+#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
#else
};
setup_page_tables(bl_regions, plat_arm_get_mmap());
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el3(0);
-#endif /* AARCH32 */
+#else
+ enable_mmu_svc_mon(0);
+#endif /* __aarch64__ */
arm_setup_romlib();
}
setup_page_tables(bl_regions, plat_arm_get_mmap());
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el3(0);
+#else
+ enable_mmu_svc_mon(0);
#endif
}
setup_page_tables(bl_regions, plat_arm_get_mmap());
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el1(0);
+#else
+ enable_mmu_svc_mon(0);
#endif
arm_setup_romlib();
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
#ifdef SPD_opteed
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
setup_page_tables(bl_regions, plat_arm_get_mmap());
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el1(0);
+#else
+ enable_mmu_svc_mon(0);
#endif
arm_setup_romlib();
}
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t arm_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
/*******************************************************************************
* Configures access to the system counter timer module.
* can use GIC system registers to manage interrupts and does
* not need GIC interface base addresses to be configured.
*/
-#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
- (defined(IMAGE_BL31) && !defined(AARCH32))
+#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
+ (defined(__aarch64__) && defined(IMAGE_BL31))
gicv3_driver_init(&arm_gic_data);
#endif
}
static mem_region_t arm_ram_ranges[] = {
{DRAM1_NS_IMAGE_LIMIT, DRAM1_PROTECTED_SIZE},
-#ifdef AARCH64
+#ifdef __aarch64__
{ARM_DRAM2_BASE, 1u << ONE_GB_SHIFT},
#endif
};
(ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
return 0;
}
-#ifndef AARCH32
+#ifdef __aarch64__
if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint <
(ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) {
return 0;
void *handle)
{
/* Execution state can be switched only if EL3 is AArch64 */
-#ifdef AARCH64
+#ifdef __aarch64__
bool caller_64, thumb = false, from_el2;
unsigned int el, endianness;
u_register_t spsr, pc, scr, sctlr;
SMC_RET1(handle, STATE_SW_E_PARAM);
exec_denied:
-#endif
+#endif /* __aarch64__ */
/* State switch denied */
SMC_RET1(handle, STATE_SW_E_DENIED);
}
/* Platform ID address */
#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* SSC_VERSION related accessors */
/* Returns the part number of the platform */
#define GET_SGI_PART_NUM \
/* Returns the configuration number of the platform */
#define GET_SGI_CONFIG_NUM \
GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/*******************************************************************************
* Memprotect definitions
/* Platform ID address */
#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* SSC_VERSION related accessors */
/* Returns the part number of the platform */
#define GET_PLAT_PART_NUM \
/* Returns the configuration number of the platform */
#define GET_PLAT_CONFIG_NUM \
GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/*************************************************************************
#pragma weak plat_ic_end_of_interrupt
/* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */
-#ifdef AARCH32
+#ifndef __aarch64__
#define IS_IN_EL1() IS_IN_SECURE()
#endif
#define MHZ_TICKS_PER_SEC 1000000U
/* Maximum time-stamp value read from architectural counters */
-#ifdef AARCH32
-#define MAX_TS UINT32_MAX
-#else
+#ifdef __aarch64__
#define MAX_TS UINT64_MAX
+#else
+#define MAX_TS UINT32_MAX
#endif
/* Following are used as ID's to capture time-stamp */
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t hikey_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
int hikey_bl2_handle_post_image_load(unsigned int image_id)
{
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
#ifdef SPD_opteed
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
#endif
/* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
#ifdef SPD_none
#undef BL32_BASE
#endif /* SPD_none */
#ifndef HISI_PWRC_H
#define HISI_PWRC_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void hisi_pwrc_set_cluster_wfi(unsigned int id);
void hisi_pwrc_set_core_bx_addr(unsigned int core,
unsigned int cluster);
int hisi_pwrc_setup(void);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* HISI_PWRC_H */
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t hikey960_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
int hikey960_bl2_handle_post_image_load(unsigned int image_id)
{
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
#ifdef SPD_opteed
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
#endif
/* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
#ifdef SPD_none
#undef BL32_BASE
#endif /* SPD_none */
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t poplar_get_spsr_for_bl33_entry(void)
{
unsigned long el_status;
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
int poplar_bl2_handle_post_image_load(unsigned int image_id)
{
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
#ifdef SPD_opteed
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
#endif
/* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
#ifdef SPD_none
#undef BL32_BASE
#endif /* SPD_none */
#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
#define LPUART_BAUD_M10_MASK (0x20000000U)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int console_lpuart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_lpuart_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* IMX8_LPUART_H */
#include <drivers/console.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
typedef struct {
console_t console;
int console_imx_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_uart_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* IMX_UART_H */
const mmap_region_t plat_agilex_mmap[] = {
MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
- MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
MT_NON_CACHEABLE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
#define CONSOLE_T_16550_BASE CONSOLE_T_DRVDATA
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int console_ls_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_ls_16550_t *console);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* LS_16550_H */
#endif
);
VERBOSE("After setup the page tables\n");
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el3(0);
-#endif /* AARCH32 */
+#else
+ enable_mmu_svc_mon(0);
+#endif /* __aarch64__ */
VERBOSE("After MMU enabled\n");
}
#endif
);
-#ifdef AARCH32
- enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
enable_mmu_el1(0);
+#else
+ enable_mmu_svc_mon(0);
#endif
}
assert(bl_mem_params);
switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
case BL32_IMAGE_ID:
bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry();
break;
/*******************************************************************************
* Gets SPSR for BL33 entry
******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
uint32_t ls_get_spsr_for_bl33_entry(void)
{
unsigned int mode;
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
/*******************************************************************************
* Returns Layerscape platform specific memory map regions.
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdio.h>
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#include <board_marvell_def.h>
#include <mvebu_def.h>
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdio.h>
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#include <common/interrupt_props.h>
#include <drivers/arm/gic_common.h>
#define CCI_CLK_CTRL (MCUCFG_BASE + 0x660)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <plat/common/common_def.h>
#include <stdint.h>
void cci_init_sf(void);
unsigned long cci_reg_access(unsigned int op, unsigned long offset, unsigned long val);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* MCSI_H */
#include <tegra_def.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <lib/mmio.h>
#include <stdint.h>
******************************************************************************/
void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* MEMCTRL_V2_H */
#define TEGRA_CHIPID_TEGRA21 U(0x21)
#define TEGRA_CHIPID_TEGRA18 U(0x18)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/*
* Tegra chip ID major/minor identifiers
bool tegra_platform_is_unit_fpga(void);
bool tegra_platform_is_virt_dev_kit(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TEGRA_PLATFORM_H */
* does basic initialization. Later architectural setup (bl1_arch_setup())
* does not do anything platform specific.
*****************************************************************************/
-#ifdef AARCH32
-#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
-#else
+#ifdef __aarch64__
#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
#endif
void bl1_plat_arch_setup(void)
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#else /* EL3_PAYLOAD_BASE */
-#ifdef AARCH64
+#ifdef __aarch64__
/* Fill BL31 related information */
{ .image_id = BL31_IMAGE_ID,
.next_handoff_image_id = BL33_IMAGE_ID,
# endif
},
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
# ifdef QEMU_LOAD_BL32
-#ifdef AARCH64
+#ifdef __aarch64__
#define BL32_EP_ATTRIBS (SECURE | EXECUTABLE)
#define BL32_IMG_ATTRIBS 0
#else
/* TODO Initialize timer */
}
-#ifdef AARCH32
-#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
-#else
+#ifdef __aarch64__
#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
#endif
void bl2_plat_arch_setup(void)
******************************************************************************/
static uint32_t qemu_get_spsr_for_bl32_entry(void)
{
-#ifdef AARCH64
+#ifdef __aarch64__
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL3-2 image.
static uint32_t qemu_get_spsr_for_bl33_entry(void)
{
uint32_t spsr;
-#ifdef AARCH64
+#ifdef __aarch64__
unsigned int mode;
/* Figure out what mode we enter the non-secure world in */
}
/* Define EL1 and EL3 variants of the function initialising the MMU */
-#ifdef AARCH32
-DEFINE_CONFIGURE_MMU_EL(svc_mon)
-#else
+#ifdef __aarch64__
DEFINE_CONFIGURE_MMU_EL(el1)
DEFINE_CONFIGURE_MMU_EL(el3)
+#else
+DEFINE_CONFIGURE_MMU_EL(svc_mon)
#endif
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdlib.h>
#endif
#ifndef PLAT_PRIVATE_H
#define PLAT_PRIVATE_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
/******************************************************************************
* Function and variable prototypes
*****************************************************************************/
-#ifdef AARCH32
-void plat_configure_mmu_svc_mon(unsigned long total_base,
- unsigned long total_size,
- unsigned long,
- unsigned long,
- unsigned long,
- unsigned long);
-
-void rockchip_plat_mmu_svc_mon(void);
-#else
+#ifdef __aarch64__
void plat_configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long,
unsigned long);
void rockchip_plat_mmu_el3(void);
+#else
+void plat_configure_mmu_svc_mon(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long,
+ unsigned long,
+ unsigned long,
+ unsigned long);
+
+void rockchip_plat_mmu_svc_mon(void);
#endif
void plat_cci_init(void);
uint32_t rockchip_get_uart_base(void);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/******************************************************************************
* cpu up status
#define PM_WARM_BOOT_SHT 0
#define PM_WARM_BOOT_BIT (1 << PM_WARM_BOOT_SHT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct psram_data_t {
uint64_t sp;
extern void *sys_sleep_flag_sram;
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif
{
void *from_bl2;
- from_bl2 = (void *) arg0;
+ from_bl2 = (void *)arg0;
bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
/* Enable and initialize the System level generic timer */
mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
- CNTCR_FCREQ(0U) | CNTCR_EN);
+ CNTCR_FCREQ(0U) | CNTCR_EN);
}
void bl31_plat_arch_setup(void)
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* SGI0 */
INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI6 */
INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* G1S interrupts */
/* Timer */
INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_LEVEL),
+ GIC_INTR_CFG_LEVEL),
/* SGI1 */
INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI2 */
INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI3 */
INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI4 */
INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI5 */
INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE),
+ GIC_INTR_CFG_EDGE),
/* SGI7 */
INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
- GIC_INTR_CFG_EDGE)
+ GIC_INTR_CFG_EDGE)
};
static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
assert(image_id < ARRAY_SIZE(uniphier_io_policies));
- *dev_handle = *(uniphier_io_policies[image_id].dev_handle);
+ *dev_handle = *uniphier_io_policies[image_id].dev_handle;
*image_spec = uniphier_io_policies[image_id].image_spec;
init_params = uniphier_io_policies[image_id].init_params;
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "uniphier.h"
-#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-
#define NAND_CMD_READ0 0
#define NAND_CMD_READSTART 0x30
int pages_per_block = nand->pages_per_block;
int page_size = nand->page_size;
int blocks_to_skip = lba / pages_per_block;
- int pages_to_read = DIV_ROUND_UP(size, page_size);
+ int pages_to_read = div_round_up(size, page_size);
int page = lba % pages_per_block;
int block = 0;
uintptr_t p = buf;
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define UNIPHIER_ROM_RSV0 0x59801200
#define UNIPHIER_SLFRSTSEL 0x61843010
-#define UNIPHIER_SLFRSTSEL_MASK (0x3 << 0)
+#define UNIPHIER_SLFRSTSEL_MASK GENMASK(1, 0)
#define UNIPHIER_SLFRSTCTL 0x61843014
-#define UNIPHIER_SLFRSTCTL_RST (1 << 0)
+#define UNIPHIER_SLFRSTCTL_RST BIT(0)
#define MPIDR_AFFINITY_INVALID ((u_register_t)-1)
const psci_power_state_t *target_state)
{
/*
- * The Boot ROM cannot distinguish warn and cold resets.
+ * The Boot ROM cannot distinguish warm and cold resets.
* Instead of the CPU reset, fake it.
*/
uniphier_holding_pen_release = MPIDR_AFFINITY_INVALID;
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <drivers/st/stm32mp1_clk.h>
#include <boot_api.h>
#endif
/* DDR power initializations */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
enum ddr_type {
STM32MP_DDR3,
STM32MP_LPDDR2,
#define TAMP_BASE U(0x5C00A000)
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
-#if !(defined(__LINKER__) || defined(__ASSEMBLY__))
+#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
static inline uint32_t tamp_bkpr(uint32_t idx)
{
return TAMP_BKP_REGISTER_BASE + (idx << 2);
#define OPTEED_C_RT_CTX_SIZE 0x60
#define OPTEED_C_RT_CTX_ENTRIES (OPTEED_C_RT_CTX_SIZE >> DWORD_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
extern optee_context_t opteed_sp_context[OPTEED_CORE_COUNT];
extern uint32_t opteed_rw;
extern struct optee_vectors *optee_vector_table;
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* OPTEED_PRIVATE_H */
#define TLKD_C_RT_CTX_SIZE 0x60
#define TLKD_C_RT_CTX_ENTRIES (TLKD_C_RT_CTX_SIZE >> DWORD_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
uint64_t pc,
tlk_context_t *tlk_ctx);
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* TLKD_PRIVATE_H */
#define TSPD_SP_CTX_SIZE 0x90
#define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT];
extern tsp_vectors_t *tsp_vectors;
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLER__*/
#endif /* TSPD_PRIVATE_H */
#include <services/sdei.h>
#include <setjmp.h>
-#ifdef AARCH32
+#ifndef __aarch64__
# error SDEI is implemented only for AArch64 systems
#endif
/* Value returned by spm_sp_synchronous_entry() when a partition is preempted */
#define SPM_SECURE_PARTITION_PREEMPTED U(0x1234)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
int spm_response_get(uint16_t client_id, uint16_t handle, uint32_t token,
u_register_t *x1, u_register_t *x2, u_register_t *x3);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SPM_PRIVATE_H */
#define SP_C_RT_CTX_SIZE 0x60
#define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <stdint.h>
u_register_t pages_count,
u_register_t smc_attributes);
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* SPM_PRIVATE_H */
projects / project / bcm63xx / atf.git / commitdiff