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| author | Lech Perczak | 2023-12-11 23:25:02 +0000 |
|---|---|---|
| committer | Lech Perczak | 2024-01-04 21:29:11 +0000 |
| commit | b80c17b093dc5b9919b1163b2eefc94a5d96dc75 (patch) | |
| tree | 7d1d82f844c288740279f0f70b7744529aaa2ad0 | |
| parent | 0c84a1528894b1ce9b377a78199591c82e1acea5 (diff) | |
| download | openwrt-b80c17b093dc5b9919b1163b2eefc94a5d96dc75.tar.gz | |
ramips: dts: rt5350: reset FE and ESW cores together
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.
Fixes: #9284
Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit fc92fecfc7ddf19bbfd7d1305a29c666f00543af)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
| -rw-r--r-- | target/linux/ramips/dts/rt5350.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ramips/dts/rt5350.dtsi b/target/linux/ramips/dts/rt5350.dtsi index 090e755743..fe43de87ca 100644 --- a/target/linux/ramips/dts/rt5350.dtsi +++ b/target/linux/ramips/dts/rt5350.dtsi @@ -343,8 +343,8 @@ compatible = "ralink,rt5350-eth"; reg = <0x10100000 0x10000>; - resets = <&rstctrl 21>; - reset-names = "fe"; + resets = <&rstctrl 21>, <&rstctrl 23>; + reset-names = "fe", "esw"; interrupt-parent = <&cpuintc>; interrupts = <5>; @@ -356,8 +356,8 @@ compatible = "ralink,rt5350-esw", "ralink,rt3050-esw"; reg = <0x10110000 0x8000>; - resets = <&rstctrl 23 &rstctrl 24>; - reset-names = "esw", "ephy"; + resets = <&rstctrl 24>; + reset-names = "ephy"; interrupt-parent = <&intc>; interrupts = <17>; |