diff options
| author | Goetz Goerisch | 2026-05-23 15:23:54 +0000 |
|---|---|---|
| committer | Hauke Mehrtens | 2026-05-25 22:04:37 +0000 |
| commit | ca4a3dde42b97f948304f489352f1c1049d2b6bd (patch) | |
| tree | f797a5b88a3910053459ec6e7d149a60cbf7ea8f | |
| parent | b3e40122a36e384c6cb4396b6ac2c2316543c193 (diff) | |
| download | openwrt-ca4a3dde42b97f948304f489352f1c1049d2b6bd.tar.gz | |
kernel: bump 6.6 to 6.6.141
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.141
Drop upstreamed patches:
generic/backport-6.6/702-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch [1]
generic/backport-6.6/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch [2]
Manually refreshed patches:
generic/backport-6.6/707-v6.8-02-net-phy-at803x-move-disable-WOL-to-specific-at8031-p.patch
generic/backport-6.6/707-v6.8-03-net-phy-at803x-raname-hw_stats-functions-to-qca83xx-.patch
generic/backport-6.6/707-v6.8-04-net-phy-at803x-move-qca83xx-specific-check-in-dedica.patch
generic/backport-6.6/707-v6.8-05-net-phy-at803x-move-specific-DT-option-for-at8031-to.patch
generic/backport-6.6/707-v6.8-06-net-phy-at803x-move-specific-at8031-probe-mode-check.patch
generic/backport-6.6/707-v6.8-07-net-phy-at803x-move-specific-at8031-config_init-to-d.patch
generic/backport-6.6/707-v6.8-08-net-phy-at803x-move-specific-at8031-WOL-bits-to-dedi.patch
generic/backport-6.6/707-v6.8-09-net-phy-at803x-move-specific-at8031-config_intr-to-d.patch
generic/backport-6.6/707-v6.8-10-net-phy-at803x-make-at8031-related-DT-functions-name.patch
generic/backport-6.6/707-v6.8-11-net-phy-at803x-move-at8031-functions-in-dedicated-se.patch
generic/backport-6.6/707-v6.8-12-net-phy-at803x-move-at8035-specific-DT-parse-to-dedi.patch
generic/backport-6.6/707-v6.8-13-net-phy-at803x-drop-specific-PHY-ID-check-from-cable.patch
generic/backport-6.6/708-v6.8-01-net-phy-at803x-move-specific-qca808x-config_aneg-to-.patch
generic/backport-6.6/708-v6.8-02-net-phy-at803x-make-read-specific-status-function-mo.patch
generic/backport-6.6/709-v6.8-01-net-phy-at803x-remove-extra-space-after-cast.patch
generic/backport-6.6/709-v6.8-02-net-phy-at803x-replace-msleep-1-with-usleep_range.patch
generic/backport-6.6/710-v6.8-net-phy-at803x-better-align-function-varibles-to-ope.patch
generic/backport-6.6/711-v6.8-01-net-phy-at803x-generalize-cdt-fault-length-function.patch
generic/backport-6.6/711-v6.8-02-net-phy-at803x-refactor-qca808x-cable-test-get-statu.patch
generic/backport-6.6/711-v6.8-03-net-phy-at803x-add-support-for-cdt-cross-short-test-.patch
generic/backport-6.6/711-v6.8-04-net-phy-at803x-make-read_status-more-generic.patch
generic/backport-6.6/712-v6.9-net-phy-at803x-add-LED-support-for-qca808x.patch
updated file path for all due to [2]
generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch [3]
bcm27xx/patches-6.6/950-0158-bcmgenet-Better-coalescing-parameter-defaults.patch [4]
All other patches autorefreshed.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.141&id=014860036d1ffe2e84e4b612fb0b9aab2fa38e67
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.141&id=22f22f1346b4add431b509a64bfb3f8cf3daa8c3
[3] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.141&id=989214c66884d70716d83dc1d0bf5e16287bf349
[4] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.141&id=355b61569e84c9ac171d36878bd9cd503cac7e2c
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23435
[Add SKBFL_SHARED_FRAG to skb_gro_receive_list() again]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
96 files changed, 168 insertions, 8149 deletions
diff --git a/include/kernel-6.6 b/include/kernel-6.6 index 3e4a27c806..207a3bc528 100644 --- a/include/kernel-6.6 +++ b/include/kernel-6.6 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.6 = .140 -LINUX_KERNEL_HASH-6.6.140 = d67c9674a2d4307f3747183935a5d434391df0fc5f5bf0e00691e059f664b7db +LINUX_VERSION-6.6 = .141 +LINUX_KERNEL_HASH-6.6.141 = 3bc2652eb62ab90a90a8b0aa156b91d276f92eb84702971df62fe1a3f1eb7fe1 diff --git a/target/linux/airoha/patches-6.6/034-v6.13-pinctrl-airoha-Add-support-for-EN7581-SoC.patch b/target/linux/airoha/patches-6.6/034-v6.13-pinctrl-airoha-Add-support-for-EN7581-SoC.patch index a7d38881ed..1538997746 100644 --- a/target/linux/airoha/patches-6.6/034-v6.13-pinctrl-airoha-Add-support-for-EN7581-SoC.patch +++ b/target/linux/airoha/patches-6.6/034-v6.13-pinctrl-airoha-Add-support-for-EN7581-SoC.patch @@ -29,7 +29,7 @@ Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -16872,6 +16872,13 @@ F: drivers/pinctrl/ +@@ -16880,6 +16880,13 @@ F: drivers/pinctrl/ F: include/dt-bindings/pinctrl/ F: include/linux/pinctrl/ diff --git a/target/linux/airoha/patches-6.6/060-v6.16-02-net-phy-mediatek-add-Airoha-PHY-ID-to-SoC-driver.patch b/target/linux/airoha/patches-6.6/060-v6.16-02-net-phy-mediatek-add-Airoha-PHY-ID-to-SoC-driver.patch index 03bb46bb89..e33f069581 100644 --- a/target/linux/airoha/patches-6.6/060-v6.16-02-net-phy-mediatek-add-Airoha-PHY-ID-to-SoC-driver.patch +++ b/target/linux/airoha/patches-6.6/060-v6.16-02-net-phy-mediatek-add-Airoha-PHY-ID-to-SoC-driver.patch @@ -22,7 +22,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org> --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -320,8 +320,9 @@ config MEDIATEK_GE_PHY +@@ -328,8 +328,9 @@ config MEDIATEK_GE_PHY config MEDIATEK_GE_SOC_PHY tristate "MediaTek SoC Ethernet PHYs" diff --git a/target/linux/bcm27xx/patches-6.6/950-0142-MAINTAINERS-Add-entry-for-BCM2835-Unicam-driver.patch b/target/linux/bcm27xx/patches-6.6/950-0142-MAINTAINERS-Add-entry-for-BCM2835-Unicam-driver.patch index 6bbe158074..213b3d0a3f 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0142-MAINTAINERS-Add-entry-for-BCM2835-Unicam-driver.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0142-MAINTAINERS-Add-entry-for-BCM2835-Unicam-driver.patch @@ -12,7 +12,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -3916,6 +3916,13 @@ N: bcm113* +@@ -3924,6 +3924,13 @@ N: bcm113* N: bcm216* N: kona diff --git a/target/linux/bcm27xx/patches-6.6/950-0157-bcmgenet-constrain-max-DMA-burst-length.patch b/target/linux/bcm27xx/patches-6.6/950-0157-bcmgenet-constrain-max-DMA-burst-length.patch index 64550cf47d..bca1ed13a8 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0157-bcmgenet-constrain-max-DMA-burst-length.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0157-bcmgenet-constrain-max-DMA-burst-length.patch @@ -9,7 +9,7 @@ Subject: [PATCH 0157/1085] bcmgenet: constrain max DMA burst length --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.h +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.h -@@ -31,7 +31,7 @@ +@@ -34,7 +34,7 @@ #define ENET_PAD 8 #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) diff --git a/target/linux/bcm27xx/patches-6.6/950-0158-bcmgenet-Better-coalescing-parameter-defaults.patch b/target/linux/bcm27xx/patches-6.6/950-0158-bcmgenet-Better-coalescing-parameter-defaults.patch index 52f1863822..18996c2fe5 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0158-bcmgenet-Better-coalescing-parameter-defaults.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0158-bcmgenet-Better-coalescing-parameter-defaults.patch @@ -18,7 +18,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org> --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c -@@ -2666,7 +2666,7 @@ static void bcmgenet_init_tx_ring(struct +@@ -2684,7 +2684,7 @@ static void bcmgenet_init_tx_ring(struct bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); @@ -27,17 +27,16 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org> /* Disable rate control for now */ bcmgenet_tdma_ring_writel(priv, index, flow_period_val, TDMA_FLOW_PERIOD); -@@ -4161,9 +4161,12 @@ static int bcmgenet_probe(struct platfor +@@ -4083,9 +4083,10 @@ static int bcmgenet_probe(struct platfor netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); /* Set default coalescing parameters */ -- for (i = 0; i < priv->hw_params->rx_queues; i++) -+ for (i = 0; i < priv->hw_params->rx_queues; i++) { +- for (i = 0; i <= priv->hw_params->rx_queues; i++) ++ for (i = 0; i <= priv->hw_params->rx_queues; i++) { priv->rx_rings[i].rx_max_coalesced_frames = 1; +- + priv->rx_rings[i].rx_coalesce_usecs = 50; + } - priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; -+ priv->rx_rings[DESC_INDEX].rx_coalesce_usecs = 50; - - /* libphy will determine the link state */ - netif_carrier_off(dev); + /* Initialize u64 stats seq counter for 32bit machines */ + for (i = 0; i <= priv->hw_params->rx_queues; i++) + u64_stats_init(&priv->rx_rings[i].stats64.syncp); diff --git a/target/linux/bcm27xx/patches-6.6/950-0167-drm-v3d-Clock-V3D-down-when-not-in-use.patch b/target/linux/bcm27xx/patches-6.6/950-0167-drm-v3d-Clock-V3D-down-when-not-in-use.patch index 890fe7ea0d..fab52c63d0 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0167-drm-v3d-Clock-V3D-down-when-not-in-use.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0167-drm-v3d-Clock-V3D-down-when-not-in-use.patch @@ -155,7 +155,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org> kref_init(&job->refcount); return 0; -@@ -1033,6 +1079,9 @@ v3d_gem_init(struct drm_device *dev) +@@ -1038,6 +1084,9 @@ v3d_gem_init(struct drm_device *dev) if (ret) return ret; diff --git a/target/linux/bcm27xx/patches-6.6/950-0170-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch b/target/linux/bcm27xx/patches-6.6/950-0170-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch index e166911156..64873a3c5f 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0170-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0170-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch @@ -27,7 +27,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org> --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c -@@ -67,6 +67,9 @@ +@@ -65,6 +65,9 @@ /* Forward declarations */ static void bcmgenet_set_rx_mode(struct net_device *dev); @@ -37,7 +37,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org> static inline void bcmgenet_writel(u32 value, void __iomem *offset) { -@@ -2495,6 +2498,11 @@ static void reset_umac(struct bcmgenet_p +@@ -2522,6 +2525,11 @@ static void reset_umac(struct bcmgenet_p bcmgenet_rbuf_ctrl_set(priv, 0); udelay(10); diff --git a/target/linux/bcm27xx/patches-6.6/950-0173-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch b/target/linux/bcm27xx/patches-6.6/950-0173-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch index 08ba072318..6a2c271e36 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0173-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0173-media-i2c-imx477-Support-for-the-Sony-IMX477-sensor.patch @@ -343,7 +343,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com> +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20059,6 +20059,14 @@ T: git git://linuxtv.org/media_tree.git +@@ -20067,6 +20067,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml F: drivers/media/i2c/imx415.c diff --git a/target/linux/bcm27xx/patches-6.6/950-0174-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch b/target/linux/bcm27xx/patches-6.6/950-0174-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch index 240c63509c..fd625e4833 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0174-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0174-media-i2c-imx519-Support-for-the-Sony-IMX519-sensor.patch @@ -177,7 +177,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20067,6 +20067,14 @@ T: git git://linuxtv.org/media_tree.git +@@ -20075,6 +20075,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/imx477.yaml F: drivers/media/i2c/imx477.c diff --git a/target/linux/bcm27xx/patches-6.6/950-0175-Documentation-devicetree-Add-documentation-for-imx37.patch b/target/linux/bcm27xx/patches-6.6/950-0175-Documentation-devicetree-Add-documentation-for-imx37.patch index 3af5c0e95c..933cf60517 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0175-Documentation-devicetree-Add-documentation-for-imx37.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0175-Documentation-devicetree-Add-documentation-for-imx37.patch @@ -132,7 +132,7 @@ Signed-off-by: David Plowman <david.plowman@raspberrypi.com> +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20064,6 +20064,7 @@ M: Raspberry Pi Kernel Maintenance <kern +@@ -20072,6 +20072,7 @@ M: Raspberry Pi Kernel Maintenance <kern L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git diff --git a/target/linux/bcm27xx/patches-6.6/950-0188-v3d_gem-Kick-the-clock-so-firmware-knows-we-are-usin.patch b/target/linux/bcm27xx/patches-6.6/950-0188-v3d_gem-Kick-the-clock-so-firmware-knows-we-are-usin.patch index 7850e796fc..e85ae68ba4 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0188-v3d_gem-Kick-the-clock-so-firmware-knows-we-are-usin.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0188-v3d_gem-Kick-the-clock-so-firmware-knows-we-are-usin.patch @@ -14,7 +14,7 @@ Signed-off-by: popcornmix <popcornmix@gmail.com> --- a/drivers/gpu/drm/v3d/v3d_gem.c +++ b/drivers/gpu/drm/v3d/v3d_gem.c -@@ -1082,6 +1082,10 @@ v3d_gem_init(struct drm_device *dev) +@@ -1087,6 +1087,10 @@ v3d_gem_init(struct drm_device *dev) mutex_init(&v3d->clk_lock); INIT_DELAYED_WORK(&v3d->clk_down_work, v3d_clock_down_work); diff --git a/target/linux/bcm27xx/patches-6.6/950-0199-bcmgenet-Disable-skip_umac_reset-by-default.patch b/target/linux/bcm27xx/patches-6.6/950-0199-bcmgenet-Disable-skip_umac_reset-by-default.patch index 05909e4e43..7a6d2e42fe 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0199-bcmgenet-Disable-skip_umac_reset-by-default.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0199-bcmgenet-Disable-skip_umac_reset-by-default.patch @@ -12,7 +12,7 @@ Signed-off-by: popcornmix <popcornmix@gmail.com> --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c -@@ -67,7 +67,7 @@ +@@ -65,7 +65,7 @@ /* Forward declarations */ static void bcmgenet_set_rx_mode(struct net_device *dev); diff --git a/target/linux/bcm27xx/patches-6.6/950-0201-media-dt-bindings-media-Add-binding-for-the-Raspberr.patch b/target/linux/bcm27xx/patches-6.6/950-0201-media-dt-bindings-media-Add-binding-for-the-Raspberr.patch index 4f4ba7db94..70671feadf 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0201-media-dt-bindings-media-Add-binding-for-the-Raspberr.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0201-media-dt-bindings-media-Add-binding-for-the-Raspberr.patch @@ -90,7 +90,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -3916,6 +3916,13 @@ N: bcm113* +@@ -3924,6 +3924,13 @@ N: bcm113* N: bcm216* N: kona diff --git a/target/linux/bcm27xx/patches-6.6/950-0221-media-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-int.patch b/target/linux/bcm27xx/patches-6.6/950-0221-media-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-int.patch index dfbacd893d..037cccc78c 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0221-media-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-int.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0221-media-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-int.patch @@ -31,7 +31,7 @@ Reported-by: kbuild test robot <lkp@intel.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -3928,7 +3928,7 @@ M: Dave Stevenson <dave.stevenson@raspbe +@@ -3936,7 +3936,7 @@ M: Dave Stevenson <dave.stevenson@raspbe L: linux-media@vger.kernel.org S: Maintained F: drivers/media/platform/bcm2835/ diff --git a/target/linux/bcm27xx/patches-6.6/950-0222-media-bcm2835-unicam-Kconfig-Makefile-for-CCP2-CSI2-.patch b/target/linux/bcm27xx/patches-6.6/950-0222-media-bcm2835-unicam-Kconfig-Makefile-for-CCP2-CSI2-.patch index af5500003e..3c4a631cfd 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0222-media-bcm2835-unicam-Kconfig-Makefile-for-CCP2-CSI2-.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0222-media-bcm2835-unicam-Kconfig-Makefile-for-CCP2-CSI2-.patch @@ -14,7 +14,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -3924,7 +3924,7 @@ F: Documentation/devicetree/bindings/med +@@ -3932,7 +3932,7 @@ F: Documentation/devicetree/bindings/med F: drivers/staging/media/rpivid BROADCOM BCM2835 CAMERA DRIVER diff --git a/target/linux/bcm27xx/patches-6.6/950-0254-staging-vc04_services-ISP-Add-a-more-complex-ISP-pro.patch b/target/linux/bcm27xx/patches-6.6/950-0254-staging-vc04_services-ISP-Add-a-more-complex-ISP-pro.patch index de67b75bf5..b2e15d24f6 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0254-staging-vc04_services-ISP-Add-a-more-complex-ISP-pro.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0254-staging-vc04_services-ISP-Add-a-more-complex-ISP-pro.patch @@ -35,7 +35,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -3930,6 +3930,15 @@ S: Maintained +@@ -3938,6 +3938,15 @@ S: Maintained F: drivers/media/platform/bcm2835/ F: Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml diff --git a/target/linux/bcm27xx/patches-6.6/950-0400-net-bcmgenet-Add-eee-module-parameter.patch b/target/linux/bcm27xx/patches-6.6/950-0400-net-bcmgenet-Add-eee-module-parameter.patch index 2bd0f66c8c..dd65f3edb7 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0400-net-bcmgenet-Add-eee-module-parameter.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0400-net-bcmgenet-Add-eee-module-parameter.patch @@ -16,7 +16,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c -@@ -70,6 +70,9 @@ static void bcmgenet_set_rx_mode(struct +@@ -68,6 +68,9 @@ static void bcmgenet_set_rx_mode(struct static bool skip_umac_reset = false; module_param(skip_umac_reset, bool, 0444); MODULE_PARM_DESC(skip_umac_reset, "Skip UMAC reset step"); @@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> static inline void bcmgenet_writel(u32 value, void __iomem *offset) { -@@ -3449,6 +3452,17 @@ static int bcmgenet_open(struct net_devi +@@ -3369,6 +3372,17 @@ static int bcmgenet_open(struct net_devi bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause); diff --git a/target/linux/bcm27xx/patches-6.6/950-0407-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch b/target/linux/bcm27xx/patches-6.6/950-0407-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch index 986922d799..c694d1bcdc 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0407-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0407-dtbindings-media-i2c-Add-IMX708-CMOS-sensor-binding.patch @@ -138,7 +138,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20108,6 +20108,14 @@ T: git git://linuxtv.org/media_tree.git +@@ -20116,6 +20116,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/imx519.yaml F: drivers/media/i2c/imx519.c diff --git a/target/linux/bcm27xx/patches-6.6/950-0434-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch b/target/linux/bcm27xx/patches-6.6/950-0434-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch index f3d68c4546..86fc9f2c63 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0434-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0434-dt-bindings-media-i2c-Replace-IMX708-sensor-binding-.patch @@ -271,7 +271,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com> +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20113,7 +20113,7 @@ M: Raspberry Pi Kernel Maintenance <kern +@@ -20121,7 +20121,7 @@ M: Raspberry Pi Kernel Maintenance <kern L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git diff --git a/target/linux/bcm27xx/patches-6.6/950-0460-dt-bindings-media-imx258-Rename-to-include-vendor-pr.patch b/target/linux/bcm27xx/patches-6.6/950-0460-dt-bindings-media-imx258-Rename-to-include-vendor-pr.patch index 50ae214755..57079cb207 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0460-dt-bindings-media-imx258-Rename-to-include-vendor-pr.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0460-dt-bindings-media-imx258-Rename-to-include-vendor-pr.patch @@ -291,7 +291,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> + }; --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20014,7 +20014,7 @@ M: Sakari Ailus <sakari.ailus@linux.inte +@@ -20022,7 +20022,7 @@ M: Sakari Ailus <sakari.ailus@linux.inte L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git diff --git a/target/linux/bcm27xx/patches-6.6/950-0767-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch b/target/linux/bcm27xx/patches-6.6/950-0767-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch index 607954b209..50258b8d1a 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0767-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0767-media-dt-bindings-i2c-Add-Rohm-BU64754-bindings.patch @@ -67,7 +67,7 @@ Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -18621,6 +18621,13 @@ S: Supported +@@ -18629,6 +18629,13 @@ S: Supported F: drivers/iio/light/rohm-bu27008.c F: drivers/iio/light/rohm-bu27034.c diff --git a/target/linux/bcm27xx/patches-6.6/950-0768-media-i2c-Add-driver-for-OmniVision-OV64A40.patch b/target/linux/bcm27xx/patches-6.6/950-0768-media-i2c-Add-driver-for-OmniVision-OV64A40.patch index 6075a9d5e7..527e877deb 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0768-media-i2c-Add-driver-for-OmniVision-OV64A40.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0768-media-i2c-Add-driver-for-OmniVision-OV64A40.patch @@ -16,7 +16,7 @@ Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -15873,6 +15873,14 @@ S: Maintained +@@ -15881,6 +15881,14 @@ S: Maintained T: git git://linuxtv.org/media_tree.git F: drivers/media/i2c/ov5695.c diff --git a/target/linux/bcm27xx/patches-6.6/950-1047-dw-axi-dmac-platform-Avoid-trampling-with-zero-lengt.patch b/target/linux/bcm27xx/patches-6.6/950-1047-dw-axi-dmac-platform-Avoid-trampling-with-zero-lengt.patch index d7d4ca6172..f903c5c670 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1047-dw-axi-dmac-platform-Avoid-trampling-with-zero-lengt.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1047-dw-axi-dmac-platform-Avoid-trampling-with-zero-lengt.patch @@ -22,7 +22,7 @@ Signed-off-by: Dom Cobley <popcornmix@gmail.com> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c -@@ -834,6 +834,9 @@ dw_axi_dma_chan_prep_slave_sg(struct dma +@@ -832,6 +832,9 @@ dw_axi_dma_chan_prep_slave_sg(struct dma mem = sg_dma_address(sg); len = sg_dma_len(sg); num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); diff --git a/target/linux/bcm27xx/patches-6.6/950-1128-pwm-Make-it-possible-to-apply-PWM-changes-in-atomic-.patch b/target/linux/bcm27xx/patches-6.6/950-1128-pwm-Make-it-possible-to-apply-PWM-changes-in-atomic-.patch index 3377683128..2040eba85f 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1128-pwm-Make-it-possible-to-apply-PWM-changes-in-atomic-.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1128-pwm-Make-it-possible-to-apply-PWM-changes-in-atomic-.patch @@ -48,7 +48,7 @@ Signed-off-by: Thierry Reding <thierry.reding@gmail.com> drivers cannot. If you rely on getting the inactive state, use .duty_cycle=0, --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -17439,7 +17439,7 @@ F: drivers/video/backlight/pwm_bl.c +@@ -17447,7 +17447,7 @@ F: drivers/video/backlight/pwm_bl.c F: include/dt-bindings/pwm/ F: include/linux/pwm.h F: include/linux/pwm_backlight.h diff --git a/target/linux/bcm27xx/patches-6.6/950-1144-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch b/target/linux/bcm27xx/patches-6.6/950-1144-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch index ad364196e9..d2f1a1fe02 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1144-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1144-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch @@ -218,7 +218,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> return; } -@@ -625,18 +701,25 @@ static int dw_axi_dma_set_hw_desc(struct +@@ -623,18 +699,25 @@ static int dw_axi_dma_set_hw_desc(struct switch (chan->direction) { case DMA_MEM_TO_DEV: reg_width = __ffs(chan->config.dst_addr_width); @@ -246,7 +246,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; block_ts = len >> reg_width; -@@ -672,9 +755,6 @@ static int dw_axi_dma_set_hw_desc(struct +@@ -670,9 +753,6 @@ static int dw_axi_dma_set_hw_desc(struct } hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); @@ -256,7 +256,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> hw_desc->lli->ctl_lo = cpu_to_le32(ctllo); set_desc_src_master(hw_desc); -@@ -769,6 +849,8 @@ dw_axi_dma_chan_prep_cyclic(struct dma_c +@@ -767,6 +847,8 @@ dw_axi_dma_chan_prep_cyclic(struct dma_c src_addr += segment_len; } @@ -265,7 +265,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> llp = desc->hw_desc[0].llp; /* Managed transfer list */ -@@ -851,6 +933,8 @@ dw_axi_dma_chan_prep_slave_sg(struct dma +@@ -849,6 +931,8 @@ dw_axi_dma_chan_prep_slave_sg(struct dma } while (len >= segment_len); } @@ -274,7 +274,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> /* Set end-of-link to the last link descriptor of list */ set_desc_last(&desc->hw_desc[num_sgs - 1]); -@@ -958,6 +1042,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan +@@ -956,6 +1040,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan num++; } @@ -283,7 +283,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> /* Set end-of-link to the last link descriptor of list */ set_desc_last(&desc->hw_desc[num - 1]); /* Managed transfer list */ -@@ -1006,7 +1092,7 @@ static void axi_chan_dump_lli(struct axi +@@ -1004,7 +1090,7 @@ static void axi_chan_dump_lli(struct axi static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, struct axi_dma_desc *desc_head) { @@ -292,7 +292,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> int i; for (i = 0; i < count; i++) -@@ -1049,11 +1135,11 @@ out: +@@ -1047,11 +1133,11 @@ out: static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) { @@ -305,7 +305,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> u64 llp; int i; -@@ -1075,6 +1161,7 @@ static void axi_chan_block_xfer_complete +@@ -1073,6 +1159,7 @@ static void axi_chan_block_xfer_complete if (chan->cyclic) { desc = vd_to_axi_desc(vd); if (desc) { @@ -313,7 +313,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> llp = lo_hi_readq(chan->chan_regs + CH_LLP); for (i = 0; i < count; i++) { hw_desc = &desc->hw_desc[i]; -@@ -1095,6 +1182,9 @@ static void axi_chan_block_xfer_complete +@@ -1093,6 +1180,9 @@ static void axi_chan_block_xfer_complete /* Remove the completed descriptor from issued list before completing */ list_del(&vd->node); vchan_cookie_complete(vd); @@ -323,7 +323,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> } out: -@@ -1324,6 +1414,10 @@ static int parse_device_properties(struc +@@ -1322,6 +1412,10 @@ static int parse_device_properties(struc chip->dw->hdata->nr_masters = tmp; diff --git a/target/linux/bcm27xx/patches-6.6/950-1145-fixup-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch b/target/linux/bcm27xx/patches-6.6/950-1145-fixup-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch index adefd4ab54..f8a8fc5959 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1145-fixup-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1145-fixup-dmaengine-dw-axi-dmac-Fixes-for-RP1.patch @@ -23,7 +23,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> struct axi_dma_hw_desc *hw_desc; int descs_put; -@@ -849,7 +849,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_c +@@ -847,7 +847,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_c src_addr += segment_len; } @@ -32,7 +32,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> llp = desc->hw_desc[0].llp; -@@ -933,7 +933,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma +@@ -931,7 +931,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma } while (len >= segment_len); } @@ -41,7 +41,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> /* Set end-of-link to the last link descriptor of list */ set_desc_last(&desc->hw_desc[num_sgs - 1]); -@@ -1042,7 +1042,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan +@@ -1040,7 +1040,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan num++; } @@ -50,7 +50,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> /* Set end-of-link to the last link descriptor of list */ set_desc_last(&desc->hw_desc[num - 1]); -@@ -1092,7 +1092,7 @@ static void axi_chan_dump_lli(struct axi +@@ -1090,7 +1090,7 @@ static void axi_chan_dump_lli(struct axi static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, struct axi_dma_desc *desc_head) { @@ -59,7 +59,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> int i; for (i = 0; i < count; i++) -@@ -1139,7 +1139,7 @@ static void axi_chan_block_xfer_complete +@@ -1137,7 +1137,7 @@ static void axi_chan_block_xfer_complete struct axi_dma_desc *desc; struct virt_dma_desc *vd; unsigned long flags; @@ -68,7 +68,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> u64 llp; int i; -@@ -1161,7 +1161,7 @@ static void axi_chan_block_xfer_complete +@@ -1159,7 +1159,7 @@ static void axi_chan_block_xfer_complete if (chan->cyclic) { desc = vd_to_axi_desc(vd); if (desc) { diff --git a/target/linux/bcm27xx/patches-6.6/950-1149-media-uapi-Add-Raspberry-Pi-PiSP-Back-End-uAPI.patch b/target/linux/bcm27xx/patches-6.6/950-1149-media-uapi-Add-Raspberry-Pi-PiSP-Back-End-uAPI.patch index a2e36d50d6..481cf8dca0 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1149-media-uapi-Add-Raspberry-Pi-PiSP-Back-End-uAPI.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1149-media-uapi-Add-Raspberry-Pi-PiSP-Back-End-uAPI.patch @@ -23,7 +23,7 @@ Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -18034,6 +18034,13 @@ L: linux-wireless@vger.kernel.org +@@ -18042,6 +18042,13 @@ L: linux-wireless@vger.kernel.org S: Orphan F: drivers/net/wireless/legacy/ray* diff --git a/target/linux/bcm27xx/patches-6.6/950-1152-media-dt-bindings-Add-bindings-for-Raspberry-Pi-PiSP.patch b/target/linux/bcm27xx/patches-6.6/950-1152-media-dt-bindings-Add-bindings-for-Raspberry-Pi-PiSP.patch index 12f91d9784..463d2b55f3 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1152-media-dt-bindings-Add-bindings-for-Raspberry-Pi-PiSP.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1152-media-dt-bindings-Add-bindings-for-Raspberry-Pi-PiSP.patch @@ -87,7 +87,7 @@ Reviewed-by: Naushir Patuck <naush@raspberrypi.com> + }; --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -18039,6 +18039,7 @@ M: Jacopo Mondi <jacopo.mondi@ideasonboa +@@ -18047,6 +18047,7 @@ M: Jacopo Mondi <jacopo.mondi@ideasonboa L: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com> L: linux-media@vger.kernel.org S: Maintained diff --git a/target/linux/bcm27xx/patches-6.6/950-1164-spi-dt-bindings-Add-RPI-RP2040-GPIO-Bridge.patch b/target/linux/bcm27xx/patches-6.6/950-1164-spi-dt-bindings-Add-RPI-RP2040-GPIO-Bridge.patch index 785b36e3cf..2c99ff9d8d 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1164-spi-dt-bindings-Add-RPI-RP2040-GPIO-Bridge.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1164-spi-dt-bindings-Add-RPI-RP2040-GPIO-Bridge.patch @@ -94,7 +94,7 @@ Signed-off-by: Richard Oliver <richard.oliver@raspberrypi.com> + --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -18029,6 +18029,11 @@ F: drivers/ras/ +@@ -18037,6 +18037,11 @@ F: drivers/ras/ F: include/linux/ras.h F: include/ras/ras_event.h diff --git a/target/linux/bcm27xx/patches-6.6/950-1165-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch b/target/linux/bcm27xx/patches-6.6/950-1165-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch index 2ae7494e8e..babe8b601e 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1165-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1165-spi-Add-a-driver-for-the-RPI-RP2040-GPIO-bridge.patch @@ -25,7 +25,7 @@ Signed-off-by: Richard Oliver <richard.oliver@raspberrypi.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -18033,6 +18033,7 @@ RASPBERRY PI RP2040 GPIO BRIDGE DRIVER +@@ -18041,6 +18041,7 @@ RASPBERRY PI RP2040 GPIO BRIDGE DRIVER M: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com> S: Maintained F: Documentation/devicetree/bindings/spi/raspberrypi,rp2040-gpio-bridge.yaml diff --git a/target/linux/bcm27xx/patches-6.6/950-1166-dmaengine-dw-axi-dmac-Honour-snps-block-size.patch b/target/linux/bcm27xx/patches-6.6/950-1166-dmaengine-dw-axi-dmac-Honour-snps-block-size.patch index 85b1cf6448..7d95698f0e 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1166-dmaengine-dw-axi-dmac-Honour-snps-block-size.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1166-dmaengine-dw-axi-dmac-Honour-snps-block-size.patch @@ -19,7 +19,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c -@@ -1470,6 +1470,7 @@ static int dw_probe(struct platform_devi +@@ -1468,6 +1468,7 @@ static int dw_probe(struct platform_devi struct dw_axi_dma *dw; struct dw_axi_dma_hcfg *hdata; struct reset_control *resets; @@ -27,7 +27,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> unsigned int flags; u32 i; int ret; -@@ -1585,9 +1586,21 @@ static int dw_probe(struct platform_devi +@@ -1583,9 +1584,21 @@ static int dw_probe(struct platform_devi * Synopsis DesignWare AxiDMA datasheet mentioned Maximum * supported blocks is 1024. Device register width is 4 bytes. * Therefore, set constraint to 1024 * 4. diff --git a/target/linux/bcm27xx/patches-6.6/950-1193-drivers-dw-axi-dmac-make-more-sensible-choices-about.patch b/target/linux/bcm27xx/patches-6.6/950-1193-drivers-dw-axi-dmac-make-more-sensible-choices-about.patch index d336532f46..de59216438 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1193-drivers-dw-axi-dmac-make-more-sensible-choices-about.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1193-drivers-dw-axi-dmac-make-more-sensible-choices-about.patch @@ -47,7 +47,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com> static inline const char *axi_chan_name(struct axi_dma_chan *chan) { return dma_chan_name(&chan->vc.chan); -@@ -685,41 +694,41 @@ static int dw_axi_dma_set_hw_desc(struct +@@ -683,41 +692,41 @@ static int dw_axi_dma_set_hw_desc(struct size_t axi_block_ts; size_t block_ts; u32 ctllo, ctlhi; @@ -99,7 +99,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com> DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; block_ts = len >> reg_width; -@@ -760,6 +769,12 @@ static int dw_axi_dma_set_hw_desc(struct +@@ -758,6 +767,12 @@ static int dw_axi_dma_set_hw_desc(struct set_desc_src_master(hw_desc); hw_desc->len = len; @@ -112,7 +112,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com> return 0; } -@@ -776,9 +791,6 @@ static size_t calculate_block_len(struct +@@ -774,9 +789,6 @@ static size_t calculate_block_len(struct case DMA_MEM_TO_DEV: data_width = BIT(chan->chip->dw->hdata->m_data_width); mem_width = __ffs(data_width | dma_addr | buf_len); diff --git a/target/linux/bcm27xx/patches-6.6/950-1243-media-dt-bindings-i2c-Add-Sony-IMX500.patch b/target/linux/bcm27xx/patches-6.6/950-1243-media-dt-bindings-i2c-Add-Sony-IMX500.patch index d4979f73e0..5e4dd5488a 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1243-media-dt-bindings-i2c-Add-Sony-IMX500.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1243-media-dt-bindings-i2c-Add-Sony-IMX500.patch @@ -150,7 +150,7 @@ Signed-off-by: Richard Oliver <richard.oliver@raspberrypi.com> + --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20129,6 +20129,13 @@ F: Documentation/devicetree/bindings/med +@@ -20137,6 +20137,13 @@ F: Documentation/devicetree/bindings/med F: Documentation/devicetree/bindings/media/i2c/imx477.yaml F: drivers/media/i2c/imx477.c diff --git a/target/linux/bcm27xx/patches-6.6/950-1244-media-i2c-Add-driver-for-Sony-IMX500-sensor.patch b/target/linux/bcm27xx/patches-6.6/950-1244-media-i2c-Add-driver-for-Sony-IMX500-sensor.patch index 12e5e2b9e4..c712a4cfc3 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1244-media-i2c-Add-driver-for-Sony-IMX500-sensor.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1244-media-i2c-Add-driver-for-Sony-IMX500-sensor.patch @@ -21,7 +21,7 @@ Signed-off-by: Richard Oliver <richard.oliver@raspberrypi.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20135,6 +20135,7 @@ L: linux-media@vger.kernel.org +@@ -20143,6 +20143,7 @@ L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/sony,imx500.yaml diff --git a/target/linux/bcm27xx/patches-6.6/950-1372-dmaengine-dw-axi-dmac-Allow-client-chosen-width.patch b/target/linux/bcm27xx/patches-6.6/950-1372-dmaengine-dw-axi-dmac-Allow-client-chosen-width.patch index 90688668b8..99fe3d264a 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1372-dmaengine-dw-axi-dmac-Allow-client-chosen-width.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1372-dmaengine-dw-axi-dmac-Allow-client-chosen-width.patch @@ -19,7 +19,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c -@@ -724,6 +724,18 @@ static int dw_axi_dma_set_hw_desc(struct +@@ -722,6 +722,18 @@ static int dw_axi_dma_set_hw_desc(struct case DMA_DEV_TO_MEM: reg_burst_msize = axi_dma_encode_msize(chan->config.src_maxburst); reg_width = __ffs(chan->config.src_addr_width); diff --git a/target/linux/bcm27xx/patches-6.6/950-1438-nvme-pci-Disable-Host-Memory-Buffer-usage.patch b/target/linux/bcm27xx/patches-6.6/950-1438-nvme-pci-Disable-Host-Memory-Buffer-usage.patch index 06c2607b1c..8a16b56a01 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1438-nvme-pci-Disable-Host-Memory-Buffer-usage.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1438-nvme-pci-Disable-Host-Memory-Buffer-usage.patch @@ -18,7 +18,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c -@@ -2011,6 +2011,7 @@ static void nvme_free_host_mem(struct nv +@@ -2012,6 +2012,7 @@ static void nvme_free_host_mem(struct nv dev->nr_host_mem_descs = 0; } @@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, u32 chunk_size) { -@@ -2079,9 +2080,11 @@ out: +@@ -2080,9 +2081,11 @@ out: dev->host_mem_descs = NULL; return -ENOMEM; } @@ -38,7 +38,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com> u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); u64 chunk_size; -@@ -2094,6 +2097,7 @@ static int nvme_alloc_host_mem(struct nv +@@ -2095,6 +2098,7 @@ static int nvme_alloc_host_mem(struct nv nvme_free_host_mem(dev); } } diff --git a/target/linux/generic/backport-6.6/602-v6.10-net-Use-backlog-NAPI-to-clean-up-the-defer_list.patch b/target/linux/generic/backport-6.6/602-v6.10-net-Use-backlog-NAPI-to-clean-up-the-defer_list.patch index 0d55be3794..b68b86795e 100644 --- a/target/linux/generic/backport-6.6/602-v6.10-net-Use-backlog-NAPI-to-clean-up-the-defer_list.patch +++ b/target/linux/generic/backport-6.6/602-v6.10-net-Use-backlog-NAPI-to-clean-up-the-defer_list.patch @@ -108,7 +108,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com> #endif --- a/net/core/skbuff.c +++ b/net/core/skbuff.c -@@ -6866,8 +6866,8 @@ nodefer: __kfree_skb(skb); +@@ -6875,8 +6875,8 @@ nodefer: __kfree_skb(skb); /* Make sure to trigger NET_RX_SOFTIRQ on the remote CPU * if we are unlucky enough (this seems very unlikely). */ diff --git a/target/linux/generic/backport-6.6/702-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch b/target/linux/generic/backport-6.6/702-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch deleted file mode 100644 index be4d4ccad9..0000000000 --- a/target/linux/generic/backport-6.6/702-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch +++ /dev/null @@ -1,2386 +0,0 @@ -From d2213db3f49bce8e7a87c8de05b9a091f78f654e Mon Sep 17 00:00:00 2001 -From: Christian Marangi <ansuelsmth@gmail.com> -Date: Tue, 14 Nov 2023 15:08:41 +0100 -Subject: [PATCH 1/3] net: phy: aquantia: move to separate directory - -Move aquantia PHY driver to separate driectory in preparation for -firmware loading support to keep things tidy. - -Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> -Reviewed-by: Andrew Lunn <andrew@lunn.ch> -Signed-off-by: David S. Miller <davem@davemloft.net> ---- - drivers/net/phy/Kconfig | 5 +---- - drivers/net/phy/Makefile | 6 +----- - drivers/net/phy/aquantia/Kconfig | 5 +++++ - drivers/net/phy/aquantia/Makefile | 6 ++++++ - drivers/net/phy/{ => aquantia}/aquantia.h | 0 - drivers/net/phy/{ => aquantia}/aquantia_hwmon.c | 0 - drivers/net/phy/{ => aquantia}/aquantia_main.c | 0 - 7 files changed, 13 insertions(+), 9 deletions(-) - create mode 100644 drivers/net/phy/aquantia/Kconfig - create mode 100644 drivers/net/phy/aquantia/Makefile - rename drivers/net/phy/{ => aquantia}/aquantia.h (100%) - rename drivers/net/phy/{ => aquantia}/aquantia_hwmon.c (100%) - rename drivers/net/phy/{ => aquantia}/aquantia_main.c (100%) - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -96,10 +96,7 @@ config ADIN1100_PHY - Currently supports the: - - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY - --config AQUANTIA_PHY -- tristate "Aquantia PHYs" -- help -- Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405 -+source "drivers/net/phy/aquantia/Kconfig" - - config AX88796B_PHY - tristate "Asix PHYs" ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -35,11 +35,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) - obj-$(CONFIG_ADIN_PHY) += adin.o - obj-$(CONFIG_ADIN1100_PHY) += adin1100.o - obj-$(CONFIG_AMD_PHY) += amd.o --aquantia-objs += aquantia_main.o --ifdef CONFIG_HWMON --aquantia-objs += aquantia_hwmon.o --endif --obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o -+obj-$(CONFIG_AQUANTIA_PHY) += aquantia/ - obj-$(CONFIG_AT803X_PHY) += at803x.o - obj-$(CONFIG_AX88796B_PHY) += ax88796b.o - obj-$(CONFIG_BCM54140_PHY) += bcm54140.o ---- /dev/null -+++ b/drivers/net/phy/aquantia/Kconfig -@@ -0,0 +1,5 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+config AQUANTIA_PHY -+ tristate "Aquantia PHYs" -+ help -+ Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405 ---- /dev/null -+++ b/drivers/net/phy/aquantia/Makefile -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0 -+aquantia-objs += aquantia_main.o -+ifdef CONFIG_HWMON -+aquantia-objs += aquantia_hwmon.o -+endif -+obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o ---- a/drivers/net/phy/aquantia.h -+++ /dev/null -@@ -1,16 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0 */ --/* HWMON driver for Aquantia PHY -- * -- * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com> -- * Author: Andrew Lunn <andrew@lunn.ch> -- * Author: Heiner Kallweit <hkallweit1@gmail.com> -- */ -- --#include <linux/device.h> --#include <linux/phy.h> -- --#if IS_REACHABLE(CONFIG_HWMON) --int aqr_hwmon_probe(struct phy_device *phydev); --#else --static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; } --#endif ---- /dev/null -+++ b/drivers/net/phy/aquantia/aquantia.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* HWMON driver for Aquantia PHY -+ * -+ * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com> -+ * Author: Andrew Lunn <andrew@lunn.ch> -+ * Author: Heiner Kallweit <hkallweit1@gmail.com> -+ */ -+ -+#include <linux/device.h> -+#include <linux/phy.h> -+ -+#if IS_REACHABLE(CONFIG_HWMON) -+int aqr_hwmon_probe(struct phy_device *phydev); -+#else -+static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; } -+#endif ---- /dev/null -+++ b/drivers/net/phy/aquantia/aquantia_hwmon.c -@@ -0,0 +1,250 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* HWMON driver for Aquantia PHY -+ * -+ * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com> -+ * Author: Andrew Lunn <andrew@lunn.ch> -+ * Author: Heiner Kallweit <hkallweit1@gmail.com> -+ */ -+ -+#include <linux/phy.h> -+#include <linux/device.h> -+#include <linux/ctype.h> -+#include <linux/hwmon.h> -+ -+#include "aquantia.h" -+ -+/* Vendor specific 1, MDIO_MMD_VEND2 */ -+#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421 -+#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422 -+#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423 -+#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424 -+#define VEND1_THERMAL_STAT1 0xc820 -+#define VEND1_THERMAL_STAT2 0xc821 -+#define VEND1_THERMAL_STAT2_VALID BIT(0) -+#define VEND1_GENERAL_STAT1 0xc830 -+#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14) -+#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13) -+#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12) -+#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11) -+ -+#if IS_REACHABLE(CONFIG_HWMON) -+ -+static umode_t aqr_hwmon_is_visible(const void *data, -+ enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ if (type != hwmon_temp) -+ return 0; -+ -+ switch (attr) { -+ case hwmon_temp_input: -+ case hwmon_temp_min_alarm: -+ case hwmon_temp_max_alarm: -+ case hwmon_temp_lcrit_alarm: -+ case hwmon_temp_crit_alarm: -+ return 0444; -+ case hwmon_temp_min: -+ case hwmon_temp_max: -+ case hwmon_temp_lcrit: -+ case hwmon_temp_crit: -+ return 0644; -+ default: -+ return 0; -+ } -+} -+ -+static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value) -+{ -+ int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); -+ -+ if (temp < 0) -+ return temp; -+ -+ /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */ -+ *value = (s16)temp * 1000 / 256; -+ -+ return 0; -+} -+ -+static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value) -+{ -+ int temp; -+ -+ if (value >= 128000 || value < -128000) -+ return -ERANGE; -+ -+ temp = value * 256 / 1000; -+ -+ /* temp is in s16 range and we're interested in lower 16 bits only */ -+ return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); -+} -+ -+static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit) -+{ -+ int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); -+ -+ if (val < 0) -+ return val; -+ -+ return !!(val & bit); -+} -+ -+static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value) -+{ -+ int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit); -+ -+ if (val < 0) -+ return val; -+ -+ *value = val; -+ -+ return 0; -+} -+ -+static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *value) -+{ -+ struct phy_device *phydev = dev_get_drvdata(dev); -+ int reg; -+ -+ if (type != hwmon_temp) -+ return -EOPNOTSUPP; -+ -+ switch (attr) { -+ case hwmon_temp_input: -+ reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2, -+ VEND1_THERMAL_STAT2_VALID); -+ if (reg < 0) -+ return reg; -+ if (!reg) -+ return -EBUSY; -+ -+ return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value); -+ -+ case hwmon_temp_lcrit: -+ return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL, -+ value); -+ case hwmon_temp_min: -+ return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN, -+ value); -+ case hwmon_temp_max: -+ return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN, -+ value); -+ case hwmon_temp_crit: -+ return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL, -+ value); -+ case hwmon_temp_lcrit_alarm: -+ return aqr_hwmon_status1(phydev, -+ VEND1_GENERAL_STAT1_LOW_TEMP_FAIL, -+ value); -+ case hwmon_temp_min_alarm: -+ return aqr_hwmon_status1(phydev, -+ VEND1_GENERAL_STAT1_LOW_TEMP_WARN, -+ value); -+ case hwmon_temp_max_alarm: -+ return aqr_hwmon_status1(phydev, -+ VEND1_GENERAL_STAT1_HIGH_TEMP_WARN, -+ value); -+ case hwmon_temp_crit_alarm: -+ return aqr_hwmon_status1(phydev, -+ VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL, -+ value); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long value) -+{ -+ struct phy_device *phydev = dev_get_drvdata(dev); -+ -+ if (type != hwmon_temp) -+ return -EOPNOTSUPP; -+ -+ switch (attr) { -+ case hwmon_temp_lcrit: -+ return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL, -+ value); -+ case hwmon_temp_min: -+ return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN, -+ value); -+ case hwmon_temp_max: -+ return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN, -+ value); -+ case hwmon_temp_crit: -+ return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL, -+ value); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static const struct hwmon_ops aqr_hwmon_ops = { -+ .is_visible = aqr_hwmon_is_visible, -+ .read = aqr_hwmon_read, -+ .write = aqr_hwmon_write, -+}; -+ -+static u32 aqr_hwmon_chip_config[] = { -+ HWMON_C_REGISTER_TZ, -+ 0, -+}; -+ -+static const struct hwmon_channel_info aqr_hwmon_chip = { -+ .type = hwmon_chip, -+ .config = aqr_hwmon_chip_config, -+}; -+ -+static u32 aqr_hwmon_temp_config[] = { -+ HWMON_T_INPUT | -+ HWMON_T_MAX | HWMON_T_MIN | -+ HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM | -+ HWMON_T_CRIT | HWMON_T_LCRIT | -+ HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM, -+ 0, -+}; -+ -+static const struct hwmon_channel_info aqr_hwmon_temp = { -+ .type = hwmon_temp, -+ .config = aqr_hwmon_temp_config, -+}; -+ -+static const struct hwmon_channel_info * const aqr_hwmon_info[] = { -+ &aqr_hwmon_chip, -+ &aqr_hwmon_temp, -+ NULL, -+}; -+ -+static const struct hwmon_chip_info aqr_hwmon_chip_info = { -+ .ops = &aqr_hwmon_ops, -+ .info = aqr_hwmon_info, -+}; -+ -+int aqr_hwmon_probe(struct phy_device *phydev) -+{ -+ struct device *dev = &phydev->mdio.dev; -+ struct device *hwmon_dev; -+ char *hwmon_name; -+ int i, j; -+ -+ hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); -+ if (!hwmon_name) -+ return -ENOMEM; -+ -+ for (i = j = 0; hwmon_name[i]; i++) { -+ if (isalnum(hwmon_name[i])) { -+ if (i != j) -+ hwmon_name[j] = hwmon_name[i]; -+ j++; -+ } -+ } -+ hwmon_name[j] = '\0'; -+ -+ hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name, -+ phydev, &aqr_hwmon_chip_info, NULL); -+ -+ return PTR_ERR_OR_ZERO(hwmon_dev); -+} -+ -+#endif ---- /dev/null -+++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -0,0 +1,882 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Driver for Aquantia PHY -+ * -+ * Author: Shaohui Xie <Shaohui.Xie@freescale.com> -+ * -+ * Copyright 2015 Freescale Semiconductor, Inc. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/delay.h> -+#include <linux/bitfield.h> -+#include <linux/phy.h> -+ -+#include "aquantia.h" -+ -+#define PHY_ID_AQ1202 0x03a1b445 -+#define PHY_ID_AQ2104 0x03a1b460 -+#define PHY_ID_AQR105 0x03a1b4a2 -+#define PHY_ID_AQR106 0x03a1b4d0 -+#define PHY_ID_AQR107 0x03a1b4e0 -+#define PHY_ID_AQCS109 0x03a1b5c2 -+#define PHY_ID_AQR405 0x03a1b4b0 -+#define PHY_ID_AQR112 0x03a1b662 -+#define PHY_ID_AQR412 0x03a1b712 -+#define PHY_ID_AQR113C 0x31c31c12 -+ -+#define MDIO_PHYXS_VEND_IF_STATUS 0xe812 -+#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) -+#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 -+#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 -+#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 -+#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 -+#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 -+#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 -+#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 -+#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 -+ -+#define MDIO_AN_VEND_PROV 0xc400 -+#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) -+#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) -+#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) -+#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) -+#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) -+#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) -+#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 -+ -+#define MDIO_AN_TX_VEND_STATUS1 0xc800 -+#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) -+#define MDIO_AN_TX_VEND_STATUS1_10BASET 0 -+#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 -+#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 -+#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 -+#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 -+#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 -+#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) -+ -+#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 -+#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) -+ -+#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 -+#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) -+ -+#define MDIO_AN_TX_VEND_INT_MASK2 0xd401 -+#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) -+ -+#define MDIO_AN_RX_LP_STAT1 0xe820 -+#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) -+#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) -+#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) -+#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) -+#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) -+ -+#define MDIO_AN_RX_LP_STAT4 0xe823 -+#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) -+#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) -+ -+#define MDIO_AN_RX_VEND_STAT3 0xe832 -+#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) -+ -+/* MDIO_MMD_C22EXT */ -+#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 -+#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 -+#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 -+#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 -+#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 -+#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 -+#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 -+#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 -+#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a -+#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b -+ -+/* Vendor specific 1, MDIO_MMD_VEND1 */ -+#define VEND1_GLOBAL_FW_ID 0x0020 -+#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) -+#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) -+ -+#define VEND1_GLOBAL_GEN_STAT2 0xc831 -+#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15) -+ -+/* The following registers all have similar layouts; first the registers... */ -+#define VEND1_GLOBAL_CFG_10M 0x0310 -+#define VEND1_GLOBAL_CFG_100M 0x031b -+#define VEND1_GLOBAL_CFG_1G 0x031c -+#define VEND1_GLOBAL_CFG_2_5G 0x031d -+#define VEND1_GLOBAL_CFG_5G 0x031e -+#define VEND1_GLOBAL_CFG_10G 0x031f -+/* ...and now the fields */ -+#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7) -+#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0 -+#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1 -+#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2 -+ -+#define VEND1_GLOBAL_RSVD_STAT1 0xc885 -+#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) -+#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) -+ -+#define VEND1_GLOBAL_RSVD_STAT9 0xc88d -+#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) -+#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 -+ -+#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 -+#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 -+ -+#define VEND1_GLOBAL_INT_STD_MASK 0xff00 -+#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) -+#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) -+#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) -+#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) -+#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) -+#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) -+#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) -+#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) -+#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) -+#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) -+#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) -+ -+#define VEND1_GLOBAL_INT_VEND_MASK 0xff01 -+#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) -+#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) -+#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) -+#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) -+#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) -+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) -+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) -+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) -+ -+/* Sleep and timeout for checking if the Processor-Intensive -+ * MDIO operation is finished -+ */ -+#define AQR107_OP_IN_PROG_SLEEP 1000 -+#define AQR107_OP_IN_PROG_TIMEOUT 100000 -+ -+struct aqr107_hw_stat { -+ const char *name; -+ int reg; -+ int size; -+}; -+ -+#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } -+static const struct aqr107_hw_stat aqr107_hw_stats[] = { -+ SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), -+ SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), -+ SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), -+ SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), -+ SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), -+ SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), -+ SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), -+ SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), -+ SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), -+ SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), -+}; -+#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) -+ -+struct aqr107_priv { -+ u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; -+}; -+ -+static int aqr107_get_sset_count(struct phy_device *phydev) -+{ -+ return AQR107_SGMII_STAT_SZ; -+} -+ -+static void aqr107_get_strings(struct phy_device *phydev, u8 *data) -+{ -+ int i; -+ -+ for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) -+ strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, -+ ETH_GSTRING_LEN); -+} -+ -+static u64 aqr107_get_stat(struct phy_device *phydev, int index) -+{ -+ const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; -+ int len_l = min(stat->size, 16); -+ int len_h = stat->size - len_l; -+ u64 ret; -+ int val; -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); -+ if (val < 0) -+ return U64_MAX; -+ -+ ret = val & GENMASK(len_l - 1, 0); -+ if (len_h) { -+ val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); -+ if (val < 0) -+ return U64_MAX; -+ -+ ret += (val & GENMASK(len_h - 1, 0)) << 16; -+ } -+ -+ return ret; -+} -+ -+static void aqr107_get_stats(struct phy_device *phydev, -+ struct ethtool_stats *stats, u64 *data) -+{ -+ struct aqr107_priv *priv = phydev->priv; -+ u64 val; -+ int i; -+ -+ for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { -+ val = aqr107_get_stat(phydev, i); -+ if (val == U64_MAX) -+ phydev_err(phydev, "Reading HW Statistics failed for %s\n", -+ aqr107_hw_stats[i].name); -+ else -+ priv->sgmii_stats[i] += val; -+ -+ data[i] = priv->sgmii_stats[i]; -+ } -+} -+ -+static int aqr_config_aneg(struct phy_device *phydev) -+{ -+ bool changed = false; -+ u16 reg; -+ int ret; -+ -+ if (phydev->autoneg == AUTONEG_DISABLE) -+ return genphy_c45_pma_setup_forced(phydev); -+ -+ ret = genphy_c45_an_config_aneg(phydev); -+ if (ret < 0) -+ return ret; -+ if (ret > 0) -+ changed = true; -+ -+ /* Clause 45 has no standardized support for 1000BaseT, therefore -+ * use vendor registers for this mode. -+ */ -+ reg = 0; -+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, -+ phydev->advertising)) -+ reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; -+ -+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, -+ phydev->advertising)) -+ reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; -+ -+ /* Handle the case when the 2.5G and 5G speeds are not advertised */ -+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, -+ phydev->advertising)) -+ reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; -+ -+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, -+ phydev->advertising)) -+ reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; -+ -+ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, -+ MDIO_AN_VEND_PROV_1000BASET_HALF | -+ MDIO_AN_VEND_PROV_1000BASET_FULL | -+ MDIO_AN_VEND_PROV_2500BASET_FULL | -+ MDIO_AN_VEND_PROV_5000BASET_FULL, reg); -+ if (ret < 0) -+ return ret; -+ if (ret > 0) -+ changed = true; -+ -+ return genphy_c45_check_and_restart_aneg(phydev, changed); -+} -+ -+static int aqr_config_intr(struct phy_device *phydev) -+{ -+ bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; -+ int err; -+ -+ if (en) { -+ /* Clear any pending interrupts before enabling them */ -+ err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); -+ if (err < 0) -+ return err; -+ } -+ -+ err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, -+ en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); -+ if (err < 0) -+ return err; -+ -+ err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, -+ en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); -+ if (err < 0) -+ return err; -+ -+ err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, -+ en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | -+ VEND1_GLOBAL_INT_VEND_MASK_AN : 0); -+ if (err < 0) -+ return err; -+ -+ if (!en) { -+ /* Clear any pending interrupts after we have disabled them */ -+ err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); -+ if (err < 0) -+ return err; -+ } -+ -+ return 0; -+} -+ -+static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) -+{ -+ int irq_status; -+ -+ irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, -+ MDIO_AN_TX_VEND_INT_STATUS2); -+ if (irq_status < 0) { -+ phy_error(phydev); -+ return IRQ_NONE; -+ } -+ -+ if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) -+ return IRQ_NONE; -+ -+ phy_trigger_machine(phydev); -+ -+ return IRQ_HANDLED; -+} -+ -+static int aqr_read_status(struct phy_device *phydev) -+{ -+ int val; -+ -+ if (phydev->autoneg == AUTONEG_ENABLE) { -+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); -+ if (val < 0) -+ return val; -+ -+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, -+ phydev->lp_advertising, -+ val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); -+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, -+ phydev->lp_advertising, -+ val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); -+ } -+ -+ return genphy_c45_read_status(phydev); -+} -+ -+static int aqr107_read_rate(struct phy_device *phydev) -+{ -+ u32 config_reg; -+ int val; -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); -+ if (val < 0) -+ return val; -+ -+ if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) -+ phydev->duplex = DUPLEX_FULL; -+ else -+ phydev->duplex = DUPLEX_HALF; -+ -+ switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { -+ case MDIO_AN_TX_VEND_STATUS1_10BASET: -+ phydev->speed = SPEED_10; -+ config_reg = VEND1_GLOBAL_CFG_10M; -+ break; -+ case MDIO_AN_TX_VEND_STATUS1_100BASETX: -+ phydev->speed = SPEED_100; -+ config_reg = VEND1_GLOBAL_CFG_100M; -+ break; -+ case MDIO_AN_TX_VEND_STATUS1_1000BASET: -+ phydev->speed = SPEED_1000; -+ config_reg = VEND1_GLOBAL_CFG_1G; -+ break; -+ case MDIO_AN_TX_VEND_STATUS1_2500BASET: -+ phydev->speed = SPEED_2500; -+ config_reg = VEND1_GLOBAL_CFG_2_5G; -+ break; -+ case MDIO_AN_TX_VEND_STATUS1_5000BASET: -+ phydev->speed = SPEED_5000; -+ config_reg = VEND1_GLOBAL_CFG_5G; -+ break; -+ case MDIO_AN_TX_VEND_STATUS1_10GBASET: -+ phydev->speed = SPEED_10000; -+ config_reg = VEND1_GLOBAL_CFG_10G; -+ break; -+ default: -+ phydev->speed = SPEED_UNKNOWN; -+ return 0; -+ } -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); -+ if (val < 0) -+ return val; -+ -+ if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == -+ VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) -+ phydev->rate_matching = RATE_MATCH_PAUSE; -+ else -+ phydev->rate_matching = RATE_MATCH_NONE; -+ -+ return 0; -+} -+ -+static int aqr107_read_status(struct phy_device *phydev) -+{ -+ int val, ret; -+ -+ ret = aqr_read_status(phydev); -+ if (ret) -+ return ret; -+ -+ if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) -+ return 0; -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); -+ if (val < 0) -+ return val; -+ -+ switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: -+ phydev->interface = PHY_INTERFACE_MODE_10GKR; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: -+ phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: -+ phydev->interface = PHY_INTERFACE_MODE_10GBASER; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: -+ phydev->interface = PHY_INTERFACE_MODE_USXGMII; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: -+ phydev->interface = PHY_INTERFACE_MODE_XAUI; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: -+ phydev->interface = PHY_INTERFACE_MODE_SGMII; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: -+ phydev->interface = PHY_INTERFACE_MODE_RXAUI; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: -+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -+ break; -+ default: -+ phydev->interface = PHY_INTERFACE_MODE_NA; -+ break; -+ } -+ -+ /* Read possibly downshifted rate from vendor register */ -+ return aqr107_read_rate(phydev); -+} -+ -+static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) -+{ -+ int val, cnt, enable; -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); -+ if (val < 0) -+ return val; -+ -+ enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); -+ cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); -+ -+ *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; -+ -+ return 0; -+} -+ -+static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) -+{ -+ int val = 0; -+ -+ if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) -+ return -E2BIG; -+ -+ if (cnt != DOWNSHIFT_DEV_DISABLE) { -+ val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; -+ val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); -+ } -+ -+ return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, -+ MDIO_AN_VEND_PROV_DOWNSHIFT_EN | -+ MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); -+} -+ -+static int aqr107_get_tunable(struct phy_device *phydev, -+ struct ethtool_tunable *tuna, void *data) -+{ -+ switch (tuna->id) { -+ case ETHTOOL_PHY_DOWNSHIFT: -+ return aqr107_get_downshift(phydev, data); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static int aqr107_set_tunable(struct phy_device *phydev, -+ struct ethtool_tunable *tuna, const void *data) -+{ -+ switch (tuna->id) { -+ case ETHTOOL_PHY_DOWNSHIFT: -+ return aqr107_set_downshift(phydev, *(const u8 *)data); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+/* If we configure settings whilst firmware is still initializing the chip, -+ * then these settings may be overwritten. Therefore make sure chip -+ * initialization has completed. Use presence of the firmware ID as -+ * indicator for initialization having completed. -+ * The chip also provides a "reset completed" bit, but it's cleared after -+ * read. Therefore function would time out if called again. -+ */ -+static int aqr107_wait_reset_complete(struct phy_device *phydev) -+{ -+ int val; -+ -+ return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -+ VEND1_GLOBAL_FW_ID, val, val != 0, -+ 20000, 2000000, false); -+} -+ -+static void aqr107_chip_info(struct phy_device *phydev) -+{ -+ u8 fw_major, fw_minor, build_id, prov_id; -+ int val; -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); -+ if (val < 0) -+ return; -+ -+ fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); -+ fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); -+ if (val < 0) -+ return; -+ -+ build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); -+ prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); -+ -+ phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", -+ fw_major, fw_minor, build_id, prov_id); -+} -+ -+static int aqr107_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* Check that the PHY interface type is compatible */ -+ if (phydev->interface != PHY_INTERFACE_MODE_SGMII && -+ phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && -+ phydev->interface != PHY_INTERFACE_MODE_2500BASEX && -+ phydev->interface != PHY_INTERFACE_MODE_XGMII && -+ phydev->interface != PHY_INTERFACE_MODE_USXGMII && -+ phydev->interface != PHY_INTERFACE_MODE_10GKR && -+ phydev->interface != PHY_INTERFACE_MODE_10GBASER && -+ phydev->interface != PHY_INTERFACE_MODE_XAUI && -+ phydev->interface != PHY_INTERFACE_MODE_RXAUI) -+ return -ENODEV; -+ -+ WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, -+ "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); -+ -+ ret = aqr107_wait_reset_complete(phydev); -+ if (!ret) -+ aqr107_chip_info(phydev); -+ -+ return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); -+} -+ -+static int aqcs109_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* Check that the PHY interface type is compatible */ -+ if (phydev->interface != PHY_INTERFACE_MODE_SGMII && -+ phydev->interface != PHY_INTERFACE_MODE_2500BASEX) -+ return -ENODEV; -+ -+ ret = aqr107_wait_reset_complete(phydev); -+ if (!ret) -+ aqr107_chip_info(phydev); -+ -+ /* AQCS109 belongs to a chip family partially supporting 10G and 5G. -+ * PMA speed ability bits are the same for all members of the family, -+ * AQCS109 however supports speeds up to 2.5G only. -+ */ -+ phy_set_max_speed(phydev, SPEED_2500); -+ -+ return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); -+} -+ -+static void aqr107_link_change_notify(struct phy_device *phydev) -+{ -+ u8 fw_major, fw_minor; -+ bool downshift, short_reach, afr; -+ int mode, val; -+ -+ if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) -+ return; -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); -+ /* call failed or link partner is no Aquantia PHY */ -+ if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) -+ return; -+ -+ short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; -+ downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); -+ if (val < 0) -+ return; -+ -+ fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); -+ fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); -+ if (val < 0) -+ return; -+ -+ afr = val & MDIO_AN_RX_VEND_STAT3_AFR; -+ -+ phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", -+ fw_major, fw_minor, -+ short_reach ? ", short reach mode" : "", -+ downshift ? ", fast-retrain downshift advertised" : "", -+ afr ? ", fast reframe advertised" : ""); -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); -+ if (val < 0) -+ return; -+ -+ mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); -+ if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) -+ phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); -+} -+ -+static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) -+{ -+ int val, err; -+ -+ /* The datasheet notes to wait at least 1ms after issuing a -+ * processor intensive operation before checking. -+ * We cannot use the 'sleep_before_read' parameter of read_poll_timeout -+ * because that just determines the maximum time slept, not the minimum. -+ */ -+ usleep_range(1000, 5000); -+ -+ err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -+ VEND1_GLOBAL_GEN_STAT2, val, -+ !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), -+ AQR107_OP_IN_PROG_SLEEP, -+ AQR107_OP_IN_PROG_TIMEOUT, false); -+ if (err) { -+ phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static int aqr107_get_rate_matching(struct phy_device *phydev, -+ phy_interface_t iface) -+{ -+ if (iface == PHY_INTERFACE_MODE_10GBASER || -+ iface == PHY_INTERFACE_MODE_2500BASEX || -+ iface == PHY_INTERFACE_MODE_NA) -+ return RATE_MATCH_PAUSE; -+ return RATE_MATCH_NONE; -+} -+ -+static int aqr107_suspend(struct phy_device *phydev) -+{ -+ int err; -+ -+ err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, -+ MDIO_CTRL1_LPOWER); -+ if (err) -+ return err; -+ -+ return aqr107_wait_processor_intensive_op(phydev); -+} -+ -+static int aqr107_resume(struct phy_device *phydev) -+{ -+ int err; -+ -+ err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, -+ MDIO_CTRL1_LPOWER); -+ if (err) -+ return err; -+ -+ return aqr107_wait_processor_intensive_op(phydev); -+} -+ -+static int aqr107_probe(struct phy_device *phydev) -+{ -+ phydev->priv = devm_kzalloc(&phydev->mdio.dev, -+ sizeof(struct aqr107_priv), GFP_KERNEL); -+ if (!phydev->priv) -+ return -ENOMEM; -+ -+ return aqr_hwmon_probe(phydev); -+} -+ -+static struct phy_driver aqr_driver[] = { -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), -+ .name = "Aquantia AQ1202", -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr_read_status, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), -+ .name = "Aquantia AQ2104", -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr_read_status, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR105), -+ .name = "Aquantia AQR105", -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr_read_status, -+ .suspend = aqr107_suspend, -+ .resume = aqr107_resume, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR106), -+ .name = "Aquantia AQR106", -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr_read_status, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR107), -+ .name = "Aquantia AQR107", -+ .probe = aqr107_probe, -+ .get_rate_matching = aqr107_get_rate_matching, -+ .config_init = aqr107_config_init, -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr107_read_status, -+ .get_tunable = aqr107_get_tunable, -+ .set_tunable = aqr107_set_tunable, -+ .suspend = aqr107_suspend, -+ .resume = aqr107_resume, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+ .link_change_notify = aqr107_link_change_notify, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), -+ .name = "Aquantia AQCS109", -+ .probe = aqr107_probe, -+ .get_rate_matching = aqr107_get_rate_matching, -+ .config_init = aqcs109_config_init, -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr107_read_status, -+ .get_tunable = aqr107_get_tunable, -+ .set_tunable = aqr107_set_tunable, -+ .suspend = aqr107_suspend, -+ .resume = aqr107_resume, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+ .link_change_notify = aqr107_link_change_notify, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR405), -+ .name = "Aquantia AQR405", -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr_read_status, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112), -+ .name = "Aquantia AQR112", -+ .probe = aqr107_probe, -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .get_tunable = aqr107_get_tunable, -+ .set_tunable = aqr107_set_tunable, -+ .suspend = aqr107_suspend, -+ .resume = aqr107_resume, -+ .read_status = aqr107_read_status, -+ .get_rate_matching = aqr107_get_rate_matching, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+ .link_change_notify = aqr107_link_change_notify, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR412), -+ .name = "Aquantia AQR412", -+ .probe = aqr107_probe, -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .get_tunable = aqr107_get_tunable, -+ .set_tunable = aqr107_set_tunable, -+ .suspend = aqr107_suspend, -+ .resume = aqr107_resume, -+ .read_status = aqr107_read_status, -+ .get_rate_matching = aqr107_get_rate_matching, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+ .link_change_notify = aqr107_link_change_notify, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), -+ .name = "Aquantia AQR113C", -+ .probe = aqr107_probe, -+ .get_rate_matching = aqr107_get_rate_matching, -+ .config_init = aqr107_config_init, -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .handle_interrupt = aqr_handle_interrupt, -+ .read_status = aqr107_read_status, -+ .get_tunable = aqr107_get_tunable, -+ .set_tunable = aqr107_set_tunable, -+ .suspend = aqr107_suspend, -+ .resume = aqr107_resume, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+ .link_change_notify = aqr107_link_change_notify, -+}, -+}; -+ -+module_phy_driver(aqr_driver); -+ -+static struct mdio_device_id __maybe_unused aqr_tbl[] = { -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(mdio, aqr_tbl); -+ -+MODULE_DESCRIPTION("Aquantia PHY driver"); -+MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); -+MODULE_LICENSE("GPL v2"); ---- a/drivers/net/phy/aquantia_hwmon.c -+++ /dev/null -@@ -1,250 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0 --/* HWMON driver for Aquantia PHY -- * -- * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com> -- * Author: Andrew Lunn <andrew@lunn.ch> -- * Author: Heiner Kallweit <hkallweit1@gmail.com> -- */ -- --#include <linux/phy.h> --#include <linux/device.h> --#include <linux/ctype.h> --#include <linux/hwmon.h> -- --#include "aquantia.h" -- --/* Vendor specific 1, MDIO_MMD_VEND2 */ --#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421 --#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422 --#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423 --#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424 --#define VEND1_THERMAL_STAT1 0xc820 --#define VEND1_THERMAL_STAT2 0xc821 --#define VEND1_THERMAL_STAT2_VALID BIT(0) --#define VEND1_GENERAL_STAT1 0xc830 --#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14) --#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13) --#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12) --#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11) -- --#if IS_REACHABLE(CONFIG_HWMON) -- --static umode_t aqr_hwmon_is_visible(const void *data, -- enum hwmon_sensor_types type, -- u32 attr, int channel) --{ -- if (type != hwmon_temp) -- return 0; -- -- switch (attr) { -- case hwmon_temp_input: -- case hwmon_temp_min_alarm: -- case hwmon_temp_max_alarm: -- case hwmon_temp_lcrit_alarm: -- case hwmon_temp_crit_alarm: -- return 0444; -- case hwmon_temp_min: -- case hwmon_temp_max: -- case hwmon_temp_lcrit: -- case hwmon_temp_crit: -- return 0644; -- default: -- return 0; -- } --} -- --static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value) --{ -- int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); -- -- if (temp < 0) -- return temp; -- -- /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */ -- *value = (s16)temp * 1000 / 256; -- -- return 0; --} -- --static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value) --{ -- int temp; -- -- if (value >= 128000 || value < -128000) -- return -ERANGE; -- -- temp = value * 256 / 1000; -- -- /* temp is in s16 range and we're interested in lower 16 bits only */ -- return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); --} -- --static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit) --{ -- int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); -- -- if (val < 0) -- return val; -- -- return !!(val & bit); --} -- --static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value) --{ -- int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit); -- -- if (val < 0) -- return val; -- -- *value = val; -- -- return 0; --} -- --static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type, -- u32 attr, int channel, long *value) --{ -- struct phy_device *phydev = dev_get_drvdata(dev); -- int reg; -- -- if (type != hwmon_temp) -- return -EOPNOTSUPP; -- -- switch (attr) { -- case hwmon_temp_input: -- reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2, -- VEND1_THERMAL_STAT2_VALID); -- if (reg < 0) -- return reg; -- if (!reg) -- return -EBUSY; -- -- return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value); -- -- case hwmon_temp_lcrit: -- return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL, -- value); -- case hwmon_temp_min: -- return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN, -- value); -- case hwmon_temp_max: -- return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN, -- value); -- case hwmon_temp_crit: -- return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL, -- value); -- case hwmon_temp_lcrit_alarm: -- return aqr_hwmon_status1(phydev, -- VEND1_GENERAL_STAT1_LOW_TEMP_FAIL, -- value); -- case hwmon_temp_min_alarm: -- return aqr_hwmon_status1(phydev, -- VEND1_GENERAL_STAT1_LOW_TEMP_WARN, -- value); -- case hwmon_temp_max_alarm: -- return aqr_hwmon_status1(phydev, -- VEND1_GENERAL_STAT1_HIGH_TEMP_WARN, -- value); -- case hwmon_temp_crit_alarm: -- return aqr_hwmon_status1(phydev, -- VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL, -- value); -- default: -- return -EOPNOTSUPP; -- } --} -- --static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type, -- u32 attr, int channel, long value) --{ -- struct phy_device *phydev = dev_get_drvdata(dev); -- -- if (type != hwmon_temp) -- return -EOPNOTSUPP; -- -- switch (attr) { -- case hwmon_temp_lcrit: -- return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL, -- value); -- case hwmon_temp_min: -- return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN, -- value); -- case hwmon_temp_max: -- return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN, -- value); -- case hwmon_temp_crit: -- return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL, -- value); -- default: -- return -EOPNOTSUPP; -- } --} -- --static const struct hwmon_ops aqr_hwmon_ops = { -- .is_visible = aqr_hwmon_is_visible, -- .read = aqr_hwmon_read, -- .write = aqr_hwmon_write, --}; -- --static u32 aqr_hwmon_chip_config[] = { -- HWMON_C_REGISTER_TZ, -- 0, --}; -- --static const struct hwmon_channel_info aqr_hwmon_chip = { -- .type = hwmon_chip, -- .config = aqr_hwmon_chip_config, --}; -- --static u32 aqr_hwmon_temp_config[] = { -- HWMON_T_INPUT | -- HWMON_T_MAX | HWMON_T_MIN | -- HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM | -- HWMON_T_CRIT | HWMON_T_LCRIT | -- HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM, -- 0, --}; -- --static const struct hwmon_channel_info aqr_hwmon_temp = { -- .type = hwmon_temp, -- .config = aqr_hwmon_temp_config, --}; -- --static const struct hwmon_channel_info * const aqr_hwmon_info[] = { -- &aqr_hwmon_chip, -- &aqr_hwmon_temp, -- NULL, --}; -- --static const struct hwmon_chip_info aqr_hwmon_chip_info = { -- .ops = &aqr_hwmon_ops, -- .info = aqr_hwmon_info, --}; -- --int aqr_hwmon_probe(struct phy_device *phydev) --{ -- struct device *dev = &phydev->mdio.dev; -- struct device *hwmon_dev; -- char *hwmon_name; -- int i, j; -- -- hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); -- if (!hwmon_name) -- return -ENOMEM; -- -- for (i = j = 0; hwmon_name[i]; i++) { -- if (isalnum(hwmon_name[i])) { -- if (i != j) -- hwmon_name[j] = hwmon_name[i]; -- j++; -- } -- } -- hwmon_name[j] = '\0'; -- -- hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name, -- phydev, &aqr_hwmon_chip_info, NULL); -- -- return PTR_ERR_OR_ZERO(hwmon_dev); --} -- --#endif ---- a/drivers/net/phy/aquantia_main.c -+++ /dev/null -@@ -1,882 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0 --/* -- * Driver for Aquantia PHY -- * -- * Author: Shaohui Xie <Shaohui.Xie@freescale.com> -- * -- * Copyright 2015 Freescale Semiconductor, Inc. -- */ -- --#include <linux/kernel.h> --#include <linux/module.h> --#include <linux/delay.h> --#include <linux/bitfield.h> --#include <linux/phy.h> -- --#include "aquantia.h" -- --#define PHY_ID_AQ1202 0x03a1b445 --#define PHY_ID_AQ2104 0x03a1b460 --#define PHY_ID_AQR105 0x03a1b4a2 --#define PHY_ID_AQR106 0x03a1b4d0 --#define PHY_ID_AQR107 0x03a1b4e0 --#define PHY_ID_AQCS109 0x03a1b5c2 --#define PHY_ID_AQR405 0x03a1b4b0 --#define PHY_ID_AQR112 0x03a1b662 --#define PHY_ID_AQR412 0x03a1b712 --#define PHY_ID_AQR113C 0x31c31c12 -- --#define MDIO_PHYXS_VEND_IF_STATUS 0xe812 --#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) --#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 --#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 --#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 --#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 --#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 --#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 --#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 --#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 -- --#define MDIO_AN_VEND_PROV 0xc400 --#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) --#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) --#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) --#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) --#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) --#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) --#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 -- --#define MDIO_AN_TX_VEND_STATUS1 0xc800 --#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) --#define MDIO_AN_TX_VEND_STATUS1_10BASET 0 --#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 --#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 --#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 --#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 --#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 --#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) -- --#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 --#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) -- --#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 --#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) -- --#define MDIO_AN_TX_VEND_INT_MASK2 0xd401 --#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) -- --#define MDIO_AN_RX_LP_STAT1 0xe820 --#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) --#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) --#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) --#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) --#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) -- --#define MDIO_AN_RX_LP_STAT4 0xe823 --#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) --#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) -- --#define MDIO_AN_RX_VEND_STAT3 0xe832 --#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) -- --/* MDIO_MMD_C22EXT */ --#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 --#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 --#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 --#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 --#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 --#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 --#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 --#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 --#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a --#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b -- --/* Vendor specific 1, MDIO_MMD_VEND1 */ --#define VEND1_GLOBAL_FW_ID 0x0020 --#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) --#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) -- --#define VEND1_GLOBAL_GEN_STAT2 0xc831 --#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15) -- --/* The following registers all have similar layouts; first the registers... */ --#define VEND1_GLOBAL_CFG_10M 0x0310 --#define VEND1_GLOBAL_CFG_100M 0x031b --#define VEND1_GLOBAL_CFG_1G 0x031c --#define VEND1_GLOBAL_CFG_2_5G 0x031d --#define VEND1_GLOBAL_CFG_5G 0x031e --#define VEND1_GLOBAL_CFG_10G 0x031f --/* ...and now the fields */ --#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7) --#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0 --#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1 --#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2 -- --#define VEND1_GLOBAL_RSVD_STAT1 0xc885 --#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) --#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) -- --#define VEND1_GLOBAL_RSVD_STAT9 0xc88d --#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) --#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 -- --#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 --#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 -- --#define VEND1_GLOBAL_INT_STD_MASK 0xff00 --#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) --#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) --#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) --#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) --#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) --#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) --#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) --#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) --#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) --#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) --#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) -- --#define VEND1_GLOBAL_INT_VEND_MASK 0xff01 --#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) --#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) --#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) --#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) --#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) --#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) --#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) --#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) -- --/* Sleep and timeout for checking if the Processor-Intensive -- * MDIO operation is finished -- */ --#define AQR107_OP_IN_PROG_SLEEP 1000 --#define AQR107_OP_IN_PROG_TIMEOUT 100000 -- --struct aqr107_hw_stat { -- const char *name; -- int reg; -- int size; --}; -- --#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } --static const struct aqr107_hw_stat aqr107_hw_stats[] = { -- SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), -- SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), -- SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), -- SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), -- SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), -- SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), -- SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), -- SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), -- SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), -- SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), --}; --#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) -- --struct aqr107_priv { -- u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; --}; -- --static int aqr107_get_sset_count(struct phy_device *phydev) --{ -- return AQR107_SGMII_STAT_SZ; --} -- --static void aqr107_get_strings(struct phy_device *phydev, u8 *data) --{ -- int i; -- -- for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) -- strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, -- ETH_GSTRING_LEN); --} -- --static u64 aqr107_get_stat(struct phy_device *phydev, int index) --{ -- const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; -- int len_l = min(stat->size, 16); -- int len_h = stat->size - len_l; -- u64 ret; -- int val; -- -- val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); -- if (val < 0) -- return U64_MAX; -- -- ret = val & GENMASK(len_l - 1, 0); -- if (len_h) { -- val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); -- if (val < 0) -- return U64_MAX; -- -- ret += (val & GENMASK(len_h - 1, 0)) << 16; -- } -- -- return ret; --} -- --static void aqr107_get_stats(struct phy_device *phydev, -- struct ethtool_stats *stats, u64 *data) --{ -- struct aqr107_priv *priv = phydev->priv; -- u64 val; -- int i; -- -- for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { -- val = aqr107_get_stat(phydev, i); -- if (val == U64_MAX) -- phydev_err(phydev, "Reading HW Statistics failed for %s\n", -- aqr107_hw_stats[i].name); -- else -- priv->sgmii_stats[i] += val; -- -- data[i] = priv->sgmii_stats[i]; -- } --} -- --static int aqr_config_aneg(struct phy_device *phydev) --{ -- bool changed = false; -- u16 reg; -- int ret; -- -- if (phydev->autoneg == AUTONEG_DISABLE) -- return genphy_c45_pma_setup_forced(phydev); -- -- ret = genphy_c45_an_config_aneg(phydev); -- if (ret < 0) -- return ret; -- if (ret > 0) -- changed = true; -- -- /* Clause 45 has no standardized support for 1000BaseT, therefore -- * use vendor registers for this mode. -- */ -- reg = 0; -- if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, -- phydev->advertising)) -- reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; -- -- if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, -- phydev->advertising)) -- reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; -- -- /* Handle the case when the 2.5G and 5G speeds are not advertised */ -- if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, -- phydev->advertising)) -- reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; -- -- if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, -- phydev->advertising)) -- reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; -- -- ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, -- MDIO_AN_VEND_PROV_1000BASET_HALF | -- MDIO_AN_VEND_PROV_1000BASET_FULL | -- MDIO_AN_VEND_PROV_2500BASET_FULL | -- MDIO_AN_VEND_PROV_5000BASET_FULL, reg); -- if (ret < 0) -- return ret; -- if (ret > 0) -- changed = true; -- -- return genphy_c45_check_and_restart_aneg(phydev, changed); --} -- --static int aqr_config_intr(struct phy_device *phydev) --{ -- bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; -- int err; -- -- if (en) { -- /* Clear any pending interrupts before enabling them */ -- err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); -- if (err < 0) -- return err; -- } -- -- err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, -- en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); -- if (err < 0) -- return err; -- -- err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, -- en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); -- if (err < 0) -- return err; -- -- err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, -- en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | -- VEND1_GLOBAL_INT_VEND_MASK_AN : 0); -- if (err < 0) -- return err; -- -- if (!en) { -- /* Clear any pending interrupts after we have disabled them */ -- err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); -- if (err < 0) -- return err; -- } -- -- return 0; --} -- --static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) --{ -- int irq_status; -- -- irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, -- MDIO_AN_TX_VEND_INT_STATUS2); -- if (irq_status < 0) { -- phy_error(phydev); -- return IRQ_NONE; -- } -- -- if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) -- return IRQ_NONE; -- -- phy_trigger_machine(phydev); -- -- return IRQ_HANDLED; --} -- --static int aqr_read_status(struct phy_device *phydev) --{ -- int val; -- -- if (phydev->autoneg == AUTONEG_ENABLE) { -- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); -- if (val < 0) -- return val; -- -- linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, -- phydev->lp_advertising, -- val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); -- linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, -- phydev->lp_advertising, -- val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); -- } -- -- return genphy_c45_read_status(phydev); --} -- --static int aqr107_read_rate(struct phy_device *phydev) --{ -- u32 config_reg; -- int val; -- -- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); -- if (val < 0) -- return val; -- -- if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) -- phydev->duplex = DUPLEX_FULL; -- else -- phydev->duplex = DUPLEX_HALF; -- -- switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { -- case MDIO_AN_TX_VEND_STATUS1_10BASET: -- phydev->speed = SPEED_10; -- config_reg = VEND1_GLOBAL_CFG_10M; -- break; -- case MDIO_AN_TX_VEND_STATUS1_100BASETX: -- phydev->speed = SPEED_100; -- config_reg = VEND1_GLOBAL_CFG_100M; -- break; -- case MDIO_AN_TX_VEND_STATUS1_1000BASET: -- phydev->speed = SPEED_1000; -- config_reg = VEND1_GLOBAL_CFG_1G; -- break; -- case MDIO_AN_TX_VEND_STATUS1_2500BASET: -- phydev->speed = SPEED_2500; -- config_reg = VEND1_GLOBAL_CFG_2_5G; -- break; -- case MDIO_AN_TX_VEND_STATUS1_5000BASET: -- phydev->speed = SPEED_5000; -- config_reg = VEND1_GLOBAL_CFG_5G; -- break; -- case MDIO_AN_TX_VEND_STATUS1_10GBASET: -- phydev->speed = SPEED_10000; -- config_reg = VEND1_GLOBAL_CFG_10G; -- break; -- default: -- phydev->speed = SPEED_UNKNOWN; -- return 0; -- } -- -- val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); -- if (val < 0) -- return val; -- -- if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == -- VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) -- phydev->rate_matching = RATE_MATCH_PAUSE; -- else -- phydev->rate_matching = RATE_MATCH_NONE; -- -- return 0; --} -- --static int aqr107_read_status(struct phy_device *phydev) --{ -- int val, ret; -- -- ret = aqr_read_status(phydev); -- if (ret) -- return ret; -- -- if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) -- return 0; -- -- val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); -- if (val < 0) -- return val; -- -- switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { -- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: -- phydev->interface = PHY_INTERFACE_MODE_10GKR; -- break; -- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: -- phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; -- break; -- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: -- phydev->interface = PHY_INTERFACE_MODE_10GBASER; -- break; -- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: -- phydev->interface = PHY_INTERFACE_MODE_USXGMII; -- break; -- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: -- phydev->interface = PHY_INTERFACE_MODE_XAUI; -- break; -- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: -- phydev->interface = PHY_INTERFACE_MODE_SGMII; -- break; -- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: -- phydev->interface = PHY_INTERFACE_MODE_RXAUI; -- break; -- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: -- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- break; -- default: -- phydev->interface = PHY_INTERFACE_MODE_NA; -- break; -- } -- -- /* Read possibly downshifted rate from vendor register */ -- return aqr107_read_rate(phydev); --} -- --static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) --{ -- int val, cnt, enable; -- -- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); -- if (val < 0) -- return val; -- -- enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); -- cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); -- -- *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; -- -- return 0; --} -- --static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) --{ -- int val = 0; -- -- if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) -- return -E2BIG; -- -- if (cnt != DOWNSHIFT_DEV_DISABLE) { -- val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; -- val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); -- } -- -- return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, -- MDIO_AN_VEND_PROV_DOWNSHIFT_EN | -- MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); --} -- --static int aqr107_get_tunable(struct phy_device *phydev, -- struct ethtool_tunable *tuna, void *data) --{ -- switch (tuna->id) { -- case ETHTOOL_PHY_DOWNSHIFT: -- return aqr107_get_downshift(phydev, data); -- default: -- return -EOPNOTSUPP; -- } --} -- --static int aqr107_set_tunable(struct phy_device *phydev, -- struct ethtool_tunable *tuna, const void *data) --{ -- switch (tuna->id) { -- case ETHTOOL_PHY_DOWNSHIFT: -- return aqr107_set_downshift(phydev, *(const u8 *)data); -- default: -- return -EOPNOTSUPP; -- } --} -- --/* If we configure settings whilst firmware is still initializing the chip, -- * then these settings may be overwritten. Therefore make sure chip -- * initialization has completed. Use presence of the firmware ID as -- * indicator for initialization having completed. -- * The chip also provides a "reset completed" bit, but it's cleared after -- * read. Therefore function would time out if called again. -- */ --static int aqr107_wait_reset_complete(struct phy_device *phydev) --{ -- int val; -- -- return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -- VEND1_GLOBAL_FW_ID, val, val != 0, -- 20000, 2000000, false); --} -- --static void aqr107_chip_info(struct phy_device *phydev) --{ -- u8 fw_major, fw_minor, build_id, prov_id; -- int val; -- -- val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); -- if (val < 0) -- return; -- -- fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); -- fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); -- -- val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); -- if (val < 0) -- return; -- -- build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); -- prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); -- -- phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", -- fw_major, fw_minor, build_id, prov_id); --} -- --static int aqr107_config_init(struct phy_device *phydev) --{ -- int ret; -- -- /* Check that the PHY interface type is compatible */ -- if (phydev->interface != PHY_INTERFACE_MODE_SGMII && -- phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && -- phydev->interface != PHY_INTERFACE_MODE_2500BASEX && -- phydev->interface != PHY_INTERFACE_MODE_XGMII && -- phydev->interface != PHY_INTERFACE_MODE_USXGMII && -- phydev->interface != PHY_INTERFACE_MODE_10GKR && -- phydev->interface != PHY_INTERFACE_MODE_10GBASER && -- phydev->interface != PHY_INTERFACE_MODE_XAUI && -- phydev->interface != PHY_INTERFACE_MODE_RXAUI) -- return -ENODEV; -- -- WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, -- "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); -- -- ret = aqr107_wait_reset_complete(phydev); -- if (!ret) -- aqr107_chip_info(phydev); -- -- return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); --} -- --static int aqcs109_config_init(struct phy_device *phydev) --{ -- int ret; -- -- /* Check that the PHY interface type is compatible */ -- if (phydev->interface != PHY_INTERFACE_MODE_SGMII && -- phydev->interface != PHY_INTERFACE_MODE_2500BASEX) -- return -ENODEV; -- -- ret = aqr107_wait_reset_complete(phydev); -- if (!ret) -- aqr107_chip_info(phydev); -- -- /* AQCS109 belongs to a chip family partially supporting 10G and 5G. -- * PMA speed ability bits are the same for all members of the family, -- * AQCS109 however supports speeds up to 2.5G only. -- */ -- phy_set_max_speed(phydev, SPEED_2500); -- -- return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); --} -- --static void aqr107_link_change_notify(struct phy_device *phydev) --{ -- u8 fw_major, fw_minor; -- bool downshift, short_reach, afr; -- int mode, val; -- -- if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) -- return; -- -- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); -- /* call failed or link partner is no Aquantia PHY */ -- if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) -- return; -- -- short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; -- downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; -- -- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); -- if (val < 0) -- return; -- -- fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); -- fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); -- -- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); -- if (val < 0) -- return; -- -- afr = val & MDIO_AN_RX_VEND_STAT3_AFR; -- -- phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", -- fw_major, fw_minor, -- short_reach ? ", short reach mode" : "", -- downshift ? ", fast-retrain downshift advertised" : "", -- afr ? ", fast reframe advertised" : ""); -- -- val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); -- if (val < 0) -- return; -- -- mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); -- if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) -- phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); --} -- --static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) --{ -- int val, err; -- -- /* The datasheet notes to wait at least 1ms after issuing a -- * processor intensive operation before checking. -- * We cannot use the 'sleep_before_read' parameter of read_poll_timeout -- * because that just determines the maximum time slept, not the minimum. -- */ -- usleep_range(1000, 5000); -- -- err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -- VEND1_GLOBAL_GEN_STAT2, val, -- !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), -- AQR107_OP_IN_PROG_SLEEP, -- AQR107_OP_IN_PROG_TIMEOUT, false); -- if (err) { -- phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); -- return err; -- } -- -- return 0; --} -- --static int aqr107_get_rate_matching(struct phy_device *phydev, -- phy_interface_t iface) --{ -- if (iface == PHY_INTERFACE_MODE_10GBASER || -- iface == PHY_INTERFACE_MODE_2500BASEX || -- iface == PHY_INTERFACE_MODE_NA) -- return RATE_MATCH_PAUSE; -- return RATE_MATCH_NONE; --} -- --static int aqr107_suspend(struct phy_device *phydev) --{ -- int err; -- -- err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, -- MDIO_CTRL1_LPOWER); -- if (err) -- return err; -- -- return aqr107_wait_processor_intensive_op(phydev); --} -- --static int aqr107_resume(struct phy_device *phydev) --{ -- int err; -- -- err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, -- MDIO_CTRL1_LPOWER); -- if (err) -- return err; -- -- return aqr107_wait_processor_intensive_op(phydev); --} -- --static int aqr107_probe(struct phy_device *phydev) --{ -- phydev->priv = devm_kzalloc(&phydev->mdio.dev, -- sizeof(struct aqr107_priv), GFP_KERNEL); -- if (!phydev->priv) -- return -ENOMEM; -- -- return aqr_hwmon_probe(phydev); --} -- --static struct phy_driver aqr_driver[] = { --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), -- .name = "Aquantia AQ1202", -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .read_status = aqr_read_status, --}, --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), -- .name = "Aquantia AQ2104", -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .read_status = aqr_read_status, --}, --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQR105), -- .name = "Aquantia AQR105", -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .read_status = aqr_read_status, -- .suspend = aqr107_suspend, -- .resume = aqr107_resume, --}, --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQR106), -- .name = "Aquantia AQR106", -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .read_status = aqr_read_status, --}, --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQR107), -- .name = "Aquantia AQR107", -- .probe = aqr107_probe, -- .get_rate_matching = aqr107_get_rate_matching, -- .config_init = aqr107_config_init, -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .read_status = aqr107_read_status, -- .get_tunable = aqr107_get_tunable, -- .set_tunable = aqr107_set_tunable, -- .suspend = aqr107_suspend, -- .resume = aqr107_resume, -- .get_sset_count = aqr107_get_sset_count, -- .get_strings = aqr107_get_strings, -- .get_stats = aqr107_get_stats, -- .link_change_notify = aqr107_link_change_notify, --}, --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), -- .name = "Aquantia AQCS109", -- .probe = aqr107_probe, -- .get_rate_matching = aqr107_get_rate_matching, -- .config_init = aqcs109_config_init, -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .read_status = aqr107_read_status, -- .get_tunable = aqr107_get_tunable, -- .set_tunable = aqr107_set_tunable, -- .suspend = aqr107_suspend, -- .resume = aqr107_resume, -- .get_sset_count = aqr107_get_sset_count, -- .get_strings = aqr107_get_strings, -- .get_stats = aqr107_get_stats, -- .link_change_notify = aqr107_link_change_notify, --}, --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQR405), -- .name = "Aquantia AQR405", -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .read_status = aqr_read_status, --}, --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQR112), -- .name = "Aquantia AQR112", -- .probe = aqr107_probe, -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .get_tunable = aqr107_get_tunable, -- .set_tunable = aqr107_set_tunable, -- .suspend = aqr107_suspend, -- .resume = aqr107_resume, -- .read_status = aqr107_read_status, -- .get_rate_matching = aqr107_get_rate_matching, -- .get_sset_count = aqr107_get_sset_count, -- .get_strings = aqr107_get_strings, -- .get_stats = aqr107_get_stats, -- .link_change_notify = aqr107_link_change_notify, --}, --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQR412), -- .name = "Aquantia AQR412", -- .probe = aqr107_probe, -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .get_tunable = aqr107_get_tunable, -- .set_tunable = aqr107_set_tunable, -- .suspend = aqr107_suspend, -- .resume = aqr107_resume, -- .read_status = aqr107_read_status, -- .get_rate_matching = aqr107_get_rate_matching, -- .get_sset_count = aqr107_get_sset_count, -- .get_strings = aqr107_get_strings, -- .get_stats = aqr107_get_stats, -- .link_change_notify = aqr107_link_change_notify, --}, --{ -- PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), -- .name = "Aquantia AQR113C", -- .probe = aqr107_probe, -- .get_rate_matching = aqr107_get_rate_matching, -- .config_init = aqr107_config_init, -- .config_aneg = aqr_config_aneg, -- .config_intr = aqr_config_intr, -- .handle_interrupt = aqr_handle_interrupt, -- .read_status = aqr107_read_status, -- .get_tunable = aqr107_get_tunable, -- .set_tunable = aqr107_set_tunable, -- .suspend = aqr107_suspend, -- .resume = aqr107_resume, -- .get_sset_count = aqr107_get_sset_count, -- .get_strings = aqr107_get_strings, -- .get_stats = aqr107_get_stats, -- .link_change_notify = aqr107_link_change_notify, --}, --}; -- --module_phy_driver(aqr_driver); -- --static struct mdio_device_id __maybe_unused aqr_tbl[] = { -- { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, -- { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, -- { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, -- { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, -- { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, -- { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, -- { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, -- { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, -- { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, -- { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, -- { } --}; -- --MODULE_DEVICE_TABLE(mdio, aqr_tbl); -- --MODULE_DESCRIPTION("Aquantia PHY driver"); --MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); --MODULE_LICENSE("GPL v2"); diff --git a/target/linux/generic/backport-6.6/704-v6.12-ipv6-Add-ipv6_addr_-cpu_to_be32-be32_to_cpu-helpers.patch b/target/linux/generic/backport-6.6/704-v6.12-ipv6-Add-ipv6_addr_-cpu_to_be32-be32_to_cpu-helpers.patch index 938979e500..b46537d0d9 100644 --- a/target/linux/generic/backport-6.6/704-v6.12-ipv6-Add-ipv6_addr_-cpu_to_be32-be32_to_cpu-helpers.patch +++ b/target/linux/generic/backport-6.6/704-v6.12-ipv6-Add-ipv6_addr_-cpu_to_be32-be32_to_cpu-helpers.patch @@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org> --- a/include/net/ipv6.h +++ b/include/net/ipv6.h -@@ -1385,4 +1385,16 @@ static inline void ip6_sock_set_recvpkti +@@ -1379,4 +1379,16 @@ static inline void ip6_sock_set_recvpkti release_sock(sk); } diff --git a/target/linux/generic/backport-6.6/707-v6.8-02-net-phy-at803x-move-disable-WOL-to-specific-at8031-p.patch b/target/linux/generic/backport-6.6/707-v6.8-02-net-phy-at803x-move-disable-WOL-to-specific-at8031-p.patch index eb9172b1cc..744866756a 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-02-net-phy-at803x-move-disable-WOL-to-specific-at8031-p.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-02-net-phy-at803x-move-disable-WOL-to-specific-at8031-p.patch @@ -17,8 +17,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -886,15 +886,6 @@ static int at803x_probe(struct phy_devic priv->is_fiber = true; break; diff --git a/target/linux/generic/backport-6.6/707-v6.8-03-net-phy-at803x-raname-hw_stats-functions-to-qca83xx-.patch b/target/linux/generic/backport-6.6/707-v6.8-03-net-phy-at803x-raname-hw_stats-functions-to-qca83xx-.patch index 5a9d1764f1..351d9781b2 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-03-net-phy-at803x-raname-hw_stats-functions-to-qca83xx-.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-03-net-phy-at803x-raname-hw_stats-functions-to-qca83xx-.patch @@ -18,8 +18,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 44 ++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 22 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -295,7 +295,7 @@ struct at803x_hw_stat { enum stat_access_type access_type; }; diff --git a/target/linux/generic/backport-6.6/707-v6.8-04-net-phy-at803x-move-qca83xx-specific-check-in-dedica.patch b/target/linux/generic/backport-6.6/707-v6.8-04-net-phy-at803x-move-qca83xx-specific-check-in-dedica.patch index f09142c5ed..4946c18ab5 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-04-net-phy-at803x-move-qca83xx-specific-check-in-dedica.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-04-net-phy-at803x-move-qca83xx-specific-check-in-dedica.patch @@ -17,8 +17,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 68 ++++++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 31 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -1623,27 +1623,26 @@ static int qca83xx_config_init(struct ph break; } diff --git a/target/linux/generic/backport-6.6/707-v6.8-05-net-phy-at803x-move-specific-DT-option-for-at8031-to.patch b/target/linux/generic/backport-6.6/707-v6.8-05-net-phy-at803x-move-specific-DT-option-for-at8031-to.patch index a5cc67a8c8..9f085f0260 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-05-net-phy-at803x-move-specific-DT-option-for-at8031-to.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-05-net-phy-at803x-move-specific-DT-option-for-at8031-to.patch @@ -14,8 +14,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 55 ++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 24 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -825,30 +825,6 @@ static int at803x_parse_dt(struct phy_de } } diff --git a/target/linux/generic/backport-6.6/707-v6.8-06-net-phy-at803x-move-specific-at8031-probe-mode-check.patch b/target/linux/generic/backport-6.6/707-v6.8-06-net-phy-at803x-move-specific-at8031-probe-mode-check.patch index 9e10e000e5..87ecb3b37b 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-06-net-phy-at803x-move-specific-at8031-probe-mode-check.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-06-net-phy-at803x-move-specific-at8031-probe-mode-check.patch @@ -14,8 +14,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -844,26 +844,6 @@ static int at803x_probe(struct phy_devic if (ret) return ret; diff --git a/target/linux/generic/backport-6.6/707-v6.8-07-net-phy-at803x-move-specific-at8031-config_init-to-d.patch b/target/linux/generic/backport-6.6/707-v6.8-07-net-phy-at803x-move-specific-at8031-config_init-to-d.patch index c9ef6df827..144edc987f 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-07-net-phy-at803x-move-specific-at8031-config_init-to-d.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-07-net-phy-at803x-move-specific-at8031-config_init-to-d.patch @@ -14,8 +14,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 45 ++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 20 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -951,27 +951,8 @@ static int at803x_hibernation_mode_confi static int at803x_config_init(struct phy_device *phydev) diff --git a/target/linux/generic/backport-6.6/707-v6.8-08-net-phy-at803x-move-specific-at8031-WOL-bits-to-dedi.patch b/target/linux/generic/backport-6.6/707-v6.8-08-net-phy-at803x-move-specific-at8031-WOL-bits-to-dedi.patch index 6746a4d43c..98f1635984 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-08-net-phy-at803x-move-specific-at8031-WOL-bits-to-dedi.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-08-net-phy-at803x-move-specific-at8031-WOL-bits-to-dedi.patch @@ -20,8 +20,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 42 ++++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 17 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -466,27 +466,11 @@ static int at803x_set_wol(struct phy_dev phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); diff --git a/target/linux/generic/backport-6.6/707-v6.8-09-net-phy-at803x-move-specific-at8031-config_intr-to-d.patch b/target/linux/generic/backport-6.6/707-v6.8-09-net-phy-at803x-move-specific-at8031-config_intr-to-d.patch index 0d284c3d24..0a2d0324ab 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-09-net-phy-at803x-move-specific-at8031-config_intr-to-d.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-09-net-phy-at803x-move-specific-at8031-config_intr-to-d.patch @@ -16,8 +16,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -990,7 +990,6 @@ static int at803x_ack_interrupt(struct p static int at803x_config_intr(struct phy_device *phydev) diff --git a/target/linux/generic/backport-6.6/707-v6.8-10-net-phy-at803x-make-at8031-related-DT-functions-name.patch b/target/linux/generic/backport-6.6/707-v6.8-10-net-phy-at803x-make-at8031-related-DT-functions-name.patch index 210949ea81..63cc046edf 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-10-net-phy-at803x-make-at8031-related-DT-functions-name.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-10-net-phy-at803x-make-at8031-related-DT-functions-name.patch @@ -14,8 +14,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -583,7 +583,7 @@ static int at803x_resume(struct phy_devi return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); } diff --git a/target/linux/generic/backport-6.6/707-v6.8-11-net-phy-at803x-move-at8031-functions-in-dedicated-se.patch b/target/linux/generic/backport-6.6/707-v6.8-11-net-phy-at803x-move-at8031-functions-in-dedicated-se.patch index 5856b59751..23a7aac5d4 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-11-net-phy-at803x-move-at8031-functions-in-dedicated-se.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-11-net-phy-at803x-move-at8031-functions-in-dedicated-se.patch @@ -13,8 +13,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 266 +++++++++++++++++++-------------------- 1 file changed, 133 insertions(+), 133 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -583,139 +583,6 @@ static int at803x_resume(struct phy_devi return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); } diff --git a/target/linux/generic/backport-6.6/707-v6.8-12-net-phy-at803x-move-at8035-specific-DT-parse-to-dedi.patch b/target/linux/generic/backport-6.6/707-v6.8-12-net-phy-at803x-move-at8035-specific-DT-parse-to-dedi.patch index 0a822c6d37..9a4f7fb5ae 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-12-net-phy-at803x-move-at8035-specific-DT-parse-to-dedi.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-12-net-phy-at803x-move-at8035-specific-DT-parse-to-dedi.patch @@ -22,8 +22,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 60 +++++++++++++++++++++++++++------------- 1 file changed, 41 insertions(+), 19 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -638,23 +638,6 @@ static int at803x_parse_dt(struct phy_de priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); diff --git a/target/linux/generic/backport-6.6/707-v6.8-13-net-phy-at803x-drop-specific-PHY-ID-check-from-cable.patch b/target/linux/generic/backport-6.6/707-v6.8-13-net-phy-at803x-drop-specific-PHY-ID-check-from-cable.patch index e1ba6ec2d0..2abfa11ac7 100644 --- a/target/linux/generic/backport-6.6/707-v6.8-13-net-phy-at803x-drop-specific-PHY-ID-check-from-cable.patch +++ b/target/linux/generic/backport-6.6/707-v6.8-13-net-phy-at803x-drop-specific-PHY-ID-check-from-cable.patch @@ -20,8 +20,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 95 +++++++++++++++++++++------------------- 1 file changed, 50 insertions(+), 45 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -1222,31 +1222,16 @@ static int at803x_cdt_fault_length(u16 s return (dt * 824) / 10; } diff --git a/target/linux/generic/backport-6.6/708-v6.8-01-net-phy-at803x-move-specific-qca808x-config_aneg-to-.patch b/target/linux/generic/backport-6.6/708-v6.8-01-net-phy-at803x-move-specific-qca808x-config_aneg-to-.patch index 0bb3673c02..0c7f3b17b8 100644 --- a/target/linux/generic/backport-6.6/708-v6.8-01-net-phy-at803x-move-specific-qca808x-config_aneg-to-.patch +++ b/target/linux/generic/backport-6.6/708-v6.8-01-net-phy-at803x-move-specific-qca808x-config_aneg-to-.patch @@ -13,8 +13,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 66 ++++++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 26 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -1045,9 +1045,8 @@ static int at803x_config_mdix(struct phy FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); } diff --git a/target/linux/generic/backport-6.6/708-v6.8-02-net-phy-at803x-make-read-specific-status-function-mo.patch b/target/linux/generic/backport-6.6/708-v6.8-02-net-phy-at803x-make-read-specific-status-function-mo.patch index 54ca3bdfc8..a52780032b 100644 --- a/target/linux/generic/backport-6.6/708-v6.8-02-net-phy-at803x-make-read-specific-status-function-mo.patch +++ b/target/linux/generic/backport-6.6/708-v6.8-02-net-phy-at803x-make-read-specific-status-function-mo.patch @@ -18,8 +18,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -301,6 +301,11 @@ static struct at803x_hw_stat qca83xx_hw_ { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, }; diff --git a/target/linux/generic/backport-6.6/709-v6.8-01-net-phy-at803x-remove-extra-space-after-cast.patch b/target/linux/generic/backport-6.6/709-v6.8-01-net-phy-at803x-remove-extra-space-after-cast.patch index 8097a33e49..5bd656fe5b 100644 --- a/target/linux/generic/backport-6.6/709-v6.8-01-net-phy-at803x-remove-extra-space-after-cast.patch +++ b/target/linux/generic/backport-6.6/709-v6.8-01-net-phy-at803x-remove-extra-space-after-cast.patch @@ -14,8 +14,8 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com> drivers/net/phy/at803x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -462,7 +462,7 @@ static int at803x_set_wol(struct phy_dev if (!ndev) return -ENODEV; diff --git a/target/linux/generic/backport-6.6/709-v6.8-02-net-phy-at803x-replace-msleep-1-with-usleep_range.patch b/target/linux/generic/backport-6.6/709-v6.8-02-net-phy-at803x-replace-msleep-1-with-usleep_range.patch index b8d4591087..e780df7cdc 100644 --- a/target/linux/generic/backport-6.6/709-v6.8-02-net-phy-at803x-replace-msleep-1-with-usleep_range.patch +++ b/target/linux/generic/backport-6.6/709-v6.8-02-net-phy-at803x-replace-msleep-1-with-usleep_range.patch @@ -13,8 +13,8 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com> drivers/net/phy/at803x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -916,9 +916,9 @@ static void at803x_link_change_notify(st at803x_context_save(phydev, &context); diff --git a/target/linux/generic/backport-6.6/710-v6.8-net-phy-at803x-better-align-function-varibles-to-ope.patch b/target/linux/generic/backport-6.6/710-v6.8-net-phy-at803x-better-align-function-varibles-to-ope.patch index 776b7bb43f..f69936719e 100644 --- a/target/linux/generic/backport-6.6/710-v6.8-net-phy-at803x-better-align-function-varibles-to-ope.patch +++ b/target/linux/generic/backport-6.6/710-v6.8-net-phy-at803x-better-align-function-varibles-to-ope.patch @@ -17,8 +17,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 67 ++++++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 30 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -1781,27 +1781,27 @@ static int qca808x_phy_fast_retrain_conf return ret; diff --git a/target/linux/generic/backport-6.6/711-v6.8-01-net-phy-at803x-generalize-cdt-fault-length-function.patch b/target/linux/generic/backport-6.6/711-v6.8-01-net-phy-at803x-generalize-cdt-fault-length-function.patch index d7196da46e..1c45c36041 100644 --- a/target/linux/generic/backport-6.6/711-v6.8-01-net-phy-at803x-generalize-cdt-fault-length-function.patch +++ b/target/linux/generic/backport-6.6/711-v6.8-01-net-phy-at803x-generalize-cdt-fault-length-function.patch @@ -14,8 +14,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -1192,10 +1192,8 @@ static bool at803x_cdt_fault_length_vali return false; } diff --git a/target/linux/generic/backport-6.6/711-v6.8-02-net-phy-at803x-refactor-qca808x-cable-test-get-statu.patch b/target/linux/generic/backport-6.6/711-v6.8-02-net-phy-at803x-refactor-qca808x-cable-test-get-statu.patch index 5d38fe7e91..fb1b435512 100644 --- a/target/linux/generic/backport-6.6/711-v6.8-02-net-phy-at803x-refactor-qca808x-cable-test-get-statu.patch +++ b/target/linux/generic/backport-6.6/711-v6.8-02-net-phy-at803x-refactor-qca808x-cable-test-get-statu.patch @@ -17,8 +17,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 80 ++++++++++++++++++++++++---------------- 1 file changed, 49 insertions(+), 31 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -2035,10 +2035,43 @@ static int qca808x_cable_test_start(stru return 0; } diff --git a/target/linux/generic/backport-6.6/711-v6.8-03-net-phy-at803x-add-support-for-cdt-cross-short-test-.patch b/target/linux/generic/backport-6.6/711-v6.8-03-net-phy-at803x-add-support-for-cdt-cross-short-test-.patch index d5793860a9..ce7c1664a9 100644 --- a/target/linux/generic/backport-6.6/711-v6.8-03-net-phy-at803x-add-support-for-cdt-cross-short-test-.patch +++ b/target/linux/generic/backport-6.6/711-v6.8-03-net-phy-at803x-add-support-for-cdt-cross-short-test-.patch @@ -20,8 +20,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 86 ++++++++++++++++++++++++++++++++-------- 1 file changed, 69 insertions(+), 17 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -254,6 +254,7 @@ #define QCA808X_CDT_ENABLE_TEST BIT(15) diff --git a/target/linux/generic/backport-6.6/711-v6.8-04-net-phy-at803x-make-read_status-more-generic.patch b/target/linux/generic/backport-6.6/711-v6.8-04-net-phy-at803x-make-read_status-more-generic.patch index c146e502fe..89a69fff3e 100644 --- a/target/linux/generic/backport-6.6/711-v6.8-04-net-phy-at803x-make-read_status-more-generic.patch +++ b/target/linux/generic/backport-6.6/711-v6.8-04-net-phy-at803x-make-read_status-more-generic.patch @@ -17,8 +17,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net> drivers/net/phy/at803x.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -1020,13 +1020,9 @@ static int at803x_read_specific_status(s static int at803x_read_status(struct phy_device *phydev) diff --git a/target/linux/generic/backport-6.6/712-v6.9-net-phy-at803x-add-LED-support-for-qca808x.patch b/target/linux/generic/backport-6.6/712-v6.9-net-phy-at803x-add-LED-support-for-qca808x.patch index 36675e7588..d212bf927e 100644 --- a/target/linux/generic/backport-6.6/712-v6.9-net-phy-at803x-add-LED-support-for-qca808x.patch +++ b/target/linux/generic/backport-6.6/712-v6.9-net-phy-at803x-add-LED-support-for-qca808x.patch @@ -42,8 +42,8 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org> drivers/net/phy/at803x.c | 327 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 327 insertions(+) ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c +--- a/drivers/net/phy/qcom/at803x.c ++++ b/drivers/net/phy/qcom/at803x.c @@ -301,6 +301,87 @@ /* Added for reference of existence but should be handled by wait_for_completion already */ #define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3)) diff --git a/target/linux/generic/backport-6.6/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch b/target/linux/generic/backport-6.6/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch deleted file mode 100644 index ba89ecdb3c..0000000000 --- a/target/linux/generic/backport-6.6/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch +++ /dev/null @@ -1,5598 +0,0 @@ -From 9e56ff53b4115875667760445b028357848b4748 Mon Sep 17 00:00:00 2001 -From: Christian Marangi <ansuelsmth@gmail.com> -Date: Mon, 29 Jan 2024 15:15:19 +0100 -Subject: [PATCH 1/5] net: phy: move at803x PHY driver to dedicated directory - -In preparation for addition of other Qcom PHY and to tidy things up, -move the at803x PHY driver to dedicated directory. - -The same order in the Kconfig selection is saved. - -Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> -Reviewed-by: Andrew Lunn <andrew@lunn.ch> -Link: https://lore.kernel.org/r/20240129141600.2592-2-ansuelsmth@gmail.com -Signed-off-by: Jakub Kicinski <kuba@kernel.org> ---- - drivers/net/phy/Kconfig | 7 +------ - drivers/net/phy/Makefile | 2 +- - drivers/net/phy/qcom/Kconfig | 7 +++++++ - drivers/net/phy/qcom/Makefile | 2 ++ - drivers/net/phy/{ => qcom}/at803x.c | 0 - 5 files changed, 11 insertions(+), 7 deletions(-) - create mode 100644 drivers/net/phy/qcom/Kconfig - create mode 100644 drivers/net/phy/qcom/Makefile - rename drivers/net/phy/{ => qcom}/at803x.c (100%) - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -318,12 +318,7 @@ config NCN26000_PHY - Currently supports the NCN26000 10BASE-T1S Industrial PHY - with MII interface. - --config AT803X_PHY -- tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs" -- depends on REGULATOR -- help -- Currently supports the AR8030, AR8031, AR8033, AR8035 and internal -- QCA8337(Internal qca8k PHY) model -+source "drivers/net/phy/qcom/Kconfig" - - config QSEMI_PHY - tristate "Quality Semiconductor PHYs" ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -36,7 +36,6 @@ obj-$(CONFIG_ADIN_PHY) += adin.o - obj-$(CONFIG_ADIN1100_PHY) += adin1100.o - obj-$(CONFIG_AMD_PHY) += amd.o - obj-$(CONFIG_AQUANTIA_PHY) += aquantia/ --obj-$(CONFIG_AT803X_PHY) += at803x.o - obj-$(CONFIG_AX88796B_PHY) += ax88796b.o - obj-$(CONFIG_BCM54140_PHY) += bcm54140.o - obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o -@@ -82,6 +81,7 @@ obj-$(CONFIG_NCN26000_PHY) += ncn26000.o - obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o - obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o - obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o -+obj-y += qcom/ - obj-$(CONFIG_QSEMI_PHY) += qsemi.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o ---- /dev/null -+++ b/drivers/net/phy/qcom/Kconfig -@@ -0,0 +1,7 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+config AT803X_PHY -+ tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs" -+ depends on REGULATOR -+ help -+ Currently supports the AR8030, AR8031, AR8033, AR8035 and internal -+ QCA8337(Internal qca8k PHY) model ---- /dev/null -+++ b/drivers/net/phy/qcom/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_AT803X_PHY) += at803x.o ---- a/drivers/net/phy/at803x.c -+++ /dev/null -@@ -1,2759 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0+ --/* -- * drivers/net/phy/at803x.c -- * -- * Driver for Qualcomm Atheros AR803x PHY -- * -- * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> -- */ -- --#include <linux/phy.h> --#include <linux/module.h> --#include <linux/string.h> --#include <linux/netdevice.h> --#include <linux/etherdevice.h> --#include <linux/ethtool_netlink.h> --#include <linux/bitfield.h> --#include <linux/regulator/of_regulator.h> --#include <linux/regulator/driver.h> --#include <linux/regulator/consumer.h> --#include <linux/of.h> --#include <linux/phylink.h> --#include <linux/sfp.h> --#include <dt-bindings/net/qca-ar803x.h> -- --#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 --#define AT803X_SFC_ASSERT_CRS BIT(11) --#define AT803X_SFC_FORCE_LINK BIT(10) --#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) --#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 --#define AT803X_SFC_MANUAL_MDIX 0x1 --#define AT803X_SFC_MANUAL_MDI 0x0 --#define AT803X_SFC_SQE_TEST BIT(2) --#define AT803X_SFC_POLARITY_REVERSAL BIT(1) --#define AT803X_SFC_DISABLE_JABBER BIT(0) -- --#define AT803X_SPECIFIC_STATUS 0x11 --#define AT803X_SS_SPEED_MASK GENMASK(15, 14) --#define AT803X_SS_SPEED_1000 2 --#define AT803X_SS_SPEED_100 1 --#define AT803X_SS_SPEED_10 0 --#define AT803X_SS_DUPLEX BIT(13) --#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) --#define AT803X_SS_MDIX BIT(6) -- --#define QCA808X_SS_SPEED_MASK GENMASK(9, 7) --#define QCA808X_SS_SPEED_2500 4 -- --#define AT803X_INTR_ENABLE 0x12 --#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) --#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) --#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) --#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) --#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) --#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) --#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) --#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) --#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) --#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) --#define AT803X_INTR_ENABLE_WOL BIT(0) -- --#define AT803X_INTR_STATUS 0x13 -- --#define AT803X_SMART_SPEED 0x14 --#define AT803X_SMART_SPEED_ENABLE BIT(5) --#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) --#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) --#define AT803X_CDT 0x16 --#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) --#define AT803X_CDT_ENABLE_TEST BIT(0) --#define AT803X_CDT_STATUS 0x1c --#define AT803X_CDT_STATUS_STAT_NORMAL 0 --#define AT803X_CDT_STATUS_STAT_SHORT 1 --#define AT803X_CDT_STATUS_STAT_OPEN 2 --#define AT803X_CDT_STATUS_STAT_FAIL 3 --#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) --#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) --#define AT803X_LED_CONTROL 0x18 -- --#define AT803X_PHY_MMD3_WOL_CTRL 0x8012 --#define AT803X_WOL_EN BIT(5) --#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C --#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B --#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A --#define AT803X_REG_CHIP_CONFIG 0x1f --#define AT803X_BT_BX_REG_SEL 0x8000 -- --#define AT803X_DEBUG_ADDR 0x1D --#define AT803X_DEBUG_DATA 0x1E -- --#define AT803X_MODE_CFG_MASK 0x0F --#define AT803X_MODE_CFG_BASET_RGMII 0x00 --#define AT803X_MODE_CFG_BASET_SGMII 0x01 --#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 --#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 --#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 --#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 --#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 --#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 --#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B --#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E --#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F -- --#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ --#define AT803X_PSSR_MR_AN_COMPLETE 0x0200 -- --#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 --#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) --#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) --#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) -- --#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 --#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) -- --#define AT803X_DEBUG_REG_HIB_CTRL 0x0b --#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) --#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) --#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) -- --#define AT803X_DEBUG_REG_3C 0x3C -- --#define AT803X_DEBUG_REG_GREEN 0x3D --#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) -- --#define AT803X_DEBUG_REG_1F 0x1F --#define AT803X_DEBUG_PLL_ON BIT(2) --#define AT803X_DEBUG_RGMII_1V8 BIT(3) -- --#define MDIO_AZ_DEBUG 0x800D -- --/* AT803x supports either the XTAL input pad, an internal PLL or the -- * DSP as clock reference for the clock output pad. The XTAL reference -- * is only used for 25 MHz output, all other frequencies need the PLL. -- * The DSP as a clock reference is used in synchronous ethernet -- * applications. -- * -- * By default the PLL is only enabled if there is a link. Otherwise -- * the PHY will go into low power state and disabled the PLL. You can -- * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always -- * enabled. -- */ --#define AT803X_MMD7_CLK25M 0x8016 --#define AT803X_CLK_OUT_MASK GENMASK(4, 2) --#define AT803X_CLK_OUT_25MHZ_XTAL 0 --#define AT803X_CLK_OUT_25MHZ_DSP 1 --#define AT803X_CLK_OUT_50MHZ_PLL 2 --#define AT803X_CLK_OUT_50MHZ_DSP 3 --#define AT803X_CLK_OUT_62_5MHZ_PLL 4 --#define AT803X_CLK_OUT_62_5MHZ_DSP 5 --#define AT803X_CLK_OUT_125MHZ_PLL 6 --#define AT803X_CLK_OUT_125MHZ_DSP 7 -- --/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask -- * but doesn't support choosing between XTAL/PLL and DSP. -- */ --#define AT8035_CLK_OUT_MASK GENMASK(4, 3) -- --#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) --#define AT803X_CLK_OUT_STRENGTH_FULL 0 --#define AT803X_CLK_OUT_STRENGTH_HALF 1 --#define AT803X_CLK_OUT_STRENGTH_QUARTER 2 -- --#define AT803X_DEFAULT_DOWNSHIFT 5 --#define AT803X_MIN_DOWNSHIFT 2 --#define AT803X_MAX_DOWNSHIFT 9 -- --#define AT803X_MMD3_SMARTEEE_CTL1 0x805b --#define AT803X_MMD3_SMARTEEE_CTL2 0x805c --#define AT803X_MMD3_SMARTEEE_CTL3 0x805d --#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) -- --#define ATH9331_PHY_ID 0x004dd041 --#define ATH8030_PHY_ID 0x004dd076 --#define ATH8031_PHY_ID 0x004dd074 --#define ATH8032_PHY_ID 0x004dd023 --#define ATH8035_PHY_ID 0x004dd072 --#define AT8030_PHY_ID_MASK 0xffffffef -- --#define QCA8081_PHY_ID 0x004dd101 -- --#define QCA8327_A_PHY_ID 0x004dd033 --#define QCA8327_B_PHY_ID 0x004dd034 --#define QCA8337_PHY_ID 0x004dd036 --#define QCA9561_PHY_ID 0x004dd042 --#define QCA8K_PHY_ID_MASK 0xffffffff -- --#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) -- --#define AT803X_PAGE_FIBER 0 --#define AT803X_PAGE_COPPER 1 -- --/* don't turn off internal PLL */ --#define AT803X_KEEP_PLL_ENABLED BIT(0) --#define AT803X_DISABLE_SMARTEEE BIT(1) -- --/* disable hibernation mode */ --#define AT803X_DISABLE_HIBERNATION_MODE BIT(2) -- --/* ADC threshold */ --#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 --#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) --#define QCA808X_ADC_THRESHOLD_80MV 0 --#define QCA808X_ADC_THRESHOLD_100MV 0xf0 --#define QCA808X_ADC_THRESHOLD_200MV 0x0f --#define QCA808X_ADC_THRESHOLD_300MV 0xff -- --/* CLD control */ --#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 --#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) --#define QCA808X_8023AZ_AFE_EN 0x90 -- --/* AZ control */ --#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 --#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 -- --#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 --#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 -- --#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E --#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 -- --#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E --#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 -- --#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 --#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 -- --#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c --#define QCA808X_TOP_OPTION1_DATA 0x0 -- --#define QCA808X_PHY_MMD3_DEBUG_1 0xa100 --#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 --#define QCA808X_PHY_MMD3_DEBUG_2 0xa101 --#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad --#define QCA808X_PHY_MMD3_DEBUG_3 0xa103 --#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 --#define QCA808X_PHY_MMD3_DEBUG_4 0xa105 --#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 --#define QCA808X_PHY_MMD3_DEBUG_5 0xa106 --#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 --#define QCA808X_PHY_MMD3_DEBUG_6 0xa011 --#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 -- --/* master/slave seed config */ --#define QCA808X_PHY_DEBUG_LOCAL_SEED 9 --#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) --#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) --#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 -- --/* Hibernation yields lower power consumpiton in contrast with normal operation mode. -- * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. -- */ --#define QCA808X_DBG_AN_TEST 0xb --#define QCA808X_HIBERNATION_EN BIT(15) -- --#define QCA808X_CDT_ENABLE_TEST BIT(15) --#define QCA808X_CDT_INTER_CHECK_DIS BIT(13) --#define QCA808X_CDT_STATUS BIT(11) --#define QCA808X_CDT_LENGTH_UNIT BIT(10) -- --#define QCA808X_MMD3_CDT_STATUS 0x8064 --#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 --#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 --#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 --#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 --#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8) --#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0) -- --#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) --#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) --#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) --#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) -- --#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0) --#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0) --#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1) --#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2) --#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3) -- --#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2) --#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1) --#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2) --#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3) -- --/* NORMAL are MDI with type set to 0 */ --#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1 --#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ -- QCA808X_CDT_STATUS_STAT_MDI1) --#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ -- QCA808X_CDT_STATUS_STAT_MDI1) --#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2 --#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ -- QCA808X_CDT_STATUS_STAT_MDI2) --#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ -- QCA808X_CDT_STATUS_STAT_MDI2) --#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3 --#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ -- QCA808X_CDT_STATUS_STAT_MDI3) --#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ -- QCA808X_CDT_STATUS_STAT_MDI3) -- --/* Added for reference of existence but should be handled by wait_for_completion already */ --#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3)) -- --#define QCA808X_MMD7_LED_GLOBAL 0x8073 --#define QCA808X_LED_BLINK_1 GENMASK(11, 6) --#define QCA808X_LED_BLINK_2 GENMASK(5, 0) --/* Values are the same for both BLINK_1 and BLINK_2 */ --#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3) --#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0) --#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1) --#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2) --#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3) --#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4) --#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5) --#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6) --#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7) --#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0) --#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0) --#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1) --#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2) --#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3) --#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4) --#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5) --#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6) --#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7) -- --#define QCA808X_MMD7_LED2_CTRL 0x8074 --#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075 --#define QCA808X_MMD7_LED1_CTRL 0x8076 --#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077 --#define QCA808X_MMD7_LED0_CTRL 0x8078 --#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2)) -- --/* LED hw control pattern is the same for every LED */ --#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0) --#define QCA808X_LED_SPEED2500_ON BIT(15) --#define QCA808X_LED_SPEED2500_BLINK BIT(14) --/* Follow blink trigger even if duplex or speed condition doesn't match */ --#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13) --#define QCA808X_LED_FULL_DUPLEX_ON BIT(12) --#define QCA808X_LED_HALF_DUPLEX_ON BIT(11) --#define QCA808X_LED_TX_BLINK BIT(10) --#define QCA808X_LED_RX_BLINK BIT(9) --#define QCA808X_LED_TX_ON_10MS BIT(8) --#define QCA808X_LED_RX_ON_10MS BIT(7) --#define QCA808X_LED_SPEED1000_ON BIT(6) --#define QCA808X_LED_SPEED100_ON BIT(5) --#define QCA808X_LED_SPEED10_ON BIT(4) --#define QCA808X_LED_COLLISION_BLINK BIT(3) --#define QCA808X_LED_SPEED1000_BLINK BIT(2) --#define QCA808X_LED_SPEED100_BLINK BIT(1) --#define QCA808X_LED_SPEED10_BLINK BIT(0) -- --#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079 --#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2)) -- --/* LED force ctrl is the same for every LED -- * No documentation exist for this, not even internal one -- * with NDA as QCOM gives only info about configuring -- * hw control pattern rules and doesn't indicate any way -- * to force the LED to specific mode. -- * These define comes from reverse and testing and maybe -- * lack of some info or some info are not entirely correct. -- * For the basic LED control and hw control these finding -- * are enough to support LED control in all the required APIs. -- * -- * On doing some comparison with implementation with qca807x, -- * it was found that it's 1:1 equal to it and confirms all the -- * reverse done. It was also found further specification with the -- * force mode and the blink modes. -- */ --#define QCA808X_LED_FORCE_EN BIT(15) --#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13) --#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3) --#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2) --#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1) --#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0) -- --#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a --/* QSDK sets by default 0x46 to this reg that sets BIT 6 for -- * LED to active high. It's not clear what BIT 3 and BIT 4 does. -- */ --#define QCA808X_LED_ACTIVE_HIGH BIT(6) -- --/* QCA808X 1G chip type */ --#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d --#define QCA808X_PHY_CHIP_TYPE_1G BIT(0) -- --#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 --#define QCA8081_PHY_FIFO_RSTN BIT(11) -- --MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); --MODULE_AUTHOR("Matus Ujhelyi"); --MODULE_LICENSE("GPL"); -- --enum stat_access_type { -- PHY, -- MMD --}; -- --struct at803x_hw_stat { -- const char *string; -- u8 reg; -- u32 mask; -- enum stat_access_type access_type; --}; -- --static struct at803x_hw_stat qca83xx_hw_stats[] = { -- { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, -- { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, -- { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, --}; -- --struct at803x_ss_mask { -- u16 speed_mask; -- u8 speed_shift; --}; -- --struct at803x_priv { -- int flags; -- u16 clk_25m_reg; -- u16 clk_25m_mask; -- u8 smarteee_lpi_tw_1g; -- u8 smarteee_lpi_tw_100m; -- bool is_fiber; -- bool is_1000basex; -- struct regulator_dev *vddio_rdev; -- struct regulator_dev *vddh_rdev; -- u64 stats[ARRAY_SIZE(qca83xx_hw_stats)]; -- int led_polarity_mode; --}; -- --struct at803x_context { -- u16 bmcr; -- u16 advertise; -- u16 control1000; -- u16 int_enable; -- u16 smart_speed; -- u16 led_control; --}; -- --static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) --{ -- int ret; -- -- ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); -- if (ret < 0) -- return ret; -- -- return phy_write(phydev, AT803X_DEBUG_DATA, data); --} -- --static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) --{ -- int ret; -- -- ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); -- if (ret < 0) -- return ret; -- -- return phy_read(phydev, AT803X_DEBUG_DATA); --} -- --static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, -- u16 clear, u16 set) --{ -- u16 val; -- int ret; -- -- ret = at803x_debug_reg_read(phydev, reg); -- if (ret < 0) -- return ret; -- -- val = ret & 0xffff; -- val &= ~clear; -- val |= set; -- -- return phy_write(phydev, AT803X_DEBUG_DATA, val); --} -- --static int at803x_write_page(struct phy_device *phydev, int page) --{ -- int mask; -- int set; -- -- if (page == AT803X_PAGE_COPPER) { -- set = AT803X_BT_BX_REG_SEL; -- mask = 0; -- } else { -- set = 0; -- mask = AT803X_BT_BX_REG_SEL; -- } -- -- return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); --} -- --static int at803x_read_page(struct phy_device *phydev) --{ -- int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); -- -- if (ccr < 0) -- return ccr; -- -- if (ccr & AT803X_BT_BX_REG_SEL) -- return AT803X_PAGE_COPPER; -- -- return AT803X_PAGE_FIBER; --} -- --static int at803x_enable_rx_delay(struct phy_device *phydev) --{ -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, -- AT803X_DEBUG_RX_CLK_DLY_EN); --} -- --static int at803x_enable_tx_delay(struct phy_device *phydev) --{ -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, -- AT803X_DEBUG_TX_CLK_DLY_EN); --} -- --static int at803x_disable_rx_delay(struct phy_device *phydev) --{ -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, -- AT803X_DEBUG_RX_CLK_DLY_EN, 0); --} -- --static int at803x_disable_tx_delay(struct phy_device *phydev) --{ -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, -- AT803X_DEBUG_TX_CLK_DLY_EN, 0); --} -- --/* save relevant PHY registers to private copy */ --static void at803x_context_save(struct phy_device *phydev, -- struct at803x_context *context) --{ -- context->bmcr = phy_read(phydev, MII_BMCR); -- context->advertise = phy_read(phydev, MII_ADVERTISE); -- context->control1000 = phy_read(phydev, MII_CTRL1000); -- context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); -- context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); -- context->led_control = phy_read(phydev, AT803X_LED_CONTROL); --} -- --/* restore relevant PHY registers from private copy */ --static void at803x_context_restore(struct phy_device *phydev, -- const struct at803x_context *context) --{ -- phy_write(phydev, MII_BMCR, context->bmcr); -- phy_write(phydev, MII_ADVERTISE, context->advertise); -- phy_write(phydev, MII_CTRL1000, context->control1000); -- phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); -- phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); -- phy_write(phydev, AT803X_LED_CONTROL, context->led_control); --} -- --static int at803x_set_wol(struct phy_device *phydev, -- struct ethtool_wolinfo *wol) --{ -- int ret, irq_enabled; -- -- if (wol->wolopts & WAKE_MAGIC) { -- struct net_device *ndev = phydev->attached_dev; -- const u8 *mac; -- unsigned int i; -- static const unsigned int offsets[] = { -- AT803X_LOC_MAC_ADDR_32_47_OFFSET, -- AT803X_LOC_MAC_ADDR_16_31_OFFSET, -- AT803X_LOC_MAC_ADDR_0_15_OFFSET, -- }; -- -- if (!ndev) -- return -ENODEV; -- -- mac = (const u8 *)ndev->dev_addr; -- -- if (!is_valid_ether_addr(mac)) -- return -EINVAL; -- -- for (i = 0; i < 3; i++) -- phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], -- mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); -- -- /* Enable WOL interrupt */ -- ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); -- if (ret) -- return ret; -- } else { -- /* Disable WOL interrupt */ -- ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); -- if (ret) -- return ret; -- } -- -- /* Clear WOL status */ -- ret = phy_read(phydev, AT803X_INTR_STATUS); -- if (ret < 0) -- return ret; -- -- /* Check if there are other interrupts except for WOL triggered when PHY is -- * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can -- * be passed up to the interrupt PIN. -- */ -- irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); -- if (irq_enabled < 0) -- return irq_enabled; -- -- irq_enabled &= ~AT803X_INTR_ENABLE_WOL; -- if (ret & irq_enabled && !phy_polling_mode(phydev)) -- phy_trigger_machine(phydev); -- -- return 0; --} -- --static void at803x_get_wol(struct phy_device *phydev, -- struct ethtool_wolinfo *wol) --{ -- int value; -- -- wol->supported = WAKE_MAGIC; -- wol->wolopts = 0; -- -- value = phy_read(phydev, AT803X_INTR_ENABLE); -- if (value < 0) -- return; -- -- if (value & AT803X_INTR_ENABLE_WOL) -- wol->wolopts |= WAKE_MAGIC; --} -- --static int qca83xx_get_sset_count(struct phy_device *phydev) --{ -- return ARRAY_SIZE(qca83xx_hw_stats); --} -- --static void qca83xx_get_strings(struct phy_device *phydev, u8 *data) --{ -- int i; -- -- for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) { -- strscpy(data + i * ETH_GSTRING_LEN, -- qca83xx_hw_stats[i].string, ETH_GSTRING_LEN); -- } --} -- --static u64 qca83xx_get_stat(struct phy_device *phydev, int i) --{ -- struct at803x_hw_stat stat = qca83xx_hw_stats[i]; -- struct at803x_priv *priv = phydev->priv; -- int val; -- u64 ret; -- -- if (stat.access_type == MMD) -- val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); -- else -- val = phy_read(phydev, stat.reg); -- -- if (val < 0) { -- ret = U64_MAX; -- } else { -- val = val & stat.mask; -- priv->stats[i] += val; -- ret = priv->stats[i]; -- } -- -- return ret; --} -- --static void qca83xx_get_stats(struct phy_device *phydev, -- struct ethtool_stats *stats, u64 *data) --{ -- int i; -- -- for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) -- data[i] = qca83xx_get_stat(phydev, i); --} -- --static int at803x_suspend(struct phy_device *phydev) --{ -- int value; -- int wol_enabled; -- -- value = phy_read(phydev, AT803X_INTR_ENABLE); -- wol_enabled = value & AT803X_INTR_ENABLE_WOL; -- -- if (wol_enabled) -- value = BMCR_ISOLATE; -- else -- value = BMCR_PDOWN; -- -- phy_modify(phydev, MII_BMCR, 0, value); -- -- return 0; --} -- --static int at803x_resume(struct phy_device *phydev) --{ -- return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); --} -- --static int at803x_parse_dt(struct phy_device *phydev) --{ -- struct device_node *node = phydev->mdio.dev.of_node; -- struct at803x_priv *priv = phydev->priv; -- u32 freq, strength, tw; -- unsigned int sel; -- int ret; -- -- if (!IS_ENABLED(CONFIG_OF_MDIO)) -- return 0; -- -- if (of_property_read_bool(node, "qca,disable-smarteee")) -- priv->flags |= AT803X_DISABLE_SMARTEEE; -- -- if (of_property_read_bool(node, "qca,disable-hibernation-mode")) -- priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; -- -- if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { -- if (!tw || tw > 255) { -- phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); -- return -EINVAL; -- } -- priv->smarteee_lpi_tw_1g = tw; -- } -- -- if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { -- if (!tw || tw > 255) { -- phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); -- return -EINVAL; -- } -- priv->smarteee_lpi_tw_100m = tw; -- } -- -- ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); -- if (!ret) { -- switch (freq) { -- case 25000000: -- sel = AT803X_CLK_OUT_25MHZ_XTAL; -- break; -- case 50000000: -- sel = AT803X_CLK_OUT_50MHZ_PLL; -- break; -- case 62500000: -- sel = AT803X_CLK_OUT_62_5MHZ_PLL; -- break; -- case 125000000: -- sel = AT803X_CLK_OUT_125MHZ_PLL; -- break; -- default: -- phydev_err(phydev, "invalid qca,clk-out-frequency\n"); -- return -EINVAL; -- } -- -- priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); -- priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; -- } -- -- ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); -- if (!ret) { -- priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; -- switch (strength) { -- case AR803X_STRENGTH_FULL: -- priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; -- break; -- case AR803X_STRENGTH_HALF: -- priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; -- break; -- case AR803X_STRENGTH_QUARTER: -- priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; -- break; -- default: -- phydev_err(phydev, "invalid qca,clk-out-strength\n"); -- return -EINVAL; -- } -- } -- -- return 0; --} -- --static int at803x_probe(struct phy_device *phydev) --{ -- struct device *dev = &phydev->mdio.dev; -- struct at803x_priv *priv; -- int ret; -- -- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -- if (!priv) -- return -ENOMEM; -- -- /* Init LED polarity mode to -1 */ -- priv->led_polarity_mode = -1; -- -- phydev->priv = priv; -- -- ret = at803x_parse_dt(phydev); -- if (ret) -- return ret; -- -- return 0; --} -- --static int at803x_get_features(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- int err; -- -- err = genphy_read_abilities(phydev); -- if (err) -- return err; -- -- if (phydev->drv->phy_id != ATH8031_PHY_ID) -- return 0; -- -- /* AR8031/AR8033 have different status registers -- * for copper and fiber operation. However, the -- * extended status register is the same for both -- * operation modes. -- * -- * As a result of that, ESTATUS_1000_XFULL is set -- * to 1 even when operating in copper TP mode. -- * -- * Remove this mode from the supported link modes -- * when not operating in 1000BaseX mode. -- */ -- if (!priv->is_1000basex) -- linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, -- phydev->supported); -- -- return 0; --} -- --static int at803x_smarteee_config(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- u16 mask = 0, val = 0; -- int ret; -- -- if (priv->flags & AT803X_DISABLE_SMARTEEE) -- return phy_modify_mmd(phydev, MDIO_MMD_PCS, -- AT803X_MMD3_SMARTEEE_CTL3, -- AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); -- -- if (priv->smarteee_lpi_tw_1g) { -- mask |= 0xff00; -- val |= priv->smarteee_lpi_tw_1g << 8; -- } -- if (priv->smarteee_lpi_tw_100m) { -- mask |= 0x00ff; -- val |= priv->smarteee_lpi_tw_100m; -- } -- if (!mask) -- return 0; -- -- ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, -- mask, val); -- if (ret) -- return ret; -- -- return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, -- AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, -- AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); --} -- --static int at803x_clk_out_config(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- -- if (!priv->clk_25m_mask) -- return 0; -- -- return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, -- priv->clk_25m_mask, priv->clk_25m_reg); --} -- --static int at8031_pll_config(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- -- /* The default after hardware reset is PLL OFF. After a soft reset, the -- * values are retained. -- */ -- if (priv->flags & AT803X_KEEP_PLL_ENABLED) -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, -- 0, AT803X_DEBUG_PLL_ON); -- else -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, -- AT803X_DEBUG_PLL_ON, 0); --} -- --static int at803x_hibernation_mode_config(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- -- /* The default after hardware reset is hibernation mode enabled. After -- * software reset, the value is retained. -- */ -- if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) -- return 0; -- -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, -- AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); --} -- --static int at803x_config_init(struct phy_device *phydev) --{ -- int ret; -- -- /* The RX and TX delay default is: -- * after HW reset: RX delay enabled and TX delay disabled -- * after SW reset: RX delay enabled, while TX delay retains the -- * value before reset. -- */ -- if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || -- phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) -- ret = at803x_enable_rx_delay(phydev); -- else -- ret = at803x_disable_rx_delay(phydev); -- if (ret < 0) -- return ret; -- -- if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || -- phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) -- ret = at803x_enable_tx_delay(phydev); -- else -- ret = at803x_disable_tx_delay(phydev); -- if (ret < 0) -- return ret; -- -- ret = at803x_smarteee_config(phydev); -- if (ret < 0) -- return ret; -- -- ret = at803x_clk_out_config(phydev); -- if (ret < 0) -- return ret; -- -- ret = at803x_hibernation_mode_config(phydev); -- if (ret < 0) -- return ret; -- -- /* Ar803x extended next page bit is enabled by default. Cisco -- * multigig switches read this bit and attempt to negotiate 10Gbps -- * rates even if the next page bit is disabled. This is incorrect -- * behaviour but we still need to accommodate it. XNP is only needed -- * for 10Gbps support, so disable XNP. -- */ -- return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); --} -- --static int at803x_ack_interrupt(struct phy_device *phydev) --{ -- int err; -- -- err = phy_read(phydev, AT803X_INTR_STATUS); -- -- return (err < 0) ? err : 0; --} -- --static int at803x_config_intr(struct phy_device *phydev) --{ -- int err; -- int value; -- -- value = phy_read(phydev, AT803X_INTR_ENABLE); -- -- if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { -- /* Clear any pending interrupts */ -- err = at803x_ack_interrupt(phydev); -- if (err) -- return err; -- -- value |= AT803X_INTR_ENABLE_AUTONEG_ERR; -- value |= AT803X_INTR_ENABLE_SPEED_CHANGED; -- value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; -- value |= AT803X_INTR_ENABLE_LINK_FAIL; -- value |= AT803X_INTR_ENABLE_LINK_SUCCESS; -- -- err = phy_write(phydev, AT803X_INTR_ENABLE, value); -- } else { -- err = phy_write(phydev, AT803X_INTR_ENABLE, 0); -- if (err) -- return err; -- -- /* Clear any pending interrupts */ -- err = at803x_ack_interrupt(phydev); -- } -- -- return err; --} -- --static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) --{ -- int irq_status, int_enabled; -- -- irq_status = phy_read(phydev, AT803X_INTR_STATUS); -- if (irq_status < 0) { -- phy_error(phydev); -- return IRQ_NONE; -- } -- -- /* Read the current enabled interrupts */ -- int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); -- if (int_enabled < 0) { -- phy_error(phydev); -- return IRQ_NONE; -- } -- -- /* See if this was one of our enabled interrupts */ -- if (!(irq_status & int_enabled)) -- return IRQ_NONE; -- -- phy_trigger_machine(phydev); -- -- return IRQ_HANDLED; --} -- --static void at803x_link_change_notify(struct phy_device *phydev) --{ -- /* -- * Conduct a hardware reset for AT8030 every time a link loss is -- * signalled. This is necessary to circumvent a hardware bug that -- * occurs when the cable is unplugged while TX packets are pending -- * in the FIFO. In such cases, the FIFO enters an error mode it -- * cannot recover from by software. -- */ -- if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { -- struct at803x_context context; -- -- at803x_context_save(phydev, &context); -- -- phy_device_reset(phydev, 1); -- usleep_range(1000, 2000); -- phy_device_reset(phydev, 0); -- usleep_range(1000, 2000); -- -- at803x_context_restore(phydev, &context); -- -- phydev_dbg(phydev, "%s(): phy was reset\n", __func__); -- } --} -- --static int at803x_read_specific_status(struct phy_device *phydev, -- struct at803x_ss_mask ss_mask) --{ -- int ss; -- -- /* Read the AT8035 PHY-Specific Status register, which indicates the -- * speed and duplex that the PHY is actually using, irrespective of -- * whether we are in autoneg mode or not. -- */ -- ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); -- if (ss < 0) -- return ss; -- -- if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { -- int sfc, speed; -- -- sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); -- if (sfc < 0) -- return sfc; -- -- speed = ss & ss_mask.speed_mask; -- speed >>= ss_mask.speed_shift; -- -- switch (speed) { -- case AT803X_SS_SPEED_10: -- phydev->speed = SPEED_10; -- break; -- case AT803X_SS_SPEED_100: -- phydev->speed = SPEED_100; -- break; -- case AT803X_SS_SPEED_1000: -- phydev->speed = SPEED_1000; -- break; -- case QCA808X_SS_SPEED_2500: -- phydev->speed = SPEED_2500; -- break; -- } -- if (ss & AT803X_SS_DUPLEX) -- phydev->duplex = DUPLEX_FULL; -- else -- phydev->duplex = DUPLEX_HALF; -- -- if (ss & AT803X_SS_MDIX) -- phydev->mdix = ETH_TP_MDI_X; -- else -- phydev->mdix = ETH_TP_MDI; -- -- switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { -- case AT803X_SFC_MANUAL_MDI: -- phydev->mdix_ctrl = ETH_TP_MDI; -- break; -- case AT803X_SFC_MANUAL_MDIX: -- phydev->mdix_ctrl = ETH_TP_MDI_X; -- break; -- case AT803X_SFC_AUTOMATIC_CROSSOVER: -- phydev->mdix_ctrl = ETH_TP_MDI_AUTO; -- break; -- } -- } -- -- return 0; --} -- --static int at803x_read_status(struct phy_device *phydev) --{ -- struct at803x_ss_mask ss_mask = { 0 }; -- int err, old_link = phydev->link; -- -- /* Update the link, but return if there was an error */ -- err = genphy_update_link(phydev); -- if (err) -- return err; -- -- /* why bother the PHY if nothing can have changed */ -- if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) -- return 0; -- -- phydev->speed = SPEED_UNKNOWN; -- phydev->duplex = DUPLEX_UNKNOWN; -- phydev->pause = 0; -- phydev->asym_pause = 0; -- -- err = genphy_read_lpa(phydev); -- if (err < 0) -- return err; -- -- ss_mask.speed_mask = AT803X_SS_SPEED_MASK; -- ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK); -- err = at803x_read_specific_status(phydev, ss_mask); -- if (err < 0) -- return err; -- -- if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) -- phy_resolve_aneg_pause(phydev); -- -- return 0; --} -- --static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) --{ -- u16 val; -- -- switch (ctrl) { -- case ETH_TP_MDI: -- val = AT803X_SFC_MANUAL_MDI; -- break; -- case ETH_TP_MDI_X: -- val = AT803X_SFC_MANUAL_MDIX; -- break; -- case ETH_TP_MDI_AUTO: -- val = AT803X_SFC_AUTOMATIC_CROSSOVER; -- break; -- default: -- return 0; -- } -- -- return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, -- AT803X_SFC_MDI_CROSSOVER_MODE_M, -- FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); --} -- --static int at803x_prepare_config_aneg(struct phy_device *phydev) --{ -- int ret; -- -- ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); -- if (ret < 0) -- return ret; -- -- /* Changes of the midx bits are disruptive to the normal operation; -- * therefore any changes to these registers must be followed by a -- * software reset to take effect. -- */ -- if (ret == 1) { -- ret = genphy_soft_reset(phydev); -- if (ret < 0) -- return ret; -- } -- -- return 0; --} -- --static int at803x_config_aneg(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- int ret; -- -- ret = at803x_prepare_config_aneg(phydev); -- if (ret) -- return ret; -- -- if (priv->is_1000basex) -- return genphy_c37_config_aneg(phydev); -- -- return genphy_config_aneg(phydev); --} -- --static int at803x_get_downshift(struct phy_device *phydev, u8 *d) --{ -- int val; -- -- val = phy_read(phydev, AT803X_SMART_SPEED); -- if (val < 0) -- return val; -- -- if (val & AT803X_SMART_SPEED_ENABLE) -- *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; -- else -- *d = DOWNSHIFT_DEV_DISABLE; -- -- return 0; --} -- --static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) --{ -- u16 mask, set; -- int ret; -- -- switch (cnt) { -- case DOWNSHIFT_DEV_DEFAULT_COUNT: -- cnt = AT803X_DEFAULT_DOWNSHIFT; -- fallthrough; -- case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: -- set = AT803X_SMART_SPEED_ENABLE | -- AT803X_SMART_SPEED_BYPASS_TIMER | -- FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); -- mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; -- break; -- case DOWNSHIFT_DEV_DISABLE: -- set = 0; -- mask = AT803X_SMART_SPEED_ENABLE | -- AT803X_SMART_SPEED_BYPASS_TIMER; -- break; -- default: -- return -EINVAL; -- } -- -- ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); -- -- /* After changing the smart speed settings, we need to perform a -- * software reset, use phy_init_hw() to make sure we set the -- * reapply any values which might got lost during software reset. -- */ -- if (ret == 1) -- ret = phy_init_hw(phydev); -- -- return ret; --} -- --static int at803x_get_tunable(struct phy_device *phydev, -- struct ethtool_tunable *tuna, void *data) --{ -- switch (tuna->id) { -- case ETHTOOL_PHY_DOWNSHIFT: -- return at803x_get_downshift(phydev, data); -- default: -- return -EOPNOTSUPP; -- } --} -- --static int at803x_set_tunable(struct phy_device *phydev, -- struct ethtool_tunable *tuna, const void *data) --{ -- switch (tuna->id) { -- case ETHTOOL_PHY_DOWNSHIFT: -- return at803x_set_downshift(phydev, *(const u8 *)data); -- default: -- return -EOPNOTSUPP; -- } --} -- --static int at803x_cable_test_result_trans(u16 status) --{ -- switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { -- case AT803X_CDT_STATUS_STAT_NORMAL: -- return ETHTOOL_A_CABLE_RESULT_CODE_OK; -- case AT803X_CDT_STATUS_STAT_SHORT: -- return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; -- case AT803X_CDT_STATUS_STAT_OPEN: -- return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; -- case AT803X_CDT_STATUS_STAT_FAIL: -- default: -- return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; -- } --} -- --static bool at803x_cdt_test_failed(u16 status) --{ -- return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == -- AT803X_CDT_STATUS_STAT_FAIL; --} -- --static bool at803x_cdt_fault_length_valid(u16 status) --{ -- switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { -- case AT803X_CDT_STATUS_STAT_OPEN: -- case AT803X_CDT_STATUS_STAT_SHORT: -- return true; -- } -- return false; --} -- --static int at803x_cdt_fault_length(int dt) --{ -- /* According to the datasheet the distance to the fault is -- * DELTA_TIME * 0.824 meters. -- * -- * The author suspect the correct formula is: -- * -- * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 -- * -- * where c is the speed of light, VF is the velocity factor of -- * the twisted pair cable, 125MHz the counter frequency and -- * we need to divide by 2 because the hardware will measure the -- * round trip time to the fault and back to the PHY. -- * -- * With a VF of 0.69 we get the factor 0.824 mentioned in the -- * datasheet. -- */ -- return (dt * 824) / 10; --} -- --static int at803x_cdt_start(struct phy_device *phydev, -- u32 cdt_start) --{ -- return phy_write(phydev, AT803X_CDT, cdt_start); --} -- --static int at803x_cdt_wait_for_completion(struct phy_device *phydev, -- u32 cdt_en) --{ -- int val, ret; -- -- /* One test run takes about 25ms */ -- ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, -- !(val & cdt_en), -- 30000, 100000, true); -- -- return ret < 0 ? ret : 0; --} -- --static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) --{ -- static const int ethtool_pair[] = { -- ETHTOOL_A_CABLE_PAIR_A, -- ETHTOOL_A_CABLE_PAIR_B, -- ETHTOOL_A_CABLE_PAIR_C, -- ETHTOOL_A_CABLE_PAIR_D, -- }; -- int ret, val; -- -- val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | -- AT803X_CDT_ENABLE_TEST; -- ret = at803x_cdt_start(phydev, val); -- if (ret) -- return ret; -- -- ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST); -- if (ret) -- return ret; -- -- val = phy_read(phydev, AT803X_CDT_STATUS); -- if (val < 0) -- return val; -- -- if (at803x_cdt_test_failed(val)) -- return 0; -- -- ethnl_cable_test_result(phydev, ethtool_pair[pair], -- at803x_cable_test_result_trans(val)); -- -- if (at803x_cdt_fault_length_valid(val)) { -- val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val); -- ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], -- at803x_cdt_fault_length(val)); -- } -- -- return 1; --} -- --static int at803x_cable_test_get_status(struct phy_device *phydev, -- bool *finished, unsigned long pair_mask) --{ -- int retries = 20; -- int pair, ret; -- -- *finished = false; -- -- /* According to the datasheet the CDT can be performed when -- * there is no link partner or when the link partner is -- * auto-negotiating. Starting the test will restart the AN -- * automatically. It seems that doing this repeatedly we will -- * get a slot where our link partner won't disturb our -- * measurement. -- */ -- while (pair_mask && retries--) { -- for_each_set_bit(pair, &pair_mask, 4) { -- ret = at803x_cable_test_one_pair(phydev, pair); -- if (ret < 0) -- return ret; -- if (ret) -- clear_bit(pair, &pair_mask); -- } -- if (pair_mask) -- msleep(250); -- } -- -- *finished = true; -- -- return 0; --} -- --static void at803x_cable_test_autoneg(struct phy_device *phydev) --{ -- /* Enable auto-negotiation, but advertise no capabilities, no link -- * will be established. A restart of the auto-negotiation is not -- * required, because the cable test will automatically break the link. -- */ -- phy_write(phydev, MII_BMCR, BMCR_ANENABLE); -- phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); --} -- --static int at803x_cable_test_start(struct phy_device *phydev) --{ -- at803x_cable_test_autoneg(phydev); -- /* we do all the (time consuming) work later */ -- return 0; --} -- --static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, -- unsigned int selector) --{ -- struct phy_device *phydev = rdev_get_drvdata(rdev); -- -- if (selector) -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, -- 0, AT803X_DEBUG_RGMII_1V8); -- else -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, -- AT803X_DEBUG_RGMII_1V8, 0); --} -- --static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) --{ -- struct phy_device *phydev = rdev_get_drvdata(rdev); -- int val; -- -- val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); -- if (val < 0) -- return val; -- -- return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; --} -- --static const struct regulator_ops vddio_regulator_ops = { -- .list_voltage = regulator_list_voltage_table, -- .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel, -- .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel, --}; -- --static const unsigned int vddio_voltage_table[] = { -- 1500000, -- 1800000, --}; -- --static const struct regulator_desc vddio_desc = { -- .name = "vddio", -- .of_match = of_match_ptr("vddio-regulator"), -- .n_voltages = ARRAY_SIZE(vddio_voltage_table), -- .volt_table = vddio_voltage_table, -- .ops = &vddio_regulator_ops, -- .type = REGULATOR_VOLTAGE, -- .owner = THIS_MODULE, --}; -- --static const struct regulator_ops vddh_regulator_ops = { --}; -- --static const struct regulator_desc vddh_desc = { -- .name = "vddh", -- .of_match = of_match_ptr("vddh-regulator"), -- .n_voltages = 1, -- .fixed_uV = 2500000, -- .ops = &vddh_regulator_ops, -- .type = REGULATOR_VOLTAGE, -- .owner = THIS_MODULE, --}; -- --static int at8031_register_regulators(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- struct device *dev = &phydev->mdio.dev; -- struct regulator_config config = { }; -- -- config.dev = dev; -- config.driver_data = phydev; -- -- priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); -- if (IS_ERR(priv->vddio_rdev)) { -- phydev_err(phydev, "failed to register VDDIO regulator\n"); -- return PTR_ERR(priv->vddio_rdev); -- } -- -- priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); -- if (IS_ERR(priv->vddh_rdev)) { -- phydev_err(phydev, "failed to register VDDH regulator\n"); -- return PTR_ERR(priv->vddh_rdev); -- } -- -- return 0; --} -- --static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) --{ -- struct phy_device *phydev = upstream; -- __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); -- __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); -- DECLARE_PHY_INTERFACE_MASK(interfaces); -- phy_interface_t iface; -- -- linkmode_zero(phy_support); -- phylink_set(phy_support, 1000baseX_Full); -- phylink_set(phy_support, 1000baseT_Full); -- phylink_set(phy_support, Autoneg); -- phylink_set(phy_support, Pause); -- phylink_set(phy_support, Asym_Pause); -- -- linkmode_zero(sfp_support); -- sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); -- /* Some modules support 10G modes as well as others we support. -- * Mask out non-supported modes so the correct interface is picked. -- */ -- linkmode_and(sfp_support, phy_support, sfp_support); -- -- if (linkmode_empty(sfp_support)) { -- dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); -- return -EINVAL; -- } -- -- iface = sfp_select_interface(phydev->sfp_bus, sfp_support); -- -- /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes -- * interface for use with SFP modules. -- * However, some copper modules detected as having a preferred SGMII -- * interface do default to and function in 1000Base-X mode, so just -- * print a warning and allow such modules, as they may have some chance -- * of working. -- */ -- if (iface == PHY_INTERFACE_MODE_SGMII) -- dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); -- else if (iface != PHY_INTERFACE_MODE_1000BASEX) -- return -EINVAL; -- -- return 0; --} -- --static const struct sfp_upstream_ops at8031_sfp_ops = { -- .attach = phy_sfp_attach, -- .detach = phy_sfp_detach, -- .module_insert = at8031_sfp_insert, --}; -- --static int at8031_parse_dt(struct phy_device *phydev) --{ -- struct device_node *node = phydev->mdio.dev.of_node; -- struct at803x_priv *priv = phydev->priv; -- int ret; -- -- if (of_property_read_bool(node, "qca,keep-pll-enabled")) -- priv->flags |= AT803X_KEEP_PLL_ENABLED; -- -- ret = at8031_register_regulators(phydev); -- if (ret < 0) -- return ret; -- -- ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, -- "vddio"); -- if (ret) { -- phydev_err(phydev, "failed to get VDDIO regulator\n"); -- return ret; -- } -- -- /* Only AR8031/8033 support 1000Base-X for SFP modules */ -- return phy_sfp_probe(phydev, &at8031_sfp_ops); --} -- --static int at8031_probe(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- int mode_cfg; -- int ccr; -- int ret; -- -- ret = at803x_probe(phydev); -- if (ret) -- return ret; -- -- /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping -- * options. -- */ -- ret = at8031_parse_dt(phydev); -- if (ret) -- return ret; -- -- ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); -- if (ccr < 0) -- return ccr; -- mode_cfg = ccr & AT803X_MODE_CFG_MASK; -- -- switch (mode_cfg) { -- case AT803X_MODE_CFG_BX1000_RGMII_50OHM: -- case AT803X_MODE_CFG_BX1000_RGMII_75OHM: -- priv->is_1000basex = true; -- fallthrough; -- case AT803X_MODE_CFG_FX100_RGMII_50OHM: -- case AT803X_MODE_CFG_FX100_RGMII_75OHM: -- priv->is_fiber = true; -- break; -- } -- -- /* Disable WoL in 1588 register which is enabled -- * by default -- */ -- return phy_modify_mmd(phydev, MDIO_MMD_PCS, -- AT803X_PHY_MMD3_WOL_CTRL, -- AT803X_WOL_EN, 0); --} -- --static int at8031_config_init(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- int ret; -- -- /* Some bootloaders leave the fiber page selected. -- * Switch to the appropriate page (fiber or copper), as otherwise we -- * read the PHY capabilities from the wrong page. -- */ -- phy_lock_mdio_bus(phydev); -- ret = at803x_write_page(phydev, -- priv->is_fiber ? AT803X_PAGE_FIBER : -- AT803X_PAGE_COPPER); -- phy_unlock_mdio_bus(phydev); -- if (ret) -- return ret; -- -- ret = at8031_pll_config(phydev); -- if (ret < 0) -- return ret; -- -- return at803x_config_init(phydev); --} -- --static int at8031_set_wol(struct phy_device *phydev, -- struct ethtool_wolinfo *wol) --{ -- int ret; -- -- /* First setup MAC address and enable WOL interrupt */ -- ret = at803x_set_wol(phydev, wol); -- if (ret) -- return ret; -- -- if (wol->wolopts & WAKE_MAGIC) -- /* Enable WOL function for 1588 */ -- ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, -- AT803X_PHY_MMD3_WOL_CTRL, -- 0, AT803X_WOL_EN); -- else -- /* Disable WoL function for 1588 */ -- ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, -- AT803X_PHY_MMD3_WOL_CTRL, -- AT803X_WOL_EN, 0); -- -- return ret; --} -- --static int at8031_config_intr(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- int err, value = 0; -- -- if (phydev->interrupts == PHY_INTERRUPT_ENABLED && -- priv->is_fiber) { -- /* Clear any pending interrupts */ -- err = at803x_ack_interrupt(phydev); -- if (err) -- return err; -- -- value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; -- value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; -- -- err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value); -- if (err) -- return err; -- } -- -- return at803x_config_intr(phydev); --} -- --/* AR8031 and AR8033 share the same read status logic */ --static int at8031_read_status(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- -- if (priv->is_1000basex) -- return genphy_c37_read_status(phydev); -- -- return at803x_read_status(phydev); --} -- --/* AR8031 and AR8035 share the same cable test get status reg */ --static int at8031_cable_test_get_status(struct phy_device *phydev, -- bool *finished) --{ -- return at803x_cable_test_get_status(phydev, finished, 0xf); --} -- --/* AR8031 and AR8035 share the same cable test start logic */ --static int at8031_cable_test_start(struct phy_device *phydev) --{ -- at803x_cable_test_autoneg(phydev); -- phy_write(phydev, MII_CTRL1000, 0); -- /* we do all the (time consuming) work later */ -- return 0; --} -- --/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */ --static int at8032_cable_test_get_status(struct phy_device *phydev, -- bool *finished) --{ -- return at803x_cable_test_get_status(phydev, finished, 0x3); --} -- --static int at8035_parse_dt(struct phy_device *phydev) --{ -- struct at803x_priv *priv = phydev->priv; -- -- /* Mask is set by the generic at803x_parse_dt -- * if property is set. Assume property is set -- * with the mask not zero. -- */ -- if (priv->clk_25m_mask) { -- /* Fixup for the AR8030/AR8035. This chip has another mask and -- * doesn't support the DSP reference. Eg. the lowest bit of the -- * mask. The upper two bits select the same frequencies. Mask -- * the lowest bit here. -- * -- * Warning: -- * There was no datasheet for the AR8030 available so this is -- * just a guess. But the AR8035 is listed as pin compatible -- * to the AR8030 so there might be a good chance it works on -- * the AR8030 too. -- */ -- priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; -- priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; -- } -- -- return 0; --} -- --/* AR8030 and AR8035 shared the same special mask for clk_25m */ --static int at8035_probe(struct phy_device *phydev) --{ -- int ret; -- -- ret = at803x_probe(phydev); -- if (ret) -- return ret; -- -- return at8035_parse_dt(phydev); --} -- --static int qca83xx_config_init(struct phy_device *phydev) --{ -- u8 switch_revision; -- -- switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; -- -- switch (switch_revision) { -- case 1: -- /* For 100M waveform */ -- at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); -- /* Turn on Gigabit clock */ -- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); -- break; -- -- case 2: -- phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); -- fallthrough; -- case 4: -- phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); -- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); -- at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); -- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); -- break; -- } -- -- /* Following original QCA sourcecode set port to prefer master */ -- phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); -- -- return 0; --} -- --static int qca8327_config_init(struct phy_device *phydev) --{ -- /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. -- * Disable on init and enable only with 100m speed following -- * qca original source code. -- */ -- at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, -- QCA8327_DEBUG_MANU_CTRL_EN, 0); -- -- return qca83xx_config_init(phydev); --} -- --static void qca83xx_link_change_notify(struct phy_device *phydev) --{ -- /* Set DAC Amplitude adjustment to +6% for 100m on link running */ -- if (phydev->state == PHY_RUNNING) { -- if (phydev->speed == SPEED_100) -- at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, -- QCA8327_DEBUG_MANU_CTRL_EN, -- QCA8327_DEBUG_MANU_CTRL_EN); -- } else { -- /* Reset DAC Amplitude adjustment */ -- at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, -- QCA8327_DEBUG_MANU_CTRL_EN, 0); -- } --} -- --static int qca83xx_resume(struct phy_device *phydev) --{ -- int ret, val; -- -- /* Skip reset if not suspended */ -- if (!phydev->suspended) -- return 0; -- -- /* Reinit the port, reset values set by suspend */ -- qca83xx_config_init(phydev); -- -- /* Reset the port on port resume */ -- phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); -- -- /* On resume from suspend the switch execute a reset and -- * restart auto-negotiation. Wait for reset to complete. -- */ -- ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), -- 50000, 600000, true); -- if (ret) -- return ret; -- -- usleep_range(1000, 2000); -- -- return 0; --} -- --static int qca83xx_suspend(struct phy_device *phydev) --{ -- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, -- AT803X_DEBUG_GATE_CLK_IN1000, 0); -- -- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, -- AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | -- AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); -- -- return 0; --} -- --static int qca8337_suspend(struct phy_device *phydev) --{ -- /* Only QCA8337 support actual suspend. */ -- genphy_suspend(phydev); -- -- return qca83xx_suspend(phydev); --} -- --static int qca8327_suspend(struct phy_device *phydev) --{ -- u16 mask = 0; -- -- /* QCA8327 cause port unreliability when phy suspend -- * is set. -- */ -- mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); -- phy_modify(phydev, MII_BMCR, mask, 0); -- -- return qca83xx_suspend(phydev); --} -- --static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) --{ -- int ret; -- -- /* Enable fast retrain */ -- ret = genphy_c45_fast_retrain(phydev, true); -- if (ret) -- return ret; -- -- phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, -- QCA808X_TOP_OPTION1_DATA); -- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, -- QCA808X_MSE_THRESHOLD_20DB_VALUE); -- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, -- QCA808X_MSE_THRESHOLD_17DB_VALUE); -- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, -- QCA808X_MSE_THRESHOLD_27DB_VALUE); -- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, -- QCA808X_MSE_THRESHOLD_28DB_VALUE); -- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, -- QCA808X_MMD3_DEBUG_1_VALUE); -- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, -- QCA808X_MMD3_DEBUG_4_VALUE); -- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, -- QCA808X_MMD3_DEBUG_5_VALUE); -- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, -- QCA808X_MMD3_DEBUG_3_VALUE); -- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, -- QCA808X_MMD3_DEBUG_6_VALUE); -- phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, -- QCA808X_MMD3_DEBUG_2_VALUE); -- -- return 0; --} -- --static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) --{ -- u16 seed_value; -- -- if (!enable) -- return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, -- QCA808X_MASTER_SLAVE_SEED_ENABLE, 0); -- -- seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE); -- return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, -- QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE, -- FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) | -- QCA808X_MASTER_SLAVE_SEED_ENABLE); --} -- --static bool qca808x_is_prefer_master(struct phy_device *phydev) --{ -- return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) || -- (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED); --} -- --static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) --{ -- return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); --} -- --static int qca808x_config_init(struct phy_device *phydev) --{ -- int ret; -- -- /* Active adc&vga on 802.3az for the link 1000M and 100M */ -- ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, -- QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); -- if (ret) -- return ret; -- -- /* Adjust the threshold on 802.3az for the link 1000M */ -- ret = phy_write_mmd(phydev, MDIO_MMD_PCS, -- QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, -- QCA808X_MMD3_AZ_TRAINING_VAL); -- if (ret) -- return ret; -- -- if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { -- /* Config the fast retrain for the link 2500M */ -- ret = qca808x_phy_fast_retrain_config(phydev); -- if (ret) -- return ret; -- -- ret = genphy_read_master_slave(phydev); -- if (ret < 0) -- return ret; -- -- if (!qca808x_is_prefer_master(phydev)) { -- /* Enable seed and configure lower ramdom seed to make phy -- * linked as slave mode. -- */ -- ret = qca808x_phy_ms_seed_enable(phydev, true); -- if (ret) -- return ret; -- } -- } -- -- /* Configure adc threshold as 100mv for the link 10M */ -- return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, -- QCA808X_ADC_THRESHOLD_MASK, -- QCA808X_ADC_THRESHOLD_100MV); --} -- --static int qca808x_read_status(struct phy_device *phydev) --{ -- struct at803x_ss_mask ss_mask = { 0 }; -- int ret; -- -- ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); -- if (ret < 0) -- return ret; -- -- linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, -- ret & MDIO_AN_10GBT_STAT_LP2_5G); -- -- ret = genphy_read_status(phydev); -- if (ret) -- return ret; -- -- /* qca8081 takes the different bits for speed value from at803x */ -- ss_mask.speed_mask = QCA808X_SS_SPEED_MASK; -- ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK); -- ret = at803x_read_specific_status(phydev, ss_mask); -- if (ret < 0) -- return ret; -- -- if (phydev->link) { -- if (phydev->speed == SPEED_2500) -- phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- else -- phydev->interface = PHY_INTERFACE_MODE_SGMII; -- } else { -- /* generate seed as a lower random value to make PHY linked as SLAVE easily, -- * except for master/slave configuration fault detected or the master mode -- * preferred. -- * -- * the reason for not putting this code into the function link_change_notify is -- * the corner case where the link partner is also the qca8081 PHY and the seed -- * value is configured as the same value, the link can't be up and no link change -- * occurs. -- */ -- if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { -- if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR || -- qca808x_is_prefer_master(phydev)) { -- qca808x_phy_ms_seed_enable(phydev, false); -- } else { -- qca808x_phy_ms_seed_enable(phydev, true); -- } -- } -- } -- -- return 0; --} -- --static int qca808x_soft_reset(struct phy_device *phydev) --{ -- int ret; -- -- ret = genphy_soft_reset(phydev); -- if (ret < 0) -- return ret; -- -- if (qca808x_has_fast_retrain_or_slave_seed(phydev)) -- ret = qca808x_phy_ms_seed_enable(phydev, true); -- -- return ret; --} -- --static bool qca808x_cdt_fault_length_valid(int cdt_code) --{ -- switch (cdt_code) { -- case QCA808X_CDT_STATUS_STAT_SAME_SHORT: -- case QCA808X_CDT_STATUS_STAT_SAME_OPEN: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: -- return true; -- default: -- return false; -- } --} -- --static int qca808x_cable_test_result_trans(int cdt_code) --{ -- switch (cdt_code) { -- case QCA808X_CDT_STATUS_STAT_NORMAL: -- return ETHTOOL_A_CABLE_RESULT_CODE_OK; -- case QCA808X_CDT_STATUS_STAT_SAME_SHORT: -- return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; -- case QCA808X_CDT_STATUS_STAT_SAME_OPEN: -- return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: -- case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: -- return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; -- case QCA808X_CDT_STATUS_STAT_FAIL: -- default: -- return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; -- } --} -- --static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair, -- int result) --{ -- int val; -- u32 cdt_length_reg = 0; -- -- switch (pair) { -- case ETHTOOL_A_CABLE_PAIR_A: -- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; -- break; -- case ETHTOOL_A_CABLE_PAIR_B: -- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; -- break; -- case ETHTOOL_A_CABLE_PAIR_C: -- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; -- break; -- case ETHTOOL_A_CABLE_PAIR_D: -- cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; -- break; -- default: -- return -EINVAL; -- } -- -- val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); -- if (val < 0) -- return val; -- -- if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT) -- val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val); -- else -- val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val); -- -- return at803x_cdt_fault_length(val); --} -- --static int qca808x_cable_test_start(struct phy_device *phydev) --{ -- int ret; -- -- /* perform CDT with the following configs: -- * 1. disable hibernation. -- * 2. force PHY working in MDI mode. -- * 3. for PHY working in 1000BaseT. -- * 4. configure the threshold. -- */ -- -- ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); -- if (ret < 0) -- return ret; -- -- ret = at803x_config_mdix(phydev, ETH_TP_MDI); -- if (ret < 0) -- return ret; -- -- /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ -- phydev->duplex = DUPLEX_FULL; -- phydev->speed = SPEED_1000; -- ret = genphy_c45_pma_setup_forced(phydev); -- if (ret < 0) -- return ret; -- -- ret = genphy_setup_forced(phydev); -- if (ret < 0) -- return ret; -- -- /* configure the thresholds for open, short, pair ok test */ -- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); -- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); -- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); -- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); -- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); -- phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); -- -- return 0; --} -- --static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair, -- u16 status) --{ -- int length, result; -- u16 pair_code; -- -- switch (pair) { -- case ETHTOOL_A_CABLE_PAIR_A: -- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status); -- break; -- case ETHTOOL_A_CABLE_PAIR_B: -- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status); -- break; -- case ETHTOOL_A_CABLE_PAIR_C: -- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status); -- break; -- case ETHTOOL_A_CABLE_PAIR_D: -- pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status); -- break; -- default: -- return -EINVAL; -- } -- -- result = qca808x_cable_test_result_trans(pair_code); -- ethnl_cable_test_result(phydev, pair, result); -- -- if (qca808x_cdt_fault_length_valid(pair_code)) { -- length = qca808x_cdt_fault_length(phydev, pair, result); -- ethnl_cable_test_fault_length(phydev, pair, length); -- } -- -- return 0; --} -- --static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) --{ -- int ret, val; -- -- *finished = false; -- -- val = QCA808X_CDT_ENABLE_TEST | -- QCA808X_CDT_LENGTH_UNIT; -- ret = at803x_cdt_start(phydev, val); -- if (ret) -- return ret; -- -- ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST); -- if (ret) -- return ret; -- -- val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); -- if (val < 0) -- return val; -- -- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val); -- if (ret) -- return ret; -- -- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val); -- if (ret) -- return ret; -- -- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val); -- if (ret) -- return ret; -- -- ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val); -- if (ret) -- return ret; -- -- *finished = true; -- -- return 0; --} -- --static int qca808x_get_features(struct phy_device *phydev) --{ -- int ret; -- -- ret = genphy_c45_pma_read_abilities(phydev); -- if (ret) -- return ret; -- -- /* The autoneg ability is not existed in bit3 of MMD7.1, -- * but it is supported by qca808x PHY, so we add it here -- * manually. -- */ -- linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); -- -- /* As for the qca8081 1G version chip, the 2500baseT ability is also -- * existed in the bit0 of MMD1.21, we need to remove it manually if -- * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d. -- */ -- ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); -- if (ret < 0) -- return ret; -- -- if (QCA808X_PHY_CHIP_TYPE_1G & ret) -- linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); -- -- return 0; --} -- --static int qca808x_config_aneg(struct phy_device *phydev) --{ -- int phy_ctrl = 0; -- int ret; -- -- ret = at803x_prepare_config_aneg(phydev); -- if (ret) -- return ret; -- -- /* The reg MII_BMCR also needs to be configured for force mode, the -- * genphy_config_aneg is also needed. -- */ -- if (phydev->autoneg == AUTONEG_DISABLE) -- genphy_c45_pma_setup_forced(phydev); -- -- if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) -- phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; -- -- ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, -- MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); -- if (ret < 0) -- return ret; -- -- return __genphy_config_aneg(phydev, ret); --} -- --static void qca808x_link_change_notify(struct phy_device *phydev) --{ -- /* Assert interface sgmii fifo on link down, deassert it on link up, -- * the interface device address is always phy address added by 1. -- */ -- mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1, -- MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL, -- QCA8081_PHY_FIFO_RSTN, -- phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); --} -- --static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, -- u16 *offload_trigger) --{ -- /* Parsing specific to netdev trigger */ -- if (test_bit(TRIGGER_NETDEV_TX, &rules)) -- *offload_trigger |= QCA808X_LED_TX_BLINK; -- if (test_bit(TRIGGER_NETDEV_RX, &rules)) -- *offload_trigger |= QCA808X_LED_RX_BLINK; -- if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) -- *offload_trigger |= QCA808X_LED_SPEED10_ON; -- if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) -- *offload_trigger |= QCA808X_LED_SPEED100_ON; -- if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) -- *offload_trigger |= QCA808X_LED_SPEED1000_ON; -- if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules)) -- *offload_trigger |= QCA808X_LED_SPEED2500_ON; -- if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) -- *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON; -- if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) -- *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON; -- -- if (rules && !*offload_trigger) -- return -EOPNOTSUPP; -- -- /* Enable BLINK_CHECK_BYPASS by default to make the LED -- * blink even with duplex or speed mode not enabled. -- */ -- *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS; -- -- return 0; --} -- --static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index) --{ -- u16 reg; -- -- if (index > 2) -- return -EINVAL; -- -- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); -- -- return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, -- QCA808X_LED_FORCE_EN); --} -- --static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index, -- unsigned long rules) --{ -- u16 offload_trigger = 0; -- -- if (index > 2) -- return -EINVAL; -- -- return qca808x_led_parse_netdev(phydev, rules, &offload_trigger); --} -- --static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index, -- unsigned long rules) --{ -- u16 reg, offload_trigger = 0; -- int ret; -- -- if (index > 2) -- return -EINVAL; -- -- reg = QCA808X_MMD7_LED_CTRL(index); -- -- ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger); -- if (ret) -- return ret; -- -- ret = qca808x_led_hw_control_enable(phydev, index); -- if (ret) -- return ret; -- -- return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, -- QCA808X_LED_PATTERN_MASK, -- offload_trigger); --} -- --static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index) --{ -- u16 reg; -- int val; -- -- if (index > 2) -- return false; -- -- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); -- -- val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); -- -- return !(val & QCA808X_LED_FORCE_EN); --} -- --static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index, -- unsigned long *rules) --{ -- u16 reg; -- int val; -- -- if (index > 2) -- return -EINVAL; -- -- /* Check if we have hw control enabled */ -- if (qca808x_led_hw_control_status(phydev, index)) -- return -EINVAL; -- -- reg = QCA808X_MMD7_LED_CTRL(index); -- -- val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); -- if (val & QCA808X_LED_TX_BLINK) -- set_bit(TRIGGER_NETDEV_TX, rules); -- if (val & QCA808X_LED_RX_BLINK) -- set_bit(TRIGGER_NETDEV_RX, rules); -- if (val & QCA808X_LED_SPEED10_ON) -- set_bit(TRIGGER_NETDEV_LINK_10, rules); -- if (val & QCA808X_LED_SPEED100_ON) -- set_bit(TRIGGER_NETDEV_LINK_100, rules); -- if (val & QCA808X_LED_SPEED1000_ON) -- set_bit(TRIGGER_NETDEV_LINK_1000, rules); -- if (val & QCA808X_LED_SPEED2500_ON) -- set_bit(TRIGGER_NETDEV_LINK_2500, rules); -- if (val & QCA808X_LED_HALF_DUPLEX_ON) -- set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); -- if (val & QCA808X_LED_FULL_DUPLEX_ON) -- set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); -- -- return 0; --} -- --static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index) --{ -- u16 reg; -- -- if (index > 2) -- return -EINVAL; -- -- reg = QCA808X_MMD7_LED_CTRL(index); -- -- return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, -- QCA808X_LED_PATTERN_MASK); --} -- --static int qca808x_led_brightness_set(struct phy_device *phydev, -- u8 index, enum led_brightness value) --{ -- u16 reg; -- int ret; -- -- if (index > 2) -- return -EINVAL; -- -- if (!value) { -- ret = qca808x_led_hw_control_reset(phydev, index); -- if (ret) -- return ret; -- } -- -- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); -- -- return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, -- QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, -- QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON : -- QCA808X_LED_FORCE_OFF); --} -- --static int qca808x_led_blink_set(struct phy_device *phydev, u8 index, -- unsigned long *delay_on, -- unsigned long *delay_off) --{ -- int ret; -- u16 reg; -- -- if (index > 2) -- return -EINVAL; -- -- reg = QCA808X_MMD7_LED_FORCE_CTRL(index); -- -- /* Set blink to 50% off, 50% on at 4Hz by default */ -- ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL, -- QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK, -- QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50); -- if (ret) -- return ret; -- -- /* We use BLINK_1 for normal blinking */ -- ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, -- QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, -- QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1); -- if (ret) -- return ret; -- -- /* We set blink to 4Hz, aka 250ms */ -- *delay_on = 250 / 2; -- *delay_off = 250 / 2; -- -- return 0; --} -- --static int qca808x_led_polarity_set(struct phy_device *phydev, int index, -- unsigned long modes) --{ -- struct at803x_priv *priv = phydev->priv; -- bool active_low = false; -- u32 mode; -- -- for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { -- switch (mode) { -- case PHY_LED_ACTIVE_LOW: -- active_low = true; -- break; -- default: -- return -EINVAL; -- } -- } -- -- /* PHY polarity is global and can't be set per LED. -- * To detect this, check if last requested polarity mode -- * match the new one. -- */ -- if (priv->led_polarity_mode >= 0 && -- priv->led_polarity_mode != active_low) { -- phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); -- return -EINVAL; -- } -- -- /* Save the last PHY polarity mode */ -- priv->led_polarity_mode = active_low; -- -- return phy_modify_mmd(phydev, MDIO_MMD_AN, -- QCA808X_MMD7_LED_POLARITY_CTRL, -- QCA808X_LED_ACTIVE_HIGH, -- active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); --} -- --static struct phy_driver at803x_driver[] = { --{ -- /* Qualcomm Atheros AR8035 */ -- PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), -- .name = "Qualcomm Atheros AR8035", -- .flags = PHY_POLL_CABLE_TEST, -- .probe = at8035_probe, -- .config_aneg = at803x_config_aneg, -- .config_init = at803x_config_init, -- .soft_reset = genphy_soft_reset, -- .set_wol = at803x_set_wol, -- .get_wol = at803x_get_wol, -- .suspend = at803x_suspend, -- .resume = at803x_resume, -- /* PHY_GBIT_FEATURES */ -- .read_status = at803x_read_status, -- .config_intr = at803x_config_intr, -- .handle_interrupt = at803x_handle_interrupt, -- .get_tunable = at803x_get_tunable, -- .set_tunable = at803x_set_tunable, -- .cable_test_start = at8031_cable_test_start, -- .cable_test_get_status = at8031_cable_test_get_status, --}, { -- /* Qualcomm Atheros AR8030 */ -- .phy_id = ATH8030_PHY_ID, -- .name = "Qualcomm Atheros AR8030", -- .phy_id_mask = AT8030_PHY_ID_MASK, -- .probe = at8035_probe, -- .config_init = at803x_config_init, -- .link_change_notify = at803x_link_change_notify, -- .set_wol = at803x_set_wol, -- .get_wol = at803x_get_wol, -- .suspend = at803x_suspend, -- .resume = at803x_resume, -- /* PHY_BASIC_FEATURES */ -- .config_intr = at803x_config_intr, -- .handle_interrupt = at803x_handle_interrupt, --}, { -- /* Qualcomm Atheros AR8031/AR8033 */ -- PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), -- .name = "Qualcomm Atheros AR8031/AR8033", -- .flags = PHY_POLL_CABLE_TEST, -- .probe = at8031_probe, -- .config_init = at8031_config_init, -- .config_aneg = at803x_config_aneg, -- .soft_reset = genphy_soft_reset, -- .set_wol = at8031_set_wol, -- .get_wol = at803x_get_wol, -- .suspend = at803x_suspend, -- .resume = at803x_resume, -- .read_page = at803x_read_page, -- .write_page = at803x_write_page, -- .get_features = at803x_get_features, -- .read_status = at8031_read_status, -- .config_intr = at8031_config_intr, -- .handle_interrupt = at803x_handle_interrupt, -- .get_tunable = at803x_get_tunable, -- .set_tunable = at803x_set_tunable, -- .cable_test_start = at8031_cable_test_start, -- .cable_test_get_status = at8031_cable_test_get_status, --}, { -- /* Qualcomm Atheros AR8032 */ -- PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), -- .name = "Qualcomm Atheros AR8032", -- .probe = at803x_probe, -- .flags = PHY_POLL_CABLE_TEST, -- .config_init = at803x_config_init, -- .link_change_notify = at803x_link_change_notify, -- .suspend = at803x_suspend, -- .resume = at803x_resume, -- /* PHY_BASIC_FEATURES */ -- .config_intr = at803x_config_intr, -- .handle_interrupt = at803x_handle_interrupt, -- .cable_test_start = at803x_cable_test_start, -- .cable_test_get_status = at8032_cable_test_get_status, --}, { -- /* ATHEROS AR9331 */ -- PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), -- .name = "Qualcomm Atheros AR9331 built-in PHY", -- .probe = at803x_probe, -- .suspend = at803x_suspend, -- .resume = at803x_resume, -- .flags = PHY_POLL_CABLE_TEST, -- /* PHY_BASIC_FEATURES */ -- .config_intr = at803x_config_intr, -- .handle_interrupt = at803x_handle_interrupt, -- .cable_test_start = at803x_cable_test_start, -- .cable_test_get_status = at8032_cable_test_get_status, -- .read_status = at803x_read_status, -- .soft_reset = genphy_soft_reset, -- .config_aneg = at803x_config_aneg, --}, { -- /* Qualcomm Atheros QCA9561 */ -- PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), -- .name = "Qualcomm Atheros QCA9561 built-in PHY", -- .probe = at803x_probe, -- .suspend = at803x_suspend, -- .resume = at803x_resume, -- .flags = PHY_POLL_CABLE_TEST, -- /* PHY_BASIC_FEATURES */ -- .config_intr = at803x_config_intr, -- .handle_interrupt = at803x_handle_interrupt, -- .cable_test_start = at803x_cable_test_start, -- .cable_test_get_status = at8032_cable_test_get_status, -- .read_status = at803x_read_status, -- .soft_reset = genphy_soft_reset, -- .config_aneg = at803x_config_aneg, --}, { -- /* QCA8337 */ -- .phy_id = QCA8337_PHY_ID, -- .phy_id_mask = QCA8K_PHY_ID_MASK, -- .name = "Qualcomm Atheros 8337 internal PHY", -- /* PHY_GBIT_FEATURES */ -- .probe = at803x_probe, -- .flags = PHY_IS_INTERNAL, -- .config_init = qca83xx_config_init, -- .soft_reset = genphy_soft_reset, -- .get_sset_count = qca83xx_get_sset_count, -- .get_strings = qca83xx_get_strings, -- .get_stats = qca83xx_get_stats, -- .suspend = qca8337_suspend, -- .resume = qca83xx_resume, --}, { -- /* QCA8327-A from switch QCA8327-AL1A */ -- .phy_id = QCA8327_A_PHY_ID, -- .phy_id_mask = QCA8K_PHY_ID_MASK, -- .name = "Qualcomm Atheros 8327-A internal PHY", -- /* PHY_GBIT_FEATURES */ -- .link_change_notify = qca83xx_link_change_notify, -- .probe = at803x_probe, -- .flags = PHY_IS_INTERNAL, -- .config_init = qca8327_config_init, -- .soft_reset = genphy_soft_reset, -- .get_sset_count = qca83xx_get_sset_count, -- .get_strings = qca83xx_get_strings, -- .get_stats = qca83xx_get_stats, -- .suspend = qca8327_suspend, -- .resume = qca83xx_resume, --}, { -- /* QCA8327-B from switch QCA8327-BL1A */ -- .phy_id = QCA8327_B_PHY_ID, -- .phy_id_mask = QCA8K_PHY_ID_MASK, -- .name = "Qualcomm Atheros 8327-B internal PHY", -- /* PHY_GBIT_FEATURES */ -- .link_change_notify = qca83xx_link_change_notify, -- .probe = at803x_probe, -- .flags = PHY_IS_INTERNAL, -- .config_init = qca8327_config_init, -- .soft_reset = genphy_soft_reset, -- .get_sset_count = qca83xx_get_sset_count, -- .get_strings = qca83xx_get_strings, -- .get_stats = qca83xx_get_stats, -- .suspend = qca8327_suspend, -- .resume = qca83xx_resume, --}, { -- /* Qualcomm QCA8081 */ -- PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), -- .name = "Qualcomm QCA8081", -- .flags = PHY_POLL_CABLE_TEST, -- .probe = at803x_probe, -- .config_intr = at803x_config_intr, -- .handle_interrupt = at803x_handle_interrupt, -- .get_tunable = at803x_get_tunable, -- .set_tunable = at803x_set_tunable, -- .set_wol = at803x_set_wol, -- .get_wol = at803x_get_wol, -- .get_features = qca808x_get_features, -- .config_aneg = qca808x_config_aneg, -- .suspend = genphy_suspend, -- .resume = genphy_resume, -- .read_status = qca808x_read_status, -- .config_init = qca808x_config_init, -- .soft_reset = qca808x_soft_reset, -- .cable_test_start = qca808x_cable_test_start, -- .cable_test_get_status = qca808x_cable_test_get_status, -- .link_change_notify = qca808x_link_change_notify, -- .led_brightness_set = qca808x_led_brightness_set, -- .led_blink_set = qca808x_led_blink_set, -- .led_hw_is_supported = qca808x_led_hw_is_supported, -- .led_hw_control_set = qca808x_led_hw_control_set, -- .led_hw_control_get = qca808x_led_hw_control_get, -- .led_polarity_set = qca808x_led_polarity_set, --}, }; -- --module_phy_driver(at803x_driver); -- --static struct mdio_device_id __maybe_unused atheros_tbl[] = { -- { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, -- { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, -- { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, -- { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, -- { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, -- { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, -- { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, -- { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, -- { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, -- { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, -- { } --}; -- --MODULE_DEVICE_TABLE(mdio, atheros_tbl); ---- /dev/null -+++ b/drivers/net/phy/qcom/at803x.c -@@ -0,0 +1,2759 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * drivers/net/phy/at803x.c -+ * -+ * Driver for Qualcomm Atheros AR803x PHY -+ * -+ * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> -+ */ -+ -+#include <linux/phy.h> -+#include <linux/module.h> -+#include <linux/string.h> -+#include <linux/netdevice.h> -+#include <linux/etherdevice.h> -+#include <linux/ethtool_netlink.h> -+#include <linux/bitfield.h> -+#include <linux/regulator/of_regulator.h> -+#include <linux/regulator/driver.h> -+#include <linux/regulator/consumer.h> -+#include <linux/of.h> -+#include <linux/phylink.h> -+#include <linux/sfp.h> -+#include <dt-bindings/net/qca-ar803x.h> -+ -+#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 -+#define AT803X_SFC_ASSERT_CRS BIT(11) -+#define AT803X_SFC_FORCE_LINK BIT(10) -+#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) -+#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 -+#define AT803X_SFC_MANUAL_MDIX 0x1 -+#define AT803X_SFC_MANUAL_MDI 0x0 -+#define AT803X_SFC_SQE_TEST BIT(2) -+#define AT803X_SFC_POLARITY_REVERSAL BIT(1) -+#define AT803X_SFC_DISABLE_JABBER BIT(0) -+ -+#define AT803X_SPECIFIC_STATUS 0x11 -+#define AT803X_SS_SPEED_MASK GENMASK(15, 14) -+#define AT803X_SS_SPEED_1000 2 -+#define AT803X_SS_SPEED_100 1 -+#define AT803X_SS_SPEED_10 0 -+#define AT803X_SS_DUPLEX BIT(13) -+#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) -+#define AT803X_SS_MDIX BIT(6) -+ -+#define QCA808X_SS_SPEED_MASK GENMASK(9, 7) -+#define QCA808X_SS_SPEED_2500 4 -+ -+#define AT803X_INTR_ENABLE 0x12 -+#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) -+#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) -+#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) -+#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) -+#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) -+#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) -+#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) -+#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) -+#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) -+#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) -+#define AT803X_INTR_ENABLE_WOL BIT(0) -+ -+#define AT803X_INTR_STATUS 0x13 -+ -+#define AT803X_SMART_SPEED 0x14 -+#define AT803X_SMART_SPEED_ENABLE BIT(5) -+#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) -+#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) -+#define AT803X_CDT 0x16 -+#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) -+#define AT803X_CDT_ENABLE_TEST BIT(0) -+#define AT803X_CDT_STATUS 0x1c -+#define AT803X_CDT_STATUS_STAT_NORMAL 0 -+#define AT803X_CDT_STATUS_STAT_SHORT 1 -+#define AT803X_CDT_STATUS_STAT_OPEN 2 -+#define AT803X_CDT_STATUS_STAT_FAIL 3 -+#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) -+#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) -+#define AT803X_LED_CONTROL 0x18 -+ -+#define AT803X_PHY_MMD3_WOL_CTRL 0x8012 -+#define AT803X_WOL_EN BIT(5) -+#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C -+#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B -+#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A -+#define AT803X_REG_CHIP_CONFIG 0x1f -+#define AT803X_BT_BX_REG_SEL 0x8000 -+ -+#define AT803X_DEBUG_ADDR 0x1D -+#define AT803X_DEBUG_DATA 0x1E -+ -+#define AT803X_MODE_CFG_MASK 0x0F -+#define AT803X_MODE_CFG_BASET_RGMII 0x00 -+#define AT803X_MODE_CFG_BASET_SGMII 0x01 -+#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 -+#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 -+#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 -+#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 -+#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 -+#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 -+#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B -+#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E -+#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F -+ -+#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ -+#define AT803X_PSSR_MR_AN_COMPLETE 0x0200 -+ -+#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 -+#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) -+#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) -+#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) -+ -+#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 -+#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) -+ -+#define AT803X_DEBUG_REG_HIB_CTRL 0x0b -+#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) -+#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) -+#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) -+ -+#define AT803X_DEBUG_REG_3C 0x3C -+ -+#define AT803X_DEBUG_REG_GREEN 0x3D -+#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) -+ -+#define AT803X_DEBUG_REG_1F 0x1F -+#define AT803X_DEBUG_PLL_ON BIT(2) -+#define AT803X_DEBUG_RGMII_1V8 BIT(3) -+ -+#define MDIO_AZ_DEBUG 0x800D -+ -+/* AT803x supports either the XTAL input pad, an internal PLL or the -+ * DSP as clock reference for the clock output pad. The XTAL reference -+ * is only used for 25 MHz output, all other frequencies need the PLL. -+ * The DSP as a clock reference is used in synchronous ethernet -+ * applications. -+ * -+ * By default the PLL is only enabled if there is a link. Otherwise -+ * the PHY will go into low power state and disabled the PLL. You can -+ * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always -+ * enabled. -+ */ -+#define AT803X_MMD7_CLK25M 0x8016 -+#define AT803X_CLK_OUT_MASK GENMASK(4, 2) -+#define AT803X_CLK_OUT_25MHZ_XTAL 0 -+#define AT803X_CLK_OUT_25MHZ_DSP 1 -+#define AT803X_CLK_OUT_50MHZ_PLL 2 -+#define AT803X_CLK_OUT_50MHZ_DSP 3 -+#define AT803X_CLK_OUT_62_5MHZ_PLL 4 -+#define AT803X_CLK_OUT_62_5MHZ_DSP 5 -+#define AT803X_CLK_OUT_125MHZ_PLL 6 -+#define AT803X_CLK_OUT_125MHZ_DSP 7 -+ -+/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask -+ * but doesn't support choosing between XTAL/PLL and DSP. -+ */ -+#define AT8035_CLK_OUT_MASK GENMASK(4, 3) -+ -+#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) -+#define AT803X_CLK_OUT_STRENGTH_FULL 0 -+#define AT803X_CLK_OUT_STRENGTH_HALF 1 -+#define AT803X_CLK_OUT_STRENGTH_QUARTER 2 -+ -+#define AT803X_DEFAULT_DOWNSHIFT 5 -+#define AT803X_MIN_DOWNSHIFT 2 -+#define AT803X_MAX_DOWNSHIFT 9 -+ -+#define AT803X_MMD3_SMARTEEE_CTL1 0x805b -+#define AT803X_MMD3_SMARTEEE_CTL2 0x805c -+#define AT803X_MMD3_SMARTEEE_CTL3 0x805d -+#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) -+ -+#define ATH9331_PHY_ID 0x004dd041 -+#define ATH8030_PHY_ID 0x004dd076 -+#define ATH8031_PHY_ID 0x004dd074 -+#define ATH8032_PHY_ID 0x004dd023 -+#define ATH8035_PHY_ID 0x004dd072 -+#define AT8030_PHY_ID_MASK 0xffffffef -+ -+#define QCA8081_PHY_ID 0x004dd101 -+ -+#define QCA8327_A_PHY_ID 0x004dd033 -+#define QCA8327_B_PHY_ID 0x004dd034 -+#define QCA8337_PHY_ID 0x004dd036 -+#define QCA9561_PHY_ID 0x004dd042 -+#define QCA8K_PHY_ID_MASK 0xffffffff -+ -+#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) -+ -+#define AT803X_PAGE_FIBER 0 -+#define AT803X_PAGE_COPPER 1 -+ -+/* don't turn off internal PLL */ -+#define AT803X_KEEP_PLL_ENABLED BIT(0) -+#define AT803X_DISABLE_SMARTEEE BIT(1) -+ -+/* disable hibernation mode */ -+#define AT803X_DISABLE_HIBERNATION_MODE BIT(2) -+ -+/* ADC threshold */ -+#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 -+#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) -+#define QCA808X_ADC_THRESHOLD_80MV 0 -+#define QCA808X_ADC_THRESHOLD_100MV 0xf0 -+#define QCA808X_ADC_THRESHOLD_200MV 0x0f -+#define QCA808X_ADC_THRESHOLD_300MV 0xff -+ -+/* CLD control */ -+#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 -+#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) -+#define QCA808X_8023AZ_AFE_EN 0x90 -+ -+/* AZ control */ -+#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 -+#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 -+ -+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 -+#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 -+ -+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E -+#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 -+ -+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E -+#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 -+ -+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 -+#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 -+ -+#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c -+#define QCA808X_TOP_OPTION1_DATA 0x0 -+ -+#define QCA808X_PHY_MMD3_DEBUG_1 0xa100 -+#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 -+#define QCA808X_PHY_MMD3_DEBUG_2 0xa101 -+#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad -+#define QCA808X_PHY_MMD3_DEBUG_3 0xa103 -+#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 -+#define QCA808X_PHY_MMD3_DEBUG_4 0xa105 -+#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 -+#define QCA808X_PHY_MMD3_DEBUG_5 0xa106 -+#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 -+#define QCA808X_PHY_MMD3_DEBUG_6 0xa011 -+#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 -+ -+/* master/slave seed config */ -+#define QCA808X_PHY_DEBUG_LOCAL_SEED 9 -+#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) -+#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) -+#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 -+ -+/* Hibernation yields lower power consumpiton in contrast with normal operation mode. -+ * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. -+ */ -+#define QCA808X_DBG_AN_TEST 0xb -+#define QCA808X_HIBERNATION_EN BIT(15) -+ -+#define QCA808X_CDT_ENABLE_TEST BIT(15) -+#define QCA808X_CDT_INTER_CHECK_DIS BIT(13) -+#define QCA808X_CDT_STATUS BIT(11) -+#define QCA808X_CDT_LENGTH_UNIT BIT(10) -+ -+#define QCA808X_MMD3_CDT_STATUS 0x8064 -+#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 -+#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 -+#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 -+#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 -+#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8) -+#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0) -+ -+#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) -+#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) -+#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) -+#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) -+ -+#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0) -+#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0) -+#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1) -+#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2) -+#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3) -+ -+#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2) -+#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1) -+#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2) -+#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3) -+ -+/* NORMAL are MDI with type set to 0 */ -+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1 -+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ -+ QCA808X_CDT_STATUS_STAT_MDI1) -+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ -+ QCA808X_CDT_STATUS_STAT_MDI1) -+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2 -+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ -+ QCA808X_CDT_STATUS_STAT_MDI2) -+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ -+ QCA808X_CDT_STATUS_STAT_MDI2) -+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3 -+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\ -+ QCA808X_CDT_STATUS_STAT_MDI3) -+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\ -+ QCA808X_CDT_STATUS_STAT_MDI3) -+ -+/* Added for reference of existence but should be handled by wait_for_completion already */ -+#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3)) -+ -+#define QCA808X_MMD7_LED_GLOBAL 0x8073 -+#define QCA808X_LED_BLINK_1 GENMASK(11, 6) -+#define QCA808X_LED_BLINK_2 GENMASK(5, 0) -+/* Values are the same for both BLINK_1 and BLINK_2 */ -+#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3) -+#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0) -+#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1) -+#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2) -+#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3) -+#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4) -+#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5) -+#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6) -+#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7) -+#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0) -+#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0) -+#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1) -+#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2) -+#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3) -+#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4) -+#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5) -+#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6) -+#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7) -+ -+#define QCA808X_MMD7_LED2_CTRL 0x8074 -+#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075 -+#define QCA808X_MMD7_LED1_CTRL 0x8076 -+#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077 -+#define QCA808X_MMD7_LED0_CTRL 0x8078 -+#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2)) -+ -+/* LED hw control pattern is the same for every LED */ -+#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0) -+#define QCA808X_LED_SPEED2500_ON BIT(15) -+#define QCA808X_LED_SPEED2500_BLINK BIT(14) -+/* Follow blink trigger even if duplex or speed condition doesn't match */ -+#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13) -+#define QCA808X_LED_FULL_DUPLEX_ON BIT(12) -+#define QCA808X_LED_HALF_DUPLEX_ON BIT(11) -+#define QCA808X_LED_TX_BLINK BIT(10) -+#define QCA808X_LED_RX_BLINK BIT(9) -+#define QCA808X_LED_TX_ON_10MS BIT(8) -+#define QCA808X_LED_RX_ON_10MS BIT(7) -+#define QCA808X_LED_SPEED1000_ON BIT(6) -+#define QCA808X_LED_SPEED100_ON BIT(5) -+#define QCA808X_LED_SPEED10_ON BIT(4) -+#define QCA808X_LED_COLLISION_BLINK BIT(3) -+#define QCA808X_LED_SPEED1000_BLINK BIT(2) -+#define QCA808X_LED_SPEED100_BLINK BIT(1) -+#define QCA808X_LED_SPEED10_BLINK BIT(0) -+ -+#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079 -+#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2)) -+ -+/* LED force ctrl is the same for every LED -+ * No documentation exist for this, not even internal one -+ * with NDA as QCOM gives only info about configuring -+ * hw control pattern rules and doesn't indicate any way -+ * to force the LED to specific mode. -+ * These define comes from reverse and testing and maybe -+ * lack of some info or some info are not entirely correct. -+ * For the basic LED control and hw control these finding -+ * are enough to support LED control in all the required APIs. -+ * -+ * On doing some comparison with implementation with qca807x, -+ * it was found that it's 1:1 equal to it and confirms all the -+ * reverse done. It was also found further specification with the -+ * force mode and the blink modes. -+ */ -+#define QCA808X_LED_FORCE_EN BIT(15) -+#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13) -+#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3) -+#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2) -+#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1) -+#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0) -+ -+#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a -+/* QSDK sets by default 0x46 to this reg that sets BIT 6 for -+ * LED to active high. It's not clear what BIT 3 and BIT 4 does. -+ */ -+#define QCA808X_LED_ACTIVE_HIGH BIT(6) -+ -+/* QCA808X 1G chip type */ -+#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d -+#define QCA808X_PHY_CHIP_TYPE_1G BIT(0) -+ -+#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 -+#define QCA8081_PHY_FIFO_RSTN BIT(11) -+ -+MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); -+MODULE_AUTHOR("Matus Ujhelyi"); -+MODULE_LICENSE("GPL"); -+ -+enum stat_access_type { -+ PHY, -+ MMD -+}; -+ -+struct at803x_hw_stat { -+ const char *string; -+ u8 reg; -+ u32 mask; -+ enum stat_access_type access_type; -+}; -+ -+static struct at803x_hw_stat qca83xx_hw_stats[] = { -+ { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, -+ { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, -+ { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, -+}; -+ -+struct at803x_ss_mask { -+ u16 speed_mask; -+ u8 speed_shift; -+}; -+ -+struct at803x_priv { -+ int flags; -+ u16 clk_25m_reg; -+ u16 clk_25m_mask; -+ u8 smarteee_lpi_tw_1g; -+ u8 smarteee_lpi_tw_100m; -+ bool is_fiber; -+ bool is_1000basex; -+ struct regulator_dev *vddio_rdev; -+ struct regulator_dev *vddh_rdev; -+ u64 stats[ARRAY_SIZE(qca83xx_hw_stats)]; -+ int led_polarity_mode; -+}; -+ -+struct at803x_context { -+ u16 bmcr; -+ u16 advertise; -+ u16 control1000; -+ u16 int_enable; -+ u16 smart_speed; -+ u16 led_control; -+}; -+ -+static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) -+{ -+ int ret; -+ -+ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); -+ if (ret < 0) -+ return ret; -+ -+ return phy_write(phydev, AT803X_DEBUG_DATA, data); -+} -+ -+static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) -+{ -+ int ret; -+ -+ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); -+ if (ret < 0) -+ return ret; -+ -+ return phy_read(phydev, AT803X_DEBUG_DATA); -+} -+ -+static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, -+ u16 clear, u16 set) -+{ -+ u16 val; -+ int ret; -+ -+ ret = at803x_debug_reg_read(phydev, reg); -+ if (ret < 0) -+ return ret; -+ -+ val = ret & 0xffff; -+ val &= ~clear; -+ val |= set; -+ -+ return phy_write(phydev, AT803X_DEBUG_DATA, val); -+} -+ -+static int at803x_write_page(struct phy_device *phydev, int page) -+{ -+ int mask; -+ int set; -+ -+ if (page == AT803X_PAGE_COPPER) { -+ set = AT803X_BT_BX_REG_SEL; -+ mask = 0; -+ } else { -+ set = 0; -+ mask = AT803X_BT_BX_REG_SEL; -+ } -+ -+ return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); -+} -+ -+static int at803x_read_page(struct phy_device *phydev) -+{ -+ int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); -+ -+ if (ccr < 0) -+ return ccr; -+ -+ if (ccr & AT803X_BT_BX_REG_SEL) -+ return AT803X_PAGE_COPPER; -+ -+ return AT803X_PAGE_FIBER; -+} -+ -+static int at803x_enable_rx_delay(struct phy_device *phydev) -+{ -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, -+ AT803X_DEBUG_RX_CLK_DLY_EN); -+} -+ -+static int at803x_enable_tx_delay(struct phy_device *phydev) -+{ -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, -+ AT803X_DEBUG_TX_CLK_DLY_EN); -+} -+ -+static int at803x_disable_rx_delay(struct phy_device *phydev) -+{ -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, -+ AT803X_DEBUG_RX_CLK_DLY_EN, 0); -+} -+ -+static int at803x_disable_tx_delay(struct phy_device *phydev) -+{ -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, -+ AT803X_DEBUG_TX_CLK_DLY_EN, 0); -+} -+ -+/* save relevant PHY registers to private copy */ -+static void at803x_context_save(struct phy_device *phydev, -+ struct at803x_context *context) -+{ -+ context->bmcr = phy_read(phydev, MII_BMCR); -+ context->advertise = phy_read(phydev, MII_ADVERTISE); -+ context->control1000 = phy_read(phydev, MII_CTRL1000); -+ context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); -+ context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); -+ context->led_control = phy_read(phydev, AT803X_LED_CONTROL); -+} -+ -+/* restore relevant PHY registers from private copy */ -+static void at803x_context_restore(struct phy_device *phydev, -+ const struct at803x_context *context) -+{ -+ phy_write(phydev, MII_BMCR, context->bmcr); -+ phy_write(phydev, MII_ADVERTISE, context->advertise); -+ phy_write(phydev, MII_CTRL1000, context->control1000); -+ phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); -+ phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); -+ phy_write(phydev, AT803X_LED_CONTROL, context->led_control); -+} -+ -+static int at803x_set_wol(struct phy_device *phydev, -+ struct ethtool_wolinfo *wol) -+{ -+ int ret, irq_enabled; -+ -+ if (wol->wolopts & WAKE_MAGIC) { -+ struct net_device *ndev = phydev->attached_dev; -+ const u8 *mac; -+ unsigned int i; -+ static const unsigned int offsets[] = { -+ AT803X_LOC_MAC_ADDR_32_47_OFFSET, -+ AT803X_LOC_MAC_ADDR_16_31_OFFSET, -+ AT803X_LOC_MAC_ADDR_0_15_OFFSET, -+ }; -+ -+ if (!ndev) -+ return -ENODEV; -+ -+ mac = (const u8 *)ndev->dev_addr; -+ -+ if (!is_valid_ether_addr(mac)) -+ return -EINVAL; -+ -+ for (i = 0; i < 3; i++) -+ phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], -+ mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); -+ -+ /* Enable WOL interrupt */ -+ ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); -+ if (ret) -+ return ret; -+ } else { -+ /* Disable WOL interrupt */ -+ ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); -+ if (ret) -+ return ret; -+ } -+ -+ /* Clear WOL status */ -+ ret = phy_read(phydev, AT803X_INTR_STATUS); -+ if (ret < 0) -+ return ret; -+ -+ /* Check if there are other interrupts except for WOL triggered when PHY is -+ * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can -+ * be passed up to the interrupt PIN. -+ */ -+ irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); -+ if (irq_enabled < 0) -+ return irq_enabled; -+ -+ irq_enabled &= ~AT803X_INTR_ENABLE_WOL; -+ if (ret & irq_enabled && !phy_polling_mode(phydev)) -+ phy_trigger_machine(phydev); -+ -+ return 0; -+} -+ -+static void at803x_get_wol(struct phy_device *phydev, -+ struct ethtool_wolinfo *wol) -+{ -+ int value; -+ -+ wol->supported = WAKE_MAGIC; -+ wol->wolopts = 0; -+ -+ value = phy_read(phydev, AT803X_INTR_ENABLE); -+ if (value < 0) -+ return; -+ -+ if (value & AT803X_INTR_ENABLE_WOL) -+ wol->wolopts |= WAKE_MAGIC; -+} -+ -+static int qca83xx_get_sset_count(struct phy_device *phydev) -+{ -+ return ARRAY_SIZE(qca83xx_hw_stats); -+} -+ -+static void qca83xx_get_strings(struct phy_device *phydev, u8 *data) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) { -+ strscpy(data + i * ETH_GSTRING_LEN, -+ qca83xx_hw_stats[i].string, ETH_GSTRING_LEN); -+ } -+} -+ -+static u64 qca83xx_get_stat(struct phy_device *phydev, int i) -+{ -+ struct at803x_hw_stat stat = qca83xx_hw_stats[i]; -+ struct at803x_priv *priv = phydev->priv; -+ int val; -+ u64 ret; -+ -+ if (stat.access_type == MMD) -+ val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); -+ else -+ val = phy_read(phydev, stat.reg); -+ -+ if (val < 0) { -+ ret = U64_MAX; -+ } else { -+ val = val & stat.mask; -+ priv->stats[i] += val; -+ ret = priv->stats[i]; -+ } -+ -+ return ret; -+} -+ -+static void qca83xx_get_stats(struct phy_device *phydev, -+ struct ethtool_stats *stats, u64 *data) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) -+ data[i] = qca83xx_get_stat(phydev, i); -+} -+ -+static int at803x_suspend(struct phy_device *phydev) -+{ -+ int value; -+ int wol_enabled; -+ -+ value = phy_read(phydev, AT803X_INTR_ENABLE); -+ wol_enabled = value & AT803X_INTR_ENABLE_WOL; -+ -+ if (wol_enabled) -+ value = BMCR_ISOLATE; -+ else -+ value = BMCR_PDOWN; -+ -+ phy_modify(phydev, MII_BMCR, 0, value); -+ -+ return 0; -+} -+ -+static int at803x_resume(struct phy_device *phydev) -+{ -+ return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); -+} -+ -+static int at803x_parse_dt(struct phy_device *phydev) -+{ -+ struct device_node *node = phydev->mdio.dev.of_node; -+ struct at803x_priv *priv = phydev->priv; -+ u32 freq, strength, tw; -+ unsigned int sel; -+ int ret; -+ -+ if (!IS_ENABLED(CONFIG_OF_MDIO)) -+ return 0; -+ -+ if (of_property_read_bool(node, "qca,disable-smarteee")) -+ priv->flags |= AT803X_DISABLE_SMARTEEE; -+ -+ if (of_property_read_bool(node, "qca,disable-hibernation-mode")) -+ priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; -+ -+ if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { -+ if (!tw || tw > 255) { -+ phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); -+ return -EINVAL; -+ } -+ priv->smarteee_lpi_tw_1g = tw; -+ } -+ -+ if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { -+ if (!tw || tw > 255) { -+ phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); -+ return -EINVAL; -+ } -+ priv->smarteee_lpi_tw_100m = tw; -+ } -+ -+ ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); -+ if (!ret) { -+ switch (freq) { -+ case 25000000: -+ sel = AT803X_CLK_OUT_25MHZ_XTAL; -+ break; -+ case 50000000: -+ sel = AT803X_CLK_OUT_50MHZ_PLL; -+ break; -+ case 62500000: -+ sel = AT803X_CLK_OUT_62_5MHZ_PLL; -+ break; -+ case 125000000: -+ sel = AT803X_CLK_OUT_125MHZ_PLL; -+ break; -+ default: -+ phydev_err(phydev, "invalid qca,clk-out-frequency\n"); -+ return -EINVAL; -+ } -+ -+ priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); -+ priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; -+ } -+ -+ ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); -+ if (!ret) { -+ priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; -+ switch (strength) { -+ case AR803X_STRENGTH_FULL: -+ priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; -+ break; -+ case AR803X_STRENGTH_HALF: -+ priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; -+ break; -+ case AR803X_STRENGTH_QUARTER: -+ priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; -+ break; -+ default: -+ phydev_err(phydev, "invalid qca,clk-out-strength\n"); -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+ -+static int at803x_probe(struct phy_device *phydev) -+{ -+ struct device *dev = &phydev->mdio.dev; -+ struct at803x_priv *priv; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ /* Init LED polarity mode to -1 */ -+ priv->led_polarity_mode = -1; -+ -+ phydev->priv = priv; -+ -+ ret = at803x_parse_dt(phydev); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int at803x_get_features(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ int err; -+ -+ err = genphy_read_abilities(phydev); -+ if (err) -+ return err; -+ -+ if (phydev->drv->phy_id != ATH8031_PHY_ID) -+ return 0; -+ -+ /* AR8031/AR8033 have different status registers -+ * for copper and fiber operation. However, the -+ * extended status register is the same for both -+ * operation modes. -+ * -+ * As a result of that, ESTATUS_1000_XFULL is set -+ * to 1 even when operating in copper TP mode. -+ * -+ * Remove this mode from the supported link modes -+ * when not operating in 1000BaseX mode. -+ */ -+ if (!priv->is_1000basex) -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, -+ phydev->supported); -+ -+ return 0; -+} -+ -+static int at803x_smarteee_config(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ u16 mask = 0, val = 0; -+ int ret; -+ -+ if (priv->flags & AT803X_DISABLE_SMARTEEE) -+ return phy_modify_mmd(phydev, MDIO_MMD_PCS, -+ AT803X_MMD3_SMARTEEE_CTL3, -+ AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); -+ -+ if (priv->smarteee_lpi_tw_1g) { -+ mask |= 0xff00; -+ val |= priv->smarteee_lpi_tw_1g << 8; -+ } -+ if (priv->smarteee_lpi_tw_100m) { -+ mask |= 0x00ff; -+ val |= priv->smarteee_lpi_tw_100m; -+ } -+ if (!mask) -+ return 0; -+ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, -+ mask, val); -+ if (ret) -+ return ret; -+ -+ return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, -+ AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, -+ AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); -+} -+ -+static int at803x_clk_out_config(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ -+ if (!priv->clk_25m_mask) -+ return 0; -+ -+ return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, -+ priv->clk_25m_mask, priv->clk_25m_reg); -+} -+ -+static int at8031_pll_config(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ -+ /* The default after hardware reset is PLL OFF. After a soft reset, the -+ * values are retained. -+ */ -+ if (priv->flags & AT803X_KEEP_PLL_ENABLED) -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, -+ 0, AT803X_DEBUG_PLL_ON); -+ else -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, -+ AT803X_DEBUG_PLL_ON, 0); -+} -+ -+static int at803x_hibernation_mode_config(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ -+ /* The default after hardware reset is hibernation mode enabled. After -+ * software reset, the value is retained. -+ */ -+ if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) -+ return 0; -+ -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, -+ AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); -+} -+ -+static int at803x_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* The RX and TX delay default is: -+ * after HW reset: RX delay enabled and TX delay disabled -+ * after SW reset: RX delay enabled, while TX delay retains the -+ * value before reset. -+ */ -+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || -+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) -+ ret = at803x_enable_rx_delay(phydev); -+ else -+ ret = at803x_disable_rx_delay(phydev); -+ if (ret < 0) -+ return ret; -+ -+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || -+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) -+ ret = at803x_enable_tx_delay(phydev); -+ else -+ ret = at803x_disable_tx_delay(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ret = at803x_smarteee_config(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ret = at803x_clk_out_config(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ret = at803x_hibernation_mode_config(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* Ar803x extended next page bit is enabled by default. Cisco -+ * multigig switches read this bit and attempt to negotiate 10Gbps -+ * rates even if the next page bit is disabled. This is incorrect -+ * behaviour but we still need to accommodate it. XNP is only needed -+ * for 10Gbps support, so disable XNP. -+ */ -+ return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); -+} -+ -+static int at803x_ack_interrupt(struct phy_device *phydev) -+{ -+ int err; -+ -+ err = phy_read(phydev, AT803X_INTR_STATUS); -+ -+ return (err < 0) ? err : 0; -+} -+ -+static int at803x_config_intr(struct phy_device *phydev) -+{ -+ int err; -+ int value; -+ -+ value = phy_read(phydev, AT803X_INTR_ENABLE); -+ -+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { -+ /* Clear any pending interrupts */ -+ err = at803x_ack_interrupt(phydev); -+ if (err) -+ return err; -+ -+ value |= AT803X_INTR_ENABLE_AUTONEG_ERR; -+ value |= AT803X_INTR_ENABLE_SPEED_CHANGED; -+ value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; -+ value |= AT803X_INTR_ENABLE_LINK_FAIL; -+ value |= AT803X_INTR_ENABLE_LINK_SUCCESS; -+ -+ err = phy_write(phydev, AT803X_INTR_ENABLE, value); -+ } else { -+ err = phy_write(phydev, AT803X_INTR_ENABLE, 0); -+ if (err) -+ return err; -+ -+ /* Clear any pending interrupts */ -+ err = at803x_ack_interrupt(phydev); -+ } -+ -+ return err; -+} -+ -+static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) -+{ -+ int irq_status, int_enabled; -+ -+ irq_status = phy_read(phydev, AT803X_INTR_STATUS); -+ if (irq_status < 0) { -+ phy_error(phydev); -+ return IRQ_NONE; -+ } -+ -+ /* Read the current enabled interrupts */ -+ int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); -+ if (int_enabled < 0) { -+ phy_error(phydev); -+ return IRQ_NONE; -+ } -+ -+ /* See if this was one of our enabled interrupts */ -+ if (!(irq_status & int_enabled)) -+ return IRQ_NONE; -+ -+ phy_trigger_machine(phydev); -+ -+ return IRQ_HANDLED; -+} -+ -+static void at803x_link_change_notify(struct phy_device *phydev) -+{ -+ /* -+ * Conduct a hardware reset for AT8030 every time a link loss is -+ * signalled. This is necessary to circumvent a hardware bug that -+ * occurs when the cable is unplugged while TX packets are pending -+ * in the FIFO. In such cases, the FIFO enters an error mode it -+ * cannot recover from by software. -+ */ -+ if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { -+ struct at803x_context context; -+ -+ at803x_context_save(phydev, &context); -+ -+ phy_device_reset(phydev, 1); -+ usleep_range(1000, 2000); -+ phy_device_reset(phydev, 0); -+ usleep_range(1000, 2000); -+ -+ at803x_context_restore(phydev, &context); -+ -+ phydev_dbg(phydev, "%s(): phy was reset\n", __func__); -+ } -+} -+ -+static int at803x_read_specific_status(struct phy_device *phydev, -+ struct at803x_ss_mask ss_mask) -+{ -+ int ss; -+ -+ /* Read the AT8035 PHY-Specific Status register, which indicates the -+ * speed and duplex that the PHY is actually using, irrespective of -+ * whether we are in autoneg mode or not. -+ */ -+ ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); -+ if (ss < 0) -+ return ss; -+ -+ if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { -+ int sfc, speed; -+ -+ sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); -+ if (sfc < 0) -+ return sfc; -+ -+ speed = ss & ss_mask.speed_mask; -+ speed >>= ss_mask.speed_shift; -+ -+ switch (speed) { -+ case AT803X_SS_SPEED_10: -+ phydev->speed = SPEED_10; -+ break; -+ case AT803X_SS_SPEED_100: -+ phydev->speed = SPEED_100; -+ break; -+ case AT803X_SS_SPEED_1000: -+ phydev->speed = SPEED_1000; -+ break; -+ case QCA808X_SS_SPEED_2500: -+ phydev->speed = SPEED_2500; -+ break; -+ } -+ if (ss & AT803X_SS_DUPLEX) -+ phydev->duplex = DUPLEX_FULL; -+ else -+ phydev->duplex = DUPLEX_HALF; -+ -+ if (ss & AT803X_SS_MDIX) -+ phydev->mdix = ETH_TP_MDI_X; -+ else -+ phydev->mdix = ETH_TP_MDI; -+ -+ switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { -+ case AT803X_SFC_MANUAL_MDI: -+ phydev->mdix_ctrl = ETH_TP_MDI; -+ break; -+ case AT803X_SFC_MANUAL_MDIX: -+ phydev->mdix_ctrl = ETH_TP_MDI_X; -+ break; -+ case AT803X_SFC_AUTOMATIC_CROSSOVER: -+ phydev->mdix_ctrl = ETH_TP_MDI_AUTO; -+ break; -+ } -+ } -+ -+ return 0; -+} -+ -+static int at803x_read_status(struct phy_device *phydev) -+{ -+ struct at803x_ss_mask ss_mask = { 0 }; -+ int err, old_link = phydev->link; -+ -+ /* Update the link, but return if there was an error */ -+ err = genphy_update_link(phydev); -+ if (err) -+ return err; -+ -+ /* why bother the PHY if nothing can have changed */ -+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) -+ return 0; -+ -+ phydev->speed = SPEED_UNKNOWN; -+ phydev->duplex = DUPLEX_UNKNOWN; -+ phydev->pause = 0; -+ phydev->asym_pause = 0; -+ -+ err = genphy_read_lpa(phydev); -+ if (err < 0) -+ return err; -+ -+ ss_mask.speed_mask = AT803X_SS_SPEED_MASK; -+ ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK); -+ err = at803x_read_specific_status(phydev, ss_mask); -+ if (err < 0) -+ return err; -+ -+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) -+ phy_resolve_aneg_pause(phydev); -+ -+ return 0; -+} -+ -+static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) -+{ -+ u16 val; -+ -+ switch (ctrl) { -+ case ETH_TP_MDI: -+ val = AT803X_SFC_MANUAL_MDI; -+ break; -+ case ETH_TP_MDI_X: -+ val = AT803X_SFC_MANUAL_MDIX; -+ break; -+ case ETH_TP_MDI_AUTO: -+ val = AT803X_SFC_AUTOMATIC_CROSSOVER; -+ break; -+ default: -+ return 0; -+ } -+ -+ return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, -+ AT803X_SFC_MDI_CROSSOVER_MODE_M, -+ FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); -+} -+ -+static int at803x_prepare_config_aneg(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); -+ if (ret < 0) -+ return ret; -+ -+ /* Changes of the midx bits are disruptive to the normal operation; -+ * therefore any changes to these registers must be followed by a -+ * software reset to take effect. -+ */ -+ if (ret == 1) { -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int at803x_config_aneg(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ int ret; -+ -+ ret = at803x_prepare_config_aneg(phydev); -+ if (ret) -+ return ret; -+ -+ if (priv->is_1000basex) -+ return genphy_c37_config_aneg(phydev); -+ -+ return genphy_config_aneg(phydev); -+} -+ -+static int at803x_get_downshift(struct phy_device *phydev, u8 *d) -+{ -+ int val; -+ -+ val = phy_read(phydev, AT803X_SMART_SPEED); -+ if (val < 0) -+ return val; -+ -+ if (val & AT803X_SMART_SPEED_ENABLE) -+ *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; -+ else -+ *d = DOWNSHIFT_DEV_DISABLE; -+ -+ return 0; -+} -+ -+static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) -+{ -+ u16 mask, set; -+ int ret; -+ -+ switch (cnt) { -+ case DOWNSHIFT_DEV_DEFAULT_COUNT: -+ cnt = AT803X_DEFAULT_DOWNSHIFT; -+ fallthrough; -+ case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: -+ set = AT803X_SMART_SPEED_ENABLE | -+ AT803X_SMART_SPEED_BYPASS_TIMER | -+ FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); -+ mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; -+ break; -+ case DOWNSHIFT_DEV_DISABLE: -+ set = 0; -+ mask = AT803X_SMART_SPEED_ENABLE | -+ AT803X_SMART_SPEED_BYPASS_TIMER; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); -+ -+ /* After changing the smart speed settings, we need to perform a -+ * software reset, use phy_init_hw() to make sure we set the -+ * reapply any values which might got lost during software reset. -+ */ -+ if (ret == 1) -+ ret = phy_init_hw(phydev); -+ -+ return ret; -+} -+ -+static int at803x_get_tunable(struct phy_device *phydev, -+ struct ethtool_tunable *tuna, void *data) -+{ -+ switch (tuna->id) { -+ case ETHTOOL_PHY_DOWNSHIFT: -+ return at803x_get_downshift(phydev, data); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static int at803x_set_tunable(struct phy_device *phydev, -+ struct ethtool_tunable *tuna, const void *data) -+{ -+ switch (tuna->id) { -+ case ETHTOOL_PHY_DOWNSHIFT: -+ return at803x_set_downshift(phydev, *(const u8 *)data); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+static int at803x_cable_test_result_trans(u16 status) -+{ -+ switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { -+ case AT803X_CDT_STATUS_STAT_NORMAL: -+ return ETHTOOL_A_CABLE_RESULT_CODE_OK; -+ case AT803X_CDT_STATUS_STAT_SHORT: -+ return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; -+ case AT803X_CDT_STATUS_STAT_OPEN: -+ return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; -+ case AT803X_CDT_STATUS_STAT_FAIL: -+ default: -+ return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; -+ } -+} -+ -+static bool at803x_cdt_test_failed(u16 status) -+{ -+ return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == -+ AT803X_CDT_STATUS_STAT_FAIL; -+} -+ -+static bool at803x_cdt_fault_length_valid(u16 status) -+{ -+ switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { -+ case AT803X_CDT_STATUS_STAT_OPEN: -+ case AT803X_CDT_STATUS_STAT_SHORT: -+ return true; -+ } -+ return false; -+} -+ -+static int at803x_cdt_fault_length(int dt) -+{ -+ /* According to the datasheet the distance to the fault is -+ * DELTA_TIME * 0.824 meters. -+ * -+ * The author suspect the correct formula is: -+ * -+ * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 -+ * -+ * where c is the speed of light, VF is the velocity factor of -+ * the twisted pair cable, 125MHz the counter frequency and -+ * we need to divide by 2 because the hardware will measure the -+ * round trip time to the fault and back to the PHY. -+ * -+ * With a VF of 0.69 we get the factor 0.824 mentioned in the -+ * datasheet. -+ */ -+ return (dt * 824) / 10; -+} -+ -+static int at803x_cdt_start(struct phy_device *phydev, -+ u32 cdt_start) -+{ -+ return phy_write(phydev, AT803X_CDT, cdt_start); -+} -+ -+static int at803x_cdt_wait_for_completion(struct phy_device *phydev, -+ u32 cdt_en) -+{ -+ int val, ret; -+ -+ /* One test run takes about 25ms */ -+ ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, -+ !(val & cdt_en), -+ 30000, 100000, true); -+ -+ return ret < 0 ? ret : 0; -+} -+ -+static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) -+{ -+ static const int ethtool_pair[] = { -+ ETHTOOL_A_CABLE_PAIR_A, -+ ETHTOOL_A_CABLE_PAIR_B, -+ ETHTOOL_A_CABLE_PAIR_C, -+ ETHTOOL_A_CABLE_PAIR_D, -+ }; -+ int ret, val; -+ -+ val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | -+ AT803X_CDT_ENABLE_TEST; -+ ret = at803x_cdt_start(phydev, val); -+ if (ret) -+ return ret; -+ -+ ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST); -+ if (ret) -+ return ret; -+ -+ val = phy_read(phydev, AT803X_CDT_STATUS); -+ if (val < 0) -+ return val; -+ -+ if (at803x_cdt_test_failed(val)) -+ return 0; -+ -+ ethnl_cable_test_result(phydev, ethtool_pair[pair], -+ at803x_cable_test_result_trans(val)); -+ -+ if (at803x_cdt_fault_length_valid(val)) { -+ val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val); -+ ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], -+ at803x_cdt_fault_length(val)); -+ } -+ -+ return 1; -+} -+ -+static int at803x_cable_test_get_status(struct phy_device *phydev, -+ bool *finished, unsigned long pair_mask) -+{ -+ int retries = 20; -+ int pair, ret; -+ -+ *finished = false; -+ -+ /* According to the datasheet the CDT can be performed when -+ * there is no link partner or when the link partner is -+ * auto-negotiating. Starting the test will restart the AN -+ * automatically. It seems that doing this repeatedly we will -+ * get a slot where our link partner won't disturb our -+ * measurement. -+ */ -+ while (pair_mask && retries--) { -+ for_each_set_bit(pair, &pair_mask, 4) { -+ ret = at803x_cable_test_one_pair(phydev, pair); -+ if (ret < 0) -+ return ret; -+ if (ret) -+ clear_bit(pair, &pair_mask); -+ } -+ if (pair_mask) -+ msleep(250); -+ } -+ -+ *finished = true; -+ -+ return 0; -+} -+ -+static void at803x_cable_test_autoneg(struct phy_device *phydev) -+{ -+ /* Enable auto-negotiation, but advertise no capabilities, no link -+ * will be established. A restart of the auto-negotiation is not -+ * required, because the cable test will automatically break the link. -+ */ -+ phy_write(phydev, MII_BMCR, BMCR_ANENABLE); -+ phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); -+} -+ -+static int at803x_cable_test_start(struct phy_device *phydev) -+{ -+ at803x_cable_test_autoneg(phydev); -+ /* we do all the (time consuming) work later */ -+ return 0; -+} -+ -+static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, -+ unsigned int selector) -+{ -+ struct phy_device *phydev = rdev_get_drvdata(rdev); -+ -+ if (selector) -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, -+ 0, AT803X_DEBUG_RGMII_1V8); -+ else -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, -+ AT803X_DEBUG_RGMII_1V8, 0); -+} -+ -+static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) -+{ -+ struct phy_device *phydev = rdev_get_drvdata(rdev); -+ int val; -+ -+ val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); -+ if (val < 0) -+ return val; -+ -+ return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; -+} -+ -+static const struct regulator_ops vddio_regulator_ops = { -+ .list_voltage = regulator_list_voltage_table, -+ .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel, -+ .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel, -+}; -+ -+static const unsigned int vddio_voltage_table[] = { -+ 1500000, -+ 1800000, -+}; -+ -+static const struct regulator_desc vddio_desc = { -+ .name = "vddio", -+ .of_match = of_match_ptr("vddio-regulator"), -+ .n_voltages = ARRAY_SIZE(vddio_voltage_table), -+ .volt_table = vddio_voltage_table, -+ .ops = &vddio_regulator_ops, -+ .type = REGULATOR_VOLTAGE, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct regulator_ops vddh_regulator_ops = { -+}; -+ -+static const struct regulator_desc vddh_desc = { -+ .name = "vddh", -+ .of_match = of_match_ptr("vddh-regulator"), -+ .n_voltages = 1, -+ .fixed_uV = 2500000, -+ .ops = &vddh_regulator_ops, -+ .type = REGULATOR_VOLTAGE, -+ .owner = THIS_MODULE, -+}; -+ -+static int at8031_register_regulators(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ struct device *dev = &phydev->mdio.dev; -+ struct regulator_config config = { }; -+ -+ config.dev = dev; -+ config.driver_data = phydev; -+ -+ priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); -+ if (IS_ERR(priv->vddio_rdev)) { -+ phydev_err(phydev, "failed to register VDDIO regulator\n"); -+ return PTR_ERR(priv->vddio_rdev); -+ } -+ -+ priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); -+ if (IS_ERR(priv->vddh_rdev)) { -+ phydev_err(phydev, "failed to register VDDH regulator\n"); -+ return PTR_ERR(priv->vddh_rdev); -+ } -+ -+ return 0; -+} -+ -+static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) -+{ -+ struct phy_device *phydev = upstream; -+ __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); -+ __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); -+ DECLARE_PHY_INTERFACE_MASK(interfaces); -+ phy_interface_t iface; -+ -+ linkmode_zero(phy_support); -+ phylink_set(phy_support, 1000baseX_Full); -+ phylink_set(phy_support, 1000baseT_Full); -+ phylink_set(phy_support, Autoneg); -+ phylink_set(phy_support, Pause); -+ phylink_set(phy_support, Asym_Pause); -+ -+ linkmode_zero(sfp_support); -+ sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); -+ /* Some modules support 10G modes as well as others we support. -+ * Mask out non-supported modes so the correct interface is picked. -+ */ -+ linkmode_and(sfp_support, phy_support, sfp_support); -+ -+ if (linkmode_empty(sfp_support)) { -+ dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); -+ return -EINVAL; -+ } -+ -+ iface = sfp_select_interface(phydev->sfp_bus, sfp_support); -+ -+ /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes -+ * interface for use with SFP modules. -+ * However, some copper modules detected as having a preferred SGMII -+ * interface do default to and function in 1000Base-X mode, so just -+ * print a warning and allow such modules, as they may have some chance -+ * of working. -+ */ -+ if (iface == PHY_INTERFACE_MODE_SGMII) -+ dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); -+ else if (iface != PHY_INTERFACE_MODE_1000BASEX) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static const struct sfp_upstream_ops at8031_sfp_ops = { -+ .attach = phy_sfp_attach, -+ .detach = phy_sfp_detach, -+ .module_insert = at8031_sfp_insert, -+}; -+ -+static int at8031_parse_dt(struct phy_device *phydev) -+{ -+ struct device_node *node = phydev->mdio.dev.of_node; -+ struct at803x_priv *priv = phydev->priv; -+ int ret; -+ -+ if (of_property_read_bool(node, "qca,keep-pll-enabled")) -+ priv->flags |= AT803X_KEEP_PLL_ENABLED; -+ -+ ret = at8031_register_regulators(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, -+ "vddio"); -+ if (ret) { -+ phydev_err(phydev, "failed to get VDDIO regulator\n"); -+ return ret; -+ } -+ -+ /* Only AR8031/8033 support 1000Base-X for SFP modules */ -+ return phy_sfp_probe(phydev, &at8031_sfp_ops); -+} -+ -+static int at8031_probe(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ int mode_cfg; -+ int ccr; -+ int ret; -+ -+ ret = at803x_probe(phydev); -+ if (ret) -+ return ret; -+ -+ /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping -+ * options. -+ */ -+ ret = at8031_parse_dt(phydev); -+ if (ret) -+ return ret; -+ -+ ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); -+ if (ccr < 0) -+ return ccr; -+ mode_cfg = ccr & AT803X_MODE_CFG_MASK; -+ -+ switch (mode_cfg) { -+ case AT803X_MODE_CFG_BX1000_RGMII_50OHM: -+ case AT803X_MODE_CFG_BX1000_RGMII_75OHM: -+ priv->is_1000basex = true; -+ fallthrough; -+ case AT803X_MODE_CFG_FX100_RGMII_50OHM: -+ case AT803X_MODE_CFG_FX100_RGMII_75OHM: -+ priv->is_fiber = true; -+ break; -+ } -+ -+ /* Disable WoL in 1588 register which is enabled -+ * by default -+ */ -+ return phy_modify_mmd(phydev, MDIO_MMD_PCS, -+ AT803X_PHY_MMD3_WOL_CTRL, -+ AT803X_WOL_EN, 0); -+} -+ -+static int at8031_config_init(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ int ret; -+ -+ /* Some bootloaders leave the fiber page selected. -+ * Switch to the appropriate page (fiber or copper), as otherwise we -+ * read the PHY capabilities from the wrong page. -+ */ -+ phy_lock_mdio_bus(phydev); -+ ret = at803x_write_page(phydev, -+ priv->is_fiber ? AT803X_PAGE_FIBER : -+ AT803X_PAGE_COPPER); -+ phy_unlock_mdio_bus(phydev); -+ if (ret) -+ return ret; -+ -+ ret = at8031_pll_config(phydev); -+ if (ret < 0) -+ return ret; -+ -+ return at803x_config_init(phydev); -+} -+ -+static int at8031_set_wol(struct phy_device *phydev, -+ struct ethtool_wolinfo *wol) -+{ -+ int ret; -+ -+ /* First setup MAC address and enable WOL interrupt */ -+ ret = at803x_set_wol(phydev, wol); -+ if (ret) -+ return ret; -+ -+ if (wol->wolopts & WAKE_MAGIC) -+ /* Enable WOL function for 1588 */ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, -+ AT803X_PHY_MMD3_WOL_CTRL, -+ 0, AT803X_WOL_EN); -+ else -+ /* Disable WoL function for 1588 */ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, -+ AT803X_PHY_MMD3_WOL_CTRL, -+ AT803X_WOL_EN, 0); -+ -+ return ret; -+} -+ -+static int at8031_config_intr(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ int err, value = 0; -+ -+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED && -+ priv->is_fiber) { -+ /* Clear any pending interrupts */ -+ err = at803x_ack_interrupt(phydev); -+ if (err) -+ return err; -+ -+ value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; -+ value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; -+ -+ err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value); -+ if (err) -+ return err; -+ } -+ -+ return at803x_config_intr(phydev); -+} -+ -+/* AR8031 and AR8033 share the same read status logic */ -+static int at8031_read_status(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ -+ if (priv->is_1000basex) -+ return genphy_c37_read_status(phydev); -+ -+ return at803x_read_status(phydev); -+} -+ -+/* AR8031 and AR8035 share the same cable test get status reg */ -+static int at8031_cable_test_get_status(struct phy_device *phydev, -+ bool *finished) -+{ -+ return at803x_cable_test_get_status(phydev, finished, 0xf); -+} -+ -+/* AR8031 and AR8035 share the same cable test start logic */ -+static int at8031_cable_test_start(struct phy_device *phydev) -+{ -+ at803x_cable_test_autoneg(phydev); -+ phy_write(phydev, MII_CTRL1000, 0); -+ /* we do all the (time consuming) work later */ -+ return 0; -+} -+ -+/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */ -+static int at8032_cable_test_get_status(struct phy_device *phydev, -+ bool *finished) -+{ -+ return at803x_cable_test_get_status(phydev, finished, 0x3); -+} -+ -+static int at8035_parse_dt(struct phy_device *phydev) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ -+ /* Mask is set by the generic at803x_parse_dt -+ * if property is set. Assume property is set -+ * with the mask not zero. -+ */ -+ if (priv->clk_25m_mask) { -+ /* Fixup for the AR8030/AR8035. This chip has another mask and -+ * doesn't support the DSP reference. Eg. the lowest bit of the -+ * mask. The upper two bits select the same frequencies. Mask -+ * the lowest bit here. -+ * -+ * Warning: -+ * There was no datasheet for the AR8030 available so this is -+ * just a guess. But the AR8035 is listed as pin compatible -+ * to the AR8030 so there might be a good chance it works on -+ * the AR8030 too. -+ */ -+ priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; -+ priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; -+ } -+ -+ return 0; -+} -+ -+/* AR8030 and AR8035 shared the same special mask for clk_25m */ -+static int at8035_probe(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ret = at803x_probe(phydev); -+ if (ret) -+ return ret; -+ -+ return at8035_parse_dt(phydev); -+} -+ -+static int qca83xx_config_init(struct phy_device *phydev) -+{ -+ u8 switch_revision; -+ -+ switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; -+ -+ switch (switch_revision) { -+ case 1: -+ /* For 100M waveform */ -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); -+ /* Turn on Gigabit clock */ -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); -+ break; -+ -+ case 2: -+ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); -+ fallthrough; -+ case 4: -+ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); -+ break; -+ } -+ -+ /* Following original QCA sourcecode set port to prefer master */ -+ phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); -+ -+ return 0; -+} -+ -+static int qca8327_config_init(struct phy_device *phydev) -+{ -+ /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. -+ * Disable on init and enable only with 100m speed following -+ * qca original source code. -+ */ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, -+ QCA8327_DEBUG_MANU_CTRL_EN, 0); -+ -+ return qca83xx_config_init(phydev); -+} -+ -+static void qca83xx_link_change_notify(struct phy_device *phydev) -+{ -+ /* Set DAC Amplitude adjustment to +6% for 100m on link running */ -+ if (phydev->state == PHY_RUNNING) { -+ if (phydev->speed == SPEED_100) -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, -+ QCA8327_DEBUG_MANU_CTRL_EN, -+ QCA8327_DEBUG_MANU_CTRL_EN); -+ } else { -+ /* Reset DAC Amplitude adjustment */ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, -+ QCA8327_DEBUG_MANU_CTRL_EN, 0); -+ } -+} -+ -+static int qca83xx_resume(struct phy_device *phydev) -+{ -+ int ret, val; -+ -+ /* Skip reset if not suspended */ -+ if (!phydev->suspended) -+ return 0; -+ -+ /* Reinit the port, reset values set by suspend */ -+ qca83xx_config_init(phydev); -+ -+ /* Reset the port on port resume */ -+ phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); -+ -+ /* On resume from suspend the switch execute a reset and -+ * restart auto-negotiation. Wait for reset to complete. -+ */ -+ ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), -+ 50000, 600000, true); -+ if (ret) -+ return ret; -+ -+ usleep_range(1000, 2000); -+ -+ return 0; -+} -+ -+static int qca83xx_suspend(struct phy_device *phydev) -+{ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, -+ AT803X_DEBUG_GATE_CLK_IN1000, 0); -+ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, -+ AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | -+ AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); -+ -+ return 0; -+} -+ -+static int qca8337_suspend(struct phy_device *phydev) -+{ -+ /* Only QCA8337 support actual suspend. */ -+ genphy_suspend(phydev); -+ -+ return qca83xx_suspend(phydev); -+} -+ -+static int qca8327_suspend(struct phy_device *phydev) -+{ -+ u16 mask = 0; -+ -+ /* QCA8327 cause port unreliability when phy suspend -+ * is set. -+ */ -+ mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); -+ phy_modify(phydev, MII_BMCR, mask, 0); -+ -+ return qca83xx_suspend(phydev); -+} -+ -+static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* Enable fast retrain */ -+ ret = genphy_c45_fast_retrain(phydev, true); -+ if (ret) -+ return ret; -+ -+ phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, -+ QCA808X_TOP_OPTION1_DATA); -+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, -+ QCA808X_MSE_THRESHOLD_20DB_VALUE); -+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, -+ QCA808X_MSE_THRESHOLD_17DB_VALUE); -+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, -+ QCA808X_MSE_THRESHOLD_27DB_VALUE); -+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, -+ QCA808X_MSE_THRESHOLD_28DB_VALUE); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, -+ QCA808X_MMD3_DEBUG_1_VALUE); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, -+ QCA808X_MMD3_DEBUG_4_VALUE); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, -+ QCA808X_MMD3_DEBUG_5_VALUE); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, -+ QCA808X_MMD3_DEBUG_3_VALUE); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, -+ QCA808X_MMD3_DEBUG_6_VALUE); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, -+ QCA808X_MMD3_DEBUG_2_VALUE); -+ -+ return 0; -+} -+ -+static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) -+{ -+ u16 seed_value; -+ -+ if (!enable) -+ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, -+ QCA808X_MASTER_SLAVE_SEED_ENABLE, 0); -+ -+ seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE); -+ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, -+ QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE, -+ FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) | -+ QCA808X_MASTER_SLAVE_SEED_ENABLE); -+} -+ -+static bool qca808x_is_prefer_master(struct phy_device *phydev) -+{ -+ return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) || -+ (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED); -+} -+ -+static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) -+{ -+ return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); -+} -+ -+static int qca808x_config_init(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* Active adc&vga on 802.3az for the link 1000M and 100M */ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, -+ QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); -+ if (ret) -+ return ret; -+ -+ /* Adjust the threshold on 802.3az for the link 1000M */ -+ ret = phy_write_mmd(phydev, MDIO_MMD_PCS, -+ QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, -+ QCA808X_MMD3_AZ_TRAINING_VAL); -+ if (ret) -+ return ret; -+ -+ if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { -+ /* Config the fast retrain for the link 2500M */ -+ ret = qca808x_phy_fast_retrain_config(phydev); -+ if (ret) -+ return ret; -+ -+ ret = genphy_read_master_slave(phydev); -+ if (ret < 0) -+ return ret; -+ -+ if (!qca808x_is_prefer_master(phydev)) { -+ /* Enable seed and configure lower ramdom seed to make phy -+ * linked as slave mode. -+ */ -+ ret = qca808x_phy_ms_seed_enable(phydev, true); -+ if (ret) -+ return ret; -+ } -+ } -+ -+ /* Configure adc threshold as 100mv for the link 10M */ -+ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, -+ QCA808X_ADC_THRESHOLD_MASK, -+ QCA808X_ADC_THRESHOLD_100MV); -+} -+ -+static int qca808x_read_status(struct phy_device *phydev) -+{ -+ struct at803x_ss_mask ss_mask = { 0 }; -+ int ret; -+ -+ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); -+ if (ret < 0) -+ return ret; -+ -+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, -+ ret & MDIO_AN_10GBT_STAT_LP2_5G); -+ -+ ret = genphy_read_status(phydev); -+ if (ret) -+ return ret; -+ -+ /* qca8081 takes the different bits for speed value from at803x */ -+ ss_mask.speed_mask = QCA808X_SS_SPEED_MASK; -+ ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK); -+ ret = at803x_read_specific_status(phydev, ss_mask); -+ if (ret < 0) -+ return ret; -+ -+ if (phydev->link) { -+ if (phydev->speed == SPEED_2500) -+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -+ else -+ phydev->interface = PHY_INTERFACE_MODE_SGMII; -+ } else { -+ /* generate seed as a lower random value to make PHY linked as SLAVE easily, -+ * except for master/slave configuration fault detected or the master mode -+ * preferred. -+ * -+ * the reason for not putting this code into the function link_change_notify is -+ * the corner case where the link partner is also the qca8081 PHY and the seed -+ * value is configured as the same value, the link can't be up and no link change -+ * occurs. -+ */ -+ if (qca808x_has_fast_retrain_or_slave_seed(phydev)) { -+ if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR || -+ qca808x_is_prefer_master(phydev)) { -+ qca808x_phy_ms_seed_enable(phydev, false); -+ } else { -+ qca808x_phy_ms_seed_enable(phydev, true); -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+static int qca808x_soft_reset(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ret = genphy_soft_reset(phydev); -+ if (ret < 0) -+ return ret; -+ -+ if (qca808x_has_fast_retrain_or_slave_seed(phydev)) -+ ret = qca808x_phy_ms_seed_enable(phydev, true); -+ -+ return ret; -+} -+ -+static bool qca808x_cdt_fault_length_valid(int cdt_code) -+{ -+ switch (cdt_code) { -+ case QCA808X_CDT_STATUS_STAT_SAME_SHORT: -+ case QCA808X_CDT_STATUS_STAT_SAME_OPEN: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+static int qca808x_cable_test_result_trans(int cdt_code) -+{ -+ switch (cdt_code) { -+ case QCA808X_CDT_STATUS_STAT_NORMAL: -+ return ETHTOOL_A_CABLE_RESULT_CODE_OK; -+ case QCA808X_CDT_STATUS_STAT_SAME_SHORT: -+ return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; -+ case QCA808X_CDT_STATUS_STAT_SAME_OPEN: -+ return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN: -+ case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT: -+ return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; -+ case QCA808X_CDT_STATUS_STAT_FAIL: -+ default: -+ return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; -+ } -+} -+ -+static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair, -+ int result) -+{ -+ int val; -+ u32 cdt_length_reg = 0; -+ -+ switch (pair) { -+ case ETHTOOL_A_CABLE_PAIR_A: -+ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; -+ break; -+ case ETHTOOL_A_CABLE_PAIR_B: -+ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; -+ break; -+ case ETHTOOL_A_CABLE_PAIR_C: -+ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; -+ break; -+ case ETHTOOL_A_CABLE_PAIR_D: -+ cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); -+ if (val < 0) -+ return val; -+ -+ if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT) -+ val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val); -+ else -+ val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val); -+ -+ return at803x_cdt_fault_length(val); -+} -+ -+static int qca808x_cable_test_start(struct phy_device *phydev) -+{ -+ int ret; -+ -+ /* perform CDT with the following configs: -+ * 1. disable hibernation. -+ * 2. force PHY working in MDI mode. -+ * 3. for PHY working in 1000BaseT. -+ * 4. configure the threshold. -+ */ -+ -+ ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); -+ if (ret < 0) -+ return ret; -+ -+ ret = at803x_config_mdix(phydev, ETH_TP_MDI); -+ if (ret < 0) -+ return ret; -+ -+ /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ -+ phydev->duplex = DUPLEX_FULL; -+ phydev->speed = SPEED_1000; -+ ret = genphy_c45_pma_setup_forced(phydev); -+ if (ret < 0) -+ return ret; -+ -+ ret = genphy_setup_forced(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* configure the thresholds for open, short, pair ok test */ -+ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); -+ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); -+ -+ return 0; -+} -+ -+static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair, -+ u16 status) -+{ -+ int length, result; -+ u16 pair_code; -+ -+ switch (pair) { -+ case ETHTOOL_A_CABLE_PAIR_A: -+ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status); -+ break; -+ case ETHTOOL_A_CABLE_PAIR_B: -+ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status); -+ break; -+ case ETHTOOL_A_CABLE_PAIR_C: -+ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status); -+ break; -+ case ETHTOOL_A_CABLE_PAIR_D: -+ pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ result = qca808x_cable_test_result_trans(pair_code); -+ ethnl_cable_test_result(phydev, pair, result); -+ -+ if (qca808x_cdt_fault_length_valid(pair_code)) { -+ length = qca808x_cdt_fault_length(phydev, pair, result); -+ ethnl_cable_test_fault_length(phydev, pair, length); -+ } -+ -+ return 0; -+} -+ -+static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) -+{ -+ int ret, val; -+ -+ *finished = false; -+ -+ val = QCA808X_CDT_ENABLE_TEST | -+ QCA808X_CDT_LENGTH_UNIT; -+ ret = at803x_cdt_start(phydev, val); -+ if (ret) -+ return ret; -+ -+ ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST); -+ if (ret) -+ return ret; -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); -+ if (val < 0) -+ return val; -+ -+ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val); -+ if (ret) -+ return ret; -+ -+ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val); -+ if (ret) -+ return ret; -+ -+ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val); -+ if (ret) -+ return ret; -+ -+ ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val); -+ if (ret) -+ return ret; -+ -+ *finished = true; -+ -+ return 0; -+} -+ -+static int qca808x_get_features(struct phy_device *phydev) -+{ -+ int ret; -+ -+ ret = genphy_c45_pma_read_abilities(phydev); -+ if (ret) -+ return ret; -+ -+ /* The autoneg ability is not existed in bit3 of MMD7.1, -+ * but it is supported by qca808x PHY, so we add it here -+ * manually. -+ */ -+ linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); -+ -+ /* As for the qca8081 1G version chip, the 2500baseT ability is also -+ * existed in the bit0 of MMD1.21, we need to remove it manually if -+ * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d. -+ */ -+ ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); -+ if (ret < 0) -+ return ret; -+ -+ if (QCA808X_PHY_CHIP_TYPE_1G & ret) -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); -+ -+ return 0; -+} -+ -+static int qca808x_config_aneg(struct phy_device *phydev) -+{ -+ int phy_ctrl = 0; -+ int ret; -+ -+ ret = at803x_prepare_config_aneg(phydev); -+ if (ret) -+ return ret; -+ -+ /* The reg MII_BMCR also needs to be configured for force mode, the -+ * genphy_config_aneg is also needed. -+ */ -+ if (phydev->autoneg == AUTONEG_DISABLE) -+ genphy_c45_pma_setup_forced(phydev); -+ -+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) -+ phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; -+ -+ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, -+ MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); -+ if (ret < 0) -+ return ret; -+ -+ return __genphy_config_aneg(phydev, ret); -+} -+ -+static void qca808x_link_change_notify(struct phy_device *phydev) -+{ -+ /* Assert interface sgmii fifo on link down, deassert it on link up, -+ * the interface device address is always phy address added by 1. -+ */ -+ mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1, -+ MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL, -+ QCA8081_PHY_FIFO_RSTN, -+ phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); -+} -+ -+static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, -+ u16 *offload_trigger) -+{ -+ /* Parsing specific to netdev trigger */ -+ if (test_bit(TRIGGER_NETDEV_TX, &rules)) -+ *offload_trigger |= QCA808X_LED_TX_BLINK; -+ if (test_bit(TRIGGER_NETDEV_RX, &rules)) -+ *offload_trigger |= QCA808X_LED_RX_BLINK; -+ if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) -+ *offload_trigger |= QCA808X_LED_SPEED10_ON; -+ if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) -+ *offload_trigger |= QCA808X_LED_SPEED100_ON; -+ if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) -+ *offload_trigger |= QCA808X_LED_SPEED1000_ON; -+ if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules)) -+ *offload_trigger |= QCA808X_LED_SPEED2500_ON; -+ if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) -+ *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON; -+ if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) -+ *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON; -+ -+ if (rules && !*offload_trigger) -+ return -EOPNOTSUPP; -+ -+ /* Enable BLINK_CHECK_BYPASS by default to make the LED -+ * blink even with duplex or speed mode not enabled. -+ */ -+ *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS; -+ -+ return 0; -+} -+ -+static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index) -+{ -+ u16 reg; -+ -+ if (index > 2) -+ return -EINVAL; -+ -+ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); -+ -+ return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, -+ QCA808X_LED_FORCE_EN); -+} -+ -+static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index, -+ unsigned long rules) -+{ -+ u16 offload_trigger = 0; -+ -+ if (index > 2) -+ return -EINVAL; -+ -+ return qca808x_led_parse_netdev(phydev, rules, &offload_trigger); -+} -+ -+static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index, -+ unsigned long rules) -+{ -+ u16 reg, offload_trigger = 0; -+ int ret; -+ -+ if (index > 2) -+ return -EINVAL; -+ -+ reg = QCA808X_MMD7_LED_CTRL(index); -+ -+ ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger); -+ if (ret) -+ return ret; -+ -+ ret = qca808x_led_hw_control_enable(phydev, index); -+ if (ret) -+ return ret; -+ -+ return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, -+ QCA808X_LED_PATTERN_MASK, -+ offload_trigger); -+} -+ -+static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index) -+{ -+ u16 reg; -+ int val; -+ -+ if (index > 2) -+ return false; -+ -+ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); -+ -+ return !(val & QCA808X_LED_FORCE_EN); -+} -+ -+static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index, -+ unsigned long *rules) -+{ -+ u16 reg; -+ int val; -+ -+ if (index > 2) -+ return -EINVAL; -+ -+ /* Check if we have hw control enabled */ -+ if (qca808x_led_hw_control_status(phydev, index)) -+ return -EINVAL; -+ -+ reg = QCA808X_MMD7_LED_CTRL(index); -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); -+ if (val & QCA808X_LED_TX_BLINK) -+ set_bit(TRIGGER_NETDEV_TX, rules); -+ if (val & QCA808X_LED_RX_BLINK) -+ set_bit(TRIGGER_NETDEV_RX, rules); -+ if (val & QCA808X_LED_SPEED10_ON) -+ set_bit(TRIGGER_NETDEV_LINK_10, rules); -+ if (val & QCA808X_LED_SPEED100_ON) -+ set_bit(TRIGGER_NETDEV_LINK_100, rules); -+ if (val & QCA808X_LED_SPEED1000_ON) -+ set_bit(TRIGGER_NETDEV_LINK_1000, rules); -+ if (val & QCA808X_LED_SPEED2500_ON) -+ set_bit(TRIGGER_NETDEV_LINK_2500, rules); -+ if (val & QCA808X_LED_HALF_DUPLEX_ON) -+ set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); -+ if (val & QCA808X_LED_FULL_DUPLEX_ON) -+ set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); -+ -+ return 0; -+} -+ -+static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index) -+{ -+ u16 reg; -+ -+ if (index > 2) -+ return -EINVAL; -+ -+ reg = QCA808X_MMD7_LED_CTRL(index); -+ -+ return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, -+ QCA808X_LED_PATTERN_MASK); -+} -+ -+static int qca808x_led_brightness_set(struct phy_device *phydev, -+ u8 index, enum led_brightness value) -+{ -+ u16 reg; -+ int ret; -+ -+ if (index > 2) -+ return -EINVAL; -+ -+ if (!value) { -+ ret = qca808x_led_hw_control_reset(phydev, index); -+ if (ret) -+ return ret; -+ } -+ -+ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); -+ -+ return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, -+ QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, -+ QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON : -+ QCA808X_LED_FORCE_OFF); -+} -+ -+static int qca808x_led_blink_set(struct phy_device *phydev, u8 index, -+ unsigned long *delay_on, -+ unsigned long *delay_off) -+{ -+ int ret; -+ u16 reg; -+ -+ if (index > 2) -+ return -EINVAL; -+ -+ reg = QCA808X_MMD7_LED_FORCE_CTRL(index); -+ -+ /* Set blink to 50% off, 50% on at 4Hz by default */ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL, -+ QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK, -+ QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50); -+ if (ret) -+ return ret; -+ -+ /* We use BLINK_1 for normal blinking */ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, -+ QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK, -+ QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1); -+ if (ret) -+ return ret; -+ -+ /* We set blink to 4Hz, aka 250ms */ -+ *delay_on = 250 / 2; -+ *delay_off = 250 / 2; -+ -+ return 0; -+} -+ -+static int qca808x_led_polarity_set(struct phy_device *phydev, int index, -+ unsigned long modes) -+{ -+ struct at803x_priv *priv = phydev->priv; -+ bool active_low = false; -+ u32 mode; -+ -+ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { -+ switch (mode) { -+ case PHY_LED_ACTIVE_LOW: -+ active_low = true; -+ break; -+ default: -+ return -EINVAL; -+ } -+ } -+ -+ /* PHY polarity is global and can't be set per LED. -+ * To detect this, check if last requested polarity mode -+ * match the new one. -+ */ -+ if (priv->led_polarity_mode >= 0 && -+ priv->led_polarity_mode != active_low) { -+ phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); -+ return -EINVAL; -+ } -+ -+ /* Save the last PHY polarity mode */ -+ priv->led_polarity_mode = active_low; -+ -+ return phy_modify_mmd(phydev, MDIO_MMD_AN, -+ QCA808X_MMD7_LED_POLARITY_CTRL, -+ QCA808X_LED_ACTIVE_HIGH, -+ active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); -+} -+ -+static struct phy_driver at803x_driver[] = { -+{ -+ /* Qualcomm Atheros AR8035 */ -+ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), -+ .name = "Qualcomm Atheros AR8035", -+ .flags = PHY_POLL_CABLE_TEST, -+ .probe = at8035_probe, -+ .config_aneg = at803x_config_aneg, -+ .config_init = at803x_config_init, -+ .soft_reset = genphy_soft_reset, -+ .set_wol = at803x_set_wol, -+ .get_wol = at803x_get_wol, -+ .suspend = at803x_suspend, -+ .resume = at803x_resume, -+ /* PHY_GBIT_FEATURES */ -+ .read_status = at803x_read_status, -+ .config_intr = at803x_config_intr, -+ .handle_interrupt = at803x_handle_interrupt, -+ .get_tunable = at803x_get_tunable, -+ .set_tunable = at803x_set_tunable, -+ .cable_test_start = at8031_cable_test_start, -+ .cable_test_get_status = at8031_cable_test_get_status, -+}, { -+ /* Qualcomm Atheros AR8030 */ -+ .phy_id = ATH8030_PHY_ID, -+ .name = "Qualcomm Atheros AR8030", -+ .phy_id_mask = AT8030_PHY_ID_MASK, -+ .probe = at8035_probe, -+ .config_init = at803x_config_init, -+ .link_change_notify = at803x_link_change_notify, -+ .set_wol = at803x_set_wol, -+ .get_wol = at803x_get_wol, -+ .suspend = at803x_suspend, -+ .resume = at803x_resume, -+ /* PHY_BASIC_FEATURES */ -+ .config_intr = at803x_config_intr, -+ .handle_interrupt = at803x_handle_interrupt, -+}, { -+ /* Qualcomm Atheros AR8031/AR8033 */ -+ PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), -+ .name = "Qualcomm Atheros AR8031/AR8033", -+ .flags = PHY_POLL_CABLE_TEST, -+ .probe = at8031_probe, -+ .config_init = at8031_config_init, -+ .config_aneg = at803x_config_aneg, -+ .soft_reset = genphy_soft_reset, -+ .set_wol = at8031_set_wol, -+ .get_wol = at803x_get_wol, -+ .suspend = at803x_suspend, -+ .resume = at803x_resume, -+ .read_page = at803x_read_page, -+ .write_page = at803x_write_page, -+ .get_features = at803x_get_features, -+ .read_status = at8031_read_status, -+ .config_intr = at8031_config_intr, -+ .handle_interrupt = at803x_handle_interrupt, -+ .get_tunable = at803x_get_tunable, -+ .set_tunable = at803x_set_tunable, -+ .cable_test_start = at8031_cable_test_start, -+ .cable_test_get_status = at8031_cable_test_get_status, -+}, { -+ /* Qualcomm Atheros AR8032 */ -+ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), -+ .name = "Qualcomm Atheros AR8032", -+ .probe = at803x_probe, -+ .flags = PHY_POLL_CABLE_TEST, -+ .config_init = at803x_config_init, -+ .link_change_notify = at803x_link_change_notify, -+ .suspend = at803x_suspend, -+ .resume = at803x_resume, -+ /* PHY_BASIC_FEATURES */ -+ .config_intr = at803x_config_intr, -+ .handle_interrupt = at803x_handle_interrupt, -+ .cable_test_start = at803x_cable_test_start, -+ .cable_test_get_status = at8032_cable_test_get_status, -+}, { -+ /* ATHEROS AR9331 */ -+ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), -+ .name = "Qualcomm Atheros AR9331 built-in PHY", -+ .probe = at803x_probe, -+ .suspend = at803x_suspend, -+ .resume = at803x_resume, -+ .flags = PHY_POLL_CABLE_TEST, -+ /* PHY_BASIC_FEATURES */ -+ .config_intr = at803x_config_intr, -+ .handle_interrupt = at803x_handle_interrupt, -+ .cable_test_start = at803x_cable_test_start, -+ .cable_test_get_status = at8032_cable_test_get_status, -+ .read_status = at803x_read_status, -+ .soft_reset = genphy_soft_reset, -+ .config_aneg = at803x_config_aneg, -+}, { -+ /* Qualcomm Atheros QCA9561 */ -+ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), -+ .name = "Qualcomm Atheros QCA9561 built-in PHY", -+ .probe = at803x_probe, -+ .suspend = at803x_suspend, -+ .resume = at803x_resume, -+ .flags = PHY_POLL_CABLE_TEST, -+ /* PHY_BASIC_FEATURES */ -+ .config_intr = at803x_config_intr, -+ .handle_interrupt = at803x_handle_interrupt, -+ .cable_test_start = at803x_cable_test_start, -+ .cable_test_get_status = at8032_cable_test_get_status, -+ .read_status = at803x_read_status, -+ .soft_reset = genphy_soft_reset, -+ .config_aneg = at803x_config_aneg, -+}, { -+ /* QCA8337 */ -+ .phy_id = QCA8337_PHY_ID, -+ .phy_id_mask = QCA8K_PHY_ID_MASK, -+ .name = "Qualcomm Atheros 8337 internal PHY", -+ /* PHY_GBIT_FEATURES */ -+ .probe = at803x_probe, -+ .flags = PHY_IS_INTERNAL, -+ .config_init = qca83xx_config_init, -+ .soft_reset = genphy_soft_reset, -+ .get_sset_count = qca83xx_get_sset_count, -+ .get_strings = qca83xx_get_strings, -+ .get_stats = qca83xx_get_stats, -+ .suspend = qca8337_suspend, -+ .resume = qca83xx_resume, -+}, { -+ /* QCA8327-A from switch QCA8327-AL1A */ -+ .phy_id = QCA8327_A_PHY_ID, -+ .phy_id_mask = QCA8K_PHY_ID_MASK, -+ .name = "Qualcomm Atheros 8327-A internal PHY", -+ /* PHY_GBIT_FEATURES */ -+ .link_change_notify = qca83xx_link_change_notify, -+ .probe = at803x_probe, -+ .flags = PHY_IS_INTERNAL, -+ .config_init = qca8327_config_init, -+ .soft_reset = genphy_soft_reset, -+ .get_sset_count = qca83xx_get_sset_count, -+ .get_strings = qca83xx_get_strings, -+ .get_stats = qca83xx_get_stats, -+ .suspend = qca8327_suspend, -+ .resume = qca83xx_resume, -+}, { -+ /* QCA8327-B from switch QCA8327-BL1A */ -+ .phy_id = QCA8327_B_PHY_ID, -+ .phy_id_mask = QCA8K_PHY_ID_MASK, -+ .name = "Qualcomm Atheros 8327-B internal PHY", -+ /* PHY_GBIT_FEATURES */ -+ .link_change_notify = qca83xx_link_change_notify, -+ .probe = at803x_probe, -+ .flags = PHY_IS_INTERNAL, -+ .config_init = qca8327_config_init, -+ .soft_reset = genphy_soft_reset, -+ .get_sset_count = qca83xx_get_sset_count, -+ .get_strings = qca83xx_get_strings, -+ .get_stats = qca83xx_get_stats, -+ .suspend = qca8327_suspend, -+ .resume = qca83xx_resume, -+}, { -+ /* Qualcomm QCA8081 */ -+ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), -+ .name = "Qualcomm QCA8081", -+ .flags = PHY_POLL_CABLE_TEST, -+ .probe = at803x_probe, -+ .config_intr = at803x_config_intr, -+ .handle_interrupt = at803x_handle_interrupt, -+ .get_tunable = at803x_get_tunable, -+ .set_tunable = at803x_set_tunable, -+ .set_wol = at803x_set_wol, -+ .get_wol = at803x_get_wol, -+ .get_features = qca808x_get_features, -+ .config_aneg = qca808x_config_aneg, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_status = qca808x_read_status, -+ .config_init = qca808x_config_init, -+ .soft_reset = qca808x_soft_reset, -+ .cable_test_start = qca808x_cable_test_start, -+ .cable_test_get_status = qca808x_cable_test_get_status, -+ .link_change_notify = qca808x_link_change_notify, -+ .led_brightness_set = qca808x_led_brightness_set, -+ .led_blink_set = qca808x_led_blink_set, -+ .led_hw_is_supported = qca808x_led_hw_is_supported, -+ .led_hw_control_set = qca808x_led_hw_control_set, -+ .led_hw_control_get = qca808x_led_hw_control_get, -+ .led_polarity_set = qca808x_led_polarity_set, -+}, }; -+ -+module_phy_driver(at803x_driver); -+ -+static struct mdio_device_id __maybe_unused atheros_tbl[] = { -+ { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, -+ { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(mdio, atheros_tbl); diff --git a/target/linux/generic/backport-6.6/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch b/target/linux/generic/backport-6.6/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch index 9c43ad13b4..47fed63996 100644 --- a/target/linux/generic/backport-6.6/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch +++ b/target/linux/generic/backport-6.6/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch @@ -193,7 +193,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org> { int value; @@ -816,73 +679,6 @@ static int at803x_config_init(struct phy - return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); + return phy_modify(phydev, MII_ADVERTISE, ADVERTISE_XNP, 0); } -static int at803x_ack_interrupt(struct phy_device *phydev) diff --git a/target/linux/generic/backport-6.6/781-24-v6.14-net-phy-move-realtek-PHY-driver-to-its-own-subdirect.patch b/target/linux/generic/backport-6.6/781-24-v6.14-net-phy-move-realtek-PHY-driver-to-its-own-subdirect.patch index e66d724a98..cde8af8df3 100644 --- a/target/linux/generic/backport-6.6/781-24-v6.14-net-phy-move-realtek-PHY-driver-to-its-own-subdirect.patch +++ b/target/linux/generic/backport-6.6/781-24-v6.14-net-phy-move-realtek-PHY-driver-to-its-own-subdirect.patch @@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org> --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -325,10 +325,7 @@ config QSEMI_PHY +@@ -333,10 +333,7 @@ config QSEMI_PHY help Currently supports the qs6612 @@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org> tristate "Renesas PHYs" --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -83,7 +83,7 @@ obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o +@@ -87,7 +87,7 @@ obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o obj-y += qcom/ obj-$(CONFIG_QSEMI_PHY) += qsemi.o diff --git a/target/linux/generic/backport-6.6/798-v6.10-01-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch b/target/linux/generic/backport-6.6/798-v6.10-01-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch index 5b627cf449..b22c3e2c24 100644 --- a/target/linux/generic/backport-6.6/798-v6.10-01-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch +++ b/target/linux/generic/backport-6.6/798-v6.10-01-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch @@ -48,7 +48,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org> +obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o obj-$(CONFIG_AMD_PHY) += amd.o obj-$(CONFIG_AQUANTIA_PHY) += aquantia/ - obj-$(CONFIG_AX88796B_PHY) += ax88796b.o + ifdef CONFIG_AX88796B_RUST_PHY --- /dev/null +++ b/drivers/net/phy/air_en8811h.c @@ -0,0 +1,1086 @@ diff --git a/target/linux/generic/backport-6.6/823-v6.12-0003-nvmem-layouts-add-U-Boot-env-layout.patch b/target/linux/generic/backport-6.6/823-v6.12-0003-nvmem-layouts-add-U-Boot-env-layout.patch index e087b51c20..73e47ffe6a 100644 --- a/target/linux/generic/backport-6.6/823-v6.12-0003-nvmem-layouts-add-U-Boot-env-layout.patch +++ b/target/linux/generic/backport-6.6/823-v6.12-0003-nvmem-layouts-add-U-Boot-env-layout.patch @@ -41,7 +41,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -21984,6 +21984,7 @@ U-BOOT ENVIRONMENT VARIABLES +@@ -21992,6 +21992,7 @@ U-BOOT ENVIRONMENT VARIABLES M: Rafał Miłecki <rafal@milecki.pl> S: Maintained F: Documentation/devicetree/bindings/nvmem/u-boot,env.yaml diff --git a/target/linux/generic/backport-6.6/870-v6.7-01-PCI-dwc-Add-host_post_init-callback.patch b/target/linux/generic/backport-6.6/870-v6.7-01-PCI-dwc-Add-host_post_init-callback.patch index d70c65225e..519722c608 100644 --- a/target/linux/generic/backport-6.6/870-v6.7-01-PCI-dwc-Add-host_post_init-callback.patch +++ b/target/linux/generic/backport-6.6/870-v6.7-01-PCI-dwc-Add-host_post_init-callback.patch @@ -32,7 +32,7 @@ Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> err_stop_link: --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h -@@ -301,6 +301,7 @@ enum dw_pcie_ltssm { +@@ -303,6 +303,7 @@ enum dw_pcie_ltssm { struct dw_pcie_host_ops { int (*host_init)(struct dw_pcie_rp *pp); void (*host_deinit)(struct dw_pcie_rp *pp); diff --git a/target/linux/generic/backport-6.6/906-01-v6.7-crypto-jitter-add-RCTAPT-support-for-different-OSRs.patch b/target/linux/generic/backport-6.6/906-01-v6.7-crypto-jitter-add-RCTAPT-support-for-different-OSRs.patch index a8e729cb28..6d20641618 100644 --- a/target/linux/generic/backport-6.6/906-01-v6.7-crypto-jitter-add-RCTAPT-support-for-different-OSRs.patch +++ b/target/linux/generic/backport-6.6/906-01-v6.7-crypto-jitter-add-RCTAPT-support-for-different-OSRs.patch @@ -43,7 +43,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> --- a/crypto/jitterentropy-kcapi.c +++ b/crypto/jitterentropy-kcapi.c -@@ -246,7 +246,7 @@ static int jent_kcapi_init(struct crypto +@@ -247,7 +247,7 @@ static int jent_kcapi_init(struct crypto crypto_shash_init(sdesc); rng->sdesc = sdesc; diff --git a/target/linux/generic/backport-6.6/906-02-v6.7-crypto-jitter-Allow-configuration-of-memory-size.patch b/target/linux/generic/backport-6.6/906-02-v6.7-crypto-jitter-Allow-configuration-of-memory-size.patch index c857f4fe00..662bfad8a1 100644 --- a/target/linux/generic/backport-6.6/906-02-v6.7-crypto-jitter-Allow-configuration-of-memory-size.patch +++ b/target/linux/generic/backport-6.6/906-02-v6.7-crypto-jitter-Allow-configuration-of-memory-size.patch @@ -85,7 +85,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> depends on CRYPTO_JITTERENTROPY --- a/crypto/jitterentropy-kcapi.c +++ b/crypto/jitterentropy-kcapi.c -@@ -54,6 +54,17 @@ +@@ -55,6 +55,17 @@ * Helper function ***************************************************************************/ diff --git a/target/linux/generic/backport-6.6/906-03-v6.7-crypto-jitter-Allow-configuration-of-oversampling-rate.patch b/target/linux/generic/backport-6.6/906-03-v6.7-crypto-jitter-Allow-configuration-of-oversampling-rate.patch index e2fb47c7c3..70cda169af 100644 --- a/target/linux/generic/backport-6.6/906-03-v6.7-crypto-jitter-Allow-configuration-of-oversampling-rate.patch +++ b/target/linux/generic/backport-6.6/906-03-v6.7-crypto-jitter-Allow-configuration-of-oversampling-rate.patch @@ -53,7 +53,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> depends on CRYPTO_JITTERENTROPY --- a/crypto/jitterentropy-kcapi.c +++ b/crypto/jitterentropy-kcapi.c -@@ -257,7 +257,9 @@ static int jent_kcapi_init(struct crypto +@@ -258,7 +258,9 @@ static int jent_kcapi_init(struct crypto crypto_shash_init(sdesc); rng->sdesc = sdesc; diff --git a/target/linux/generic/backport-6.6/906-07-v6.10-crypto-jitter-Use-kvfree_sensitive-to-fix-Coccinelle.patch b/target/linux/generic/backport-6.6/906-07-v6.10-crypto-jitter-Use-kvfree_sensitive-to-fix-Coccinelle.patch index 88a0bd15c0..3a865e5131 100644 --- a/target/linux/generic/backport-6.6/906-07-v6.10-crypto-jitter-Use-kvfree_sensitive-to-fix-Coccinelle.patch +++ b/target/linux/generic/backport-6.6/906-07-v6.10-crypto-jitter-Use-kvfree_sensitive-to-fix-Coccinelle.patch @@ -18,7 +18,7 @@ Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> --- a/crypto/jitterentropy-kcapi.c +++ b/crypto/jitterentropy-kcapi.c -@@ -61,8 +61,7 @@ void *jent_kvzalloc(unsigned int len) +@@ -62,8 +62,7 @@ void *jent_kvzalloc(unsigned int len) void jent_kvzfree(void *ptr, unsigned int len) { diff --git a/target/linux/generic/pending-6.6/479-mtd-spi-nor-add-xtx-xt25f128b.patch b/target/linux/generic/pending-6.6/479-mtd-spi-nor-add-xtx-xt25f128b.patch index 945f5baf10..6bf0d5995a 100644 --- a/target/linux/generic/pending-6.6/479-mtd-spi-nor-add-xtx-xt25f128b.patch +++ b/target/linux/generic/pending-6.6/479-mtd-spi-nor-add-xtx-xt25f128b.patch @@ -71,7 +71,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name> static const struct flash_info spi_nor_generic_flash = { --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h -@@ -647,6 +647,7 @@ extern const struct spi_nor_manufacturer +@@ -653,6 +653,7 @@ extern const struct spi_nor_manufacturer extern const struct spi_nor_manufacturer spi_nor_winbond; extern const struct spi_nor_manufacturer spi_nor_xilinx; extern const struct spi_nor_manufacturer spi_nor_xmc; diff --git a/target/linux/generic/pending-6.6/510-block-add-uImage.FIT-subimage-block-driver.patch b/target/linux/generic/pending-6.6/510-block-add-uImage.FIT-subimage-block-driver.patch index 1d91f8372a..a87466b6a7 100644 --- a/target/linux/generic/pending-6.6/510-block-add-uImage.FIT-subimage-block-driver.patch +++ b/target/linux/generic/pending-6.6/510-block-add-uImage.FIT-subimage-block-driver.patch @@ -36,7 +36,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -22011,6 +22011,12 @@ F: Documentation/filesystems/ubifs-authe +@@ -22019,6 +22019,12 @@ F: Documentation/filesystems/ubifs-authe F: Documentation/filesystems/ubifs.rst F: fs/ubifs/ diff --git a/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch b/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch index 217492f92c..3e914298e8 100644 --- a/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch +++ b/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch @@ -45,7 +45,7 @@ Signe-off-by: Felix Fietkau <nbd@nbd.name> INDIRECT_CALLABLE_DECLARE(int tcp6_gro_complete(struct sk_buff *skb, int thoff)); --- a/net/core/gro.c +++ b/net/core/gro.c -@@ -225,6 +225,33 @@ done: +@@ -227,6 +227,35 @@ done: return 0; } @@ -71,6 +71,8 @@ Signe-off-by: Felix Fietkau <nbd@nbd.name> + p->truesize += skb->truesize; + p->len += skb->len; + ++ skb_shinfo(p)->flags |= skb_shinfo(skb)->flags & SKBFL_SHARED_FRAG; ++ + NAPI_GRO_CB(skb)->same_flow = 1; + + return 0; @@ -298,7 +300,7 @@ Signe-off-by: Felix Fietkau <nbd@nbd.name> skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4; --- a/net/ipv4/udp_offload.c +++ b/net/ipv4/udp_offload.c -@@ -539,33 +539,6 @@ out: +@@ -539,35 +539,6 @@ out: return segs; } @@ -324,6 +326,8 @@ Signe-off-by: Felix Fietkau <nbd@nbd.name> - p->truesize += skb->truesize; - p->len += skb->len; - +- skb_shinfo(p)->flags |= skb_shinfo(skb)->flags & SKBFL_SHARED_FRAG; +- - NAPI_GRO_CB(skb)->same_flow = 1; - - return 0; diff --git a/target/linux/generic/pending-6.6/681-net-remove-NETIF_F_GSO_FRAGLIST-from-NETIF_F_GSO_SOF.patch b/target/linux/generic/pending-6.6/681-net-remove-NETIF_F_GSO_FRAGLIST-from-NETIF_F_GSO_SOF.patch index 3e51a06f23..a31f273dc9 100644 --- a/target/linux/generic/pending-6.6/681-net-remove-NETIF_F_GSO_FRAGLIST-from-NETIF_F_GSO_SOF.patch +++ b/target/linux/generic/pending-6.6/681-net-remove-NETIF_F_GSO_FRAGLIST-from-NETIF_F_GSO_SOF.patch @@ -35,7 +35,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name> | NETIF_F_HW_CSUM --- a/drivers/net/macvlan.c +++ b/drivers/net/macvlan.c -@@ -902,7 +902,7 @@ static int macvlan_hwtstamp_set(struct n +@@ -903,7 +903,7 @@ static int macvlan_hwtstamp_set(struct n static struct lock_class_key macvlan_netdev_addr_lock_key; #define ALWAYS_ON_OFFLOADS \ diff --git a/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch index 642afec742..dc42775276 100644 --- a/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch +++ b/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch @@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name> --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c -@@ -8528,7 +8528,7 @@ static int nft_register_flowtable_net_ho +@@ -8530,7 +8530,7 @@ static int nft_register_flowtable_net_ho err = flowtable->data.type->setup(&flowtable->data, hook->ops.dev, FLOW_BLOCK_BIND); diff --git a/target/linux/generic/pending-6.6/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch b/target/linux/generic/pending-6.6/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch index 70bd736127..45c3f88d51 100644 --- a/target/linux/generic/pending-6.6/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch +++ b/target/linux/generic/pending-6.6/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch @@ -19,7 +19,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -13357,7 +13357,9 @@ M: Daniel Golle <daniel@makrotopia.org> +@@ -13365,7 +13365,9 @@ M: Daniel Golle <daniel@makrotopia.org> L: netdev@vger.kernel.org S: Maintained F: drivers/net/pcs/pcs-mtk-lynxi.c diff --git a/target/linux/generic/pending-6.6/741-net-phy-broadcom-update-dependency-condition.patch b/target/linux/generic/pending-6.6/741-net-phy-broadcom-update-dependency-condition.patch index 80b69920e9..a3b0cc7609 100644 --- a/target/linux/generic/pending-6.6/741-net-phy-broadcom-update-dependency-condition.patch +++ b/target/linux/generic/pending-6.6/741-net-phy-broadcom-update-dependency-condition.patch @@ -24,7 +24,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net> --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -113,7 +113,7 @@ config BROADCOM_PHY +@@ -121,7 +121,7 @@ config BROADCOM_PHY tristate "Broadcom 54XX PHYs" select BCM_NET_PHYLIB select BCM_NET_PHYPTP if NETWORK_PHY_TIMESTAMPING diff --git a/target/linux/ipq40xx/patches-6.6/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch b/target/linux/ipq40xx/patches-6.6/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch index 39e1bceefc..616858d063 100644 --- a/target/linux/ipq40xx/patches-6.6/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch +++ b/target/linux/ipq40xx/patches-6.6/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch @@ -32,7 +32,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -17718,6 +17718,13 @@ L: netdev@vger.kernel.org +@@ -17726,6 +17726,13 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/qualcomm/emac/ diff --git a/target/linux/ipq40xx/patches-6.6/701-net-dsa-add-out-of-band-tagging-protocol.patch b/target/linux/ipq40xx/patches-6.6/701-net-dsa-add-out-of-band-tagging-protocol.patch index 01c2aa0de2..a776f296af 100644 --- a/target/linux/ipq40xx/patches-6.6/701-net-dsa-add-out-of-band-tagging-protocol.patch +++ b/target/linux/ipq40xx/patches-6.6/701-net-dsa-add-out-of-band-tagging-protocol.patch @@ -64,7 +64,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -17724,6 +17724,7 @@ L: netdev@vger.kernel.org +@@ -17732,6 +17732,7 @@ L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml F: drivers/net/ethernet/qualcomm/ipqess/ @@ -136,7 +136,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> #include <net/dst.h> #include <net/sock.h> #include <net/checksum.h> -@@ -4826,6 +4830,9 @@ static const u8 skb_ext_type_len[] = { +@@ -4833,6 +4837,9 @@ static const u8 skb_ext_type_len[] = { #if IS_ENABLED(CONFIG_MCTP_FLOWS) [SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow), #endif diff --git a/target/linux/ipq40xx/patches-6.6/999-atm-mpoa-intel-dsl-phy-support.patch b/target/linux/ipq40xx/patches-6.6/999-atm-mpoa-intel-dsl-phy-support.patch index b05e49d974..2aab05e2f4 100644 --- a/target/linux/ipq40xx/patches-6.6/999-atm-mpoa-intel-dsl-phy-support.patch +++ b/target/linux/ipq40xx/patches-6.6/999-atm-mpoa-intel-dsl-phy-support.patch @@ -4,7 +4,7 @@ Subject: [PATCH] UGW_SW-29163: ATM oam support --- a/drivers/net/ppp/ppp_generic.c +++ b/drivers/net/ppp/ppp_generic.c -@@ -2982,6 +2982,22 @@ char *ppp_dev_name(struct ppp_channel *c +@@ -2985,6 +2985,22 @@ char *ppp_dev_name(struct ppp_channel *c return name; } @@ -27,7 +27,7 @@ Subject: [PATCH] UGW_SW-29163: ATM oam support /* * Disconnect a channel from the generic layer. -@@ -3629,6 +3645,7 @@ EXPORT_SYMBOL(ppp_unregister_channel); +@@ -3632,6 +3648,7 @@ EXPORT_SYMBOL(ppp_unregister_channel); EXPORT_SYMBOL(ppp_channel_index); EXPORT_SYMBOL(ppp_unit_number); EXPORT_SYMBOL(ppp_dev_name); diff --git a/target/linux/lantiq/patches-6.6/0101-find_active_root.patch b/target/linux/lantiq/patches-6.6/0101-find_active_root.patch index e07e653267..4741dfb612 100644 --- a/target/linux/lantiq/patches-6.6/0101-find_active_root.patch +++ b/target/linux/lantiq/patches-6.6/0101-find_active_root.patch @@ -98,8 +98,8 @@ Signed-off-by: Mathias Kresin <openwrt@kresin.me> return nr_parts; @@ -197,6 +249,7 @@ ofpart_none: + if (dedicated) of_node_put(ofpart_node); - of_node_put(pp); kfree(parts); + kfree(part_nodes); return ret; diff --git a/target/linux/lantiq/patches-6.6/0731-v6.11-dt-bindings-net-dsa-lantiq-gswip-convert-to-YAML-schema.patch b/target/linux/lantiq/patches-6.6/0731-v6.11-dt-bindings-net-dsa-lantiq-gswip-convert-to-YAML-schema.patch index 34a730c36f..70715d8ef1 100644 --- a/target/linux/lantiq/patches-6.6/0731-v6.11-dt-bindings-net-dsa-lantiq-gswip-convert-to-YAML-schema.patch +++ b/target/linux/lantiq/patches-6.6/0731-v6.11-dt-bindings-net-dsa-lantiq-gswip-convert-to-YAML-schema.patch @@ -382,7 +382,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org> -}; --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -11864,6 +11864,7 @@ LANTIQ / INTEL Ethernet drivers +@@ -11872,6 +11872,7 @@ LANTIQ / INTEL Ethernet drivers M: Hauke Mehrtens <hauke@hauke-m.de> L: netdev@vger.kernel.org S: Maintained diff --git a/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch index f912d4ed3b..f757670cef 100644 --- a/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch +++ b/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch @@ -891,7 +891,7 @@ Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> +}; --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -8360,6 +8360,14 @@ F: drivers/ptp/ptp_qoriq.c +@@ -8368,6 +8368,14 @@ F: drivers/ptp/ptp_qoriq.c F: drivers/ptp/ptp_qoriq_debugfs.c F: include/linux/fsl/ptp_qoriq.h diff --git a/target/linux/mediatek/patches-6.6/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.6/500-gsw-rtl8367s-mt7622-support.patch index bb7e7be6d2..e0f6f906e6 100644 --- a/target/linux/mediatek/patches-6.6/500-gsw-rtl8367s-mt7622-support.patch +++ b/target/linux/mediatek/patches-6.6/500-gsw-rtl8367s-mt7622-support.patch @@ -1,6 +1,6 @@ --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -416,6 +416,12 @@ config ROCKCHIP_PHY +@@ -424,6 +424,12 @@ config ROCKCHIP_PHY help Currently supports the integrated Ethernet PHY. @@ -15,7 +15,7 @@ select CRC16 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -102,6 +102,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o +@@ -106,6 +106,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_REALTEK_PHY) += realtek/ obj-$(CONFIG_RENESAS_PHY) += uPD60620.o obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff --git a/target/linux/mediatek/patches-6.6/733-01-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch b/target/linux/mediatek/patches-6.6/733-01-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch index a12097498e..ef21ff4d17 100644 --- a/target/linux/mediatek/patches-6.6/733-01-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch +++ b/target/linux/mediatek/patches-6.6/733-01-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch @@ -27,7 +27,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -313,22 +313,7 @@ config MAXLINEAR_GPHY +@@ -321,22 +321,7 @@ config MAXLINEAR_GPHY Support for the Maxlinear GPY115, GPY211, GPY212, GPY215, GPY241, GPY245 PHYs. @@ -53,7 +53,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> tristate "Micrel PHYs" --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -82,8 +82,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o +@@ -86,8 +86,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o diff --git a/target/linux/mediatek/patches-6.6/735-net-phy-realtek-rtl8261n.patch b/target/linux/mediatek/patches-6.6/735-net-phy-realtek-rtl8261n.patch index 676bd7c093..98abaabc1d 100644 --- a/target/linux/mediatek/patches-6.6/735-net-phy-realtek-rtl8261n.patch +++ b/target/linux/mediatek/patches-6.6/735-net-phy-realtek-rtl8261n.patch @@ -1,6 +1,6 @@ --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -396,6 +396,8 @@ config QSEMI_PHY +@@ -404,6 +404,8 @@ config QSEMI_PHY source "drivers/net/phy/realtek/Kconfig" @@ -11,7 +11,7 @@ help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -100,6 +100,7 @@ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja +@@ -104,6 +104,7 @@ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja obj-y += qcom/ obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_REALTEK_PHY) += realtek/ diff --git a/target/linux/mvebu/patches-6.6/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch b/target/linux/mvebu/patches-6.6/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch index d70bfe9a1a..5a5e4db31c 100644 --- a/target/linux/mvebu/patches-6.6/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch +++ b/target/linux/mvebu/patches-6.6/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch @@ -16,7 +16,7 @@ Cc: Robert Marko <robert.marko@sartura.hr> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -10143,6 +10143,22 @@ IFCVF VIRTIO DATA PATH ACCELERATOR +@@ -10151,6 +10151,22 @@ IFCVF VIRTIO DATA PATH ACCELERATOR R: Zhu Lingshan <lingshan.zhu@intel.com> F: drivers/vdpa/ifcvf/ diff --git a/target/linux/ramips/patches-6.6/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch b/target/linux/ramips/patches-6.6/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch index 0e68aa5907..15d8c037b1 100644 --- a/target/linux/ramips/patches-6.6/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch +++ b/target/linux/ramips/patches-6.6/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch @@ -65,7 +65,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net> &spi_nor_esmt, --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h -@@ -631,6 +631,7 @@ struct sfdp { +@@ -637,6 +637,7 @@ struct sfdp { /* Manufacturer drivers. */ extern const struct spi_nor_manufacturer spi_nor_atmel; diff --git a/target/linux/realtek/patches-6.6/302-clocksource-add-otto-driver.patch b/target/linux/realtek/patches-6.6/302-clocksource-add-otto-driver.patch index 791ad0edb7..bb51df4c97 100644 --- a/target/linux/realtek/patches-6.6/302-clocksource-add-otto-driver.patch +++ b/target/linux/realtek/patches-6.6/302-clocksource-add-otto-driver.patch @@ -83,7 +83,7 @@ Signed-off-by: Sander Vanheule <sander@svanheule.net> obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h -@@ -181,6 +181,7 @@ enum cpuhp_state { +@@ -180,6 +180,7 @@ enum cpuhp_state { CPUHP_AP_MARCO_TIMER_STARTING, CPUHP_AP_MIPS_GIC_TIMER_STARTING, CPUHP_AP_ARC_TIMER_STARTING, diff --git a/target/linux/realtek/patches-6.6/720-add-rtl-phy.patch b/target/linux/realtek/patches-6.6/720-add-rtl-phy.patch index 4d6866db24..fa2f41fe0c 100644 --- a/target/linux/realtek/patches-6.6/720-add-rtl-phy.patch +++ b/target/linux/realtek/patches-6.6/720-add-rtl-phy.patch @@ -14,7 +14,7 @@ Submitted-by: Birger Koblitz <mail@birger-koblitz.de> --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -407,6 +407,12 @@ config QSEMI_PHY +@@ -415,6 +415,12 @@ config QSEMI_PHY source "drivers/net/phy/realtek/Kconfig" @@ -29,7 +29,7 @@ Submitted-by: Birger Koblitz <mail@birger-koblitz.de> help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -100,6 +100,7 @@ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja +@@ -104,6 +104,7 @@ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja obj-y += qcom/ obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_REALTEK_PHY) += realtek/ diff --git a/target/linux/starfive/patches-6.6/0049-MAINTAINERS-Update-all-StarFive-entries.patch b/target/linux/starfive/patches-6.6/0049-MAINTAINERS-Update-all-StarFive-entries.patch index 1f023052fc..4d72fb9938 100644 --- a/target/linux/starfive/patches-6.6/0049-MAINTAINERS-Update-all-StarFive-entries.patch +++ b/target/linux/starfive/patches-6.6/0049-MAINTAINERS-Update-all-StarFive-entries.patch @@ -12,7 +12,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -7054,6 +7054,14 @@ T: git git://anongit.freedesktop.org/drm +@@ -7062,6 +7062,14 @@ T: git git://anongit.freedesktop.org/drm F: Documentation/devicetree/bindings/display/rockchip/ F: drivers/gpu/drm/rockchip/ @@ -27,7 +27,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> DRM DRIVERS FOR STI M: Alain Volmat <alain.volmat@foss.st.com> L: dri-devel@lists.freedesktop.org -@@ -16018,6 +16026,13 @@ F: Documentation/i2c/busses/i2c-ocores.r +@@ -16026,6 +16034,13 @@ F: Documentation/i2c/busses/i2c-ocores.r F: drivers/i2c/busses/i2c-ocores.c F: include/linux/platform_data/i2c-ocores.h @@ -41,7 +41,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> OPENRISC ARCHITECTURE M: Jonas Bonn <jonas@southpole.se> M: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> -@@ -16429,6 +16444,14 @@ S: Maintained +@@ -16437,6 +16452,14 @@ S: Maintained F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c @@ -56,7 +56,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> PCI DRIVER FOR RENESAS R-CAR M: Marek Vasut <marek.vasut+renesas@gmail.com> M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -@@ -16660,7 +16683,7 @@ M: Daire McNamara <daire.mcnamara@microc +@@ -16668,7 +16691,7 @@ M: Daire McNamara <daire.mcnamara@microc L: linux-pci@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/pci/microchip* @@ -65,7 +65,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> PCIE DRIVER FOR QUALCOMM MSM M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> -@@ -16684,6 +16707,13 @@ S: Maintained +@@ -16692,6 +16715,13 @@ S: Maintained F: Documentation/devicetree/bindings/pci/socionext,uniphier-pcie* F: drivers/pci/controller/dwc/pcie-uniphier* @@ -79,7 +79,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> PCIE DRIVER FOR ST SPEAR13XX M: Pratyush Anand <pratyush.anand@gmail.com> L: linux-pci@vger.kernel.org -@@ -18456,7 +18486,7 @@ F: drivers/char/hw_random/mpfs-rng.c +@@ -18464,7 +18494,7 @@ F: drivers/char/hw_random/mpfs-rng.c F: drivers/clk/microchip/clk-mpfs*.c F: drivers/i2c/busses/i2c-microchip-corei2c.c F: drivers/mailbox/mailbox-mpfs.c @@ -88,7 +88,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> F: drivers/pwm/pwm-microchip-core.c F: drivers/reset/reset-mpfs.c F: drivers/rtc/rtc-mpfs.c -@@ -20431,6 +20461,15 @@ M: Ion Badulescu <ionut@badula.org> +@@ -20439,6 +20469,15 @@ M: Ion Badulescu <ionut@badula.org> S: Odd Fixes F: drivers/net/ethernet/adaptec/starfire* @@ -104,7 +104,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> STARFIVE CRYPTO DRIVER M: Jia Jie Ho <jiajie.ho@starfivetech.com> M: William Qiu <william.qiu@starfivetech.com> -@@ -20469,6 +20508,13 @@ S: Supported +@@ -20477,6 +20516,13 @@ S: Supported F: Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml F: drivers/clk/starfive/clk-starfive-jh7110-pll.c @@ -118,7 +118,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> STARFIVE JH7110 SYSCON M: William Qiu <william.qiu@starfivetech.com> M: Xingyu Wu <xingyu.wu@starfivetech.com> -@@ -20516,9 +20562,10 @@ F: drivers/usb/cdns3/cdns3-starfive.c +@@ -20524,9 +20570,10 @@ F: drivers/usb/cdns3/cdns3-starfive.c STARFIVE JH71XX PMU CONTROLLER DRIVER M: Walker Chen <walker.chen@starfivetech.com> @@ -130,7 +130,7 @@ Signed-off-by: Hal Feng <hal.feng@starfivetech.com> F: include/dt-bindings/power/starfive,jh7110-pmu.h STARFIVE SOC DRIVERS -@@ -20526,7 +20573,13 @@ M: Conor Dooley <conor@kernel.org> +@@ -20534,7 +20581,13 @@ M: Conor Dooley <conor@kernel.org> S: Maintained T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: Documentation/devicetree/bindings/soc/starfive/ diff --git a/target/linux/starfive/patches-6.6/1003-dmaengine-dw-axi-dmac-Handle-xfer-start-while-non-id.patch b/target/linux/starfive/patches-6.6/1003-dmaengine-dw-axi-dmac-Handle-xfer-start-while-non-id.patch index d0c692e1a5..ca5edb3e7e 100644 --- a/target/linux/starfive/patches-6.6/1003-dmaengine-dw-axi-dmac-Handle-xfer-start-while-non-id.patch +++ b/target/linux/starfive/patches-6.6/1003-dmaengine-dw-axi-dmac-Handle-xfer-start-while-non-id.patch @@ -28,7 +28,7 @@ Signed-off-by: Curry Zhang <curry.zhang@starfivetech.com> } axi_dma_enable(chan->chip); -@@ -1028,6 +1030,14 @@ static noinline void axi_chan_handle_err +@@ -1026,6 +1028,14 @@ static noinline void axi_chan_handle_err axi_chan_name(chan)); goto out; } diff --git a/target/linux/starfive/patches-6.6/1004-dmaengine-dw-axi-dmac-Add-StarFive-JH7100-support.patch b/target/linux/starfive/patches-6.6/1004-dmaengine-dw-axi-dmac-Add-StarFive-JH7100-support.patch index 74a05cf80a..b23bbe05b3 100644 --- a/target/linux/starfive/patches-6.6/1004-dmaengine-dw-axi-dmac-Add-StarFive-JH7100-support.patch +++ b/target/linux/starfive/patches-6.6/1004-dmaengine-dw-axi-dmac-Add-StarFive-JH7100-support.patch @@ -12,7 +12,7 @@ Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c -@@ -677,8 +677,13 @@ static int dw_axi_dma_set_hw_desc(struct +@@ -675,8 +675,13 @@ static int dw_axi_dma_set_hw_desc(struct hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); @@ -26,7 +26,7 @@ Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> hw_desc->lli->ctl_lo = cpu_to_le32(ctllo); set_desc_src_master(hw_desc); -@@ -1502,7 +1507,11 @@ static int dw_probe(struct platform_devi +@@ -1500,7 +1505,11 @@ static int dw_probe(struct platform_devi * Therefore, set constraint to 1024 * 4. */ dw->dma.dev->dma_parms = &dw->dma_parms; @@ -38,7 +38,7 @@ Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> platform_set_drvdata(pdev, chip); pm_runtime_enable(chip->dev); -@@ -1587,6 +1596,9 @@ static const struct of_device_id dw_dma_ +@@ -1585,6 +1594,9 @@ static const struct of_device_id dw_dma_ .compatible = "intel,kmb-axi-dma", .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS, }, { diff --git a/target/linux/starfive/patches-6.6/1014-reset-starfive-Add-JH7100-audio-reset-driver.patch b/target/linux/starfive/patches-6.6/1014-reset-starfive-Add-JH7100-audio-reset-driver.patch index 578b6bf84a..9aa9bdce31 100644 --- a/target/linux/starfive/patches-6.6/1014-reset-starfive-Add-JH7100-audio-reset-driver.patch +++ b/target/linux/starfive/patches-6.6/1014-reset-starfive-Add-JH7100-audio-reset-driver.patch @@ -20,7 +20,7 @@ Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -20550,7 +20550,7 @@ STARFIVE JH71X0 RESET CONTROLLER DRIVERS +@@ -20558,7 +20558,7 @@ STARFIVE JH71X0 RESET CONTROLLER DRIVERS M: Emil Renner Berthing <kernel@esmil.dk> M: Hal Feng <hal.feng@starfivetech.com> S: Maintained |