#include <assert.h>
#include <bl_common.h>
#include <boot_api.h>
-#include <console.h>
#include <debug.h>
#include <delay_timer.h>
#include <desc_image_load.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
+#include <stm32_console.h>
#include <stm32mp1_clk.h>
+#include <stm32mp1_context.h>
#include <stm32mp1_dt.h>
#include <stm32mp1_pmic.h>
#include <stm32mp1_private.h>
-#include <stm32mp1_context.h>
#include <stm32mp1_pwr.h>
#include <stm32mp1_ram.h>
#include <stm32mp1_rcc.h>
#include <string.h>
#include <xlat_tables_v2.h>
+static struct console_stm32 console;
+
void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock);
- if (console_init(dt_dev_info.base, clk_rate,
- STM32MP1_UART_BAUDRATE) == 0) {
+ if (console_stm32_register(dt_dev_info.base, clk_rate,
+ STM32MP1_UART_BAUDRATE, &console) == 0) {
panic();
}
ARM_WITH_NEON := yes
BL2_AT_EL3 := 1
USE_COHERENT_MEM := 0
+MULTI_CONSOLE_API := 1
STM32_TF_VERSION ?= 0
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
-#include <console.h>
#include <context.h>
#include <context_mgmt.h>
#include <debug.h>
#include <platform.h>
#include <platform_def.h>
#include <platform_sp_min.h>
+#include <stm32_console.h>
#include <stm32mp1_clk.h>
#include <stm32mp1_dt.h>
#include <stm32mp1_private.h>
******************************************************************************/
static entry_point_info_t bl33_image_ep_info;
+static struct console_stm32 console;
+
/*******************************************************************************
* Interrupt handler for FIQ (secure IRQ)
******************************************************************************/
result = dt_get_stdout_uart_info(&dt_dev_info);
if ((result > 0) && dt_dev_info.status) {
- if (console_init(dt_dev_info.base, 0, STM32MP1_UART_BAUDRATE)
- == 0) {
+ if (console_stm32_register(dt_dev_info.base, 0,
+ STM32MP1_UART_BAUDRATE, &console) ==
+ 0) {
panic();
}
}
ldr r0, =STM32MP1_DEBUG_USART_BASE
ldr r1, =STM32MP1_HSI_CLK
ldr r2, =STM32MP1_UART_BAUDRATE
- b console_core_init
+ b console_stm32_core_init
endfunc plat_crash_console_init
/* ---------------------------------------------
*/
func plat_crash_console_flush
ldr r1, =STM32MP1_DEBUG_USART_BASE
- b console_core_flush
+ b console_stm32_core_flush
endfunc plat_crash_console_flush
/* ---------------------------------------------
*/
func plat_crash_console_putc
ldr r1, =STM32MP1_DEBUG_USART_BASE
- b console_core_putc
+ b console_stm32_core_putc
endfunc plat_crash_console_putc