diff options
| author | Mantas Pucka | 2025-03-28 08:40:44 +0000 |
|---|---|---|
| committer | Christian Marangi | 2025-04-12 08:38:50 +0000 |
| commit | e46bc86df785b49443ddcf1e09f5c7821ab4de1c (patch) | |
| tree | f799ce97ffd951c46cc2387c8366c1cb79c94ace | |
| parent | baf7be6705b5a097bacf765516918af94a9d98e2 (diff) | |
| download | openwrt-e46bc86df785b49443ddcf1e09f5c7821ab4de1c.tar.gz | |
qualcommbe: ipq95xx: nsscc: fix port5 clock parent
Fix incorrect port5 clock management
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://github.com/openwrt/openwrt/pull/18459
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
| -rw-r--r-- | target/linux/qualcommbe/patches-6.6/310-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/target/linux/qualcommbe/patches-6.6/310-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch b/target/linux/qualcommbe/patches-6.6/310-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch new file mode 100644 index 0000000000..ac846284bf --- /dev/null +++ b/target/linux/qualcommbe/patches-6.6/310-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch @@ -0,0 +1,46 @@ +From ce4c7eea1b6f05723240aadc5e1c240d26a6ef88 Mon Sep 17 00:00:00 2001 +From: Mantas Pucka <mantas@8devices.com> +Date: Mon, 31 Mar 2025 15:39:59 +0300 +Subject: [PATCH] clk: qcom: nsscc-ipq9574: fix port5 clock config + +Currently there is no configuration to derive 25/125MHz port5 clock +from uniphy1 running at 125MHz. This is needed for SGMII mode when +port5 is using uniphy1. + +Fix this by adding option such clock config option. + +Signed-off-by: Mantas Pucka <mantas@8devices.com> +--- + drivers/clk/qcom/nsscc-ipq9574.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/clk/qcom/nsscc-ipq9574.c ++++ b/drivers/clk/qcom/nsscc-ipq9574.c +@@ -387,11 +387,13 @@ static const struct freq_multi_tbl ftbl_ + + static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = { + C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), + }; + + static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = { + C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), + }; + +@@ -412,11 +414,13 @@ static const struct freq_multi_tbl ftbl_ + + static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = { + C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), + }; + + static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = { + C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), + }; + |