qualcommax: ipq50xx: remove named clock references for GE PHY

With completely carving out GE PHY out of the QCA-SSDK, the named clock
references to the GE PHY RX and TX clocks are no longer needed.
So, let's revert to using the DT indices as per the upstream GCC driver.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18774
Signed-off-by: Robert Marko <robimarko@gmail.com>

diff --git a/target/linux/qualcommax/patches-6.12/0722-clk-gcc-ipq5018-refer-to-ge-phy-rx-and-tx-clk-providers-by-name.patch b/target/linux/qualcommax/patches-6.12/0722-clk-gcc-ipq5018-refer-to-ge-phy-rx-and-tx-clk-providers-by-name.patch
deleted file mode 100644 (file)
index 1610a24..0000000
--- a/target/linux/qualcommax/patches-6.12/0722-clk-gcc-ipq5018-refer-to-ge-phy-rx-and-tx-clk-providers-by-name.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From ce9e56a436e486690097cfbdda2d0c11b60db4c2 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <hzyitc@outlook.com>
-Date: Sun, 8 Sep 2024 16:40:12 +0800
-Subject: [PATCH] clk: gcc-ipq5018: refer to GE PHY rx and tx clk providers by name
-
-QCA-SSDK does not register the output clocks of the onboard GE Phy and 
-uniphy so the GCC and DTS can't reference them by their index.
-The SSDK references them by name, so let's change the GCC driver 
-accordingly.
-
-Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
-Signed-off-by: George Moussalem <george.moussalem@outlook.com>
----
- drivers/clk/qcom/gcc-ipq5018.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq5018.c
-+++ b/drivers/clk/qcom/gcc-ipq5018.c
-@@ -336,8 +336,8 @@ static const struct parent_map gcc_xo_gp
- 
- static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
-       { .index = DT_XO },
--      { .index = DT_GEPHY_RX_CLK },
--      { .index = DT_GEPHY_TX_CLK },
-+      { .name =  "gephy_gcc_rx", .index = -1 },
-+      { .name =  "gephy_gcc_tx", .index = -1 },
-       { .hw = &ubi32_pll.clkr.hw },
-       { .hw = &gpll0.clkr.hw },
- };
-@@ -352,8 +352,8 @@ static const struct parent_map gcc_xo_ge
- 
- static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
-       { .index = DT_XO },
--      { .index = DT_GEPHY_TX_CLK },
--      { .index = DT_GEPHY_RX_CLK },
-+      { .name =  "gephy_gcc_tx", .index = -1 },
-+      { .name =  "gephy_gcc_rx", .index = -1 },
-       { .hw = &ubi32_pll.clkr.hw },
-       { .hw = &gpll0.clkr.hw },
- };
-@@ -368,8 +368,8 @@ static const struct parent_map gcc_xo_ge
- 
- static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
-       { .index = DT_XO },
--      { .index = DT_UNIPHY_RX_CLK },
--      { .index = DT_UNIPHY_TX_CLK },
-+      { .name =  "uniphy_gcc_rx", .index = -1 },
-+      { .name =  "uniphy_gcc_tx", .index = -1 },
-       { .hw = &ubi32_pll.clkr.hw },
-       { .hw = &gpll0.clkr.hw },
- };
-@@ -384,8 +384,8 @@ static const struct parent_map gcc_xo_un
- 
- static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
-       { .index = DT_XO },
--      { .index = DT_UNIPHY_TX_CLK },
--      { .index = DT_UNIPHY_RX_CLK },
-+      { .name =  "uniphy_gcc_tx", .index = -1 },
-+      { .name =  "uniphy_gcc_rx", .index = -1 },
-       { .hw = &ubi32_pll.clkr.hw },
-       { .hw = &gpll0.clkr.hw },
- };

diff --git a/target/linux/qualcommax/patches-6.12/0722-clk-qcom-gcc-ipq5018-refer-to-uniphy-rx-and-tx-clk-providers-by-name.patch b/target/linux/qualcommax/patches-6.12/0722-clk-qcom-gcc-ipq5018-refer-to-uniphy-rx-and-tx-clk-providers-by-name.patch
new file mode 100644 (file)
index 0000000..6ecdee0
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.12/0722-clk-qcom-gcc-ipq5018-refer-to-uniphy-rx-and-tx-clk-providers-by-name.patch
@@ -0,0 +1,40 @@
+From ce9e56a436e486690097cfbdda2d0c11b60db4c2 Mon Sep 17 00:00:00 2001
+From: Ziyang Huang <hzyitc@outlook.com>
+Date: Sun, 8 Sep 2024 16:40:12 +0800
+Subject: [PATCH] clk: gcc-ipq5018: refer to UNIPHY rx and tx clk providers by name
+
+QCA-SSDK does not register the output clocks of the onboard uniphy so the
+GCC and DTS can't reference them by their index.
+The SSDK references them by name, so let's change the GCC driver 
+accordingly.
+
+Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
+Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+---
+ drivers/clk/qcom/gcc-ipq5018.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq5018.c
++++ b/drivers/clk/qcom/gcc-ipq5018.c
+@@ -368,8 +368,8 @@ static const struct parent_map gcc_xo_ge
+ 
+ static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
+       { .index = DT_XO },
+-      { .index = DT_UNIPHY_RX_CLK },
+-      { .index = DT_UNIPHY_TX_CLK },
++      { .name =  "uniphy_gcc_rx", .index = -1 },
++      { .name =  "uniphy_gcc_tx", .index = -1 },
+       { .hw = &ubi32_pll.clkr.hw },
+       { .hw = &gpll0.clkr.hw },
+ };
+@@ -384,8 +384,8 @@ static const struct parent_map gcc_xo_un
+ 
+ static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
+       { .index = DT_XO },
+-      { .index = DT_UNIPHY_TX_CLK },
+-      { .index = DT_UNIPHY_RX_CLK },
++      { .name =  "uniphy_gcc_tx", .index = -1 },
++      { .name =  "uniphy_gcc_rx", .index = -1 },
+       { .hw = &ubi32_pll.clkr.hw },
+       { .hw = &gpll0.clkr.hw },
+ };