ramips: fix some clocks in mt7621.dtsi

As the cpu clock calculation has been fixed, the clock for gic and spi
should be also fixed.

Signed-off-by: Weijie Gao <hackpascal@gmail.com>
(backported from ed25e3ac02d9193d7cba89563a88b8bccc4b4513)

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index c0e830a360ecb2183ed95769b2630e4f2b253dc9..97a28cb10f0c4e5a1624e5c7f8c492cb5802be18 100644 (file)
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -41,14 +41,6 @@
                clock-output-names = "cpu", "bus";
        };
 
-       cpuclock: cpuclock {
-               #clock-cells = <0>;
-               compatible = "fixed-clock";
-
-               /* FIXME: there should be way to detect this */
-               clock-frequency = <880000000>;
-       };
-
        sysclock: sysclock {
                #clock-cells = <0>;
                compatible = "fixed-clock";
@@ -176,7 +168,6 @@
                        compatible = "ns16550a";
                        reg = <0xc00 0x100>;
 
-                       clocks = <&sysclock>;
                        clock-frequency = <50000000>;
 
                        interrupt-parent = <&gic>;
@@ -193,7 +184,7 @@
                        compatible = "ralink,mt7621-spi";
                        reg = <0xb00 0x100>;
 
-                       clocks = <&sysclock>;
+                       clocks = <&pll MT7621_CLK_BUS>;
 
                        resets = <&rstctrl 18>;
                        reset-names = "spi";
@@ -402,7 +393,7 @@
                timer {
                        compatible = "mti,gic-timer";
                        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-                       clocks = <&cpuclock>;
+                       clocks = <&pll MT7621_CLK_CPU>;
                };
        };