#
# Top-level generic files
#
-fit-dtb.blob
+fit-dtb.blob*
/MLO*
/SPL*
/System.map
--- /dev/null
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+ "arm,pl310-cache"
+ "arm,l220-cache"
+ "arm,l210-cache"
+ "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+ "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+ "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+ "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+ "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+ registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Minimum valid values are 1. Controllers
+ without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Controllers without setup latency control
+ should use 0. Controllers without separate read and write Tag RAM latency
+ values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges : <start length> Starting address and length of window to
+ filter. Addresses in the filter window are directed to the M1 port. Other
+ addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+ I/O coherent mode. Valid only when the arm,pl310-cache compatible
+ string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+ if this is not specified, the line size is assumed to be equal to the
+ cache block size
+- cache-id-part: cache id part number to be used if it is not present
+ on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
+ disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+ 0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+ controllers with respect to the shareable attribute is to transform "normal
+ memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+ or "write through no write allocate" (for writes).
+ On systems where this may cause DMA buffer corruption, this property must be
+ specified to indicate that such transforms are precluded.
+- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
+- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
+- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
+ Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
+ will randomly hang unless outer sync operations are disabled.
+- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
+ (forcibly enable), property absent (retain settings set by firmware)
+- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
+ <1> (forcibly enable), property absent (retain settings set by
+ firmware)
+- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
+ disable), <1> (forcibly enable), property absent (OS specific behavior,
+ preferably retain firmware settings)
+- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
+ <1> (forcibly enable), property absent (OS specific behavior,
+ preferably retain firmware settings)
+- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310)
+- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero
+ write (PL310)
+
+Example:
+
+L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfff12000 0x1000>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-ranges = <0x80000000 0x8000000>;
+ cache-unified;
+ cache-level = <2>;
+ interrupts = <45>;
+};
+
+Note 1: The description in this document doesn't apply to integrated L2
+ cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
+ integrated L2 controllers are assumed to be all preconfigured by
+ early secure boot code. Thus no need to deal with their configuration
+ in the kernel at all.
--- /dev/null
+The following properties are common to the Ethernet controllers:
+
+NOTE: All 'phy*' properties documented below are Ethernet specific. For the
+generic PHY 'phys' property, see
+Documentation/devicetree/bindings/phy/phy-bindings.txt.
+
+- local-mac-address: array of 6 bytes, specifies the MAC address that was
+ assigned to the network device;
+- mac-address: array of 6 bytes, specifies the MAC address that was last used by
+ the boot program; should be used in cases where the MAC address assigned to
+ the device by the boot program is different from the "local-mac-address"
+ property;
+- nvmem-cells: phandle, reference to an nvmem node for the MAC address;
+- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
+- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
+- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
+ the maximum frame size (there's contradiction in the Devicetree
+ Specification).
+- phy-mode: string, operation mode of the PHY interface. This is now a de-facto
+ standard property; supported values are:
+ * "internal"
+ * "mii"
+ * "gmii"
+ * "sgmii"
+ * "qsgmii"
+ * "tbi"
+ * "rev-mii"
+ * "rmii"
+ * "rgmii" (RX and TX delays are added by the MAC when required)
+ * "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the
+ MAC should not add the RX or TX delays in this case)
+ * "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
+ should not add an RX delay in this case)
+ * "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
+ should not add an TX delay in this case)
+ * "rtbi"
+ * "smii"
+ * "xgmii"
+ * "trgmii"
+ * "2000base-x",
+ * "2500base-x",
+ * "rxaui"
+ * "xaui"
+ * "10gbase-kr" (10GBASE-KR, XFI, SFI)
+- phy-connection-type: the same as "phy-mode" property but described in the
+ Devicetree Specification;
+- phy-handle: phandle, specifies a reference to a node representing a PHY
+ device; this property is described in the Devicetree Specification and so
+ preferred;
+- phy: the same as "phy-handle" property, not recommended for new bindings.
+- phy-device: the same as "phy-handle" property, not recommended for new
+ bindings.
+- rx-fifo-depth: the size of the controller's receive fifo in bytes. This
+ is used for components that can have configurable receive fifo sizes,
+ and is useful for determining certain configuration settings such as
+ flow control thresholds.
+- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
+ is used for components that can have configurable fifo sizes.
+- managed: string, specifies the PHY management type. Supported values are:
+ "auto", "in-band-status". "auto" is the default, it usess MDIO for
+ management if fixed-link is not specified.
+
+Child nodes of the Ethernet controller are typically the individual PHY devices
+connected via the MDIO bus (sometimes the MDIO bus controller is separate).
+They are described in the phy.txt file in this same directory.
+For non-MDIO PHY management see fixed-link.txt.
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
- depends on ARCH_ZYNQ || ARCH_VERSAL
+ depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP
help
This defines memory to be allocated for Dynamic allocation
TODO: Use for other architectures
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in SPL before relocation"
depends on SYS_MALLOC_F
+ default 0x2800 if RCAR_GEN3
default SYS_MALLOC_F_LEN
help
Before relocation, memory is very limited on many platforms. Still,
if FIT
config FIT_EXTERNAL_OFFSET
- hex "Text Base"
+ hex "FIT external data offset"
default 0x0
help
This specifies a data offset in fit image.
select SPL_RSA
config SPL_LOAD_FIT
- bool "Enable SPL loading U-Boot as a FIT"
+ bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part
and passing the correct one to U-Boot.
config SPL_LOAD_FIT_FULL
- bool "Enable SPL loading U-Boot as a FIT"
+ bool "Enable SPL loading U-Boot as a FIT (full fitImage features)"
select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part
string ".its file generator script for U-Boot FIT image"
depends on SPL_FIT
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
+ default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
help
Specifies a (platform specific) script file to generate the FIT
source file used to build the U-Boot FIT image file. This gets
config SYS_CLK_FREQ
- depends on ARC || ARCH_SUNXI
+ depends on ARC || ARCH_SUNXI || MPC83xx
int "CPU clock frequency"
help
TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
ARM ROCKCHIP
M: Simon Glass <sjg@chromium.org>
M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
T: git git://git.denx.de/u-boot-rockchip.git
F: arch/arm/include/asm/arch-rockchip/
F: doc/README.iscsi
F: Documentation/efi.rst
F: include/capitalization.h
+F: include/charset.h
F: include/cp1250.h
F: include/cp437.h
F: include/efi*
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-fsl-qoriq.git
+F: drivers/watchdog/sp805_wdt.c
I2C
M: Heiko Schocher <hs@denx.de>
F: drivers/gpio/mscc_sgpio.c
F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
+F: include/dt-bindings/mscc/
F: drivers/pinctrl/mscc/
F: drivers/net/mscc_eswitch/
F: arch/mips/mach-jz47xx/
MMC
-M: Jaehoon Chung <jh80.chung@samsung.com>
+M: Peng Fan <peng.fan@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-mmc.git
F: drivers/mmc/
VERSION = 2019
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
# KBUILD_MODULES := 1
#endif
+define size_check
+ actual=$$( wc -c $1 | awk '{print $$1}'); \
+ limit=$$( printf "%d" $2 ); \
+ if test $$actual -gt $$limit; then \
+ echo "$1 exceeds file size limit:" >&2; \
+ echo " limit: $$limit bytes" >&2; \
+ echo " actual: $$actual bytes" >&2; \
+ echo " excess: $$((actual - limit)) bytes" >&2; \
+ exit 1; \
+ fi
+endef
+export size_check
+
export KBUILD_MODULES KBUILD_BUILTIN
export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
-libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
+libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/serial/
libs-y += drivers/usb/dwc3/
libs-y += drivers/usb/common/
#########################################################################
ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
-BOARD_SIZE_CHECK = \
- @actual=`wc -c $@ | awk '{print $$1}'`; \
- limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
- if test $$actual -gt $$limit; then \
- echo "$@ exceeds file size limit:" >&2 ; \
- echo " limit: $$limit bytes" >&2 ; \
- echo " actual: $$actual bytes" >&2 ; \
- echo " excess: $$((actual - limit)) bytes" >&2; \
- exit 1; \
- fi
+BOARD_SIZE_CHECK= @ $(call size_check,$@,$(CONFIG_BOARD_SIZE_LIMIT))
else
BOARD_SIZE_CHECK =
endif
+ifneq ($(CONFIG_SPL_SIZE_LIMIT),0)
+SPL_SIZE_CHECK = @$(call size_check,$@,$$(tools/spl_size_limit))
+else
+SPL_SIZE_CHECK =
+endif
+
# Statically apply RELA-style relocations (currently arm64 only)
# This is useful for arm64 where static relocation needs to be performed on
# the raw binary, but certain simulators only accept an ELF file (but don't
@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
@echo >&2 "===================================================="
endif
+endif
+ifneq ($(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG),)
+ifneq ($(CONFIG_WDT),y)
+ @echo >&2 "===================== WARNING ======================"
+ @echo >&2 "This board does not use CONFIG_WDT (DM watchdog support)."
+ @echo >&2 "Please update the board to use CONFIG_WDT before the"
+ @echo >&2 "v2019.10 release."
+ @echo >&2 "Failure to update by the deadline may result in board removal."
+ @echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
+ @echo >&2 "===================================================="
+endif
endif
@# Check that this build does not use CONFIG options that we do not
@# know about unless they are in Kconfig. All the existing CONFIG
fit-dtb.blob: dts/dt.dtb FORCE
$(call if_changed,mkimage)
+ifneq ($(SOURCE_DATE_EPOCH),)
+ touch -d @$(SOURCE_DATE_EPOCH) fit-dtb.blob
+ chmod 0600 fit-dtb.blob
+endif
MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a 0 -e 0 -E \
%.imx: %.bin
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+ $(BOARD_SIZE_CHECK)
%.vyb: %.imx
$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
spl/u-boot-spl.srec: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
+%.scif: %.srec
+ $(Q)$(MAKE) $(build)=arch/arm/mach-rmobile $@
+
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \
$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
+ $(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin) \
$(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE
$(call if_changed,binman)
spl/u-boot-spl.bin: spl/u-boot-spl
@:
+ $(SPL_SIZE_CHECK)
+
spl/u-boot-spl: tools prepare \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
envtools: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools/env
+tools-only: export TOOLS_ONLY=y
tools-only: scripts_basic $(version_h) $(timestamp_h)
$(Q)$(MAKE) $(build)=tools
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
- boot* u-boot* MLO* SPL System.map fit-dtb.blob
+ boot* u-boot* MLO* SPL System.map fit-dtb.blob*
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
the defaults discussed just above.
- Cache Configuration:
- CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
- CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
- Cache Configuration for ARM:
CONFIG_SH_MMCIF_CLK
Define the clock frequency for MMCIF
- CONFIG_SUPPORT_EMMC_BOOT
- Enable some additional features of the eMMC boot partitions.
-
- USB Device Firmware Update (DFU) class support:
CONFIG_DFU_OVER_USB
This enables the USB portion of the DFU USB class
- CONFIG_SYS_FMAN_FW_ADDR
The address in the storage device where the FMAN microcode is located. The
- meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ meaning of this address depends on which CONFIG_SYS_QE_FMAN_FW_IN_xxx macro
is also specified.
- CONFIG_SYS_QE_FW_ADDR
The address in the storage device where the QE microcode is located. The
- meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ meaning of this address depends on which CONFIG_SYS_QE_FMAN_FW_IN_xxx macro
is also specified.
- CONFIG_SYS_QE_FMAN_FW_LENGTH
select HAVE_PRIVATE_LIBGCC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
+ select SUPPORT_OF_CONTROL
config MICROBLAZE
bool "MicroBlaze architecture"
config X86
bool "x86 architecture"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
select CREATE_ARCH_SYMLINK
select DM
select DM_PCI
imply DM_USB
imply DM_VIDEO
imply SYSRESET
+ imply SPL_SYSRESET
imply SYSRESET_X86
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
imply PCH
+ imply RTC_MC146818
+
+ # Thing to enable for when SPL/TPL are enabled: SPL
+ imply SPL_DM
+ imply SPL_OF_LIBFDT
+ imply SPL_DRIVERS_MISC_SUPPORT
+ imply SPL_GPIO_SUPPORT
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_SERIAL_SUPPORT
+ imply SPL_SPI_FLASH_SUPPORT
+ imply SPL_SPI_SUPPORT
+ imply SPL_OF_CONTROL
+ imply SPL_TIMER
+ imply SPL_REGMAP
+ imply SPL_SYSCON
+ # TPL
+ imply TPL_DM
+ imply TPL_OF_LIBFDT
+ imply TPL_DRIVERS_MISC_SUPPORT
+ imply TPL_GPIO_SUPPORT
+ imply TPL_LIBCOMMON_SUPPORT
+ imply TPL_LIBGENERIC_SUPPORT
+ imply TPL_SERIAL_SUPPORT
+ imply TPL_SPI_FLASH_SUPPORT
+ imply TPL_SPI_SUPPORT
+ imply TPL_OF_CONTROL
+ imply TPL_TIMER
+ imply TPL_REGMAP
+ imply TPL_SYSCON
config XTENSA
bool "Xtensa architecture"
The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
should be included from include/config.h.
+config SYS_DISABLE_DCACHE_OPS
+ bool
+ help
+ This option disables dcache flush and dcache invalidation
+ operations. For example, on coherent systems where cache
+ operatios are not required, enable this option to avoid them.
+ Note that, its up to the individual architectures to implement
+ this functionality.
+
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/m68k/Kconfig"
Build kernel for Big Endian Mode of ARC CPU
config SYS_ICACHE_OFF
- bool "Do not use Instruction Cache"
+ bool "Do not enable icache"
default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
- bool "Do not use Data Cache"
+ bool "Do not enable dcache"
default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
menuconfig ARC_DBG
bool "ARC debugging"
lr r5, [ARC_BCR_IC_BUILD]
breq r5, 0, 1f ; I$ doesn't exist
lr r5, [ARC_AUX_IC_CTRL]
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
#else
bset r5, r5, 0 ; I$ exists, but is not used
breq r5, 0, 1f ; D$ doesn't exist
lr r5, [ARC_AUX_DC_CTRL]
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
bclr r5, r5, 0 ; Enable (+Inv)
#else
bset r5, r5, 0 ; Disable (+Inv)
config THUMB2_KERNEL
bool
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
config SYS_ARM_CACHE_CP15
bool "CP15 based cache enabling support"
help
density. For ARM architectures that support Thumb2 this flag will
result in Thumb2 code generated by GCC.
+config TPL_SYS_THUMB_BUILD
+ bool "Build TPL using the Thumb instruction set"
+ default y if SYS_THUMB_BUILD
+ depends on TPL && !ARM64
+ help
+ Use this flag to build SPL using the Thumb instruction set for
+ ARM architectures. Thumb instruction set provides better code
+ density. For ARM architectures that support Thumb2 this flag will
+ result in Thumb2 code generated by GCC.
+
+
config SYS_L2CACHE_OFF
bool "L2cache off"
help
Such implementation may be faster under some conditions
but may increase the binary size.
+config TPL_USE_ARCH_MEMCPY
+ bool "Use an assembly optimized implementation of memcpy for TPL"
+ default y if USE_ARCH_MEMCPY
+ depends on !ARM64
+ help
+ Enable the generation of an optimized version of memcpy.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
config USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset"
default y
Such implementation may be faster under some conditions
but may increase the binary size.
+config TPL_USE_ARCH_MEMSET
+ bool "Use an assembly optimized implementation of memset for TPL"
+ default y if USE_ARCH_MEMSET
+ depends on !ARM64
+ help
+ Enable the generation of an optimized version of memset.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
config ARM64_SUPPORT_AARCH32
bool "ARM64 system support AArch32 execution state"
default y if ARM64 && !TARGET_THUNDERX_88XX
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
- select BOARD_EARLY_INIT_F
+ select BOARD_EARLY_INIT_F if !RZA1
select DM
select DM_SERIAL
imply CMD_DM
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
+ imply L2X0_CACHE
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
+config TARGET_LS1028AQDS
+ bool "Support ls1028aqds"
+ select ARCH_LS1028A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS1028AQDS platform
+ The LS1028A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1028A
+ Layerscape Architecture processor.
+
+config TARGET_LS1028ARDB
+ bool "Support ls1028ardb"
+ select ARCH_LS1028A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS1028ARDB platform
+ The LS1028A Development System (RDB) is a high-performance
+ development platform that supports the QorIQ LS1028A
+ Layerscape Architecture processor.
+
config TARGET_LS1088ARDB
bool "Support ls1088ardb"
select ARCH_LS1088A
select SYSCON
select SYSRESET
select SYS_THUMB_BUILD
+ imply SPL_SYSRESET
imply CMD_DM
imply CMD_POWEROFF
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
+ imply USE_PREBOOT
help
Support for STM32MP SoC family developed by STMicroelectronics,
MPUs based on ARM cortex A core
select SYS_THUMB_BUILD if !ARM64
imply ADC
imply CMD_DM
+ imply DEBUG_UART_BOARD_INIT
imply DISTRO_DEFAULTS
imply FAT_WRITE
imply SARADC_ROCKCHIP
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
+source "board/freescale/ls1028a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/ucRobotics/bubblegum_96/Kconfig"
source "board/birdland/bav335x/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
+source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/xilinx/Kconfig"
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
__weak void invalidate_l2_cache(void) {}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
/* flush I/D-cache */
static void cache_flush (void)
{
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
/*
* disable MMU and D cache
- * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
+ * enable I cache if SYS_ICACHE_OFF is not defined
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0
ulong timer_get_boot_us(void)
{
+ if (!gd->arch.timer_rate_hz)
+ timer_init();
+
return lldiv(get_ticks(), gd->arch.timer_rate_hz / 1000000);
}
#define ARMV7_DCACHE_INVAL_RANGE 1
#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Asm functions from cache_v7_asm.S */
void v7_flush_dcache_all(void);
flush_dcache_range(start, stop);
v7_inval_tlb();
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
void arm_init_domains(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
#include <common.h>
#include <linux/sizes.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* Bit[1] of the descriptor indicates the descriptor type,
invalidate_dcache_all();
set_cr(get_cr() | CR_C);
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
uint get_svr(void)
/*
* If I-cache is enabled invalidate it
*/
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
#else
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
};
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct dcache_config {
u32 ways;
u32 sets;
}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
!TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
!TARGET_LS1012AFRWY && \
+ !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* With 4k page granule, a virtual address is split into 4 lookup parts
debug("flushing dcache successfully.\n");
}
+#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
/*
* Invalidates range in all levels of D-cache/unified cache
*/
{
__asm_flush_dcache_range(start, stop);
}
+#else
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+#endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
void dcache_enable(void)
{
__asm_invalidate_tlb_all();
}
-#else /* CONFIG_SYS_DCACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* For SPL builds, we may want to not have dcache enabled. Any real U-Boot
{
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable(void)
{
__asm_invalidate_l3_icache();
}
-#else /* CONFIG_SYS_ICACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
void icache_enable(void)
{
{
}
-#endif /* CONFIG_SYS_ICACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
/*
* Enable dCache & iCache, whether cache is actually enabled
select SYS_I2C_MXC_I2C2
imply PANIC_HANG
+config ARCH_LS1028A
+ bool
+ select ARMV8_SET_SMPEN
+ select FSL_LSCH3
+ select NXP_LSCH3_2
+ select SYS_FSL_HAS_CCI400
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_LE
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
+ select FSL_TZASC_1
+ select ARCH_EARLY_INIT_R
+ select BOARD_EARLY_INIT_F
+ select SYS_I2C_MXC
+ select SYS_I2C_MXC_I2C1
+ select SYS_I2C_MXC_I2C2
+ select SYS_I2C_MXC_I2C3
+ select SYS_I2C_MXC_I2C4
+ select SYS_I2C_MXC_I2C5
+ select SYS_I2C_MXC_I2C6
+ select SYS_I2C_MXC_I2C7
+ select SYS_I2C_MXC_I2C8
+ select SYS_FSL_ERRATUM_A009007
+ select SYS_FSL_ERRATUM_A008514 if !TFABOOT
+ select SYS_FSL_ERRATUM_A009663 if !TFABOOT
+ select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+ imply PANIC_HANG
+
config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
- depends on PCIE_LAYERSCAPE
+ depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
default "fsl,ls1012a-pcie" if ARCH_LS1012A
+ default "fsl,ls1028a-pcie" if ARCH_LS1028A
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
+ default 2 if ARCH_LS1028A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
- default 0x3090000 if ARCH_LS1088A
+ default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
default 0x180000 if FSL_LSCH2
help
Offset for CCI400 base
config SYS_FSL_PCLK_DIV
int "Platform clock divider"
+ default 1 if ARCH_LS1028A
default 1 if ARCH_LS1043A
default 1 if ARCH_LS1046A
default 1 if ARCH_LS1088A
ifneq ($(CONFIG_ARCH_LS1088A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
endif
+
+ifneq ($(CONFIG_ARCH_LS1028A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
+endif
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+ CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#endif
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
+#endif
+#ifdef SYS_PCIE5_PHYS_ADDR
+ { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
+ SYS_PCIE5_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#endif
+#ifdef SYS_PCIE6_PHYS_ADDR
+ { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
+ SYS_PCIE6_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
#endif
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
CONFIG_SYS_FSL_WRIOP1_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
+#endif
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
CONFIG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
strcpy(name, "unknown");
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
final_map[i].virt = 0x2800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
+#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
case CONFIG_SYS_PCIE3_PHYS_ADDR:
final_map[i].phys = 0x3000000000ULL;
final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
+#endif
+#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
case CONFIG_SYS_PCIE4_PHYS_ADDR:
final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
+#endif
default:
break;
}
icache_enable();
dcache_enable();
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)
if (prio)
return ENVL_UNKNOWN;
-#ifdef CONFIG_CHAIN_OF_TRUST
- /* Check Boot Mode
- * If Boot Mode is Secure, return ENVL_NOWHERE
- */
- if (fsl_check_boot_mode_secure() == 1)
- goto done;
+#ifdef CONFIG_ENV_IS_NOWHERE
+ return env_loc;
#endif
switch (src) {
break;
}
-#ifdef CONFIG_CHAIN_OF_TRUST
-done:
-#endif
return env_loc;
}
#endif /* CONFIG_TFABOOT */
6. LS2088A
7. LS2081A
8. LX2160A
+ 9. LS1028A
LS1043A
---------
2)LX2080A, few difference w.r.t. LX2160A:
a) Eight 64-bit ARM v8 Cortex-A72 CPUs
+
+
+LS1028A
+--------
+The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with
+a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and
+a TSNenabled 4-port switch.
+
+The high performance Cortex-A72 cores, performing above 16,000 CoreMarks,
+combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and
+Octal/Quad SPI interfaces provide capabilities for a number of industrial and
+embedded applications. The device provides excellent integration with the
+new Time-Sensitive Networking standard, and enables a number of
+TSN applications.
+
+The LS1028A SoC includes the following function and features:
+ - Two 64-bit ARM v8 A72 CPUs
+ - Cache Coherent interconnect (CCI-400)
+ - One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC
+ - eDP/Displayport interface
+ - Graphics processing unit
+ - One Configurable x4 SerDes
+ - Ethernet interfaces
+ - Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one
+ ethernet MAC supporting 1G, 100M, 10M.
+ - Switched: TSN IP to support four 2.5/1G interfaces.
+ - None of the MACs support MACSEC
+ - Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII
+ - Support for 10G-SXGMII and 10G-QXGMII.
+ - Energy efficient Ethernet support (802.3az)
+ - IEEE 1588 support
+ - High-speed peripheral interfaces
+ - Two PCIe 3.0 controllers, one supporting x4 operation
+ - One serial ATA (SATA 3.0) controller
+ - Additional peripheral interfaces
+ - Two high-speed USB 2.0/3.0 controllers with integrated PHY each
+ supporting host or device modes
+ - Two Enhanced secure digital host controllers (SD/SDIO/eMMC)
+ - Two Serial peripheral interface (SPI) controllers
+ - Eight I2C controllers
+ - Two UART controllers
+ - Additional six Industrual UARTs (LPUART).
+ - One FlexSPI controller
+ - General Purpose IO (GPIO)
+ - Two CAN-FD interfaces
+ - Eight Flextimers with PWM I/O
+ - Support for hardware virtualization and partitioning enforcement
+ - Layerscape Trust Architecture
+ - Service Processor (SP) provides pre-boot initialization and secure-boot
+ capabilities
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+ u8 rcw_lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },
+ {0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },
+ {0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },
+ {0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },
+ {0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
+ {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
+ {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
+ {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
return readl(MC_ME_CS);
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define S32V234_IRAM_BASE 0x3e800000UL
#define S32V234_IRAM_SIZE 0x800000UL
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
{
return invalidate_dcache_range(start, stop);
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
}
#if defined(IMAGE_MAX_SIZE)
-ASSERT(__image_copy_end - __image_copy_start < (IMAGE_MAX_SIZE), \
+ASSERT(__image_copy_end - __image_copy_start <= (IMAGE_MAX_SIZE), \
"SPL image too big");
#endif
#if defined(CONFIG_SPL_BSS_MAX_SIZE)
-ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
+ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \
"SPL image BSS too big");
#endif
#if defined(CONFIG_SPL_MAX_FOOTPRINT)
-ASSERT(__bss_end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
+ASSERT(__bss_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \
"SPL image plus BSS too big");
#endif
dtb-$(CONFIG_ARCH_OWL) += \
bubblegum_96.dtb
-dtb-$(CONFIG_ARCH_ROCKCHIP) += \
- rk3036-sdk.dtb \
- rk3128-evb.dtb \
- rk3188-radxarock.dtb \
- rk3229-evb.dtb \
+dtb-$(CONFIG_ROCKCHIP_RK3036) += \
+ rk3036-sdk.dtb
+
+dtb-$(CONFIG_ROCKCHIP_RK3128) += \
+ rk3128-evb.dtb
+
+dtb-$(CONFIG_ROCKCHIP_RK3188) += \
+ rk3188-radxarock.dtb
+
+dtb-$(CONFIG_ROCKCHIP_RK322X) += \
+ rk3229-evb.dtb
+
+dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-evb.dtb \
rk3288-fennec.dtb \
rk3288-firefly.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-speedy.dtb \
- rk3288-vyasa.dtb \
- rk3328-evb.dtb \
- rk3399-ficus.dtb \
+ rk3288-vyasa.dtb
+
+dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ rk3328-evb.dtb
+
+dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-lion.dtb \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
+
+dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-evb.dtb \
+ rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
+ rk3399-nanopc-t4.dtb \
+ rk3399-nanopi-m4.dtb \
+ rk3399-nanopi-neo4.dtb \
+ rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
+ rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \
+ rk3399-rockpro64.dtb
+
+dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb
+
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-odroidc2.dtb \
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb \
- armada-xp-db-xc3-24g4xg.dtb
+ armada-xp-db-xc3-24g4xg.dtb \
+ armada-xp-crs305-1g-4s.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
am335x-evmsk.dtb \
am335x-bonegreen.dtb \
am335x-icev2.dtb \
+ am335x-pocketbeagle.dtb \
am335x-pxm50.dtb \
am335x-rut.dtb \
am335x-shc.dtb \
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
+ socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
fsl-ls1088a-qds.dtb \
+ fsl-ls1028a-rdb.dtb \
+ fsl-ls1028a-qds.dtb \
fsl-lx2160a-rdb.dtb \
fsl-lx2160a-qds.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN50I_H6) += \
+ sun50i-h6-beelink-gs1.dtb \
sun50i-h6-orangepi-lite2.dtb \
sun50i-h6-orangepi-one-plus.dtb \
sun50i-h6-pine-h64.dtb
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb \
sun50i-a64-pinebook.dtb \
- sun50i-a64-sopine-baseboard.dtb
+ sun50i-a64-sopine-baseboard.dtb \
+ sun50i-a64-teres-i.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb \
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
+ imx6ull-dart-6ul.dtb
dtb-$(CONFIG_ARCH_MX6) += \
imx6-colibri.dtb
imx7d-sdb-qspi.dtb \
imx7-colibri-emmc.dtb \
imx7-colibri-rawnand.dtb \
- imx7s-warp.dtb
+ imx7s-warp.dtb \
+ imx7d-pico-pi.dtb \
+ imx7d-pico-hobbit.dtb
+
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
-dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_IMX8) += \
+ fsl-imx8qxp-mek.dtb \
+ fsl-imx8qm-mek.dtb \
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb
+dtb-$(CONFIG_RZA1) += \
+ r7s72100-gr-peach-u-boot.dtb
+
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author: Robert Nelson <robertcnelson@gmail.com>
+ */
+
+/ {
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&dcdc2_reg>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+};
+
+&cpu0_opp_table {
+ /*
+ * Octavo Systems:
+ * The EFUSE_SMA register is not programmed for any of the AM335x wafers
+ * we get and we are not programming them during our production test.
+ * Therefore, from a DEVICE_ID revision point of view, the silicon looks
+ * like it is Revision 2.1. However, from an EFUSE_SMA point of view for
+ * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the
+ * EFUSE_SMA register reads as all zeros).
+ */
+ oppnitro-1000000000 {
+ opp-supported-hw = <0x06 0x0100>;
+ };
+};
+
+&am33xx_pinmux {
+ i2c0_pins: pinmux-i2c0-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
+ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+ >;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@24 {
+ reg = <0x24>;
+ };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+ interrupts = <7>; /* NMI */
+ interrupt-parent = <&intc>;
+
+ ti,pmic-shutdown-controller;
+
+ pwrbutton {
+ interrupts = <2>;
+ status = "okay";
+ };
+
+ regulators {
+ dcdc1_reg: regulator@0 {
+ regulator-name = "vdds_dpr";
+ regulator-always-on;
+ };
+
+ dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1351500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@3 {
+ regulator-name = "vio,vrtc,vdds";
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@4 {
+ regulator-name = "vdd_3v3aux";
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@5 {
+ regulator-name = "vdd_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@6 {
+ regulator-name = "vdd_3v3a";
+ regulator-always-on;
+ };
+ };
+};
+
+&aes {
+ status = "okay";
+};
+
+&sham {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author: Robert Nelson <robertcnelson@gmail.com>
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-osd335x-common.dtsi"
+
+/ {
+ model = "TI AM335x PocketBeagle";
+ compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usr_leds_pins>;
+
+ compatible = "gpio-leds";
+
+ usr0 {
+ label = "beaglebone:green:usr0";
+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ usr1 {
+ label = "beaglebone:green:usr1";
+ gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ usr2 {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+
+ usr3 {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ vmmcsd_fixed: fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&am33xx_pinmux {
+ i2c2_pins: pinmux-i2c2-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */
+ AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */
+ >;
+ };
+
+ ehrpwm0_pins: pinmux-ehrpwm0-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */
+ >;
+ };
+
+ ehrpwm1_pins: pinmux-ehrpwm1-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */
+ >;
+ };
+
+ mmc0_pins: pinmux-mmc0-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */
+ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
+ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
+ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
+ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
+ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
+ AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
+ AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */
+ >;
+ };
+
+ spi0_pins: pinmux-spi0-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
+ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
+ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
+ AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
+ >;
+ };
+
+ spi1_pins: pinmux-spi1-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */
+ AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */
+ AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */
+ AM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */
+ >;
+ };
+
+ usr_leds_pins: pinmux-usr-leds-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
+ AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
+ AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
+ AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
+ >;
+ };
+
+ uart0_pins: pinmux-uart0-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */
+ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */
+ >;
+ };
+
+ uart4_pins: pinmux-uart4-pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */
+ AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */
+ >;
+ };
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&ehrpwm0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ehrpwm0_pins>;
+};
+
+&epwmss1 {
+ status = "okay";
+};
+
+&ehrpwm1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ehrpwm1_pins>;
+};
+
+&i2c0 {
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&rtc {
+ system-power-controller;
+};
+
+&tscadc {
+ status = "okay";
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ ti,chan-step-avg = <16 16 16 16 16 16 16 16>;
+ ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>;
+ ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&cppi41dma {
+ status = "okay";
+};
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+ u-boot,dm-pre-reloc;
rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
u-boot,dm-spl;
};
};
+
+&sdhci {
+ u-boot,dm-spl;
+};
status = "okay";
u-boot,dm-spl;
};
+
+&sdhci {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&spi0 {
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for CRS305-1G-4S board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx3236.dtsi"
+#include "armada-xp-crs305-1g-4s-u-boot.dtsi"
+
+/ {
+ model = "CRS305-1G-4S";
+ compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
+ };
+};
+
+&L2 {
+ arm,parity-enable;
+ marvell,ecc-enable;
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ m25p,fast-read;
+
+ partition@u-boot {
+ reg = <0x00000000 0x00100000>;
+ label = "u-boot";
+ };
+ partition@u-boot-env {
+ reg = <0x00100000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition@unused {
+ reg = <0x00140000 0x00ec0000>;
+ label = "unused";
+ };
+
+ };
+};
/ {
model = "Siemens taurus";
- compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
+ compatible = "atmel,at91sam9g20", "atmel,at91sam9";
chosen {
u-boot,dm-pre-reloc;
clock-frequency = <18432000>;
};
};
+};
- ahb {
- apb {
- pinctrl@fffff400 {
- board {
- pinctrl_pck0_as_mck: pck0_as_mck {
- atmel,pins =
- <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */
- };
-
- };
- };
-
- dbgu: serial@fffff200 {
- u-boot,dm-pre-reloc;
- status = "okay";
- };
-
- usart0: serial@fffb0000 {
- pinctrl-0 =
- <&pinctrl_usart0
- &pinctrl_usart0_rts
- &pinctrl_usart0_cts
- &pinctrl_usart0_dtr_dsr
- &pinctrl_usart0_dcd
- &pinctrl_usart0_ri>;
- status = "okay";
- };
-
- usart1: serial@fffb4000 {
- status = "okay";
- };
-
- macb0: ethernet@fffc4000 {
- phy-mode = "rmii";
- status = "okay";
- };
-
- usb1: gadget@fffa4000 {
- atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- ssc0: ssc@fffbc000 {
- status = "okay";
- pinctrl-0 = <&pinctrl_ssc0_tx>;
- };
-
- spi0: spi@fffc8000 {
- cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
- mtd_dataflash@0 {
- compatible = "atmel,at45", "atmel,dataflash";
- spi-max-frequency = <50000000>;
- reg = <1>;
- };
- };
-
- rtc@fffffd20 {
- atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
- status = "okay";
- };
-
- watchdog@fffffd40 {
- timeout-sec = <15>;
- status = "okay";
- };
-
- gpbr: syscon@fffffd50 {
- status = "okay";
- };
- };
+&dbgu {
+ status = "okay";
+};
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
- status = "okay";
- };
+&gpbr {
+ status = "okay";
+};
+
+&macb0 {
+ phy-mode = "rmii";
+ status = "okay";
+};
- usb0: ohci@00500000 {
- num-ports = <2>;
- status = "okay";
+&nand0 {
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ status = "okay";
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+ board {
+ pinctrl_pck0_as_mck: pck0_as_mck {
+ atmel,pins =
+ /* PC1 periph B */
+ <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
+
};
};
+
+&rtc {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ status = "okay";
+};
+
+&spi0 {
+ cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
+ mtd_dataflash@0 {
+ compatible = "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ };
+};
+
+&ssc0 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_ssc0_tx>;
+};
+
+&usart0 {
+ pinctrl-0 =
+ <&pinctrl_usart0
+ &pinctrl_usart0_rts
+ &pinctrl_usart0_cts
+ &pinctrl_usart0_dtr_dsr
+ &pinctrl_usart0_dcd
+ &pinctrl_usart0_ri>;
+ status = "okay";
+};
+
+&usart1 {
+ status = "okay";
+};
+
+&usb0 {
+ num-ports = <2>;
+ status = "okay";
+};
+
+&usb1 {
+ atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&watchdog {
+ u-boot,dm-pre-reloc;
+ timeout-sec = <15>;
+ status = "okay";
+};
clock-frequency = <0xbebc200>;
u-boot,dm-pre-reloc;
};
+
+ refclk50mhz: refclk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
};
ubus {
wdt1: watchdog@ff800480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff800480 0x0 0x14>;
- clocks = <&periph_osc>;
+ clocks = <&refclk50mhz>;
};
wdt2: watchdog@ff8004c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff8004c0 0x0 0x14>;
- clocks = <&periph_osc>;
+ clocks = <&refclk50mhz>;
};
wdt-reboot {
clock-frequency = <200000000>;
u-boot,dm-pre-reloc;
};
+
+ refclk50mhz: refclk50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
};
ubus {
wdt1: watchdog@ff802780 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff802780 0x0 0x14>;
- clocks = <&periph_osc>;
+ clocks = <&refclk50mhz>;
};
wdt2: watchdog@ff8027c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff8027c0 0x0 0x14>;
- clocks = <&periph_osc>;
+ clocks = <&refclk50mhz>;
};
wdt-reboot {
power-domains = <&pd_dma>;
wakeup-irq = <225>;
};
+ pd_dma_lpuart1: PD_DMA_UART1 {
+ reg = <SC_R_UART_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpuart2: PD_DMA_UART2 {
+ reg = <SC_R_UART_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpuart3: PD_DMA_UART3 {
+ reg = <SC_R_UART_3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
};
};
status = "disabled";
};
+ lpuart1: serial@5a070000 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a070000 0x0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_UART1_CLK>,
+ <&clk IMX8QXP_UART1_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd_dma_lpuart1>;
+ status = "disabled";
+ };
+
+ lpuart2: serial@5a080000 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a080000 0x0 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_UART2_CLK>,
+ <&clk IMX8QXP_UART2_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd_dma_lpuart2>;
+ status = "disabled";
+ };
+
+ lpuart3: serial@5a090000 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a090000 0x0 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QXP_UART3_CLK>,
+ <&clk IMX8QXP_UART3_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd_dma_lpuart3>;
+ status = "disabled";
+ };
+
usdhc1: usdhc@5b010000 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
interrupt-parent = <&gic>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+ u-boot,dm-spl;
+};
+
+&pd_conn {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpio6 {
+ u-boot,dm-spl;
+};
+
+&gpio7 {
+ u-boot,dm-spl;
+};
+
+&lpuart0 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qm.dtsi"
+#include "fsl-imx8qm-mek-u-boot.dtsi"
+
+/ {
+ model = "Freescale i.MX8QM MEK";
+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+ chosen {
+ bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+ stdout-path = &lpuart0;
+ };
+
+ reg_usdhc2_vmmc: usdhc2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sw-3p3-sd1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <4800>;
+ enable-active-high;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx8qm-mek {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c
+ SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c
+ SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
+ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
+ SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061
+ SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
+ SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
+ SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061
+ SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061
+ SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061
+ SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
+ SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
+ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
+ SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061
+ SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061
+ >;
+ };
+
+ pinctrl_fec2: fec2grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
+ SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
+ SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
+ SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
+ SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
+ SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
+ SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
+ SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
+ SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
+ SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
+ SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
+ SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
+ SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
+ >;
+ };
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ SC_P_UART0_RX_DMA_UART0_RX 0x06000020
+ SC_P_UART0_TX_DMA_UART0_TX 0x06000020
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
+ SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
+ SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-txid";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ fsl,rgmii_rxc_dly;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ at803x,eee-disabled;
+ at803x,vddio-1p8v;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ at803x,eee-disabled;
+ at803x,vddio-1p8v;
+ status = "disabled";
+ };
+ };
+};
+
+&lpuart0 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "fsl-imx8-ca53.dtsi"
+#include <dt-bindings/clock/imx8qm-clock.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_pd.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "fsl,imx8qm";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
+ serial0 = &lpuart0;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ /* DRAM space - 1, size : 1 GB DRAM */
+ };
+
+ gic: interrupt-controller@51a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+ <0x0 0x51b00000 0 0xC0000>, /* GICR */
+ <0x0 0x52000000 0 0x2000>, /* GICC */
+ <0x0 0x52010000 0 0x1000>, /* GICH */
+ <0x0 0x52020000 0 0x20000>; /* GICV */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-parent = <&gic>;
+ };
+
+ mu: mu@5d1c0000 {
+ compatible = "fsl,imx8-mu";
+ reg = <0x0 0x5d1c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ fsl,scu_ap_mu_id = <0>;
+ status = "okay";
+
+ clk: clk {
+ compatible = "fsl,imx8qm-clk";
+ #clock-cells = <1>;
+ };
+
+ iomuxc: iomuxc {
+ compatible = "fsl,imx8qm-iomuxc";
+ };
+ };
+
+ imx8qm-pm {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_lsio: PD_LSIO {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_lsio_gpio0: PD_LSIO_GPIO_0 {
+ reg = <SC_R_GPIO_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio1: PD_LSIO_GPIO_1 {
+ reg = <SC_R_GPIO_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio2: PD_LSIO_GPIO_2 {
+ reg = <SC_R_GPIO_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio3: PD_LSIO_GPIO_3 {
+ reg = <SC_R_GPIO_3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio4: PD_LSIO_GPIO_4 {
+ reg = <SC_R_GPIO_4>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio5: PD_LSIO_GPIO_5{
+ reg = <SC_R_GPIO_5>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio6:PD_LSIO_GPIO_6 {
+ reg = <SC_R_GPIO_6>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ pd_lsio_gpio7: PD_LSIO_GPIO_7 {
+ reg = <SC_R_GPIO_7>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_lsio>;
+ };
+ };
+
+ pd_conn: PD_CONN {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_conn_sdch0: PD_CONN_SDHC_0 {
+ reg = <SC_R_SDHC_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_sdch1: PD_CONN_SDHC_1 {
+ reg = <SC_R_SDHC_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_sdch2: PD_CONN_SDHC_2 {
+ reg = <SC_R_SDHC_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ };
+ pd_conn_enet0: PD_CONN_ENET_0 {
+ reg = <SC_R_ENET_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ wakeup-irq = <258>;
+ };
+ pd_conn_enet1: PD_CONN_ENET_1 {
+ reg = <SC_R_ENET_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_conn>;
+ fsl,wakeup_irq = <262>;
+ };
+ };
+
+ pd_dma: PD_DMA {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_LAST>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_dma_lpi2c0: PD_DMA_I2C_0 {
+ reg = <SC_R_I2C_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpi2c1: PD_DMA_I2C_1 {
+ reg = <SC_R_I2C_1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpi2c2:PD_DMA_I2C_2 {
+ reg = <SC_R_I2C_2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpi2c3: PD_DMA_I2C_3 {
+ reg = <SC_R_I2C_3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpi2c4: PD_DMA_I2C_4 {
+ reg = <SC_R_I2C_4>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ };
+ pd_dma_lpuart0: PD_DMA_UART0 {
+ reg = <SC_R_UART_0>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ wakeup-irq = <345>;
+ };
+ };
+ };
+
+ gpio0: gpio@5d080000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d080000 0x0 0x10000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ power-domains = <&pd_lsio_gpio0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@5d090000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d090000 0x0 0x10000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ power-domains = <&pd_lsio_gpio1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@5d0a0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ power-domains = <&pd_lsio_gpio2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@5d0b0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ power-domains = <&pd_lsio_gpio3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@5d0c0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ power-domains = <&pd_lsio_gpio4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@5d0d0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0d0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ power-domains = <&pd_lsio_gpio5>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@5d0e0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ power-domains = <&pd_lsio_gpio6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio7: gpio@5d0f0000 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ reg = <0x0 0x5d0f0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ power-domains = <&pd_lsio_gpio7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ lpuart0: serial@5a060000 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a060000 0x0 0x1000>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QM_UART0_CLK>,
+ <&clk IMX8QM_UART0_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_UART0_CLK>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd_dma_lpuart0>;
+ status = "disabled";
+ };
+
+ usdhc1: usdhc@5b010000 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x5b010000 0x0 0x10000>;
+ clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
+ <&clk IMX8QM_SDHC0_CLK>,
+ <&clk IMX8QM_CLK_DUMMY>;
+ clock-names = "ipg", "per", "ahb";
+ assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
+ assigned-clock-rates = <400000000>;
+ power-domains = <&pd_conn_sdch0>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc@5b020000 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x5b020000 0x0 0x10000>;
+ clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
+ <&clk IMX8QM_SDHC1_CLK>,
+ <&clk IMX8QM_CLK_DUMMY>;
+ clock-names = "ipg", "per", "ahb";
+ assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
+ assigned-clock-rates = <200000000>;
+ power-domains = <&pd_conn_sdch1>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc3: usdhc@5b030000 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x5b030000 0x0 0x10000>;
+ clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
+ <&clk IMX8QM_SDHC2_CLK>,
+ <&clk IMX8QM_CLK_DUMMY>;
+ clock-names = "ipg", "per", "ahb";
+ assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
+ assigned-clock-rates = <200000000>;
+ power-domains = <&pd_conn_sdch2>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@5b040000 {
+ compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
+ reg = <0x0 0x5b040000 0x0 0x10000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QM_ENET0_IPG_CLK>,
+ <&clk IMX8QM_ENET0_AHB_CLK>,
+ <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
+ <&clk IMX8QM_ENET0_PTP_CLK>,
+ <&clk IMX8QM_ENET0_TX_CLK>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
+ "enet_2x_txclk";
+ assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
+ <&clk IMX8QM_ENET0_REF_DIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ fsl,wakeup_irq = <0>;
+ power-domains = <&pd_conn_enet0>;
+ status = "disabled";
+ };
+
+ fec2: ethernet@5b050000 {
+ compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
+ reg = <0x0 0x5b050000 0x0 0x10000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8QM_ENET1_IPG_CLK>,
+ <&clk IMX8QM_ENET1_AHB_CLK>,
+ <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
+ <&clk IMX8QM_ENET1_PTP_CLK>,
+ <&clk IMX8QM_ENET1_TX_CLK>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
+ "enet_2x_txclk";
+ assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
+ <&clk IMX8QM_ENET1_REF_DIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ fsl,wakeup_irq = <0>;
+ power-domains = <&pd_conn_enet1>;
+ status = "disabled";
+ };
+};
+
+&A53_0 {
+ clocks = <&clk IMX8QM_A53_DIV>;
+};
* Copyright 2018 NXP
*/
+&{/imx8qx-pm} {
+
+ u-boot,dm-spl;
+};
+
&mu {
u-boot,dm-spl;
};
sata: sata@3200000 {
compatible = "fsl,ls1012a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>;
+ reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+ 0x0 0x20140520 0x0 0x4>; /* ecc sata addr */
+ reg-names = "sata-base", "ecc-addr";
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028AQDS device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+ model = "NXP Layerscape 1028a QDS Board";
+ compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
+};
+
+&dspi0 {
+ status = "okay";
+};
+
+&dspi1 {
+ status = "okay";
+};
+
+&dspi2 {
+ status = "okay";
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028ARDB device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+ model = "NXP Layerscape 1028a RDB Board";
+ compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
+};
+
+&dspi0 {
+ status = "okay";
+};
+
+&dspi1 {
+ status = "okay";
+};
+
+&dspi2 {
+ status = "okay";
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP ls1028a SOC common device tree source
+ *
+ * Copyright 2019 NXP
+ *
+ */
+
+/ {
+ compatible = "fsl,ls1028a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ clockgen: clocking@1300000 {
+ compatible = "fsl,ls1028a-clockgen";
+ reg = <0x0 0x1300000 0x0 0xa0000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ memory@01080000 {
+ device_type = "memory";
+ reg = <0x00000000 0x01080000 0 0x80000000>;
+ /* DRAM space - 1, size : 2 GB DRAM */
+ };
+
+ gic: interrupt-controller@6000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+ <0x0 0x06040000 0 0x40000>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <1 9 0x4>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
+ <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
+ <1 11 0x8>, /* Virtual PPI, active-low */
+ <1 10 0x8>; /* Hypervisor PPI, active-low */
+ };
+
+ fspi: flexspi@20C0000 {
+ compatible = "nxp,dn-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20C0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>; /*64MB flash*/
+ reg-names = "FSPI", "FSPI-memory";
+ num-cs = <1>;
+ status = "disabled";
+ };
+
+ serial0: serial@21c0500 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ interrupts = <0 32 0x1>; /* edge triggered */
+ status = "disabled";
+ };
+
+ serial1: serial@21c0600 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ interrupts = <0 32 0x1>; /* edge triggered */
+ status = "disabled";
+ };
+
+ pcie@3400000 {
+ compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000
+ 0x00 0x03480000 0x0 0x40000 /* lut registers */
+ 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
+ 0x80 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000
+ 0x00 0x03580000 0x0 0x40000 /* lut registers */
+ 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
+ 0x88 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ i2c0: i2c@2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2040000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2040000 0x0 0x10000>;
+ interrupts = <0 74 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@2050000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2050000 0x0 0x10000>;
+ interrupts = <0 74 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@2060000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2060000 0x0 0x10000>;
+ interrupts = <0 75 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@2070000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2070000 0x0 0x10000>;
+ interrupts = <0 75 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ usb1: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 80 0x4>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ usb2: usb3@3110000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <0 81 0x4>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 26 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <5>;
+ litte-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi@2110000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <0 26 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <5>;
+ little-endian;
+ status = "disabled";
+ };
+
+ dspi2: dspi@2120000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2120000 0x0 0x10000>;
+ interrupts = <0 26 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <5>;
+ little-endian;
+ status = "disabled";
+ };
+
+ esdhc0: esdhc@2140000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>;
+ big-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc1: esdhc@2150000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2150000 0x0 0x10000>;
+ interrupts = <0 63 0x4>;
+ big-endian;
+ non-removable;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1028a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 133 4>;
+ clocks = <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ cluster1_core0_watchdog: wdt@c000000 {
+ compatible = "arm,sp805-wdt";
+ reg = <0x0 0xc000000 0x0 0x1000>;
+ };
+};
sata: sata@3200000 {
compatible = "fsl,ls1043a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>;
+ reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+ 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
+ reg-names = "sata-base", "ecc-addr";
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
sata: sata@3200000 {
compatible = "fsl,ls1046a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>;
+ reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+ 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
+ reg-names = "sata-base", "ecc-addr";
interrupts = <0 69 4>;
clocks = <&clockgen 4 1>;
status = "disabled";
sata: sata@3200000 {
compatible = "fsl,ls1088a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>;
+ reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+ 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
+ reg-names = "sata-base", "ecc-addr";
interrupts = <0 133 4>;
status = "disabled";
};
status = "disabled";
};
+
+ pcie@3400000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03480000 0x0 0x40000 /* LUT registers */
+ 0x00 0x034c0000 0x0 0x40000 /* PF control registers */
+ 0x80 0x00000000 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03580000 0x0 0x40000 /* LUT registers */
+ 0x00 0x035c0000 0x0 0x40000 /* PF control registers */
+ 0x88 0x00000000 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
+ };
+
+ pcie@3600000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03680000 0x0 0x40000 /* LUT registers */
+ 0x00 0x036c0000 0x0 0x40000 /* PF control registers */
+ 0x90 0x00000000 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
+ };
+
+ pcie@3700000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03780000 0x0 0x40000 /* LUT registers */
+ 0x00 0x037c0000 0x0 0x40000 /* PF control registers */
+ 0x98 0x00000000 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
+ };
+
+ pcie@3800000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03880000 0x0 0x40000 /* LUT registers */
+ 0x00 0x038c0000 0x0 0x40000 /* PF control registers */
+ 0xa0 0x00000000 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
+ };
+
+ pcie@3900000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03980000 0x0 0x40000 /* LUT registers */
+ 0x00 0x039c0000 0x0 0x40000 /* PF control registers */
+ 0xa8 0x00000000 0x0 0x1000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
+ };
};
chosen {
stdout-path = &uart2;
};
+
+ aliases {
+ mmc0 = &esdhc3;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usbh1_vbus: regulator-usbh1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbh1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+};
+
+&esdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
};
&fec {
pinctrl-0 = <&pinctrl_hog>;
imx53-kp {
+ pinctrl_esdhc3: esdhc3grp {
+ fsl,pins = <
+ MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d4
+ MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d4
+ MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d4
+ MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d4
+ MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d4
+ MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d4
+ MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d4
+ MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d4
+ MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1e4
+ MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d4
+ >;
+ };
+
pinctrl_eth: ethgrp {
fsl,pins = <
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
fsl,pins = <
/* PHY RESET */
MX53_PAD_PATA_DA_0__GPIO7_6 0x182
- /* VBUS_PWR_EN */
- MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
/* BOOSTER_OFF */
MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
/* LCD BACKLIGHT */
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
>;
};
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ /* VBUS_PWR_EN */
+ MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
+ >;
+ };
};
};
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ vbus-supply = <®_usbh1_vbus>;
+ status = "okay";
+};
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
+ ipu0 = &ipu;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
mmc2 = &esdhc3;
mmc3 = &esdhc4;
+ usb1 = &usbh1;
};
tzic: tz-interrupt-controller@fffc000 {
compatible = "simple-bus";
interrupt-parent = <&tzic>;
ranges;
+ u-boot,dm-pre-reloc;
aips@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
status = "disabled";
};
+ usbh1: usb@53f80200 {
+ compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+ reg = <0x53f80200 0x0200>;
+ interrupts = <14>;
+ clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
clks: ccm@53fd4000{
compatible = "fsl,imx53-ccm";
reg = <0x53fd4000 0x4000>;
status = "disabled";
};
};
+
+ ipu: ipu@18000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-ipu";
+ reg = <0x18000000 0x08000000>;
+ interrupts = <11 10>;
+ clocks = <&clks IMX5_CLK_IPU_GATE>,
+ <&clks IMX5_CLK_IPU_DI0_GATE>,
+ <&clks IMX5_CLK_IPU_DI1_GATE>;
+ clock-names = "bus", "di0", "di1";
+ resets = <&src 2>;
+ u-boot,dm-pre-reloc;
+
+ ipu_csi0: port@0 {
+ reg = <0>;
+ };
+
+ ipu_csi1: port@1 {
+ reg = <1>;
+ };
+
+ ipu_di0: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ ipu_di0_disp0: endpoint@0 {
+ reg = <0>;
+ };
+
+ ipu_di0_lvds0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+
+ ipu_di1: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ ipu_di1_disp1: endpoint@0 {
+ reg = <0>;
+ };
+
+ ipu_di1_lvds1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&lvds1_in>;
+ };
+
+ ipu_di1_tve: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tve_in>;
+ };
+ };
+ };
+
+ tve: tve@63ff0000 {
+ compatible = "fsl,imx53-tve";
+ reg = <0x63ff0000 0x1000>;
+ interrupts = <92>;
+ clocks = <&clks IMX5_CLK_TVE_GATE>,
+ <&clks IMX5_CLK_IPU_DI1_SEL>;
+ clock-names = "tve", "di_sel";
+ status = "disabled";
+
+ port {
+ tve_in: endpoint {
+ remote-endpoint = <&ipu_di1_tve>;
+ };
+ };
+ };
+
+ src: src@53fd0000 {
+ compatible = "fsl,imx53-src", "fsl,imx51-src";
+ reg = <0x53fd0000 0x4000>;
+ #reset-cells = <1>;
+ };
+
+ ldb: ldb@53fa8008 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-ldb";
+ reg = <0x53fa8008 0x4>;
+ gpr = <&gpr>;
+ clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
+ <&clks IMX5_CLK_LDB_DI1_SEL>,
+ <&clks IMX5_CLK_IPU_DI0_SEL>,
+ <&clks IMX5_CLK_IPU_DI1_SEL>,
+ <&clks IMX5_CLK_LDB_DI0_GATE>,
+ <&clks IMX5_CLK_LDB_DI1_GATE>;
+ clock-names = "di0_pll", "di1_pll",
+ "di0_sel", "di1_sel",
+ "di0", "di1";
+ status = "disabled";
+
+ lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lvds0_in: endpoint {
+ remote-endpoint = <&ipu_di0_lvds0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+ };
+
+ lvds-channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ status = "disabled";
+
+ port@1 {
+ reg = <1>;
+
+ lvds1_in: endpoint {
+ remote-endpoint = <&ipu_di1_lvds1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+ };
+ };
};
};
-/*
- * Copyright 2018 Logic PD, Inc.
- * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
/ {
keyboard {
debounce-interval = <10>;
wakeup-source;
};
+
btn3 {
gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
label = "btn3";
leds {
compatible = "gpio-leds";
- gen_led0 {
+ gen-led0 {
label = "led0";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led0>;
linux,default-trigger = "cpu0";
};
- gen_led1 {
+ gen-led1 {
label = "led1";
gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
};
- gen_led2 {
+ gen-led2 {
label = "led2";
gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- gen_led3 {
+ gen-led3 {
label = "led3";
gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
};
- reg_usb_otg_vbus: regulator-otg-vbus@0 {
+ reg_usb_otg_vbus: regulator-otg-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_otg>;
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
enable-active-high;
};
- reg_usb_h1_vbus: regulator-usbh1vbus@1 {
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
};
- reg_3v3: regulator-3v3@2 {
+ reg_3v3: regulator-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_3v3>;
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
enable-active-high;
regulator-always-on;
};
- reg_enet: regulator-ethernet@3 {
+ reg_enet: regulator-ethernet {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_pwr>;
+ pinctrl-0 = <&pinctrl_reg_enet>;
compatible = "regulator-fixed";
regulator-name = "ethernet-supply";
regulator-min-microvolt = <3300000>;
vin-supply = <&sw4_reg>;
};
- reg_audio: regulator-audio@4 {
+ reg_audio: regulator-audio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_audio>;
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
- regulator-always-on;
vin-supply = <®_3v3>;
};
- reg_hdmi: regulator-hdmi@5 {
+ reg_hdmi: regulator-hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_hdmi>;
compatible = "regulator-fixed";
vin-supply = <®_3v3>;
};
- reg_uart3: regulator-uart3@6 {
+ reg_uart3: regulator-uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_uart3>;
compatible = "regulator-fixed";
vin-supply = <®_3v3>;
};
- reg_1v8: regulator-1v8@7 {
+ reg_1v8: regulator-1v8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_1v8>;
compatible = "regulator-fixed";
vin-supply = <®_3v3>;
};
- reg_pcie: regulator@8 {
+ reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie_reg>;
- regulator-name = "MPCIE_3V3";
+ pinctrl-0 = <&pinctrl_reg_pcie>;
+ regulator-name = "mpcie_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
- mipi_pwr: regulator@9 {
+ reg_mipi: regulator-mipi {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mipi_pwr>;
+ pinctrl-0 = <&pinctrl_reg_mipi>;
regulator-name = "mipi_pwr_en";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
- audio-codec = <&codec>;
+ audio-codec = <&wm8962>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
status = "disabled";
};
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&usbh1 {
- vbus-supply = <®_usb_h1_vbus>;
- status = "okay";
-};
-
-&usbotg {
- vbus-supply = <®_usb_otg_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- disable-over-current;
- status = "okay";
-};
-
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
phy-supply = <®_enet>;
status = "okay";
};
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- no-1-8-v;
- keep-power-in-suspend;
- status = "okay";
-};
-
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
- codec: wm8962@1a {
+ wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
reg = <0x10>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
- DOVDD-supply = <&mipi_pwr>;
- AVDD-supply = <&mipi_pwr>;
- DVDD-supply = <&mipi_pwr>;
+ DOVDD-supply = <®_mipi>;
+ AVDD-supply = <®_mipi>;
+ DVDD-supply = <®_mipi>;
reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
};
};
+&ipu1_csi1_from_mipi_vc1 {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+};
+
&mipi_csi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
- status = "okay";
vpcie-supply = <®_pcie>;
- /* fsl,max-link-speed = <2>; */
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
};
&ssi2 {
status = "okay";
};
-&iomuxc {
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <®_3v3>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
>;
};
- pinctrl_i2c1: i2c1 {
+ pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
>;
};
- pinctrl_enet_pwr: enet_pwr {
+ pinctrl_enet: enetgrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
>;
};
- pinctrl_mipi_pwr: pwr_mipi {
- fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_led0: led0grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
};
pinctrl_ov5640: ov5640grp {
>;
};
- pinctrl_reg_hdmi: reg_hdmi {
+ pinctrl_pcf8574: pcf8575grp {
fsl,pins = <
- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
>;
};
- pinctrl_uart3: uart3grp {
+ pinctrl_pcie: pciegrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
- MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0
- >;
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
};
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
- >;
+ pinctrl_reg_1v8: reg1v8grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ >;
};
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
- >;
- };
-
- pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
- fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
- >;
+ pinctrl_reg_3v3: reg3v3grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
+ >;
};
- pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
+ pinctrl_reg_audio: reg-audiogrp {
fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
>;
};
- pinctrl_enet: enetgrp {
+ pinctrl_reg_enet: reg-enetgrp {
fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
>;
};
- pinctrl_reg_audio: audio-reg {
+ pinctrl_reg_hdmi: reg-hdmigrp {
fsl,pins = <
- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
>;
};
- pinctrl_pcie: pcie {
- fsl,pins = <
- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
- >;
+ pinctrl_reg_mipi: reg-mipigrp {
+ fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
};
- pinctrl_pcie_reg: pciereggrp {
+ pinctrl_reg_pcie: reg-pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
- pinctrl_pcf8574: pcf8575-pins {
+ pinctrl_reg_uart3: reguart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ >;
+ };
+
+ pinctrl_reg_usb_h1_vbus: usbh1grp {
fsl,pins = <
- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
- pinctrl_lcd: lcdgrp {
+ pinctrl_reg_usb_otg: reg-usb-otggrp {
fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */
- MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */
- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
- pinctrl_pwm3: pwm3grp {
+ pinctrl_uart3: uart3grp {
fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
>;
};
- pinctrl_reg_uart3: uart3reg {
+ pinctrl_usbotg: usbotggrp {
fsl,pins = <
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
>;
};
- pinctrl_reg_3v3: reg-3v3 {
+ pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
>;
};
- pinctrl_reg_1v8: reg-1v8 {
+ pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
fsl,pins = <
- MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
- pinctrl_led0: led0 {
+ pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
fsl,pins = <
- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
>;
};
+
};
-/*
- * Copyright 2018 Logic PD
- * This file is adapted from imx6qdl-sabresd.dtsi.
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
stdout-path = &uart1;
};
- memory {
+ memory@10000000 {
+ device_type = "memory";
reg = <0x10000000 0x80000000>;
};
};
};
-/* Reroute power feeding the CPU to come from the external PMIC */
-®_arm
-{
- vin-supply = <&sw1a_reg>;
-};
-
-®_soc
-{
- vin-supply = <&sw1c_reg>;
-};
-
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- status = "okay";
nand-on-flash-bbt;
+ status = "okay";
};
&i2c3 {
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
- pmic: pfuze100@08 {
+ pfuze100: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulator-max-microvolt = <3300000>;
regulator-name = "gen_3v3";
regulator-boot-on;
- /* regulator-always-on; */
};
sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-name = "sw3a_vddr";
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-name = "sw3b_vddr";
regulator-boot-on;
regulator-always-on;
vgen3_reg: vgen3 {
regulator-name = "gen_vadj_0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
};
vgen5_reg: vgen5 {
- regulator-name = "gen_adj_1";
- regulator-min-microvolt = <3300000>;
+ regulator-name = "gen_vadj_1";
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
- temp_sense0: tmp102@4a {
+ temperature-sensor@49 {
compatible = "ti,tmp102";
- reg = <0x4a>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tempsense>;
+ reg = <0x49>;
interrupt-parent = <&gpio6>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
- temp_sense1: tmp102@49 {
+ temperature-sensor@4a {
compatible = "ti,tmp102";
- reg = <0x49>;
+ reg = <0x4a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tempsense>;
interrupt-parent = <&gpio6>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
- mfg_eeprom: at24@51 {
+ eeprom@51 {
compatible = "atmel,24c64";
pagesize = <32>;
- read-only;
+ read-only; /* Manufacturing EEPROM programmed at factory */
reg = <0x51>;
};
- user_eeprom: at24@52 {
+ eeprom@52 {
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x52>;
};
};
+/* Reroute power feeding the CPU to come from the external PMIC */
+®_arm
+{
+ vin-supply = <&sw1a_reg>;
+};
+
+®_soc
+{
+ vin-supply = <&sw1c_reg>;
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
- pinctrl_hog: hoggrp {
+ pinctrl_gpmi_nand: gpmi-nandgrp {
fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = < /* Enable ARM Debugger */
MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
>;
};
- pinctrl_gpmi_nand: gpminandgrp {
+ pinctrl_i2c3: i2c3grp {
fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
- pinctrl_i2c3: i2c3grp {
+ pinctrl_tempsense: tempsensegrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */
>;
};
-
- pinctrl_tempsense: tempsensegrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */
- >;
- };
};
&snvs_poweroff {
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
uart-has-rtscts;
+ status = "okay";
+
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_usdhc1>;
non-removable;
keep-power-in-suspend;
- enable-sdio-wakeup;
- status = "okay";
+ wakeup-source;
vmmc-supply = <&sw2_reg>;
+ status = "okay";
};
&usdhc3 {
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <®_wl18xx_vmmc>;
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
+ status = "okay";
+
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>;
-/*
- * Copyright 2018 Logic PD, Inc.
- * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6-logicpd-baseboard.dtsi"
/ {
- model = "Logic PD i.MX6QD SOM-M3 (HDMI)";
+ model = "Logic PD i.MX6QD SOM-M3";
compatible = "fsl,imx6q";
- backlight: backlight_lvds {
+ backlight: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm3 0 20000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
power-supply = <®_lcd>;
};
+ panel-lvds0 {
+ compatible = "okaya,rs800480t-7x0gp";
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
reg_lcd: regulator-lcd {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_reg>;
startup-delay-us = <500000>;
};
- lcd_reset: lcd_reset {
+ reg_lcd_reset: regulator-lcd-reset {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_reset>;
compatible = "regulator-fixed";
regulator-always-on;
vin-supply = <®_lcd>;
};
+};
- panel-lvds0 {
- compatible = "ampire,am800480b3tmqw";
- backlight = <&backlight>;
-
- port {
- panel_in_lvds0: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
- };
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};
&hdmi {
status = "okay";
};
-&i2c1 {
- ili_touch: ilitouch@26 {
- compatible = "ili,ili2117a";
- reg = <0x26>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touchscreen>;
- interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
- ili2117a,poll-period = <10>;
- ili2117a,max-touch = <2>;
- };
-};
-
-®_hdmi {
- regulator-always-on;
-};
-
&ldb {
status = "okay";
port@4 {
reg = <4>;
-
lvds0_out: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
-&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
- <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
- <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
- <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
-};
-
&pwm3 {
status = "okay";
};
-&usdhc2 {
- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+®_hdmi {
+ regulator-always-on; /* Without this, the level shifter on HDMI doesn't turn on */
};
&iomuxc {
pinctrl_lcd_reset: lcdreset {
fsl,pins = <
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
>;
};
>;
};
};
-
/ {
aliases {
ipu1 = &ipu2;
+ video1 = &ipu2;
spi4 = &ecspi5;
};
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
power-domains = <&pd_pu>;
+ #cooling-cells = <2>;
};
ipu2: ipu@2800000 {
};
ipu2_di0: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <2>;
ipu2_di0_disp0: endpoint@0 {
};
ipu2_di1: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <3>;
ipu2_di1_hdmi: endpoint@1 {
i2c1 = &i2c2;
i2c2 = &i2c3;
ipu0 = &ipu1;
+ video0 = &ipu1;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2019 Toradex AG
*/
/dts-v1/;
/ {
model = "Toradex Colibri iMX6ULL";
- compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
+ compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
+
+ aliases {
+ mmc0 = &usdhc1;
+ usb0 = &usbotg1; /* required for ums */
+ };
chosen {
stdout-path = &uart1;
regulator-max-microvolt = <3300000>;
};
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
reg_sd1_vmmc: regulator-sd1-vmmc {
compatible = "regulator-gpio";
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1 3300000 0x0>;
vin-supply = <®_module_3v3>;
};
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
+ vin-supply = <®_5v0>;
+ };
};
&adc1 {
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};
+/* Ethernet */
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
};
};
+/* NAND */
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
+/*
+ * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
+ */
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
- sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
- scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
&i2c2 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
- sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
- scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
ad7879@2c {
&pinctrl_lcdif_ctrl>;
};
+/* PWM <A> */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
#pwm-cells = <3>;
};
+/* PWM <B> */
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
#pwm-cells = <3>;
};
+/* PWM <C> */
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
#pwm-cells = <3>;
};
+/* PWM <D> */
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
status = "disabled";
};
+/* Colibri UART_A */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
- fsl,uart-has-rtscts;
+ uart-has-rtscts;
fsl,dte-mode;
status = "okay";
};
+/* Colibri UART_B */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
- fsl,uart-has-rtscts;
+ uart-has-rtscts;
fsl,dte-mode;
};
+/* Colibri UART_C */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,dte-mode;
};
+/* Colibri USBC */
&usbotg1 {
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
+ status = "okay";
};
+/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
};
+/* Colibri MMC */
&usdhc1 {
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vmmc-supply = <®_sd1_vmmc>;
+ status = "okay";
};
&iomuxc {
+ pinctrl_can_int: canint-grp {
+ fsl,pins = <
+ /* SODIMM 73 */
+ MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14
+ >;
+ };
+
+ pinctrl_enet2: enet2-grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1-cs-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
+ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
+ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio_bl_on: gpio-bl-on-grp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
+ >;
+ };
+
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
>;
};
- pinctrl_can_int: canint-grp {
- fsl,pins = <
- MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */
- >;
- };
-
- pinctrl_enet2: enet2-grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
- >;
- };
-
- pinctrl_ecspi1_cs: ecspi1-cs-grp {
- fsl,pins = <
- MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
- >;
- };
-
- pinctrl_ecspi1: ecspi1-grp {
- fsl,pins = <
- MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
- MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
- MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
- >;
- };
-
- pinctrl_flexcan2: flexcan2-grp {
- fsl,pins = <
- MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
- MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
- >;
- };
-
- pinctrl_gpio_bl_on: gpio-bl-on-grp {
- fsl,pins = <
- MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
- >;
- };
-
pinctrl_gpmi_nand: gpmi-nand-grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
+
+ MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
>;
};
};
>;
};
- pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */
+ pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
>;
>;
};
};
-
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "imx6ull-dart-6ul.dtsi"
+
+/ {
+ model = "Variscite DART-6UL Evaluation Kit";
+ compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
+};
+
+&usdhc2 {
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1_id>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_usb_otg1_id: usbotg1idgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
+ >;
+ };
+
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ */
+
+/ {
+ model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
+ compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio1: mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <1>;
+ };
+ };
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio2: mdio2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <1>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ fsl,no-blockmark-swap;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0 0x400000>;
+ };
+
+ partition@400000 {
+ label = "uboot-env";
+ reg = <0x400000 0x100000>;
+ };
+
+ partition@500000 {
+ label = "root";
+ reg = <0x500000 0x0>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "cat,24c32";
+ reg = <0x50>;
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ #pwm-cells = <3>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ bus-width = <0x4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ keep-power-in-suspend;
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0X1b0b0
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1
+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
+ MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
+ MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2cgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1grp_gpio {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
+ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2cgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2grp_gpio {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
+ MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
+
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+ >;
+ };
+};
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
+#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 0x3 0x0
+
#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
-#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
#endif /* __DTS_IMX6ULL_PINFUNC_H */
spi4 = &ecspi4;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
};
cpus {
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2017 NXP
+
+#include "imx7d-pico.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX7D Board using Hobbit baseboard";
+ compatible = "technexion,imx7d-pico-hobbit", "fsl,imx7d";
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led {
+ label = "gpio-led";
+ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx7-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,cpu {
+ sound-dai = <&sai1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ };
+ };
+};
+
+&i2c1 {
+ sgtl5000: codec@a {
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ compatible = "fsl,sgtl5000";
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_vref_1v8>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ adc081c: adc@50 {
+ compatible = "ti,adc081c";
+ reg = <0x50>;
+ vref-supply = <®_3p3v>;
+ };
+};
+
+&ecspi3 {
+ ads7846@0 {
+ reg = <0>;
+ compatible = "ti,ads7846";
+ interrupt-parent = <&gpio2>;
+ interrupts = <7 0>;
+ spi-max-frequency = <1000000>;
+ pendown-gpio = <&gpio2 7 0>;
+ vcc-supply = <®_3p3v>;
+ ti,x-min = /bits/ 16 <0>;
+ ti,x-max = /bits/ 16 <4095>;
+ ti,y-min = /bits/ 16 <0>;
+ ti,y-max = /bits/ 16 <4095>;
+ ti,pressure-max = /bits/ 16 <1024>;
+ ti,x-plate-ohms = /bits/ 16 <90>;
+ ti,y-plate-ohms = /bits/ 16 <90>;
+ ti,debounce-max = /bits/ 16 <70>;
+ ti,debounce-tol = /bits/ 16 <3>;
+ ti,debounce-rep = /bits/ 16 <2>;
+ ti,settle-delay-usec = /bits/ 16 <150>;
+ wakeup-source;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
+ MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
+ MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
+ MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
+ MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
+ MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14
+ MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
+ >;
+ };
+};
\ No newline at end of file
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2017 NXP
+
+#include "imx7d-pico.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX7D Board and PI baseboard";
+ compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led {
+ label = "gpio-led";
+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx7-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,cpu {
+ sound-dai = <&sai1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ };
+ };
+};
+
+&i2c1 {
+ sgtl5000: codec@a {
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ compatible = "fsl,sgtl5000";
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_vref_1v8>;
+ };
+};
+
+&i2c4 {
+ polytouch: touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchscreen>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
+ MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
+ MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
+ MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
+ MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
+ MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14
+ MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14
+ >;
+ };
+
+ pinctrl_touchscreen: touchscreengrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14
+ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
+ >;
+ };
+
+};
\ No newline at end of file
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2017 NXP
+
+/dts-v1/;
+
+#include "imx7d.dtsi"
+
+
+/ {
+ aliases {
+ mmc0 = &usdhc3;
+ };
+
+ /* Will be filled by the bootloader */
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0>;
+ };
+
+ reg_wlreg_on: regulator-wlreg_on {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wlreg_on>;
+ regulator-name = "wlreg_on";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_pwr>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_vref_1v8: regulator-vref-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ usdhc2_pwrseq: usdhc2_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
+ clock-names = "ext_clock";
+ };
+};
+
+&clks {
+ assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
+ <&clks IMX7D_CLKO2_ROOT_DIV>;
+ assigned-clock-parents = <&clks IMX7D_CKIL>;
+ assigned-clock-rates = <0>, <32768>;
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ status = "okay";
+ };
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ pmic: pfuze3000@8 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1a {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+ /* use sw1c_reg to align with pfuze100/pfuze200 */
+ sw1c_reg: sw1b {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vldo2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vccsd {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: v33 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
+ <&clks IMX7D_SAI1_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+ assigned-clock-rates = <0>, <24576000>;
+ status = "okay";
+};
+
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 { /* Backlight */
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ status = "okay";
+};
+
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart7 { /* Bluetooth */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7>;
+ assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usb_otg2_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ tuning-step = <2>;
+ vmmc-supply = <®_3p3v>;
+ wakeup-source;
+ no-1-8-v;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&usdhc2 { /* Wifi SDIO */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
+ no-1-8-v;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_wlreg_on>;
+ mmc-pwrseq = <&usdhc2_pwrseq>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ no-1-8-v;
+ fsl,tuning-step = <2>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
+ MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
+ MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
+ MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
+ MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f
+ MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
+ MX7D_PAD_SD2_WP__ENET1_MDC 0x3
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+ MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
+ >;
+ };
+
+ pinctrl_can1: can1frp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
+ MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
+ >;
+ };
+
+ pinctrl_can2: can2frp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
+ MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
+ MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_pwm1: pwm1 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
+ >;
+ };
+
+ pinctrl_pwm2: pwm2 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
+ >;
+ };
+
+ pinctrl_pwm3: pwm3 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
+ >;
+ };
+
+ pinctrl_reg_wlreg_on: regregongrp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
+ MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
+ MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
+ MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
+ MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
+ >;
+ };
+
+ pinctrl_uart6: uart6grp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79
+ MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79
+ MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79
+ MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79
+ >;
+ };
+
+ pinctrl_uart7: uart7grp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79
+ MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79
+ MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79
+ MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79
+ >;
+ };
+
+ pinctrl_usbotg1_pwr: usbotg_pwr {
+ fsl,pins = <
+ MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_CMD__SD2_CMD 0x59
+ MX7D_PAD_SD2_CLK__SD2_CLK 0x19
+ MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
+ MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
+ MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
+ MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_wifi_clk: wificlkgrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
+ >;
+ };
+};
\ No newline at end of file
aliases {
mmc0 = &usdhc3;
+ usb0 = &usbotg1;
+ };
+
+ chosen {
+ stdout-path = &uart1;
};
gpio-keys {
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
-#include <dt-bindings/pinctrl/k3-am65.h>
+#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/dma/k3-udma.h>
/ {
u-boot,dm-spl;
main_uart0_pins_default: main_uart0_pins_default {
pinctrl-single,pins = <
- AM65X_IOPAD(0x01e4, PIN_INPUT | MUX_MODE0) /* (AF11) UART0_RXD */
- AM65X_IOPAD(0x01e8, PIN_OUTPUT | MUX_MODE0) /* (AE11) UART0_TXD */
- AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */
- AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */
+ AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
+ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
+ AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
+ AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
>;
u-boot,dm-spl;
};
main_mmc0_pins_default: main_mmc0_pins_default {
pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP | MUX_MODE0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP | MUX_MODE0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP | MUX_MODE0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP | MUX_MODE0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP | MUX_MODE0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP | MUX_MODE0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */
+ AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
+ AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
+ AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
+ AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
+ AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
+ AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
+ AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
+ AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
+ AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
+ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
+ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
u-boot,dm-spl;
};
main_mmc1_pins_default: main_mmc1_pins_default {
pinctrl-single,pins = <
- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (C27) MMC1_CLK */
- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP | MUX_MODE0) /* (C28) MMC1_CMD */
- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP | MUX_MODE0) /* (D28) MMC1_DAT0 */
- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP | MUX_MODE0) /* (E27) MMC1_DAT1 */
- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP | MUX_MODE0) /* (D26) MMC1_DAT2 */
- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP | MUX_MODE0) /* (D27) MMC1_DAT3 */
- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */
- AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */
+ AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
+ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
+ AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
+ AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
+ AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
+ AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
+ AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
+ AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
>;
u-boot,dm-spl;
};
};
&dmsc {
- mboxes= <&mcu_secproxy 7>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
u-boot,dm-spl;
wkup_uart0_pins_default: wkup_uart0_pins_default {
pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT | MUX_MODE0) /* (AB1) WKUP_UART0_RXD */
- AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT | MUX_MODE0) /* (AB5) WKUP_UART0_TXD */
- AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT | MUX_MODE1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT | MUX_MODE1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
>;
u-boot,dm-spl;
};
wkup_vtt_pins_default: wkup_vtt_pins_default {
pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP | MUX_MODE7) /* WKUP_GPIO0_28 */
+ AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
>;
u-boot,dm-spl;
};
interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
- wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
- cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */
+ wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
+ cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */
vmmc-supply = <&vmmc1>;
bus-width = <4>;
cap-power-off-card;
sata: sata@3200000 {
compatible = "fsl,ls1021a-ahci";
- reg = <0x3200000 0x10000>;
+ reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+ 0x0 0x20220520 0x0 0x4>; /* ecc sata addr*/
+ reg-names = "sata-base", "ecc-addr";
interrupts = <0 101 4>;
status = "disabled";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/ {
+ soc {
+ ethmac: ethernet@ff3f0000 {
+ compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.710",
+ "snps,dwmac";
+ reg = <0x0 0xff3f0000 0x0 0x10000
+ 0x0 0xff634540 0x0 0x8>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+ status = "disabled";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+ };
+
+ sd_emmc_a: sd@ffe03000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0xffe03000 0x0 0x800>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc CLKID_SD_EMMC_A>,
+ <&clkc CLKID_SD_EMMC_A_CLK0>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_A>;
+ };
+
+ sd_emmc_b: sd@ffe05000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0xffe05000 0x0 0x800>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc CLKID_SD_EMMC_B>,
+ <&clkc CLKID_SD_EMMC_B_CLK0>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_B>;
+ };
+
+ sd_emmc_c: mmc@ffe07000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0xffe07000 0x0 0x800>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc CLKID_SD_EMMC_C>,
+ <&clkc CLKID_SD_EMMC_C_CLK0>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_C>;
+ };
+ };
+};
+
+&periphs_pinctrl {
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "emmc_clk",
+ "emmc_cmd";
+ function = "emmc";
+ bias-pull-up;
+ };
+ };
+
+ emmc_ds_pins: emmc-ds {
+ mux {
+ groups = "emmc_nand_ds";
+ function = "emmc";
+ bias-pull-down;
+ };
+ };
+
+ emmc_clk_gate_pins: emmc_clk_gate {
+ mux {
+ groups = "BOOT_8";
+ function = "gpio_periphs";
+ bias-pull-down;
+ };
+ };
+
+ eth_leds_pins: eth-leds {
+ mux {
+ groups = "eth_link_led",
+ "eth_act_led";
+ function = "eth";
+ bias-disable;
+ };
+ };
+
+ eth_rmii_pins: eth-rmii {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_rgmii_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_txen",
+ "eth_txd0",
+ "eth_txd1";
+ function = "eth";
+ bias-disable;
+ };
+ };
+
+ eth_rgmii_pins: eth-rgmii {
+ mux {
+ groups = "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ bias-disable;
+ };
+ };
+
+ sdcard_c_pins: sdcard_c {
+ mux {
+ groups = "sdcard_d0_c",
+ "sdcard_d1_c",
+ "sdcard_d2_c",
+ "sdcard_d3_c",
+ "sdcard_cmd_c",
+ "sdcard_clk_c";
+ function = "sdcard";
+ bias-pull-up;
+ };
+ };
+
+ sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
+ mux {
+ groups = "GPIOC_4";
+ function = "gpio_periphs";
+ bias-pull-down;
+ };
+ };
+
+ sdcard_z_pins: sdcard_z {
+ mux {
+ groups = "sdcard_d0_z",
+ "sdcard_d1_z",
+ "sdcard_d2_z",
+ "sdcard_d3_z",
+ "sdcard_cmd_z",
+ "sdcard_clk_z";
+ function = "sdcard";
+ bias-pull-up;
+ };
+ };
+
+ sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
+ mux {
+ groups = "GPIOZ_6";
+ function = "gpio_periphs";
+ bias-pull-down;
+ };
+ };
+};
+
+&periphs {
+ eth_phy: mdio-multiplexer@4c000 {
+ compatible = "amlogic,g12a-mdio-mux";
+ reg = <0x0 0x4c000 0x0 0xa4>;
+ clocks = <&clkc CLKID_ETH_PHY>,
+ <&xtal>,
+ <&clkc CLKID_MPLL_5OM>;
+ clock-names = "pclk", "clkin0", "clkin1";
+ mdio-parent-bus = <&mdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ext_mdio: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ int_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_ephy: ethernet_phy@8 {
+ compatible = "ethernet-phy-id0180.3300",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <8>;
+ max-speed = <100>;
+
+ /* FIXME: Add irq support */
+ };
+ };
+ };
+};
+
+
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12a-u-boot.dtsi"
+
+ / {
+ aliases {
+ ethernet0 = ðmac;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_leds_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&internal_ephy>;
+ phy-mode = "rmii";
+};
+
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
/dts-v1/;
#include "meson-g12a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
/ {
compatible = "amlogic,u200", "amlogic,g12a";
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ main_12v: regulator-main_12v {
+ compatible = "regulator-fixed";
+ regulator-name = "12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ usb_pwr_en: regulator-usb_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_12v>;
+ regulator-always-on;
+ };
+
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
};
&uart_AO {
status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
};
+&usb {
+ status = "okay";
+ vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+ phy-supply = <&vcc_5v>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&vcc_5v>;
+};
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/g12a-clkc.h>
+#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
/ {
compatible = "amlogic,g12a";
};
};
+ efuse: efuse {
+ compatible = "amlogic,meson-gxbb-efuse";
+ clocks = <&clkc CLKID_EFUSE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
reg = <0x0 0x05000000 0x0 0x300000>;
no-map;
};
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x10000000>;
+ alignment = <0x0 0x400000>;
+ linux,cma-default;
+ };
+ };
+
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gxbb-sm";
};
soc {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
+ hdmi_tx: hdmi-tx@0 {
+ compatible = "amlogic,meson-g12a-dw-hdmi";
+ reg = <0x0 0x0 0x0 0x10000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
+ resets = <&reset RESET_HDMITX_CAPB3>,
+ <&reset RESET_HDMITX_PHY>,
+ <&reset RESET_HDMITX>;
+ reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+ clocks = <&clkc CLKID_HDMI>,
+ <&clkc CLKID_HTX_PCLK>,
+ <&clkc CLKID_VPU_INTR>;
+ clock-names = "isfr", "iahb", "venci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ /* VPU VENC Input */
+ hdmi_tx_venc_port: port@0 {
+ reg = <0>;
+
+ hdmi_tx_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+
+ /* TMDS Output */
+ hdmi_tx_tmds_port: port@1 {
+ reg = <1>;
+ };
+ };
+
periphs: bus@34400 {
compatible = "simple-bus";
reg = <0x0 0x34400 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
+
+ periphs_pinctrl: pinctrl@40 {
+ compatible = "amlogic,meson-g12a-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@40 {
+ reg = <0x0 0x40 0x0 0x4c>,
+ <0x0 0xe8 0x0 0x18>,
+ <0x0 0x120 0x0 0x18>,
+ <0x0 0x2c0 0x0 0x40>,
+ <0x0 0x340 0x0 0x1c>;
+ reg-names = "gpio",
+ "pull",
+ "pull-enable",
+ "mux",
+ "ds";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 0 86>;
+ };
+
+ cec_ao_a_h_pins: cec_ao_a_h {
+ mux {
+ groups = "cec_ao_a_h";
+ function = "cec_ao_a_h";
+ bias-disable;
+ };
+ };
+
+ cec_ao_b_h_pins: cec_ao_b_h {
+ mux {
+ groups = "cec_ao_b_h";
+ function = "cec_ao_b_h";
+ bias-disable;
+ };
+ };
+
+ hdmitx_ddc_pins: hdmitx_ddc {
+ mux {
+ groups = "hdmitx_sda",
+ "hdmitx_sck";
+ function = "hdmitx";
+ bias-disable;
+ };
+ };
+
+ hdmitx_hpd_pins: hdmitx_hpd {
+ mux {
+ groups = "hdmitx_hpd_in";
+ function = "hdmitx";
+ bias-disable;
+ };
+ };
+
+ uart_a_pins: uart-a {
+ mux {
+ groups = "uart_a_tx",
+ "uart_a_rx";
+ function = "uart_a";
+ bias-disable;
+ };
+ };
+
+ uart_a_cts_rts_pins: uart-a-cts-rts {
+ mux {
+ groups = "uart_a_cts",
+ "uart_a_rts";
+ function = "uart_a";
+ bias-disable;
+ };
+ };
+
+ uart_b_pins: uart-b {
+ mux {
+ groups = "uart_b_tx",
+ "uart_b_rx";
+ function = "uart_b";
+ bias-disable;
+ };
+ };
+
+ uart_c_pins: uart-c {
+ mux {
+ groups = "uart_c_tx",
+ "uart_c_rx";
+ function = "uart_c";
+ bias-disable;
+ };
+ };
+
+ uart_c_cts_rts_pins: uart-c-cts-rts {
+ mux {
+ groups = "uart_c_cts",
+ "uart_c_rts";
+ function = "uart_c";
+ bias-disable;
+ };
+ };
+ };
+ };
+
+ usb2_phy0: phy@36000 {
+ compatible = "amlogic,g12a-usb2-phy";
+ reg = <0x0 0x36000 0x0 0x2000>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ resets = <&reset RESET_USB_PHY20>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
+ dmc: bus@38000 {
+ compatible = "simple-bus";
+ reg = <0x0 0x38000 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
+
+ canvas: video-lut@48 {
+ compatible = "amlogic,canvas";
+ reg = <0x0 0x48 0x0 0x14>;
+ };
+ };
+
+ usb2_phy1: phy@3a000 {
+ compatible = "amlogic,g12a-usb2-phy";
+ reg = <0x0 0x3a000 0x0 0x2000>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ resets = <&reset RESET_USB_PHY21>;
+ reset-names = "phy";
+ #phy-cells = <0>;
};
hiu: bus@3c000 {
};
};
};
+
+ usb3_pcie_phy: phy@46000 {
+ compatible = "amlogic,g12a-usb3-pcie-phy";
+ reg = <0x0 0x46000 0x0 0x2000>;
+ clocks = <&clkc CLKID_PCIE_PLL>;
+ clock-names = "ref_clk";
+ resets = <&reset RESET_PCIE_PHY>;
+ reset-names = "phy";
+ assigned-clocks = <&clkc CLKID_PCIE_PLL>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <1>;
+ };
};
aobus: bus@ff800000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
+ rti: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x0 0x0 0x0 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
+
+ clkc_AO: clock-controller {
+ compatible = "amlogic,meson-g12a-aoclkc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "mpeg-clk";
+ };
+
+ pwrc_vpu: power-controller-vpu {
+ compatible = "amlogic,meson-g12a-pwrc-vpu";
+ #power-domain-cells = <0>;
+ amlogic,hhi-sysctrl = <&hhi>;
+ resets = <&reset RESET_VIU>,
+ <&reset RESET_VENC>,
+ <&reset RESET_VCBUS>,
+ <&reset RESET_BT656>,
+ <&reset RESET_RDMA>,
+ <&reset RESET_VENCI>,
+ <&reset RESET_VENCP>,
+ <&reset RESET_VDAC>,
+ <&reset RESET_VDI6>,
+ <&reset RESET_VENCL>,
+ <&reset RESET_VID_LOCK>;
+ clocks = <&clkc CLKID_VPU>,
+ <&clkc CLKID_VAPB>;
+ clock-names = "vpu", "vapb";
+ /*
+ * VPU clocking is provided by two identical clock paths
+ * VPU_0 and VPU_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ * Same for VAPB but with a final gate after the glitch free mux.
+ */
+ assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+ <&clkc CLKID_VPU_0>,
+ <&clkc CLKID_VPU>, /* Glitch free mux */
+ <&clkc CLKID_VAPB_0_SEL>,
+ <&clkc CLKID_VAPB_0>,
+ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_VPU_0>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_VAPB_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <666666666>,
+ <0>, /* Do Nothing */
+ <0>, /* Do Nothing */
+ <250000000>,
+ <0>; /* Do Nothing */
+ };
+
+ ao_pinctrl: pinctrl@14 {
+ compatible = "amlogic,meson-g12a-aobus-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio_ao: bank@14 {
+ reg = <0x0 0x14 0x0 0x8>,
+ <0x0 0x1c 0x0 0x8>,
+ <0x0 0x24 0x0 0x14>;
+ reg-names = "mux",
+ "ds",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ao_pinctrl 0 0 15>;
+ };
+
+ uart_ao_a_pins: uart-a-ao {
+ mux {
+ groups = "uart_ao_a_tx",
+ "uart_ao_a_rx";
+ function = "uart_ao_a";
+ bias-disable;
+ };
+ };
+
+ uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
+ mux {
+ groups = "uart_ao_a_cts",
+ "uart_ao_a_rts";
+ function = "uart_ao_a";
+ bias-disable;
+ };
+ };
+ };
+ };
+
+ cec_AO: cec@100 {
+ compatible = "amlogic,meson-gx-ao-cec";
+ reg = <0x0 0x00100 0x0 0x14>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_AO CLKID_AO_CEC>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
+ sec_AO: ao-secure@140 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x0 0x140 0x0 0x140>;
+ amlogic,has-chip-id;
+ };
+
+ cecb_AO: cec@280 {
+ compatible = "amlogic,meson-g12a-ao-cec";
+ reg = <0x0 0x00280 0x0 0x1c>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
+ clock-names = "oscin";
+ status = "disabled";
+ };
+
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ saradc: adc@9000 {
+ compatible = "amlogic,meson-g12a-saradc",
+ "amlogic,meson-saradc";
+ reg = <0x0 0x9000 0x0 0x48>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>,
+ <&clkc_AO CLKID_AO_SAR_ADC>,
+ <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
+ <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "adc_clk", "adc_sel";
+ status = "disabled";
+ };
+ };
+
+ vpu: vpu@ff900000 {
+ compatible = "amlogic,meson-g12a-vpu";
+ reg = <0x0 0xff900000 0x0 0x100000>,
+ <0x0 0xff63c000 0x0 0x1000>;
+ reg-names = "vpu", "hhi";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ amlogic,canvas = <&canvas>;
+ power-domains = <&pwrc_vpu>;
+
+ /* CVBS VDAC output port */
+ cvbs_vdac_port: port@0 {
+ reg = <0>;
+ };
+
+ /* HDMI-TX output port */
+ hdmi_tx_port: port@1 {
+ reg = <1>;
+
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_tx_in>;
+ };
+ };
};
gic: interrupt-controller@ffc01000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
+ reset: reset-controller@1004 {
+ compatible = "amlogic,meson-g12a-reset",
+ "amlogic,meson-axg-reset";
+ reg = <0x0 0x1004 0x0 0x9c>;
+ #reset-cells = <1>;
+ };
+
clk_msr: clock-measure@18000 {
compatible = "amlogic,meson-g12a-clk-measure";
reg = <0x0 0x18000 0x0 0x10>;
};
+
+ uart_C: serial@22000 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x22000 0x0 0x18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_B: serial@23000 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x23000 0x0 0x18>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_A: serial@24000 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x24000 0x0 0x18>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+ };
+
+ usb: usb@ffe09000 {
+ status = "disabled";
+ compatible = "amlogic,meson-g12a-usb-ctrl";
+ reg = <0x0 0xffe09000 0x0 0xa0>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc CLKID_USB>;
+ resets = <&reset RESET_USB>;
+
+ dr_mode = "otg";
+
+ phys = <&usb2_phy0>, <&usb2_phy1>,
+ <&usb3_pcie_phy PHY_TYPE_USB3>;
+ phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
+
+ dwc2: usb@ff400000 {
+ compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "ddr";
+ phys = <&usb2_phy1>;
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ };
+
+ dwc3: usb@ff500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff500000 0x0 0x100000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,dis_u2_susphy_quirk;
+ snps,quirk-frame-length-adjustment;
+ };
+ };
+
+ mali: gpu@ffe40000 {
+ compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
+ reg = <0x0 0xffe40000 0x0 0x40000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpu", "mmu", "job";
+ clocks = <&clkc CLKID_MALI>;
+ resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_MALI_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <800000000>,
+ <0>; /* Do Nothing */
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the GR Peach board
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include "r7s72100-gr-peach.dts"
+
+/ {
+ aliases {
+ spi0 = &rpc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+
+ leds {
+ led1 {
+ label = "peach:bottom:red";
+ };
+
+ led-red {
+ label = "peach:tri:red";
+ gpios = <&port6 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-green {
+ label = "peach:tri:green";
+ gpios = <&port6 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-blue {
+ label = "peach:tri:blue";
+ gpios = <&port6 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ rpc: rpc@0xee200000 {
+ compatible = "renesas,rpc-r7s72100", "renesas,rpc";
+ reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
+ bank-width = <2>;
+ num-cs = <1>;
+ status = "okay";
+ spi-max-frequency = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ status = "okay";
+ };
+ };
+};
+
+&ostm0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&scif2 {
+ u-boot,dm-pre-reloc;
+ clock = <66666666>; /* ToDo: Replace by DM clock driver */
+};
+
+&scif2_pins {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the GR-Peach board
+ *
+ * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ * Copyright (C) 2016 Renesas Electronics
+ */
+
+/dts-v1/;
+#include "r7s72100.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
+
+/ {
+ model = "GR-Peach";
+ compatible = "renesas,gr-peach", "renesas,r7s72100";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x00a00000>;
+ };
+
+ lbsc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ flash@18000000 {
+ compatible = "mtd-rom";
+ probe-type = "map_rom";
+ reg = <0x18000000 0x00800000>;
+ bank-width = <4>;
+ device-width = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ rootfs@600000 {
+ label = "rootfs";
+ reg = <0x00600000 0x00200000>;
+ };
+ };
+
+ leds {
+ status = "okay";
+ compatible = "gpio-leds";
+
+ led1 {
+ gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pinctrl {
+ scif2_pins: serial2 {
+ /* P6_2 as RxD2; P6_3 as TxD2 */
+ pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
+ };
+
+ ether_pins: ether {
+ /* Ethernet on Ports 1,3,5,10 */
+ pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
+ <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
+ <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
+ <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
+ <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
+ <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
+ <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
+ <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
+ <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
+ <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
+ <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
+ <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
+ <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
+ <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
+ <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
+ <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
+ <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
+ <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
+ };
+};
+
+&extal_clk {
+ clock-frequency = <13333000>;
+};
+
+&usb_x1_clk {
+ clock-frequency = <48000000>;
+};
+
+&mtu2 {
+ status = "okay";
+};
+
+&ostm0 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scif2_pins>;
+
+ status = "okay";
+};
+
+ðer {
+ pinctrl-names = "default";
+ pinctrl-0 = <ðer_pins>;
+
+ status = "okay";
+
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+
+ reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <5>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r7s72100 SoC
+ *
+ * Copyright (C) 2013-14 Renesas Solutions Corp.
+ * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
+ */
+
+#include <dt-bindings/clock/r7s72100-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "renesas,r7s72100";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &spi4;
+ };
+
+ /* Fixed factor clocks */
+ b_clk: b {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ clock-frequency = <400000000>;
+ clocks = <&cpg_clocks R7S72100_CLK_I>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ /* External clocks */
+ extal_clk: extal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ /* If clk present, value must be set by board */
+ clock-frequency = <0>;
+ };
+
+ p0_clk: p0 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+ clock-mult = <1>;
+ clock-div = <12>;
+ };
+
+ p1_clk: p1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+ clock-mult = <1>;
+ clock-div = <6>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ rtc_x1_clk: rtc_x1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ /* If clk present, value must be set by board to 32678 */
+ clock-frequency = <0>;
+ };
+
+ rtc_x3_clk: rtc_x3 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ /* If clk present, value must be set by board to 4000000 */
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ L2: cache-controller@3ffff000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x3ffff000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ arm,early-bresp-disable;
+ arm,full-line-zero-disable;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ scif0: serial@e8007000 {
+ compatible = "renesas,scif-r7s72100", "renesas,scif";
+ reg = <0xe8007000 64>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif1: serial@e8007800 {
+ compatible = "renesas,scif-r7s72100", "renesas,scif";
+ reg = <0xe8007800 64>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif2: serial@e8008000 {
+ compatible = "renesas,scif-r7s72100", "renesas,scif";
+ reg = <0xe8008000 64>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif3: serial@e8008800 {
+ compatible = "renesas,scif-r7s72100", "renesas,scif";
+ reg = <0xe8008800 64>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif4: serial@e8009000 {
+ compatible = "renesas,scif-r7s72100", "renesas,scif";
+ reg = <0xe8009000 64>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif5: serial@e8009800 {
+ compatible = "renesas,scif-r7s72100", "renesas,scif";
+ reg = <0xe8009800 64>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif6: serial@e800a000 {
+ compatible = "renesas,scif-r7s72100", "renesas,scif";
+ reg = <0xe800a000 64>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ scif7: serial@e800a800 {
+ compatible = "renesas,scif-r7s72100", "renesas,scif";
+ reg = <0xe800a800 64>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ spi0: spi@e800c800 {
+ compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+ reg = <0xe800c800 0x24>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+ power-domains = <&cpg_clocks>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@e800d000 {
+ compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+ reg = <0xe800d000 0x24>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+ power-domains = <&cpg_clocks>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@e800d800 {
+ compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+ reg = <0xe800d800 0x24>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+ power-domains = <&cpg_clocks>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@e800e000 {
+ compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+ reg = <0xe800e000 0x24>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+ power-domains = <&cpg_clocks>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@e800e800 {
+ compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+ reg = <0xe800e800 0x24>;
+ interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+ power-domains = <&cpg_clocks>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ usbhs0: usb@e8010000 {
+ compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
+ reg = <0xe8010000 0x1a0>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R7S72100_CLK_USB0>;
+ renesas,buswait = <4>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ usbhs1: usb@e8207000 {
+ compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
+ reg = <0xe8207000 0x1a0>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R7S72100_CLK_USB1>;
+ renesas,buswait = <4>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ mmcif: mmc@e804c800 {
+ compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
+ reg = <0xe804c800 0x80>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
+ power-domains = <&cpg_clocks>;
+ reg-io-width = <4>;
+ bus-width = <8>;
+ status = "disabled";
+ };
+
+ sdhi0: sd@e804e000 {
+ compatible = "renesas,sdhi-r7s72100";
+ reg = <0xe804e000 0x100>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
+ <&mstp12_clks R7S72100_CLK_SDHI01>;
+ clock-names = "core", "cd";
+ power-domains = <&cpg_clocks>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ status = "disabled";
+ };
+
+ sdhi1: sd@e804e800 {
+ compatible = "renesas,sdhi-r7s72100";
+ reg = <0xe804e800 0x100>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
+ <&mstp12_clks R7S72100_CLK_SDHI11>;
+ clock-names = "core", "cd";
+ power-domains = <&cpg_clocks>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@e8201000 {
+ compatible = "arm,pl390";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xe8201000 0x1000>,
+ <0xe8202000 0x1000>;
+ };
+
+ ether: ethernet@e8203000 {
+ compatible = "renesas,ether-r7s72100";
+ reg = <0xe8203000 0x800>,
+ <0xe8204800 0x200>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
+ phy-mode = "mii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ceu: camera@e8210000 {
+ reg = <0xe8210000 0x3000>;
+ compatible = "renesas,r7s72100-ceu";
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp6_clks R7S72100_CLK_CEU>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ wdt: watchdog@fcfe0000 {
+ compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
+ reg = <0xfcfe0000 0x6>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&p0_clk>;
+ };
+
+ /* Special CPG clocks */
+ cpg_clocks: cpg_clocks@fcfe0000 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-cpg-clocks",
+ "renesas,rz-cpg-clocks";
+ reg = <0xfcfe0000 0x18>;
+ clocks = <&extal_clk>, <&usb_x1_clk>;
+ clock-output-names = "pll", "i", "g";
+ #power-domain-cells = <0>;
+ };
+
+ /* MSTP clocks */
+ mstp3_clks: mstp3_clks@fcfe0420 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0420 4>;
+ clocks = <&p0_clk>;
+ clock-indices = <R7S72100_CLK_MTU2>;
+ clock-output-names = "mtu2";
+ };
+
+ mstp4_clks: mstp4_clks@fcfe0424 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0424 4>;
+ clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
+ <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+ clock-indices = <
+ R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
+ R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
+ >;
+ clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
+ };
+
+ mstp5_clks: mstp5_clks@fcfe0428 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0428 4>;
+ clocks = <&p0_clk>, <&p0_clk>;
+ clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
+ clock-output-names = "ostm0", "ostm1";
+ };
+
+ mstp6_clks: mstp6_clks@fcfe042c {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe042c 4>;
+ clocks = <&b_clk>, <&p0_clk>;
+ clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
+ clock-output-names = "ceu", "rtc";
+ };
+
+ mstp7_clks: mstp7_clks@fcfe0430 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0430 4>;
+ clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
+ clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
+ clock-output-names = "ether", "usb0", "usb1";
+ };
+
+ mstp8_clks: mstp8_clks@fcfe0434 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0434 4>;
+ clocks = <&p1_clk>;
+ clock-indices = <R7S72100_CLK_MMCIF>;
+ clock-output-names = "mmcif";
+ };
+
+ mstp9_clks: mstp9_clks@fcfe0438 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0438 4>;
+ clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
+ clock-indices = <
+ R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
+ >;
+ clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
+ };
+
+ mstp10_clks: mstp10_clks@fcfe043c {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe043c 4>;
+ clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
+ <&p1_clk>;
+ clock-indices = <
+ R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
+ R7S72100_CLK_SPI4
+ >;
+ clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
+ };
+ mstp12_clks: mstp12_clks@fcfe0444 {
+ #clock-cells = <1>;
+ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xfcfe0444 4>;
+ clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+ clock-indices = <
+ R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
+ R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
+ >;
+ clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
+ };
+
+ pinctrl: pin-controller@fcfe3000 {
+ compatible = "renesas,r7s72100-ports";
+
+ reg = <0xfcfe3000 0x4230>;
+
+ port0: gpio-0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 6>;
+ };
+
+ port1: gpio-1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ port2: gpio-2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ port3: gpio-3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ port4: gpio-4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ port5: gpio-5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 80 11>;
+ };
+
+ port6: gpio-6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ port7: gpio-7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ port8: gpio-8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ port9: gpio-9 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 144 8>;
+ };
+
+ port10: gpio-10 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 160 16>;
+ };
+
+ port11: gpio-11 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 176 16>;
+ };
+ };
+
+ ostm0: timer@fcfec000 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec000 0x30>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ ostm1: timer@fcfec400 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec400 0x30>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@fcfee000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+ reg = <0xfcfee000 0x44>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
+ clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@fcfee400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+ reg = <0xfcfee400 0x44>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
+ clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@fcfee800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+ reg = <0xfcfee800 0x44>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
+ clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fcfeec00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+ reg = <0xfcfeec00 0x44>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
+ clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ mtu2: timer@fcff0000 {
+ compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+ reg = <0xfcff0000 0x400>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tgi0a";
+ clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+
+ rtc: rtc@fcff1000 {
+ compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
+ reg = <0xfcff1000 0x2e>;
+ interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "alarm", "period", "carry";
+ clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
+ <&rtc_x3_clk>, <&extal_clk>;
+ clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
+ };
+
+ usb_x1_clk: usb_x1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ /* If clk present, value must be set by board */
+ clock-frequency = <0>;
+ };
+};
};
&uart2 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
regulator-boot-on;
vin-supply = <&vcc18_wl>;
};
+
+ sound {
+ compatible = "rockchip,audio-max98090-jerry";
+
+ cpu {
+ sound-dai = <&i2s 0>;
+ };
+
+ codec {
+ sound-dai = <&max98090 0>;
+ };
+ };
};
&backlight {
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
+/ {
+ chosen {
+ u-boot,spl-boot-order = &emmc;
+ tick-timer = "/timer@ff810000";
+ };
+};
+
+&dmc {
+ u-boot,dm-pre-reloc;
+
+ /*
+ * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
+ * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
+ * details on the 'rockchip,memory-schedule' property and how it
+ * affects the physical-address to device-address mapping.
+ */
+ rockchip,memory-schedule = <DMC_MSCH_CBRD>;
+ rockchip,ddr-frequency = <800000000>;
+ rockchip,ddr-speed-bin = <DDR3_1600K>;
+
+ status = "okay";
+};
&pinctrl {
u-boot,dm-pre-reloc;
u-boot,dm-pre-reloc;
};
+&sgrf {
+ u-boot,dm-pre-reloc;
+};
+
&cru {
u-boot,dm-pre-reloc;
};
&uart4 {
u-boot,dm-pre-reloc;
};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <24000000>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
-#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
/ {
model = "Rockchip RK3399 Evaluation Board";
};
&sdmmc {
- u-boot,dm-pre-reloc;
bus-width = <4>;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-sdram-ddr3-1600.dtsi"
/dts-v1/;
#include "rk3399-rock960.dtsi"
-#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "96boards RK3399 Ficus";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-ddr3-1600.dtsi"
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
-#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
model = "Firefly-RK3399 Board";
};
&sdmmc {
- u-boot,dm-pre-reloc;
bus-width = <4>;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-gru-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
/dts-v1/;
#include "rk3399-gru-chromebook.dtsi"
-#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
/ {
model = "Google Bob";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
&spi1 {
status = "okay";
- u-boot,dm-pre-reloc;
pinctrl-names = "default", "sleep";
pinctrl-1 = <&spi1_sleep>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPC-T4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPC-T4";
+ compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
+
+ vcc12v0_sys: vcc12v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <12000000>;
+ regulator-min-microvolt = <12000000>;
+ regulator-name = "vcc12v0_sys";
+ };
+
+ vcc5v0_host0: vcc5v0-host0 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc5v0_host0";
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_rx>;
+ };
+};
+
+&pinctrl {
+ ir {
+ ir_rx: ir-rx {
+ /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */
+ rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdhci {
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+&u2phy0_host {
+ phy-supply = <&vcc5v0_host0>;
+};
+
+&u2phy1_host {
+ phy-supply = <&vcc5v0_host0>;
+};
+
+&vcc5v0_sys {
+ vin-supply = <&vcc12v0_sys>;
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc12v0_sys>;
+};
+
+&vbus_typec {
+ enable-active-high;
+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_sys>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * FriendlyElec NanoPi M4 board device tree source
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi M4";
+ compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_core: vcc5v0-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_core";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
+
+ vcc5v0_usb1: vcc5v0-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb2: vcc5v0-usb2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb2";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_core>;
+};
+
+&u2phy0_host {
+ phy-supply = <&vcc5v0_usb1>;
+};
+
+&u2phy1_host {
+ phy-supply = <&vcc5v0_usb2>;
+};
+
+&vbus_typec {
+ regulator-always-on;
+ vin-supply = <&vdd_5v>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi NEO4";
+ compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc5v0_core: vcc5v0-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_core";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
+
+ vcc5v0_usb1: vcc5v0-usb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb1";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_core>;
+};
+
+&u2phy0_host {
+ phy-supply = <&vcc5v0_usb1>;
+};
+
+&vbus_typec {
+ regulator-always-on;
+ vin-supply = <&vdd_5v>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+
+&sdmmc {
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * RK3399-based FriendlyElec boards device tree source
+ *
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sys";
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc5v0_sys";
+ vin-supply = <&vdd_5v>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_s3";
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v0_sd: vcc3v0-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_pwr_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc3v0_sd";
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vbus_typec: vbus-typec {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vbus_typec";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_key>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_gpio>;
+
+ status {
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ label = "status_led";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clock-parents = <&clkin_gmac>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc3v3_s3>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpu_b_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu_b";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpu_sleep>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_gpu";
+ regulator-ramp-delay = <1000>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ clock-output-names = "xin32k", "rtc_clko_wifi";
+ #clock-cells = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_3v0>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_center";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_cpu_l";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_cam: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_cam";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_touch: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc3v0_touch";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmupll: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmupll";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <3000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_sdio";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcca3v0_codec";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc_1v5";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_codec";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc_3v0";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s3";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <200000>;
+ i2c-scl-rising-time-ns = <150>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <160>;
+ i2c-scl-falling-time-ns = <30>;
+ status = "okay";
+
+ fusb0: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ vbus-supply = <&vbus_typec>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&io_domains {
+ bt656-supply = <&vcc_1v8>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vcc_sdio>;
+ gpio1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pcie_phy {
+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+ assigned-clock-rates = <100000000>;
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+ max-link-speed = <2>;
+ num-lanes = <4>;
+ status = "okay";
+};
+
+&pinctrl {
+ fusb30x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ gpio-leds {
+ leds_gpio: leds-gpio {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ cpu_b_sleep: cpu-b-sleep {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ gpu_sleep: gpu-sleep {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ power_key: power-key {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio {
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_reg_on_h: bt-reg-on-h {
+ /* external pullup to VCC1V8_PMUPLL */
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_reg_on_h: wifi-reg_on-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc0_det_l: sdmmc0-det-l {
+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ sdmmc0_pwr_h: sdmmc0-pwr-h {
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2_pin_pull_down>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v0_sd>;
+ vqmmc-supply = <&vcc_sdio>;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_host {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_host {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ max-speed = <4000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/ {
+ cluster0_opp: opp-table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <850000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <925000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cluster1_opp: opp-table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1200000>;
+ };
+ };
+
+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <800000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <297000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <925000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1100000>;
+ };
+ };
+};
+
+&cpu_l0 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l1 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l2 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l3 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_b0 {
+ operating-points-v2 = <&cluster1_opp>;
+};
+
+&cpu_b1 {
+ operating-points-v2 = <&cluster1_opp>;
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-ddr3-1333.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "dt-bindings/pwm/pwm.h"
+#include "dt-bindings/input/input.h"
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Orange Pi RK3399 Board";
+ compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <100000>;
+ };
+
+ button-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <300000>;
+ };
+
+ back {
+ label = "Back";
+ linux,code = <KEY_BACK>;
+ press-threshold-microvolt = <985000>;
+ };
+
+ menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <1314000>;
+ };
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ linux,input-type = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_btn>;
+ wakeup-source;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v0_sd: vcc3v0-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_pwr_h>;
+ regulator-boot-on;
+ regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <3000000>;
+ regulator-name = "vcc3v0_sd";
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc5v0_typec0: vcc5v0-typec0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_typec0_en>;
+ regulator-name = "vcc5v0_typec0";
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ vin-supply = <&vcc_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc3v3_s3>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ status = "okay";
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ vcc10-supply = <&vcc3v3_sys>;
+ vcc11-supply = <&vcc3v3_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_3v0>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG1 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_tp: LDO_REG2 {
+ regulator-name = "vcc3v0_tp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmupll: LDO_REG3 {
+ regulator-name = "vcc1v8_pmupll";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-name = "vcc_sdio";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-name = "vcca1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+
+ ak09911@c {
+ compatible = "asahi-kasei,ak09911";
+ reg = <0x0c>;
+ vdd-supply = <&vcc3v3_s3>;
+ };
+
+ mpu6500@68 {
+ compatible = "invensense,mpu6500";
+ reg = <0x68>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsensor_int_l>;
+ vddio-supply = <&vcc3v3_s3>;
+ };
+
+ lsm6ds3@6a {
+ compatible = "st,lsm6ds3";
+ reg = <0x6a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gyr_int_l>;
+ vdd-supply = <&vcc3v3_s3>;
+ vddio-supply = <&vcc3v3_s3>;
+ };
+
+ cm32181@10 {
+ compatible = "capella,cm32181";
+ reg = <0x10>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&light_int_l>;
+ vdd-supply = <&vcc3v3_s3>;
+ };
+};
+
+&io_domains {
+ status = "okay";
+ bt656-supply = <&vcc_3v0>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vcc_sdio>;
+ gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+ buttons {
+ pwr_btn: pwr-btn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sd {
+ sdmmc0_pwr_h: sdmmc0-pwr-h {
+ rockchip,pins =
+ <RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins =
+ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_typec0_en: vcc5v0-typec0-en {
+ rockchip,pins =
+ <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_reg_on_h: wifi-reg-on-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_host_wake_l: wifi-host-wake-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ bluetooth {
+ bt_reg_on_h: bt-enable-h {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ mpu6500 {
+ gsensor_int_l: gsensor-int-l {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ lsm6ds3 {
+ gyr_int_l: gyr-int-l {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ cm32181 {
+ light_int_l: light-int-l {
+ rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ clock-frequency = <50000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <50000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_l>;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ clock-frequency = <150000000>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ vmmc-supply = <&vcc3v0_sd>;
+ vqmmc-supply = <&vcc_sdio>;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ phy-supply = <&vcc5v0_typec0>;
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
/dts-v1/;
#include "rk3399-puma.dtsi"
+#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
};
&sdmmc {
- u-boot,dm-pre-reloc;
clock-frequency = <150000000>;
max-frequency = <40000000>;
supports-sd;
&spi1 {
- u-boot,dm-pre-reloc;
-
status = "okay";
#address-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
+ * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi 4";
+ compatible = "radxa,rockpi4", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc12v_dcin: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwr_en>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_typec: vcc5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_typec_en>;
+ regulator-name = "vcc5v0_typec";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_lan: vcc3v3-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_lan";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc5v0_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_codec: LDO_REG1 {
+ regulator-name = "vcc1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_hdmi: LDO_REG2 {
+ regulator-name = "vcc1v8_hdmi";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8: LDO_REG3 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-name = "vcc_sdio";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcc0v9_hdmi: LDO_REG7 {
+ regulator-name = "vcc0v9_hdmi";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc_cam: SWITCH_REG1 {
+ regulator-name = "vcc_cam";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_mipi: SWITCH_REG2 {
+ regulator-name = "vcc_mipi";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel1_gpio>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel2_gpio>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-rising-time-ns = <300>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+};
+
+&i2s0 {
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ status = "okay";
+};
+
+&i2s1 {
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ bt656-supply = <&vcc_3v0>;
+ audio-supply = <&vcc_3v0>;
+ sdmmc-supply = <&vcc_sdio>;
+ gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+ status = "okay";
+
+ pmu1830-supply = <&vcc_3v0>;
+};
+
+&pinctrl {
+ pcie {
+ pcie_pwr_en: pcie-pwr-en {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ vsel1_gpio: vsel1-gpio {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ vsel2_gpio: vsel2-gpio {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ usb-typec {
+ vcc5v0_typec_en: vcc5v0-typec-en {
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+
+ vref-supply = <&vcc_1v8>;
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
/dts-v1/;
#include "rk3399-rock960.dtsi"
-#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
/ {
model = "96boards Rock960";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Pine64 RockPro64";
+ compatible = "pine64,rockpro64", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwrbtn>;
+
+ power {
+ debounce-interval = <100>;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Key Power";
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
+
+ work-led {
+ label = "work";
+ default-state = "on";
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ };
+
+ diy-led {
+ label = "diy";
+ default-state = "off";
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ /* switched by pmic_sleep */
+ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwr_en>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_typec: vcc5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_typec_en>;
+ regulator-name = "vcc5v0_typec";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vdd_log: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <168>;
+ i2c-scl-falling-time-ns = <4>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc5v0_sys>;
+ vcc12-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca_1v8>;
+
+ regulators {
+ vdd_center: DCDC_REG1 {
+ regulator-name = "vdd_center";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_l: DCDC_REG2 {
+ regulator-name = "vdd_cpu_l";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG1 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v0_touch: LDO_REG2 {
+ regulator-name = "vcc3v0_touch";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8: LDO_REG3 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_sdio: LDO_REG4 {
+ regulator-name = "vcc_sdio";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG5 {
+ regulator-name = "vcca3v0_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v5: LDO_REG6 {
+ regulator-name = "vcc_1v5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG7 {
+ regulator-name = "vcca1v8_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v0: LDO_REG8 {
+ regulator-name = "vcc_3v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+ regulator-name = "vcc3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_s0: SWITCH_REG2 {
+ regulator-name = "vcc3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu_b: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel1_gpio>;
+ regulator-name = "vdd_cpu_b";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: regulator@41 {
+ compatible = "silergy,syr828";
+ reg = <0x41>;
+ fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsel2_gpio>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c1 {
+ i2c-scl-rising-time-ns = <300>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ fusb0: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ vbus-supply = <&vcc5v0_typec>;
+ status = "okay";
+ };
+};
+
+&i2s0 {
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <8>;
+ status = "okay";
+};
+
+&i2s1 {
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ status = "okay";
+};
+
+&i2s2 {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ bt656-supply = <&vcc1v8_dvp>;
+ audio-supply = <&vcca1v8_codec>;
+ sdmmc-supply = <&vcc_sdio>;
+ gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+ pmu1830-supply = <&vcc_3v0>;
+ status = "okay";
+};
+
+&pinctrl {
+ buttons {
+ pwrbtn: pwrbtn {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ fusb302x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ work_led_gpio: work_led-gpio {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_gpio: diy_led-gpio {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_pwr_en: pcie-pwr-en {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ vsel1_gpio: vsel1-gpio {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ vsel2_gpio: vsel2-gpio {
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-typec {
+ vcc5v0_typec_en: vcc5v0_typec_en {
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb2 {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca1v8_s3>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_otg: otg-port {
+ status = "okay";
+ };
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&spi1 {
+ u-boot,dm-pre-reloc;
+};
rockchip,pins =
<1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
};
+
+ pwm2_pin_pull_down: pwm2-pin-pull-down {
+ rockchip,pins =
+ <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
+ };
};
pwm3a {
reg = <0x1>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- txen-skew-ps = <800>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <400>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <400>;
- rxd1-skew-ps = <400>;
- rxd2-skew-ps = <400>;
- rxd3-skew-ps = <400>;
+ txen-skew-ps = <480>;
+ txc-skew-ps = <1800>;
+ rxdv-skew-ps = <240>;
+ rxc-skew-ps = <1800>;
+ rxd0-skew-ps = <240>;
+ rxd1-skew-ps = <240>;
+ rxd2-skew-ps = <240>;
+ rxd3-skew-ps = <240>;
};
ethernet-phy@7 {
reg = <0x7>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- txen-skew-ps = <800>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <400>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <400>;
- rxd1-skew-ps = <400>;
- rxd2-skew-ps = <400>;
- rxd3-skew-ps = <400>;
+ txen-skew-ps = <480>;
+ txc-skew-ps = <1800>;
+ rxdv-skew-ps = <240>;
+ rxc-skew-ps = <1800>;
+ rxd0-skew-ps = <240>;
+ rxd1-skew-ps = <240>;
+ rxd2-skew-ps = <240>;
+ rxd3-skew-ps = <240>;
};
};
};
reg = <0x1>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- txen-skew-ps = <800>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <400>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <400>;
- rxd1-skew-ps = <400>;
- rxd2-skew-ps = <400>;
- rxd3-skew-ps = <400>;
+ txen-skew-ps = <480>;
+ txc-skew-ps = <1800>;
+ rxdv-skew-ps = <240>;
+ rxc-skew-ps = <1800>;
+ rxd0-skew-ps = <240>;
+ rxd1-skew-ps = <240>;
+ rxd2-skew-ps = <240>;
+ rxd3-skew-ps = <240>;
};
ethernet-phy@7 {
reg = <0x7>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- txen-skew-ps = <800>;
- txc-skew-ps = <3000>;
- rxdv-skew-ps = <400>;
- rxc-skew-ps = <3000>;
- rxd0-skew-ps = <400>;
- rxd1-skew-ps = <400>;
- rxd2-skew-ps = <400>;
- rxd3-skew-ps = <400>;
+ txen-skew-ps = <480>;
+ txc-skew-ps = <1800>;
+ rxdv-skew-ps = <240>;
+ rxc-skew-ps = <1800>;
+ rxd0-skew-ps = <240>;
+ rxd1-skew-ps = <240>;
+ rxd2-skew-ps = <240>;
+ rxd3-skew-ps = <240>;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/ {
+ chosen {
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ u-boot,dm-pre-reloc;
+
+ altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clock_manager@0xffd04000 {
+ u-boot,dm-pre-reloc;
+
+ mainpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ perpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ pinmux@0xffd07000 {
+ u-boot,dm-pre-reloc;
+
+ shared {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpga {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ noc@0xffd10000 {
+ u-boot,dm-pre-reloc;
+
+ firewall {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ fpgabridge@0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@2 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@3 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@4 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@5 {
+ u-boot,dm-pre-reloc;
+ };
+};
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+
+#include "socfpga_arria10.dtsi"
/ {
model = "Altera SOCFPGA Arria 10";
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = <&fs_loader0>;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc 1>;
+ };
+};
+
+&fpga_mgr {
+ u-boot,dm-pre-reloc;
+ altr,bitstream = "fit_spl_fpga.itb";
+};
&mmc {
u-boot,dm-pre-reloc;
*</auto-generated>
*/
-#include "socfpga_arria10.dtsi"
-
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
- chosen {
- cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */
- };
-
/* Clock sources */
clocks {
- u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
/* Clock source: altera_arria10_hps_eosc1 */
altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
- u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
/* Clock source: altera_arria10_hps_cb_intosc_ls */
altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
- u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
/* Clock source: altera_arria10_hps_f2h_free */
altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
- u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
* Binding: device
*/
i_clk_mgr: clock_manager@0xffd04000 {
- u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-clk-init";
reg = <0xffd04000 0x00000200>;
reg-names = "soc_clock_manager_OCP_SLV";
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
mainpll {
- u-boot,dm-pre-reloc;
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <191>; /* Field: vco1.numer */
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
perpll {
- u-boot,dm-pre-reloc;
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <159>; /* Field: vco1.numer */
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
alteragrp {
- u-boot,dm-pre-reloc;
nocclk = <0x0384000b>; /* Register: nocclk */
mpuclk = <0x03840001>; /* Register: mpuclk */
};
* Binding: pinmux
*/
i_io48_pin_mux: pinmux@0xffd07000 {
- u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "pinctrl-single";
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
shared {
- u-boot,dm-pre-reloc;
reg = <0xffd07000 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated {
- u-boot,dm-pre-reloc;
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated_cfg {
- u-boot,dm-pre-reloc;
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x003f3f3f>;
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
fpga {
- u-boot,dm-pre-reloc;
reg = <0xffd07400 0x00000100>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000001>;
* Binding: device
*/
i_noc: noc@0xffd10000 {
- u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-noc";
reg = <0xffd10000 0x00008000>;
reg-names = "mpu_m0";
firewall {
- u-boot,dm-pre-reloc;
/*
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
&gpio0 {
};
&uart0 {
+ clock-frequency = <100000000>;
u-boot,dm-pre-reloc;
};
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
&gpio1 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Aries/DENX MCV";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1 GiB */
+ };
+};
+
+&mmc0 { /* On-SoM eMMC */
+ bus-width = <8>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2019 Wolfgang Grandegger <wg@aries-embedded.de>
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include "socfpga_cyclone5_mcv.dtsi"
+
+/ {
+ model = "Aries/DENX MCV EVK";
+ compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
+
+ aliases {
+ ethernet0 = &gmac0;
+ stmpe-i2c0 = &stmpe1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&gpio0 { /* GPIO 0 ... 28 */
+ status = "okay";
+};
+
+&gpio1 { /* GPIO 29 ... 57 */
+ status = "okay";
+};
+
+&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ stmpe1: stmpe811@41 {
+ compatible = "st,stmpe811";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ id = <0>;
+ blocks = <0x5>;
+ irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ ts,sample-time = <4>;
+ ts,mod-12b = <1>;
+ ts,ref-sel = <0>;
+ ts,adc-freq = <1>;
+ ts,ave-ctrl = <1>;
+ ts,touch-det-delay = <3>;
+ ts,settling = <4>;
+ ts,fraction-z = <7>;
+ ts,i-drive = <1>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
&gpio0 {
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
&gpio0 { /* GPIO 0..29 */
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
};
};
u-boot,dm-pre-reloc;
};
+ sdr: sdr@f8000400 {
+ compatible = "altr,sdr-ctl-s10";
+ reg = <0xf8000400 0x80>,
+ <0xf8010000 0x190>,
+ <0xf8011000 0x500>;
+ resets = <&rst DDRSCH_RESET>;
+ u-boot,dm-pre-reloc;
+ };
+
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
};
&qspi {
+ reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
qflash0: n25q512a {
#address-cells = <1>;
#size-cells = <1>;
+ compatible = "jedec,spi-nor";
spi-max-frequency = <108000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
reg = <0>;
};
};
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
+ spi0 = &qspi;
};
soc {
st,sdram-refcount = < 1292 >;
};
};
+
+ qspi: quadspi@A0001000 {
+ compatible = "st,stm32-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+ reg-names = "qspi", "qspi_mm";
+ interrupts = <91>;
+ spi-max-frequency = <108000000>;
+ clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
+ resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
+ pinctrl-0 = <&qspi_pins>;
+ };
};
};
};
};
+ qspi_pins: qspi@0 {
+ pins {
+ pinmux = <STM32_PINMUX('F',10, AF9)>, /* CLK */
+ <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
+ <STM32_PINMUX('F', 8, AF10)>, /* BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* BK1_IO1 */
+ <STM32_PINMUX('F', 7, AF9)>, /* BK1_IO2 */
+ <STM32_PINMUX('F', 6, AF9)>; /* BK1_IO3 */
+ slew-rate = <2>;
+ };
+ };
+
usart3_pins_a: usart3@0 {
u-boot,dm-pre-reloc;
pins1 {
&syscfg {
u-boot,dm-pre-reloc;
};
+
+&qspi {
+ reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
+ flash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <108000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+};
};
&qspi {
+ reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
qflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "micron,n25q128a13", "jedec,spi-nor";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <108000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- memory-map = <0x90000000 0x1000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
reg = <0>;
};
};
};
&qspi {
+ reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
flash0: mx66l51235l {
#address-cells = <1>;
#size-cells = <1>;
+ compatible = "jedec,spi-nor";
spi-max-frequency = <108000000>;
+ spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
* address mapping : RBC
* Tc > + 85C : N
*/
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.43"
-#define DDR_MEM_SPEED 533
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.44"
+#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
#define DDR_MSTR 0x00041401
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
-#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
-#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-/* STM32MP157C ED1 and ED2 BOARD configuration
+ *
+ * STM32MP157C ED1 BOARD configuration
* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
* Reference used NT5CC256M16DP-DI from NANYA
*
* timing mode optimized
* Scheduling/QoS options : type = 2
* address mapping : RBC
+ * Tc > + 85C : N
*/
-#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
-#define DDR_MEM_SPEED 533
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.44"
+#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x40000000
#define DDR_MSTR 0x00040401
#define DDR_ADDRMAP11 0x00000000
#define DDR_ODTCFG 0x06000600
#define DDR_ODTMAP 0x00000001
-#define DDR_SCHED 0x00001201
+#define DDR_SCHED 0x00000C01
#define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x01000001
#define DDR_PERFLPR1 0x08000200
#define DDR_PCCFG 0x00000010
#define DDR_PCFGR_0 0x00010000
#define DDR_PCFGW_0 0x00000000
-#define DDR_PCFGQOS0_0 0x02100B03
+#define DDR_PCFGQOS0_0 0x02100C03
#define DDR_PCFGQOS1_0 0x00800100
-#define DDR_PCFGWQOS0_0 0x01100B03
+#define DDR_PCFGWQOS0_0 0x01100C03
#define DDR_PCFGWQOS1_0 0x01000200
#define DDR_PCFGR_1 0x00010000
#define DDR_PCFGW_1 0x00000000
-#define DDR_PCFGQOS0_1 0x02100B03
-#define DDR_PCFGQOS1_1 0x00800100
-#define DDR_PCFGWQOS0_1 0x01100B03
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
#define DDR_PCFGWQOS1_1 0x01000200
#define DDR_PGCR 0x01442E02
#define DDR_PTR0 0x0022AA5B
#define DDR_MR2 0x00000208
#define DDR_MR3 0x00000000
#define DDR_ODTCR 0x00010000
-#define DDR_ZQ0CR1 0x0000005B
+#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Vasily Khoruzhick <anarsoul@gmail.com>
+ *
+ */
+
+#include "sunxi-u-boot.dtsi"
+
+/ {
+ vdd_bl: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "bl-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ enable-active-high;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 0>;
+ brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+ default-brightness-level = <2>;
+ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+ power-supply = <&vdd_bl>;
+ };
+};
+
+/* The ANX6345 eDP-bridge is on i2c */
+&i2c0 {
+ anx6345: edp-bridge@38 {
+ compatible = "analogix,anx6345";
+ reg = <0x38>;
+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+ status = "okay";
+ };
+};
+
+&pwm {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) Harald Geyer <harald@ccbib.org>
+ * based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Olimex A64 Teres-I";
+ compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+
+ framebuffer-lcd {
+ eDP25-supply = <®_dldo2>;
+ eDP12-supply = <®_dldo3>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ lid-switch {
+ label = "Lid Switch";
+ gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ capslock {
+ label = "teres-i:green:capslock";
+ gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
+ };
+
+ numlock {
+ label = "teres-i:green:numlock";
+ gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+ };
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ status = "okay";
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+
+/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline)
+ * driver for this chip at the moment, the bootloader initializes it.
+ * However it can be accessed with the i2c-dev driver from user space.
+ */
+&i2c0 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <®_aldo2>;
+ vqmmc-supply = <®_dldo4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723bs: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+};
+
+#include "axp803.dtsi"
+
+®_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-pe";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1040000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-ddr3";
+};
+
+®_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-pd";
+};
+
+®_dldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd-edp";
+};
+
+®_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+®_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+®_eldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dvdd-csi";
+};
+
+®_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+®_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&simplefb_hdmi {
+ vcc-hdmi-supply = <®_dldo1>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2019 Clément Péron <peron.clem@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Beelink GS1";
+ compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "beelink:white:power";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ default-state = "on";
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_cldo1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc2 {
+ vmmc-supply = <®_cldo1>;
+ vqmmc-supply = <®_bldo2>;
+ non-removable;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp805: pmic@36 {
+ compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x36>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ x-powers,self-working-mode;
+ vina-supply = <®_vcc5v>;
+ vinb-supply = <®_vcc5v>;
+ vinc-supply = <®_vcc5v>;
+ vind-supply = <®_vcc5v>;
+ vine-supply = <®_vcc5v>;
+ aldoin-supply = <®_vcc5v>;
+ bldoin-supply = <®_vcc5v>;
+ cldoin-supply = <®_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-ac200";
+ regulator-enable-ramp-delay = <100000>;
+ };
+
+ reg_aldo3: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc25-dram";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-bias-pll";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-efuse-pcie-hdmi-io";
+ };
+
+ reg_bldo3: bldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dcxoio";
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ reg_cldo1: cldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+ };
+
+ reg_cldo2: cldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+ };
+
+ reg_cldo3: cldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <960000>;
+ regulator-max-microvolt = <960000>;
+ regulator-name = "vdd-sys";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
reg = <0x0 0x80000000 0x0 0x80000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05>;
avdd-pex-pll-supply = <&vdd_1v05>;
reg = <0x80000000 0x80000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;
reg = <0x80000000 0x80000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;
interrupt-parent = <&lic>;
- pcie-controller@01003000 {
+ pcie@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
reg = <0x01003000 0x00000800 /* PADS registers */
power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>;
};
- pcie-controller@10003000 {
+ pcie@10003000 {
status = "okay";
pci@1,0 {
power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
};
- pcie-controller@10003000 {
+ pcie@10003000 {
status = "okay";
pci@1,0 {
};
aliases {
+ ethernet = "/ethernet@2490000";
mmc0 = "/sdhci@3460000";
mmc1 = "/sdhci@3400000";
i2c0 = "/bpmp/i2c";
ethernet@2490000 {
status = "okay";
phy-reset-gpios = <&gpio_main TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
};
i2c@3160000 {
#interrupt-cells = <2>;
};
- pcie-controller@10003000 {
+ pcie@10003000 {
compatible = "nvidia,tegra186-pcie";
device_type = "pci";
reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
nvidia,sys-clock-req-active-high;
};
- pcie-controller@80003000 {
+ pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;
spi-max-frequency = <25000000>;
};
- pcie-controller@80003000 {
+ pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;
reset-names = "fuse";
};
- pcie-controller@80003000 {
+ pcie@80003000 {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
reg = <0x80003000 0x00000800 /* PADS registers */
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
- pcie-controller@01003000 {
+ pcie@1003000 {
status = "okay";
pci@1,0 {
#address-cells = <2>;
#size-cells = <2>;
- pcie-controller@01003000 {
+ pcie@1003000 {
compatible = "nvidia,tegra210-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
reg = <0x80000000 0x40000000>;
};
- pcie-controller@00003000 {
+ pcie@3000 {
status = "okay";
avdd-pexa-supply = <&vdd2_reg>;
vdd-pexa-supply = <&vdd2_reg>;
reg = <0x80000000 0x7ff00000>;
};
- pcie-controller@00003000 {
+ pcie@3000 {
status = "okay";
avdd-pexa-supply = <&ldo1_reg>;
reg = <0x80000000 0x40000000>;
};
- pcie-controller@00003000 {
+ pcie@3000 {
status = "okay";
/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
compatible = "nvidia,tegra30";
interrupt-parent = <&lic>;
- pcie-controller@00003000 {
+ pcie@3000 {
compatible = "nvidia,tegra30-pcie";
device_type = "pci";
reg = <0x00003000 0x00000800 /* PADS registers */
status = "okay";
};
+/* Ethernet */
&fec1 {
phy-mode = "rmii";
+ phy-handle = <ðphy1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ max-speed = <100>;
+ reg = <1>;
+ };
+ };
};
&i2c0 {
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#elif defined(CONFIG_ARCH_LS1028A)
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_TZASC_400
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE 0x02200000
+#define TZPCR0SIZE_BASE (TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+
+#define SRDS_MAX_LANES 4
+
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x06000000
+#define GICR_BASE 0x06040000
+
+/* SMMU Definitions */
+#define SMMU_BASE 0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
+#ifdef CONFIG_ARCH_LS2080A
#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
+#else
+#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
+#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000
+#define SYS_PCIE5_PHYS_SIZE 0x800000000
+#define SYS_PCIE6_PHYS_SIZE 0x800000000
+#endif
#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LS1088A
+#ifdef CONFIG_ARCH_LX2160A
+#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
+#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
+#endif
+
+#ifdef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL
+#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL
+#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL
+#elif CONFIG_ARCH_LS1088A
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
+#elif CONFIG_ARCH_LS1028A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
#else
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 30
+#elif defined(CONFIG_ARCH_LS1028A)
+#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
+#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR 29
#endif
#define RCW_SB_EN_REG_INDEX 9
#define RCW_SB_EN_MASK 0x00000400
/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
#define SVR_LS1043A_P23 0x879202
#define SVR_LS1023A_P23 0x87920A
+#define SVR_LS1028A 0x870B00
#define SVR_LS1046A 0x870700
#define SVR_LS1026A 0x870708
#define SVR_LS1048A 0x870320
#define FSL_PEX_STREAM_ID_NUM (0x100)
#endif
-#if defined(CONFIG_ARCH_LS2080A)
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A)
#define FSL_PEX_STREAM_ID_END 22
#elif defined(CONFIG_ARCH_LS1088A)
#define FSL_PEX_STREAM_ID_END 18
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_IMX8MQ 0x82
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
+#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
#if defined(CONFIG_IMX8QXP)
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#elif defined(CONFIG_IMX8QM)
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
#else
#error "No pin header"
#endif
sc_pm_clock_rate_t *rate);
int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);
-int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
- sc_pm_clock_rate_t *rate);
-int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
- sc_pm_clock_rate_t *rate);
int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_bool_t enable, sc_bool_t autog);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_USB_H__
+#define __MESON_USB_H__
+
+int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode);
+
+#endif /* __MESON_USB_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
ARM_VECTORS
#endif
-#if defined(CONFIG_SPL_BUILD) && (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
+#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \
+ (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
#endif
#ifndef _ASM_ARCH_DDR_RK3188_H
#define _ASM_ARCH_DDR_RK3188_H
-#include <asm/arch/ddr_rk3288.h>
+#include <asm/arch-rockchip/ddr_rk3288.h>
/*
* RK3188 Memory scheduler register map.
GRF_GPIO3B6_SEL_SHIFT = 12,
GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT,
GRF_MAC_RXCLK = 1,
+ GRF_UART3_SIN = 2,
+ GRF_GPIO3B7_SEL_SHIFT = 14,
+ GRF_GPIO3B7_SEL_MASK = 3 << GRF_GPIO3B7_SEL_SHIFT,
+ GRF_UART3_SOUT = 2,
/* GRF_GPIO3C_IOMUX */
GRF_GPIO3C1_SEL_SHIFT = 2,
#define RK_SETBITS(set) RK_CLRSETBITS(0, set)
#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0)
-#define TIMER7_BASE 0xff810020
-
#define rk_clrsetreg(addr, clr, set) \
writel(((clr) | (set)) << 16 | (set), addr)
#define rk_clrreg(addr, clr) writel((clr) << 16, addr)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
#define SUNXI_RTC_BASE 0x07000000
#define SUNXI_R_CPUCFG_BASE 0x07000400
#define SUNXI_PRCM_BASE 0x07010000
+#define SUNXI_R_WDOG_BASE 0x07020400
#define SUNXI_R_PIO_BASE 0x07022000
#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_TWI_BASE 0x07081400
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 NVIDIA Corporation. All rights reserved.
+ */
+
+#ifndef _TEGRA_CBOOT_H_
+#define _TEGRA_CBOOT_H_
+
+#ifdef CONFIG_ARM64
+extern unsigned long cboot_boot_x0;
+
+void cboot_save_boot_params(unsigned long x0, unsigned long x1,
+ unsigned long x2, unsigned long x3);
+int cboot_dram_init(void);
+int cboot_dram_init_banksize(void);
+ulong cboot_get_usable_ram_top(ulong total_size);
+int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]);
+#else
+static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1,
+ unsigned long x2, unsigned long x3)
+{
+}
+
+static inline int cboot_dram_init(void)
+{
+ return -ENOSYS;
+}
+
+static inline int cboot_dram_init_banksize(void)
+{
+ return -ENOSYS;
+}
+
+static inline ulong cboot_get_usable_ram_top(ulong total_size)
+{
+ return 0;
+}
+
+static inline int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN])
+{
+ return -ENOSYS;
+}
+#endif
+
+#endif
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2019
* NVIDIA Corporation <www.nvidia.com>
*/
/* APBDEV_PMC_CNTRL2_0 0x440 */
#define HOLD_CKE_LOW_EN (1 << 12)
+/* PMC read/write functions */
+u32 tegra_pmc_readl(unsigned long offset);
+void tegra_pmc_writel(u32 value, unsigned long offset);
+
+#define PMC_CNTRL 0x0
+#define PMC_CNTRL_MAIN_RST BIT(4)
+
+#if IS_ENABLED(CONFIG_TEGRA186)
+# define PMC_SCRATCH0 0x32000
+#else
+# define PMC_SCRATCH0 0x00050
+#endif
+
+/* for secure PMC */
+#define TEGRA_SMC_PMC 0xc2fffe00
+#define TEGRA_SMC_PMC_READ 0xaa
+#define TEGRA_SMC_PMC_WRITE 0xbb
+
#endif /* PMC_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_PMU_H_
+#define _TEGRA_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA_PMU_H_ */
#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+ defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) || \
+ defined(CONFIG_TEGRA132) || defined(CONFIG_TEGRA210)
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
+#else
+#define NV_PA_PMC_BASE 0xc360000
+#endif
#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * tegra_ahub.h - Definitions for Tegra124 audio hub driver
+ * Taken from dc tegra_ahub.h
+ *
+ * Copyright 2018 Google LLC
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA_AHUB_H_
+#define _TEGRA_AHUB_H_
+
+/*
+ * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio
+ * transmitted by a particular TX CIF.
+ */
+struct xbar_regs {
+ u32 apbif_rx0; /* AUDIO_APBIF_RX0, offset 0x00 */
+ u32 apbif_rx1; /* AUDIO_APBIF_RX1, offset 0x04 */
+ u32 apbif_rx2; /* AUDIO_APBIF_RX2, offset 0x08 */
+ u32 apbif_rx3; /* AUDIO_APBIF_RX3, offset 0x0C */
+
+ u32 i2s0_rx0; /* AUDIO_I2S0_RX0, offset 0x10 */
+ u32 i2s1_rx0; /* AUDIO_I2S1_RX0, offset 0x14 */
+ u32 i2s2_rx0; /* AUDIO_I2S2_RX0, offset 0x18 */
+ u32 i2s3_rx0; /* AUDIO_I2S3_RX0, offset 0x1C */
+ u32 i2s4_rx0; /* AUDIO_I2S4_RX0, offset 0x20 */
+
+ u32 dam0_rx0; /* AUDIO_DAM0_RX0, offset 0x24 */
+ u32 dam0_rx1; /* AUDIO_DAM0_RX1, offset 0x28 */
+ u32 dam1_rx0; /* AUDIO_DAM1_RX0, offset 0x2C */
+ u32 dam1_rx1; /* AUDIO_DAM1_RX1, offset 0x30 */
+ u32 dam2_rx0; /* AUDIO_DAM2_RX0, offset 0x34 */
+ u32 dam2_rx1; /* AUDIO_DAM2_RX1, offset 0x38 */
+
+ u32 spdif_rx0; /* AUDIO_SPDIF_RX0, offset 0x3C */
+ u32 spdif_rx1; /* AUDIO_SPDIF_RX1, offset 0x40 */
+
+ u32 apbif_rx4; /* AUDIO_APBIF_RX4, offset 0x44 */
+ u32 apbif_rx5; /* AUDIO_APBIF_RX4, offset 0x48 */
+ u32 apbif_rx6; /* AUDIO_APBIF_RX4, offset 0x4C */
+ u32 apbif_rx7; /* AUDIO_APBIF_RX4, offset 0x50 */
+ u32 apbif_rx8; /* AUDIO_APBIF_RX4, offset 0x54 */
+ u32 apbif_rx9; /* AUDIO_APBIF_RX4, offset 0x58 */
+
+ u32 amx0_rx0; /* AUDIO_AMX0_RX0, offset 0x5C */
+ u32 amx0_rx1; /* AUDIO_AMX0_RX1, offset 0x60 */
+ u32 amx0_rx2; /* AUDIO_AMX0_RX2, offset 0x64 */
+ u32 amx0_rx3; /* AUDIO_AMX0_RX3, offset 0x68 */
+
+ u32 adx0_rx0; /* AUDIO_ADX0_RX0, offset 0x6C */
+};
+
+struct apbif_regs {
+ u32 channel0_ctrl; /* APBIF_CHANNEL0_CTRL */
+ u32 channel0_clr; /* APBIF_CHANNEL0_CLEAR */
+ u32 channel0_stat; /* APBIF_CHANNEL0_STATUS */
+ u32 channel0_txfifo; /* APBIF_CHANNEL0_TXFIFO */
+ u32 channel0_rxfifo; /* APBIF_CHANNEL0_RXFIFO */
+ u32 channel0_cif_tx0_ctrl; /* APBIF_AUDIOCIF_TX0_CTRL */
+ u32 channel0_cif_rx0_ctrl; /* APBIF_AUDIOCIF_RX0_CTRL */
+ u32 channel0_reserved0; /* RESERVED, offset 0x1C */
+ /* ahub_channel1_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+ /* ahub_channel2_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+ /* ahub_channel3_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+ u32 reserved123[3 * 8];
+ u32 config_link_ctrl; /* APBIF_CONFIG_LINK_CTRL_0, off 0x80 */
+ u32 misc_ctrl; /* APBIF_MISC_CTRL_0, offset 0x84 */
+ u32 apbdma_live_stat; /* APBIF_APBDMA_LIVE_STATUS_0 */
+ u32 i2s_live_stat; /* APBIF_I2S_LIVE_STATUS_0 */
+ u32 dam0_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */
+ u32 dam1_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */
+ u32 dam2_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */
+ u32 spdif_live_stat; /* APBIF_SPDIF_LIVE_STATUS_0 */
+ u32 i2s_int_mask; /* APBIF_I2S_INT_MASK_0, offset B0 */
+ u32 dam_int_mask; /* APBIF_DAM_INT_MASK_0 */
+ u32 reserved_int_mask; /* RESERVED, offset 0xB8 */
+ u32 spdif_int_mask; /* APBIF_SPDIF_INT_MASK_0 */
+ u32 apbif_int_mask; /* APBIF_APBIF_INT_MASK_0, off C0 */
+ u32 reserved2_int_mask; /* RESERVED, offset 0xC4 */
+ u32 i2s_int_stat; /* APBIF_I2S_INT_STATUS_0, offset C8 */
+ u32 dam_int_stat; /* APBIF_DAM_INT_STATUS_0 */
+ u32 reserved_int_stat; /* RESERVED, offset 0xD0 */
+ u32 spdif_int_stat; /* APBIF_SPDIF_INT_STATUS_0 */
+ u32 apbif_int_stat; /* APBIF_APBIF_INT_STATUS_0 */
+ u32 reserved2_int_stat; /* RESERVED, offset 0xDC */
+ u32 i2s_int_src; /* APBIF_I2S_INT_SOURCE_0, offset E0 */
+ u32 dam_int_src; /* APBIF_DAM_INT_SOURCE_0 */
+ u32 reserved_int_src; /* RESERVED, offset 0xE8 */
+ u32 spdif_int_src; /* APBIF_SPDIF_INT_SOURCE_0 */
+ u32 apbif_int_src; /* APBIF_APBIF_INT_SOURCE_0, off F0 */
+ u32 reserved2_int_src; /* RESERVED, offset 0xF4 */
+ u32 i2s_int_set; /* APBIF_I2S_INT_SET_0, offset 0xF8 */
+ u32 dam_int_set; /* APBIF_DAM_INT_SET_0, offset 0xFC */
+ u32 spdif_int_set; /* APBIF_SPDIF_INT_SET_0, off 0x100 */
+ u32 apbif_int_set; /* APBIF_APBIF_INT_SET_0, off 0x104 */
+};
+
+/*
+ * Tegra AHUB Registers Definition
+ */
+enum {
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT = 24,
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US = 0x3f,
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK =
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US <<
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT,
+
+ /* Channel count minus 1 */
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT = 20,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US = 0xf,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK =
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US <<
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT,
+
+ /* Channel count minus 1 */
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT = 16,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US = 0xf,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK =
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US <<
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT,
+
+ TEGRA_AUDIOCIF_BITS_4 = 0,
+ TEGRA_AUDIOCIF_BITS_8 = 1,
+ TEGRA_AUDIOCIF_BITS_12 = 2,
+ TEGRA_AUDIOCIF_BITS_16 = 3,
+ TEGRA_AUDIOCIF_BITS_20 = 4,
+ TEGRA_AUDIOCIF_BITS_24 = 5,
+ TEGRA_AUDIOCIF_BITS_28 = 6,
+ TEGRA_AUDIOCIF_BITS_32 = 7,
+
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT = 12,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_MASK =
+ 7 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_4 =
+ TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_8 =
+ TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_12 =
+ TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_16 =
+ TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_20 =
+ TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_24 =
+ TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_28 =
+ TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_32 =
+ TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT = 8,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_MASK =
+ 7 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_4 =
+ TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_8 =
+ TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_12 =
+ TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_16 =
+ TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_20 =
+ TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_24 =
+ TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_28 =
+ TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_32 =
+ TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+
+ TEGRA_AUDIOCIF_EXPAND_ZERO = 0,
+ TEGRA_AUDIOCIF_EXPAND_ONE = 1,
+ TEGRA_AUDIOCIF_EXPAND_LFSR = 2,
+
+ TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT = 6,
+ TEGRA_AUDIOCIF_CTRL_EXPAND_MASK = 3 << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_EXPAND_ZERO =
+ TEGRA_AUDIOCIF_EXPAND_ZERO << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_EXPAND_ONE =
+ TEGRA_AUDIOCIF_EXPAND_ONE << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_EXPAND_LFSR =
+ TEGRA_AUDIOCIF_EXPAND_LFSR << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+
+ TEGRA_AUDIOCIF_STEREO_CONV_CH0 = 0,
+ TEGRA_AUDIOCIF_STEREO_CONV_CH1 = 1,
+ TEGRA_AUDIOCIF_STEREO_CONV_AVG = 2,
+
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT = 4,
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_MASK =
+ 3 << TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH0 =
+ TEGRA_AUDIOCIF_STEREO_CONV_CH0 <<
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH1 =
+ TEGRA_AUDIOCIF_STEREO_CONV_CH1 <<
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_AVG =
+ TEGRA_AUDIOCIF_STEREO_CONV_AVG <<
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+
+ TEGRA_AUDIOCIF_CTRL_REPLICATE = 3,
+
+ TEGRA_AUDIOCIF_DIRECTION_TX = 0,
+ TEGRA_AUDIOCIF_DIRECTION_RX = 1,
+
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT = 2,
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_MASK =
+ 1 << TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_TX =
+ TEGRA_AUDIOCIF_DIRECTION_TX <<
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_RX =
+ TEGRA_AUDIOCIF_DIRECTION_RX <<
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT,
+
+ TEGRA_AUDIOCIF_TRUNCATE_ROUND = 0,
+ TEGRA_AUDIOCIF_TRUNCATE_CHOP = 1,
+
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT = 1,
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_MASK =
+ 1 << TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_ROUND =
+ TEGRA_AUDIOCIF_TRUNCATE_ROUND <<
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_CHOP =
+ TEGRA_AUDIOCIF_TRUNCATE_CHOP <<
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT,
+
+ TEGRA_AUDIOCIF_MONO_CONV_ZERO = 0,
+ TEGRA_AUDIOCIF_MONO_CONV_COPY = 1,
+
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT = 0,
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_MASK =
+ 1 << TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_ZERO =
+ TEGRA_AUDIOCIF_MONO_CONV_ZERO <<
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_COPY =
+ TEGRA_AUDIOCIF_MONO_CONV_COPY <<
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT,
+
+ /* Registers within TEGRA_AUDIO_CLUSTER_BASE */
+
+ TEGRA_AHUB_CHANNEL_CTRL = 0x0,
+ TEGRA_AHUB_CHANNEL_CTRL_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_CTRL_COUNT = 4,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_EN = 1 << 31,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_EN = 1 << 30,
+ TEGRA_AHUB_CHANNEL_CTRL_LOOPBACK = 1 << 29,
+
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT = 16,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US = 0xff,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK =
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US <<
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT,
+
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT = 8,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US = 0xff,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK =
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US <<
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT,
+
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN = 1 << 6,
+
+ TEGRA_PACK_8_4 = 2,
+ TEGRA_PACK_16 = 3,
+
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT = 4,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US = 3,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK =
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US <<
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_8_4 =
+ TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 =
+ TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT,
+
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_EN = 1 << 2,
+
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT = 0,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US = 3,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK =
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US <<
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_8_4 =
+ TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_16 =
+ TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT,
+
+ /* TEGRA_AHUB_CHANNEL_CLEAR */
+
+ TEGRA_AHUB_CHANNEL_CLEAR = 0x4,
+ TEGRA_AHUB_CHANNEL_CLEAR_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_CLEAR_COUNT = 4,
+ TEGRA_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET = 1 << 31,
+ TEGRA_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET = 1 << 30,
+
+ TEGRA_AHUB_CHANNEL_STATUS = 0x8,
+ TEGRA_AHUB_CHANNEL_STATUS_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_STATUS_COUNT = 4,
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT = 24,
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US = 0xff,
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK =
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US <<
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT,
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT = 16,
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US = 0xff,
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK =
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US <<
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT,
+ TEGRA_AHUB_CHANNEL_STATUS_TX_TRIG = 1 << 1,
+ TEGRA_AHUB_CHANNEL_STATUS_RX_TRIG = 1 << 0,
+
+ TEGRA_AHUB_CHANNEL_TXFIFO = 0xc,
+ TEGRA_AHUB_CHANNEL_TXFIFO_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_TXFIFO_COUNT = 4,
+
+ TEGRA_AHUB_CHANNEL_RXFIFO = 0x10,
+ TEGRA_AHUB_CHANNEL_RXFIFO_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_RXFIFO_COUNT = 4,
+
+ TEGRA_AHUB_CIF_TX_CTRL = 0x14,
+ TEGRA_AHUB_CIF_TX_CTRL_STRIDE = 0x20,
+ TEGRA_AHUB_CIF_TX_CTRL_COUNT = 4,
+ /* Uses field from TEGRA_AUDIOCIF_CTRL_* */
+
+ TEGRA_AHUB_CIF_RX_CTRL = 0x18,
+ TEGRA_AHUB_CIF_RX_CTRL_STRIDE = 0x20,
+ TEGRA_AHUB_CIF_RX_CTRL_COUNT = 4,
+ /* Uses field from TEGRA_AUDIOCIF_CTRL_* */
+
+ TEGRA_AHUB_CONFIG_LINK_CTRL = 0x80,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT = 28,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US = 0xf,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK =
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US <<
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT = 16,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US = 0xfff,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK =
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US <<
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT = 4,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US = 0xfff,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK =
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US <<
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_CG_EN = 1 << 2,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR = 1 << 1,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_SOFT_RESET = 1 << 0,
+
+ TEGRA_AHUB_MISC_CTRL = 0x84,
+ TEGRA_AHUB_MISC_CTRL_AUDIO_ACTIVE = 1 << 31,
+ TEGRA_AHUB_MISC_CTRL_AUDIO_CG_EN = 1 << 8,
+ TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT = 0,
+ TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK =
+ 0x1f << TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT,
+
+ TEGRA_AHUB_APBDMA_LIVE_STATUS = 0x88,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL = 1 << 31,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL = 1 << 30,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL = 1 << 29,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL = 1 << 28,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL = 1 << 27,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL = 1 << 26,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL = 1 << 25,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL = 1 << 24,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY = 1 << 23,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY = 1 << 22,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY = 1 << 21,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY = 1 << 20,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY = 1 << 19,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY = 1 << 18,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY = 1 << 17,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY = 1 << 16,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL = 1 << 15,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL = 1 << 14,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL = 1 << 13,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL = 1 << 12,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL = 1 << 11,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL = 1 << 10,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL = 1 << 9,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL = 1 << 8,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY = 1 << 7,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY = 1 << 6,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY = 1 << 5,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY = 1 << 4,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY = 1 << 3,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY = 1 << 2,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY = 1 << 1,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY = 1 << 0,
+
+ TEGRA_AHUB_I2S_LIVE_STATUS = 0x8c,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL = 1 << 29,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL = 1 << 28,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL = 1 << 27,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL = 1 << 26,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL = 1 << 25,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL = 1 << 24,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL = 1 << 23,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL = 1 << 22,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL = 1 << 21,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL = 1 << 20,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED = 1 << 19,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED = 1 << 18,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED = 1 << 17,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED = 1 << 16,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED = 1 << 15,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED = 1 << 14,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED = 1 << 13,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED = 1 << 12,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED = 1 << 11,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED = 1 << 10,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY = 1 << 9,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY = 1 << 8,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY = 1 << 7,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY = 1 << 6,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY = 1 << 5,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY = 1 << 4,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY = 1 << 3,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY = 1 << 2,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY = 1 << 1,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY = 1 << 0,
+
+ TEGRA_AHUB_DAM_LIVE_STATUS = 0x90,
+ TEGRA_AHUB_DAM_LIVE_STATUS_STRIDE = 0x8,
+ TEGRA_AHUB_DAM_LIVE_STATUS_COUNT = 3,
+ TEGRA_AHUB_DAM_LIVE_STATUS_TX_ENABLED = 1 << 26,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX1_ENABLED = 1 << 25,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX0_ENABLED = 1 << 24,
+ TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL = 1 << 15,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL = 1 << 9,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL = 1 << 8,
+ TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY = 1 << 7,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY = 1 << 1,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY = 1 << 0,
+
+ TEGRA_AHUB_SPDIF_LIVE_STATUS = 0xa8,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED = 1 << 11,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED = 1 << 10,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED = 1 << 9,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED = 1 << 8,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL = 1 << 7,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL = 1 << 6,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL = 1 << 5,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL = 1 << 4,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY = 1 << 3,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY = 1 << 2,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY = 1 << 1,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY = 1 << 0,
+
+ TEGRA_AHUB_I2S_INT_MASK = 0xb0,
+ TEGRA_AHUB_DAM_INT_MASK = 0xb4,
+ TEGRA_AHUB_SPDIF_INT_MASK = 0xbc,
+ TEGRA_AHUB_APBIF_INT_MASK = 0xc0,
+ TEGRA_AHUB_I2S_INT_STATUS = 0xc8,
+ TEGRA_AHUB_DAM_INT_STATUS = 0xcc,
+ TEGRA_AHUB_SPDIF_INT_STATUS = 0xd4,
+ TEGRA_AHUB_APBIF_INT_STATUS = 0xd8,
+ TEGRA_AHUB_I2S_INT_SOURCE = 0xe0,
+ TEGRA_AHUB_DAM_INT_SOURCE = 0xe4,
+ TEGRA_AHUB_SPDIF_INT_SOURCE = 0xec,
+ TEGRA_AHUB_APBIF_INT_SOURCE = 0xf0,
+ TEGRA_AHUB_I2S_INT_SET = 0xf8,
+ TEGRA_AHUB_DAM_INT_SET = 0xfc,
+ TEGRA_AHUB_SPDIF_INT_SET = 0x100,
+ TEGRA_AHUB_APBIF_INT_SET = 0x104,
+
+ TEGRA_AHUB_AUDIO_RX = 0x0,
+ TEGRA_AHUB_AUDIO_RX_STRIDE = 0x4,
+ TEGRA_AHUB_AUDIO_RX_COUNT = 17,
+};
+
+#endif /* _TEGRA_I2C_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * tegra_i2s.h - Definitions for Tegra124 I2S driver.
+ * Note, some structures (ex, CIF) are different in Tegra114.
+ *
+ * NVIDIA Tegra I2S controller
+ * Modified from dc tegra_regs.h
+ *
+ * Copyright 2018 Google LLC
+ *
+ * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA_I2S_H_
+#define _TEGRA_I2S_H_
+
+struct i2s_ctlr {
+ u32 ctrl; /* I2S_CTRL_0, 0x00 */
+ u32 timing; /* I2S_TIMING_0, 0x04 */
+ u32 offset; /* I2S_OFFSET_0, 0x08 */
+ u32 ch_ctrl; /* I2S_CH_CTRL_0, 0x0C */
+ u32 slot_ctrl; /* I2S_SLOT_CTRL_0, 0x10 */
+ u32 cif_tx_ctrl; /* I2S_CIF_TX_CTRL_0, 0x14 */
+ u32 cif_rx_ctrl; /* I2S_CIF_RX_CTRL_0, 0x18 */
+ u32 flowctl; /* I2S_FLOWCTL_0, 0x1C */
+ u32 tx_step; /* I2S_TX_STEP_0, 0x20 */
+ u32 flow_status; /* I2S_FLOW_STATUS_0, 0x24 */
+ u32 flow_total; /* I2S_FLOW_TOTAL_0, 0x28 */
+ u32 flow_over; /* I2S_FLOW_OVER_0, 0x2C */
+ u32 flow_under; /* I2S_FLOW_UNDER_0, 0x30 */
+ u32 reserved[12]; /* RESERVED, 0x34 - 0x60 */
+ u32 slot_ctrl2; /* I2S_SLOT_CTRL2_0, 0x64*/
+};
+
+enum {
+ I2S_CTRL_XFER_EN_TX = 1 << 31,
+ I2S_CTRL_XFER_EN_RX = 1 << 30,
+ I2S_CTRL_CG_EN = 1 << 29,
+ I2S_CTRL_SOFT_RESET = 1 << 28,
+ I2S_CTRL_TX_FLOWCTL_EN = 1 << 27,
+
+ I2S_CTRL_OBS_SEL_SHIFT = 24,
+ I2S_CTRL_OBS_SEL_MASK = 7 << I2S_CTRL_OBS_SEL_SHIFT,
+
+ I2S_FRAME_FORMAT_LRCK = 0,
+ I2S_FRAME_FORMAT_FSYNC = 1,
+
+ I2S_CTRL_FRAME_FORMAT_SHIFT = 12,
+ I2S_CTRL_FRAME_FORMAT_MASK = 7 << I2S_CTRL_FRAME_FORMAT_SHIFT,
+ I2S_CTRL_FRAME_FORMAT_LRCK = I2S_FRAME_FORMAT_LRCK <<
+ I2S_CTRL_FRAME_FORMAT_SHIFT,
+ I2S_CTRL_FRAME_FORMAT_FSYNC = I2S_FRAME_FORMAT_FSYNC <<
+ I2S_CTRL_FRAME_FORMAT_SHIFT,
+
+ I2S_CTRL_MASTER_ENABLE = 1 << 10,
+
+ I2S_LRCK_LEFT_LOW = 0,
+ I2S_LRCK_RIGHT_LOW = 1,
+
+ I2S_CTRL_LRCK_SHIFT = 9,
+ I2S_CTRL_LRCK_MASK = 1 << I2S_CTRL_LRCK_SHIFT,
+ I2S_CTRL_LRCK_L_LOW = I2S_LRCK_LEFT_LOW << I2S_CTRL_LRCK_SHIFT,
+ I2S_CTRL_LRCK_R_LOW = I2S_LRCK_RIGHT_LOW << I2S_CTRL_LRCK_SHIFT,
+
+ I2S_CTRL_LPBK_ENABLE = 1 << 8,
+
+ I2S_BIT_CODE_LINEAR = 0,
+ I2S_BIT_CODE_ULAW = 1,
+ I2S_BIT_CODE_ALAW = 2,
+
+ I2S_CTRL_BIT_CODE_SHIFT = 4,
+ I2S_CTRL_BIT_CODE_MASK = 3 << I2S_CTRL_BIT_CODE_SHIFT,
+ I2S_CTRL_BIT_CODE_LINEAR = I2S_BIT_CODE_LINEAR <<
+ I2S_CTRL_BIT_CODE_SHIFT,
+ I2S_CTRL_BIT_CODE_ULAW = I2S_BIT_CODE_ULAW << I2S_CTRL_BIT_CODE_SHIFT,
+ I2S_CTRL_BIT_CODE_ALAW = I2S_BIT_CODE_ALAW << I2S_CTRL_BIT_CODE_SHIFT,
+
+ I2S_BITS_8 = 1,
+ I2S_BITS_12 = 2,
+ I2S_BITS_16 = 3,
+ I2S_BITS_20 = 4,
+ I2S_BITS_24 = 5,
+ I2S_BITS_28 = 6,
+ I2S_BITS_32 = 7,
+
+ /* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
+ I2S_CTRL_BIT_SIZE_SHIFT = 0,
+ I2S_CTRL_BIT_SIZE_MASK = 7 << I2S_CTRL_BIT_SIZE_SHIFT,
+ I2S_CTRL_BIT_SIZE_8 = I2S_BITS_8 << I2S_CTRL_BIT_SIZE_SHIFT,
+ I2S_CTRL_BIT_SIZE_12 = I2S_BITS_12 << I2S_CTRL_BIT_SIZE_SHIFT,
+ I2S_CTRL_BIT_SIZE_16 = I2S_BITS_16 << I2S_CTRL_BIT_SIZE_SHIFT,
+ I2S_CTRL_BIT_SIZE_20 = I2S_BITS_20 << I2S_CTRL_BIT_SIZE_SHIFT,
+ I2S_CTRL_BIT_SIZE_24 = I2S_BITS_24 << I2S_CTRL_BIT_SIZE_SHIFT,
+ I2S_CTRL_BIT_SIZE_28 = I2S_BITS_28 << I2S_CTRL_BIT_SIZE_SHIFT,
+ I2S_CTRL_BIT_SIZE_32 = I2S_BITS_32 << I2S_CTRL_BIT_SIZE_SHIFT,
+
+ I2S_TIMING_NON_SYM_ENABLE = 1 << 12,
+ I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT = 0,
+ I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US = 0x7ff,
+ I2S_TIMING_CHANNEL_BIT_COUNT_MASK =
+ I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US <<
+ I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT,
+
+ I2S_OFFSET_RX_DATA_OFFSET_SHIFT = 16,
+ I2S_OFFSET_RX_DATA_OFFSET_MASK_US = 0x7ff,
+ I2S_OFFSET_RX_DATA_OFFSET_MASK = I2S_OFFSET_RX_DATA_OFFSET_MASK_US <<
+ I2S_OFFSET_RX_DATA_OFFSET_SHIFT,
+ I2S_OFFSET_TX_DATA_OFFSET_SHIFT = 0,
+ I2S_OFFSET_TX_DATA_OFFSET_MASK_US = 0x7ff,
+ I2S_OFFSET_TX_DATA_OFFSET_MASK = I2S_OFFSET_TX_DATA_OFFSET_MASK_US <<
+ I2S_OFFSET_TX_DATA_OFFSET_SHIFT,
+
+ /* FSYNC width - 1 in bit clocks */
+ I2S_CH_CTRL_FSYNC_WIDTH_SHIFT = 24,
+ I2S_CH_CTRL_FSYNC_WIDTH_MASK_US = 0xff,
+ I2S_CH_CTRL_FSYNC_WIDTH_MASK = I2S_CH_CTRL_FSYNC_WIDTH_MASK_US <<
+ I2S_CH_CTRL_FSYNC_WIDTH_SHIFT,
+
+ I2S_HIGHZ_NO = 0,
+ I2S_HIGHZ_YES = 1,
+ I2S_HIGHZ_ON_HALF_BIT_CLK = 2,
+
+ I2S_CH_CTRL_HIGHZ_CTRL_SHIFT = 12,
+ I2S_CH_CTRL_HIGHZ_CTRL_MASK = 3 << I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+ I2S_CH_CTRL_HIGHZ_CTRL_NO = I2S_HIGHZ_NO <<
+ I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+ I2S_CH_CTRL_HIGHZ_CTRL_YES = I2S_HIGHZ_YES <<
+ I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+ I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK = I2S_HIGHZ_ON_HALF_BIT_CLK <<
+ I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+
+ I2S_MSB_FIRST = 0,
+ I2S_LSB_FIRST = 1,
+
+ I2S_CH_CTRL_RX_BIT_ORDER_SHIFT = 10,
+ I2S_CH_CTRL_RX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
+ I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
+ I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
+ I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
+ I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
+ I2S_CH_CTRL_TX_BIT_ORDER_SHIFT = 9,
+ I2S_CH_CTRL_TX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
+ I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
+ I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
+ I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
+ I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
+
+ I2S_POS_EDGE = 0,
+ I2S_NEG_EDGE = 1,
+
+ I2S_CH_CTRL_EGDE_CTRL_SHIFT = 8,
+ I2S_CH_CTRL_EGDE_CTRL_MASK = 1 << I2S_CH_CTRL_EGDE_CTRL_SHIFT,
+ I2S_CH_CTRL_EGDE_CTRL_POS_EDGE = I2S_POS_EDGE <<
+ I2S_CH_CTRL_EGDE_CTRL_SHIFT,
+ I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE = I2S_NEG_EDGE <<
+ I2S_CH_CTRL_EGDE_CTRL_SHIFT,
+
+ /* Sample size is # bits from BIT_SIZE minus this field */
+ I2S_CH_CTRL_RX_MASK_BITS_SHIFT = 4,
+ I2S_CH_CTRL_RX_MASK_BITS_MASK_US = 7,
+ I2S_CH_CTRL_RX_MASK_BITS_MASK = I2S_CH_CTRL_RX_MASK_BITS_MASK_US <<
+ I2S_CH_CTRL_RX_MASK_BITS_SHIFT,
+
+ I2S_CH_CTRL_TX_MASK_BITS_SHIFT = 0,
+ I2S_CH_CTRL_TX_MASK_BITS_MASK_US = 7,
+ I2S_CH_CTRL_TX_MASK_BITS_MASK = I2S_CH_CTRL_TX_MASK_BITS_MASK_US <<
+ I2S_CH_CTRL_TX_MASK_BITS_SHIFT,
+
+ /* Number of slots in frame, minus 1 */
+ I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT = 16,
+ I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US = 7,
+ I2S_SLOT_CTRL_TOTAL_SLOTS_MASK = I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US <<
+ I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT,
+
+ /* TDM mode slot enable bitmask */
+ I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT = 8,
+ I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK =
+ 0xff << I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT,
+
+ I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT = 0,
+ I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK = 0xff <<
+ I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT,
+
+ I2S_FILTER_LINEAR = 0,
+ I2S_FILTER_QUAD = 1,
+
+ I2S_FLOWCTL_FILTER_SHIFT = 31,
+ I2S_FLOWCTL_FILTER_MASK = 1 << I2S_FLOWCTL_FILTER_SHIFT,
+ I2S_FLOWCTL_FILTER_LINEAR = I2S_FILTER_LINEAR <<
+ I2S_FLOWCTL_FILTER_SHIFT,
+ I2S_FLOWCTL_FILTER_QUAD = I2S_FILTER_QUAD << I2S_FLOWCTL_FILTER_SHIFT,
+
+ I2S_TX_STEP_SHIFT = 0,
+ I2S_TX_STEP_MASK_US = 0xffff,
+ I2S_TX_STEP_MASK = I2S_TX_STEP_MASK_US << I2S_TX_STEP_SHIFT,
+
+ I2S_FLOW_STATUS_UNDERFLOW = 1 << 31,
+ I2S_FLOW_STATUS_OVERFLOW = 1 << 30,
+ I2S_FLOW_STATUS_MONITOR_INT_EN = 1 << 4,
+ I2S_FLOW_STATUS_COUNTER_CLR = 1 << 3,
+ I2S_FLOW_STATUS_MONITOR_CLR = 1 << 2,
+ I2S_FLOW_STATUS_COUNTER_EN = 1 << 1,
+ I2S_FLOW_STATUS_MONITOR_EN = 1 << 0,
+};
+
+#endif /* _TEGRA_I2C_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA114_PMU_H_
-#define _TEGRA114_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _TEGRA114_PMU_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010-2013
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA124_PMU_H_
-#define _TEGRA124_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _TEGRA124_PMU_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _ARCH_PMU_H_
-#define _ARCH_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _ARCH_PMU_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA210_PMU_H_
-#define _TEGRA210_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _TEGRA210_PMU_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA30_PMU_H_
-#define _TEGRA30_PMU_H_
-
-/* Set core and CPU voltages to nominal levels */
-int pmu_set_nominal(void);
-
-#endif /* _TEGRA30_PMU_H_ */
unsigned int tbl;
unsigned long lastinc;
unsigned long long timer_reset_value;
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long tlb_addr;
unsigned long tlb_size;
#if defined(CONFIG_ARM64)
#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
- !defined(CONFIG_ARCH_BCM63158)
+ !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP)
#include <asm/arch/gpio.h>
#endif
#include <asm-generic/gpio.h>
unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
unsigned long reg1, unsigned long reg2);
+unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
+ unsigned long *reg1, unsigned long reg2,
+ unsigned long reg3);
#endif
#define MACH_TYPE_ECIA 623
#define MACH_TYPE_CM4008 624
#define MACH_TYPE_P2001 625
-#define MACH_TYPE_TWISTER 626
#define MACH_TYPE_MUDSHARK 627
#define MACH_TYPE_HB2 628
#define MACH_TYPE_IQ80332 629
#define MACH_TYPE_VPNEXT_MPU 2747
#define MACH_TYPE_BCMRING_TABLET_V1 2748
#define MACH_TYPE_SGARM10 2749
-#define MACH_TYPE_CM_T3517 2750
#define MACH_TYPE_OMAP3_CPS 2751
#define MACH_TYPE_AXAR1500_RECEIVER 2752
#define MACH_TYPE_WBD222 2753
#define MACH_TYPE_AX8008 2999
#define MACH_TYPE_GNET_SGCE 3000
#define MACH_TYPE_PXWNAS_500_1000 3001
-#define MACH_TYPE_EA20 3002
#define MACH_TYPE_AWM2 3003
#define MACH_TYPE_TI8148EVM 3004
#define MACH_TYPE_SEABOARD 3005
#define MACH_TYPE_SGH_I710 3525
#define MACH_TYPE_INTEGREPROSCB 3526
#define MACH_TYPE_MONZA 3527
-#define MACH_TYPE_CALIMAIN 3528
#define MACH_TYPE_MX6Q_SABREAUTO 3529
#define MACH_TYPE_GMA01X 3530
#define MACH_TYPE_SBC51 3531
#define MACH_TYPE_TAISHAN 3653
#define MACH_TYPE_TOUCHLINK 3654
#define MACH_TYPE_STM32F103ZE 3655
-#define MACH_TYPE_MCX 3656
#define MACH_TYPE_STM_NMHDK_FLI7610 3657
#define MACH_TYPE_TOP28X 3658
#define MACH_TYPE_OKL4VP_MICROVISOR 3659
#define MACH_TYPE_IMXT_NAV 3829
#define MACH_TYPE_IMXT_FULL 3830
#define MACH_TYPE_AG09015 3831
-#define MACH_TYPE_AM3517_MT_VENTOUX 3832
#define MACH_TYPE_DP1ARM9 3833
#define MACH_TYPE_PICASSO_M 3834
#define MACH_TYPE_VIDEO_GADGET 3835
#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
+#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#include <linux/compiler.h>
#include <asm/armv7_mpu.h>
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
DECLARE_GLOBAL_DATA_PTR;
}
#endif
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable (void)
{
return;
}
#endif
-#ifdef CONFIG_SYS_DCACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_enable (void)
{
return;
noncached_end = end;
noncached_next = start;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
#endif
}
* Set up initial C runtime environment and call board_init_f(0).
*/
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
+ ldr r0, =(CONFIG_TPL_STACK)
+#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
* (2) inserts the vector table using ARM_VECTORS as appropriate
*/
#include <asm/arch/boot0.h>
-
#else
/*
#include <common.h>
#define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818
+#define BAREBOX_IMAGE_MAGIC 0x00786f62
struct arm_z_header {
uint32_t code[9];
{
struct arm_z_header *zi = (struct arm_z_header *)image;
- if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) {
+ if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC &&
+ zi->zi_magic != BAREBOX_IMAGE_MAGIC) {
#ifndef CONFIG_SPL_FRAMEWORK
- puts("Bad Linux ARM zImage magic!\n");
+ puts("zimage: Bad magic!\n");
#endif
return 1;
}
}
#if defined(IMAGE_MAX_SIZE)
-ASSERT(__image_copy_end - __start < (IMAGE_MAX_SIZE), \
+ASSERT(__image_copy_end - __start <= (IMAGE_MAX_SIZE), \
"SPL image too big");
#endif
#if defined(CONFIG_SPL_BSS_MAX_SIZE)
-ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
+ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \
"SPL image BSS too big");
#endif
prompt "DaVinci board select"
optional
-config TARGET_IPAM390
- bool "IPAM390 board"
- select MACH_DAVINCI_DA850_EVM
- select SOC_DA850
- select SUPPORT_SPL
-
config TARGET_DA850EVM
bool "DA850 EVM board"
select MACH_DAVINCI_DA850_EVM
select SOC_DA850
select SUPPORT_SPL
-config TARGET_EA20
- bool "EA20 board"
- select BOARD_LATE_INIT
- select MACH_DAVINCI_DA850_EVM
- select SOC_DA850
-
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SOC_DA8XX
select SUPPORT_SPL
-config TARGET_CALIMAIN
- bool "Calimain board"
- select SOC_DA850
-
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
select MACH_DAVINCI_DA850_EVM
endif
-source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/ea20/Kconfig"
-source "board/omicron/calimain/Kconfig"
source "board/lego/ev3/Kconfig"
config SPL_LDSCRIPT
- default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390
default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
endif
obj-$(CONFIG_SOC_DM644X) += dm644x.o
obj-$(CONFIG_SOC_DM646X) += dm646x.o
obj-$(CONFIG_SOC_DA850) += da850_pinmux.o
-obj-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
obj-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
endif
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += lowlevel_init.o
-endif
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV PLLC_PLLDIV1
-#define DDR_PLLDIV PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV PLLC_PLLDIV2
-#define DSP_PLLDIV PLLC_PLLDIV1
-#define DDR_PLLDIV PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DSP_PLLDIV PLLC_PLLDIV1
-#define ARM_PLLDIV PLLC_PLLDIV2
-#define DDR_PLLDIV PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DA8XX
unsigned int sysdiv[9] = {
PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
return 0;
}
-#else /* CONFIG_SOC_DA8XX */
-
-static unsigned pll_div(volatile void *pllbase, unsigned offset)
-{
- u32 div;
-
- div = REG(pllbase + offset);
- return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
-}
-
-static inline unsigned pll_prediv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
- /* this register read seems to fail on pll0 */
- if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
- return 8;
- else
- return pll_div(pllbase, PLLC_PREDIV);
-#elif defined(CONFIG_SOC_DM365)
- return pll_div(pllbase, PLLC_PREDIV);
-#endif
- return 1;
-}
-
-static inline unsigned pll_postdiv(volatile void *pllbase)
-{
-#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
- return pll_div(pllbase, PLLC_POSTDIV);
-#elif defined(CONFIG_SOC_DM6446)
- if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
- return pll_div(pllbase, PLLC_POSTDIV);
-#endif
- return 1;
-}
-
-static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
-{
- volatile void *pllbase = (volatile void *) pll_addr;
-#ifdef CONFIG_SOC_DM646X
- unsigned base = CONFIG_REFCLK_FREQ / 1000;
-#else
- unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
-#endif
-
- /* the PLL might be bypassed */
- if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
- base /= pll_prediv(pllbase);
-#if defined(CONFIG_SOC_DM365)
- base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
-#else
- base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
-#endif
- base /= pll_postdiv(pllbase);
- }
- return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
-}
-
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
-}
-#endif
-
-#if defined(CONFIG_SOC_DM365)
-unsigned int davinci_clk_get(unsigned int div)
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
-}
-#endif
-
-int set_cpu_clk_info(void)
-{
- unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#if defined(CONFIG_SOC_DM365)
- pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#endif
- gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
-
-#ifdef DSP_PLLDIV
- gd->bd->bi_dsp_freq =
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
-#else
- gd->bd->bi_dsp_freq = 0;
-#endif
-
- pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#if defined(CONFIG_SOC_DM365)
- pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#endif
- gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
-
- return 0;
-}
-
-#endif /* !CONFIG_SOC_DA8XX */
-
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SoC-specific code for tms320dm355 and similar chips
- *
- * Copyright (C) 2009 David Brownell
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-
- /* Bringup UART0 out of reset */
- REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_LPSC_I2C);
-
- /* Enable I2C pin Mux */
- REG(PINMUX3) |= (1 << 20) | (1 << 19);
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SoC-specific code for tms320dm365 and similar chips
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-}
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_LPSC_I2C);
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SoC-specific lowlevel code for tms320dm365 and similar chips
- * Actually used for booting from NAND with nand_spl.
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/dm365_lowlevel.h>
-#include <asm/arch/hardware.h>
-
-void dm365_waitloop(unsigned long loopcnt)
-{
- unsigned long i;
-
- for (i = 0; i < loopcnt; i++)
- asm(" NOP");
-}
-
-int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
-{
- unsigned int clksrc = 0x0;
-
- /* Power up the PLL */
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
-
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
- setbits_le32(&dv_pll0_regs->pllctl,
- clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
- /*
- * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
- * through MMR
- */
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
-
- /* Set PLLEN=0 => PLL BYPASS MODE */
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
- dm365_waitloop(150);
-
- /* PLLRST=1(reset assert) */
- setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
- dm365_waitloop(300);
-
- /*Bring PLL out of Reset*/
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
- /* Program the Multiper and Pre-Divider for PLL1 */
- writel(pllmult, &dv_pll0_regs->pllm);
- writel(prediv, &dv_pll0_regs->prediv);
-
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
- PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
- &dv_pll0_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
-
- /* Program the PostDiv for PLL1 */
- writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
-
- /* Post divider setting for PLL1 */
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
-
- dm365_waitloop(300);
-
- /* Set the GOSET bit */
- writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
-
- dm365_waitloop(300);
-
- /* Wait for PLL to LOCK */
- while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
- == PLL0_LOCK))
- ;
-
- /* Enable the PLL Bit of PLLCTL*/
- setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
- return 0;
-}
-
-int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
-{
- unsigned int clksrc = 0x0;
-
- /* Power up the PLL*/
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
-
- /*
- * Select the Clock Mode as Onchip Oscilator or External Clock on
- * MXI pin
- * VDB has input on MXI pin
- */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
- setbits_le32(&dv_pll1_regs->pllctl,
- clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
- /*
- * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
- * through MMR
- */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
-
- /* Set PLLEN=0 => PLL BYPASS MODE */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
- dm365_waitloop(50);
-
- /* PLLRST=1(reset assert) */
- setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
- dm365_waitloop(300);
-
- /* Bring PLL out of Reset */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
- /* Program the Multiper and Pre-Divider for PLL2 */
- writel(pllm, &dv_pll1_regs->pllm);
- writel(prediv, &dv_pll1_regs->prediv);
-
- writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
-
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
- PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
- &dv_pll1_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
-
- /* Post divider setting for PLL2 */
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
-
- /* GoCmd for PostDivider to take effect */
- writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
-
- dm365_waitloop(150);
-
- /* Wait for PLL to LOCK */
- while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
- == PLL1_LOCK))
- ;
-
- dm365_waitloop(4100);
-
- /* Enable the PLL2 */
- setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
- /* do this after PLL's have been set up */
- writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
- &dv_sys_module_regs->peri_clkctl);
-
- return 0;
-}
-
-int dm365_ddr_setup(void)
-{
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
- clrbits_le32(&dv_sys_module_regs->vtpiocr,
- VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
-
- /* Set bit CLRZ (bit 13) */
- setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
-
- /* Check VTP READY Status */
- while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
- ;
-
- /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
- setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
-
- /* Set bit LOCK(bit7) */
- setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
-
- /*
- * Powerdown VTP as it is locked (bit 6)
- * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
- */
- setbits_le32(&dv_sys_module_regs->vtpiocr,
- VPTIO_IOPWRDN | VPTIO_PWRDN);
-
- /* Wait for calibration to complete */
- dm365_waitloop(150);
-
- /* Set the DDR2 to synreset, then enable it again */
- lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-
- /* Program SDRAM Bank Config Register */
- writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
- &dv_ddr2_regs_ctrl->sdbcr);
- writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
- &dv_ddr2_regs_ctrl->sdbcr);
-
- /* Program SDRAM Timing Control Register1 */
- writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
- /* Program SDRAM Timing Control Register2 */
- writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
- writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
-
- writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
-
- /* Program SDRAM Refresh Control Register */
- writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
-
- lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- return 0;
-}
-
-static void dm365_vpss_sync_reset(void)
-{
- unsigned int PdNum = 0;
-
- /* VPSS_CLKMD 1:1 */
- setbits_le32(&dv_sys_module_regs->vpss_clkctl,
- VPSS_CLK_CTL_VPSS_CLKMD);
-
- /* LPSC SyncReset DDR Clock Enable */
- writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
- ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
- &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
-
- writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
- while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
- ;
- while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
- PSC_MD_STATE_MSK) == PSC_SYNCRESET))
- ;
-}
-
-static void dm365_por_reset(void)
-{
- struct davinci_timer *wdog =
- (struct davinci_timer *)DAVINCI_WDOG_BASE;
-
- if (readl(&dv_pll0_regs->rstype) &
- (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
- dm365_vpss_sync_reset();
-
- writel(DV_TMPBUF_VAL, TMPBUF);
- setbits_le32(TMPSTATUS, FLAG_PORRST);
- writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
- writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
- while (1);
- }
-}
-
-static void dm365_wdt_reset(void)
-{
- struct davinci_timer *wdog =
- (struct davinci_timer *)DAVINCI_WDOG_BASE;
-
- if (readl(TMPBUF) != DV_TMPBUF_VAL) {
- writel(DV_TMPBUF_VAL, TMPBUF);
- setbits_le32(TMPSTATUS, FLAG_PORRST);
- setbits_le32(TMPSTATUS, FLAG_FLGOFF);
-
- dm365_waitloop(100);
-
- dm365_vpss_sync_reset();
-
- writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
- writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
- while (1);
- }
-}
-
-static void dm365_wdt_flag_on(void)
-{
- /* VPSS_CLKMD 1:2 */
- clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
- VPSS_CLK_CTL_VPSS_CLKMD);
- writel(0, TMPBUF);
- setbits_le32(TMPSTATUS, FLAG_FLGON);
-}
-
-void dm365_psc_init(void)
-{
- unsigned char i = 0;
- unsigned char lpsc_start;
- unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
- unsigned int PdNum = 0;
-
- lpscmin = 0;
- lpscmax = 2;
-
- for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
- if (lpscgroup == 0) {
- /* Enabling LPSC 3 to 28 SCR first */
- lpsc_start = DAVINCI_LPSC_VPSSMSTR;
- lpsc_end = DAVINCI_LPSC_TIMER1;
- } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
- lpsc_start = DAVINCI_LPSC_CFG5;
- lpsc_end = DAVINCI_LPSC_VPSSMASTER;
- } else {
- lpsc_start = DAVINCI_LPSC_MJCP;
- lpsc_end = DAVINCI_LPSC_HDVICP;
- }
-
- /* NEXT=0x3, Enable LPSC's */
- for (i = lpsc_start; i <= lpsc_end; i++)
- setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
-
- /*
- * Program goctl to start transition sequence for LPSCs
- * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
- * Domain 0 Modules
- */
- writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
- /*
- * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
- */
- while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
- == 0))
- ;
-
- /* Wait for MODSTAT = ENABLE from LPSC's */
- for (i = lpsc_start; i <= lpsc_end; i++)
- while (!((readl(&dv_psc_regs->mdstat[i]) &
- PSC_MD_STATE_MSK) == PSC_ENABLE))
- ;
- }
-}
-
-static void dm365_emif_init(void)
-{
- writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
- writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
-
- setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
-
- writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
-
- return;
-}
-
-void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
- unsigned long value)
-{
- clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
- setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
-}
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
- return;
-}
-
-#if defined(CONFIG_POST)
-int post_log(char *format, ...)
-{
- return 0;
-}
-#endif
-
-void dm36x_lowlevel_init(ulong bootflag)
-{
- struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
- (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
- DAVINCI_UART_CTRL_BASE);
-
- /* Mask all interrupts */
- writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
- writel(0x0, &dv_aintc_regs->eabase);
- writel(0x0, &dv_aintc_regs->eint0);
- writel(0x0, &dv_aintc_regs->eint1);
-
- /* Clear all interrupts */
- writel(0xffffffff, &dv_aintc_regs->fiq0);
- writel(0xffffffff, &dv_aintc_regs->fiq1);
- writel(0xffffffff, &dv_aintc_regs->irq0);
- writel(0xffffffff, &dv_aintc_regs->irq1);
-
- dm365_por_reset();
- dm365_wdt_reset();
-
- /* System PSC setup - enable all */
- dm365_psc_init();
-
- /* Setup Pinmux */
- dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
- dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
- dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
- dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
- dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
-
- /* PLL setup */
- dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
- CONFIG_SYS_DM36x_PLL1_PREDIV);
- dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
- CONFIG_SYS_DM36x_PLL2_PREDIV);
-
- /* GPIO setup */
- board_gpio_init();
-
- NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
- /*
- * Fix Power and Emulation Management Register
- * see sprufh2.pdf page 38 Table 22
- */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
- &davinci_uart_ctrl_regs->pwremu_mgmt);
-
- puts("ddr init\n");
- dm365_ddr_setup();
-
- puts("emif init\n");
- dm365_emif_init();
-
- dm365_wdt_flag_on();
-
-#if defined(CONFIG_POST)
- /*
- * Do memory tests, calls arch_memory_failure_handle()
- * if error detected.
- */
- memory_post_test(0);
-#endif
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SoC-specific code for tms320dm644x chips
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5 (1 << 11)
-#define PINMUX0_AECS4 (1 << 10)
-
-#define PINMUX1_I2C (1 << 7)
-#define PINMUX1_UART1 (1 << 1)
-#define PINMUX1_UART0 (1 << 0)
-
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-
- /* Bringup UART0 out of reset */
- REG(UART0_PWREMU_MGMT) = 0x00006001;
-
- /* Enable UART0 MUX lines */
- REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
- lpsc_on(DAVINCI_LPSC_EMAC);
- lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
- lpsc_on(DAVINCI_LPSC_MDIO);
-
- /* Enable GIO3.3V cells used for EMAC */
- REG(VDD3P3V_PWDN) = 0;
-
- /* Enable EMAC. */
- REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_LPSC_I2C);
-
- /* Enable I2C pin Mux */
- REG(PINMUX1) |= PINMUX1_I2C;
-}
-#endif
-
-void davinci_errata_workarounds(void)
-{
- /*
- * Workaround for TMS320DM6446 errata 1.3.22:
- * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
- * Revision(s) Affected: 1.3 and earlier
- */
- REG(PSC_SILVER_BULLET) = 0;
-
- /*
- * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
- * as suggested in TMS320DM6446 errata 2.1.2:
- *
- * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
- * low priority modules can occupy the bus and prevent high priority
- * modules like the VPSS from getting the required DDR2 throughput.
- * A hex value of 0x20 should provide a good ARM (cache enabled)
- * performance and still allow good utilization by the VPSS or other
- * modules.
- */
- REG(VBPR) = 0x20;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SoC-specific code for TMS320DM646x chips
- */
-
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_DM646X_LPSC_UART0);
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
- lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_DM646X_LPSC_I2C);
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- */
-
-#include <common.h>
-#include <net.h>
-#include <dp83848.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../drivers/net/ti/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int dp83848_is_phy_connected(int phy_addr)
-{
- u_int16_t id1, id2;
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
- return(0);
- if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
- return(0);
-
- if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
- return(1);
-
- return(0);
-}
-
-int dp83848_get_link_speed(int phy_addr)
-{
- u_int16_t tmp;
- volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
- return(0);
-
- if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
- return(0);
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
- return(0);
-
- /* Speed doesn't matter, there is no setting for it in EMAC... */
- if (tmp & DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
-}
-
-
-int dp83848_init_phy(int phy_addr)
-{
- int ret = 1;
-
- if (!dp83848_get_link_speed(phy_addr)) {
- /* Try another time */
- udelay(100000);
- ret = dp83848_get_link_speed(phy_addr);
- }
-
- /* Disable PHY Interrupts */
- davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
-
- return(ret);
-}
-
-
-int dp83848_auto_negotiate(int phy_addr)
-{
- u_int16_t tmp;
-
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
- return(0);
-
- /* Restart Auto_negotiation */
- tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
- tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
- davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
- /* Set the Auto_negotiation Advertisement Register
- * MII advertising for Next page, 100BaseTxFD and HD,
- * 10BaseTFD and HD, IEEE 802.3
- */
- tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
- DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
- davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
-
-
- /* Read Control Register */
- if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
- return(0);
-
- tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
- davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
- /* Restart Auto_negotiation */
- tmp |= DP83848_RESTART_AUTONEG;
- davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
- /*check AutoNegotiate complete */
- udelay(10000);
- if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
- return(0);
-
- if (!(tmp & DP83848_AUTONEG_COMP))
- return(0);
-
- return (dp83848_get_link_speed(phy_addr));
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../drivers/net/ti/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
-
-#define MII_PHY_CONFIG_REG 22
-
-/* PHY Config bits */
-#define PHY_SYS_CLK_EN (1 << 4)
-
-int et1011c_get_link_speed(int phy_addr)
-{
- u_int16_t data;
-
- if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
- davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
- /* Enable 125MHz clock sourced from PHY */
- davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
- data | PHY_SYS_CLK_EN);
- return (1);
- }
- return (0);
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
#define DA8XX_USB_VBUS_GPIO (1 << 15)
-int usb_phy_on(void);
-void usb_phy_off(void);
-
#endif /* __DA8XX_MUSB_H__ */
int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
int n_items);
-#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
+#if defined(CONFIG_DRIVER_TI_EMAC)
void davinci_emac_mii_mode_sel(int mode_sel);
#endif
-#if defined(CONFIG_SOC_DA8XX)
void irq_init(void);
int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
const int n_items);
-#endif
#endif /* __MISC_H */
#include <asm/arch/hardware.h>
-#ifdef CONFIG_SOC_DM365
-#define EMAC_BASE_ADDR (0x01d07000)
-#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
-#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
-#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
-#define DAVINCI_EMAC_VERSION2
-#elif defined(CONFIG_SOC_DA8XX)
#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
#define DAVINCI_EMAC_VERSION2
-#else
-#define EMAC_BASE_ADDR (0x01c80000)
-#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
-#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
-#define EMAC_MDIO_BASE_ADDR (0x01c84000)
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DAVINCI_EMAC_VERSION2
-#define DAVINCI_EMAC_GIG_ENABLE
-#endif
-#ifdef CONFIG_SOC_DM646X
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ 76500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
-#elif defined(CONFIG_SOC_DM365)
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ 121500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
-#elif defined(CONFIG_SOC_DA8XX)
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
-#else
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
-#endif
-
-#define PHY_KSZ8873 (0x00221450)
-int ksz8873_is_phy_connected(int phy_addr);
-int ksz8873_get_link_speed(int phy_addr);
-int ksz8873_init_phy(int phy_addr);
-int ksz8873_auto_negotiate(int phy_addr);
-
-#define PHY_LXT972 (0x001378e2)
-int lxt972_is_phy_connected(int phy_addr);
-int lxt972_get_link_speed(int phy_addr);
-int lxt972_init_phy(int phy_addr);
-int lxt972_auto_negotiate(int phy_addr);
-
-#define PHY_DP83848 (0x20005c90)
-int dp83848_is_phy_connected(int phy_addr);
-int dp83848_get_link_speed(int phy_addr);
-int dp83848_init_phy(int phy_addr);
-int dp83848_auto_negotiate(int phy_addr);
-
-#define PHY_ET1011C (0x282f013)
-int et1011c_get_link_speed(int phy_addr);
#endif /* _DM644X_EMAC_H_ */
#ifndef _GPIO_DEFS_H_
#define _GPIO_DEFS_H_
-#ifndef CONFIG_SOC_DA8XX
-#define DAVINCI_GPIO_BINTEN 0x01C67008
-#define DAVINCI_GPIO_BANK01 0x01C67010
-#define DAVINCI_GPIO_BANK23 0x01C67038
-#define DAVINCI_GPIO_BANK45 0x01C67060
-#define DAVINCI_GPIO_BANK67 0x01C67088
-
-#else /* CONFIG_SOC_DA8XX */
#define DAVINCI_GPIO_BINTEN 0x01E26008
#define DAVINCI_GPIO_BANK01 0x01E26010
#define DAVINCI_GPIO_BANK23 0x01E26038
#define DAVINCI_GPIO_BANK45 0x01E26060
#define DAVINCI_GPIO_BANK67 0x01E26088
#define DAVINCI_GPIO_BANK8 0x01E260B0
-#endif /* CONFIG_SOC_DA8XX */
#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
#define gpio_status() gpio_info()
#endif
#define GPIO_NAME_SIZE 20
-#if defined(CONFIG_SOC_DM644X)
-/* GPIO0 to GPIO53, omit the V3.3 volts one */
-#define MAX_NUM_GPIOS 70
-#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
+#if !defined(CONFIG_SOC_DA850)
#define MAX_NUM_GPIOS 128
#else
#define MAX_NUM_GPIOS 144
typedef volatile unsigned int * dv_reg_p;
#endif
-/*
- * Base register addresses
- *
- * NOTE: some of these DM6446-specific addresses DO NOT WORK
- * on other DaVinci chips. Double check them before you try
- * using the addresses ... or PSC module identifiers, etc.
- */
-#ifndef CONFIG_SOC_DA8XX
-
-#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
-#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
-#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
-#define DAVINCI_UART0_BASE (0x01c20000)
-#define DAVINCI_UART1_BASE (0x01c20400)
-#define DAVINCI_TIMER3_BASE (0x01c20800)
-#define DAVINCI_I2C_BASE (0x01c21000)
-#define DAVINCI_TIMER0_BASE (0x01c21400)
-#define DAVINCI_TIMER1_BASE (0x01c21800)
-#define DAVINCI_WDOG_BASE (0x01c21c00)
-#define DAVINCI_PWM0_BASE (0x01c22000)
-#define DAVINCI_PWM1_BASE (0x01c22400)
-#define DAVINCI_PWM2_BASE (0x01c22800)
-#define DAVINCI_TIMER4_BASE (0x01c23800)
-#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
-#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
-#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
-#define DAVINCI_ARM_INTC_BASE (0x01c48000)
-#define DAVINCI_USB_OTG_BASE (0x01c64000)
-#define DAVINCI_CFC_ATA_BASE (0x01c66000)
-#define DAVINCI_SPI_BASE (0x01c66800)
-#define DAVINCI_GPIO_BASE (0x01c67000)
-#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
-#if !defined(CONFIG_SOC_DM646X)
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
-#endif
-#define DAVINCI_DDR_BASE (0x80000000)
-
-#ifdef CONFIG_SOC_DM644X
-#define DAVINCI_UART2_BASE 0x01c20800
-#define DAVINCI_UHPI_BASE 0x01c67800
-#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
-#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
-#define DAVINCI_IMCOP_BASE 0x01cc0000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
-#define DAVINCI_VLYNQ_BASE 0x01e01000
-#define DAVINCI_ASP_BASE 0x01e02000
-#define DAVINCI_MMC_SD_BASE 0x01e10000
-#define DAVINCI_MS_BASE 0x01e20000
-#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
-
-#elif defined(CONFIG_SOC_DM355)
-#define DAVINCI_MMC_SD1_BASE 0x01e00000
-#define DAVINCI_ASP0_BASE 0x01e02000
-#define DAVINCI_ASP1_BASE 0x01e04000
-#define DAVINCI_UART2_BASE 0x01e06000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
-#define DAVINCI_MMC_SD0_BASE 0x01e11000
-
-#elif defined(CONFIG_SOC_DM365)
-#define DAVINCI_MMC_SD1_BASE 0x01d00000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
-#define DAVINCI_MMC_SD0_BASE 0x01d11000
-#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
-#define DAVINCI_SPI0_BASE 0x01c66000
-#define DAVINCI_SPI1_BASE 0x01c66800
-
-#elif defined(CONFIG_SOC_DM646X)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
-
-#endif
-
-#else /* CONFIG_SOC_DA8XX */
-
#define DAVINCI_UART0_BASE 0x01c42000
#define DAVINCI_UART1_BASE 0x01d0c000
#define DAVINCI_UART2_BASE 0x01d0d000
#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
-#endif /* CONFIG_SOC_DA8XX */
/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN 0
#define DAVINCI_GPSC_DSPDOMAIN 1
-#ifndef CONFIG_SOC_DA8XX
-
-#define DAVINCI_LPSC_VPSSMSTR 0
-#define DAVINCI_LPSC_VPSSSLV 1
-#define DAVINCI_LPSC_TPCC 2
-#define DAVINCI_LPSC_TPTC0 3
-#define DAVINCI_LPSC_TPTC1 4
-#define DAVINCI_LPSC_EMAC 5
-#define DAVINCI_LPSC_EMAC_WRAPPER 6
-#define DAVINCI_LPSC_MDIO 7
-#define DAVINCI_LPSC_IEEE1394 8
-#define DAVINCI_LPSC_USB 9
-#define DAVINCI_LPSC_ATA 10
-#define DAVINCI_LPSC_VLYNQ 11
-#define DAVINCI_LPSC_UHPI 12
-#define DAVINCI_LPSC_DDR_EMIF 13
-#define DAVINCI_LPSC_AEMIF 14
-#define DAVINCI_LPSC_MMC_SD 15
-#define DAVINCI_LPSC_MEMSTICK 16
-#define DAVINCI_LPSC_McBSP 17
-#define DAVINCI_LPSC_I2C 18
-#define DAVINCI_LPSC_UART0 19
-#define DAVINCI_LPSC_UART1 20
-#define DAVINCI_LPSC_UART2 21
-#define DAVINCI_LPSC_SPI 22
-#define DAVINCI_LPSC_PWM0 23
-#define DAVINCI_LPSC_PWM1 24
-#define DAVINCI_LPSC_PWM2 25
-#define DAVINCI_LPSC_GPIO 26
-#define DAVINCI_LPSC_TIMER0 27
-#define DAVINCI_LPSC_TIMER1 28
-#define DAVINCI_LPSC_TIMER2 29
-#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
-#define DAVINCI_LPSC_ARM 31
-#define DAVINCI_LPSC_SCR2 32
-#define DAVINCI_LPSC_SCR3 33
-#define DAVINCI_LPSC_SCR4 34
-#define DAVINCI_LPSC_CROSSBAR 35
-#define DAVINCI_LPSC_CFG27 36
-#define DAVINCI_LPSC_CFG3 37
-#define DAVINCI_LPSC_CFG5 38
-#define DAVINCI_LPSC_GEM 39
-#define DAVINCI_LPSC_IMCOP 40
-#define DAVINCI_LPSC_VPSSMASTER 47
-#define DAVINCI_LPSC_MJCP 50
-#define DAVINCI_LPSC_HDVICP 51
-
-#define DAVINCI_DM646X_LPSC_EMAC 14
-#define DAVINCI_DM646X_LPSC_UART0 26
-#define DAVINCI_DM646X_LPSC_I2C 31
-#define DAVINCI_DM646X_LPSC_TIMER0 34
-
-#else /* CONFIG_SOC_DA8XX */
-
#define DAVINCI_LPSC_TPCC 0
#define DAVINCI_LPSC_TPTC0 1
#define DAVINCI_LPSC_TPTC1 2
#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
-#endif /* CONFIG_SOC_DA8XX */
-
#ifndef __ASSEMBLY__
void lpsc_on(unsigned int id);
void lpsc_syncreset(unsigned int id);
void davinci_enable_i2c(void);
void davinci_errata_workarounds(void);
-#ifndef CONFIG_SOC_DA8XX
-
-/* Some PSC defines */
-#define PSC_CHP_SHRTSW (0x01c40038)
-#define PSC_GBLCTL (0x01c41010)
-#define PSC_EPCPR (0x01c41070)
-#define PSC_EPCCR (0x01c41078)
-#define PSC_PTCMD (0x01c41120)
-#define PSC_PTSTAT (0x01c41128)
-#define PSC_PDSTAT (0x01c41200)
-#define PSC_PDSTAT1 (0x01c41204)
-#define PSC_PDCTL (0x01c41300)
-#define PSC_PDCTL1 (0x01c41304)
-
-#define PSC_MDCTL_BASE (0x01c41a00)
-#define PSC_MDSTAT_BASE (0x01c41800)
-
-#define VDD3P3V_PWDN (0x01c40048)
-#define UART0_PWREMU_MGMT (0x01c20030)
-
-#define PSC_SILVER_BULLET (0x01c41a20)
-
-#else /* CONFIG_SOC_DA8XX */
-
#define PSC_ENABLE 0x3
#define PSC_DISABLE 0x2
#define PSC_SYNCRESET 0x1
#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
-#endif /* CONFIG_SOC_DA8XX */
-
#define PSC_MDSTAT_STATE 0x3f
#define PSC_MDCTL_NEXT 0x07
-#ifndef CONFIG_SOC_DA8XX
-
-/* Miscellania... */
-#define VBPR (0x20000020)
-
-/* NOTE: system control modules are *highly* chip-specific, both
- * as to register content (e.g. for muxing) and which registers exist.
- */
-#define PINMUX0 0x01c40000
-#define PINMUX1 0x01c40004
-#define PINMUX2 0x01c40008
-#define PINMUX3 0x01c4000c
-#define PINMUX4 0x01c40010
-
-struct davinci_uart_ctrl_regs {
- dv_reg revid1;
- dv_reg res;
- dv_reg pwremu_mgmt;
- dv_reg mdr;
-};
-
-#define DAVINCI_UART_CTRL_BASE 0x28
-
-/* UART PWREMU_MGMT definitions */
-#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
-#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
-#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
-
-#else /* CONFIG_SOC_DA8XX */
-
struct davinci_pllc_regs {
dv_reg revid;
dv_reg rsvd1[56];
DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
}
-#endif /* CONFIG_SOC_DA8XX */
-
-#if defined(CONFIG_SOC_DM365)
-#include <asm/arch/aintc_defs.h>
-#include <asm/arch/ddr2_defs.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pll_defs.h>
-#include <asm/arch/psc_defs.h>
-#include <asm/arch/syscfg_defs.h>
-#include <asm/arch/timer_defs.h>
-
-#define TMPBUF 0x00017ff8
-#define TMPSTATUS 0x00017ff0
-#define DV_TMPBUF_VAL 0x591b3ed7
-#define FLAG_PORRST 0x00000001
-#define FLAG_WDTRST 0x00000002
-#define FLAG_FLGON 0x00000004
-#define FLAG_FLGOFF 0x00000010
-
-#endif
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_ARCH_HARDWARE_H */
#ifndef _I2C_DEFS_H_
#define _I2C_DEFS_H_
-#ifndef CONFIG_SOC_DA8XX
-#define I2C_BASE 0x01c21000
-#else
#define I2C_BASE 0x01c22000
-#endif
#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-#ifndef _DV_SYSCFG_DEFS_H_
-#define _DV_SYSCFG_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-/* System Control Module register structure for DM365 */
-struct dv_sys_module_regs {
- unsigned int pinmux[5]; /* 0x00 */
- unsigned int bootcfg; /* 0x14 */
- unsigned int arm_intmux; /* 0x18 */
- unsigned int edma_evtmux; /* 0x1C */
- unsigned int ddr_slew; /* 0x20 */
- unsigned int clkout; /* 0x24 */
- unsigned int device_id; /* 0x28 */
- unsigned int vdac_config; /* 0x2C */
- unsigned int timer64_ctl; /* 0x30 */
- unsigned int usbbphy_ctl; /* 0x34 */
- unsigned int misc; /* 0x38 */
- unsigned int mstpri[2]; /* 0x3C */
- unsigned int vpss_clkctl; /* 0x44 */
- unsigned int peri_clkctl; /* 0x48 */
- unsigned int deepsleep; /* 0x4C */
- unsigned int dft_enable; /* 0x50 */
- unsigned int debounce[8]; /* 0x54 */
- unsigned int vtpiocr; /* 0x74 */
- unsigned int pupdctl0; /* 0x78 */
- unsigned int pupdctl1; /* 0x7C */
- unsigned int hdimcopbt; /* 0x80 */
- unsigned int pll0_config; /* 0x84 */
- unsigned int pll1_config; /* 0x88 */
-};
-
-#define VPTIO_RDY (1 << 15)
-#define VPTIO_IOPWRDN (1 << 14)
-#define VPTIO_CLRZ (1 << 13)
-#define VPTIO_LOCK (1 << 7)
-#define VPTIO_PWRDN (1 << 6)
-
-#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
-
-#define dv_sys_module_regs \
- ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
-
-#endif /* !CONFIG_SOC_DA8XX */
-#endif /* _DV_SYSCFG_DEFS_H_ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Micrel KSZ8873 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2011 Heiko Schocher <hsdenx.de>
- *
- * based on:
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <net.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/io.h>
-#include "../../../drivers/net/ti/davinci_emac.h"
-
-int ksz8873_is_phy_connected(int phy_addr)
-{
- u_int16_t dummy;
-
- return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
-}
-
-int ksz8873_get_link_speed(int phy_addr)
-{
- emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
- /* we always have a link to the switch, 100 FD */
- writel((EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
- &emac->MACCONTROL);
- return 1;
-}
-
-
-int ksz8873_init_phy(int phy_addr)
-{
- return 1;
-}
-
-
-int ksz8873_auto_negotiate(int phy_addr)
-{
- return dp83848_get_link_speed(phy_addr);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Low-level board setup code for TI DaVinci SoC based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- */
-
-#include <config.h>
-
-#define MDSTAT_STATE 0x3f
-
-.globl lowlevel_init
-lowlevel_init:
-#ifdef CONFIG_SOC_DM644X
-
- /*-------------------------------------------------------*
- * Mask all IRQs by setting all bits in the EINT default *
- *-------------------------------------------------------*/
- mov r1, $0
- ldr r0, =EINT_ENABLE0
- str r1, [r0]
- ldr r0, =EINT_ENABLE1
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Put the GEM in reset *
- *------------------------------------------------------*/
-
- /* Put the GEM in reset */
- ldr r8, PSC_GEM_FLAG_CLEAR
- ldr r6, MDCTL_GEM
- ldr r7, [r6]
- and r7, r7, r8
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x02
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x02
- bne checkStatClkStopGem
-
- /* Check for GEM Reset Completion */
-checkGemStatClkStop:
- ldr r6, MDSTAT_GEM
- ldr r7, [r6]
- ands r7, r7, $0x100
- bne checkGemStatClkStop
-
- /* Do this for enabling a WDT initiated reset this is a workaround
- for a chip bug. Not required under normal situations */
- ldr r6, P1394
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * Enable L1 & L2 Memories in Fast mode *
- *------------------------------------------------------*/
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, MMARG_BRF0
- ldr r10, MMARG_BRF0_VAL
- str r10, [r6]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * DDR2 PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r10, $0
- ldr r6, PLL2_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r10, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-WaitPPL2Loop:
- subs r10, r10, $1
- bne WaitPPL2Loop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL2_PLLM
- mov r2, $0x17 /* 162 MHz */
- str r2, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV2
- mov r3, $0x01
- str r3, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV1
- mov r4, $0x0b /* 54 MHz */
- str r4, [r6]
-
- /* PLL2 DIV2 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV2
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop_0:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop_0
-
- /* PLL2 DIV1 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV1
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0x218
-ResetPPL2Loop:
- subs r10, r10, $1
- bne ResetPPL2Loop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-PLL2Lock:
- subs r10, r10, $1
- bne PLL2Lock
-
- /* Enable the PLL */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x01
- str r8, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkStop
-
- /*------------------------------------------------------*
- * Program DDR2 MMRs for 162MHz Setting *
- *------------------------------------------------------*/
-
- /* Program PHY Control Register */
- ldr r6, DDRCTL
- ldr r7, DDRCTL_VAL
- str r7, [r6]
-
- /* Program SDRAM Bank Config Register */
- ldr r6, SDCFG
- ldr r7, SDCFG_VAL
- str r7, [r6]
-
- /* Program SDRAM TIM-0 Config Register */
- ldr r6, SDTIM0
- ldr r7, SDTIM0_VAL_162MHz
- str r7, [r6]
-
- /* Program SDRAM TIM-1 Config Register */
- ldr r6, SDTIM1
- ldr r7, SDTIM1_VAL_162MHz
- str r7, [r6]
-
- /* Program the SDRAM Bank Config Control Register */
- ldr r10, MASK_VAL
- ldr r8, SDCFG
- ldr r9, SDCFG_VAL
- and r9, r9, r10
- str r9, [r8]
-
- /* Program SDRAM SDREF Config Register */
- ldr r6, SDREF
- ldr r7, SDREF_VAL
- str r7, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Issue a Dummy DDR2 read/write */
- ldr r8, DDR2_START_ADDR
- ldr r7, DUMMY_VAL
- str r7, [r8]
- ldr r7, [r8]
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x01
- bne checkDDRStatClkStop2
-
- /*------------------------------------------------------*
- * Turn DDR2 Controller Clocks On *
- *------------------------------------------------------*/
-
- /* Enable the DDR2 LPSC Module */
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkEn2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkEn2
-
- /* DDR Writes and Reads */
- ldr r6, CFGTEST
- mov r3, $0x01
- str r3, [r6]
-
- /*------------------------------------------------------*
- * System PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r2, $0
- ldr r6, PLL1_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r2, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-
-WaitLoop:
- subs r10, r10, $1
- bne WaitLoop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Disable the PLL */
- orr r8, r8, $0x10
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL1_PLLM
- mov r3, $0x15 /* For 594MHz */
- str r3, [r6]
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0xff
-
-ResetLoop:
- subs r10, r10, $1
- bne ResetLoop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL1_CTL
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-
-PLL1Lock:
- subs r10, r10, $1
- bne PLL1Lock
-
- /* Enable the PLL */
- orr r8, r8, $0x01
- str r8, [r6]
-
- nop
- nop
- nop
- nop
-
- /*------------------------------------------------------*
- * AEMIF configuration for NOR Flash (double check) *
- *------------------------------------------------------*/
- ldr r0, _PINMUX0
- ldr r1, _DEV_SETTING
- str r1, [r0]
-
- ldr r0, WAITCFG
- ldr r1, WAITCFG_VAL
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
-
- ldr r0, ACFG3
- ldr r1, ACFG3_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG4
- ldr r1, ACFG4_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG5
- ldr r1, ACFG5_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- /*--------------------------------------*
- * VTP manual Calibration *
- *--------------------------------------*/
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR0
- str r1, [r0]
-
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR1
- str r1, [r0]
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTPLock:
- subs r10, r10, $1
- bne VTPLock
-
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, DDRVTPR
- ldr r7, [r6]
- mov r8, r7, LSL #32-10
- mov r8, r8, LSR #32-10 /* grab low 10 bits */
- ldr r7, VTP_RECAL
- orr r8, r7, r8
- ldr r7, VTP_EN
- orr r8, r7, r8
- str r8, [r0]
-
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTP1Lock:
- subs r10, r10, $1
- bne VTP1Lock
-
- ldr r1, [r0]
- ldr r2, VTP_MASK
- and r2, r1, r2
- str r2, [r0]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*
- * Call board-specific lowlevel init.
- * That MUST be present and THAT returns
- * back to arch calling code with "mov pc, lr."
- */
- b dv_board_init
-
-.ltorg
-
-_PINMUX0:
- .word 0x01c40000 /* Device Configuration Registers */
-_PINMUX1:
- .word 0x01c40004 /* Device Configuration Registers */
-
-_DEV_SETTING:
- .word 0x00000c1f
-
-WAITCFG:
- .word 0x01e00004
-WAITCFG_VAL:
- .word 0
-ACFG3:
- .word 0x01e00014
-ACFG3_VAL:
- .word 0x3ffffffd
-ACFG4:
- .word 0x01e00018
-ACFG4_VAL:
- .word 0x3ffffffd
-ACFG5:
- .word 0x01e0001c
-ACFG5_VAL:
- .word 0x3ffffffd
-
-MDCTL_DDR2:
- .word 0x01c41a34
-MDSTAT_DDR2:
- .word 0x01c41834
-
-PTCMD:
- .word 0x01c41120
-PTSTAT:
- .word 0x01c41128
-
-EINT_ENABLE0:
- .word 0x01c48018
-EINT_ENABLE1:
- .word 0x01c4801c
-
-PSC_FLAG_CLEAR:
- .word 0xffffffe0
-PSC_GEM_FLAG_CLEAR:
- .word 0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
- .word 0x200000e4
-DDRCTL_VAL:
- .word 0x50006405
-SDREF:
- .word 0x2000000c
-SDREF_VAL:
- .word 0x000005c3
-SDCFG:
- .word 0x20000008
-SDCFG_VAL:
-#ifdef DDR_4BANKS
- .word 0x00178622
-#elif defined DDR_8BANKS
- .word 0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
- .word 0x20000010
-SDTIM0_VAL_162MHz:
- .word 0x28923211
-SDTIM1:
- .word 0x20000014
-SDTIM1_VAL_162MHz:
- .word 0x0016c722
-VTPIOCR:
- .word 0x200000f0 /* VTP IO Control register */
-DDRVTPR:
- .word 0x01c42030 /* DDR VPTR MMR */
-VTP_MMR0:
- .word 0x201f
-VTP_MMR1:
- .word 0xa01f
-DFT_ENABLE:
- .word 0x01c4004c
-VTP_LOCK_COUNT:
- .word 0x5b0
-VTP_MASK:
- .word 0xffffdfff
-VTP_RECAL:
- .word 0x08000
-VTP_EN:
- .word 0x02000
-CFGTEST:
- .word 0x80010000
-MASK_VAL:
- .word 0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
- .word 0x01c41a9c
-MDSTAT_GEM:
- .word 0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
- .word 0x01c41a20
-
-PLL_CLKSRC_MASK:
- .word 0xfffffeff /* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
- .word 0xffffffdf /* Select the PLLEN source */
-PLL_BYPASS_MASK:
- .word 0xfffffffe /* Put the PLL in BYPASS */
-PLL_RESET_MASK:
- .word 0xfffffff7 /* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
- .word 0xfffffffd /* PLL Power up Mask Bit */
-PLL_DISABLE_ENABLE_MASK:
- .word 0xffffffef /* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
- .word 0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
- .word 0x01c40900
-PLL1_PLLM:
- .word 0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
- .word 0x01c40d00
-PLL2_PLLM:
- .word 0x01c40d10
-PLL2_DIV1:
- .word 0x01c40d18
-PLL2_DIV2:
- .word 0x01c40d1c
-PLL2_PLLCMD:
- .word 0x01c40d38
-PLL2_PLLSTAT:
- .word 0x01c40d3c
-PLL2_DIV_MASK:
- .word 0xffff7fff
-
-MMARG_BRF0:
- .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
- .word 0x00444400
-
-DDR2_START_ADDR:
- .word 0x80000000
-DUMMY_VAL:
- .word 0xa55aa55a
-#else /* CONFIG_SOC_DM644X */
- mov pc, lr
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Intel LXT971/LXT972 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <lxt971a.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../drivers/net/ti/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int lxt972_is_phy_connected(int phy_addr)
-{
- u_int16_t id1, id2;
-
- if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
- return(0);
- if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
- return(0);
-
- if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0))
- return(1);
-
- return(0);
-}
-
-int lxt972_get_link_speed(int phy_addr)
-{
- u_int16_t stat1, tmp;
- volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
- if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
- return(0);
-
- if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */
- return(0);
-
- if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
- return(0);
-
- tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
-
- davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
- /* Read back */
- if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
- return(0);
-
- /* Speed doesn't matter, there is no setting for it in EMAC... */
- if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
-}
-
-
-int lxt972_init_phy(int phy_addr)
-{
- int ret = 1;
-
- if (!lxt972_get_link_speed(phy_addr)) {
- /* Try another time */
- ret = lxt972_get_link_speed(phy_addr);
- }
-
- /* Disable PHY Interrupts */
- davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
-
- return(ret);
-}
-
-
-int lxt972_auto_negotiate(int phy_addr)
-{
- u_int16_t tmp;
-
- if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
- return(0);
-
- /* Restart Auto_negotiation */
- tmp |= BMCR_ANRESTART;
- davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
-
- /*check AutoNegotiate complete */
- udelay (10000);
- if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
- return(0);
-
- if (!(tmp & BMSR_ANEGCOMPLETE))
- return(0);
-
- return (lxt972_get_link_speed(phy_addr));
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
/*
* Set the mii mode as MII or RMII
*/
-#if defined(CONFIG_SOC_DA8XX)
void davinci_emac_mii_mode_sel(int mode_sel)
{
int val;
val |= (1 << 8);
writel(val, &davinci_syscfg_regs->cfgchip3);
}
-#endif
+
/*
* If there is no MAC address in the environment, then it will be initialized
* (silently) from the value in the EEPROM.
}
#endif /* CONFIG_DRIVER_TI_EMAC */
-#if defined(CONFIG_SOC_DA8XX)
void irq_init(void)
{
/*
return 0;
}
-#endif
static void lpsc_transition(unsigned int id, unsigned int state)
{
dv_reg_p mdstat, mdctl, ptstat, ptcmd;
-#ifdef CONFIG_SOC_DA8XX
struct davinci_psc_regs *psc_regs;
-#endif
-#ifndef CONFIG_SOC_DA8XX
- if (id >= DAVINCI_LPSC_GEM)
- return; /* Don't work on DSP Power Domain */
-
- mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
- mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
- ptstat = REG_P(PSC_PTSTAT);
- ptcmd = REG_P(PSC_PTCMD);
-#else
if (id < DAVINCI_LPSC_PSC1_BASE) {
if (id >= PSC_PSC0_MODULE_ID_CNT)
return;
}
ptstat = &psc_regs->ptstat;
ptcmd = &psc_regs->ptcmd;
-#endif
while (readl(ptstat) & 0x01)
continue;
return; /* Already in that state */
writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
-
- switch (id) {
-#ifdef CONFIG_SOC_DM644X
- /* Special treatment for some modules as for sprue14 p.7.4.2 */
- case DAVINCI_LPSC_VPSSSLV:
- case DAVINCI_LPSC_EMAC:
- case DAVINCI_LPSC_EMAC_WRAPPER:
- case DAVINCI_LPSC_MDIO:
- case DAVINCI_LPSC_USB:
- case DAVINCI_LPSC_ATA:
- case DAVINCI_LPSC_VLYNQ:
- case DAVINCI_LPSC_UHPI:
- case DAVINCI_LPSC_DDR_EMIF:
- case DAVINCI_LPSC_AEMIF:
- case DAVINCI_LPSC_MMC_SD:
- case DAVINCI_LPSC_MEMSTICK:
- case DAVINCI_LPSC_McBSP:
- case DAVINCI_LPSC_GPIO:
- writel(readl(mdctl) | 0x200, mdctl);
- break;
-#endif
- }
-
writel(0x01, ptcmd);
while (readl(ptstat) & 0x01)
{
lpsc_transition(id, 0x0);
}
-
-/* Not all DaVinci chips have a DSP power domain. */
-#ifdef CONFIG_SOC_DM644X
-
-/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-void dsp_on(void)
-{
- int i;
-
- if (REG(PSC_PDSTAT1) & 0x1f)
- return; /* Already on */
-
- REG(PSC_GBLCTL) |= 0x01;
- REG(PSC_PDCTL1) |= 0x01;
- REG(PSC_PDCTL1) &= ~0x100;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
- REG(PSC_PTCMD) = 0x02;
-
- for (i = 0; i < 100; i++) {
- if (REG(PSC_EPCPR) & 0x02)
- break;
- }
-
- REG(PSC_CHP_SHRTSW) = 0x01;
- REG(PSC_PDCTL1) |= 0x100;
- REG(PSC_EPCCR) = 0x02;
-
- for (i = 0; i < 100; i++) {
- if (!(REG(PSC_PTSTAT) & 0x02))
- break;
- }
-
- REG(PSC_GBLCTL) &= ~0x1f;
-}
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-#endif /* have a DSP */
}
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
-void spl_board_init(void)
+void board_init_f(ulong dummy)
{
-#ifdef CONFIG_SOC_DM365
- dm36x_lowlevel_init(0);
-#endif
-#ifdef CONFIG_SOC_DA8XX
arch_cpu_init();
-#endif
+
+ spl_early_init();
+
preloader_console_init();
}
config TARGET_SPRING
bool "Spring board"
select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
select SUPPORT_SPL
config TARGET_SMDK5420
select OF_CONTROL
select PINCTRL
select PINCTRL_EXYNOS7420
- select SPL_DISABLE_OF_CONTROL
select SUPPORT_SPL
endchoice
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
endif
-ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
-BOARD_SIZE_CHECK = \
- @actual=`wc -c $@ | awk '{print $$1}'`; \
- limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
- if test $$actual -gt $$limit; then \
- echo "$@ exceeds file size limit:" >&2 ; \
- echo " limit: $$limit bytes" >&2 ; \
- echo " actual: $$actual bytes" >&2 ; \
- echo " excess: $$((actual - limit)) bytes" >&2; \
- exit 1; \
- fi
-else
-BOARD_SIZE_CHECK =
-endif
-
PLUGIN = board/$(BOARDDIR)/plugin
ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
- $(BOARD_SIZE_CHECK)
ifeq ($(CONFIG_OF_SEPARATE),y)
MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
-obj-$(CONFIG_ARM64) += sip.o
+obj-$(CONFIG_ARM64) += lowlevel.o sip.o
obj-$(CONFIG_MX5) += mx5/
obj-$(CONFIG_MX6) += mx6/
}
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
SPL runs in EL3 mode, it use MU0_A to communicate with SCU.
So we could not reuse the one in dts which is for normal U-Boot.
+config IMX8QM
+ select IMX8
+ select SUPPORT_SPL
+ bool
+
config IMX8QXP
select IMX8
select SUPPORT_SPL
select BOARD_LATE_INIT
select IMX8QXP
+config TARGET_IMX8QM_MEK
+ bool "Support i.MX8QM MEK board"
+ select BOARD_LATE_INIT
+ select IMX8QM
+
endchoice
source "board/freescale/imx8qxp_mek/Kconfig"
+source "board/freescale/imx8qm_mek/Kconfig"
endif
dcache_enable();
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
case MXC_CPU_IMX8QXP:
case MXC_CPU_IMX8QXP_A0:
return "QXP";
+ case MXC_CPU_IMX8QM:
+ return "QM";
default:
return "??";
}
static const struct udevice_id cpu_imx8_ids[] = {
{ .compatible = "arm,cortex-a35" },
+ { .compatible = "arm,cortex-a53" },
{ }
};
int arch_cpu_init(void)
{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
/*
* Init timer at very early state, because sscg pll setting
* will use it
imx_set_wdog_powerdown(false);
}
+ if (is_imx8mq()) {
+ clock_enable(CCGR_OCOTP, 1);
+ if (readl(&ocotp->ctrl) & 0x200)
+ writel(0x200, &ocotp->ctrl_clr);
+ }
+
return 0;
}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+ mrs x0, CurrentEL
+ cmp x0, #8
+ b.eq 1f
+ ret
+1:
+ msr daifclr, #4
+
+ /* set HCR_EL2.AMO to catch SERROR */
+ mrs x0, hcr_el2
+ orr x0, x0, #0x20
+ msr hcr_el2, x0
+ isb
+ ret
+ENDPROC(lowlevel_init)
config TARGET_ZMX25
bool "Support zmx25"
select BOARD_LATE_INIT
- select CPU_ARM926EJS1
+ select CPU_ARM926EJS
endchoice
select DM_I2C
select DM_PMIC
select DM_SERIAL
+ select DM_MMC
+ select BLK
+ select DM_USB
+ select DM_REGULATOR
select MX53
imply CMD_DM
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
select DM_THERMAL
select MX6ULL
+config TARGET_DART_6UL
+ bool "Variscite imx6ULL dart(DART-SOM-6ULL)"
+ select MX6ULL
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_SERIAL
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_DHCOMIMX6
bool "dh_imx6"
select BOARD_EARLY_INIT_F
return regs.regs[0];
}
+
+/*
+ * Do an SMC call to return 2 registers by having reg1 passed in by reference
+ */
+unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
+ unsigned long *reg1, unsigned long reg2,
+ unsigned long reg3)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = id;
+ regs.regs[1] = reg0;
+ regs.regs[2] = *reg1;
+ regs.regs[3] = reg2;
+ regs.regs[4] = reg3;
+
+ smc_call(®s);
+
+ *reg1 = regs.regs[1];
+
+ return regs.regs[0];
+}
$(error "No openssl in $(PATH), consider installing openssl")
endif
-SHA_VALUE= $(shell openssl dgst -sha512 -hex $(obj)/u-boot-spl.bin | sed -e "s/^.*= //g")
IMAGE_SIZE= $(shell cat $(obj)/u-boot-spl.bin | wc -c)
-LOADADDR= $(shell echo $(CONFIG_SPL_TEXT_BASE) | sed -e "s/^0x//g")
MAX_SIZE= $(shell printf "%d" $(CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE))
-# Parameters to get populated into the x509 template
-SED_OPTS= -e s/TEST_IMAGE_LENGTH/$(IMAGE_SIZE)/
-SED_OPTS+= -e s/TEST_IMAGE_SHA_VAL/$(SHA_VALUE)/
-SED_OPTS+= -e s/TEST_CERT_TYPE/1/ # CERT_TYPE_PRIMARY_IMAGE_BIN
-SED_OPTS+= -e s/TEST_BOOT_CORE/$(CONFIG_SYS_K3_BOOT_CORE_ID)/
-SED_OPTS+= -e s/TEST_BOOT_ARCH_WIDTH/32/
-SED_OPTS+= -e s/TEST_BOOT_ADDR/$(LOADADDR)/
-
-# Command to generate ecparam key
-quiet_cmd_genkey = OPENSSL $@
-cmd_genkey = openssl ecparam -out $@ -name prime256v1 -genkey
-
-# Command to generate x509 certificate
-quiet_cmd_gencert = OPENSSL $@
-cmd_gencert = cat $(srctree)/tools/k3_x509template.txt | sed $(SED_OPTS) > u-boot-spl-x509.txt; \
- openssl req -new -x509 -key $(KEY) -nodes -outform DER -out $@ -config u-boot-spl-x509.txt -sha512
-
-# If external key is not provided, generate key using openssl.
ifeq ($(CONFIG_SYS_K3_KEY), "")
-KEY=u-boot-spl-eckey.pem
+KEY=""
# On HS use real key or warn if not available
ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/custMpk.pem),)
KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY))
endif
-u-boot-spl-eckey.pem: FORCE
- $(call if_changed,genkey)
-
# tiboot3.bin is mandated by ROM and ROM only supports R5 boot.
# So restrict tiboot3.bin creation for CPU_V7R.
ifdef CONFIG_CPU_V7R
-u-boot-spl-cert.bin: $(KEY) $(obj)/u-boot-spl.bin image_check FORCE
- $(call if_changed,gencert)
-
image_check: $(obj)/u-boot-spl.bin FORCE
@if [ $(IMAGE_SIZE) -gt $(MAX_SIZE) ]; then \
echo "===============================================" >&2; \
exit 1; \
fi
-tiboot3.bin: u-boot-spl-cert.bin $(obj)/u-boot-spl.bin FORCE
- $(call if_changed,cat)
+tiboot3.bin: image_check FORCE
+ $(srctree)/tools/k3_gen_x509_cert.sh -c 16 -b $(obj)/u-boot-spl.bin \
+ -o $@ -l $(CONFIG_SPL_TEXT_BASE) -k $(KEY)
ALL-y += tiboot3.bin
endif
void enable_caches(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
-/*
- * Disable the dcache. Currently the network driver (mvgbe.c) and USB
- * EHCI driver (ehci-marvell.c) and possibly others rely on the data
- * cache being disabled.
- */
-#define CONFIG_SYS_DCACHE_OFF
/*
* By default kwbimage.cfg from board specific folder is used
#include <asm/armv8/mmu.h>
#include <asm/sections.h>
#include <dm/uclass.h>
-#include <linux/io.h>
#include <dt-bindings/clock/mt8516-clk.h>
DECLARE_GLOBAL_DATA_PTR;
-#define WDOG_SWRST 0x10007014
-#define WDOG_SWRST_KEY 0x1209
-
int dram_init(void)
{
int ret;
void reset_cpu(ulong addr)
{
- while (1) {
- writel(WDOG_SWRST_KEY, WDOG_SWRST);
- mdelay(5);
- }
+ psci_system_reset();
}
int print_cpuinfo(void)
#include <asm/io.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
+#include <usb.h>
+#include <linux/usb/otg.h>
+#include <asm/arch/usb.h>
+#include <usb/dwc2_udc.h>
#include <phy.h>
+#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
/* Enable power gate */
clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
}
+
+#if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
+ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
+static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ struct fdtdec_phandle_args args;
+ const void *blob = gd->fdt_blob;
+ int node, dwc2_node;
+ struct udevice *dev, *clk_dev;
+ struct clk clk;
+ int ret;
+
+ /* find the usb glue node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "amlogic,meson-g12a-usb-ctrl");
+ if (node < 0) {
+ debug("Not found usb-control node\n");
+ return -ENODEV;
+ }
+
+ if (!fdtdec_get_is_enabled(blob, node)) {
+ debug("usb is disabled in the device tree\n");
+ return -ENODEV;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
+ if (ret) {
+ debug("Not found usb-control device\n");
+ return ret;
+ }
+
+ /* find the dwc2 node */
+ dwc2_node = fdt_node_offset_by_compatible(blob, node,
+ "amlogic,meson-g12a-usb");
+ if (dwc2_node < 0) {
+ debug("Not found dwc2 node\n");
+ return -ENODEV;
+ }
+
+ if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
+ debug("dwc2 is disabled in the device tree\n");
+ return -ENODEV;
+ }
+
+ meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
+ if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
+ debug("usbotg: can't get base address\n");
+ return -ENODATA;
+ }
+
+ /* Enable clock */
+ ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
+ "#clock-cells", 0, 0, &args);
+ if (ret) {
+ debug("usbotg has no clocks defined in the device tree\n");
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
+ if (ret)
+ return ret;
+
+ if (args.args_count != 1) {
+ debug("Can't find clock ID in the device tree\n");
+ return -ENODATA;
+ }
+
+ clk.dev = clk_dev;
+ clk.id = args.args[0];
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ debug("Failed to enable usbotg clock\n");
+ return ret;
+ }
+
+ meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
+ "g-rx-fifo-size", 0);
+ meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
+ "g-np-tx-fifo-size", 0);
+ meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
+ "g-tx-fifo-size", 0);
+
+ /* Switch to peripheral mode */
+ ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
+ if (ret)
+ return ret;
+
+ return dwc2_udc_probe(&meson_g12a_dwc2_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ const void *blob = gd->fdt_blob;
+ struct udevice *dev;
+ int node;
+ int ret;
+
+ /* find the usb glue node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "amlogic,meson-g12a-usb-ctrl");
+ if (node < 0)
+ return -ENODEV;
+
+ if (!fdtdec_get_is_enabled(blob, node))
+ return -ENODEV;
+
+ ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
+ if (ret)
+ return ret;
+
+ /* Switch to OTG mode */
+ ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
GX_ETH_REG_0_TX_RATIO(4) |
GX_ETH_REG_0_PHY_CLK_EN |
GX_ETH_REG_0_CLK_EN);
+
+ /* Reset to external PHY */
+ if(!IS_ENABLED(CONFIG_MESON_GXBB))
+ writel(0x2009087f, GX_ETH_REG_3);
+
break;
case PHY_INTERFACE_MODE_RMII:
out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
GX_ETH_REG_0_CLK_EN);
- /* Use GXL RMII Internal PHY */
- if (IS_ENABLED(CONFIG_MESON_GXL) &&
- (flags & MESON_USE_INTERNAL_RMII_PHY)) {
- writel(0x10110181, GX_ETH_REG_2);
- writel(0xe40908ff, GX_ETH_REG_3);
+ /* Use GXL RMII Internal PHY (also on GXM) */
+ if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
+ if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
+ writel(0x10110181, GX_ETH_REG_2);
+ writel(0xe40908ff, GX_ETH_REG_3);
+ } else
+ writel(0x2009087f, GX_ETH_REG_3);
}
break;
config TARGET_TURRIS_OMNIA
bool "Support Turris Omnia"
select 88F6820
+ select BOARD_LATE_INIT
+ select DM_I2C
+ select I2C_MUX
+ select I2C_MUX_PCA954x
+ select SPL_I2C_MUX
+ select SYS_I2C_MVTWSI
+ select ATSHA204A
config TARGET_TURRIS_MOX
bool "Support Turris Mox"
bool "Support DB-XC3-24G4XG"
select 98DX3336
+config TARGET_CRS305_1G_4S
+ bool "Support CRS305-1G-4S"
+ select 98DX3236
+
endchoice
config SYS_BOARD
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
+ default "crs305-1g-4s" if TARGET_CRS305_1G_4S
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
default "controlcenterdc" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
+ default "crs305-1g-4s" if TARGET_CRS305_1G_4S
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
default "CZ.NIC" if TARGET_TURRIS_MOX
default "gdsys" if TARGET_CONTROLCENTERDC
default "alliedtelesis" if TARGET_X530
+ default "mikrotik" if TARGET_CRS305_1G_4S
config SYS_SOC
default "mvebu"
endif
endif
-ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif
#include <asm/omap_musb.h>
#include <asm/davinci_rtc.h>
+#define AM43XX_EMIF_BASE 0x4C000000
+#define AM43XX_SDRAM_CONFIG_OFFSET 0x8
+#define AM43XX_SDRAM_TYPE_MASK 0xE0000000
+#define AM43XX_SDRAM_TYPE_SHIFT 29
+#define AM43XX_SDRAM_TYPE_DDR3 3
+#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
+#define AM43XX_RDWRLVLFULL_START 0x80000000
+
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
struct prm_device_inst *prm_device =
(struct prm_device_inst *)PRM_DEVICE_INST;
- u32 scratch1;
+ u32 scratch1, sdrc;
void (*resume_func)(void);
scratch1 = readl(&rtc->scratch1);
rtc_only_prcm_init();
sdram_init();
- /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */
- writel(0, &prm_device->emif_ctrl);
+ /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
+ /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
+ sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
+
+ sdrc &= AM43XX_SDRAM_TYPE_MASK;
+ sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
+
+ if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
+ writel(AM43XX_RDWRLVLFULL_START,
+ AM43XX_EMIF_BASE +
+ AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
+ mdelay(1);
+
+am43xx_wait:
+ sdrc = readl(AM43XX_EMIF_BASE +
+ AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
+ if (sdrc == AM43XX_RDWRLVLFULL_START)
+ goto am43xx_wait;
+ }
resume_func = (void *)readl(&rtc->scratch0);
if (resume_func)
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
+#ifdef CONFIG_AM43XX
+ struct prm_device_inst *prm_device =
+ (struct prm_device_inst *)PRM_DEVICE_INST;
+#endif
+
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+#ifdef CONFIG_AM43XX
+ /*
+ * Disable EMIF_DEVOFF
+ * -> Cold Boot: This is just rewriting the default register value.
+ * -> RTC Resume: Must disable DEVOFF before leveling.
+ */
+ writel(0, &prm_device->emif_ctrl);
+#endif
+
/* Perform hardware leveling for DDR3 */
if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
/* Enable read leveling */
writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+ /* Wait 1ms because of L3 timeout error */
+ udelay(1000);
+
/*
* Enable full read and write leveling. Wait for read and write
* leveling bit to clear RDWRLVLFULL_START bit 31
* Enable hardware leveling on the EMIF. For details about these
* magic values please see the EMIF registers section of the TRM.
*/
- writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
- writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+ if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
+ /* PHY_INVERT_CLKOUT = 1 */
+ writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+ writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+ } else {
+ /* PHY_INVERT_CLKOUT = 0 */
+ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+ }
+
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
- writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
- writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+ writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+ writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
/*
* Sequence to ensure that the PHY is again in a known state after
select DM_SERIAL
imply CMD_DM
-config TARGET_MT_VENTOUX
- bool "TeeJet Mt.Ventoux"
- select OMAP3_GPIO_4
- select OMAP3_GPIO_5 if USB_EHCI_HCD
-
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select DM
select OMAP3_GPIO_5
select OMAP3_GPIO_6 if LED_STATUS
-config TARGET_CM_T3517
- bool "CompuLab CM-T3517 boards"
- select OMAP3_GPIO_2
- select OMAP3_GPIO_5
- select OMAP3_GPIO_6 if LED_STATUS
-
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
select DM
select OMAP3_GPIO_4
select OMAP3_GPIO_6
-config TARGET_ECO5PK
- bool "ECO5PK"
- select OMAP3_GPIO_5 if USB_EHCI_HCD
-
config TARGET_TRICORDER
bool "Tricorder"
select OMAP3_GPIO_2
-config TARGET_MCX
- bool "MCX"
- select BOARD_LATE_INIT
- select OMAP3_GPIO_2 if USB_EHCI_HCD
- select OMAP3_GPIO_5 if USB_EHCI_HCD
-
config TARGET_OMAP3_LOGIC
bool "OMAP3 Logic"
select BOARD_LATE_INIT
select OMAP3_GPIO_5
select OMAP3_GPIO_6
-config TARGET_TWISTER
- bool "Twister"
- select OMAP3_GPIO_2
- select OMAP3_GPIO_5 if USB_EHCI_HCD
-
config TARGET_OMAP3_CAIRO
bool "QUIPOS CAIRO"
select DM
default "omap3"
source "board/logicpd/am3517evm/Kconfig"
-source "board/teejet/mt_ventoux/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
-source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
-source "board/8dtech/eco5pk/Kconfig"
source "board/corscience/tricorder/Kconfig"
-source "board/htkw/mcx/Kconfig"
source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
-source "board/technexion/twister/Kconfig"
source "board/quipos/cairo/Kconfig"
source "board/lg/sniper/Kconfig"
#endif
#ifdef CONFIG_DM_GPIO
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+/* Manually initialize GPIO banks when OF_CONTROL doesn't */
static const struct omap_gpio_platdata omap34xx_gpio[] = {
{ 0, OMAP34XX_GPIO1_BASE },
{ 1, OMAP34XX_GPIO2_BASE },
{ "gpio_omap", &omap34xx_gpio[4] },
{ "gpio_omap", &omap34xx_gpio[5] },
};
-
+#endif
#else
static const struct gpio_bank gpio_bank_34xx[6] = {
.arch_extension sec
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.global flush_dcache_range
#endif
push {r4, r5, lr}
ldr r4, =omap_smc_sec_cpu1_args
stm r4, {r0,r1,r2,r3} @ Save args to memory
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mov r0, r4
mov r1, #CONFIG_SYS_CACHELINE_SIZE
add r1, r0, r1 @ dcache is not enabled on CPU1, so
*/
.section .data
omap_smc_sec_cpu1_args:
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.balign CONFIG_SYS_CACHELINE_SIZE
.rept CONFIG_SYS_CACHELINE_SIZE/4
.word 0
debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
debug("tee_file_size = %d\n", tee_file_size);
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range(
rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
/* Reuse the tee_info buffer for SMC params */
smc_cpu1_params = (u32 *)&tee_info;
smc_cpu1_params[0] = 0;
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
roundup(sizeof(u32), ARCH_DMA_MINALIGN));
#endif
select ARM64
select PHY
select CMD_CACHE
+ select PINCTRL
+ select PINCONF
+ select PINCTRL_PFC
+ select SUPPORT_SPL
imply CMD_FS_UUID
imply CMD_GPT
imply CMD_UUID
imply CMD_MMC_SWRITE if MMC
imply SUPPORT_EMMC_RPMB if MMC
+ imply SPL
+ imply SPL_BOARD_INIT
+ imply SPL_GZIP
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_SERIAL_SUPPORT
+ imply SPL_SYS_MALLOC_SIMPLE
+ imply SPL_TINY_MEMSET
+ imply SPL_YMODEM_SUPPORT
+ imply USE_TINY_PRINTF
+
+config RZA1
+ prompt "Renesas ARM SoCs RZ/A1 (32bit)"
+ select CPU_V7A
endchoice
source "arch/arm/mach-rmobile/Kconfig.32"
source "arch/arm/mach-rmobile/Kconfig.64"
+source "arch/arm/mach-rmobile/Kconfig.rza1"
endif
--- /dev/null
+if RZA1
+
+# required by the Ethernet driver
+config R7S72100
+ bool
+ default y
+
+# required by serial and usb driver
+config CPU_RZA1
+ bool
+ default y
+
+choice
+ prompt "Renesas RZ/A1 board select"
+
+# Renesas Supported Boards
+config TARGET_GRPEACH
+ bool "GR-PEACH board"
+
+endchoice
+
+config SYS_SOC
+ default "rmobile"
+
+# Renesas Supported Boards
+source "board/renesas/grpeach/Kconfig"
+
+endif
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+
+OBJCOPYFLAGS_u-boot-spl.srec := -O srec
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
+ $(OBJCOPYFLAGS_$(@F)) $< $@
+
+spl/u-boot-spl.srec: spl/u-boot-spl FORCE
+ $(call if_changed,objcopy)
+
+ifneq ($(CONFIG_R8A77990)$(CONFIG_R8A77995),)
+#
+# The first 6 generate statements generate the R-Car Gen3 SCIF loader header.
+# The subsequent generate statements represent the following chunk of assembler
+# code, which copies the loaded data from 0xe6304030 to 0xe6318000. This is to
+# work around a limitation of the D3/E3 BootROM, which does not permit loading
+# to 0xe6318000 directly.
+#
+# mov x0, #0xe6000000
+# orr x0, x0, #0x00300000
+# orr x1, x0, #0x00004000
+# orr x1, x1, #0x00000030
+#
+# orr x2, x0, #0x00018000
+# mov x0, x2
+# mov x3, #0x7000
+#1: ldp x4, x5, [x1], #16
+#
+# stp x4, x5, [x2], #16
+# subs x3, x3, #16
+# b.ge 1b
+# br x0
+#
+quiet_cmd_srec_cat = SRECCAT $@
+ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
+ -offset -0x13fd0 \
+ -Output_Block_Size 16 \
+ -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
+ -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
+ -generate 0xe63005d4 0xe63005d8 -l-e-constant 0xe6304000 4 \
+ -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
+ -generate 0xe6301154 0xe6301158 -l-e-constant 0xe6304000 4 \
+ -generate 0xe6301264 0xe6301268 -l-e-constant $2 4 \
+ -generate 0xe6304000 0xe6304004 -l-e-constant 0xd2bcc000 4 \
+ -generate 0xe6304004 0xe6304008 -l-e-constant 0xb26c0400 4 \
+ -generate 0xe6304008 0xe630400c -l-e-constant 0xb2720001 4 \
+ -generate 0xe630400c 0xe6304010 -l-e-constant 0xb27c0421 4 \
+ -generate 0xe6304010 0xe6304014 -l-e-constant 0xb2710402 4 \
+ -generate 0xe6304014 0xe6304018 -l-e-constant 0xaa0203e0 4 \
+ -generate 0xe6304018 0xe630401c -l-e-constant 0xd28e0003 4 \
+ -generate 0xe630401c 0xe6304020 -l-e-constant 0xa8c11424 4 \
+ -generate 0xe6304020 0xe6304024 -l-e-constant 0xa8811444 4 \
+ -generate 0xe6304024 0xe6304028 -l-e-constant 0xf1004063 4 \
+ -generate 0xe6304028 0xe630402c -l-e-constant 0x54ffffaa 4 \
+ -generate 0xe630402c 0xe6304030 -l-e-constant 0xd61f0000 4
+else
+quiet_cmd_srec_cat = SRECCAT $@
+ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
+ -Output_Block_Size 16 \
+ -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
+ -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
+ -generate 0xe63005d4 0xe63005d8 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
+ -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
+ -generate 0xe6301154 0xe6301158 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
+ -generate 0xe6301264 0xe6301268 -l-e-constant $2 4
+endif
+
+spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin
+ $(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}'))
+
+# if srec_cat is present build u-boot-spl.scif by default
+has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
+ALL-$(has_srec_cat) += u-boot-spl.scif
+CLEAN_FILES += u-boot-spl.scif
/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_GEN3
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
#endif
#ifdef CONFIG_DISPLAY_CPUINFO
+#ifndef CONFIG_RZA1
static u32 __rmobile_get_cpu_type(void)
{
return 0x0;
return 0;
}
+#else
+int print_cpuinfo(void)
+{
+ printf("CPU: Renesas Electronics RZ/A1\n");
+ return 0;
+}
+#endif
#endif /* CONFIG_DISPLAY_CPUINFO */
#include <asm/arch/r8a7794.h>
#elif defined(CONFIG_RCAR_GEN3)
#include <asm/arch/rcar-gen3-base.h>
+#elif defined(CONFIG_R7S72100)
#else
#error "SOC Name not defined"
#endif
select SPL_RAM
select SPL_DRIVERS_MISC_SUPPORT
select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
- select DEBUG_UART_BOARD_INIT
select BOARD_LATE_INIT
select ROCKCHIP_BROM_HELPER
help
bool "Support Rockchip RK3228/RK3229"
select CPU_V7A
select SUPPORT_SPL
+ select SUPPORT_TPL
select SPL
+ select SPL_DM
+ select SPL_OF_LIBFDT
+ select TPL
+ select TPL_DM
+ select TPL_OF_LIBFDT
+ select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
+ select TPL_NEEDS_SEPARATE_STACK if TPL
+ select SPL_DRIVERS_MISC_SUPPORT
+ imply SPL_SERIAL_SUPPORT
+ imply TPL_SERIAL_SUPPORT
select ROCKCHIP_BROM_HELPER
- select DEBUG_UART_BOARD_INIT
+ select TPL_LIBCOMMON_SUPPORT
+ select TPL_LIBGENERIC_SUPPORT
help
The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
including NEON and GPU, Mali-400 graphics, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+if ROCKCHIP_RK322X
+
+config TPL_TEXT_BASE
+ default 0x10081000
+
+config TPL_MAX_SIZE
+ default 28672
+
+config TPL_STACK
+ default 0x10088000
+
+endif
+
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7A
imply SPL_SEPARATE_BSS
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
- select DEBUG_UART_BOARD_INIT
help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
into a big and little cluster with 4 cores each) Cortex-A53 including
bool "Support Rockchip RK3399"
select ARM64
select SUPPORT_SPL
+ select SUPPORT_TPL
select SPL
+ select SPL_ATF
+ select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
+ select SPL_LOAD_FIT
+ select SPL_CLK if SPL
+ select SPL_PINCTRL if SPL
+ select SPL_RAM if SPL
+ select SPL_REGMAP if SPL
+ select SPL_SYSCON if SPL
+ select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
+ select TPL_NEEDS_SEPARATE_STACK if TPL
select SPL_SEPARATE_BSS
select SPL_SERIAL_SUPPORT
select SPL_DRIVERS_MISC_SUPPORT
- select DEBUG_UART_BOARD_INIT
+ select CLK
+ select FIT
+ select PINCTRL
+ select RAM
+ select REGMAP
+ select SYSCON
+ select DM_PMIC
+ select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
select ROCKCHIP_BROM_HELPER
+ imply TPL_SERIAL_SUPPORT
+ imply TPL_LIBCOMMON_SUPPORT
+ imply TPL_LIBGENERIC_SUPPORT
+ imply TPL_SYS_MALLOC_SIMPLE
+ imply TPL_BOOTROM_SUPPORT
+ imply TPL_DRIVERS_MISC_SUPPORT
+ imply TPL_OF_CONTROL
+ imply TPL_DM
+ imply TPL_REGMAP
+ imply TPL_SYSCON
+ imply TPL_RAM
+ imply TPL_CLK
+ imply TPL_TINY_MEMSET
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+if ROCKCHIP_RK3399
+
+config TPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+
+config TPL_TEXT_BASE
+ default 0xff8c2000
+
+config TPL_MAX_SIZE
+ default 188416
+
+config TPL_STACK
+ default 0xff8effff
+
+endif
+
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
config TPL_ROCKCHIP_BACK_TO_BROM
bool "TPL returns to bootrom"
- default y if ROCKCHIP_RK3368
+ default y
select ROCKCHIP_BROM_HELPER
depends on TPL
help
default 0x10300580 if ROCKCHIP_RV1108
default 0
help
- The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
+ The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
according to the value from this register.
config ROCKCHIP_SPL_RESERVE_IRAM
obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
+obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o
+obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o
obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
#include <common.h>
#include <adc.h>
#include <asm/io.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
#if (CONFIG_ROCKCHIP_BOOT_MODE_REG == 0)
*/
#include <common.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/boot_mode.h>
#include <asm/io.h>
#include <asm/setjmp.h>
#include <asm/system.h>
#!/usr/bin/env python
"""
-A script to generate FIT image source for rockchip boards
-with ARM Trusted Firmware
-and multiple device trees (given on the command line)
-
-usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+# SPDX-License-Identifier: GPL-2.0+
+#
+# A script to generate FIT image source for rockchip boards
+# with ARM Trusted Firmware
+# and multiple device trees (given on the command line)
+#
+# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
"""
import os
# pip install pyelftools
from elftools.elf.elffile import ELFFile
-ELF_SEG_P_TYPE='p_type'
-ELF_SEG_P_PADDR='p_paddr'
-ELF_SEG_P_VADDR='p_vaddr'
-ELF_SEG_P_OFFSET='p_offset'
-ELF_SEG_P_FILESZ='p_filesz'
-ELF_SEG_P_MEMSZ='p_memsz'
+ELF_SEG_P_TYPE = 'p_type'
+ELF_SEG_P_PADDR = 'p_paddr'
+ELF_SEG_P_VADDR = 'p_vaddr'
+ELF_SEG_P_OFFSET = 'p_offset'
+ELF_SEG_P_FILESZ = 'p_filesz'
+ELF_SEG_P_MEMSZ = 'p_memsz'
-DT_HEADER="""// SPDX-License-Identifier: GPL-2.0+ OR X11
+DT_HEADER = """
/*
- * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
- *
- * Minimal dts for a SPL FIT image payload.
+ * This is a generated file.
*/
/dts-v1/;
/ {
- description = "Configuration to load ATF before U-Boot";
+ description = "FIT image for U-Boot with bl31 (TF-A)";
#address-cells = <1>;
images {
+"""
+
+DT_UBOOT = """
uboot {
description = "U-Boot (64-bit)";
data = /incbin/("u-boot-nodtb.bin");
"""
-DT_IMAGES_NODE_END="""
- };
-"""
+DT_IMAGES_NODE_END = """ };
-DT_END="""
-};
"""
-def append_atf_node(file, atf_index, phy_addr, elf_entry):
- """
- Append ATF DT node to input FIT dts file.
- """
+DT_END = "};"
+
+def append_bl31_node(file, atf_index, phy_addr, elf_entry):
+ # Append BL31 DT node to input FIT dts file.
data = 'bl31_0x%08x.bin' % phy_addr
file.write('\t\tatf_%d {\n' % atf_index)
file.write('\t\t\tdescription = \"ARM Trusted Firmware\";\n')
file.write('\n')
def append_fdt_node(file, dtbs):
- """
- Append FDT nodes.
- """
+ # Append FDT nodes.
cnt = 1
for dtb in dtbs:
dtname = os.path.basename(dtb)
file.write('\n')
cnt = cnt + 1
-def append_conf_section(file, cnt, dtname, atf_cnt):
+def append_conf_section(file, cnt, dtname, segments):
file.write('\t\tconfig_%d {\n' % cnt)
file.write('\t\t\tdescription = "%s";\n' % dtname)
file.write('\t\t\tfirmware = "atf_1";\n')
file.write('\t\t\tloadables = "uboot",')
- for i in range(1, atf_cnt):
- file.write('"atf_%d"' % (i+1))
- if i != (atf_cnt - 1):
+ for i in range(1, segments):
+ file.write('"atf_%d"' % (i))
+ if i != (segments - 1):
file.write(',')
else:
file.write(';\n')
file.write('\t\t};\n')
file.write('\n')
-def append_conf_node(file, dtbs, atf_cnt):
- """
- Append configeration nodes.
- """
+def append_conf_node(file, dtbs, segments):
+ # Append configeration nodes.
cnt = 1
file.write('\tconfigurations {\n')
file.write('\t\tdefault = "config_1";\n')
for dtb in dtbs:
dtname = os.path.basename(dtb)
- append_conf_section(file, cnt, dtname, atf_cnt)
+ append_conf_section(file, cnt, dtname, segments)
cnt = cnt + 1
file.write('\t};\n')
file.write('\n')
-def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
- """
- Generate FIT script for ATF image.
- """
- if fit_file_name != sys.stdout:
- fit_file = open(fit_file_name, "wb")
- else:
- fit_file = sys.stdout
-
+def generate_atf_fit_dts_uboot(fit_file, uboot_file_name):
num_load_seg = 0
p_paddr = 0xFFFFFFFF
with open(uboot_file_name, 'rb') as uboot_file:
uboot = ELFFile(uboot_file)
for i in range(uboot.num_segments()):
seg = uboot.get_segment(i)
- if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
+ if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
num_load_seg = num_load_seg + 1
assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1)
- fit_file.write(DT_HEADER % p_paddr)
+ fit_file.write(DT_UBOOT % p_paddr)
+def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name):
with open(bl31_file_name, 'rb') as bl31_file:
bl31 = ELFFile(bl31_file)
elf_entry = bl31.header['e_entry']
- for i in range(bl31.num_segments()):
+ segments = bl31.num_segments()
+ for i in range(segments):
seg = bl31.get_segment(i)
- if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
+ if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
paddr = seg.__getitem__(ELF_SEG_P_PADDR)
- p= seg.__getitem__(ELF_SEG_P_PADDR)
- append_atf_node(fit_file, i+1, paddr, elf_entry)
- atf_cnt = i+1
+ append_bl31_node(fit_file, i + 1, paddr, elf_entry)
append_fdt_node(fit_file, dtbs_file_name)
- fit_file.write('%s\n' % DT_IMAGES_NODE_END)
- append_conf_node(fit_file, dtbs_file_name, atf_cnt)
- fit_file.write('%s\n' % DT_END)
+ fit_file.write(DT_IMAGES_NODE_END)
+ append_conf_node(fit_file, dtbs_file_name, segments)
+
+def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
+ # Generate FIT script for ATF image.
+ if fit_file_name != sys.stdout:
+ fit_file = open(fit_file_name, "wb")
+ else:
+ fit_file = sys.stdout
+
+ fit_file.write(DT_HEADER)
+ generate_atf_fit_dts_uboot(fit_file, uboot_file_name)
+ generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name)
+ fit_file.write(DT_END)
if fit_file_name != sys.stdout:
fit_file.close()
num = bl31.num_segments()
for i in range(num):
seg = bl31.get_segment(i)
- if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
+ if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD':
paddr = seg.__getitem__(ELF_SEG_P_PADDR)
file_name = 'bl31_0x%08x.bin' % paddr
with open(file_name, "wb") as atf:
- atf.write(seg.data());
-
-def get_bl31_segments_info(bl31_file_name):
- """
- Get load offset, physical offset, file size
- from bl31 elf file program headers.
- """
- with open(bl31_file_name) as bl31_file:
- bl31 = ELFFile(bl31_file)
-
- num = bl31.num_segments()
- print('Number of Segments : %d' % bl31.num_segments())
- for i in range(num):
- print('Segment %d' % i)
- seg = bl31.get_segment(i)
- ptype = seg[ELF_SEG_P_TYPE]
- poffset = seg[ELF_SEG_P_OFFSET]
- pmemsz = seg[ELF_SEG_P_MEMSZ]
- pfilesz = seg[ELF_SEG_P_FILESZ]
- print('type: %s\nfilesz: %08x\nmemsz: %08x\noffset: %08x' % (ptype, pfilesz, pmemsz, poffset))
- paddr = seg[ELF_SEG_P_PADDR]
- print('paddr: %08x' % paddr)
+ atf.write(seg.data())
def main():
- uboot_elf="./u-boot"
- bl31_elf="./bl31.elf"
- FIT_ITS=sys.stdout
+ uboot_elf = "./u-boot"
+ bl31_elf = "./bl31.elf"
+ fit_its = sys.stdout
opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h")
for opt, val in opts:
if opt == "-o":
- FIT_ITS=val
+ fit_its = val
elif opt == "-u":
- uboot_elf=val
+ uboot_elf = val
elif opt == "-b":
- bl31_elf=val
+ bl31_elf = val
elif opt == "-h":
print(__doc__)
sys.exit(2)
dtbs = args
- #get_bl31_segments_info("u-boot")
- #get_bl31_segments_info("bl31.elf")
- generate_atf_fit_dts(FIT_ITS, bl31_elf, uboot_elf, dtbs)
- generate_atf_binary(bl31_elf);
+ generate_atf_fit_dts(fit_its, bl31_elf, uboot_elf, dtbs)
+ generate_atf_binary(bl31_elf)
if __name__ == "__main__":
main()
#include <common.h>
#include <debug_uart.h>
#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/grf_rk3036.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sdram_rk3036.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
-
-#define GRF_BASE 0x20008000
-
-#define DEBUG_UART_BASE 0x20068000
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
+#include <asm/arch-rockchip/timer.h>
void board_init_f(ulong dummy)
{
-#ifdef EARLY_DEBUG
- struct rk3036_grf * const grf = (void *)GRF_BASE;
- /*
- * NOTE: sd card and debug uart use same iomux in rk3036,
- * so if you enable uart,
- * you can not boot from sdcard
- */
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C3_MASK << GPIO1C3_SHIFT |
- GPIO1C2_MASK << GPIO1C2_SHIFT,
- GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
- GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
+#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
rockchip_timer_init();
#include <ram.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/grf_rk3036.h>
-#include <asm/arch/boot_mode.h>
-#include <asm/arch/sdram_rk3036.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/grf_rk3036.h>
+#include <asm/arch-rockchip/boot_mode.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
#include <dm/pinctrl.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
select BOARD_LATE_INIT
config SYS_SOC
- default "rockchip"
+ default "rk3036"
config SYS_MALLOC_F_LEN
default 0x400
obj-y += syscon_rk3036.o
endif
+obj-y += rk3036.o
obj-y += sdram_rk3036.o
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3036.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3036.h>
int rockchip_get_clk(struct udevice **devp)
{
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_rk3036.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#define GRF_BASE 0x20008000
+ struct rk3036_grf * const grf = (void *)GRF_BASE;
+ enum {
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_MMC0_D1,
+ GPIO1C3_UART2_SOUT,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_MMC0_D0,
+ GPIO1C2_UART2_SIN,
+ };
+ /*
+ * NOTE: sd card and debug uart use same iomux in rk3036,
+ * so if you enable uart,
+ * you can not boot from sdcard
+ */
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C3_MASK << GPIO1C3_SHIFT |
+ GPIO1C2_MASK << GPIO1C2_SHIFT,
+ GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
+ GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
+}
+#endif
#include <common.h>
#include <asm/io.h>
#include <asm/types.h>
-#include <asm/arch/cru_rk3036.h>
-#include <asm/arch/grf_rk3036.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sdram_rk3036.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
+#include <asm/arch-rockchip/cru_rk3036.h>
+#include <asm/arch-rockchip/grf_rk3036.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
+#include <asm/arch-rockchip/timer.h>
+#include <asm/arch-rockchip/uart.h>
/*
* we can not fit the code to access the device tree in SPL
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk3036_syscon_ids[] = {
{ .compatible = "rockchip,rk3036-grf", .data = ROCKCHIP_SYSCON_GRF },
#include <ram.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/grf_rk3128.h>
-#include <asm/arch/boot_mode.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/grf_rk3128.h>
+#include <asm/arch-rockchip/boot_mode.h>
+#include <asm/arch-rockchip/timer.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
endchoice
config SYS_SOC
- default "rockchip"
+ default "rk3128"
config SYS_MALLOC_F_LEN
default 0x0800
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3128.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3128.h>
int rockchip_get_clk(struct udevice **devp)
{
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk3128_syscon_ids[] = {
{ .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF },
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3188.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3188.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/pmu_rk3188.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/arch-rockchip/timer.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
#include <dm/test.h>
return ret;
}
-void board_debug_uart_init(void)
-{
- /* Enable early UART on the RK3188 */
-#define GRF_BASE 0x20008000
- struct rk3188_grf * const grf = (void *)GRF_BASE;
- enum {
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3,
- GPIO1B1_GPIO = 0,
- GPIO1B1_UART2_SOUT,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK = 3,
- GPIO1B0_GPIO = 0,
- GPIO1B0_UART2_SIN,
- };
-
- /* Enable early UART on the RK3188 */
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK << GPIO1B1_SHIFT |
- GPIO1B0_MASK << GPIO1B0_SHIFT,
- GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
- GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
-}
-
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
-#define EARLY_UART
-#ifdef EARLY_UART
+#ifdef CONFIG_DEBUG_UART
/*
* Debug UART can be used from here if required:
*
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3188.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
+#include <asm/arch-rockchip/boot_mode.h>
#include <dm/pinctrl.h>
__weak int rk_board_late_init(void)
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
UART and GPIOs.
config SYS_SOC
- default "rockchip"
+ default "rk3188"
config SYS_MALLOC_F_LEN
default 0x0800
ifndef CONFIG_TPL_BUILD
obj-y += clk_rk3188.o
+obj-y += rk3188.o
obj-y += syscon_rk3188.o
endif
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3188.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3188.h>
int rockchip_get_clk(struct udevice **devp)
{
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ /* Enable early UART on the RK3188 */
+#define GRF_BASE 0x20008000
+ struct rk3188_grf * const grf = (void *)GRF_BASE;
+ enum {
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART2_SOUT,
+ GPIO1B1_JTAG_TDO,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 3,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_UART2_SIN,
+ GPIO1B0_JTAG_TDI,
+ };
+
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK << GPIO1B1_SHIFT |
+ GPIO1B0_MASK << GPIO1B0_SHIFT,
+ GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
+ GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
+}
+#endif
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk3188_syscon_ids[] = {
{ .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
*/
#include <common.h>
-#include <debug_uart.h>
#include <dm.h>
-#include <ram.h>
#include <spl.h>
#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/cru_rk322x.h>
-#include <asm/arch/grf_rk322x.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
+#include <asm/arch-rockchip/hardware.h>
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
-#define GRF_BASE 0x11000000
-#define SGRF_BASE 0x10140000
-#define DEBUG_UART_BASE 0x11030000
-
-void board_debug_uart_init(void)
+u32 spl_boot_mode(const u32 boot_device)
{
- static struct rk322x_grf * const grf = (void *)GRF_BASE;
- enum {
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_UART1_SIN,
- GPIO1B2_UART21_SIN,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_UART1_SOUT,
- GPIO1B1_UART21_SOUT,
- };
- enum {
- CON_IOMUX_UART2SEL_SHIFT= 8,
- CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
- CON_IOMUX_UART2SEL_2 = 0,
- CON_IOMUX_UART2SEL_21,
- };
-
- /* Enable early UART2 channel 1 on the RK322x */
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK | GPIO1B2_MASK,
- GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
- GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
- /* Set channel C as UART2 input */
- rk_clrsetreg(&grf->con_iomux,
- CON_IOMUX_UART2SEL_MASK,
- CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+ return MMCSD_MODE_RAW;
}
#define SGRF_DDR_CON0 0x10150000
void board_init_f(ulong dummy)
{
- struct udevice *dev;
int ret;
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug_uart_init();
- printascii("SPL Init");
-
ret = spl_early_init();
if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
+ printf("spl_early_init() failed: %d\n", ret);
hang();
}
-
- rockchip_timer_init();
- printf("timer init done\n");
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- printf("DRAM init failed: %d\n", ret);
- return;
- }
+ preloader_console_init();
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
-#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
- back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/timer.h>
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ debug_uart_init();
+ printascii("TPL Init");
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ rockchip_timer_init();
+ printf("timer init done\n");
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return;
+ }
+
+#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT)
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+#endif
+}
#include <ram.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/boot_mode.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/grf_rk322x.h>
+#include <asm/arch-rockchip/boot_mode.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk322x.h>
+#include <asm/arch-rockchip/periph.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
-#include <asm/arch/grf_rk322x.h>
+#include <asm/arch-rockchip/grf_rk322x.h>
/* Enable early UART2 channel 1 on the RK322x */
#define GRF_BASE 0x11000000
- struct rk322x_grf * const grf = (void *)GRF_BASE;
- enum {
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_UART21_SIN,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_UART1_SOUT,
- GPIO1B1_UART21_SOUT,
- };
- enum {
- CON_IOMUX_UART2SEL_SHIFT= 8,
- CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
- CON_IOMUX_UART2SEL_2 = 0,
- CON_IOMUX_UART2SEL_21,
- };
-
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK | GPIO1B2_MASK,
- GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
- GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
- /* Set channel C as UART2 input */
- rk_clrsetreg(&grf->con_iomux,
- CON_IOMUX_UART2SEL_MASK,
- CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+ static struct rk322x_grf * const grf = (void *)GRF_BASE;
/*
* The integrated macphy is enabled by default, disable it
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
select BOARD_LATE_INIT
config SYS_SOC
- default "rockchip"
+ default "rk322x"
config SYS_MALLOC_F_LEN
default 0x400
# SPDX-License-Identifier: GPL-2.0+
#
-
obj-y += clk_rk322x.o
+obj-y += rk322x.o
obj-y += syscon_rk322x.o
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk322x.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk322x.h>
int rockchip_get_clk(struct udevice **devp)
{
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_rk322x.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#define GRF_BASE 0x11000000
+ static struct rk322x_grf * const grf = (void *)GRF_BASE;
+ enum {
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART1_SIN,
+ GPIO1B2_UART21_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART1_SOUT,
+ GPIO1B1_UART21_SOUT,
+ };
+ enum {
+ CON_IOMUX_UART2SEL_SHIFT = 8,
+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_2 = 0,
+ CON_IOMUX_UART2SEL_21,
+ };
+
+ /* Enable early UART2 channel 1 on the RK322x */
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK | GPIO1B2_MASK,
+ GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
+ GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
+ /* Set channel C as UART2 input */
+ rk_clrsetreg(&grf->con_iomux,
+ CON_IOMUX_UART2SEL_MASK,
+ CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+}
+#endif
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk322x_syscon_ids[] = {
{ .compatible = "rockchip,rk3228-grf", .data = ROCKCHIP_SYSCON_GRF },
#include <spl.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/sdram_common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sys_proto.h>
+#include <asm/arch-rockchip/timer.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
#include <dm/test.h>
struct udevice *dev;
int ret;
- /* Example code showing how to enable the debug UART on RK3288 */
-#include <asm/arch/grf_rk3288.h>
- /* Enable early UART on the RK3288 */
-#define GRF_BASE 0xff770000
- struct rk3288_grf * const grf = (void *)GRF_BASE;
-
- rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
- GPIO7C6_MASK << GPIO7C6_SHIFT,
- GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
- GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+#ifdef CONFIG_DEBUG_UART
/*
* Debug UART can be used from here if required:
*
*/
debug_uart_init();
debug("\nspl:debug uart enabled in %s\n", __func__);
+#endif
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
#include <spl.h>
#include <version.h>
#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/sys_proto.h>
+#include <asm/arch-rockchip/timer.h>
-#define GRF_BASE 0xff770000
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
- /* Example code showing how to enable the debug UART on RK3288 */
- /* Enable early UART on the RK3288 */
- struct rk3288_grf * const grf = (void *)GRF_BASE;
-
- rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
- GPIO7C6_MASK << GPIO7C6_SHIFT,
- GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
- GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+#ifdef CONFIG_DEBUG_UART
/*
* Debug UART can be used from here if required:
*
* printascii("string");
*/
debug_uart_init();
-
+#endif
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
#include <ram.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/qos_rk3288.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
+#include <asm/arch-rockchip/qos_rk3288.h>
+#include <asm/arch-rockchip/boot_mode.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
{
const uintptr_t GRF_SOC_CON0 = 0xff770244;
const uintptr_t GRF_SOC_CON2 = 0xff77024c;
- struct udevice *pinctrl;
struct udevice *dev;
int ret;
debug("CLK init failed: %d\n", ret);
return ret;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- return ret;
- }
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- return ret;
- }
rk_setreg(GRF_SOC_CON2, 1 << 0);
/*
and have the required PMIC code.
config SYS_SOC
- default "rockchip"
+ default "rk3288"
config SYS_MALLOC_F_LEN
default 0x0800
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
int rockchip_get_clk(struct udevice **devp)
{
* Copyright (c) 2016 Rockchip Electronics Co., Ltd
*/
#include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
-#define GRF_SOC_CON2 0xff77024c
+#define GRF_BASE 0xff770000
int arch_cpu_init(void)
{
/* We do some SoC one time setting here. */
+ struct rk3288_grf * const grf = (void *)GRF_BASE;
/* Use rkpwm by default */
- rk_setreg(GRF_SOC_CON2, 1 << 0);
+ rk_setreg(&grf->soc_con2, 1 << 0);
return 0;
}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ /* Enable early UART on the RK3288 */
+ struct rk3288_grf * const grf = (void *)GRF_BASE;
+
+ rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
+ GPIO7C6_MASK << GPIO7C6_SHIFT,
+ GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
+ GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+}
+#endif
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk3288_syscon_ids[] = {
{ .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC },
endchoice
config SYS_SOC
- default "rockchip"
+ default "rk3328"
config SYS_MALLOC_F_LEN
default 0x0800
#include <common.h>
#include <dm.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3328.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3328.h>
int rockchip_get_clk(struct udevice **devp)
{
*/
#include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
*/
#include <common.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
#include <dm.h>
#include <syscon.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
-#include <asm/arch/cru_rk3368.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/timer.h>
-#include <dm/pinctrl.h>
-
-void board_debug_uart_init(void)
-{
-}
+#include <asm/arch-rockchip/periph.h>
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl;
struct udevice *dev;
int ret;
hang();
}
- /* Set up our preloader console */
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- pr_err("%s: pinctrl init failed: %d\n", __func__, ret);
- hang();
- }
-
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
- if (ret) {
- pr_err("%s: failed to set up console UART\n", __func__);
- hang();
- }
-
preloader_console_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
#include <spl.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3368.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/timer.h>
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
}
-void board_debug_uart_init(void)
-{
- /*
- * N.B.: This is called before the device-model has been
- * initialised. For this reason, we can not access
- * the GRF address range using the syscon API.
- */
- struct rk3368_grf * const grf =
- (struct rk3368_grf * const)0xff770000;
-
- enum {
- GPIO2D1_MASK = GENMASK(3, 2),
- GPIO2D1_GPIO = 0,
- GPIO2D1_UART0_SOUT = (1 << 2),
-
- GPIO2D0_MASK = GENMASK(1, 0),
- GPIO2D0_GPIO = 0,
- GPIO2D0_UART0_SIN = (1 << 0),
- };
-
-#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
- /* Enable early UART0 on the RK3368 */
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D0_MASK, GPIO2D0_UART0_SIN);
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
-#endif
-}
-
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
-#define EARLY_UART
-#ifdef EARLY_UART
+#ifdef CONFIG_DEBUG_UART
/*
* Debug UART can be used from here if required:
*
endchoice
config SYS_SOC
- default "rockchip"
+ default "rk3368"
source "board/theobroma-systems/lion_rk3368/Kconfig"
source "board/rockchip/sheep_rk3368/Kconfig"
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3368.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
int rockchip_get_clk(struct udevice **devp)
{
#include <common.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3368.h>
-#include <asm/arch/grf_rk3368.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
#include <syscon.h>
DECLARE_GLOBAL_DATA_PTR;
return mcu_init();
}
#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ /*
+ * N.B.: This is called before the device-model has been
+ * initialised. For this reason, we can not access
+ * the GRF address range using the syscon API.
+ */
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+ struct rk3368_grf * const grf =
+ (struct rk3368_grf * const)0xff770000;
+
+ enum {
+ GPIO2D1_MASK = GENMASK(3, 2),
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_UART0_SOUT = (1 << 2),
+
+ GPIO2D0_MASK = GENMASK(1, 0),
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_UART0_SIN = (1 << 0),
+ };
+
+ /* Enable early UART0 on the RK3368 */
+ rk_clrsetreg(&grf->gpio2d_iomux,
+ GPIO2D0_MASK, GPIO2D0_UART0_SIN);
+ rk_clrsetreg(&grf->gpio2d_iomux,
+ GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
+ struct rk3368_pmu_grf * const pmugrf __maybe_unused =
+ (struct rk3368_pmu_grf * const)0xff738000;
+
+ enum {
+ /* UART4 */
+ GPIO0D2_MASK = GENMASK(5, 4),
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_UART4_SOUT = (3 << 4),
+
+ GPIO0D3_MASK = GENMASK(7, 6),
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_UART4_SIN = (3 << 6),
+ };
+
+ /* Enable early UART4 on the PX5 */
+ rk_clrsetreg(&pmugrf->gpio0d_iomux,
+ GPIO0D2_MASK | GPIO0D3_MASK,
+ GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
+ struct rk3368_grf * const grf =
+ (struct rk3368_grf * const)0xff770000;
+
+ enum {
+ GPIO2A6_SHIFT = 12,
+ GPIO2A6_MASK = GENMASK(13, 12),
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
+
+ GPIO2A5_SHIFT = 10,
+ GPIO2A5_MASK = GENMASK(11, 10),
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
+ };
+
+ /* Enable early UART2 on the RK3368 */
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A6_MASK, GPIO2A6_UART2_SIN);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
+#endif
+}
+#endif
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk3368_syscon_ids[] = {
{ .compatible = "rockchip,rk3368-grf",
#include <spl_gpio.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3399.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/sys_proto.h>
#include <dm/pinctrl.h>
void board_return_to_bootrom(void)
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
}
-void board_debug_uart_init(void)
-{
-#define GRF_BASE 0xff770000
-#define GPIO0_BASE 0xff720000
-#define PMUGRF_BASE 0xff320000
- struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
-#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
- struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
- struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
-#endif
-
-#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
- /* Enable early UART0 on the RK3399 */
- rk_clrsetreg(&grf->gpio2c_iomux,
- GRF_GPIO2C0_SEL_MASK,
- GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio2c_iomux,
- GRF_GPIO2C1_SEL_MASK,
- GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
-#else
-# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
- rk_setreg(&grf->io_vsel, 1 << 0);
-
- /*
- * Let's enable these power rails here, we are already running the SPI
- * Flash based code.
- */
- spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
- spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
-
- spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
- spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
-#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
-
- /* Enable early UART2 channel C on the RK3399 */
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C3_SEL_MASK,
- GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C4_SEL_MASK,
- GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
- /* Set channel C as UART2 input */
- rk_clrsetreg(&grf->soc_con7,
- GRF_UART_DBG_SEL_MASK,
- GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
-#endif
-}
void board_init_f(ulong dummy)
{
struct rk3399_grf_regs *grf;
int ret;
-#define EARLY_UART
-#ifdef EARLY_UART
+#ifdef CONFIG_DEBUG_UART
debug_uart_init();
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+
+#define TIMER_CHN10_BASE 0xff8680a0
+#define TIMER_END_COUNT_L 0x00
+#define TIMER_END_COUNT_H 0x04
+#define TIMER_INIT_COUNT_L 0x10
+#define TIMER_INIT_COUNT_H 0x14
+#define TIMER_CONTROL_REG 0x1c
+
+#define TIMER_EN 0x1
+#define TIMER_FMODE (0 << 1)
+#define TIMER_RMODE (1 << 1)
+
+void secure_timer_init(void)
+{
+ writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
+ writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
+ writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
+ writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
+ writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ printascii("U-Boot TPL board init\n");
+#endif
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ secure_timer_init();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ pr_err("DRAM init failed: %d\n", ret);
+ return;
+ }
+}
+
+void board_return_to_bootrom(void)
+{
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
*/
#include <common.h>
-#include <asm/arch/boot_mode.h>
+#include <asm/arch-rockchip/boot_mode.h>
int board_late_init(void)
{
endchoice
config SYS_SOC
- default "rockchip"
+ default "rk3399"
config SYS_MALLOC_F_LEN
default 0x0800
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3399.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3399.h>
static int rockchip_get_cruclk(struct udevice **devp)
{
*/
#include <common.h>
+#include <spl_gpio.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/gpio.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
#define GRF_EMMCCORE_CON11 0xff77f02c
+#define GRF_BASE 0xff770000
static struct mm_region rk3399_mem_map[] = {
{
int arch_cpu_init(void)
{
/* We do some SoC one time setting here. */
+ struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
/* Emmc clock generator: disable the clock multipilier */
- rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
+ rk_clrreg(&grf->emmccore_con[11], 0x0ff);
return 0;
}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#define GRF_BASE 0xff770000
+#define GPIO0_BASE 0xff720000
+#define PMUGRF_BASE 0xff320000
+ struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
+#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+ struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+ struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
+#endif
+
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+ /* Enable early UART0 on the RK3399 */
+ rk_clrsetreg(&grf->gpio2c_iomux,
+ GRF_GPIO2C0_SEL_MASK,
+ GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2c_iomux,
+ GRF_GPIO2C1_SEL_MASK,
+ GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
+ /* Enable early UART3 on the RK3399 */
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GRF_GPIO3B6_SEL_MASK,
+ GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GRF_GPIO3B7_SEL_MASK,
+ GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
+#else
+# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
+ rk_setreg(&grf->io_vsel, 1 << 0);
+
+ /*
+ * Let's enable these power rails here, we are already running the SPI
+ * Flash based code.
+ */
+ spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
+
+ spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
+#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
+
+ /* Enable early UART2 channel C on the RK3399 */
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GRF_GPIO4C3_SEL_MASK,
+ GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio4c_iomux,
+ GRF_GPIO4C4_SEL_MASK,
+ GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
+ /* Set channel C as UART2 input */
+ rk_clrsetreg(&grf->soc_con7,
+ GRF_UART_DBG_SEL_MASK,
+ GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
+#endif
+}
+#endif
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk3399_syscon_ids[] = {
{ .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF },
*/
#include <common.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/timer.h>
#include <asm/io.h>
#include <linux/types.h>
return timebase_h << 32 | timebase_l;
}
-static uint64_t usec_to_tick(unsigned int usec)
-{
- uint64_t tick = usec;
- tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000);
- return tick;
-}
-
void rockchip_udelay(unsigned int usec)
{
uint64_t tmp;
RV1108 ELGIN is a board based on the Rockchip RV1108.
config SYS_SOC
- default "rockchip"
+ default "rv1108"
config SYS_MALLOC_F_LEN
default 0x400
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rv1108.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rv1108.h>
int rockchip_get_clk(struct udevice **devp)
{
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
#include <common.h>
#include <dm.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rv1108_syscon_ids[] = {
{ .compatible = "rockchip,rv1108-grf", .data = ROCKCHIP_SYSCON_GRF },
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/sdram_common.h>
#include <dm/uclass-internal.h>
DECLARE_GLOBAL_DATA_PTR;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Rockchip Electronics Co., Ltd
+ * Kever Yang<kever.yang@rock-chips.com>
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ .text : {
+ . = ALIGN(8);
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ .rodata : {
+ . = ALIGN(8);
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ .data : {
+ . = ALIGN(8);
+ *(.data*)
+ }
+
+ .u_boot_list : {
+ . = ALIGN(8);
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ .image_copy_end : {
+ . = ALIGN(8);
+ *(.__image_copy_end)
+ }
+
+ .end : {
+ . = ALIGN(8);
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ .bss_start (NOLOAD) : {
+ . = ALIGN(8);
+ KEEP(*(.__bss_start));
+ }
+
+ .bss (NOLOAD) : {
+ *(.bss*)
+ . = ALIGN(8);
+ }
+
+ .bss_end (NOLOAD) : {
+ KEEP(*(.__bss_end));
+ }
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
+
+#if defined(CONFIG_TPL_MAX_SIZE)
+ASSERT(__image_copy_end - __image_copy_start < (CONFIG_TPL_MAX_SIZE), \
+ "TPL image too big");
+#endif
+
+#if defined(CONFIG_TPL_BSS_MAX_SIZE)
+ASSERT(__bss_end - __bss_start < (CONFIG_TPL_BSS_MAX_SIZE), \
+ "TPL image BSS too big");
+#endif
+
+#if defined(CONFIG_TPL_MAX_FOOTPRINT)
+ASSERT(__bss_end - _start < (CONFIG_TPL_MAX_FOOTPRINT), \
+ "TPL image plus BSS too big");
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Rockchip Electronic Co.,Ltd
+ */
+
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE
+
+#undef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE
+
+#include "../cpu/u-boot-spl.lds"
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
config TARGET_SOCFPGA_ARRIA10
bool
- select ALTERA_SDRAM
+ select SPL_ALTERA_SDRAM
select SPL_BOARD_INIT if SPL
select CLK
select SPL_CLK if SPL
config TARGET_SOCFPGA_GEN5
bool
- select ALTERA_SDRAM
+ select SPL_ALTERA_SDRAM
imply FPGA_SOCFPGA
imply SPL_STACK_R
imply SPL_SYS_MALLOC_SIMPLE
prompt "Altera SOCFPGA board select"
optional
+config TARGET_SOCFPGA_ARIES_MCVEVK
+ bool "Aries MCVEVK (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_ARRIA10_SOCDK
bool "Altera SOCFPGA SoCDK (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
+ default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
+ default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "socfpga_is1" if TARGET_SOCFPGA_IS1
+ default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
* All rights reserved.
*/
+#include <asm/cache.h>
+#include <altera.h>
+#include <image.h>
+
#ifndef _FPGA_MANAGER_ARRIA10_H_
#define _FPGA_MANAGER_ARRIA10_H_
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
+#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
+#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
+#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
#ifndef __ASSEMBLY__
struct socfpga_fpga_manager {
u32 imgcfg_fifo_status;
};
+enum rbf_type {
+ unknown,
+ periph_section,
+ core_section
+};
+
+enum rbf_security {
+ invalid,
+ unencrypted,
+ encrypted
+};
+
+struct rbf_info {
+ enum rbf_type section;
+ enum rbf_security security;
+};
+
+struct fpga_loadfs_info {
+ fpga_fs_info *fpga_fsinfo;
+ u32 remaining;
+ u32 offset;
+ struct rbf_info rbfinfo;
+};
+
/* Functions */
int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
int fpgamgr_program_finish(void);
int is_fpgamgr_user_mode(void);
int fpgamgr_wait_early_user_mode(void);
-
+const char *get_fpga_filename(void);
+int is_fpgamgr_early_user_mode(void);
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+ u32 offset);
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_ARRIA10_H_ */
void socfpga_sdram_remap_zero(void);
#endif
-void do_bridge_reset(int enable);
+void do_bridge_reset(int enable, unsigned int mask);
+void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */
#include <dt-bindings/reset/altr,rst-mgr.h>
-void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);
struct socfpga_reset_manager {
#define _RESET_MANAGER_S10_
void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
void socfpga_bridges_reset(int enable);
#define RSTMGR_MPUMODRST_CORE0 0
#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
+#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
+
/* Watchdogs and MPU warm reset mask */
#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
- *
- */
-
-#ifndef _SDRAM_S10_H_
-#define _SDRAM_S10_H_
-
-phys_size_t sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-#define DDR_TWR 15
-#define DDR_READ_LATENCY_DELAY 40
-#define DDR_ACTIVATE_FAWBANK 0x1
-
-/* ECC HMC registers */
-#define DDRIOCTRL 0x8
-#define DDRCALSTAT 0xc
-#define DRAMADDRWIDTH 0xe0
-#define ECCCTRL1 0x100
-#define ECCCTRL2 0x104
-#define ERRINTEN 0x110
-#define ERRINTENS 0x114
-#define INTMODE 0x11c
-#define INTSTAT 0x120
-#define AUTOWB_CORRADDR 0x138
-#define ECC_REG2WRECCDATABUS 0x144
-#define ECC_DIAGON 0x150
-#define ECC_DECSTAT 0x154
-#define HPSINTFCSEL 0x210
-#define RSTHANDSHAKECTRL 0x214
-#define RSTHANDSHAKESTAT 0x218
-
-#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003
-#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0)
-#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
-#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8)
-#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0)
-#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8)
-#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0)
-#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16)
-#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0)
-#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0)
-#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1)
-#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0)
-#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
-#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
-#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
-#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
-#define DDR_HMC_CORE2SEQ_INT_REQ 0xF
-#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
-#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
-
-#define DDR_HMC_ERRINTEN_INTMASK \
- (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \
- DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
-
-/* NOC DDR scheduler */
-#define DDR_SCH_ID_COREID 0
-#define DDR_SCH_ID_REVID 0x4
-#define DDR_SCH_DDRCONF 0x8
-#define DDR_SCH_DDRTIMING 0xc
-#define DDR_SCH_DDRMODE 0x10
-#define DDR_SCH_READ_LATENCY 0x14
-#define DDR_SCH_ACTIVATE 0x38
-#define DDR_SCH_DEVTODEV 0x3c
-#define DDR_SCH_DDR4TIMING 0x40
-
-#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0
-#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6
-#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12
-#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18
-#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21
-#define DDR_SCH_DDRTIMING_WRTORD_OFF 26
-#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31
-#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1
-#define DDR_SCH_ACTIVATE_RRD_OFF 0
-#define DDR_SCH_ACTIVATE_FAW_OFF 4
-#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10
-#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0
-#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2
-#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
-
-/* HMC MMR IO48 registers */
-#define CTRLCFG0 0x28
-#define CTRLCFG1 0x2c
-#define DRAMTIMING0 0x50
-#define CALTIMING0 0x7c
-#define CALTIMING1 0x80
-#define CALTIMING2 0x84
-#define CALTIMING3 0x88
-#define CALTIMING4 0x8c
-#define CALTIMING9 0xa0
-#define DRAMADDRW 0xa8
-#define DRAMSTS 0xec
-#define NIOSRESERVED0 0x110
-#define NIOSRESERVED1 0x114
-#define NIOSRESERVED2 0x118
-
-#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
- (((x) >> 0) & 0x1F)
-#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
- (((x) >> 5) & 0x1F)
-#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
- (((x) >> 10) & 0xF)
-#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
- (((x) >> 14) & 0x3)
-#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
- (((x) >> 16) & 0x7)
-
-#define CTRLCFG0_CFG_MEMTYPE(x) \
- (((x) >> 0) & 0xF)
-#define CTRLCFG0_CFG_DIMM_TYPE(x) \
- (((x) >> 4) & 0x7)
-#define CTRLCFG0_CFG_AC_POS(x) \
- (((x) >> 7) & 0x3)
-#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
- (((x) >> 9) & 0x1F)
-
-#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
- (((x) >> 0) & 0x1F)
-#define CTRLCFG1_CFG_ADDR_ORDER(x) \
- (((x) >> 5) & 0x3)
-#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
- (((x) >> 7) & 0x1)
-
-#define DRAMTIMING0_CFG_TCL(x) \
- (((x) >> 0) & 0x7F)
-
-#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
- (((x) >> 0) & 0x3F)
-#define CALTIMING0_CFG_ACT_TO_PCH(x) \
- (((x) >> 6) & 0x3F)
-#define CALTIMING0_CFG_ACT_TO_ACT(x) \
- (((x) >> 12) & 0x3F)
-#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
- (((x) >> 18) & 0x3F)
-
-#define CALTIMING1_CFG_RD_TO_RD(x) \
- (((x) >> 0) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
- (((x) >> 6) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
- (((x) >> 12) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_WR(x) \
- (((x) >> 18) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_WR_DC(x) \
- (((x) >> 24) & 0x3F)
-
-#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
- (((x) >> 0) & 0x3F)
-#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
- (((x) >> 6) & 0x3F)
-#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
- (((x) >> 12) & 0x3F)
-#define CALTIMING2_CFG_WR_TO_WR(x) \
- (((x) >> 18) & 0x3F)
-#define CALTIMING2_CFG_WR_TO_WR_DC(x) \
- (((x) >> 24) & 0x3F)
-
-#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
- (((x) >> 0) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_RD(x) \
- (((x) >> 6) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
- (((x) >> 12) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_RD_DB(x) \
- (((x) >> 18) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_PCH(x) \
- (((x) >> 24) & 0x3F)
-
-#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
- (((x) >> 0) & 0x3F)
-#define CALTIMING4_CFG_PCH_TO_VALID(x) \
- (((x) >> 6) & 0x3F)
-#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
- (((x) >> 12) & 0x3F)
-#define CALTIMING4_CFG_ARF_TO_VALID(x) \
- (((x) >> 18) & 0xFF)
-#define CALTIMING4_CFG_PDN_TO_VALID(x) \
- (((x) >> 26) & 0x3F)
-
-#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
- (((x) >> 0) & 0xFF)
-
-/* Firewall DDR scheduler MPFE */
-#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
-#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
-
-#endif /* _SDRAM_S10_H_ */
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_enable(void)
+{
+ struct udevice *dev;
+
+ if (uclass_get_device(UCLASS_CACHE, 0, &dev))
+ pr_err("cache controller driver NOT found!\n");
+}
+
+void v7_outer_cache_disable(void)
{
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void socfpga_pl310_clear(void)
+{
+ u32 mask = 0xff, ena = 0;
+
+ icache_enable();
+
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
writel(0x0, &pl310->pl310_tag_latency_ctrl);
writel(0x10, &pl310->pl310_data_latency_ctrl);
L310_SHARED_ATT_OVERRIDE_ENABLE);
/* Enable the L2 cache */
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
+ ena = readl(&pl310->pl310_ctrl);
+ ena |= L2X0_CTRL_EN;
+
+ /*
+ * Invalidate the PL310 L2 cache. Keep the invalidation code
+ * entirely in L1 I-cache to avoid any bus traffic through
+ * the L2.
+ */
+ asm volatile(
+ ".align 5 \n"
+ " b 3f \n"
+ "1: str %1, [%4] \n"
+ " dsb \n"
+ " isb \n"
+ " str %0, [%2] \n"
+ " dsb \n"
+ " isb \n"
+ "2: ldr %0, [%2] \n"
+ " cmp %0, #0 \n"
+ " bne 2b \n"
+ " str %0, [%3] \n"
+ " dsb \n"
+ " isb \n"
+ " b 4f \n"
+ "3: b 1b \n"
+ "4: nop \n"
+ : "+r"(mask), "+r"(ena)
+ : "r"(&pl310->pl310_inv_way),
+ "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
+ : "memory", "cc");
-void v7_outer_cache_disable(void)
-{
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#ifndef CONFIG_SPL_BUILD
static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (argc != 2)
+ unsigned int mask = ~0;
+
+ if (argc < 2 || argc > 3)
return CMD_RET_USAGE;
argv++;
+ if (argc == 3)
+ mask = simple_strtoul(argv[1], NULL, 16);
+
switch (*argv[0]) {
case 'e': /* Enable */
- do_bridge_reset(1);
+ do_bridge_reset(1, mask);
break;
case 'd': /* Disable */
- do_bridge_reset(0);
+ do_bridge_reset(0, mask);
break;
default:
return CMD_RET_USAGE;
return 0;
}
-U_BOOT_CMD(bridge, 2, 1, do_bridge,
+U_BOOT_CMD(bridge, 3, 1, do_bridge,
"SoCFPGA HPS FPGA bridge control",
- "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
- "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+ "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+ "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
""
);
}
#endif
-void do_bridge_reset(int enable)
+void do_bridge_reset(int enable, unsigned int mask)
{
if (enable)
socfpga_reset_deassert_bridges_handoff();
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
-static void socfpga_sdram_apply_static_cfg(void)
+void do_bridge_reset(int enable, unsigned int mask)
{
- const u32 applymask = 0x8;
- u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
-
- /*
- * SDRAM staticcfg register specific:
- * When applying the register setting, the CPU must not access
- * SDRAM. Luckily for us, we can abuse i-cache here to help us
- * circumvent the SDRAM access issue. The idea is to make sure
- * that the code is in one full i-cache line by branching past
- * it and back. Once it is in the i-cache, we execute the core
- * of the code and apply the register settings.
- *
- * The code below uses 7 instructions, while the Cortex-A9 has
- * 32-byte cachelines, thus the limit is 8 instructions total.
- */
- asm volatile(
- ".align 5 \n"
- " b 2f \n"
- "1: str %0, [%1] \n"
- " dsb \n"
- " isb \n"
- " b 3f \n"
- "2: b 1b \n"
- "3: nop \n"
- : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
-}
+ int i;
-void do_bridge_reset(int enable)
-{
if (enable) {
+ socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
+ !(mask & BIT(1)),
+ !(mask & BIT(2)));
+ for (i = 0; i < 2; i++) { /* Reload SW setting cache */
+ iswgrp_handoff[i] =
+ readl(&sysmgr_regs->iswgrp_handoff[i]);
+ }
+
writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
- socfpga_sdram_apply_static_cfg();
writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
writel(iswgrp_handoff[1], &nic301_regs->remap);
} else {
writel(0, &sysmgr_regs->fpgaintfgrp_module);
writel(0, &sdr_ctrl->fpgaport_rst);
- socfpga_sdram_apply_static_cfg();
writel(0, &reset_manager_base->brg_mod_reset);
writel(1, &nic301_regs->remap);
}
#include <asm/arch/misc.h>
#include <asm/pl310.h>
#include <linux/libfdt.h>
+#include <asm/arch/mailbox_s10.h>
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
return 0;
}
-void do_bridge_reset(int enable)
+void do_bridge_reset(int enable, unsigned int mask)
{
+ /* Check FPGA status before bridge enable */
+ if (enable) {
+ int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
+
+ if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
+ ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
+
+ if (ret)
+ return;
+ }
+
socfpga_bridges_reset(enable);
}
writel(0xffffffff, &reset_manager_base->per2_mod_reset);
}
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, &reset_manager_base->per_mod_reset);
-}
-
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
#define L3REGS_REMAP_OCRAM_MASK 0x01
+void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
+{
+ u32 brgmask = 0x0;
+ u32 l3rmask = L3REGS_REMAP_OCRAM_MASK;
+
+ if (h2f)
+ brgmask |= BIT(0);
+ else
+ l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK;
+
+ if (lwh2f)
+ brgmask |= BIT(1);
+ else
+ l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK;
+
+ if (f2h)
+ brgmask |= BIT(2);
+
+ writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
+ writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
+}
+
void socfpga_bridges_reset(int enable)
{
const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
if (enable) {
/* brdmodrst */
- writel(0xffffffff, &reset_manager_base->brg_mod_reset);
+ writel(0x7, &reset_manager_base->brg_mod_reset);
+ writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
} else {
- writel(0, &sysmgr_regs->iswgrp_handoff[0]);
- writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
+ socfpga_bridges_set_handoff_regs(false, false, false);
/* Check signal from FPGA. */
if (!fpgamgr_test_fpga_ready()) {
/* clear idle request to all bridges */
setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
- /* Release bridges from reset state per handoff value */
+ /* Release all bridges from reset state */
clrbits_le32(&reset_manager_base->brgmodrst, ~0);
/* Poll until all idleack to 0 */
(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
;
- /* Put all bridges (except NOR DDR scheduler) into reset */
+ /* Reset all bridges (except NOR DDR scheduler & F2S) */
setbits_le32(&reset_manager_base->brgmodrst,
- ~RSTMGR_BRGMODRST_DDRSCH_MASK);
+ ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
+ RSTMGR_BRGMODRST_FPGA2SOC_MASK));
/* Disable NOC timeout */
writel(0, &system_manager_base->noc_timeout);
}
}
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, &reset_manager_base->per1modrst);
- /* Enable OCP first */
- writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
- writel(0, &reset_manager_base->per0modrst);
-}
-
/*
* Return non-zero if the CPU has been warm reset
*/
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
*/
#include <common.h>
#include <fdtdec.h>
#include <watchdog.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/fpga_manager.h>
+#include <mmc.h>
+#include <memalign.h>
+
+#define FPGA_BUFSIZ 16 * 1024
DECLARE_GLOBAL_DATA_PTR;
void spl_board_init(void)
{
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
+
/* enable console uart printing */
preloader_console_init();
WATCHDOG_RESET();
arch_early_init_r();
+
+ /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+ if (is_fpgamgr_user_mode()) {
+ int ret = config_pins(gd->fdt_blob, "shared");
+
+ if (ret)
+ return;
+
+ ret = config_pins(gd->fdt_blob, "fpga");
+ if (ret)
+ return;
+ } else if (!is_fpgamgr_early_user_mode()) {
+ /* Program IOSSM(early IO release) or full FPGA */
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+ }
+
+ /* If the IOSSM/full FPGA is already loaded, start DDR */
+ if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+ ddr_calibration_sequence();
+
+ if (!is_fpgamgr_user_mode())
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
}
void board_init_f(ulong dummy)
socfpga_init_security_policies();
socfpga_sdram_remap_zero();
+ socfpga_pl310_clear();
/* Assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();
#include <common.h>
#include <asm/io.h>
-#include <asm/pl310.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <image.h>
DECLARE_GLOBAL_DATA_PTR;
-static struct pl310_regs *const pl310 =
- (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
}
#endif
-static void socfpga_pl310_clear(void)
-{
- u32 mask = 0xff, ena = 0;
-
- icache_enable();
-
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x111, &pl310->pl310_tag_latency_ctrl);
- writel(0x121, &pl310->pl310_data_latency_ctrl);
-
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(&pl310->pl310_aux_ctrl,
- L310_AUX_CTRL_DATA_PREFETCH_MASK |
- L310_AUX_CTRL_INST_PREFETCH_MASK |
- L310_SHARED_ATT_OVERRIDE_ENABLE);
-
- /* Enable the L2 cache */
- ena = readl(&pl310->pl310_ctrl);
- ena |= L2X0_CTRL_EN;
-
- /*
- * Invalidate the PL310 L2 cache. Keep the invalidation code
- * entirely in L1 I-cache to avoid any bus traffic through
- * the L2.
- */
- asm volatile(
- ".align 5 \n"
- " b 3f \n"
- "1: str %1, [%4] \n"
- " dsb \n"
- " isb \n"
- " str %0, [%2] \n"
- " dsb \n"
- " isb \n"
- "2: ldr %0, [%2] \n"
- " cmp %0, #0 \n"
- " bne 2b \n"
- " str %0, [%3] \n"
- " dsb \n"
- " isb \n"
- " b 4f \n"
- "3: b 1b \n"
- "4: nop \n"
- : "+r"(mask), "+r"(ena)
- : "r"(&pl310->pl310_inv_way),
- "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
- : "memory", "cc");
-
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-
void board_init_f(ulong dummy)
{
const struct cm_config *cm_default_cfg = cm_get_default_config();
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
- /* De-assert reset for bridges based on handoff */
- socfpga_bridges_reset(0);
+ /* Set bridges handoff value */
+ socfpga_bridges_set_handoff_regs(true, true, true);
debug("Unfreezing/Thaw all I/O banks\n");
/* unfreeze / thaw all IO banks */
debug("DRAM init failed: %d\n", ret);
hang();
}
-
- if (!socfpga_is_booting_from_fpga())
- socfpga_bridges_reset(1);
}
#include <asm/arch/firewall_s10.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/reset_manager.h>
-#include <asm/arch/sdram_s10.h>
#include <asm/arch/system_manager.h>
#include <watchdog.h>
+#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
- debug("DDR: Initializing Hard Memory Controller\n");
- if (sdram_mmr_init_full(0)) {
- puts("DDR: Initialization failed.\n");
- hang();
- }
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+ struct udevice *dev;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ hang();
+ }
+#endif
mbox_init();
O_I_WB_RD_WR_ALLOC, REGION_16MB },
#endif
+ { 0x90000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+ SHARED_WRITE_BUFFERED, REGION_256MB },
+
#if defined(CONFIG_STM32F7) || defined(CONFIG_STM32H7)
{ 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_512MB },
select SPL_DM_RESET
select SPL_SERIAL_SUPPORT
select SPL_SYSCON
+ imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
+ imply SPL_BOOTSTAGE if BOOTSTAGE
imply SPL_DISPLAY_PRINT
imply SPL_LIBDISK_SUPPORT
config SYS_SOC
default "stm32mp"
+config SYS_MALLOC_LEN
+ default 0x2000000
+
+config ENV_SIZE
+ default 0x1000
+
config TARGET_STM32MP1
bool "Support stm32mp1xx"
select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
select STM32_RCC
select STM32_RESET
select SYS_ARCH_TIMER
+ imply BOOTCOUNT_LIMIT
+ imply BOOTSTAGE
+ imply CMD_BOOTCOUNT
+ imply CMD_BOOTSTAGE
imply SYSRESET_PSCI if STM32MP1_TRUSTED
imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
help
Partition on the second MMC to load U-Boot from when the MMC is being
used in raw mode
+config BOOTSTAGE_STASH_ADDR
+ default 0xC3000000
+
+if BOOTCOUNT_LIMIT
+config SYS_BOOTCOUNT_SINGLEWORD
+ default y
+
+# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
+config SYS_BOOTCOUNT_ADDR
+ default 0x5C00A154
+endif
+
if DEBUG_UART
config DEBUG_UART_BOARD_INIT
#include <dm.h>
#include <misc.h>
#include <asm/io.h>
-#include <linux/iopoll.h>
#include <asm/arch/stm32mp1_smc.h>
#include <linux/arm-smccc.h>
+#include <linux/iopoll.h>
#define BSEC_OTP_MAX_VALUE 95
#ifndef __MACH_STM32MP_DDR_H_
#define __MACH_STM32MP_DDR_H_
-int board_ddr_power_init(void);
+/* DDR power initializations */
+enum ddr_type {
+ STM32MP_DDR3,
+ STM32MP_LPDDR2,
+ STM32MP_LPDDR3,
+};
+
+int board_ddr_power_init(enum ddr_type ddr_type);
#endif
#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
+#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21)
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
#define TAMP_BOOT_MODE_SHIFT 8
return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
}
-static void __secure stm32mp_smp_kick_all_cpus(void)
+static void __secure stm32mp_raise_sgi0(int cpu)
{
u32 gic_dist_addr;
gic_dist_addr = stm32mp_get_gicd_base_address();
- /* kick all CPUs (except this one) by writing to GICD_SGIR */
- writel(1U << 24, gic_dist_addr + GICD_SGIR);
+ /* ask cpu with SGI0 */
+ writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
}
void __secure psci_arch_cpu_entry(void)
u32 cpu = psci_get_cpu_id();
psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
+
+ /* reset magic in TAMP register */
+ writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
}
int __secure psci_features(u32 function_id, u32 psci_fid)
if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
return ARM_PSCI_RET_ALREADY_ON;
+ /* reset magic in TAMP register */
+ if (readl(TAMP_BACKUP_MAGIC_NUMBER))
+ writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
+ /*
+ * ROM code need a first SGI0 after core reset
+ * core is ready when magic is set to 0 in ROM code
+ */
+ while (readl(TAMP_BACKUP_MAGIC_NUMBER))
+ stm32mp_raise_sgi0(cpu);
+
/* store target PC and context id*/
psci_save(cpu, pc, context_id);
writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
TAMP_BACKUP_MAGIC_NUMBER);
- stm32mp_smp_kick_all_cpus();
+ /* Generate an IT to start the core */
+ stm32mp_raise_sgi0(cpu);
return ARM_PSCI_RET_SUCCESS;
}
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
+#if defined(CONFIG_MACH_SUN50I_H6)
+ /* WDOG is broken for some H6 rev. use the R_WDOG instead */
static const struct sunxi_wdog *wdog =
- ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
+ (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
+#else
+ static const struct sunxi_wdog *wdog =
+ ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+#endif
/* Set the watchdog for its shortest interval (.5s) and wait */
writel(WDT_CFG_RESET, &wdog->cfg);
writel(WDT_MODE_EN, &wdog->mode);
#endif
}
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
config SPL_SERIAL_SUPPORT
default y
+config TEGRA_CLKRST
+ bool
+
+config TEGRA_GP_PADCTRL
+ bool
+
config TEGRA_IVC
bool "Tegra IVC protocol"
help
U-Boot, it is typically used for communication between the main CPU
and various auxiliary processors.
+config TEGRA_MC
+ bool
+
+config TEGRA_PINCTRL
+ bool
+
+config TEGRA_PMC
+ bool
+
+config TEGRA_PMC_SECURE
+ bool
+ depends on TEGRA_PMC
+
config TEGRA_COMMON
bool "Tegra common options"
select BINMAN
select SPL
select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
+ select TEGRA_CLKRST
select TEGRA_COMMON
select TEGRA_GPIO
+ select TEGRA_GP_PADCTRL
+ select TEGRA_MC
select TEGRA_NO_BPMP
+ select TEGRA_PINCTRL
+ select TEGRA_PMC
config TEGRA_ARMV8_COMMON
bool "Tegra 64-bit common options"
select ARM64
select LINUX_KERNEL_IMAGE_HEADER
+ select POSITION_INDEPENDENT
select TEGRA_COMMON
if TEGRA_ARMV8_COMMON
config TEGRA210
bool "Tegra210 family"
select TEGRA_ARMV8_COMMON
+ select TEGRA_CLKRST
select TEGRA_GPIO
+ select TEGRA_GP_PADCTRL
+ select TEGRA_MC
select TEGRA_NO_BPMP
+ select TEGRA_PINCTRL
+ select TEGRA_PMC
+ select TEGRA_PMC_SECURE
config TEGRA186
bool "Tegra186 family"
config TEGRA_DISCONNECT_UDC_ON_BOOT
bool "Disconnect USB device mode controller on boot"
+ depends on CI_UDC
default y
help
When loading U-Boot into RAM over USB protocols using tools such as
# SPDX-License-Identifier: GPL-2.0+
#
-# (C) Copyright 2010-2015 Nvidia Corporation.
+# (C) Copyright 2010-2019 Nvidia Corporation.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifndef CONFIG_TEGRA186
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += cpu.o
obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
endif
-obj-y += ap.o
+obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o
obj-y += board.o board2.o
obj-y += cache.o
-obj-y += clock.o
-obj-y += pinmux-common.o
-obj-y += powergate.o
+obj-$(CONFIG_TEGRA_CLKRST) += clock.o
+obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o
+obj-$(CONFIG_TEGRA_PMC) += powergate.o
obj-y += xusb-padctl-dummy.o
-endif
-obj-$(CONFIG_ARM64) += arm64-mmu.o
+obj-$(CONFIG_ARM64) += arm64-mmu.o cboot.o
obj-y += dt-setup.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
obj-$(CONFIG_TEGRA_GPU) += gpu.o
obj-$(CONFIG_TEGRA_IVC) += ivc.o
-obj-y += lowlevel_init.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+obj-y += pmc.o
obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
#include <ns16550.h>
#include <spl.h>
#include <asm/io.h>
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
+#endif
+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
#include <asm/arch/funcmux.h>
+#endif
+#if IS_ENABLED(CONFIG_TEGRA_MC)
#include <asm/arch/mc.h>
+#endif
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/cboot.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/warmboot.h>
static bool from_spl __attribute__ ((section(".data")));
#ifndef CONFIG_SPL_BUILD
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3)
{
from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
+
+ /*
+ * The logic for this is somewhat indirect. The purpose of the marker
+ * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
+ * was loaded from a read-only instance of itself, which is something
+ * that can happen in secure boot setups. So basically the presence
+ * of the marker is an indication that U-Boot was loaded by one such
+ * special variant of U-Boot. Conversely, the absence of the marker
+ * indicates that this instance of U-Boot was loaded by something
+ * other than a special U-Boot. This could be SPL, but it could just
+ * as well be one of any number of other first stage bootloaders.
+ */
+ if (from_spl)
+ cboot_save_boot_params(r0, r1, r2, r3);
+
save_boot_params_ret();
}
#endif
}
#endif
+#if IS_ENABLED(CONFIG_TEGRA_MC)
/* Read the RAM size directly from the memory controller */
static phys_size_t query_sdram_size(void)
{
return size_bytes;
}
+#endif
int dram_init(void)
{
+ int err;
+
+ /* try to initialize DRAM from cboot DTB first */
+ err = cboot_dram_init();
+ if (err == 0)
+ return 0;
+
+#if IS_ENABLED(CONFIG_TEGRA_MC)
/* We do not initialise DRAM here. We just query the size */
gd->ram_size = query_sdram_size();
+#endif
+
return 0;
}
+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
static int uart_configs[] = {
#if defined(CONFIG_TEGRA20)
#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
}
}
}
+#endif
void board_init_uart_f(void)
{
+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
int uart_ids = 0; /* bit mask of which UART ids to enable */
#ifdef CONFIG_TEGRA_ENABLE_UARTA
uart_ids |= UARTE;
#endif
setup_uarts(uart_ids);
+#endif
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
};
#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016, NVIDIA CORPORATION.
- */
-
-#include <common.h>
-#include <asm/arch/tegra.h>
-
-int board_early_init_f(void)
-{
- return 0;
-}
-
-__weak int tegra_board_init(void)
-{
- return 0;
-}
-
-int board_init(void)
-{
- return tegra_board_init();
-}
-
-__weak int tegra_soc_board_init_late(void)
-{
- return 0;
-}
-
-int board_late_init(void)
-{
- return tegra_soc_board_init_late();
-}
#include <asm/io.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/cboot.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/pmu.h>
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/uart.h>
#include <asm/arch-tegra/warmboot.h>
#include <asm/arch-tegra/gpu.h>
#include <asm/arch-tegra/usb.h>
#include <asm/arch-tegra/xusb-padctl.h>
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
#include <asm/arch/clock.h>
+#endif
+#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/pmu.h>
+#endif
#include <asm/arch/tegra.h>
#ifdef CONFIG_TEGRA_CLOCK_SCALING
#include <asm/arch/emc.h>
__weak void gpio_early_init_uart(void) {}
__weak void pin_mux_display(void) {}
__weak void start_cpu_fan(void) {}
+__weak void cboot_late_init(void) {}
#if defined(CONFIG_TEGRA_NAND)
__weak void pin_mux_nand(void)
__maybe_unused int board_id;
/* Do clocks and UART first so that printf() works */
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
clock_init();
clock_verify();
+#endif
tegra_gpu_config();
int board_early_init_f(void)
{
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
if (!clock_early_init_done())
clock_early_init();
+#endif
#if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
#define USBCMD_FS2 (1 << 15)
#endif
/* Do any special system timer/TSC setup */
-#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
+# if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (!tegra_cpu_is_non_secure())
-#endif
+# endif
arch_timer_init();
+#endif
pinmux_init();
board_init_uart_f();
}
#endif
start_cpu_fan();
+ cboot_late_init();
return 0;
}
*/
int dram_init_banksize(void)
{
+ int err;
+
+ /* try to compute DRAM bank size based on cboot DTB first */
+ err = cboot_dram_init_banksize();
+ if (err == 0)
+ return err;
+
+ /* fall back to default DRAM bank size computation */
+
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
*/
ulong board_get_usable_ram_top(ulong total_size)
{
+ ulong ram_top;
+
+ /* try to get top of usable RAM based on cboot DTB first */
+ ram_top = cboot_get_usable_ram_top(total_size);
+ if (ram_top > 0)
+ return ram_top;
+
+ /* fall back to default usable RAM computation */
+
return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
}
#include <common.h>
#include <asm/io.h>
#include <asm/arch-tegra/ap.h>
+#if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL)
#include <asm/arch/gp_padctrl.h>
+#endif
#ifndef CONFIG_ARM64
void config_cache(void)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <linux/ctype.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/cboot.h>
+#include <asm/armv8/mmu.h>
+
+/*
+ * Size of a region that's large enough to hold the relocated U-Boot and all
+ * other allocations made around it (stack, heap, page tables, etc.)
+ * In practice, running "bdinfo" at the shell prompt, the stack reaches about
+ * 5MB from the address selected for ram_top as of the time of writing,
+ * so a 16MB region should be plenty.
+ */
+#define MIN_USABLE_RAM_SIZE SZ_16M
+/*
+ * The amount of space we expect to require for stack usage. Used to validate
+ * that all reservations fit into the region selected for the relocation target
+ */
+#define MIN_USABLE_STACK_SIZE SZ_1M
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct mm_region tegra_mem_map[];
+
+/*
+ * These variables are written to before relocation, and hence cannot be
+ * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary.
+ * The section attribute forces this into .data and avoids this issue. This
+ * also has the nice side-effect of the content being valid after relocation.
+ */
+
+/* The number of valid entries in ram_banks[] */
+static int ram_bank_count __attribute__((section(".data")));
+
+/*
+ * The usable top-of-RAM for U-Boot. This is both:
+ * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing.
+ * b) At the end of a region that has enough space to hold the relocated U-Boot
+ * and all other allocations made around it (stack, heap, page tables, etc.)
+ */
+static u64 ram_top __attribute__((section(".data")));
+/* The base address of the region of RAM that ends at ram_top */
+static u64 region_base __attribute__((section(".data")));
+
+/*
+ * Explicitly put this in the .data section because it is written before the
+ * .bss section is zeroed out but it needs to persist.
+ */
+unsigned long cboot_boot_x0 __attribute__((section(".data")));
+
+void cboot_save_boot_params(unsigned long x0, unsigned long x1,
+ unsigned long x2, unsigned long x3)
+{
+ cboot_boot_x0 = x0;
+}
+
+int cboot_dram_init(void)
+{
+ unsigned int na, ns;
+ const void *cboot_blob = (void *)cboot_boot_x0;
+ int node, len, i;
+ const u32 *prop;
+
+ if (!cboot_blob)
+ return -EINVAL;
+
+ na = fdtdec_get_uint(cboot_blob, 0, "#address-cells", 2);
+ ns = fdtdec_get_uint(cboot_blob, 0, "#size-cells", 2);
+
+ node = fdt_path_offset(cboot_blob, "/memory");
+ if (node < 0) {
+ pr_err("Can't find /memory node in cboot DTB");
+ hang();
+ }
+ prop = fdt_getprop(cboot_blob, node, "reg", &len);
+ if (!prop) {
+ pr_err("Can't find /memory/reg property in cboot DTB");
+ hang();
+ }
+
+ /* Calculate the true # of base/size pairs to read */
+ len /= 4; /* Convert bytes to number of cells */
+ len /= (na + ns); /* Convert cells to number of banks */
+ if (len > CONFIG_NR_DRAM_BANKS)
+ len = CONFIG_NR_DRAM_BANKS;
+
+ /* Parse the /memory node, and save useful entries */
+ gd->ram_size = 0;
+ ram_bank_count = 0;
+ for (i = 0; i < len; i++) {
+ u64 bank_start, bank_end, bank_size, usable_bank_size;
+
+ /* Extract raw memory region data from DTB */
+ bank_start = fdt_read_number(prop, na);
+ prop += na;
+ bank_size = fdt_read_number(prop, ns);
+ prop += ns;
+ gd->ram_size += bank_size;
+ bank_end = bank_start + bank_size;
+ debug("Bank %d: %llx..%llx (+%llx)\n", i,
+ bank_start, bank_end, bank_size);
+
+ /*
+ * Align the bank to MMU section size. This is not strictly
+ * necessary, since the translation table construction code
+ * handles page granularity without issue. However, aligning
+ * the MMU entries reduces the size and number of levels in the
+ * page table, so is worth it.
+ */
+ bank_start = ROUND(bank_start, SZ_2M);
+ bank_end = bank_end & ~(SZ_2M - 1);
+ bank_size = bank_end - bank_start;
+ debug(" aligned: %llx..%llx (+%llx)\n",
+ bank_start, bank_end, bank_size);
+ if (bank_end <= bank_start)
+ continue;
+
+ /* Record data used to create MMU translation tables */
+ ram_bank_count++;
+ /* Index below is deliberately 1-based to skip MMIO entry */
+ tegra_mem_map[ram_bank_count].virt = bank_start;
+ tegra_mem_map[ram_bank_count].phys = bank_start;
+ tegra_mem_map[ram_bank_count].size = bank_size;
+ tegra_mem_map[ram_bank_count].attrs =
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE;
+
+ /* Determine best bank to relocate U-Boot into */
+ if (bank_end > SZ_4G)
+ bank_end = SZ_4G;
+ debug(" end %llx (usable)\n", bank_end);
+ usable_bank_size = bank_end - bank_start;
+ debug(" size %llx (usable)\n", usable_bank_size);
+ if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) &&
+ (bank_end > ram_top)) {
+ ram_top = bank_end;
+ region_base = bank_start;
+ debug("ram top now %llx\n", ram_top);
+ }
+ }
+
+ /* Ensure memory map contains the desired sentinel entry */
+ tegra_mem_map[ram_bank_count + 1].virt = 0;
+ tegra_mem_map[ram_bank_count + 1].phys = 0;
+ tegra_mem_map[ram_bank_count + 1].size = 0;
+ tegra_mem_map[ram_bank_count + 1].attrs = 0;
+
+ /* Error out if a relocation target couldn't be found */
+ if (!ram_top) {
+ pr_err("Can't find a usable RAM top");
+ hang();
+ }
+
+ return 0;
+}
+
+int cboot_dram_init_banksize(void)
+{
+ int i;
+
+ if (ram_bank_count == 0)
+ return -EINVAL;
+
+ if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) {
+ pr_err("Reservations exceed chosen region size");
+ hang();
+ }
+
+ for (i = 0; i < ram_bank_count; i++) {
+ gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
+ gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
+ }
+
+#ifdef CONFIG_PCI
+ gd->pci_ram_top = ram_top;
+#endif
+
+ return 0;
+}
+
+ulong cboot_get_usable_ram_top(ulong total_size)
+{
+ return ram_top;
+}
+
+/*
+ * The following few functions run late during the boot process and dynamically
+ * calculate the load address of various binaries. To keep track of multiple
+ * allocations, some writable list of RAM banks must be used. tegra_mem_map[]
+ * is used for this purpose to avoid making yet another copy of the list of RAM
+ * banks. This is safe because tegra_mem_map[] is only used once during very
+ * early boot to create U-Boot's page tables, long before this code runs. If
+ * this assumption becomes invalid later, we can just fix the code to copy the
+ * list of RAM banks into some private data structure before running.
+ */
+
+static char *gen_varname(const char *var, const char *ext)
+{
+ size_t len_var = strlen(var);
+ size_t len_ext = strlen(ext);
+ size_t len = len_var + len_ext + 1;
+ char *varext = malloc(len);
+
+ if (!varext)
+ return 0;
+ strcpy(varext, var);
+ strcpy(varext + len_var, ext);
+ return varext;
+}
+
+static void mark_ram_allocated(int bank, u64 allocated_start, u64 allocated_end)
+{
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+ bool keep_front = allocated_start != bank_start;
+ bool keep_tail = allocated_end != bank_end;
+
+ if (keep_front && keep_tail) {
+ /*
+ * There are CONFIG_NR_DRAM_BANKS DRAM entries in the array,
+ * starting at index 1 (index 0 is MMIO). So, we are at DRAM
+ * entry "bank" not "bank - 1" as for a typical 0-base array.
+ * The number of remaining DRAM entries is therefore
+ * "CONFIG_NR_DRAM_BANKS - bank". We want to duplicate the
+ * current entry and shift up the remaining entries, dropping
+ * the last one. Thus, we must copy one fewer entry than the
+ * number remaining.
+ */
+ memmove(&tegra_mem_map[bank + 1], &tegra_mem_map[bank],
+ CONFIG_NR_DRAM_BANKS - bank - 1);
+ tegra_mem_map[bank].size = allocated_start - bank_start;
+ bank++;
+ tegra_mem_map[bank].virt = allocated_end;
+ tegra_mem_map[bank].phys = allocated_end;
+ tegra_mem_map[bank].size = bank_end - allocated_end;
+ } else if (keep_front) {
+ tegra_mem_map[bank].size = allocated_start - bank_start;
+ } else if (keep_tail) {
+ tegra_mem_map[bank].virt = allocated_end;
+ tegra_mem_map[bank].phys = allocated_end;
+ tegra_mem_map[bank].size = bank_end - allocated_end;
+ } else {
+ /*
+ * We could move all subsequent banks down in the array but
+ * that's not necessary for subsequent allocations to work, so
+ * we skip doing so.
+ */
+ tegra_mem_map[bank].size = 0;
+ }
+}
+
+static void reserve_ram(u64 start, u64 size)
+{
+ int bank;
+ u64 end = start + size;
+
+ for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+
+ if (end <= bank_start || start > bank_end)
+ continue;
+ mark_ram_allocated(bank, start, end);
+ break;
+ }
+}
+
+static u64 alloc_ram(u64 size, u64 align, u64 offset)
+{
+ int bank;
+
+ for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+ u64 allocated = ROUND(bank_start, align) + offset;
+ u64 allocated_end = allocated + size;
+
+ if (allocated_end > bank_end)
+ continue;
+ mark_ram_allocated(bank, allocated, allocated_end);
+ return allocated;
+ }
+ return 0;
+}
+
+static void set_calculated_aliases(char *aliases, u64 address)
+{
+ char *tmp, *alias;
+ int err;
+
+ aliases = strdup(aliases);
+ if (!aliases) {
+ pr_err("strdup(aliases) failed");
+ return;
+ }
+
+ tmp = aliases;
+ while (true) {
+ alias = strsep(&tmp, " ");
+ if (!alias)
+ break;
+ debug("%s: alias: %s\n", __func__, alias);
+ err = env_set_hex(alias, address);
+ if (err)
+ pr_err("Could not set %s\n", alias);
+ }
+
+ free(aliases);
+}
+
+static void set_calculated_env_var(const char *var)
+{
+ char *var_size;
+ char *var_align;
+ char *var_offset;
+ char *var_aliases;
+ u64 size;
+ u64 align;
+ u64 offset;
+ char *aliases;
+ u64 address;
+ int err;
+
+ var_size = gen_varname(var, "_size");
+ if (!var_size)
+ return;
+ var_align = gen_varname(var, "_align");
+ if (!var_align)
+ goto out_free_var_size;
+ var_offset = gen_varname(var, "_offset");
+ if (!var_offset)
+ goto out_free_var_align;
+ var_aliases = gen_varname(var, "_aliases");
+ if (!var_aliases)
+ goto out_free_var_offset;
+
+ size = env_get_hex(var_size, 0);
+ if (!size) {
+ pr_err("%s not set or zero\n", var_size);
+ goto out_free_var_aliases;
+ }
+ align = env_get_hex(var_align, 1);
+ /* Handle extant variables, but with a value of 0 */
+ if (!align)
+ align = 1;
+ offset = env_get_hex(var_offset, 0);
+ aliases = env_get(var_aliases);
+
+ debug("%s: Calc var %s; size=%llx, align=%llx, offset=%llx\n",
+ __func__, var, size, align, offset);
+ if (aliases)
+ debug("%s: Aliases: %s\n", __func__, aliases);
+
+ address = alloc_ram(size, align, offset);
+ if (!address) {
+ pr_err("Could not allocate %s\n", var);
+ goto out_free_var_aliases;
+ }
+ debug("%s: Address %llx\n", __func__, address);
+
+ err = env_set_hex(var, address);
+ if (err)
+ pr_err("Could not set %s\n", var);
+ if (aliases)
+ set_calculated_aliases(aliases, address);
+
+out_free_var_aliases:
+ free(var_aliases);
+out_free_var_offset:
+ free(var_offset);
+out_free_var_align:
+ free(var_align);
+out_free_var_size:
+ free(var_size);
+}
+
+#ifdef DEBUG
+static void dump_ram_banks(void)
+{
+ int bank;
+
+ for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
+ u64 bank_start = tegra_mem_map[bank].virt;
+ u64 bank_size = tegra_mem_map[bank].size;
+ u64 bank_end = bank_start + bank_size;
+
+ if (!bank_size)
+ continue;
+ printf("%d: %010llx..%010llx (+%010llx)\n", bank - 1,
+ bank_start, bank_end, bank_size);
+ }
+}
+#endif
+
+static void set_calculated_env_vars(void)
+{
+ char *vars, *tmp, *var;
+
+#ifdef DEBUG
+ printf("RAM banks before any calculated env. var.s:\n");
+ dump_ram_banks();
+#endif
+
+ reserve_ram(cboot_boot_x0, fdt_totalsize(cboot_boot_x0));
+
+#ifdef DEBUG
+ printf("RAM after reserving cboot DTB:\n");
+ dump_ram_banks();
+#endif
+
+ vars = env_get("calculated_vars");
+ if (!vars) {
+ debug("%s: No env var calculated_vars\n", __func__);
+ return;
+ }
+
+ vars = strdup(vars);
+ if (!vars) {
+ pr_err("strdup(calculated_vars) failed");
+ return;
+ }
+
+ tmp = vars;
+ while (true) {
+ var = strsep(&tmp, " ");
+ if (!var)
+ break;
+ debug("%s: var: %s\n", __func__, var);
+ set_calculated_env_var(var);
+#ifdef DEBUG
+ printf("RAM banks after allocating %s:\n", var);
+ dump_ram_banks();
+#endif
+ }
+
+ free(vars);
+}
+
+static int set_fdt_addr(void)
+{
+ int ret;
+
+ ret = env_set_hex("fdt_addr", cboot_boot_x0);
+ if (ret) {
+ printf("Failed to set fdt_addr to point at DTB: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * Attempt to use /chosen/nvidia,ether-mac in the cboot DTB to U-Boot's
+ * ethaddr environment variable if possible.
+ */
+static int cboot_get_ethaddr_legacy(const void *fdt, uint8_t mac[ETH_ALEN])
+{
+ const char *const properties[] = {
+ "nvidia,ethernet-mac",
+ "nvidia,ether-mac",
+ };
+ const char *prop;
+ unsigned int i;
+ int node, len;
+
+ node = fdt_path_offset(fdt, "/chosen");
+ if (node < 0) {
+ printf("Can't find /chosen node in cboot DTB\n");
+ return node;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(properties); i++) {
+ prop = fdt_getprop(fdt, node, properties[i], &len);
+ if (prop)
+ break;
+ }
+
+ if (!prop) {
+ printf("Can't find Ethernet MAC address in cboot DTB\n");
+ return -ENOENT;
+ }
+
+ eth_parse_enetaddr(prop, mac);
+
+ if (!is_valid_ethaddr(mac)) {
+ printf("Invalid MAC address: %s\n", prop);
+ return -EINVAL;
+ }
+
+ debug("Legacy MAC address: %pM\n", mac);
+
+ return 0;
+}
+
+int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN])
+{
+ int node, len, err = 0;
+ const uchar *prop;
+ const char *path;
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path) {
+ err = -ENOENT;
+ goto out;
+ }
+
+ debug("ethernet alias found: %s\n", path);
+
+ node = fdt_path_offset(fdt, path);
+ if (node < 0) {
+ err = -ENOENT;
+ goto out;
+ }
+
+ prop = fdt_getprop(fdt, node, "local-mac-address", &len);
+ if (!prop) {
+ err = -ENOENT;
+ goto out;
+ }
+
+ if (len != ETH_ALEN) {
+ err = -EINVAL;
+ goto out;
+ }
+
+ debug("MAC address: %pM\n", prop);
+ memcpy(mac, prop, ETH_ALEN);
+
+out:
+ if (err < 0)
+ err = cboot_get_ethaddr_legacy(fdt, mac);
+
+ return err;
+}
+
+static char *strip(const char *ptr)
+{
+ const char *end;
+
+ while (*ptr && isblank(*ptr))
+ ptr++;
+
+ /* empty string */
+ if (*ptr == '\0')
+ return strdup(ptr);
+
+ end = ptr;
+
+ while (end[1])
+ end++;
+
+ while (isblank(*end))
+ end--;
+
+ return strndup(ptr, end - ptr + 1);
+}
+
+static char *cboot_get_bootargs(const void *fdt)
+{
+ const char *args;
+ int offset, len;
+
+ offset = fdt_path_offset(fdt, "/chosen");
+ if (offset < 0)
+ return NULL;
+
+ args = fdt_getprop(fdt, offset, "bootargs", &len);
+ if (!args)
+ return NULL;
+
+ return strip(args);
+}
+
+int cboot_late_init(void)
+{
+ const void *fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN];
+ char *bootargs;
+ int err;
+
+ set_calculated_env_vars();
+ /*
+ * Ignore errors here; the value may not be used depending on
+ * extlinux.conf or boot script content.
+ */
+ set_fdt_addr();
+
+ /* Ignore errors here; not all cases care about Ethernet addresses */
+ err = cboot_get_ethaddr(fdt, mac);
+ if (!err) {
+ void *blob = (void *)gd->fdt_blob;
+
+ err = fdtdec_set_ethernet_mac_address(blob, mac, sizeof(mac));
+ if (err < 0)
+ printf("failed to set MAC address %pM: %d\n", mac, err);
+ }
+
+ bootargs = cboot_get_bootargs(fdt);
+ if (bootargs) {
+ env_set("cbootargs", bootargs);
+ free(bootargs);
+ }
+
+ return 0;
+}
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
*/
/* Tegra SoC common clock control functions */
reset_set_enable(periph_id, 1);
clock_enable(periph_id);
+ udelay(2);
effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
NULL);
int clock_external_output(int clk_id)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 val;
if (clk_id >= 1 && clk_id <= 3) {
- setbits_le32(&pmc->pmc_clk_out_cntrl,
- 1 << (2 + (clk_id - 1) * 8));
+ val = tegra_pmc_readl(offsetof(struct pmc_ctlr,
+ pmc_clk_out_cntrl));
+ val |= 1 << (2 + (clk_id - 1) * 8);
+ tegra_pmc_writel(val,
+ offsetof(struct pmc_ctlr,
+ pmc_clk_out_cntrl));
+
} else {
printf("%s: Unknown output clock id %d\n", __func__, clk_id);
return -EINVAL;
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
*
* Derived from code (arch/arm/lib/reset.c) that is:
*
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
puts("Entering RCM...\n");
udelay(50000);
- pmc->pmc_scratch0 = 2;
+ tegra_pmc_writel(2, PMC_SCRATCH0);
disable_interrupts();
reset_cpu(0);
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
*/
#include <common.h>
static int is_cpu_powered(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
+ return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
+ pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
}
static void remove_cpu_io_clamps(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
debug("%s entry\n", __func__);
/* Remove the clamps on the CPU I/O signals */
- reg = readl(&pmc->pmc_remove_clamping);
+ reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
reg |= CPU_CLMP;
- writel(reg, &pmc->pmc_remove_clamping);
+ tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));
/* Give I/O signals time to stabilize */
udelay(IO_STABILIZATION_DELAY);
void powerup_cpu(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
debug("%s entry\n", __func__);
if (!is_cpu_powered()) {
/* Toggle the CPU power state (OFF -> ON) */
- reg = readl(&pmc->pmc_pwrgate_toggle);
+ reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
+ pmc_pwrgate_toggle));
reg &= PARTID_CP;
reg |= START_CP;
- writel(reg, &pmc->pmc_pwrgate_toggle);
+ tegra_pmc_writel(reg,
+ offsetof(struct pmc_ctlr,
+ pmc_pwrgate_toggle));
/* Wait for the power to come up */
while (!is_cpu_powered()) {
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
-#include <asm/arch/pmu.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmu.h>
#include <asm/arch-tegra/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * SoC-specific setup info
- *
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-#ifdef CONFIG_ARM64
- .align 5
-ENTRY(reset_cpu)
- /* get address for global reset register */
- ldr x1, =PRM_RSTCTRL
- ldr w3, [x1]
- /* force reset */
- orr w3, w3, #0x10
- str w3, [x1]
- mov w0, w0
-1:
- b 1b
-ENDPROC(reset_cpu)
-#else
- .align 5
-ENTRY(reset_cpu)
- ldr r1, rstctl @ get addr for global reset
- @ reg
- ldr r3, [r1]
- orr r3, r3, #0x10
- str r3, [r1] @ force reset
- mov r0, r0
-_loop_forever:
- b _loop_forever
-rstctl:
- .word PRM_RSTCTRL
-ENDPROC(reset_cpu)
-#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <common.h>
+
+#include <linux/arm-smccc.h>
+
+#include <asm/io.h>
+#include <asm/arch-tegra/pmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
+static bool tegra_pmc_detect_tz_only(void)
+{
+ static bool initialized = false;
+ static bool is_tz_only = false;
+ u32 value, saved;
+
+ if (!initialized) {
+ saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
+ value = saved ^ 0xffffffff;
+
+ if (value == 0xffffffff)
+ value = 0xdeadbeef;
+
+ /* write pattern and read it back */
+ writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
+ value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
+
+ /* if we read all-zeroes, access is restricted to TZ only */
+ if (value == 0) {
+ debug("access to PMC is restricted to TZ\n");
+ is_tz_only = true;
+ } else {
+ /* restore original value */
+ writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
+ }
+
+ initialized = true;
+ }
+
+ return is_tz_only;
+}
+#endif
+
+uint32_t tegra_pmc_readl(unsigned long offset)
+{
+#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
+ if (tegra_pmc_detect_tz_only()) {
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
+ 0, 0, 0, &res);
+ if (res.a0)
+ printf("%s(): SMC failed: %lu\n", __func__, res.a0);
+
+ return res.a1;
+ }
+#endif
+
+ return readl(NV_PA_PMC_BASE + offset);
+}
+
+void tegra_pmc_writel(u32 value, unsigned long offset)
+{
+#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
+ if (tegra_pmc_detect_tz_only()) {
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
+ value, 0, 0, 0, 0, &res);
+ if (res.a0)
+ printf("%s(): SMC failed: %lu\n", __func__, res.a0);
+
+ return;
+ }
+#endif
+
+ writel(value, NV_PA_PMC_BASE + offset);
+}
+
+void reset_cpu(ulong addr)
+{
+ u32 value;
+
+ value = tegra_pmc_readl(PMC_CNTRL);
+ value |= PMC_CNTRL_MAIN_RST;
+ tegra_pmc_writel(value, PMC_CNTRL);
+}
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*/
#include <common.h>
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/pmc.h>
#define PWRGATE_TOGGLE 0x30
#define PWRGATE_TOGGLE_START (1 << 8)
u32 value, mask = state ? (1 << id) : 0, old_mask;
unsigned long start, timeout = 25;
- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ value = tegra_pmc_readl(PWRGATE_STATUS);
old_mask = value & (1 << id);
if (mask == old_mask)
return 0;
- writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
+ tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
start = get_timer(0);
while (get_timer(start) < timeout) {
- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
+ value = tegra_pmc_readl(PWRGATE_STATUS);
if ((value & (1 << id)) == mask)
return 0;
}
else
value = 1 << id;
- writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
+ tegra_pmc_writel(value, REMOVE_CLAMPING);
return 0;
}
*/
#define CLK(x) CLOCK_ID_ ## x
static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
- { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
+ { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(CLK_M),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
MASK_BITS_31_30},
{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
#
# SPDX-License-Identifier: GPL-2.0
-obj-y += ../board186.o
obj-y += cache.o
-obj-y += nvtboot_board.o
-obj-y += nvtboot_ll.o
-obj-y += nvtboot_mem.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.
- */
-
-#include <stdlib.h>
-#include <common.h>
-#include <fdt_support.h>
-#include <fdtdec.h>
-#include <asm/arch/tegra.h>
-#include <asm/armv8/mmu.h>
-
-extern unsigned long nvtboot_boot_x0;
-
-/*
- * The following few functions run late during the boot process and dynamically
- * calculate the load address of various binaries. To keep track of multiple
- * allocations, some writable list of RAM banks must be used. tegra_mem_map[]
- * is used for this purpose to avoid making yet another copy of the list of RAM
- * banks. This is safe because tegra_mem_map[] is only used once during very
- * early boot to create U-Boot's page tables, long before this code runs. If
- * this assumption becomes invalid later, we can just fix the code to copy the
- * list of RAM banks into some private data structure before running.
- */
-
-extern struct mm_region tegra_mem_map[];
-
-static char *gen_varname(const char *var, const char *ext)
-{
- size_t len_var = strlen(var);
- size_t len_ext = strlen(ext);
- size_t len = len_var + len_ext + 1;
- char *varext = malloc(len);
-
- if (!varext)
- return 0;
- strcpy(varext, var);
- strcpy(varext + len_var, ext);
- return varext;
-}
-
-static void mark_ram_allocated(int bank, u64 allocated_start, u64 allocated_end)
-{
- u64 bank_start = tegra_mem_map[bank].virt;
- u64 bank_size = tegra_mem_map[bank].size;
- u64 bank_end = bank_start + bank_size;
- bool keep_front = allocated_start != bank_start;
- bool keep_tail = allocated_end != bank_end;
-
- if (keep_front && keep_tail) {
- /*
- * There are CONFIG_NR_DRAM_BANKS DRAM entries in the array,
- * starting at index 1 (index 0 is MMIO). So, we are at DRAM
- * entry "bank" not "bank - 1" as for a typical 0-base array.
- * The number of remaining DRAM entries is therefore
- * "CONFIG_NR_DRAM_BANKS - bank". We want to duplicate the
- * current entry and shift up the remaining entries, dropping
- * the last one. Thus, we must copy one fewer entry than the
- * number remaining.
- */
- memmove(&tegra_mem_map[bank + 1], &tegra_mem_map[bank],
- CONFIG_NR_DRAM_BANKS - bank - 1);
- tegra_mem_map[bank].size = allocated_start - bank_start;
- bank++;
- tegra_mem_map[bank].virt = allocated_end;
- tegra_mem_map[bank].phys = allocated_end;
- tegra_mem_map[bank].size = bank_end - allocated_end;
- } else if (keep_front) {
- tegra_mem_map[bank].size = allocated_start - bank_start;
- } else if (keep_tail) {
- tegra_mem_map[bank].virt = allocated_end;
- tegra_mem_map[bank].phys = allocated_end;
- tegra_mem_map[bank].size = bank_end - allocated_end;
- } else {
- /*
- * We could move all subsequent banks down in the array but
- * that's not necessary for subsequent allocations to work, so
- * we skip doing so.
- */
- tegra_mem_map[bank].size = 0;
- }
-}
-
-static void reserve_ram(u64 start, u64 size)
-{
- int bank;
- u64 end = start + size;
-
- for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
- u64 bank_start = tegra_mem_map[bank].virt;
- u64 bank_size = tegra_mem_map[bank].size;
- u64 bank_end = bank_start + bank_size;
-
- if (end <= bank_start || start > bank_end)
- continue;
- mark_ram_allocated(bank, start, end);
- break;
- }
-}
-
-static u64 alloc_ram(u64 size, u64 align, u64 offset)
-{
- int bank;
-
- for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
- u64 bank_start = tegra_mem_map[bank].virt;
- u64 bank_size = tegra_mem_map[bank].size;
- u64 bank_end = bank_start + bank_size;
- u64 allocated = ROUND(bank_start, align) + offset;
- u64 allocated_end = allocated + size;
-
- if (allocated_end > bank_end)
- continue;
- mark_ram_allocated(bank, allocated, allocated_end);
- return allocated;
- }
- return 0;
-}
-
-static void set_calculated_aliases(char *aliases, u64 address)
-{
- char *tmp, *alias;
- int err;
-
- aliases = strdup(aliases);
- if (!aliases) {
- pr_err("strdup(aliases) failed");
- return;
- }
-
- tmp = aliases;
- while (true) {
- alias = strsep(&tmp, " ");
- if (!alias)
- break;
- debug("%s: alias: %s\n", __func__, alias);
- err = env_set_hex(alias, address);
- if (err)
- pr_err("Could not set %s\n", alias);
- }
-
- free(aliases);
-}
-
-static void set_calculated_env_var(const char *var)
-{
- char *var_size;
- char *var_align;
- char *var_offset;
- char *var_aliases;
- u64 size;
- u64 align;
- u64 offset;
- char *aliases;
- u64 address;
- int err;
-
- var_size = gen_varname(var, "_size");
- if (!var_size)
- return;
- var_align = gen_varname(var, "_align");
- if (!var_align)
- goto out_free_var_size;
- var_offset = gen_varname(var, "_offset");
- if (!var_offset)
- goto out_free_var_align;
- var_aliases = gen_varname(var, "_aliases");
- if (!var_aliases)
- goto out_free_var_offset;
-
- size = env_get_hex(var_size, 0);
- if (!size) {
- pr_err("%s not set or zero\n", var_size);
- goto out_free_var_aliases;
- }
- align = env_get_hex(var_align, 1);
- /* Handle extant variables, but with a value of 0 */
- if (!align)
- align = 1;
- offset = env_get_hex(var_offset, 0);
- aliases = env_get(var_aliases);
-
- debug("%s: Calc var %s; size=%llx, align=%llx, offset=%llx\n",
- __func__, var, size, align, offset);
- if (aliases)
- debug("%s: Aliases: %s\n", __func__, aliases);
-
- address = alloc_ram(size, align, offset);
- if (!address) {
- pr_err("Could not allocate %s\n", var);
- goto out_free_var_aliases;
- }
- debug("%s: Address %llx\n", __func__, address);
-
- err = env_set_hex(var, address);
- if (err)
- pr_err("Could not set %s\n", var);
- if (aliases)
- set_calculated_aliases(aliases, address);
-
-out_free_var_aliases:
- free(var_aliases);
-out_free_var_offset:
- free(var_offset);
-out_free_var_align:
- free(var_align);
-out_free_var_size:
- free(var_size);
-}
-
-#ifdef DEBUG
-static void dump_ram_banks(void)
-{
- int bank;
-
- for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
- u64 bank_start = tegra_mem_map[bank].virt;
- u64 bank_size = tegra_mem_map[bank].size;
- u64 bank_end = bank_start + bank_size;
-
- if (!bank_size)
- continue;
- printf("%d: %010llx..%010llx (+%010llx)\n", bank - 1,
- bank_start, bank_end, bank_size);
- }
-}
-#endif
-
-static void set_calculated_env_vars(void)
-{
- char *vars, *tmp, *var;
-
-#ifdef DEBUG
- printf("RAM banks before any calculated env. var.s:\n");
- dump_ram_banks();
-#endif
-
- reserve_ram(nvtboot_boot_x0, fdt_totalsize(nvtboot_boot_x0));
-
-#ifdef DEBUG
- printf("RAM after reserving cboot DTB:\n");
- dump_ram_banks();
-#endif
-
- vars = env_get("calculated_vars");
- if (!vars) {
- debug("%s: No env var calculated_vars\n", __func__);
- return;
- }
-
- vars = strdup(vars);
- if (!vars) {
- pr_err("strdup(calculated_vars) failed");
- return;
- }
-
- tmp = vars;
- while (true) {
- var = strsep(&tmp, " ");
- if (!var)
- break;
- debug("%s: var: %s\n", __func__, var);
- set_calculated_env_var(var);
-#ifdef DEBUG
- printf("RAM banks affter allocating %s:\n", var);
- dump_ram_banks();
-#endif
- }
-
- free(vars);
-}
-
-static int set_fdt_addr(void)
-{
- int ret;
-
- ret = env_set_hex("fdt_addr", nvtboot_boot_x0);
- if (ret) {
- printf("Failed to set fdt_addr to point at DTB: %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-/*
- * Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's
- * ethaddr environment variable if possible.
- */
-static int set_ethaddr_from_nvtboot(void)
-{
- const void *nvtboot_blob = (void *)nvtboot_boot_x0;
- int ret, node, len;
- const u32 *prop;
-
- /* Already a valid address in the environment? If so, keep it */
- if (env_get("ethaddr"))
- return 0;
-
- node = fdt_path_offset(nvtboot_blob, "/chosen");
- if (node < 0) {
- printf("Can't find /chosen node in nvtboot DTB\n");
- return node;
- }
- prop = fdt_getprop(nvtboot_blob, node, "nvidia,ether-mac", &len);
- if (!prop) {
- printf("Can't find nvidia,ether-mac property in nvtboot DTB\n");
- return -ENOENT;
- }
-
- ret = env_set("ethaddr", (void *)prop);
- if (ret) {
- printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-int tegra_soc_board_init_late(void)
-{
- set_calculated_env_vars();
- /*
- * Ignore errors here; the value may not be used depending on
- * extlinux.conf or boot script content.
- */
- set_fdt_addr();
- /* Ignore errors here; not all cases care about Ethernet addresses */
- set_ethaddr_from_nvtboot();
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Save nvtboot-related boot-time CPU state
- *
- * (C) Copyright 2015-2016 NVIDIA Corporation <www.nvidia.com>
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-.align 8
-.globl nvtboot_boot_x0
-nvtboot_boot_x0:
- .dword 0
-
-ENTRY(save_boot_params)
- adr x8, nvtboot_boot_x0
- str x0, [x8]
- b save_boot_params_ret
-ENDPROC(save_boot_params)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <fdtdec.h>
-#include <linux/sizes.h>
-#include <asm/arch/tegra.h>
-#include <asm/armv8/mmu.h>
-
-/*
- * Size of a region that's large enough to hold the relocated U-Boot and all
- * other allocations made around it (stack, heap, page tables, etc.)
- * In practice, running "bdinfo" at the shell prompt, the stack reaches about
- * 5MB from the address selected for ram_top as of the time of writing,
- * so a 16MB region should be plenty.
- */
-#define MIN_USABLE_RAM_SIZE SZ_16M
-/*
- * The amount of space we expect to require for stack usage. Used to validate
- * that all reservations fit into the region selected for the relocation target
- */
-#define MIN_USABLE_STACK_SIZE SZ_1M
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern unsigned long nvtboot_boot_x0;
-extern struct mm_region tegra_mem_map[];
-
-/*
- * These variables are written to before relocation, and hence cannot be
- * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary.
- * The section attribute forces this into .data and avoids this issue. This
- * also has the nice side-effect of the content being valid after relocation.
- */
-
-/* The number of valid entries in ram_banks[] */
-static int ram_bank_count __attribute__((section(".data")));
-
-/*
- * The usable top-of-RAM for U-Boot. This is both:
- * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing.
- * b) At the end of a region that has enough space to hold the relocated U-Boot
- * and all other allocations made around it (stack, heap, page tables, etc.)
- */
-static u64 ram_top __attribute__((section(".data")));
-/* The base address of the region of RAM that ends at ram_top */
-static u64 region_base __attribute__((section(".data")));
-
-int dram_init(void)
-{
- unsigned int na, ns;
- const void *nvtboot_blob = (void *)nvtboot_boot_x0;
- int node, len, i;
- const u32 *prop;
-
- na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
- ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
-
- node = fdt_path_offset(nvtboot_blob, "/memory");
- if (node < 0) {
- pr_err("Can't find /memory node in nvtboot DTB");
- hang();
- }
- prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
- if (!prop) {
- pr_err("Can't find /memory/reg property in nvtboot DTB");
- hang();
- }
-
- /* Calculate the true # of base/size pairs to read */
- len /= 4; /* Convert bytes to number of cells */
- len /= (na + ns); /* Convert cells to number of banks */
- if (len > CONFIG_NR_DRAM_BANKS)
- len = CONFIG_NR_DRAM_BANKS;
-
- /* Parse the /memory node, and save useful entries */
- gd->ram_size = 0;
- ram_bank_count = 0;
- for (i = 0; i < len; i++) {
- u64 bank_start, bank_end, bank_size, usable_bank_size;
-
- /* Extract raw memory region data from DTB */
- bank_start = fdt_read_number(prop, na);
- prop += na;
- bank_size = fdt_read_number(prop, ns);
- prop += ns;
- gd->ram_size += bank_size;
- bank_end = bank_start + bank_size;
- debug("Bank %d: %llx..%llx (+%llx)\n", i,
- bank_start, bank_end, bank_size);
-
- /*
- * Align the bank to MMU section size. This is not strictly
- * necessary, since the translation table construction code
- * handles page granularity without issue. However, aligning
- * the MMU entries reduces the size and number of levels in the
- * page table, so is worth it.
- */
- bank_start = ROUND(bank_start, SZ_2M);
- bank_end = bank_end & ~(SZ_2M - 1);
- bank_size = bank_end - bank_start;
- debug(" aligned: %llx..%llx (+%llx)\n",
- bank_start, bank_end, bank_size);
- if (bank_end <= bank_start)
- continue;
-
- /* Record data used to create MMU translation tables */
- ram_bank_count++;
- /* Index below is deliberately 1-based to skip MMIO entry */
- tegra_mem_map[ram_bank_count].virt = bank_start;
- tegra_mem_map[ram_bank_count].phys = bank_start;
- tegra_mem_map[ram_bank_count].size = bank_size;
- tegra_mem_map[ram_bank_count].attrs =
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE;
-
- /* Determine best bank to relocate U-Boot into */
- if (bank_end > SZ_4G)
- bank_end = SZ_4G;
- debug(" end %llx (usable)\n", bank_end);
- usable_bank_size = bank_end - bank_start;
- debug(" size %llx (usable)\n", usable_bank_size);
- if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) &&
- (bank_end > ram_top)) {
- ram_top = bank_end;
- region_base = bank_start;
- debug("ram top now %llx\n", ram_top);
- }
- }
-
- /* Ensure memory map contains the desired sentinel entry */
- tegra_mem_map[ram_bank_count + 1].virt = 0;
- tegra_mem_map[ram_bank_count + 1].phys = 0;
- tegra_mem_map[ram_bank_count + 1].size = 0;
- tegra_mem_map[ram_bank_count + 1].attrs = 0;
-
- /* Error out if a relocation target couldn't be found */
- if (!ram_top) {
- pr_err("Can't find a usable RAM top");
- hang();
- }
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- int i;
-
- if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) {
- pr_err("Reservations exceed chosen region size");
- hang();
- }
-
- for (i = 0; i < ram_bank_count; i++) {
- gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
- gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
- }
-
-#ifdef CONFIG_PCI
- gd->pci_ram_top = ram_top;
-#endif
-
- return 0;
-}
-
-ulong board_get_usable_ram_top(ulong total_size)
-{
- return ram_top;
-}
CLOCK_TYPE_PDCT,
CLOCK_TYPE_ACPT,
CLOCK_TYPE_ASPTE,
- CLOCK_TYPE_PMDACD2T,
+ CLOCK_TYPE_PDD2T,
CLOCK_TYPE_PCST,
CLOCK_TYPE_DP,
{ CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
MASK_BITS_31_29},
- { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
- CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
+ { CLK(PERIPH), CLK(NONE), CLK(DISPLAY), CLK(NONE),
+ CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
MASK_BITS_31_29},
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDD2T),
+ TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDD2T),
/* 0x10 */
TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
- { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
# processor family
config MCF520x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF52x2
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF523x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF530x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5301x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF532x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF537x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5441x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5445x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF5227x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
config MCF547x_8x
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
bool
# processor type
# ccflags-y += -DET_DEBUG
extra-y = start.o
-obj-y = cpu.o speed.o cpu_init.o interrupts.o
+obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o
#include <asm/rtc.h>
#include <linux/compiler.h>
+void cfspi_port_conf(void)
+{
+ gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
+}
+
/*
* Breath some life into the CPU...
*
#endif
icache_enable();
+
+ cfspi_port_conf();
}
/*
break;
}
}
-
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
- return -1;
-
- /* Clear FIFO and resume transfer */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
- break;
- }
-
- return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Clear FIFO */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 2:
- clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
- break;
- }
-}
-#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Angelo Dureghello <angleo@sysam.it>
+ *
+ * CPU specific dspi routines
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CF_DSPI
+void dspi_chip_select(int cs)
+{
+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+ setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
+ break;
+ }
+}
+
+void dspi_chip_unselect(int cs)
+{
+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+ break;
+ }
+}
+#endif /* CONFIG_CF_DSPI */
clr.l %sp@-
/* run low-level board init code (from flash) */
- bsr board_init_f
+ move.l #board_init_f, %a1
+ jsr (%a1)
/* board_init_f() does not return */
# ccflags-y += -DET_DEBUG
extra-y = start.o
-obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o
+obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
#endif
}
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+ gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+ out_8(&gpio->par_dspi,
+ GPIO_PAR_DSPI_SIN_SIN |
+ GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *)MMAP_PM;
+
+ out_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+ GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+ out_8(&gpio->srcr_dspiow, 3);
+
+ /* DSPI0 */
+ out_8(&pm->pmcr0, 23);
+#endif
+}
+#endif
+
/*
* Breath some life into the CPU...
*
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+#ifdef CONFIG_CF_SPI
+ cfspi_port_conf();
+#endif
+
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
}
#endif
-#ifdef CONFIG_CF_DSPI
-void cfspi_port_conf(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-#ifdef CONFIG_MCF5445x
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN |
- GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-#endif
-
-#ifdef CONFIG_MCF5441x
- pm_t *pm = (pm_t *) MMAP_PM;
-
- out_8(&gpio->par_dspi0,
- GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
- GPIO_PAR_DSPI0_SCK_DSPI0SCK);
- out_8(&gpio->srcr_dspiow, 3);
-
- /* DSPI0 */
- out_8(&pm->pmcr0, 23);
-#endif
-}
-
-int cfspi_claim_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
- return -1;
-
- /* Clear FIFO and resume transfer */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
-
-#ifdef CONFIG_MCF5441x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
- setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
- setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
- break;
- }
-#endif
-
- return 0;
-}
-
-void cfspi_release_bus(uint bus, uint cs)
-{
- dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Clear FIFO */
- clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
-
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
-
-#ifdef CONFIG_MCF5441x
- if (cs == 1)
- clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
-#endif
-}
-
-#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Angelo Dureghello <angleo@sysam.it>
+ *
+ * CPU specific dspi routines
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CF_DSPI
+void dspi_chip_select(int cs)
+{
+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ break;
+ case 3:
+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+ setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
+ break;
+ case 5:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ break;
+ }
+#endif
+#ifdef CONFIG_MCF5441x
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi0,
+ ~GPIO_PAR_DSPI0_PCS0_MASK);
+ setbits_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspiow,
+ GPIO_PAR_DSPIOW_DSPI0PSC1);
+ setbits_8(&gpio->par_dspiow,
+ GPIO_PAR_DSPIOW_DSPI0PSC1);
+ break;
+ }
+#endif
+}
+
+void dspi_chip_unselect(int cs)
+{
+ struct gpio *gpio = (struct gpio *)MMAP_GPIO;
+
+#ifdef CONFIG_MCF5445x
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
+ break;
+ case 2:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
+ break;
+ case 3:
+ clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
+ break;
+ case 5:
+ clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
+ break;
+ }
+#endif
+#ifdef CONFIG_MCF5441x
+ if (cs == 1)
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
+}
+#endif /* CONFIG_CF_DSPI */
* then (and always) gd struct space will be reserved
*/
move.l %sp, -(%sp)
- bsr board_init_f_alloc_reserve
+ move.l #board_init_f_alloc_reserve, %a1
+ jsr (%a1)
/* update stack and frame-pointers */
move.l %d0, %sp
/* initialize reserved area */
move.l %d0, -(%sp)
- bsr board_init_f_init_reserve
+ move.l #board_init_f_init_reserve, %a1
+ jsr (%a1)
/* run low-level CPU init code (from flash) */
jbsr cpu_init_f
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- . = ALIGN(256);
+ . = ALIGN(4);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
- . = ALIGN(256);
+ . = ALIGN(4);
__init_end = .;
+ _end = .;
+
__bss_start = .;
.bss (NOLOAD) :
{
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5208.dtsi"
+
+/ {
+ model = "Freescale M5208EVBE";
+ compatible = "fsl,M5208EVBE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+ model = "Freescale M52277EVB";
+ compatible = "fsl,M52277EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5227x.dtsi"
+
+/ {
+ model = "Freescale M52277_stmicro";
+ compatible = "fsl,M52277_stmicro";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+ model = "Freescale M5235EVB";
+ compatible = "fsl,M5235EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf523x.dtsi"
+
+/ {
+ model = "Freescale M5235EVB_Flash32";
+ compatible = "fsl,M5235EVB_Flash32";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5249.dtsi"
+
+/ {
+ model = "Freescale M5249EVB";
+ compatible = "fsl,M5249EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5253.dtsi"
+
+/ {
+ model = "Freescale M5253DEMO";
+ compatible = "fsl,M5253DEMO";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+ model = "Freescale M5272C3";
+ compatible = "fsl,M5272C3";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5275.dtsi"
+
+/ {
+ model = "Freescale M5275EVB";
+ compatible = "fsl,M5275EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+ model = "Freescale M5282EVB";
+ compatible = "fsl,M5282EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5301x.dtsi"
+
+/ {
+ model = "Freescale M53017EVB";
+ compatible = "fsl,M53017EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+ model = "Freescale M5329AFEE";
+ compatible = "fsl,M5329AFEE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5329.dtsi"
+
+/ {
+ model = "Freescale M5329BFEE";
+ compatible = "fsl,M5329BFEE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+ model = "Freescale M5373EVB";
+ compatible = "fsl,M5373EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR";
+ compatible = "fsl,M54418TWR";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_nand_mii";
+ compatible = "fsl,M54418TWR_nand_mii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_nand_rmii";
+ compatible = "fsl,M54418TWR_nand_rmii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_nand_rmii_lowfreq";
+ compatible = "fsl,M54418TWR_nand_rmii_lowfreq";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_serial_mii";
+ compatible = "fsl,M54418TWR_serial_mii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Freescale M54418TWR_serial_rmii";
+ compatible = "fsl,M54418TWR_serial_rmii";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54451EVB";
+ compatible = "fsl,M54451EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54451EVB_stmicro";
+ compatible = "fsl,M54451EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB";
+ compatible = "fsl,M54455EVB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_a66";
+ compatible = "fsl,M54455EVB_a66";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_i66";
+ compatible = "fsl,M54455EVB_i66";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_intel";
+ compatible = "fsl,M5275EVB_intel";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5445x.dtsi"
+
+/ {
+ model = "Freescale M54455EVB_stm33";
+ compatible = "fsl,M5275EVB_stm33";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475AFE";
+ compatible = "fsl,M5475AFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475BFE";
+ compatible = "fsl,M5475BFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475CFE";
+ compatible = "fsl,M5475CFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475DFE";
+ compatible = "fsl,M5475DFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475EFE";
+ compatible = "fsl,M5475EFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475FFE";
+ compatible = "fsl,M5475FFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5475GFE";
+ compatible = "fsl,M5475GFE";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485AFE";
+ compatible = "fsl,M5485AFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485BFE";
+ compatible = "fsl,M5485BFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485CFE";
+ compatible = "fsl,M5485CFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485DFE";
+ compatible = "fsl,M5485DFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485EFE";
+ compatible = "fsl,M5485EFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485FFE";
+ compatible = "fsl,M5485FFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485GFE";
+ compatible = "fsl,M5485GFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf54xx.dtsi"
+
+/ {
+ model = "Freescale M5485HFE";
+ compatible = "fsl,M5485HFE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \
+ M52277EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \
+ M5235EVB_Flash32.dtb
+dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb
+dtb-$(CONFIG_TARGET_EB_CPU5282) += eb_cpu5282.dtb \
+ eb_cpu5282_internal.dtb
+dtb-$(CONFIG_TARGET_M5208EVBE) += M5208EVBE.dtb
+dtb-$(CONFIG_TARGET_M5249EVB) += M5249EVB.dtb
+dtb-$(CONFIG_TARGET_M5253DEMO) += M5253DEMO.dtb
+dtb-$(CONFIG_TARGET_M5272C3) += M5272C3.dtb
+dtb-$(CONFIG_TARGET_M5275EVB) += M5275EVB.dtb
+dtb-$(CONFIG_TARGET_M5282EVB) += M5282EVB.dtb
+dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb
+dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb
+dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb
+dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb
+dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \
+ M54418TWR_nand_mii.dtb \
+ M54418TWR_nand_rmii.dtb \
+ M54418TWR_serial_mii.dtb \
+ M54418TWR_serial_rmii.dtb \
+ M54418TWR_nand_rmii_lowfreq.dtb
+dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \
+ M54451EVB_stmicro.dtb
+dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
+ M54455EVB_intel.dtb \
+ M54455EVB_stm33.dtb \
+ M54455EVB_a66.dtb \
+ M54455EVB_i66.dtb
+dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
+dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
+dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
+ M5475BFE.dtb \
+ M5475CFE.dtb \
+ M5475DFE.dtb \
+ M5475EFE.dtb \
+ M5475FFE.dtb \
+ M5475GFE.dtb
+dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \
+ M5485BFE.dtb \
+ M5485CFE.dtb \
+ M5485DFE.dtb \
+ M5485EFE.dtb \
+ M5485FFE.dtb \
+ M5485GFE.dtb \
+ M5485HFE.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5307.dtsi"
+
+/ {
+ model = "Sysam AMCORE";
+ compatible = "sysam,AMCORE";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf537x.dtsi"
+
+/ {
+ model = "Astro mcf5373l";
+ compatible = "astro,mcf5373l";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5272.dtsi"
+
+/ {
+ model = "Cobra 5272";
+ compatible = "cobra,M5272";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+ model = "BuS eb_cpuM5282";
+ compatible = "bus,eb_cpuM5282";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5282.dtsi"
+
+/ {
+ model = "BuS eb_cpu5282_internals";
+ compatible = "bus,eb_cpu5282_internals";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5208";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5227x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf523x";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5249";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart@1c0 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x1c0 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5253";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart@1c0 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x1c0 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart3: uart@c00 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xc00 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5271";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5272";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart@100 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x100 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@140 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x140 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5275";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5282";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ipsbar: ipsbar@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
+
+ uart0: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@240 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x240 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@280 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x280 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5301x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5307";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MBAR */
+ mbar: mbar@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x10000000 0x10000>;
+ reg = <0x10000000 0x10000>;
+
+ uart0: uart@1c0 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x1c0 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@200 {
+ compatible = "fsl,mcf-uart";
+ reg = <0x200 0x40>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5329";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5329";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5441x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ uart3: uart@fc06c000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc06c000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+
+ dspi1: dspi@fc03c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc03c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+
+ dspi2: dspi@ec038000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xec038000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+
+ dspi3: dspi@ec03c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xec03c00 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf5445x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+
+ uart1: uart@fc064000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc064000 0x40>;
+ status = "disabled";
+ };
+
+ uart2: uart@fc068000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc068000 0x40>;
+ status = "disabled";
+ };
+
+ dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/ {
+ compatible = "fsl,mcf54x5";
+
+ aliases {
+ /* TO DO, clarify on serial, this SoC seems to have SPC and
+ * no UARTS.
+ */
+ spi0 = &dspi0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mbar: mbar@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x80000000 0x10000>;
+ reg = <0x80000000 0x10000>;
+
+ dspi0: dspi@8a00 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x8a00 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+/dts-v1/;
+/include/ "mcf5441x.dtsi"
+
+/ {
+ model = "Sysam stmark2";
+ compatible = "sysam,stmark2";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&dspi0 {
+ spi-mode = <3>;
+ status = "okay";
+
+ flash: is25lp128@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <60000000>;
+ reg = <1>;
+ };
+};
/* Bit definitions and macros for DRFDR group */
#define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF))
+/* Architecture-related operations */
+void dspi_chip_select(int cs);
+void dspi_chip_unselect(int cs);
+
#endif /* __DSPI_H__ */
}
#if defined(CONFIG_SPL_MAX_FOOTPRINT)
-ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
+ASSERT(__end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \
"SPL image plus BSS too big");
#endif
select SYSRESET
imply CMD_DM
-config ARCH_MT7620
- bool "Support MT7620/7688 SoCs"
+config ARCH_MTMIPS
+ bool "Support MediaTek MIPS platforms"
imply CMD_DM
select DISPLAY_CPUINFO
select DM
select DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
- select ARCH_MISC_INIT
select MIPS_TUNE_24KC
select OF_CONTROL
select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_LITTLE_ENDIAN
+ select SYS_MALLOC_CLEAR_ON_INIT
select SYSRESET
config ARCH_JZ47XX
source "arch/mips/mach-bmips/Kconfig"
source "arch/mips/mach-jz47xx/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
-source "arch/mips/mach-mt7620/Kconfig"
+source "arch/mips/mach-mtmips/Kconfig"
if MIPS
machine-$(CONFIG_ARCH_BMIPS) += bmips
machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
machine-$(CONFIG_MACH_PIC32) += pic32
-machine-$(CONFIG_ARCH_MT7620) += mt7620
+machine-$(CONFIG_ARCH_MTMIPS) += mtmips
machine-$(CONFIG_ARCH_MSCC) += mscc
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_ARCH_MT7620) += \
+dtb-$(CONFIG_ARCH_MTMIPS) += \
gardena-smart-gateway-mt7688.dtb \
linkit-smart-7688.dtb
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
/dts-v1/;
#include "mscc,luton.dtsi"
+#include <dt-bindings/mscc/luton_data.h>
/ {
model = "Luton26 PCB090 Reference Board";
&mdio0 {
status = "okay";
-};
-
-&port0 {
- phy-handle = <&phy0>;
-};
-
-&port1 {
- phy-handle = <&phy1>;
-};
-
-&port2 {
- phy-handle = <&phy2>;
-};
-
-&port3 {
- phy-handle = <&phy3>;
-};
-
-&port4 {
- phy-handle = <&phy4>;
-};
-
-&port5 {
- phy-handle = <&phy5>;
-};
-
-&port6 {
- phy-handle = <&phy6>;
-};
-
-&port7 {
- phy-handle = <&phy7>;
-};
-&port8 {
- phy-handle = <&phy8>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
};
-&port9 {
- phy-handle = <&phy9>;
-};
+&mdio1 {
+ status = "okay";
-&port10 {
- phy-handle = <&phy10>;
+ phy12: ethernet-phy@12 {
+ reg = <0>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <1>;
+ };
+ phy14: ethernet-phy@14 {
+ reg = <2>;
+ };
+ phy15: ethernet-phy@15 {
+ reg = <3>;
+ };
+ phy16: ethernet-phy@16 {
+ reg = <4>;
+ };
+ phy17: ethernet-phy@17 {
+ reg = <5>;
+ };
+ phy18: ethernet-phy@18 {
+ reg = <6>;
+ };
+ phy19: ethernet-phy@19 {
+ reg = <7>;
+ };
+ phy20: ethernet-phy@20 {
+ reg = <8>;
+ };
+ phy21: ethernet-phy@21 {
+ reg = <9>;
+ };
+ phy22: ethernet-phy@22 {
+ reg = <10>;
+ };
+ phy23: ethernet-phy@23 {
+ reg = <11>;
+ };
};
-&port11 {
- phy-handle = <&phy11>;
+&switch {
+ ethernet-ports {
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <&phy0>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <&phy1>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ phy-handle = <&phy2>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ phy-handle = <&phy3>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ phy-handle = <&phy4>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ phy-handle = <&phy5>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ phy-handle = <&phy6>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ phy-handle = <&phy7>;
+ };
+ port8: port@8 {
+ reg = <8>;
+ phy-handle = <&phy8>;
+ };
+ port9: port@9 {
+ reg = <9>;
+ phy-handle = <&phy9>;
+ };
+ port10: port@10 {
+ reg = <10>;
+ phy-handle = <&phy10>;
+ };
+ port11: port@11 {
+ reg = <11>;
+ phy-handle = <&phy11>;
+ };
+ port12: port@12 {
+ reg = <12>;
+ phy-handle = <&phy12>;
+ phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>;
+ };
+ port13: port@13 {
+ reg = <13>;
+ phy-handle = <&phy13>;
+ phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
+ };
+ port14: port@14 {
+ reg = <14>;
+ phy-handle = <&phy14>;
+ phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
+ };
+ port15: port@15 {
+ reg = <15>;
+ phy-handle = <&phy15>;
+ phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
+ };
+ port16: port@16 {
+ reg = <16>;
+ phy-handle = <&phy16>;
+ phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>;
+ };
+ port17: port@17 {
+ reg = <17>;
+ phy-handle = <&phy17>;
+ phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
+ };
+ port18: port@18 {
+ reg = <18>;
+ phy-handle = <&phy18>;
+ phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
+ };
+ port19: port@19 {
+ reg = <19>;
+ phy-handle = <&phy19>;
+ phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
+ };
+ port20: port@20 {
+ reg = <20>;
+ phy-handle = <&phy20>;
+ phys = <&serdes_hsio 20 SERDES6G(3) PHY_MODE_QSGMII>;
+ };
+ port21: port@21 {
+ reg = <21>;
+ phy-handle = <&phy21>;
+ phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
+ };
+ port22: port@22 {
+ reg = <22>;
+ phy-handle = <&phy22>;
+ phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
+ };
+ port23: port@23 {
+ reg = <23>;
+ phy-handle = <&phy23>;
+ phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
+ };
+ };
};
&mdio0 {
status = "okay";
-};
-
-&port0 {
- phy-handle = <&phy0>;
-};
-
-&port1 {
- phy-handle = <&phy1>;
-};
-
-&port2 {
- phy-handle = <&phy2>;
-};
-
-&port3 {
- phy-handle = <&phy3>;
-};
-&port4 {
- phy-handle = <&phy4>;
-};
-
-&port5 {
- phy-handle = <&phy5>;
-};
-
-&port6 {
- phy-handle = <&phy6>;
-};
-
-&port7 {
- phy-handle = <&phy7>;
-};
-
-&port8 {
- phy-handle = <&phy8>;
-};
-
-&port9 {
- phy-handle = <&phy9>;
-};
-
-&port10 {
- phy-handle = <&phy10>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
};
-&port11 {
- phy-handle = <&phy11>;
+&switch {
+ ethernet-ports {
+ port0: port@0 {
+ reg = <0>;
+ phy-handle = <&phy0>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ phy-handle = <&phy1>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ phy-handle = <&phy2>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ phy-handle = <&phy3>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ phy-handle = <&phy4>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ phy-handle = <&phy5>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ phy-handle = <&phy6>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ phy-handle = <&phy7>;
+ };
+ port8: port@8 {
+ reg = <8>;
+ phy-handle = <&phy8>;
+ };
+ port9: port@9 {
+ reg = <9>;
+ phy-handle = <&phy9>;
+ };
+ port10: port@10 {
+ reg = <10>;
+ phy-handle = <&phy10>;
+ };
+ port11: port@11 {
+ reg = <11>;
+ phy-handle = <&phy11>;
+ };
+ };
};
<0x030000 0x1000>, // VTSS_TO_REW
<0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
<0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
- <0x0a0000 0x0100>; // VTSS_TO_HSIO
+ <0x0a0000 0x10000>; // VTSS_TO_HSIO
reg-names = "port0", "port1", "port2", "port3",
"port4", "port5", "port6", "port7",
"port8", "port9", "port10", "port11",
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
-
- port0: port@0 {
- reg = <0>;
- };
- port1: port@1 {
- reg = <1>;
- };
- port2: port@2 {
- reg = <2>;
- };
- port3: port@3 {
- reg = <3>;
- };
- port4: port@4 {
- reg = <4>;
- };
- port5: port@5 {
- reg = <5>;
- };
- port6: port@6 {
- reg = <6>;
- };
- port7: port@7 {
- reg = <7>;
- };
- port8: port@8 {
- reg = <8>;
- };
- port9: port@9 {
- reg = <9>;
- };
- port10: port@10 {
- reg = <10>;
- };
- port11: port@11 {
- reg = <11>;
- };
- port12: port@12 {
- reg = <12>;
- };
- port13: port@13 {
- reg = <13>;
- };
- port14: port@14 {
- reg = <14>;
- };
- port15: port@15 {
- reg = <15>;
- };
- port16: port@16 {
- reg = <16>;
- };
- port17: port@17 {
- reg = <17>;
- };
- port18: port@18 {
- reg = <18>;
- };
- port19: port@19 {
- reg = <19>;
- };
- port20: port@20 {
- reg = <20>;
- };
- port21: port@21 {
- reg = <21>;
- };
- port22: port@22 {
- reg = <22>;
- };
- port23: port@23 {
- reg = <23>;
- };
};
};
compatible = "mscc,luton-miim";
reg = <0x700a0 0x24>;
status = "disabled";
+ };
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- phy2: ethernet-phy@2 {
- reg = <2>;
- };
- phy3: ethernet-phy@3 {
- reg = <3>;
- };
- phy4: ethernet-phy@4 {
- reg = <4>;
- };
- phy5: ethernet-phy@5 {
- reg = <5>;
- };
- phy6: ethernet-phy@6 {
- reg = <6>;
- };
- phy7: ethernet-phy@7 {
- reg = <7>;
- };
- phy8: ethernet-phy@8 {
- reg = <8>;
- };
- phy9: ethernet-phy@9 {
- reg = <9>;
- };
- phy10: ethernet-phy@10 {
- reg = <10>;
- };
- phy11: ethernet-phy@11 {
- reg = <11>;
+ mdio1: mdio@700c4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,luton-miim";
+ reg = <0x700c4 0x24>;
+ status = "disabled";
+ };
+
+ hsio: syscon@10d0000 {
+ compatible = "mscc,luton-hsio", "syscon", "simple-mfd";
+ reg = <0xa0000 0x10000>;
+
+ serdes_hsio: serdes_hsio {
+ compatible = "mscc,vsc7527-serdes";
+ #phy-cells = <3>;
};
};
};
status = "disabled";
};
- switch@1010000 {
+ switch: switch@1010000 {
pinctrl-0 = <&miim1_pins>;
pinctrl-names = "default";
compatible = "mscc,vsc7514-switch";
- reg = <0x1010000 0x10000>, /* VTSS_TO_SYS */
- <0x1030000 0x10000>, /* VTSS_TO_REW */
- <0x1080000 0x100>, /* VTSS_TO_DEVCPU_QS */
- <0x10d0000 0x10000>, /* VTSS_TO_HSIO */
- <0x11e0000 0x100>, /* VTSS_TO_DEV_0 */
- <0x11f0000 0x100>, /* VTSS_TO_DEV_1 */
- <0x1200000 0x100>, /* VTSS_TO_DEV_2 */
- <0x1210000 0x100>, /* VTSS_TO_DEV_3 */
- <0x1220000 0x100>, /* VTSS_TO_DEV_4 */
- <0x1230000 0x100>, /* VTSS_TO_DEV_5 */
- <0x1240000 0x100>, /* VTSS_TO_DEV_6 */
- <0x1250000 0x100>, /* VTSS_TO_DEV_7 */
- <0x1260000 0x100>, /* VTSS_TO_DEV_8 */
- <0x1270000 0x100>, /* NA */
- <0x1280000 0x100>, /* NA */
- <0x1800000 0x80000>, /* VTSS_TO_QSYS */
- <0x1880000 0x10000>; /* VTSS_TO_ANA */
- reg-names = "sys", "rew", "qs", "hsio", "port0",
- "port1", "port2", "port3", "port4", "port5",
- "port6", "port7", "port8", "port9",
- "port10", "qsys", "ana";
+
+ reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0
+ <0x11f0000 0x100>, // VTSS_TO_DEV_1
+ <0x1200000 0x100>, // VTSS_TO_DEV_2
+ <0x1210000 0x100>, // VTSS_TO_DEV_3
+ <0x1220000 0x100>, // VTSS_TO_DEV_4
+ <0x1230000 0x100>, // VTSS_TO_DEV_5
+ <0x1240000 0x100>, // VTSS_TO_DEV_6
+ <0x1250000 0x100>, // VTSS_TO_DEV_7
+ <0x1260000 0x100>, // VTSS_TO_DEV_8
+ <0x1270000 0x100>, // VTSS_TO_DEV_9
+ <0x1280000 0x100>, // VTSS_TO_DEV_10
+ <0x1010000 0x10000>, // VTSS_TO_SYS
+ <0x1030000 0x10000>, // VTSS_TO_REW
+ <0x1080000 0x100>, // VTSS_TO_DEVCPU_QS
+ <0x10d0000 0x10000>, // VTSS_TO_HSIO
+ <0x1800000 0x80000>,// VTSS_TO_QSYS
+ <0x1880000 0x10000>;// VTSS_TO_ANA
+ reg-names = "port0", "port1", "port2", "port3", "port4",
+ "port5", "port6", "port7", "port8", "port9",
+ "port10",
+ "sys", "rew", "qs", "hsio", "qsys", "ana";
interrupts = <21 22>;
interrupt-names = "xtr", "inj";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
-
- port0: port@0 {
- reg = <0>;
- };
- port1: port@1 {
- reg = <1>;
- };
- port2: port@2 {
- reg = <2>;
- };
- port3: port@3 {
- reg = <3>;
- };
- port4: port@4 {
- reg = <4>;
- };
- port5: port@5 {
- reg = <5>;
- };
- port6: port@6 {
- reg = <6>;
- };
- port7: port@7 {
- reg = <7>;
- };
- port8: port@8 {
- reg = <8>;
- };
- port9: port@9 {
- reg = <9>;
- };
- port10: port@10 {
- reg = <10>;
- };
};
};
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
- reg = <0x107009c 0x24>, <0x10700f0 0x8>;
+ reg = <0x107009c 0x24>;
interrupts = <14>;
status = "disabled";
+ };
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- phy2: ethernet-phy@2 {
- reg = <2>;
- };
- phy3: ethernet-phy@3 {
- reg = <3>;
+ mdio1: mdio@10700f0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,ocelot-miim";
+ reg = <0x10700c0 0x24>;
+ interrupts = <14>;
+ status = "disabled";
+ };
+
+ hsio: syscon@10d0000 {
+ compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
+ reg = <0x10d0000 0x10000>;
+
+ serdes_hsio: serdes_hsio {
+ compatible = "mscc,vsc7514-serdes";
+ #phy-cells = <3>;
};
};
#gpio-cells = <2>;
gpio-ranges = <&sgpio 0 0 64>;
};
+
+ switch: switch@011e0000 {
+ compatible = "mscc,vsc7418-switch";
+ reg = <0x011e0000 0x0100>, // VTSS_TO_DEV0
+ <0x011f0000 0x0100>, // VTSS_TO_DEV1
+ <0x01200000 0x0100>, // VTSS_TO_DEV2
+ <0x01210000 0x0100>, // VTSS_TO_DEV3
+ <0x01220000 0x0100>, // VTSS_TO_DEV4
+ <0x01230000 0x0100>, // VTSS_TO_DEV5
+ <0x01240000 0x0100>, // VTSS_TO_DEV6
+ <0x01250000 0x0100>, // VTSS_TO_DEV7
+ <0x01260000 0x0100>, // VTSS_TO_DEV8
+ <0x01270000 0x0100>, // VTSS_TO_DEV9
+ <0x01280000 0x0100>, // VTSS_TO_DEV10
+ <0x01900000 0x100000>, // ANA
+ <0x01080000 0x20000>, // QS
+ <0x01800000 0x100000>, // QSYS
+ <0x01030000 0x10000>, // REW
+ <0x01010000 0x20000>, // SYS
+ <0x010a0000 0x10000>; // HSIO
+ reg-names = "port0", "port1", "port2", "port3",
+ "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10",
+ "ana", "qs", "qsys", "rew", "sys",
+ "hsio";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio0: mdio@0107005c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,serval-miim";
+ reg = <0x0107005c 0x24>;
+ status = "disabled";
+ };
+
+ mdio1: mdio@01070080 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,serval-miim";
+ reg = <0x01070080 0x24>;
+ status = "disabled";
+ };
+
+ hsio: syscon@10d0000 {
+ compatible = "mscc,serval-hsio", "syscon", "simple-mfd";
+ reg = <0x10a0000 0x10000>;
+
+ serdes_hsio: serdes_hsio {
+ compatible = "mscc,vsc7418-serdes";
+ #phy-cells = <3>;
+ };
+ };
};
};
/dts-v1/;
#include "mscc,ocelot_pcb.dtsi"
+#include <dt-bindings/mscc/ocelot_data.h>
/ {
model = "Ocelot PCB120 Reference Board";
mscc,sgpio-ports = <0x000FFFFF>;
};
+&mdio0 {
+ status = "okay";
+
+ phy4: ethernet-phy@4 {
+ reg = <3>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <2>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <1>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <0>;
+ };
+};
+
+&mdio1 {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <3>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <2>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <1>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <0>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+ port0: port@0 {
+ reg = <5>;
+ phy-handle = <&phy0>;
+ phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>;
+ };
+ port1: port@1 {
+ reg = <9>;
+ phy-handle = <&phy1>;
+ phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>;
+ };
+ port2: port@2 {
+ reg = <6>;
+ phy-handle = <&phy2>;
+ phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>;
+ };
+ port3: port@3 {
+ reg = <4>;
+ phy-handle = <&phy3>;
+ phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
+ };
+ port4: port@4 {
+ reg = <3>;
+ phy-handle = <&phy4>;
+ };
+ port5: port@5 {
+ reg = <2>;
+ phy-handle = <&phy5>;
+ };
+ port6: port@6 {
+ reg = <1>;
+ phy-handle = <&phy6>;
+ };
+ port7: port@7 {
+ reg = <0>;
+ phy-handle = <&phy7>;
+ };
+ };
+};
&mdio0 {
status = "okay";
-};
-
-&port0 {
- phy-handle = <&phy0>;
-};
-&port1 {
- phy-handle = <&phy1>;
-};
-
-&port2 {
- phy-handle = <&phy2>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
};
-&port3 {
- phy-handle = <&phy3>;
+&switch {
+ ethernet-ports {
+ port0: port@0 {
+ reg = <2>;
+ phy-handle = <&phy2>;
+ };
+ port1: port@1 {
+ reg = <3>;
+ phy-handle = <&phy3>;
+ };
+ port2: port@2 {
+ reg = <0>;
+ phy-handle = <&phy0>;
+ };
+ port3: port@3 {
+ reg = <1>;
+ phy-handle = <&phy1>;
+ };
+ };
};
/dts-v1/;
#include "mscc,serval.dtsi"
+#include <dt-bindings/mscc/serval_data.h>
/ {
model = "Serval PCB105 Reference Board";
status = "okay";
sgpio-ports = <0x00FFFFFF>;
};
+
+&mdio1 {
+ status = "okay";
+
+ phy16: ethernet-phy@16 {
+ reg = <16>;
+ };
+ phy17: ethernet-phy@17 {
+ reg = <17>;
+ };
+ phy18: ethernet-phy@18 {
+ reg = <18>;
+ };
+ phy19: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+
+ port0: port@0 {
+ reg = <7>;
+ phy-handle = <&phy16>;
+ phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
+ };
+ port1: port@1 {
+ reg = <6>;
+ phy-handle = <&phy17>;
+ phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
+ };
+ port2: port@2 {
+ reg = <5>;
+ phy-handle = <&phy18>;
+ phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
+ };
+ port3: port@3 {
+ reg = <4>;
+ phy-handle = <&phy19>;
+ phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
+ };
+ };
+};
/dts-v1/;
#include "mscc,serval.dtsi"
+#include <dt-bindings/mscc/serval_data.h>
/ {
model = "Serval PCB106 Reference Board";
status = "okay";
sgpio-ports = <0x00FFFFFF>;
};
+
+&mdio1 {
+ status = "okay";
+
+ phy16: ethernet-phy@16 {
+ reg = <16>;
+ };
+ phy17: ethernet-phy@17 {
+ reg = <17>;
+ };
+ phy18: ethernet-phy@18 {
+ reg = <18>;
+ };
+ phy19: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+
+ port0: port@0 {
+ reg = <7>;
+ phy-handle = <&phy16>;
+ phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
+ };
+ port1: port@1 {
+ reg = <6>;
+ phy-handle = <&phy17>;
+ phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
+ };
+ port2: port@2 {
+ reg = <5>;
+ phy-handle = <&phy18>;
+ phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
+ };
+ port3: port@3 {
+ reg = <4>;
+ phy-handle = <&phy19>;
+ phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
+ };
+ };
+};
static int boot_setup_fdt(bootm_headers_t *images)
{
+ images->initrd_start = virt_to_phys((void *)images->initrd_start);
+ images->initrd_end = virt_to_phys((void *)images->initrd_end);
return image_setup_libfdt(images, images->ft_addr, images->ft_len,
&images->lmb);
}
config SOC_LUTON
bool "Luton SOC Family"
select SOC_VCOREIII
- select MSCC_BITBANG_SPI_GPIO
help
This supports MSCC Luton family of SOCs.
;
}
-#if defined(CONFIG_SOC_OCELOT)
-static inline void hal_vcoreiii_ddr_reset_assert(void)
-{
- /* DDR has reset pin on GPIO 19 toggle Low-High to release */
- setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
- writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
- sleep_100ns(10000);
-}
-
-static inline void hal_vcoreiii_ddr_reset_release(void)
-{
- /* DDR has reset pin on GPIO 19 toggle Low-High to release */
- setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
- writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
- sleep_100ns(10000);
-}
-
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
/*
* DDR memory sanity checking failed, tally and do hard reset
*
{
register u32 reset;
+#if defined(CONFIG_SOC_OCELOT)
writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6));
clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+#endif
/* We have to execute the reset function from cache. Indeed,
* the reboot workaround in _machine_restart() will change the
panic("DDR init failed\n");
}
+#else /* JR2 || ServalT */
+static inline void hal_vcoreiii_ddr_failed(void)
+{
+ writel(0, BASE_CFG + ICPU_RESET);
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
+
+ panic("DDR init failed\n");
+}
+#endif
+
+#if defined(CONFIG_SOC_OCELOT)
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+ /* DDR has reset pin on GPIO 19 toggle Low-High to release */
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
+ sleep_100ns(10000);
+}
+
+static inline void hal_vcoreiii_ddr_reset_release(void)
+{
+ /* DDR has reset pin on GPIO 19 toggle Low-High to release */
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+ sleep_100ns(10000);
+}
+
#else /* JR2 || ServalT || Serval */
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
writel(readl(BASE_CFG + ICPU_RESET) |
ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET);
}
-
-static inline void hal_vcoreiii_ddr_failed(void)
-{
- writel(0, BASE_CFG + ICPU_RESET);
- writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
-
- panic("DDR init failed\n");
-}
#endif /* JR2 || ServalT || Serval */
/*
#define GPIO_ALT(x) (0x54 + 4 * (x))
+#define PERF_PHY_CFG 0xf0
#endif
/* Do global reset */
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
- for (i = 0; i < 1000; i++)
+ for (i = 0; i < 2000; i++)
;
/* Power down DDR for clean DDR re-training */
+++ /dev/null
-menu "MediaTek MIPS platforms"
- depends on ARCH_MT7620
-
-config SYS_MALLOC_F_LEN
- default 0x1000
-
-config SYS_SOC
- default "mt7620" if SOC_MT7620
-
-choice
- prompt "MediaTek MIPS SoC select"
-
-config SOC_MT7620
- bool "MT7620/8"
- select MIPS_L1_CACHE_SHIFT_5
- help
- This supports MediaTek MIPS MT7620 family.
-
-endchoice
-
-choice
- prompt "Board select"
-
-config BOARD_GARDENA_SMART_GATEWAY_MT7688
- bool "GARDENA smart Gateway"
- depends on SOC_MT7620
- select BOARD_LATE_INIT
- select SUPPORTS_BOOT_RAM
- help
- GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
- and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.
-
-config BOARD_LINKIT_SMART_7688
- bool "LinkIt Smart 7688"
- depends on SOC_MT7620
- select SUPPORTS_BOOT_RAM
- help
- Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM
- and 32 MiB of flash (SPI).
- Between its different peripherals there's an integrated switch with 4
- ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
- a MT7688 (PCIe).
-
-endchoice
-
-choice
- prompt "Boot mode"
-
-config BOOT_RAM
- bool "RAM boot"
- depends on SUPPORTS_BOOT_RAM
- help
- This builds an image that is linked to a RAM address. It can be used
- for booting from CFE via TFTP using an ELF image, but it can also be
- booted from RAM by other bootloaders using a BIN image.
-
-config BOOT_ROM
- bool "ROM boot"
- depends on SUPPORTS_BOOT_RAM
- help
- This builds an image that is linked to a ROM address. It can be
- used as main bootloader image which is programmed onto the onboard
- flash storage (SPI NOR).
-
-endchoice
-
-choice
- prompt "DDR2 size"
-
-config ONBOARD_DDR2_SIZE_256MBIT
- bool "256MBit (32MByte) total size"
- depends on BOOT_ROM
- help
- Use 256MBit (32MByte) of DDR total size
-
-config ONBOARD_DDR2_SIZE_512MBIT
- bool "512MBit (64MByte) total size"
- depends on BOOT_ROM
- help
- Use 512MBit (64MByte) of DDR total size
-
-config ONBOARD_DDR2_SIZE_1024MBIT
- bool "1024MBit (128MByte) total size"
- depends on BOOT_ROM
- help
- Use 1024MBit (128MByte) of DDR total size
-
-config ONBOARD_DDR2_SIZE_2048MBIT
- bool "2048MBit (256MByte) total size"
- depends on BOOT_ROM
- help
- Use 2048MBit (256MByte) of DDR total size
-
-endchoice
-
-choice
- prompt "DDR2 chip width"
-
-config ONBOARD_DDR2_CHIP_WIDTH_8BIT
- bool "8bit DDR chip width"
- depends on BOOT_ROM
- help
- Use DDR chips with 8bit width
-
-config ONBOARD_DDR2_CHIP_WIDTH_16BIT
- bool "16bit DDR chip width"
- depends on BOOT_ROM
- help
- Use DDR chips with 16bit width
-
-endchoice
-
-choice
- prompt "DDR2 bus width"
-
-config ONBOARD_DDR2_BUS_WIDTH_16BIT
- bool "16bit DDR bus width"
- depends on BOOT_ROM
- help
- Use 16bit DDR bus width
-
-config ONBOARD_DDR2_BUS_WIDTH_32BIT
- bool "32bit DDR bus width"
- depends on BOOT_ROM
- help
- Use 32bit DDR bus width
-
-endchoice
-
-config SUPPORTS_BOOT_RAM
- bool
-
-source "board/gardena/smart-gateway-mt7688/Kconfig"
-source "board/seeed/linkit-smart-7688/Kconfig"
-
-endmenu
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += cpu.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += ddr_calibrate.o
-obj-y += lowlevel_init.o
-endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ram.h>
-#include <wdt.h>
-#include <asm/io.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include "mt76xx.h"
-
-#define STR_LEN 6
-
-#ifdef CONFIG_BOOT_ROM
-int mach_cpu_init(void)
-{
- ddr_calibrate();
-
- return 0;
-}
-#endif
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
-
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)",
- "PLL (4-Byte SPI Addr)",
- "XTAL (3-Byte SPI Addr)",
- "XTAL (4-Byte SPI Addr)" };
- const void *blob = gd->fdt_blob;
- void __iomem *sysc_base;
- char buf[STR_LEN + 1];
- fdt_addr_t base;
- fdt_size_t size;
- char *str;
- int node;
- u32 val;
-
- /* Get system controller base address */
- node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc");
- if (node < 0)
- return -FDT_ERR_NOTFOUND;
-
- base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg",
- 0, &size, true);
- if (base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- sysc_base = ioremap_nocache(base, size);
-
- str = (char *)sysc_base + MT76XX_CHIPID_OFFS;
- snprintf(buf, STR_LEN + 1, "%s", str);
- val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS);
- printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf,
- (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0));
-
- val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1;
- printf("Boot from %s\n", boot_str[val]);
-
- return 0;
-}
-
-int arch_misc_init(void)
-{
- /*
- * It has been noticed, that sometimes the d-cache is not in a
- * "clean-state" when U-Boot is running on MT7688. This was
- * detected when using the ethernet driver (which uses d-cache)
- * and a TFTP command does not complete. Flushing the complete
- * d-cache (again?) here seems to fix this issue.
- */
- flush_dcache_range(gd->bd->bi_memstart,
- gd->bd->bi_memstart + gd->ram_size - 1);
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Stefan Roese <sr@denx.de>
- *
- * This code is mostly based on the code extracted from this MediaTek
- * github repository:
- *
- * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
- *
- * I was not able to find a specific license or other developers
- * copyrights here, so I can't add them here.
- *
- * Most functions in this file are copied from the MediaTek U-Boot
- * repository. Without any documentation, it was impossible to really
- * implement this differently. So its mostly a cleaned-up version of
- * the original code, with only support for the MT7628 / MT7688 SoC.
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <asm/cacheops.h>
-#include <asm/io.h>
-#include "mt76xx.h"
-
-#define NUM_OF_CACHELINE 128
-#define MIN_START 6
-#define MIN_FINE_START 0xf
-#define MAX_START 7
-#define MAX_FINE_START 0x0
-
-#define CPU_FRAC_DIV 1
-
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
-#define DRAM_BUTTOM 0x02000000
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
-#define DRAM_BUTTOM 0x04000000
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
-#define DRAM_BUTTOM 0x08000000
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
-#define DRAM_BUTTOM 0x10000000
-#endif
-
-static inline void cal_memcpy(void *src, void *dst, u32 size)
-{
- u8 *psrc = (u8 *)src;
- u8 *pdst = (u8 *)dst;
- int i;
-
- for (i = 0; i < size; i++, psrc++, pdst++)
- *pdst = *psrc;
-}
-
-static inline void cal_memset(void *src, u8 pat, u32 size)
-{
- u8 *psrc = (u8 *)src;
- int i;
-
- for (i = 0; i < size; i++, psrc++)
- *psrc = pat;
-}
-
-#define pref_op(hint, addr) \
- __asm__ __volatile__( \
- ".set push\n" \
- ".set noreorder\n" \
- "pref %0, %1\n" \
- ".set pop\n" \
- : \
- : "i" (hint), "R" (*(u8 *)(addr)))
-
-static inline void cal_patgen(u32 start_addr, u32 size, u32 bias)
-{
- u32 *addr = (u32 *)start_addr;
- int i;
-
- for (i = 0; i < size; i++)
- addr[i] = start_addr + i + bias;
-}
-
-static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs,
- u32 offs, u32 pat, u32 val)
-{
- u32 nc_addr;
- u32 *c_addr;
- int i;
-
- for (nc_addr = 0xa0000000;
- nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32);
- nc_addr += (DRAM_BUTTOM >> 6) + offs) {
- writel(0x00007474, (void *)MT76XX_MEMCTRL_BASE + 0x64);
- wmb(); /* Make sure store if finished */
-
- c_addr = (u32 *)(nc_addr & 0xdfffffff);
- cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32);
- cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat);
-
- if (dqs > 0)
- writel(0x00000074 |
- (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) |
- (((k == 0) ? val : test_dqs) << 8),
- (void *)MT76XX_MEMCTRL_BASE + 0x64);
- else
- writel(0x00007400 |
- (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) |
- (((k == 0) ? val : test_dqs) << 0),
- (void *)MT76XX_MEMCTRL_BASE + 0x64);
- wmb(); /* Make sure store if finished */
-
- invalidate_dcache_range((u32)c_addr,
- (u32)c_addr +
- NUM_OF_CACHELINE * 32);
- wmb(); /* Make sure store if finished */
-
- for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
- if (i % 8 == 0)
- pref_op(0, &c_addr[i]);
- }
-
- for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
- if (c_addr[i] != nc_addr + i + pat)
- return -1;
- }
- }
-
- return 0;
-}
-
-void ddr_calibrate(void)
-{
- u32 min_coarse_dqs[2];
- u32 max_coarse_dqs[2];
- u32 min_fine_dqs[2];
- u32 max_fine_dqs[2];
- u32 coarse_dqs[2];
- u32 fine_dqs[2];
- int reg = 0, ddr_cfg2_reg;
- int flag;
- int i, k;
- int dqs = 0;
- u32 min_coarse_dqs_bnd, min_fine_dqs_bnd, coarse_dqs_dll, fine_dqs_dll;
- u32 val;
- u32 fdiv = 0, frac = 0;
-
- /* Setup clock to run at full speed */
- val = readl((void *)MT76XX_DYN_CFG0_REG);
- fdiv = (u32)((val >> 8) & 0x0F);
- if (CPU_FRAC_DIV < 1 || CPU_FRAC_DIV > 10)
- frac = val & 0x0f;
- else
- frac = CPU_FRAC_DIV;
-
- while (frac < fdiv) {
- val = readl((void *)MT76XX_DYN_CFG0_REG);
- fdiv = (val >> 8) & 0x0f;
- fdiv--;
- val &= ~(0x0f << 8);
- val |= (fdiv << 8);
- writel(val, (void *)MT76XX_DYN_CFG0_REG);
- udelay(500);
- val = readl((void *)MT76XX_DYN_CFG0_REG);
- fdiv = (val >> 8) & 0x0f;
- }
-
- clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
- ddr_cfg2_reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x48);
- clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x48,
- (0x3 << 28) | (0x3 << 26));
-
- min_coarse_dqs[0] = MIN_START;
- min_coarse_dqs[1] = MIN_START;
- min_fine_dqs[0] = MIN_FINE_START;
- min_fine_dqs[1] = MIN_FINE_START;
- max_coarse_dqs[0] = MAX_START;
- max_coarse_dqs[1] = MAX_START;
- max_fine_dqs[0] = MAX_FINE_START;
- max_fine_dqs[1] = MAX_FINE_START;
- dqs = 0;
-
- /* Add by KP, DQS MIN boundary */
- reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x20);
- coarse_dqs_dll = (reg & 0xf00) >> 8;
- fine_dqs_dll = (reg & 0xf0) >> 4;
- if (coarse_dqs_dll <= 8)
- min_coarse_dqs_bnd = 8 - coarse_dqs_dll;
- else
- min_coarse_dqs_bnd = 0;
-
- if (fine_dqs_dll <= 8)
- min_fine_dqs_bnd = 8 - fine_dqs_dll;
- else
- min_fine_dqs_bnd = 0;
- /* DQS MIN boundary */
-
-DQS_CAL:
-
- for (k = 0; k < 2; k++) {
- u32 test_dqs;
-
- if (k == 0)
- test_dqs = MAX_START;
- else
- test_dqs = MAX_FINE_START;
-
- do {
- flag = test_loop(k, dqs, test_dqs, max_coarse_dqs,
- 0x400, 0x3, 0xf);
- if (flag == -1)
- break;
-
- test_dqs++;
- } while (test_dqs <= 0xf);
-
- if (k == 0) {
- max_coarse_dqs[dqs] = test_dqs;
- } else {
- test_dqs--;
-
- if (test_dqs == MAX_FINE_START - 1) {
- max_coarse_dqs[dqs]--;
- max_fine_dqs[dqs] = 0xf;
- } else {
- max_fine_dqs[dqs] = test_dqs;
- }
- }
- }
-
- for (k = 0; k < 2; k++) {
- u32 test_dqs;
-
- if (k == 0)
- test_dqs = MIN_START;
- else
- test_dqs = MIN_FINE_START;
-
- do {
- flag = test_loop(k, dqs, test_dqs, min_coarse_dqs,
- 0x480, 0x1, 0x0);
- if (k == 0) {
- if (flag == -1 ||
- test_dqs == min_coarse_dqs_bnd)
- break;
-
- test_dqs--;
-
- if (test_dqs < min_coarse_dqs_bnd)
- break;
- } else {
- if (flag == -1) {
- test_dqs++;
- break;
- } else if (test_dqs == min_fine_dqs_bnd) {
- break;
- }
-
- test_dqs--;
-
- if (test_dqs < min_fine_dqs_bnd)
- break;
- }
- } while (test_dqs >= 0);
-
- if (k == 0) {
- min_coarse_dqs[dqs] = test_dqs;
- } else {
- if (test_dqs == MIN_FINE_START + 1) {
- min_coarse_dqs[dqs]++;
- min_fine_dqs[dqs] = 0x0;
- } else {
- min_fine_dqs[dqs] = test_dqs;
- }
- }
- }
-
- if (dqs == 0) {
- dqs = 1;
- goto DQS_CAL;
- }
-
- for (i = 0; i < 2; i++) {
- u32 temp;
-
- coarse_dqs[i] = (max_coarse_dqs[i] + min_coarse_dqs[i]) >> 1;
- temp =
- (((max_coarse_dqs[i] + min_coarse_dqs[i]) % 2) * 4) +
- ((max_fine_dqs[i] + min_fine_dqs[i]) >> 1);
- if (temp >= 0x10) {
- coarse_dqs[i]++;
- fine_dqs[i] = (temp - 0x10) + 0x8;
- } else {
- fine_dqs[i] = temp;
- }
- }
- reg = (coarse_dqs[1] << 12) | (fine_dqs[1] << 8) |
- (coarse_dqs[0] << 4) | fine_dqs[0];
-
- clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
- writel(reg, (void *)MT76XX_MEMCTRL_BASE + 0x64);
- writel(ddr_cfg2_reg, (void *)MT76XX_MEMCTRL_BASE + 0x48);
- setbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
-
- for (i = 0; i < 2; i++)
- debug("[%02X%02X%02X%02X]", min_coarse_dqs[i],
- min_fine_dqs[i], max_coarse_dqs[i], max_fine_dqs[i]);
- debug("\nDDR Calibration DQS reg = %08X\n", reg);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2018 Stefan Roese <sr@denx.de>
- *
- * This code is mostly based on the code extracted from this MediaTek
- * github repository:
- *
- * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
- *
- * I was not able to find a specific license or other developers
- * copyrights here, so I can't add them here.
- */
-
-#include <config.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/asm.h>
-#include "mt76xx.h"
-
-#ifndef BIT
-#define BIT(nr) (1 << (nr))
-#endif
-
-#define DELAY_USEC(us) ((us) / 100)
-
-#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
-#define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12)
-
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
-#define DDR_CFG1_SIZE_VAL 0x222e2323
-#define DDR_CFG4_SIZE_VAL 7
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
-#define DDR_CFG1_SIZE_VAL 0x22322323
-#define DDR_CFG4_SIZE_VAL 9
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
-#define DDR_CFG1_SIZE_VAL 0x22362323
-#define DDR_CFG4_SIZE_VAL 9
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
-#define DDR_CFG1_SIZE_VAL 0x223a2323
-#define DDR_CFG4_SIZE_VAL 9
-#endif
-
-#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT)
-#define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16)
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT)
-#define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16)
-#endif
-
-#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT)
-#define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12)
-#endif
-#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT)
-#define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12)
-#endif
-
- .set noreorder
-
-LEAF(lowlevel_init)
-
- /* Load base addresses as physical addresses for later usage */
- li s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE)
- li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)
- li s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE)
-
- /* polling CPLL is ready */
- li t1, DELAY_USEC(1000000)
- la t5, MT76XX_ROM_STATUS_REG
-1:
- lw t2, 0(t5)
- andi t2, t2, 0x1
- bnez t2, CPLL_READY
- subu t1, t1, 1
- bgtz t1, 1b
- nop
- la t0, MT76XX_CLKCFG0_REG
- lw t3, 0(t0)
- ori t3, t3, 0x1
- sw t3, 0(t0)
- b CPLL_DONE
- nop
-CPLL_READY:
- la t0, MT76XX_CLKCFG0_REG
- lw t1, 0(t0)
- li t2, ~0x0c
- and t1, t1, t2
- ori t1, t1, 0xc
- sw t1, 0(t0)
- la t0, MT76XX_DYN_CFG0_REG
- lw t3, 0(t0)
- li t5, ~((0x0f << 8) | (0x0f << 0))
- and t3, t3, t5
- li t5, (10 << 8) | (1 << 0)
- or t3, t3, t5
- sw t3, 0(t0)
- la t0, MT76XX_CLKCFG0_REG
- lw t3, 0(t0)
- li t4, ~0x0F
- and t3, t3, t4
- ori t3, t3, 0xc
- sw t3, 0(t0)
- lw t3, 0(t0)
- ori t3, t3, 0x08
- sw t3, 0(t0)
-
-CPLL_DONE:
- /* Reset MC */
- lw t2, 0x34(s0)
- ori t2, BIT(10)
- sw t2, 0x34(s0)
- nop
-
- /*
- * SDR and DDR initialization: delay 200us
- */
- li t0, DELAY_USEC(200 + 40)
- li t1, 0x1
-1:
- sub t0, t0, t1
- bnez t0, 1b
- nop
-
- /* set DRAM IO PAD for MT7628IC */
- /* DDR LDO Enable */
- lw t4, 0x100(s2)
- li t2, BIT(31)
- or t4, t4, t2
- sw t4, 0x100(s2)
- lw t4, 0x10c(s2)
- j LDO_1P8V
- nop
-LDO_1P8V:
- li t2, ~BIT(6)
- and t4, t4, t2
- sw t4, 0x10c(s2)
- j DDRLDO_SOFT_START
-LDO_2P5V:
- /* suppose external DDR1 LDO 2.5V */
- li t2, BIT(6)
- or t4, t4, t2
- sw t4, 0x10c(s2)
-
-DDRLDO_SOFT_START:
- lw t2, 0x10c(s2)
- li t3, BIT(16)
- or t2, t2, t3
- sw t2, 0x10c(s2)
- li t3, DELAY_USEC(250*50)
-LDO_DELAY:
- subu t3, t3, 1
- bnez t3, LDO_DELAY
- nop
-
- lw t2, 0x10c(s2)
- li t3, BIT(18)
- or t2, t2, t3
- sw t2, 0x10c(s2)
-
-SET_RG_BUCK_FPWM:
- lw t2, 0x104(s2)
- ori t2, t2, BIT(10)
- sw t2, 0x104(s2)
-
-DDR_PAD_CFG:
- /* clean CLK PAD */
- lw t2, 0x704(s2)
- li t8, 0xfffff0f0
- and t2, t2, t8
- /* clean CMD PAD */
- lw t3, 0x70c(s2)
- li t8, 0xfffff0f0
- and t3, t3, t8
- /* clean DQ IPAD */
- lw t4, 0x710(s2)
- li t8, 0xfffff8ff
- and t4, t4, t8
- /* clean DQ OPAD */
- lw t5, 0x714(s2)
- li t8, 0xfffff0f0
- and t5, t5, t8
- /* clean DQS IPAD */
- lw t6, 0x718(s2)
- li t8, 0xfffff8ff
- and t6, t6, t8
- /* clean DQS OPAD */
- lw t7, 0x71c(s2)
- li t8, 0xfffff0f0
- and t7, t7, t8
-
- lw t9, 0xc(s0)
- srl t9, t9, 16
- andi t9, t9, 0x1
- bnez t9, MT7628_AN_DDR1_PAD
-MT7628_KN_PAD:
- li t8, 0x00000303
- or t2, t2, t8
- or t3, t3, t8
- or t5, t5, t8
- or t7, t7, t8
- li t8, 0x00000000
- or t4, t4, t8
- or t6, t6, t8
- j SET_PAD_CFG
-MT7628_AN_DDR1_PAD:
- lw t1, 0x10(s0)
- andi t1, t1, 0x1
- beqz t1, MT7628_AN_DDR2_PAD
- li t8, 0x00000c0c
- or t2, t2, t8
- li t8, 0x00000202
- or t3, t3, t8
- li t8, 0x00000707
- or t5, t5, t8
- li t8, 0x00000c0c
- or t7, t7, t8
- li t8, 0x00000000
- or t4, t4, t8
- or t6, t6, t8
- j SET_PAD_CFG
-MT7628_AN_DDR2_PAD:
- li t8, 0x00000c0c
- or t2, t2, t8
- li t8, 0x00000202
- or t3, t3, t8
- li t8, 0x00000404
- or t5, t5, t8
- li t8, 0x00000c0c
- or t7, t7, t8
- li t8, 0x00000000 /* ODT off */
- or t4, t4, t8
- or t6, t6, t8
-
-SET_PAD_CFG:
- sw t2, 0x704(s2)
- sw t3, 0x70c(s2)
- sw t4, 0x710(s2)
- sw t5, 0x714(s2)
- sw t6, 0x718(s2)
- sw t7, 0x71c(s2)
-
- /*
- * DDR initialization: reset pin to 0
- */
- lw t2, 0x34(s0)
- and t2, ~BIT(10)
- sw t2, 0x34(s0)
- nop
-
- /*
- * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
- */
-DDR_READY:
- li t1, DDR_CFG1_REG
- lw t0, 0(t1)
- nop
- and t2, t0, BIT(21)
- beqz t2, DDR_READY
- nop
-
- /*
- * DDR initialization
- *
- * Only DDR2 supported right now. DDR2 support can be added, once
- * boards using it will get added to mainline U-Boot.
- */
- li t1, DDR_CFG2_REG
- lw t0, 0(t1)
- nop
- and t0, ~BIT(30)
- and t0, ~(7 << 4)
- or t0, (4 << 4)
- or t0, BIT(30)
- or t0, BIT(11)
- sw t0, 0(t1)
- nop
-
- li t1, DDR_CFG3_REG
- lw t2, 0(t1)
- /* Disable ODT; reference board ok, ev board fail */
- and t2, ~BIT(6)
- or t2, BIT(2)
- li t0, DDR_CFG4_REG
- lw t1, 0(t0)
- li t2, ~(0x01f | 0x0f0)
- and t1, t1, t2
- ori t1, t1, DDR_CFG4_SIZE_VAL
- sw t1, 0(t0)
- nop
-
- /*
- * DDR initialization: config size and width on reg DDR_CFG1
- */
- li t6, DDR_CFG1_SIZE_VAL
-
- and t6, ~DDR_CFG1_CHIP_WIDTH_MASK
- or t6, DDR_CFG1_CHIP_WIDTH_VAL
-
- /* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
- and t6, ~DDR_CFG1_BUS_WIDTH_MASK
- or t6, DDR_CFG1_BUS_WIDTH_VAL
-
- li t5, DDR_CFG1_REG
- sw t6, 0(t5)
- nop
-
- /*
- * DDR: enable self auto refresh for power saving
- * enable it by default for both RAM and ROM version (for CoC)
- */
- lw t1, 0x14(s1)
- nop
- and t1, 0xff000000
- or t1, 0x01
- sw t1, 0x14(s1)
- nop
- lw t1, 0x10(s1)
- nop
- or t1, 0x10
- sw t1, 0x10(s1)
- nop
-
- jr ra
- nop
- END(lowlevel_init)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Stefan Roese <sr@denx.de>
- */
-
-#ifndef __MT76XX_H
-#define __MT76XX_H
-
-#define MT76XX_SYSCTL_BASE 0x10000000
-
-#define MT76XX_CHIPID_OFFS 0x00
-#define MT76XX_CHIP_REV_ID_OFFS 0x0c
-#define MT76XX_SYSCFG0_OFFS 0x10
-
-#define MT76XX_MEMCTRL_BASE (MT76XX_SYSCTL_BASE + 0x0300)
-#define MT76XX_RGCTRL_BASE (MT76XX_SYSCTL_BASE + 0x1000)
-
-#define MT76XX_ROM_STATUS_REG (MT76XX_SYSCTL_BASE + 0x0028)
-#define MT76XX_CLKCFG0_REG (MT76XX_SYSCTL_BASE + 0x002c)
-#define MT76XX_DYN_CFG0_REG (MT76XX_SYSCTL_BASE + 0x0440)
-
-#define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44)
-#define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48)
-#define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c)
-#define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50)
-
-#ifndef __ASSEMBLY__
-/* Prototypes */
-void ddr_calibrate(void);
-#endif
-
-#endif
--- /dev/null
+menu "MediaTek MIPS platforms"
+ depends on ARCH_MTMIPS
+
+config SYS_MALLOC_F_LEN
+ default 0x1000
+
+config SYS_SOC
+ default "mt7628" if SOC_MT7628
+
+choice
+ prompt "MediaTek MIPS SoC select"
+
+config SOC_MT7628
+ bool "MT7628"
+ select MIPS_L1_CACHE_SHIFT_5
+ help
+ This supports MediaTek MT7628/MT7688.
+
+endchoice
+
+choice
+ prompt "Board select"
+
+config BOARD_GARDENA_SMART_GATEWAY_MT7688
+ bool "GARDENA smart Gateway"
+ depends on SOC_MT7628
+ select BOARD_LATE_INIT
+ select SUPPORTS_BOOT_RAM
+ help
+ GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
+ and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.
+
+config BOARD_LINKIT_SMART_7688
+ bool "LinkIt Smart 7688"
+ depends on SOC_MT7628
+ select SUPPORTS_BOOT_RAM
+ help
+ Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM
+ and 32 MiB of flash (SPI).
+ Between its different peripherals there's an integrated switch with 4
+ ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
+ a MT7688 (PCIe).
+
+endchoice
+
+choice
+ prompt "Boot mode"
+
+config BOOT_RAM
+ bool "RAM boot"
+ depends on SUPPORTS_BOOT_RAM
+ help
+ This builds an image that is linked to a RAM address. It can be used
+ for booting from CFE via TFTP using an ELF image, but it can also be
+ booted from RAM by other bootloaders using a BIN image.
+
+config BOOT_ROM
+ bool "ROM boot"
+ depends on SUPPORTS_BOOT_RAM
+ help
+ This builds an image that is linked to a ROM address. It can be
+ used as main bootloader image which is programmed onto the onboard
+ flash storage (SPI NOR).
+
+endchoice
+
+choice
+ prompt "DDR2 size"
+
+config ONBOARD_DDR2_SIZE_256MBIT
+ bool "256MBit (32MByte) total size"
+ depends on BOOT_ROM
+ help
+ Use 256MBit (32MByte) of DDR total size
+
+config ONBOARD_DDR2_SIZE_512MBIT
+ bool "512MBit (64MByte) total size"
+ depends on BOOT_ROM
+ help
+ Use 512MBit (64MByte) of DDR total size
+
+config ONBOARD_DDR2_SIZE_1024MBIT
+ bool "1024MBit (128MByte) total size"
+ depends on BOOT_ROM
+ help
+ Use 1024MBit (128MByte) of DDR total size
+
+config ONBOARD_DDR2_SIZE_2048MBIT
+ bool "2048MBit (256MByte) total size"
+ depends on BOOT_ROM
+ help
+ Use 2048MBit (256MByte) of DDR total size
+
+endchoice
+
+choice
+ prompt "DDR2 chip width"
+
+config ONBOARD_DDR2_CHIP_WIDTH_8BIT
+ bool "8bit DDR chip width"
+ depends on BOOT_ROM
+ help
+ Use DDR chips with 8bit width
+
+config ONBOARD_DDR2_CHIP_WIDTH_16BIT
+ bool "16bit DDR chip width"
+ depends on BOOT_ROM
+ help
+ Use DDR chips with 16bit width
+
+endchoice
+
+choice
+ prompt "DDR2 bus width"
+
+config ONBOARD_DDR2_BUS_WIDTH_16BIT
+ bool "16bit DDR bus width"
+ depends on BOOT_ROM
+ help
+ Use 16bit DDR bus width
+
+config ONBOARD_DDR2_BUS_WIDTH_32BIT
+ bool "32bit DDR bus width"
+ depends on BOOT_ROM
+ help
+ Use 32bit DDR bus width
+
+endchoice
+
+config SUPPORTS_BOOT_RAM
+ bool
+
+source "board/gardena/smart-gateway-mt7688/Kconfig"
+source "board/seeed/linkit-smart-7688/Kconfig"
+
+endmenu
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += cpu.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+obj-y += ddr_calibrate.o
+obj-y += lowlevel_init.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include "mt76xx.h"
+
+#define STR_LEN 6
+
+#ifdef CONFIG_BOOT_ROM
+int mach_cpu_init(void)
+{
+ ddr_calibrate();
+
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)",
+ "PLL (4-Byte SPI Addr)",
+ "XTAL (3-Byte SPI Addr)",
+ "XTAL (4-Byte SPI Addr)" };
+ const void *blob = gd->fdt_blob;
+ void __iomem *sysc_base;
+ char buf[STR_LEN + 1];
+ fdt_addr_t base;
+ fdt_size_t size;
+ char *str;
+ int node;
+ u32 val;
+
+ /* Get system controller base address */
+ node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc");
+ if (node < 0)
+ return -FDT_ERR_NOTFOUND;
+
+ base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg",
+ 0, &size, true);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ sysc_base = ioremap_nocache(base, size);
+
+ str = (char *)sysc_base + MT76XX_CHIPID_OFFS;
+ snprintf(buf, STR_LEN + 1, "%s", str);
+ val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS);
+ printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf,
+ (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0));
+
+ val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1;
+ printf("Boot from %s\n", boot_str[val]);
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ *
+ * This code is mostly based on the code extracted from this MediaTek
+ * github repository:
+ *
+ * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
+ *
+ * I was not able to find a specific license or other developers
+ * copyrights here, so I can't add them here.
+ *
+ * Most functions in this file are copied from the MediaTek U-Boot
+ * repository. Without any documentation, it was impossible to really
+ * implement this differently. So its mostly a cleaned-up version of
+ * the original code, with only support for the MT7628 / MT7688 SoC.
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <asm/cacheops.h>
+#include <asm/io.h>
+#include "mt76xx.h"
+
+#define NUM_OF_CACHELINE 128
+#define MIN_START 6
+#define MIN_FINE_START 0xf
+#define MAX_START 7
+#define MAX_FINE_START 0x0
+
+#define CPU_FRAC_DIV 1
+
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
+#define DRAM_BUTTOM 0x02000000
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
+#define DRAM_BUTTOM 0x04000000
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
+#define DRAM_BUTTOM 0x08000000
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
+#define DRAM_BUTTOM 0x10000000
+#endif
+
+static inline void cal_memcpy(void *src, void *dst, u32 size)
+{
+ u8 *psrc = (u8 *)src;
+ u8 *pdst = (u8 *)dst;
+ int i;
+
+ for (i = 0; i < size; i++, psrc++, pdst++)
+ *pdst = *psrc;
+}
+
+static inline void cal_memset(void *src, u8 pat, u32 size)
+{
+ u8 *psrc = (u8 *)src;
+ int i;
+
+ for (i = 0; i < size; i++, psrc++)
+ *psrc = pat;
+}
+
+#define pref_op(hint, addr) \
+ __asm__ __volatile__( \
+ ".set push\n" \
+ ".set noreorder\n" \
+ "pref %0, %1\n" \
+ ".set pop\n" \
+ : \
+ : "i" (hint), "R" (*(u8 *)(addr)))
+
+static inline void cal_patgen(u32 start_addr, u32 size, u32 bias)
+{
+ u32 *addr = (u32 *)start_addr;
+ int i;
+
+ for (i = 0; i < size; i++)
+ addr[i] = start_addr + i + bias;
+}
+
+static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs,
+ u32 offs, u32 pat, u32 val)
+{
+ u32 nc_addr;
+ u32 *c_addr;
+ int i;
+
+ for (nc_addr = 0xa0000000;
+ nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32);
+ nc_addr += (DRAM_BUTTOM >> 6) + offs) {
+ writel(0x00007474, (void *)MT76XX_MEMCTRL_BASE + 0x64);
+ wmb(); /* Make sure store if finished */
+
+ c_addr = (u32 *)(nc_addr & 0xdfffffff);
+ cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32);
+ cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat);
+
+ if (dqs > 0)
+ writel(0x00000074 |
+ (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) |
+ (((k == 0) ? val : test_dqs) << 8),
+ (void *)MT76XX_MEMCTRL_BASE + 0x64);
+ else
+ writel(0x00007400 |
+ (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) |
+ (((k == 0) ? val : test_dqs) << 0),
+ (void *)MT76XX_MEMCTRL_BASE + 0x64);
+ wmb(); /* Make sure store if finished */
+
+ invalidate_dcache_range((u32)c_addr,
+ (u32)c_addr +
+ NUM_OF_CACHELINE * 32);
+ wmb(); /* Make sure store if finished */
+
+ for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
+ if (i % 8 == 0)
+ pref_op(0, &c_addr[i]);
+ }
+
+ for (i = 0; i < NUM_OF_CACHELINE * 8; i++) {
+ if (c_addr[i] != nc_addr + i + pat)
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+void ddr_calibrate(void)
+{
+ u32 min_coarse_dqs[2];
+ u32 max_coarse_dqs[2];
+ u32 min_fine_dqs[2];
+ u32 max_fine_dqs[2];
+ u32 coarse_dqs[2];
+ u32 fine_dqs[2];
+ int reg = 0, ddr_cfg2_reg;
+ int flag;
+ int i, k;
+ int dqs = 0;
+ u32 min_coarse_dqs_bnd, min_fine_dqs_bnd, coarse_dqs_dll, fine_dqs_dll;
+ u32 val;
+ u32 fdiv = 0, frac = 0;
+
+ /* Setup clock to run at full speed */
+ val = readl((void *)MT76XX_DYN_CFG0_REG);
+ fdiv = (u32)((val >> 8) & 0x0F);
+ if (CPU_FRAC_DIV < 1 || CPU_FRAC_DIV > 10)
+ frac = val & 0x0f;
+ else
+ frac = CPU_FRAC_DIV;
+
+ while (frac < fdiv) {
+ val = readl((void *)MT76XX_DYN_CFG0_REG);
+ fdiv = (val >> 8) & 0x0f;
+ fdiv--;
+ val &= ~(0x0f << 8);
+ val |= (fdiv << 8);
+ writel(val, (void *)MT76XX_DYN_CFG0_REG);
+ udelay(500);
+ val = readl((void *)MT76XX_DYN_CFG0_REG);
+ fdiv = (val >> 8) & 0x0f;
+ }
+
+ clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
+ ddr_cfg2_reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x48);
+ clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x48,
+ (0x3 << 28) | (0x3 << 26));
+
+ min_coarse_dqs[0] = MIN_START;
+ min_coarse_dqs[1] = MIN_START;
+ min_fine_dqs[0] = MIN_FINE_START;
+ min_fine_dqs[1] = MIN_FINE_START;
+ max_coarse_dqs[0] = MAX_START;
+ max_coarse_dqs[1] = MAX_START;
+ max_fine_dqs[0] = MAX_FINE_START;
+ max_fine_dqs[1] = MAX_FINE_START;
+ dqs = 0;
+
+ /* Add by KP, DQS MIN boundary */
+ reg = readl((void *)MT76XX_MEMCTRL_BASE + 0x20);
+ coarse_dqs_dll = (reg & 0xf00) >> 8;
+ fine_dqs_dll = (reg & 0xf0) >> 4;
+ if (coarse_dqs_dll <= 8)
+ min_coarse_dqs_bnd = 8 - coarse_dqs_dll;
+ else
+ min_coarse_dqs_bnd = 0;
+
+ if (fine_dqs_dll <= 8)
+ min_fine_dqs_bnd = 8 - fine_dqs_dll;
+ else
+ min_fine_dqs_bnd = 0;
+ /* DQS MIN boundary */
+
+DQS_CAL:
+
+ for (k = 0; k < 2; k++) {
+ u32 test_dqs;
+
+ if (k == 0)
+ test_dqs = MAX_START;
+ else
+ test_dqs = MAX_FINE_START;
+
+ do {
+ flag = test_loop(k, dqs, test_dqs, max_coarse_dqs,
+ 0x400, 0x3, 0xf);
+ if (flag == -1)
+ break;
+
+ test_dqs++;
+ } while (test_dqs <= 0xf);
+
+ if (k == 0) {
+ max_coarse_dqs[dqs] = test_dqs;
+ } else {
+ test_dqs--;
+
+ if (test_dqs == MAX_FINE_START - 1) {
+ max_coarse_dqs[dqs]--;
+ max_fine_dqs[dqs] = 0xf;
+ } else {
+ max_fine_dqs[dqs] = test_dqs;
+ }
+ }
+ }
+
+ for (k = 0; k < 2; k++) {
+ u32 test_dqs;
+
+ if (k == 0)
+ test_dqs = MIN_START;
+ else
+ test_dqs = MIN_FINE_START;
+
+ do {
+ flag = test_loop(k, dqs, test_dqs, min_coarse_dqs,
+ 0x480, 0x1, 0x0);
+ if (k == 0) {
+ if (flag == -1 ||
+ test_dqs == min_coarse_dqs_bnd)
+ break;
+
+ test_dqs--;
+
+ if (test_dqs < min_coarse_dqs_bnd)
+ break;
+ } else {
+ if (flag == -1) {
+ test_dqs++;
+ break;
+ } else if (test_dqs == min_fine_dqs_bnd) {
+ break;
+ }
+
+ test_dqs--;
+
+ if (test_dqs < min_fine_dqs_bnd)
+ break;
+ }
+ } while (test_dqs >= 0);
+
+ if (k == 0) {
+ min_coarse_dqs[dqs] = test_dqs;
+ } else {
+ if (test_dqs == MIN_FINE_START + 1) {
+ min_coarse_dqs[dqs]++;
+ min_fine_dqs[dqs] = 0x0;
+ } else {
+ min_fine_dqs[dqs] = test_dqs;
+ }
+ }
+ }
+
+ if (dqs == 0) {
+ dqs = 1;
+ goto DQS_CAL;
+ }
+
+ for (i = 0; i < 2; i++) {
+ u32 temp;
+
+ coarse_dqs[i] = (max_coarse_dqs[i] + min_coarse_dqs[i]) >> 1;
+ temp =
+ (((max_coarse_dqs[i] + min_coarse_dqs[i]) % 2) * 4) +
+ ((max_fine_dqs[i] + min_fine_dqs[i]) >> 1);
+ if (temp >= 0x10) {
+ coarse_dqs[i]++;
+ fine_dqs[i] = (temp - 0x10) + 0x8;
+ } else {
+ fine_dqs[i] = temp;
+ }
+ }
+ reg = (coarse_dqs[1] << 12) | (fine_dqs[1] << 8) |
+ (coarse_dqs[0] << 4) | fine_dqs[0];
+
+ clrbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
+ writel(reg, (void *)MT76XX_MEMCTRL_BASE + 0x64);
+ writel(ddr_cfg2_reg, (void *)MT76XX_MEMCTRL_BASE + 0x48);
+ setbits_le32((void *)MT76XX_MEMCTRL_BASE + 0x10, BIT(4));
+
+ for (i = 0; i < 2; i++)
+ debug("[%02X%02X%02X%02X]", min_coarse_dqs[i],
+ min_fine_dqs[i], max_coarse_dqs[i], max_fine_dqs[i]);
+ debug("\nDDR Calibration DQS reg = %08X\n", reg);
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) 2018 Stefan Roese <sr@denx.de>
+ *
+ * This code is mostly based on the code extracted from this MediaTek
+ * github repository:
+ *
+ * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
+ *
+ * I was not able to find a specific license or other developers
+ * copyrights here, so I can't add them here.
+ */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include "mt76xx.h"
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define DELAY_USEC(us) ((us) / 100)
+
+#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
+#define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12)
+
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
+#define DDR_CFG1_SIZE_VAL 0x222e2323
+#define DDR_CFG4_SIZE_VAL 7
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
+#define DDR_CFG1_SIZE_VAL 0x22322323
+#define DDR_CFG4_SIZE_VAL 9
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
+#define DDR_CFG1_SIZE_VAL 0x22362323
+#define DDR_CFG4_SIZE_VAL 9
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
+#define DDR_CFG1_SIZE_VAL 0x223a2323
+#define DDR_CFG4_SIZE_VAL 9
+#endif
+
+#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT)
+#define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16)
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT)
+#define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16)
+#endif
+
+#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT)
+#define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12)
+#endif
+#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT)
+#define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12)
+#endif
+
+ .set noreorder
+
+LEAF(lowlevel_init)
+
+ /* Load base addresses as physical addresses for later usage */
+ li s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE)
+ li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)
+ li s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE)
+
+ /* polling CPLL is ready */
+ li t1, DELAY_USEC(1000000)
+ la t5, MT76XX_ROM_STATUS_REG
+1:
+ lw t2, 0(t5)
+ andi t2, t2, 0x1
+ bnez t2, CPLL_READY
+ subu t1, t1, 1
+ bgtz t1, 1b
+ nop
+ la t0, MT76XX_CLKCFG0_REG
+ lw t3, 0(t0)
+ ori t3, t3, 0x1
+ sw t3, 0(t0)
+ b CPLL_DONE
+ nop
+CPLL_READY:
+ la t0, MT76XX_CLKCFG0_REG
+ lw t1, 0(t0)
+ li t2, ~0x0c
+ and t1, t1, t2
+ ori t1, t1, 0xc
+ sw t1, 0(t0)
+ la t0, MT76XX_DYN_CFG0_REG
+ lw t3, 0(t0)
+ li t5, ~((0x0f << 8) | (0x0f << 0))
+ and t3, t3, t5
+ li t5, (10 << 8) | (1 << 0)
+ or t3, t3, t5
+ sw t3, 0(t0)
+ la t0, MT76XX_CLKCFG0_REG
+ lw t3, 0(t0)
+ li t4, ~0x0F
+ and t3, t3, t4
+ ori t3, t3, 0xc
+ sw t3, 0(t0)
+ lw t3, 0(t0)
+ ori t3, t3, 0x08
+ sw t3, 0(t0)
+
+CPLL_DONE:
+ /* Reset MC */
+ lw t2, 0x34(s0)
+ ori t2, BIT(10)
+ sw t2, 0x34(s0)
+ nop
+
+ /*
+ * SDR and DDR initialization: delay 200us
+ */
+ li t0, DELAY_USEC(200 + 40)
+ li t1, 0x1
+1:
+ sub t0, t0, t1
+ bnez t0, 1b
+ nop
+
+ /* set DRAM IO PAD for MT7628IC */
+ /* DDR LDO Enable */
+ lw t4, 0x100(s2)
+ li t2, BIT(31)
+ or t4, t4, t2
+ sw t4, 0x100(s2)
+ lw t4, 0x10c(s2)
+ j LDO_1P8V
+ nop
+LDO_1P8V:
+ li t2, ~BIT(6)
+ and t4, t4, t2
+ sw t4, 0x10c(s2)
+ j DDRLDO_SOFT_START
+LDO_2P5V:
+ /* suppose external DDR1 LDO 2.5V */
+ li t2, BIT(6)
+ or t4, t4, t2
+ sw t4, 0x10c(s2)
+
+DDRLDO_SOFT_START:
+ lw t2, 0x10c(s2)
+ li t3, BIT(16)
+ or t2, t2, t3
+ sw t2, 0x10c(s2)
+ li t3, DELAY_USEC(250*50)
+LDO_DELAY:
+ subu t3, t3, 1
+ bnez t3, LDO_DELAY
+ nop
+
+ lw t2, 0x10c(s2)
+ li t3, BIT(18)
+ or t2, t2, t3
+ sw t2, 0x10c(s2)
+
+SET_RG_BUCK_FPWM:
+ lw t2, 0x104(s2)
+ ori t2, t2, BIT(10)
+ sw t2, 0x104(s2)
+
+DDR_PAD_CFG:
+ /* clean CLK PAD */
+ lw t2, 0x704(s2)
+ li t8, 0xfffff0f0
+ and t2, t2, t8
+ /* clean CMD PAD */
+ lw t3, 0x70c(s2)
+ li t8, 0xfffff0f0
+ and t3, t3, t8
+ /* clean DQ IPAD */
+ lw t4, 0x710(s2)
+ li t8, 0xfffff8ff
+ and t4, t4, t8
+ /* clean DQ OPAD */
+ lw t5, 0x714(s2)
+ li t8, 0xfffff0f0
+ and t5, t5, t8
+ /* clean DQS IPAD */
+ lw t6, 0x718(s2)
+ li t8, 0xfffff8ff
+ and t6, t6, t8
+ /* clean DQS OPAD */
+ lw t7, 0x71c(s2)
+ li t8, 0xfffff0f0
+ and t7, t7, t8
+
+ lw t9, 0xc(s0)
+ srl t9, t9, 16
+ andi t9, t9, 0x1
+ bnez t9, MT7628_AN_DDR1_PAD
+MT7628_KN_PAD:
+ li t8, 0x00000303
+ or t2, t2, t8
+ or t3, t3, t8
+ or t5, t5, t8
+ or t7, t7, t8
+ li t8, 0x00000000
+ or t4, t4, t8
+ or t6, t6, t8
+ j SET_PAD_CFG
+MT7628_AN_DDR1_PAD:
+ lw t1, 0x10(s0)
+ andi t1, t1, 0x1
+ beqz t1, MT7628_AN_DDR2_PAD
+ li t8, 0x00000c0c
+ or t2, t2, t8
+ li t8, 0x00000202
+ or t3, t3, t8
+ li t8, 0x00000707
+ or t5, t5, t8
+ li t8, 0x00000c0c
+ or t7, t7, t8
+ li t8, 0x00000000
+ or t4, t4, t8
+ or t6, t6, t8
+ j SET_PAD_CFG
+MT7628_AN_DDR2_PAD:
+ li t8, 0x00000c0c
+ or t2, t2, t8
+ li t8, 0x00000202
+ or t3, t3, t8
+ li t8, 0x00000404
+ or t5, t5, t8
+ li t8, 0x00000c0c
+ or t7, t7, t8
+ li t8, 0x00000000 /* ODT off */
+ or t4, t4, t8
+ or t6, t6, t8
+
+SET_PAD_CFG:
+ sw t2, 0x704(s2)
+ sw t3, 0x70c(s2)
+ sw t4, 0x710(s2)
+ sw t5, 0x714(s2)
+ sw t6, 0x718(s2)
+ sw t7, 0x71c(s2)
+
+ /*
+ * DDR initialization: reset pin to 0
+ */
+ lw t2, 0x34(s0)
+ and t2, ~BIT(10)
+ sw t2, 0x34(s0)
+ nop
+
+ /*
+ * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
+ */
+DDR_READY:
+ li t1, DDR_CFG1_REG
+ lw t0, 0(t1)
+ nop
+ and t2, t0, BIT(21)
+ beqz t2, DDR_READY
+ nop
+
+ /*
+ * DDR initialization
+ *
+ * Only DDR2 supported right now. DDR2 support can be added, once
+ * boards using it will get added to mainline U-Boot.
+ */
+ li t1, DDR_CFG2_REG
+ lw t0, 0(t1)
+ nop
+ and t0, ~BIT(30)
+ and t0, ~(7 << 4)
+ or t0, (4 << 4)
+ or t0, BIT(30)
+ or t0, BIT(11)
+ sw t0, 0(t1)
+ nop
+
+ li t1, DDR_CFG3_REG
+ lw t2, 0(t1)
+ /* Disable ODT; reference board ok, ev board fail */
+ and t2, ~BIT(6)
+ or t2, BIT(2)
+ li t0, DDR_CFG4_REG
+ lw t1, 0(t0)
+ li t2, ~(0x01f | 0x0f0)
+ and t1, t1, t2
+ ori t1, t1, DDR_CFG4_SIZE_VAL
+ sw t1, 0(t0)
+ nop
+
+ /*
+ * DDR initialization: config size and width on reg DDR_CFG1
+ */
+ li t6, DDR_CFG1_SIZE_VAL
+
+ and t6, ~DDR_CFG1_CHIP_WIDTH_MASK
+ or t6, DDR_CFG1_CHIP_WIDTH_VAL
+
+ /* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
+ and t6, ~DDR_CFG1_BUS_WIDTH_MASK
+ or t6, DDR_CFG1_BUS_WIDTH_VAL
+
+ li t5, DDR_CFG1_REG
+ sw t6, 0(t5)
+ nop
+
+ /*
+ * DDR: enable self auto refresh for power saving
+ * enable it by default for both RAM and ROM version (for CoC)
+ */
+ lw t1, 0x14(s1)
+ nop
+ and t1, 0xff000000
+ or t1, 0x01
+ sw t1, 0x14(s1)
+ nop
+ lw t1, 0x10(s1)
+ nop
+ or t1, 0x10
+ sw t1, 0x10(s1)
+ nop
+
+ jr ra
+ nop
+ END(lowlevel_init)
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __MT76XX_H
+#define __MT76XX_H
+
+#define MT76XX_SYSCTL_BASE 0x10000000
+
+#define MT76XX_CHIPID_OFFS 0x00
+#define MT76XX_CHIP_REV_ID_OFFS 0x0c
+#define MT76XX_SYSCFG0_OFFS 0x10
+
+#define MT76XX_MEMCTRL_BASE (MT76XX_SYSCTL_BASE + 0x0300)
+#define MT76XX_RGCTRL_BASE (MT76XX_SYSCTL_BASE + 0x1000)
+
+#define MT76XX_ROM_STATUS_REG (MT76XX_SYSCTL_BASE + 0x0028)
+#define MT76XX_CLKCFG0_REG (MT76XX_SYSCTL_BASE + 0x002c)
+#define MT76XX_DYN_CFG0_REG (MT76XX_SYSCTL_BASE + 0x0440)
+
+#define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44)
+#define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48)
+#define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c)
+#define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50)
+
+#ifndef __ASSEMBLY__
+/* Prototypes */
+void ddr_calibrate(void);
+#endif
+
+#endif
endchoice
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
source "board/AndesTech/adp-ag101p/Kconfig"
source "board/AndesTech/adp-ae3xx/Kconfig"
mfsr $r1, $mr8
and $r1, $r1, $r0
mtsr $r1, $mr8
-#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/*
* MMU_CTL NTC0 Cacheable/Write-Back
*/
mtsr $r1, $mr0
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_ARCH_MAP_SYSMEM
/*
* MMU_CTL NTC1 Non-cacheable
#endif
#endif
-#if !defined(CONFIG_SYS_ICACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
li $r0, 0x1
mfsr $r1, $mr8
or $r1, $r1, $r0
mtsr $r1, $mr8
#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
li $r0, 0x2
mfsr $r1, $mr8
or $r1, $r1, $r0
*/
#include <common.h>
-#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
static inline unsigned long CACHE_SET(unsigned char cache)
{
if (cache == ICACHE)
}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
unsigned long end, line_size;
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_wbinval_all(void)
{
unsigned long end, line_size;
endchoice
+config HIGH_BATS
+ bool "Enable high BAT registers"
+ help
+ Enable BATs (block address translation registers) 4-7 on machines
+ that support them.
+
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"
config TARGET_MPC8308_P1M
bool "Support mpc8308_p1m"
+ select ARCH_MPC8308
config TARGET_SBC8349
bool "Support sbc8349"
+ select ARCH_MPC8349
config TARGET_VE8313
bool "Support ve8313"
+ select ARCH_MPC8313
config TARGET_VME8349
bool "Support vme8349"
+ select ARCH_MPC8349
+
+config TARGET_CADDY2
+ bool "Support caddy2"
+ select ARCH_MPC8349
config TARGET_MPC8308RDB
bool "Support MPC8308RDB"
+ select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
-config TARGET_MPC8313ERDB
- bool "Support MPC8313ERDB"
+config TARGET_MPC8313ERDB_NOR
+ bool "Support MPC8313ERDB_NOR"
+ select ARCH_MPC8313
+ select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
+
+config TARGET_MPC8313ERDB_NAND
+ bool "Support MPC8313ERDB_NAND"
+ select ARCH_MPC8313
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
+ select ARCH_MPC8315
select BOARD_EARLY_INIT_F
config TARGET_MPC8323ERDB
bool "Support MPC8323ERDB"
+ select ARCH_MPC832X
config TARGET_MPC832XEMDS
bool "Support MPC832XEMDS"
+ select ARCH_MPC832X
select BOARD_EARLY_INIT_F
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
+ select ARCH_MPC8349
+ select BOARD_EARLY_INIT_F
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
+ select SYS_FSL_HAS_DDR2
+
+config TARGET_MPC8349EMDS_SDRAM
+ bool "Support MPC8349EMDS_SDRAM"
+ select ARCH_MPC8349
select BOARD_EARLY_INIT_F
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
+ select ARCH_MPC8349
imply CMD_IRQ
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
+ select ARCH_MPC837X
select BOARD_EARLY_INIT_F
imply CMD_SATA
imply FSL_SATA
config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
+ select ARCH_MPC837X
select BOARD_EARLY_INIT_F
config TARGET_IDS8313
bool "Support ids8313"
+ select ARCH_MPC8313
select DM
imply CMD_DM
-config TARGET_KM8360
- bool "Support km8360"
+config TARGET_KMETER1
+ bool "Support kmeter1"
+ select ARCH_MPC8360
+ imply CMD_CRAMFS
+ imply CMD_DIAG
+ imply FS_CRAMFS
+
+config TARGET_KMCOGE5NE
+ bool "Support kmcoge5ne"
+ select ARCH_MPC8360
imply CMD_CRAMFS
imply CMD_DIAG
imply FS_CRAMFS
config TARGET_SUVD3
bool "Support suvd3"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMVECT1
+ bool "Support kmvect1"
+ select ARCH_MPC8309
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMTEGR1
+ bool "Support kmtegr1"
+ select ARCH_MPC8309
imply CMD_CRAMFS
imply FS_CRAMFS
config TARGET_TUXX1
bool "Support tuxx1"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMSUPX5
+ bool "Support kmsupx5"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_TUGE1
+ bool "Support tuge1"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMOPTI2
+ bool "Support kmopti2"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMTEPR2
+ bool "Support kmtepr2"
+ select ARCH_MPC832X
imply CMD_CRAMFS
imply FS_CRAMFS
config TARGET_TQM834X
bool "Support TQM834x"
+ select ARCH_MPC8349
config TARGET_HRCON
bool "Support hrcon"
+ select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER
bool "Support strider"
+ select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_PCA953X
+config TARGET_GAZERBEAM
+ bool "Support gazerbeam"
+ select ARCH_MPC8308
+ select SYS_FSL_ERRATUM_ESDHC111
+ imply ENV_IS_IN_FLASH
+ help
+ The "Gazerbeam" is a modular system by Guntermann & Drunck GmbH
+ Systementwicklung based on the NXP MPC8308 SoC for usage in KVM
+ appliances.
+
+ Features include:
+ * Two gigabit ethernet ports
+ * Multiple USB ports (depending on variant)
+ * Several gigabit ethernet or optical fiber ports (depending on
+ variant)
+ * Several display port inputs and outputs, and supporting redrivers
+ (depending on variant)
+ * Several FPGAs with custom logic (depending on variant)
+
+endchoice
+
+config MPC83XX_QUICC_ENGINE
+ bool
+
+# TODO: Imply MPC83xx PCI driver
+config MPC83XX_PCI_SUPPORT
+ bool
+
+# TODO: Imply TSEC driver
+config MPC83XX_TSEC1_SUPPORT
+ bool
+
+config MPC83XX_TSEC2_SUPPORT
+ bool
+
+config MPC83XX_PCIE1_SUPPORT
+ bool
+
+config MPC83XX_PCIE2_SUPPORT
+ bool
+
+config MPC83XX_SDHC_SUPPORT
+ bool
+
+config MPC83XX_SATA_SUPPORT
+ bool
+
+config MPC83XX_SECOND_I2C_SUPPORT
+ bool
+
+config MPC83XX_LDP_PIN
+ bool
+
+config ARCH_MPC830X
+ bool
+ select MPC83XX_SDHC_SUPPORT
+
+config ARCH_MPC8308
+ bool
+ select ARCH_MPC830X
+ select MPC83XX_TSEC1_SUPPORT
+ select MPC83XX_TSEC2_SUPPORT
+ select MPC83XX_PCIE1_SUPPORT
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8309
+ bool
+ select ARCH_MPC830X
+ select MPC83XX_QUICC_ENGINE
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC831X
+ bool
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_TSEC1_SUPPORT
+ select MPC83XX_TSEC2_SUPPORT
+
+config ARCH_MPC8313
+ bool
+ select ARCH_MPC831X
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8315
+ bool
+ select ARCH_MPC831X
+ select MPC83XX_PCIE1_SUPPORT
+ select MPC83XX_PCIE2_SUPPORT
+ select MPC83XX_SATA_SUPPORT
+
+config ARCH_MPC832X
+ bool
+ select MPC83XX_QUICC_ENGINE
+ select MPC83XX_PCI_SUPPORT
+
+config ARCH_MPC834X
+ bool
+
+config ARCH_MPC8349
+ bool
+ select ARCH_MPC834X
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_TSEC1_SUPPORT
+ select MPC83XX_TSEC2_SUPPORT
+ select MPC83XX_LDP_PIN
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8360
+ bool
+ select MPC83XX_QUICC_ENGINE
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_LDP_PIN
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC837X
+ bool
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_TSEC1_SUPPORT
+ select MPC83XX_TSEC2_SUPPORT
+ select MPC83XX_PCIE1_SUPPORT
+ select MPC83XX_PCIE2_SUPPORT
+ select MPC83XX_SDHC_SUPPORT
+ select MPC83XX_SATA_SUPPORT
+ select MPC83XX_LDP_PIN
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config SYS_IMMR
+ hex "Value for IMMR"
+ default 0xE0000000
+ help
+ Address for the Internal Memory-Mapped Registers (IMMR) window used
+ to configure the features of the SoC.
+
+source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/hid/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
+
+menu "Legacy options"
+
+if ARCH_MPC8349
+
+#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT
+choice
+ prompt "PMC slot configuration"
+
+config PCI_ALL_PCI1
+ bool "All PMC slots on PCI1"
+
+config PCI_ONE_PCI1
+ bool "First PMC1 on PCI1"
+
+config PCI_TWO_PCI1
+ bool "First two PMC1 on PCI1"
+
endchoice
+config PCI_64BIT
+ bool "PMC2 is 64bit"
+
+endif
+
+endmenu
+
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8308rdb/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"
obj-y += ecc.o
obj-$(CONFIG_QE) += qe_io.o
obj-$(CONFIG_FSL_SERDES) += serdes.o
+ifndef CONFIG_ARCH_MPC8308
obj-$(CONFIG_PCI) += pci.o
+endif
obj-$(CONFIG_PCIE) += pcie.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
--- /dev/null
+menu "Arbiter"
+
+choice
+ prompt "Pipeline depth"
+
+config ACR_PIPE_DEP_UNSET
+ bool "Don't set value"
+
+config ACR_PIPE_DEP_1
+ bool "1"
+
+config ACR_PIPE_DEP_2
+ bool "2"
+
+config ACR_PIPE_DEP_3
+ bool "3"
+
+config ACR_PIPE_DEP_4
+ bool "4"
+
+endchoice
+
+choice
+ prompt "Repeat count"
+
+config ACR_RPTCNT_UNSET
+ bool "Don't set value"
+
+config ACR_RPTCNT_1
+ bool "1"
+
+config ACR_RPTCNT_2
+ bool "2"
+
+config ACR_RPTCNT_3
+ bool "3"
+
+config ACR_RPTCNT_4
+ bool "4"
+
+config ACR_RPTCNT_5
+ bool "5"
+
+config ACR_RPTCNT_6
+ bool "6"
+
+config ACR_RPTCNT_7
+ bool "7"
+
+config ACR_RPTCNT_8
+ bool "8"
+
+endchoice
+
+choice
+ prompt "Address parking"
+
+config ACR_APARK_UNSET
+ bool "Don't set value"
+
+config ACR_APARK_MASTER
+ bool "Park to master"
+
+config ACR_APARK_LAST
+ bool "Park to last owner"
+
+config ACR_APARK_DISABLE
+ bool "Disabled"
+
+endchoice
+
+choice
+ prompt "Parking master"
+
+config ACR_PARKM_UNSET
+ bool "Don't set value"
+
+config ACR_PARKM_E300
+ bool "e300 core"
+
+config ACR_PARKM_TSEC_1_2
+ bool "TSEC1, TSEC2"
+
+config ACR_PARKM_USB_I2C1_BOOT
+ bool "USB/I2C1_BOOT"
+
+config ACR_PARKM_DMA_ESDHC_USB
+ bool "DMA, ESDHC, USB"
+
+config ACR_PARKM_PEX
+ bool "PCI Express"
+
+if MPC83XX_QUICC_ENGINE
+
+config ACR_PARKM_ENC_CORE
+ bool "Encryption core"
+
+endif
+
+endchoice
+
+config ACR_PIPE_DEP
+ hex
+ default 0x0 if ACR_PIPE_DEP_UNSET
+ default 0x0 if ACR_PIPE_DEP_1
+ default 0x10000 if ACR_PIPE_DEP_2
+ default 0x20000 if ACR_PIPE_DEP_3
+ default 0x30000 if ACR_PIPE_DEP_4
+
+config ACR_RPTCNT
+ hex
+ default 0x0 if ACR_RPTCNT_UNSET
+ default 0x0 if ACR_RPTCNT_1
+ default 0x100 if ACR_RPTCNT_2
+ default 0x200 if ACR_RPTCNT_3
+ default 0x300 if ACR_RPTCNT_4
+ default 0x400 if ACR_RPTCNT_5
+ default 0x500 if ACR_RPTCNT_6
+ default 0x600 if ACR_RPTCNT_7
+ default 0x700 if ACR_RPTCNT_8
+
+config ACR_APARK
+ hex
+ default 0x0 if ACR_APARK_UNSET
+ default 0x0 if ACR_APARK_MASTER
+ default 0x10 if ACR_APARK_LAST
+ default 0x20 if ACR_APARK_DISABLE
+
+config ACR_PARKM
+ hex
+ default 0x0 if ACR_PARKM_UNSET
+ default 0x0 if ACR_PARKM_E300
+ default 0x2 if ACR_PARKM_TSEC_1_2
+ default 0x3 if ACR_PARKM_USB_I2C1_BOOT
+ default 0x4 if ACR_PARKM_DMA_ESDHC_USB
+ default 0x5 if ACR_PARKM_PEX
+ default 0x5 if ACR_PARKM_ENC_CORE
+
+endmenu
--- /dev/null
+ const __be32 acr_mask =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+ ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+ ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+ ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+ ACR_PARKM |
+#endif
+ 0;
+ const __be32 acr_val =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+ CONFIG_ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+ CONFIG_ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+ CONFIG_ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+ CONFIG_ACR_PARKM |
+#endif
+ 0;
--- /dev/null
+menu "BATS setup"
+
+menuconfig BAT0
+ bool "BAT0"
+
+if BAT0
+
+config BAT0_NAME
+ string "Identifier"
+
+config BAT0_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT0_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT0_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT0_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT0_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT0_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT0_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT0_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT0_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT0_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT0_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT0_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT0_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT0_ACCESS_NONE
+ bool "No access"
+
+config BAT0_ACCESS_RO
+ bool "Read-only"
+
+config BAT0_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT0_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT0_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT0_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT0_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT0_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT0_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT0_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT0_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT0_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT0_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT0_LENGTH
+ hex
+ default 0x00000000 if BAT0_LENGTH_128_KBYTES
+ default 0x00000004 if BAT0_LENGTH_256_KBYTES
+ default 0x0000000c if BAT0_LENGTH_512_KBYTES
+ default 0x0000001c if BAT0_LENGTH_1_MBYTES
+ default 0x0000003c if BAT0_LENGTH_2_MBYTES
+ default 0x0000007c if BAT0_LENGTH_4_MBYTES
+ default 0x000000fc if BAT0_LENGTH_8_MBYTES
+ default 0x000001fc if BAT0_LENGTH_16_MBYTES
+ default 0x000003fc if BAT0_LENGTH_32_MBYTES
+ default 0x000007fc if BAT0_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT0_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT0_LENGTH_256_MBYTES
+
+config BAT0_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT0_ACCESS_NONE
+ default 0x1 if BAT0_ACCESS_RO
+ default 0x2 if BAT0_ACCESS_RW
+
+config BAT0_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+
+config BAT0_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x8 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x10 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x18 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x20 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x28 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x30 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x38 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x40 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x48 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x50 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x58 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x60 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x68 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x70 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x78 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+
+config BAT0_VALID_BITS
+ hex
+ default 0x0 if !BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID
+ default 0x1 if !BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID
+ default 0x2 if BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID
+ default 0x3 if BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID
+
+menuconfig BAT1
+ bool "BAT1"
+
+if BAT1
+
+config BAT1_NAME
+ string "Identifier"
+
+config BAT1_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT1_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT1_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT1_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT1_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT1_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT1_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT1_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT1_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT1_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT1_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT1_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT1_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT1_ACCESS_NONE
+ bool "No access"
+
+config BAT1_ACCESS_RO
+ bool "Read-only"
+
+config BAT1_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT1_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT1_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT1_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT1_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT1_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT1_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT1_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT1_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT1_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT1_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT1_LENGTH
+ hex
+ default 0x00000000 if BAT1_LENGTH_128_KBYTES
+ default 0x00000004 if BAT1_LENGTH_256_KBYTES
+ default 0x0000000c if BAT1_LENGTH_512_KBYTES
+ default 0x0000001c if BAT1_LENGTH_1_MBYTES
+ default 0x0000003c if BAT1_LENGTH_2_MBYTES
+ default 0x0000007c if BAT1_LENGTH_4_MBYTES
+ default 0x000000fc if BAT1_LENGTH_8_MBYTES
+ default 0x000001fc if BAT1_LENGTH_16_MBYTES
+ default 0x000003fc if BAT1_LENGTH_32_MBYTES
+ default 0x000007fc if BAT1_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT1_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT1_LENGTH_256_MBYTES
+
+config BAT1_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT1_ACCESS_NONE
+ default 0x1 if BAT1_ACCESS_RO
+ default 0x2 if BAT1_ACCESS_RW
+
+config BAT1_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+
+config BAT1_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x8 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x10 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x18 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x20 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x28 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x30 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x38 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x40 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x48 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x50 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x58 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x60 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x68 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x70 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x78 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+
+config BAT1_VALID_BITS
+ hex
+ default 0x0 if !BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID
+ default 0x1 if !BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID
+ default 0x2 if BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID
+ default 0x3 if BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID
+
+menuconfig BAT2
+ bool "BAT2"
+
+if BAT2
+
+config BAT2_NAME
+ string "Identifier"
+
+config BAT2_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT2_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT2_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT2_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT2_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT2_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT2_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT2_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT2_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT2_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT2_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT2_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT2_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT2_ACCESS_NONE
+ bool "No access"
+
+config BAT2_ACCESS_RO
+ bool "Read-only"
+
+config BAT2_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT2_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT2_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT2_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT2_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT2_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT2_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT2_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT2_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT2_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT2_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT2_LENGTH
+ hex
+ default 0x00000000 if BAT2_LENGTH_128_KBYTES
+ default 0x00000004 if BAT2_LENGTH_256_KBYTES
+ default 0x0000000c if BAT2_LENGTH_512_KBYTES
+ default 0x0000001c if BAT2_LENGTH_1_MBYTES
+ default 0x0000003c if BAT2_LENGTH_2_MBYTES
+ default 0x0000007c if BAT2_LENGTH_4_MBYTES
+ default 0x000000fc if BAT2_LENGTH_8_MBYTES
+ default 0x000001fc if BAT2_LENGTH_16_MBYTES
+ default 0x000003fc if BAT2_LENGTH_32_MBYTES
+ default 0x000007fc if BAT2_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT2_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT2_LENGTH_256_MBYTES
+
+config BAT2_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT2_ACCESS_NONE
+ default 0x1 if BAT2_ACCESS_RO
+ default 0x2 if BAT2_ACCESS_RW
+
+config BAT2_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+
+config BAT2_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x8 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x10 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x18 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x20 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x28 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x30 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x38 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x40 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x48 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x50 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x58 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x60 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x68 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x70 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x78 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+
+config BAT2_VALID_BITS
+ hex
+ default 0x0 if !BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID
+ default 0x1 if !BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID
+ default 0x2 if BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID
+ default 0x3 if BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID
+
+menuconfig BAT3
+ bool "BAT3"
+
+if BAT3
+
+config BAT3_NAME
+ string "Identifier"
+
+config BAT3_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT3_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT3_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT3_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT3_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT3_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT3_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT3_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT3_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT3_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT3_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT3_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT3_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT3_ACCESS_NONE
+ bool "No access"
+
+config BAT3_ACCESS_RO
+ bool "Read-only"
+
+config BAT3_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT3_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT3_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT3_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT3_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT3_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT3_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT3_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT3_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT3_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT3_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT3_LENGTH
+ hex
+ default 0x00000000 if BAT3_LENGTH_128_KBYTES
+ default 0x00000004 if BAT3_LENGTH_256_KBYTES
+ default 0x0000000c if BAT3_LENGTH_512_KBYTES
+ default 0x0000001c if BAT3_LENGTH_1_MBYTES
+ default 0x0000003c if BAT3_LENGTH_2_MBYTES
+ default 0x0000007c if BAT3_LENGTH_4_MBYTES
+ default 0x000000fc if BAT3_LENGTH_8_MBYTES
+ default 0x000001fc if BAT3_LENGTH_16_MBYTES
+ default 0x000003fc if BAT3_LENGTH_32_MBYTES
+ default 0x000007fc if BAT3_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT3_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT3_LENGTH_256_MBYTES
+
+config BAT3_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT3_ACCESS_NONE
+ default 0x1 if BAT3_ACCESS_RO
+ default 0x2 if BAT3_ACCESS_RW
+
+config BAT3_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+
+config BAT3_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x8 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x10 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x18 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x20 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x28 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x30 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x38 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x40 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x48 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x50 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x58 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x60 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x68 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x70 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x78 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+
+config BAT3_VALID_BITS
+ hex
+ default 0x0 if !BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID
+ default 0x1 if !BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID
+ default 0x2 if BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID
+ default 0x3 if BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID
+
+if HIGH_BATS
+
+menuconfig BAT4
+ bool "BAT4"
+
+if BAT4
+
+config BAT4_NAME
+ string "Identifier"
+
+config BAT4_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT4_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT4_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT4_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT4_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT4_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT4_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT4_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT4_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT4_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT4_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT4_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT4_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT4_ACCESS_NONE
+ bool "No access"
+
+config BAT4_ACCESS_RO
+ bool "Read-only"
+
+config BAT4_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT4_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT4_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT4_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT4_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT4_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT4_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT4_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT4_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT4_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT4_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT4_LENGTH
+ hex
+ default 0x00000000 if BAT4_LENGTH_128_KBYTES
+ default 0x00000004 if BAT4_LENGTH_256_KBYTES
+ default 0x0000000c if BAT4_LENGTH_512_KBYTES
+ default 0x0000001c if BAT4_LENGTH_1_MBYTES
+ default 0x0000003c if BAT4_LENGTH_2_MBYTES
+ default 0x0000007c if BAT4_LENGTH_4_MBYTES
+ default 0x000000fc if BAT4_LENGTH_8_MBYTES
+ default 0x000001fc if BAT4_LENGTH_16_MBYTES
+ default 0x000003fc if BAT4_LENGTH_32_MBYTES
+ default 0x000007fc if BAT4_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT4_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT4_LENGTH_256_MBYTES
+
+config BAT4_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT4_ACCESS_NONE
+ default 0x1 if BAT4_ACCESS_RO
+ default 0x2 if BAT4_ACCESS_RW
+
+config BAT4_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+
+config BAT4_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x8 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x10 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x18 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x20 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x28 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x30 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x38 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x40 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x48 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x50 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x58 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x60 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x68 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x70 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x78 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+
+config BAT4_VALID_BITS
+ hex
+ default 0x0 if !BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID
+ default 0x1 if !BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID
+ default 0x2 if BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID
+ default 0x3 if BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID
+
+menuconfig BAT5
+ bool "BAT5"
+
+if BAT5
+
+config BAT5_NAME
+ string "Identifier"
+
+config BAT5_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT5_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT5_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT5_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT5_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT5_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT5_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT5_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT5_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT5_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT5_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT5_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT5_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT5_ACCESS_NONE
+ bool "No access"
+
+config BAT5_ACCESS_RO
+ bool "Read-only"
+
+config BAT5_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT5_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT5_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT5_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT5_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT5_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT5_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT5_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT5_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT5_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT5_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT5_LENGTH
+ hex
+ default 0x00000000 if BAT5_LENGTH_128_KBYTES
+ default 0x00000004 if BAT5_LENGTH_256_KBYTES
+ default 0x0000000c if BAT5_LENGTH_512_KBYTES
+ default 0x0000001c if BAT5_LENGTH_1_MBYTES
+ default 0x0000003c if BAT5_LENGTH_2_MBYTES
+ default 0x0000007c if BAT5_LENGTH_4_MBYTES
+ default 0x000000fc if BAT5_LENGTH_8_MBYTES
+ default 0x000001fc if BAT5_LENGTH_16_MBYTES
+ default 0x000003fc if BAT5_LENGTH_32_MBYTES
+ default 0x000007fc if BAT5_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT5_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT5_LENGTH_256_MBYTES
+
+config BAT5_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT5_ACCESS_NONE
+ default 0x1 if BAT5_ACCESS_RO
+ default 0x2 if BAT5_ACCESS_RW
+
+config BAT5_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+
+config BAT5_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x8 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x10 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x18 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x20 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x28 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x30 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x38 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x40 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x48 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x50 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x58 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x60 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x68 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x70 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x78 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+
+config BAT5_VALID_BITS
+ hex
+ default 0x0 if !BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID
+ default 0x1 if !BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID
+ default 0x2 if BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID
+ default 0x3 if BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID
+
+menuconfig BAT6
+ bool "BAT6"
+
+if BAT6
+
+config BAT6_NAME
+ string "Identifier"
+
+config BAT6_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT6_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT6_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT6_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT6_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT6_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT6_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT6_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT6_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT6_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT6_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT6_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT6_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT6_ACCESS_NONE
+ bool "No access"
+
+config BAT6_ACCESS_RO
+ bool "Read-only"
+
+config BAT6_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT6_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT6_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT6_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT6_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT6_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT6_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT6_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT6_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT6_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT6_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT6_LENGTH
+ hex
+ default 0x00000000 if BAT6_LENGTH_128_KBYTES
+ default 0x00000004 if BAT6_LENGTH_256_KBYTES
+ default 0x0000000c if BAT6_LENGTH_512_KBYTES
+ default 0x0000001c if BAT6_LENGTH_1_MBYTES
+ default 0x0000003c if BAT6_LENGTH_2_MBYTES
+ default 0x0000007c if BAT6_LENGTH_4_MBYTES
+ default 0x000000fc if BAT6_LENGTH_8_MBYTES
+ default 0x000001fc if BAT6_LENGTH_16_MBYTES
+ default 0x000003fc if BAT6_LENGTH_32_MBYTES
+ default 0x000007fc if BAT6_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT6_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT6_LENGTH_256_MBYTES
+
+config BAT6_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT6_ACCESS_NONE
+ default 0x1 if BAT6_ACCESS_RO
+ default 0x2 if BAT6_ACCESS_RW
+
+config BAT6_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+
+config BAT6_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x8 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x10 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x18 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x20 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x28 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x30 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x38 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x40 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x48 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x50 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x58 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x60 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x68 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x70 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x78 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+
+config BAT6_VALID_BITS
+ hex
+ default 0x0 if !BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID
+ default 0x1 if !BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID
+ default 0x2 if BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID
+ default 0x3 if BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID
+
+menuconfig BAT7
+ bool "BAT7"
+
+if BAT7
+
+config BAT7_NAME
+ string "Identifier"
+
+config BAT7_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT7_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT7_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT7_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT7_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT7_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT7_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT7_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT7_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT7_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT7_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT7_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT7_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT7_ACCESS_NONE
+ bool "No access"
+
+config BAT7_ACCESS_RO
+ bool "Read-only"
+
+config BAT7_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT7_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT7_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT7_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT7_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT7_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT7_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT7_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT7_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT7_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT7_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT7_LENGTH
+ hex
+ default 0x00000000 if BAT7_LENGTH_128_KBYTES
+ default 0x00000004 if BAT7_LENGTH_256_KBYTES
+ default 0x0000000c if BAT7_LENGTH_512_KBYTES
+ default 0x0000001c if BAT7_LENGTH_1_MBYTES
+ default 0x0000003c if BAT7_LENGTH_2_MBYTES
+ default 0x0000007c if BAT7_LENGTH_4_MBYTES
+ default 0x000000fc if BAT7_LENGTH_8_MBYTES
+ default 0x000001fc if BAT7_LENGTH_16_MBYTES
+ default 0x000003fc if BAT7_LENGTH_32_MBYTES
+ default 0x000007fc if BAT7_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT7_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT7_LENGTH_256_MBYTES
+
+config BAT7_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT7_ACCESS_NONE
+ default 0x1 if BAT7_ACCESS_RO
+ default 0x2 if BAT7_ACCESS_RW
+
+config BAT7_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+
+config BAT7_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x8 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x10 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x18 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x20 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x28 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x30 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x38 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x40 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x48 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x50 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x58 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x60 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x68 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x70 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x78 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+
+config BAT7_VALID_BITS
+ hex
+ default 0x0 if !BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID
+ default 0x1 if !BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID
+ default 0x2 if BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID
+ default 0x3 if BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID
+
+endif
+
+endmenu
--- /dev/null
+#ifdef CONFIG_BAT0
+#define CONFIG_SYS_IBAT0L (\
+ (CONFIG_BAT0_BASE) |\
+ (CONFIG_BAT0_PAGE_PROTECTION) |\
+ (CONFIG_BAT0_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT0U (\
+ (CONFIG_BAT0_BASE) |\
+ (CONFIG_BAT0_LENGTH) |\
+ (CONFIG_BAT0_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT0L (\
+ (CONFIG_BAT0_BASE) |\
+ (CONFIG_BAT0_PAGE_PROTECTION) |\
+ (CONFIG_BAT0_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT0U (\
+ (CONFIG_BAT0_BASE) |\
+ (CONFIG_BAT0_LENGTH) |\
+ (CONFIG_BAT0_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT0L (0)
+#define CONFIG_SYS_IBAT0U (0)
+#define CONFIG_SYS_DBAT0L (0)
+#define CONFIG_SYS_DBAT0U (0)
+#endif /* CONFIG_BAT0 */
+
+#ifdef CONFIG_BAT1
+#define CONFIG_SYS_IBAT1L (\
+ (CONFIG_BAT1_BASE) |\
+ (CONFIG_BAT1_PAGE_PROTECTION) |\
+ (CONFIG_BAT1_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT1U (\
+ (CONFIG_BAT1_BASE) |\
+ (CONFIG_BAT1_LENGTH) |\
+ (CONFIG_BAT1_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT1L (\
+ (CONFIG_BAT1_BASE) |\
+ (CONFIG_BAT1_PAGE_PROTECTION) |\
+ (CONFIG_BAT1_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT1U (\
+ (CONFIG_BAT1_BASE) |\
+ (CONFIG_BAT1_LENGTH) |\
+ (CONFIG_BAT1_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT1L (0)
+#define CONFIG_SYS_IBAT1U (0)
+#define CONFIG_SYS_DBAT1L (0)
+#define CONFIG_SYS_DBAT1U (0)
+#endif /* CONFIG_BAT1 */
+
+#ifdef CONFIG_BAT2
+#define CONFIG_SYS_IBAT2L (\
+ (CONFIG_BAT2_BASE) |\
+ (CONFIG_BAT2_PAGE_PROTECTION) |\
+ (CONFIG_BAT2_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT2U (\
+ (CONFIG_BAT2_BASE) |\
+ (CONFIG_BAT2_LENGTH) |\
+ (CONFIG_BAT2_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT2L (\
+ (CONFIG_BAT2_BASE) |\
+ (CONFIG_BAT2_PAGE_PROTECTION) |\
+ (CONFIG_BAT2_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT2U (\
+ (CONFIG_BAT2_BASE) |\
+ (CONFIG_BAT2_LENGTH) |\
+ (CONFIG_BAT2_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT2L (0)
+#define CONFIG_SYS_IBAT2U (0)
+#define CONFIG_SYS_DBAT2L (0)
+#define CONFIG_SYS_DBAT2U (0)
+#endif /* CONFIG_BAT2 */
+
+#ifdef CONFIG_BAT3
+#define CONFIG_SYS_IBAT3L (\
+ (CONFIG_BAT3_BASE) |\
+ (CONFIG_BAT3_PAGE_PROTECTION) |\
+ (CONFIG_BAT3_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT3U (\
+ (CONFIG_BAT3_BASE) |\
+ (CONFIG_BAT3_LENGTH) |\
+ (CONFIG_BAT3_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT3L (\
+ (CONFIG_BAT3_BASE) |\
+ (CONFIG_BAT3_PAGE_PROTECTION) |\
+ (CONFIG_BAT3_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT3U (\
+ (CONFIG_BAT3_BASE) |\
+ (CONFIG_BAT3_LENGTH) |\
+ (CONFIG_BAT3_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT3L (0)
+#define CONFIG_SYS_IBAT3U (0)
+#define CONFIG_SYS_DBAT3L (0)
+#define CONFIG_SYS_DBAT3U (0)
+#endif /* CONFIG_BAT3 */
+
+#ifdef CONFIG_BAT4
+#define CONFIG_SYS_IBAT4L (\
+ (CONFIG_BAT4_BASE) |\
+ (CONFIG_BAT4_PAGE_PROTECTION) |\
+ (CONFIG_BAT4_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT4U (\
+ (CONFIG_BAT4_BASE) |\
+ (CONFIG_BAT4_LENGTH) |\
+ (CONFIG_BAT4_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT4L (\
+ (CONFIG_BAT4_BASE) |\
+ (CONFIG_BAT4_PAGE_PROTECTION) |\
+ (CONFIG_BAT4_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT4U (\
+ (CONFIG_BAT4_BASE) |\
+ (CONFIG_BAT4_LENGTH) |\
+ (CONFIG_BAT4_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT4L (0)
+#define CONFIG_SYS_IBAT4U (0)
+#define CONFIG_SYS_DBAT4L (0)
+#define CONFIG_SYS_DBAT4U (0)
+#endif /* CONFIG_BAT4 */
+
+#ifdef CONFIG_BAT5
+#define CONFIG_SYS_IBAT5L (\
+ (CONFIG_BAT5_BASE) |\
+ (CONFIG_BAT5_PAGE_PROTECTION) |\
+ (CONFIG_BAT5_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT5U (\
+ (CONFIG_BAT5_BASE) |\
+ (CONFIG_BAT5_LENGTH) |\
+ (CONFIG_BAT5_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT5L (\
+ (CONFIG_BAT5_BASE) |\
+ (CONFIG_BAT5_PAGE_PROTECTION) |\
+ (CONFIG_BAT5_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT5U (\
+ (CONFIG_BAT5_BASE) |\
+ (CONFIG_BAT5_LENGTH) |\
+ (CONFIG_BAT5_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT5L (0)
+#define CONFIG_SYS_IBAT5U (0)
+#define CONFIG_SYS_DBAT5L (0)
+#define CONFIG_SYS_DBAT5U (0)
+#endif /* CONFIG_BAT5 */
+
+#ifdef CONFIG_BAT6
+#define CONFIG_SYS_IBAT6L (\
+ (CONFIG_BAT6_BASE) |\
+ (CONFIG_BAT6_PAGE_PROTECTION) |\
+ (CONFIG_BAT6_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT6U (\
+ (CONFIG_BAT6_BASE) |\
+ (CONFIG_BAT6_LENGTH) |\
+ (CONFIG_BAT6_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT6L (\
+ (CONFIG_BAT6_BASE) |\
+ (CONFIG_BAT6_PAGE_PROTECTION) |\
+ (CONFIG_BAT6_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT6U (\
+ (CONFIG_BAT6_BASE) |\
+ (CONFIG_BAT6_LENGTH) |\
+ (CONFIG_BAT6_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT6L (0)
+#define CONFIG_SYS_IBAT6U (0)
+#define CONFIG_SYS_DBAT6L (0)
+#define CONFIG_SYS_DBAT6U (0)
+#endif /* CONFIG_BAT6 */
+
+#ifdef CONFIG_BAT7
+#define CONFIG_SYS_IBAT7L (\
+ (CONFIG_BAT7_BASE) |\
+ (CONFIG_BAT7_PAGE_PROTECTION) |\
+ (CONFIG_BAT7_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT7U (\
+ (CONFIG_BAT7_BASE) |\
+ (CONFIG_BAT7_LENGTH) |\
+ (CONFIG_BAT7_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT7L (\
+ (CONFIG_BAT7_BASE) |\
+ (CONFIG_BAT7_PAGE_PROTECTION) |\
+ (CONFIG_BAT7_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT7U (\
+ (CONFIG_BAT7_BASE) |\
+ (CONFIG_BAT7_LENGTH) |\
+ (CONFIG_BAT7_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L (0)
+#define CONFIG_SYS_DBAT7U (0)
+#endif /* CONFIG_BAT7 */
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
-#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
#include <linux/immap_qe.h>
#include <asm/io.h>
#endif
#ifdef MPC83xx_RESET
/* Interrupts and MMU off */
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
- msr &= ~( MSR_EE | MSR_IR | MSR_DR);
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+ msr = mfmsr();
+ msr &= ~(MSR_EE | MSR_IR | MSR_DR);
+ mtmsr(msr);
/* enable Reset Control Reg */
immap->reset.rpr = 0x52535445;
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+ sync();
+ isync();
/* confirm Reset Control Reg is enabled */
- while(!((immap->reset.rcer) & RCER_CRE));
+ while(!((immap->reset.rcer) & RCER_CRE))
+ ;
udelay(200);
immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
/* Interrupts and MMU off */
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
+ msr = mfmsr();
msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+ mtmsr(msr);
/*
* Trying to execute the next instruction at a non-existing address
}
#endif
+#ifndef CONFIG_DM_ETH
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
#endif
return 0;
}
+#endif /* !CONFIG_DM_ETH */
/*
* Initializes on-chip MMC controllers.
return 0;
#endif
}
+
+void ppcDWstore(unsigned int *addr, unsigned int *value)
+{
+ asm("lfd 1, 0(%1)\n\t"
+ "stfd 1, 0(%0)"
+ :
+ : "r" (addr), "r" (value)
+ : "memory");
+}
+
+void ppcDWload(unsigned int *addr, unsigned int *ret)
+{
+ asm("lfd 1, 0(%0)\n\t"
+ "stfd 1, 0(%1)"
+ :
+ : "r" (addr), "r" (ret)
+ : "memory");
+}
#include <usb/ehci-ci.h>
#endif
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+#include "sysio/sysio.h"
+#include "arbiter/arbiter.h"
+#include "initreg/initreg.h"
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_QE
*/
void cpu_init_f (volatile immap_t * im)
{
- __be32 acr_mask =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- ACR_PIPE_DEP |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- ACR_RPTCNT |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- ACR_APARK |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- ACR_PARKM |
-#endif
- 0;
- __be32 acr_val =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
-#endif
- 0;
- __be32 spcr_mask =
-#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
- SPCR_OPT |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
- SPCR_TSECEP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
- SPCR_TSEC1EP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
- SPCR_TSEC2EP |
-#endif
- 0;
- __be32 spcr_val =
-#ifdef CONFIG_SYS_SPCR_OPT
- (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
- (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
- (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
- (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
-#endif
- 0;
__be32 sccr_mask =
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
SCCR_ENCCM |
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
-#endif
- 0;
- __be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
- LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- LCRR_CLKDIV |
-#endif
- 0;
- __be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
- CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- CONFIG_SYS_LCRR_CLKDIV |
#endif
0;
/* System General Purpose Register */
#ifdef CONFIG_SYS_SICRH
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
&im->sysconf.sicrh);
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
-#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
+#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
uint32_t temp;
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
}
ddr->err_disable = val;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
return 0;
} else if (strcmp(argv[1], "errdetectclr") == 0) {
val = ddr->err_detect;
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
return 0;
} else if (strcmp(argv[1], "mirror") == 0) {
val = ddr->ecc_err_inject;
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* write memory location injecting errors */
ppcDWstore((u32 *) i, pattern);
- __asm__ __volatile__("sync");
+ sync();
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* read data, this generates ECC error */
ppcDWload((u32 *) i, ret);
- __asm__ __volatile__("sync");
+ sync();
/* re-initialize memory, double word write the location again,
* generates new ECC code this time */
ppcDWstore((u32 *) i, writeback);
- __asm__ __volatile__("sync");
+ sync();
}
enable_interrupts();
return 0;
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* write memory location injecting errors */
*(u32 *) i = 0xfedcba98UL;
- __asm__ __volatile__("sync");
+ sync();
/* sub double word write,
* bus will read-modify-write,
* generates ECC error */
*((u32 *) i + 1) = 0x76543210UL;
- __asm__ __volatile__("sync");
+ sync();
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* re-initialize memory,
* double word write the location again,
* generates new ECC code this time */
ppcDWstore((u32 *) i, writeback);
- __asm__ __volatile__("sync");
+ sync();
}
enable_interrupts();
return 0;
--- /dev/null
+menu "ELBC register setup"
+
+choice
+ prompt "OR/BR for NAND SPL"
+
+config ELBC_BR_OR_NAND_PRELIM_NONE
+ bool "None"
+
+config ELBC_BR_OR_NAND_PRELIM_0
+ bool "0"
+
+config ELBC_BR_OR_NAND_PRELIM_1
+ bool "1"
+
+config ELBC_BR_OR_NAND_PRELIM_2
+ bool "2"
+
+config ELBC_BR_OR_NAND_PRELIM_3
+ bool "3"
+
+config ELBC_BR_OR_NAND_PRELIM_4
+ bool "4"
+
+endchoice
+
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4"
+
+endmenu
--- /dev/null
+menuconfig ELBC_BR0_OR0
+ bool "ELBC BR0/OR0"
+
+if ELBC_BR0_OR0
+
+config BR0_OR0_NAME
+ string "Identifier"
+
+config BR0_OR0_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR0_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR0_PORTSIZE_16BIT
+ depends on !BR0_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR0_PORTSIZE_32BIT
+ depends on !BR0_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR0_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR0_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR0_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR0_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR0_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR0_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR0_MACHINE_GPCM
+ bool "GPCM"
+
+config BR0_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR0_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR0_MACHINE_UPMA
+ select BR0_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR0_MACHINE_UPMB
+ select BR0_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR0_MACHINE_UPMC
+ select BR0_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR0_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR0_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR0_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR0_AM_32_KBYTES
+ depends on !BR0_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR0_AM_64_KBYTES
+ bool "64 kb"
+
+config OR0_AM_128_KBYTES
+ bool "128 kb"
+
+config OR0_AM_256_KBYTES
+ bool "256 kb"
+
+config OR0_AM_512_KBYTES
+ bool "512 kb"
+
+config OR0_AM_1_MBYTES
+ bool "1 mb"
+
+config OR0_AM_2_MBYTES
+ bool "2 mb"
+
+config OR0_AM_4_MBYTES
+ bool "4 mb"
+
+config OR0_AM_8_MBYTES
+ bool "8 mb"
+
+config OR0_AM_16_MBYTES
+ bool "16 mb"
+
+config OR0_AM_32_MBYTES
+ bool "32 mb"
+
+config OR0_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_256_MBYTES
+ bool "256 mb"
+
+config OR0_AM_512_MBYTES
+ depends on BR0_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_1_GBYTES
+ bool "1 gb"
+
+config OR0_AM_2_GBYTES
+ depends on BR0_MACHINE_FCM
+ bool "2 gb"
+
+config OR0_AM_4_GBYTES
+ depends on BR0_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR0_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR0_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR0_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR0_MACHINE_GPCM || BR0_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR0_SCY_0
+ bool "No wait states"
+
+config OR0_SCY_1
+ bool "1 wait state"
+
+config OR0_SCY_2
+ bool "2 wait states"
+
+config OR0_SCY_3
+ bool "3 wait states"
+
+config OR0_SCY_4
+ bool "4 wait states"
+
+config OR0_SCY_5
+ bool "5 wait states"
+
+config OR0_SCY_6
+ bool "6 wait states"
+
+config OR0_SCY_7
+ bool "7 wait states"
+
+config OR0_SCY_8
+ depends on BR0_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR0_SCY_9
+ depends on BR0_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR0_SCY_10
+ depends on BR0_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR0_SCY_11
+ depends on BR0_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR0_SCY_12
+ depends on BR0_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR0_SCY_13
+ depends on BR0_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR0_SCY_14
+ depends on BR0_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR0_SCY_15
+ depends on BR0_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM
+
+if BR0_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR0_CSNT_NORMAL
+ bool "Normal"
+
+config OR0_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR0_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR0_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR0_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR0_XACS_NORMAL
+ bool "Normal"
+
+config OR0_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR0_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR0_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR0_MACHINE_GPCM
+
+if BR0_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR0_PGS_SMALL
+ bool "Small page device"
+
+config OR0_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR0_CSCT_1_CYCLE
+ depends on OR0_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR0_CSCT_2_CYCLE
+ depends on OR0_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR0_CSCT_4_CYCLE
+ depends on OR0_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR0_CSCT_8_CYCLE
+ depends on OR0_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR0_CST_COINCIDENT
+ depends on OR0_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR0_CST_QUARTER_CLOCK
+ depends on OR0_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR0_CST_HALF_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR0_CST_ONE_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR0_CHT_HALF_CLOCK
+ depends on OR0_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR0_CHT_ONE_CLOCK
+ depends on OR0_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR0_CHT_ONE_HALF_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR0_CHT_TWO_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR0_RST_THREE_QUARTER_CLOCK
+ depends on OR0_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR0_RST_ONE_HALF_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR0_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR0_MACHINE_FCM
+
+if BR0_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR0_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR0_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR0_MACHINE_UPM
+
+if BR0_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR0_COLS_7
+ bool "7"
+
+config OR0_COLS_8
+ bool "8"
+
+config OR0_COLS_9
+ bool "9"
+
+config OR0_COLS_10
+ bool "10"
+
+config OR0_COLS_11
+ bool "11"
+
+config OR0_COLS_12
+ bool "12"
+
+config OR0_COLS_13
+ bool "13"
+
+config OR0_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR0_ROWS_9
+ bool "9"
+
+config OR0_ROWS_10
+ bool "10"
+
+config OR0_ROWS_11
+ bool "11"
+
+config OR0_ROWS_12
+ bool "12"
+
+config OR0_ROWS_13
+ bool "13"
+
+config OR0_ROWS_14
+ bool "14"
+
+config OR0_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR0_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR0_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR0_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR0_TRLX_NORMAL
+ bool "Normal"
+
+config OR0_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR0_EHTR_NORMAL
+ depends on OR0_TRLX_NORMAL
+ bool "Normal"
+
+config OR0_EHTR_1_CYCLE
+ depends on OR0_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR0_EHTR_4_CYCLE
+ depends on OR0_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR0_EHTR_8_CYCLE
+ depends on OR0_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR0_EAD_NONE
+ bool "None"
+
+config OR0_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR0_OR0
+
+config BR0_PORTSIZE
+ hex
+ default 0x800 if BR0_PORTSIZE_8BIT
+ default 0x1000 if BR0_PORTSIZE_16BIT
+ default 0x1800 if BR0_PORTSIZE_32BIT
+
+config BR0_ERRORCHECKING
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if BR0_ERRORCHECKING_DISABLED
+ default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR0_ERRORCHECKING_BOTH
+
+config BR0_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR0_WRITE_PROTECT
+ default 0x100 if BR0_WRITE_PROTECT
+
+config BR0_MACHINE
+ hex
+ default 0x0 if BR0_MACHINE_GPCM
+ default 0x20 if BR0_MACHINE_FCM
+ default 0x60 if BR0_MACHINE_SDRAM
+ default 0x80 if BR0_MACHINE_UPMA
+ default 0xa0 if BR0_MACHINE_UPMB
+ default 0xc0 if BR0_MACHINE_UPMC
+
+config BR0_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR0_ATOMIC_NONE
+ default 0x4 if BR0_ATOMIC_RAWA
+ default 0x8 if BR0_ATOMIC_WARA
+
+config BR0_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR0_OR0
+ default 0x1 if ELBC_BR0_OR0
+
+config OR0_AM
+ hex
+ default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM
+ default 0xffff0000 if OR0_AM_64_KBYTES
+ default 0xfffe0000 if OR0_AM_128_KBYTES
+ default 0xfffc0000 if OR0_AM_256_KBYTES
+ default 0xfff80000 if OR0_AM_512_KBYTES
+ default 0xfff00000 if OR0_AM_1_MBYTES
+ default 0xffe00000 if OR0_AM_2_MBYTES
+ default 0xffc00000 if OR0_AM_4_MBYTES
+ default 0xff800000 if OR0_AM_8_MBYTES
+ default 0xff000000 if OR0_AM_16_MBYTES
+ default 0xfe000000 if OR0_AM_32_MBYTES
+ default 0xfc000000 if OR0_AM_64_MBYTES
+ default 0xf8000000 if OR0_AM_128_MBYTES
+ default 0xf0000000 if OR0_AM_256_MBYTES
+ default 0xe0000000 if OR0_AM_512_MBYTES
+ default 0xc0000000 if OR0_AM_1_GBYTES
+ default 0x80000000 if OR0_AM_2_GBYTES
+ default 0x00000000 if OR0_AM_4_GBYTES
+
+config OR0_XAM
+ hex
+ default 0x0 if !OR0_XAM_SET
+ default 0x6000 if OR0_XAM_SET
+
+config OR0_BCTLD
+ hex
+ default 0x0 if OR0_BCTLD_ASSERTED
+ default 0x1000 if OR0_BCTLD_NOT_ASSERTED
+
+config OR0_BI
+ hex
+ default 0x0 if !BR0_MACHINE_UPM
+ default 0x0 if OR0_BI_BURSTSUPPORT
+ default 0x100 if OR0_BI_BURSTINHIBIT
+
+config OR0_COLS
+ hex
+ default 0x0 if !BR0_MACHINE_SDRAM
+ default 0x0 if OR0_COLS_7
+ default 0x400 if OR0_COLS_8
+ default 0x800 if OR0_COLS_9
+ default 0xc00 if OR0_COLS_10
+ default 0x1000 if OR0_COLS_11
+ default 0x1400 if OR0_COLS_12
+ default 0x1800 if OR0_COLS_13
+ default 0x1c00 if OR0_COLS_14
+
+config OR0_ROWS
+ hex
+ default 0x0 if !BR0_MACHINE_SDRAM
+ default 0x0 if OR0_ROWS_9
+ default 0x40 if OR0_ROWS_10
+ default 0x80 if OR0_ROWS_11
+ default 0xc0 if OR0_ROWS_12
+ default 0x100 if OR0_ROWS_13
+ default 0x140 if OR0_ROWS_14
+ default 0x180 if OR0_ROWS_15
+
+config OR0_PMSEL
+ hex
+ default 0x0 if !BR0_MACHINE_SDRAM
+ default 0x0 if OR0_PMSEL_BTB
+ default 0x20 if OR0_PMSEL_KEPT_OPEN
+
+config OR0_SCY
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM
+ default 0x0 if OR0_SCY_0
+ default 0x10 if OR0_SCY_1
+ default 0x20 if OR0_SCY_2
+ default 0x30 if OR0_SCY_3
+ default 0x40 if OR0_SCY_4
+ default 0x50 if OR0_SCY_5
+ default 0x60 if OR0_SCY_6
+ default 0x70 if OR0_SCY_7
+ default 0x80 if OR0_SCY_8
+ default 0x90 if OR0_SCY_9
+ default 0xa0 if OR0_SCY_10
+ default 0xb0 if OR0_SCY_11
+ default 0xc0 if OR0_SCY_12
+ default 0xd0 if OR0_SCY_13
+ default 0xe0 if OR0_SCY_14
+ default 0xf0 if OR0_SCY_15
+
+config OR0_PGS
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_PGS_SMALL
+ default 0x400 if OR0_PGS_LARGE
+
+config OR0_CSCT
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_CSCT_1_CYCLE
+ default 0x0 if OR0_CSCT_2_CYCLE
+ default 0x200 if OR0_CSCT_4_CYCLE
+ default 0x200 if OR0_CSCT_8_CYCLE
+
+config OR0_CST
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_CST_COINCIDENT
+ default 0x100 if OR0_CST_QUARTER_CLOCK
+ default 0x0 if OR0_CST_HALF_CLOCK
+ default 0x100 if OR0_CST_ONE_CLOCK
+
+config OR0_CHT
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_CHT_HALF_CLOCK
+ default 0x80 if OR0_CHT_ONE_CLOCK
+ default 0x0 if OR0_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR0_CHT_TWO_CLOCK
+
+config OR0_RST
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR0_RST_ONE_CLOCK
+ default 0x0 if OR0_RST_ONE_HALF_CLOCK
+
+config OR0_CSNT
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM
+ default 0x0 if OR0_CSNT_NORMAL
+ default 0x800 if OR0_CSNT_EARLIER
+
+config OR0_ACS
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM
+ default 0x0 if OR0_ACS_SAME_TIME
+ default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER
+
+config OR0_XACS
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM
+ default 0x0 if OR0_XACS_NORMAL
+ default 0x100 if OR0_XACS_EXTENDED
+
+config OR0_SETA
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM
+ default 0x0 if OR0_SETA_INTERNAL
+ default 0x8 if OR0_SETA_EXTERNAL
+
+config OR0_TRLX
+ hex
+ default 0x0 if OR0_TRLX_NORMAL
+ default 0x4 if OR0_TRLX_RELAXED
+
+config OR0_EHTR
+ hex
+ default 0x0 if OR0_EHTR_NORMAL
+ default 0x2 if OR0_EHTR_1_CYCLE
+ default 0x0 if OR0_EHTR_4_CYCLE
+ default 0x2 if OR0_EHTR_8_CYCLE
+
+config OR0_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR0_EAD_NONE
+ default 0x1 if OR0_EAD_EXTRA
--- /dev/null
+menuconfig ELBC_BR1_OR1
+ bool "ELBC BR1/OR1"
+
+if ELBC_BR1_OR1
+
+config BR1_OR1_NAME
+ string "Identifier"
+
+config BR1_OR1_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR1_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR1_PORTSIZE_16BIT
+ depends on !BR1_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR1_PORTSIZE_32BIT
+ depends on !BR1_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR1_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR1_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR1_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR1_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR1_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR1_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR1_MACHINE_GPCM
+ bool "GPCM"
+
+config BR1_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR1_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR1_MACHINE_UPMA
+ select BR1_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR1_MACHINE_UPMB
+ select BR1_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR1_MACHINE_UPMC
+ select BR1_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR1_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR1_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR1_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR1_AM_32_KBYTES
+ depends on !BR1_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR1_AM_64_KBYTES
+ bool "64 kb"
+
+config OR1_AM_128_KBYTES
+ bool "128 kb"
+
+config OR1_AM_256_KBYTES
+ bool "256 kb"
+
+config OR1_AM_512_KBYTES
+ bool "512 kb"
+
+config OR1_AM_1_MBYTES
+ bool "1 mb"
+
+config OR1_AM_2_MBYTES
+ bool "2 mb"
+
+config OR1_AM_4_MBYTES
+ bool "4 mb"
+
+config OR1_AM_8_MBYTES
+ bool "8 mb"
+
+config OR1_AM_16_MBYTES
+ bool "16 mb"
+
+config OR1_AM_32_MBYTES
+ bool "32 mb"
+
+config OR1_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_256_MBYTES
+ bool "256 mb"
+
+config OR1_AM_512_MBYTES
+ depends on BR1_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_1_GBYTES
+ bool "1 gb"
+
+config OR1_AM_2_GBYTES
+ depends on BR1_MACHINE_FCM
+ bool "2 gb"
+
+config OR1_AM_4_GBYTES
+ depends on BR1_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR1_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR1_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR1_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR1_MACHINE_GPCM || BR1_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR1_SCY_0
+ bool "No wait states"
+
+config OR1_SCY_1
+ bool "1 wait state"
+
+config OR1_SCY_2
+ bool "2 wait states"
+
+config OR1_SCY_3
+ bool "3 wait states"
+
+config OR1_SCY_4
+ bool "4 wait states"
+
+config OR1_SCY_5
+ bool "5 wait states"
+
+config OR1_SCY_6
+ bool "6 wait states"
+
+config OR1_SCY_7
+ bool "7 wait states"
+
+config OR1_SCY_8
+ depends on BR1_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR1_SCY_9
+ depends on BR1_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR1_SCY_10
+ depends on BR1_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR1_SCY_11
+ depends on BR1_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR1_SCY_12
+ depends on BR1_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR1_SCY_13
+ depends on BR1_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR1_SCY_14
+ depends on BR1_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR1_SCY_15
+ depends on BR1_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM
+
+if BR1_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR1_CSNT_NORMAL
+ bool "Normal"
+
+config OR1_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR1_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR1_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR1_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR1_XACS_NORMAL
+ bool "Normal"
+
+config OR1_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR1_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR1_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR1_MACHINE_GPCM
+
+if BR1_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR1_PGS_SMALL
+ bool "Small page device"
+
+config OR1_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR1_CSCT_1_CYCLE
+ depends on OR1_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR1_CSCT_2_CYCLE
+ depends on OR1_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR1_CSCT_4_CYCLE
+ depends on OR1_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR1_CSCT_8_CYCLE
+ depends on OR1_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR1_CST_COINCIDENT
+ depends on OR1_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR1_CST_QUARTER_CLOCK
+ depends on OR1_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR1_CST_HALF_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR1_CST_ONE_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR1_CHT_HALF_CLOCK
+ depends on OR1_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR1_CHT_ONE_CLOCK
+ depends on OR1_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR1_CHT_ONE_HALF_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR1_CHT_TWO_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR1_RST_THREE_QUARTER_CLOCK
+ depends on OR1_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR1_RST_ONE_HALF_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR1_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR1_MACHINE_FCM
+
+if BR1_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR1_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR1_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR1_MACHINE_UPM
+
+if BR1_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR1_COLS_7
+ bool "7"
+
+config OR1_COLS_8
+ bool "8"
+
+config OR1_COLS_9
+ bool "9"
+
+config OR1_COLS_10
+ bool "10"
+
+config OR1_COLS_11
+ bool "11"
+
+config OR1_COLS_12
+ bool "12"
+
+config OR1_COLS_13
+ bool "13"
+
+config OR1_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR1_ROWS_9
+ bool "9"
+
+config OR1_ROWS_10
+ bool "10"
+
+config OR1_ROWS_11
+ bool "11"
+
+config OR1_ROWS_12
+ bool "12"
+
+config OR1_ROWS_13
+ bool "13"
+
+config OR1_ROWS_14
+ bool "14"
+
+config OR1_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR1_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR1_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR1_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR1_TRLX_NORMAL
+ bool "Normal"
+
+config OR1_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR1_EHTR_NORMAL
+ depends on OR1_TRLX_NORMAL
+ bool "Normal"
+
+config OR1_EHTR_1_CYCLE
+ depends on OR1_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR1_EHTR_4_CYCLE
+ depends on OR1_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR1_EHTR_8_CYCLE
+ depends on OR1_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR1_EAD_NONE
+ bool "None"
+
+config OR1_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR1_OR1
+
+config BR1_PORTSIZE
+ hex
+ default 0x800 if BR1_PORTSIZE_8BIT
+ default 0x1000 if BR1_PORTSIZE_16BIT
+ default 0x1800 if BR1_PORTSIZE_32BIT
+
+config BR1_ERRORCHECKING
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if BR1_ERRORCHECKING_DISABLED
+ default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR1_ERRORCHECKING_BOTH
+
+config BR1_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR1_WRITE_PROTECT
+ default 0x100 if BR1_WRITE_PROTECT
+
+config BR1_MACHINE
+ hex
+ default 0x0 if BR1_MACHINE_GPCM
+ default 0x20 if BR1_MACHINE_FCM
+ default 0x60 if BR1_MACHINE_SDRAM
+ default 0x80 if BR1_MACHINE_UPMA
+ default 0xa0 if BR1_MACHINE_UPMB
+ default 0xc0 if BR1_MACHINE_UPMC
+
+config BR1_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR1_ATOMIC_NONE
+ default 0x4 if BR1_ATOMIC_RAWA
+ default 0x8 if BR1_ATOMIC_WARA
+
+config BR1_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR1_OR1
+ default 0x1 if ELBC_BR1_OR1
+
+config OR1_AM
+ hex
+ default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM
+ default 0xffff0000 if OR1_AM_64_KBYTES
+ default 0xfffe0000 if OR1_AM_128_KBYTES
+ default 0xfffc0000 if OR1_AM_256_KBYTES
+ default 0xfff80000 if OR1_AM_512_KBYTES
+ default 0xfff00000 if OR1_AM_1_MBYTES
+ default 0xffe00000 if OR1_AM_2_MBYTES
+ default 0xffc00000 if OR1_AM_4_MBYTES
+ default 0xff800000 if OR1_AM_8_MBYTES
+ default 0xff000000 if OR1_AM_16_MBYTES
+ default 0xfe000000 if OR1_AM_32_MBYTES
+ default 0xfc000000 if OR1_AM_64_MBYTES
+ default 0xf8000000 if OR1_AM_128_MBYTES
+ default 0xf0000000 if OR1_AM_256_MBYTES
+ default 0xe0000000 if OR1_AM_512_MBYTES
+ default 0xc0000000 if OR1_AM_1_GBYTES
+ default 0x80000000 if OR1_AM_2_GBYTES
+ default 0x00000000 if OR1_AM_4_GBYTES
+
+config OR1_XAM
+ hex
+ default 0x0 if !OR1_XAM_SET
+ default 0x6000 if OR1_XAM_SET
+
+config OR1_BCTLD
+ hex
+ default 0x0 if OR1_BCTLD_ASSERTED
+ default 0x1000 if OR1_BCTLD_NOT_ASSERTED
+
+config OR1_BI
+ hex
+ default 0x0 if !BR1_MACHINE_UPM
+ default 0x0 if OR1_BI_BURSTSUPPORT
+ default 0x100 if OR1_BI_BURSTINHIBIT
+
+config OR1_COLS
+ hex
+ default 0x0 if !BR1_MACHINE_SDRAM
+ default 0x0 if OR1_COLS_7
+ default 0x400 if OR1_COLS_8
+ default 0x800 if OR1_COLS_9
+ default 0xc00 if OR1_COLS_10
+ default 0x1000 if OR1_COLS_11
+ default 0x1400 if OR1_COLS_12
+ default 0x1800 if OR1_COLS_13
+ default 0x1c00 if OR1_COLS_14
+
+config OR1_ROWS
+ hex
+ default 0x0 if !BR1_MACHINE_SDRAM
+ default 0x0 if OR1_ROWS_9
+ default 0x40 if OR1_ROWS_10
+ default 0x80 if OR1_ROWS_11
+ default 0xc0 if OR1_ROWS_12
+ default 0x100 if OR1_ROWS_13
+ default 0x140 if OR1_ROWS_14
+ default 0x180 if OR1_ROWS_15
+
+config OR1_PMSEL
+ hex
+ default 0x0 if !BR1_MACHINE_SDRAM
+ default 0x0 if OR1_PMSEL_BTB
+ default 0x20 if OR1_PMSEL_KEPT_OPEN
+
+config OR1_SCY
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM
+ default 0x0 if OR1_SCY_0
+ default 0x10 if OR1_SCY_1
+ default 0x20 if OR1_SCY_2
+ default 0x30 if OR1_SCY_3
+ default 0x40 if OR1_SCY_4
+ default 0x50 if OR1_SCY_5
+ default 0x60 if OR1_SCY_6
+ default 0x70 if OR1_SCY_7
+ default 0x80 if OR1_SCY_8
+ default 0x90 if OR1_SCY_9
+ default 0xa0 if OR1_SCY_10
+ default 0xb0 if OR1_SCY_11
+ default 0xc0 if OR1_SCY_12
+ default 0xd0 if OR1_SCY_13
+ default 0xe0 if OR1_SCY_14
+ default 0xf0 if OR1_SCY_15
+
+config OR1_PGS
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_PGS_SMALL
+ default 0x400 if OR1_PGS_LARGE
+
+config OR1_CSCT
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_CSCT_1_CYCLE
+ default 0x0 if OR1_CSCT_2_CYCLE
+ default 0x200 if OR1_CSCT_4_CYCLE
+ default 0x200 if OR1_CSCT_8_CYCLE
+
+config OR1_CST
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_CST_COINCIDENT
+ default 0x100 if OR1_CST_QUARTER_CLOCK
+ default 0x0 if OR1_CST_HALF_CLOCK
+ default 0x100 if OR1_CST_ONE_CLOCK
+
+config OR1_CHT
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_CHT_HALF_CLOCK
+ default 0x80 if OR1_CHT_ONE_CLOCK
+ default 0x0 if OR1_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR1_CHT_TWO_CLOCK
+
+config OR1_RST
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR1_RST_ONE_CLOCK
+ default 0x0 if OR1_RST_ONE_HALF_CLOCK
+
+config OR1_CSNT
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM
+ default 0x0 if OR1_CSNT_NORMAL
+ default 0x800 if OR1_CSNT_EARLIER
+
+config OR1_ACS
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM
+ default 0x0 if OR1_ACS_SAME_TIME
+ default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER
+
+config OR1_XACS
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM
+ default 0x0 if OR1_XACS_NORMAL
+ default 0x100 if OR1_XACS_EXTENDED
+
+config OR1_SETA
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM
+ default 0x0 if OR1_SETA_INTERNAL
+ default 0x8 if OR1_SETA_EXTERNAL
+
+config OR1_TRLX
+ hex
+ default 0x0 if OR1_TRLX_NORMAL
+ default 0x4 if OR1_TRLX_RELAXED
+
+config OR1_EHTR
+ hex
+ default 0x0 if OR1_EHTR_NORMAL
+ default 0x2 if OR1_EHTR_1_CYCLE
+ default 0x0 if OR1_EHTR_4_CYCLE
+ default 0x2 if OR1_EHTR_8_CYCLE
+
+config OR1_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR1_EAD_NONE
+ default 0x1 if OR1_EAD_EXTRA
--- /dev/null
+menuconfig ELBC_BR2_OR2
+ bool "ELBC BR2/OR2"
+
+if ELBC_BR2_OR2
+
+config BR2_OR2_NAME
+ string "Identifier"
+
+config BR2_OR2_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR2_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR2_PORTSIZE_16BIT
+ depends on !BR2_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR2_PORTSIZE_32BIT
+ depends on !BR2_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR2_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR2_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR2_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR2_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR2_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR2_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR2_MACHINE_GPCM
+ bool "GPCM"
+
+config BR2_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR2_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR2_MACHINE_UPMA
+ select BR2_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR2_MACHINE_UPMB
+ select BR2_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR2_MACHINE_UPMC
+ select BR2_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR2_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR2_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR2_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR2_AM_32_KBYTES
+ depends on !BR2_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR2_AM_64_KBYTES
+ bool "64 kb"
+
+config OR2_AM_128_KBYTES
+ bool "128 kb"
+
+config OR2_AM_256_KBYTES
+ bool "256 kb"
+
+config OR2_AM_512_KBYTES
+ bool "512 kb"
+
+config OR2_AM_1_MBYTES
+ bool "1 mb"
+
+config OR2_AM_2_MBYTES
+ bool "2 mb"
+
+config OR2_AM_4_MBYTES
+ bool "4 mb"
+
+config OR2_AM_8_MBYTES
+ bool "8 mb"
+
+config OR2_AM_16_MBYTES
+ bool "16 mb"
+
+config OR2_AM_32_MBYTES
+ bool "32 mb"
+
+config OR2_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_256_MBYTES
+ bool "256 mb"
+
+config OR2_AM_512_MBYTES
+ depends on BR2_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_1_GBYTES
+ bool "1 gb"
+
+config OR2_AM_2_GBYTES
+ depends on BR2_MACHINE_FCM
+ bool "2 gb"
+
+config OR2_AM_4_GBYTES
+ depends on BR2_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR2_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR2_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR2_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR2_MACHINE_GPCM || BR2_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR2_SCY_0
+ bool "No wait states"
+
+config OR2_SCY_1
+ bool "1 wait state"
+
+config OR2_SCY_2
+ bool "2 wait states"
+
+config OR2_SCY_3
+ bool "3 wait states"
+
+config OR2_SCY_4
+ bool "4 wait states"
+
+config OR2_SCY_5
+ bool "5 wait states"
+
+config OR2_SCY_6
+ bool "6 wait states"
+
+config OR2_SCY_7
+ bool "7 wait states"
+
+config OR2_SCY_8
+ depends on BR2_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR2_SCY_9
+ depends on BR2_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR2_SCY_10
+ depends on BR2_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR2_SCY_11
+ depends on BR2_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR2_SCY_12
+ depends on BR2_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR2_SCY_13
+ depends on BR2_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR2_SCY_14
+ depends on BR2_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR2_SCY_15
+ depends on BR2_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM
+
+if BR2_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR2_CSNT_NORMAL
+ bool "Normal"
+
+config OR2_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR2_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR2_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR2_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR2_XACS_NORMAL
+ bool "Normal"
+
+config OR2_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR2_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR2_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR2_MACHINE_GPCM
+
+if BR2_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR2_PGS_SMALL
+ bool "Small page device"
+
+config OR2_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR2_CSCT_1_CYCLE
+ depends on OR2_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR2_CSCT_2_CYCLE
+ depends on OR2_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR2_CSCT_4_CYCLE
+ depends on OR2_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR2_CSCT_8_CYCLE
+ depends on OR2_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR2_CST_COINCIDENT
+ depends on OR2_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR2_CST_QUARTER_CLOCK
+ depends on OR2_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR2_CST_HALF_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR2_CST_ONE_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR2_CHT_HALF_CLOCK
+ depends on OR2_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR2_CHT_ONE_CLOCK
+ depends on OR2_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR2_CHT_ONE_HALF_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR2_CHT_TWO_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR2_RST_THREE_QUARTER_CLOCK
+ depends on OR2_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR2_RST_ONE_HALF_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR2_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR2_MACHINE_FCM
+
+if BR2_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR2_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR2_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR2_MACHINE_UPM
+
+if BR2_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR2_COLS_7
+ bool "7"
+
+config OR2_COLS_8
+ bool "8"
+
+config OR2_COLS_9
+ bool "9"
+
+config OR2_COLS_10
+ bool "10"
+
+config OR2_COLS_11
+ bool "11"
+
+config OR2_COLS_12
+ bool "12"
+
+config OR2_COLS_13
+ bool "13"
+
+config OR2_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR2_ROWS_9
+ bool "9"
+
+config OR2_ROWS_10
+ bool "10"
+
+config OR2_ROWS_11
+ bool "11"
+
+config OR2_ROWS_12
+ bool "12"
+
+config OR2_ROWS_13
+ bool "13"
+
+config OR2_ROWS_14
+ bool "14"
+
+config OR2_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR2_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR2_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR2_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR2_TRLX_NORMAL
+ bool "Normal"
+
+config OR2_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR2_EHTR_NORMAL
+ depends on OR2_TRLX_NORMAL
+ bool "Normal"
+
+config OR2_EHTR_1_CYCLE
+ depends on OR2_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR2_EHTR_4_CYCLE
+ depends on OR2_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR2_EHTR_8_CYCLE
+ depends on OR2_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR2_EAD_NONE
+ bool "None"
+
+config OR2_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR2_OR2
+
+config BR2_PORTSIZE
+ hex
+ default 0x800 if BR2_PORTSIZE_8BIT
+ default 0x1000 if BR2_PORTSIZE_16BIT
+ default 0x1800 if BR2_PORTSIZE_32BIT
+
+config BR2_ERRORCHECKING
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if BR2_ERRORCHECKING_DISABLED
+ default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR2_ERRORCHECKING_BOTH
+
+config BR2_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR2_WRITE_PROTECT
+ default 0x100 if BR2_WRITE_PROTECT
+
+config BR2_MACHINE
+ hex
+ default 0x0 if BR2_MACHINE_GPCM
+ default 0x20 if BR2_MACHINE_FCM
+ default 0x60 if BR2_MACHINE_SDRAM
+ default 0x80 if BR2_MACHINE_UPMA
+ default 0xa0 if BR2_MACHINE_UPMB
+ default 0xc0 if BR2_MACHINE_UPMC
+
+config BR2_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR2_ATOMIC_NONE
+ default 0x4 if BR2_ATOMIC_RAWA
+ default 0x8 if BR2_ATOMIC_WARA
+
+config BR2_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR2_OR2
+ default 0x1 if ELBC_BR2_OR2
+
+config OR2_AM
+ hex
+ default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM
+ default 0xffff0000 if OR2_AM_64_KBYTES
+ default 0xfffe0000 if OR2_AM_128_KBYTES
+ default 0xfffc0000 if OR2_AM_256_KBYTES
+ default 0xfff80000 if OR2_AM_512_KBYTES
+ default 0xfff00000 if OR2_AM_1_MBYTES
+ default 0xffe00000 if OR2_AM_2_MBYTES
+ default 0xffc00000 if OR2_AM_4_MBYTES
+ default 0xff800000 if OR2_AM_8_MBYTES
+ default 0xff000000 if OR2_AM_16_MBYTES
+ default 0xfe000000 if OR2_AM_32_MBYTES
+ default 0xfc000000 if OR2_AM_64_MBYTES
+ default 0xf8000000 if OR2_AM_128_MBYTES
+ default 0xf0000000 if OR2_AM_256_MBYTES
+ default 0xe0000000 if OR2_AM_512_MBYTES
+ default 0xc0000000 if OR2_AM_1_GBYTES
+ default 0x80000000 if OR2_AM_2_GBYTES
+ default 0x00000000 if OR2_AM_4_GBYTES
+
+config OR2_XAM
+ hex
+ default 0x0 if !OR2_XAM_SET
+ default 0x6000 if OR2_XAM_SET
+
+config OR2_BCTLD
+ hex
+ default 0x0 if OR2_BCTLD_ASSERTED
+ default 0x1000 if OR2_BCTLD_NOT_ASSERTED
+
+config OR2_BI
+ hex
+ default 0x0 if !BR2_MACHINE_UPM
+ default 0x0 if OR2_BI_BURSTSUPPORT
+ default 0x100 if OR2_BI_BURSTINHIBIT
+
+config OR2_COLS
+ hex
+ default 0x0 if !BR2_MACHINE_SDRAM
+ default 0x0 if OR2_COLS_7
+ default 0x400 if OR2_COLS_8
+ default 0x800 if OR2_COLS_9
+ default 0xc00 if OR2_COLS_10
+ default 0x1000 if OR2_COLS_11
+ default 0x1400 if OR2_COLS_12
+ default 0x1800 if OR2_COLS_13
+ default 0x1c00 if OR2_COLS_14
+
+config OR2_ROWS
+ hex
+ default 0x0 if !BR2_MACHINE_SDRAM
+ default 0x0 if OR2_ROWS_9
+ default 0x40 if OR2_ROWS_10
+ default 0x80 if OR2_ROWS_11
+ default 0xc0 if OR2_ROWS_12
+ default 0x100 if OR2_ROWS_13
+ default 0x140 if OR2_ROWS_14
+ default 0x180 if OR2_ROWS_15
+
+config OR2_PMSEL
+ hex
+ default 0x0 if !BR2_MACHINE_SDRAM
+ default 0x0 if OR2_PMSEL_BTB
+ default 0x20 if OR2_PMSEL_KEPT_OPEN
+
+config OR2_SCY
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM
+ default 0x0 if OR2_SCY_0
+ default 0x10 if OR2_SCY_1
+ default 0x20 if OR2_SCY_2
+ default 0x30 if OR2_SCY_3
+ default 0x40 if OR2_SCY_4
+ default 0x50 if OR2_SCY_5
+ default 0x60 if OR2_SCY_6
+ default 0x70 if OR2_SCY_7
+ default 0x80 if OR2_SCY_8
+ default 0x90 if OR2_SCY_9
+ default 0xa0 if OR2_SCY_10
+ default 0xb0 if OR2_SCY_11
+ default 0xc0 if OR2_SCY_12
+ default 0xd0 if OR2_SCY_13
+ default 0xe0 if OR2_SCY_14
+ default 0xf0 if OR2_SCY_15
+
+config OR2_PGS
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_PGS_SMALL
+ default 0x400 if OR2_PGS_LARGE
+
+config OR2_CSCT
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_CSCT_1_CYCLE
+ default 0x0 if OR2_CSCT_2_CYCLE
+ default 0x200 if OR2_CSCT_4_CYCLE
+ default 0x200 if OR2_CSCT_8_CYCLE
+
+config OR2_CST
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_CST_COINCIDENT
+ default 0x100 if OR2_CST_QUARTER_CLOCK
+ default 0x0 if OR2_CST_HALF_CLOCK
+ default 0x100 if OR2_CST_ONE_CLOCK
+
+config OR2_CHT
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_CHT_HALF_CLOCK
+ default 0x80 if OR2_CHT_ONE_CLOCK
+ default 0x0 if OR2_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR2_CHT_TWO_CLOCK
+
+config OR2_RST
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR2_RST_ONE_CLOCK
+ default 0x0 if OR2_RST_ONE_HALF_CLOCK
+
+config OR2_CSNT
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM
+ default 0x0 if OR2_CSNT_NORMAL
+ default 0x800 if OR2_CSNT_EARLIER
+
+config OR2_ACS
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM
+ default 0x0 if OR2_ACS_SAME_TIME
+ default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER
+
+config OR2_XACS
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM
+ default 0x0 if OR2_XACS_NORMAL
+ default 0x100 if OR2_XACS_EXTENDED
+
+config OR2_SETA
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM
+ default 0x0 if OR2_SETA_INTERNAL
+ default 0x8 if OR2_SETA_EXTERNAL
+
+config OR2_TRLX
+ hex
+ default 0x0 if OR2_TRLX_NORMAL
+ default 0x4 if OR2_TRLX_RELAXED
+
+config OR2_EHTR
+ hex
+ default 0x0 if OR2_EHTR_NORMAL
+ default 0x2 if OR2_EHTR_1_CYCLE
+ default 0x0 if OR2_EHTR_4_CYCLE
+ default 0x2 if OR2_EHTR_8_CYCLE
+
+config OR2_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR2_EAD_NONE
+ default 0x1 if OR2_EAD_EXTRA
--- /dev/null
+menuconfig ELBC_BR3_OR3
+ bool "ELBC BR3/OR3"
+
+if ELBC_BR3_OR3
+
+config BR3_OR3_NAME
+ string "Identifier"
+
+config BR3_OR3_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR3_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR3_PORTSIZE_16BIT
+ depends on !BR3_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR3_PORTSIZE_32BIT
+ depends on !BR3_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR3_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR3_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR3_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR3_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR3_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR3_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR3_MACHINE_GPCM
+ bool "GPCM"
+
+config BR3_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR3_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR3_MACHINE_UPMA
+ select BR3_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR3_MACHINE_UPMB
+ select BR3_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR3_MACHINE_UPMC
+ select BR3_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR3_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR3_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR3_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR3_AM_32_KBYTES
+ depends on !BR3_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR3_AM_64_KBYTES
+ bool "64 kb"
+
+config OR3_AM_128_KBYTES
+ bool "128 kb"
+
+config OR3_AM_256_KBYTES
+ bool "256 kb"
+
+config OR3_AM_512_KBYTES
+ bool "512 kb"
+
+config OR3_AM_1_MBYTES
+ bool "1 mb"
+
+config OR3_AM_2_MBYTES
+ bool "2 mb"
+
+config OR3_AM_4_MBYTES
+ bool "4 mb"
+
+config OR3_AM_8_MBYTES
+ bool "8 mb"
+
+config OR3_AM_16_MBYTES
+ bool "16 mb"
+
+config OR3_AM_32_MBYTES
+ bool "32 mb"
+
+config OR3_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR3_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR3_AM_256_MBYTES
+ bool "256 mb"
+
+config OR3_AM_512_MBYTES
+ depends on BR3_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR3_AM_1_GBYTES
+ bool "1 gb"
+
+config OR3_AM_2_GBYTES
+ depends on BR3_MACHINE_FCM
+ bool "2 gb"
+
+config OR3_AM_4_GBYTES
+ depends on BR3_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR3_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR3_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR3_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR3_MACHINE_GPCM || BR3_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR3_SCY_0
+ bool "No wait states"
+
+config OR3_SCY_1
+ bool "1 wait state"
+
+config OR3_SCY_2
+ bool "2 wait states"
+
+config OR3_SCY_3
+ bool "3 wait states"
+
+config OR3_SCY_4
+ bool "4 wait states"
+
+config OR3_SCY_5
+ bool "5 wait states"
+
+config OR3_SCY_6
+ bool "6 wait states"
+
+config OR3_SCY_7
+ bool "7 wait states"
+
+config OR3_SCY_8
+ depends on BR3_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR3_SCY_9
+ depends on BR3_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR3_SCY_10
+ depends on BR3_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR3_SCY_11
+ depends on BR3_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR3_SCY_12
+ depends on BR3_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR3_SCY_13
+ depends on BR3_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR3_SCY_14
+ depends on BR3_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR3_SCY_15
+ depends on BR3_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM
+
+if BR3_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR3_CSNT_NORMAL
+ bool "Normal"
+
+config OR3_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR3_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR3_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR3_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR3_XACS_NORMAL
+ bool "Normal"
+
+config OR3_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR3_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR3_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR3_MACHINE_GPCM
+
+if BR3_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR3_PGS_SMALL
+ bool "Small page device"
+
+config OR3_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR3_CSCT_1_CYCLE
+ depends on OR3_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR3_CSCT_2_CYCLE
+ depends on OR3_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR3_CSCT_4_CYCLE
+ depends on OR3_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR3_CSCT_8_CYCLE
+ depends on OR3_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR3_CST_COINCIDENT
+ depends on OR3_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR3_CST_QUARTER_CLOCK
+ depends on OR3_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR3_CST_HALF_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR3_CST_ONE_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR3_CHT_HALF_CLOCK
+ depends on OR3_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR3_CHT_ONE_CLOCK
+ depends on OR3_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR3_CHT_ONE_HALF_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR3_CHT_TWO_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR3_RST_THREE_QUARTER_CLOCK
+ depends on OR3_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR3_RST_ONE_HALF_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR3_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR3_MACHINE_FCM
+
+if BR3_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR3_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR3_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR3_MACHINE_UPM
+
+if BR3_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR3_COLS_7
+ bool "7"
+
+config OR3_COLS_8
+ bool "8"
+
+config OR3_COLS_9
+ bool "9"
+
+config OR3_COLS_10
+ bool "10"
+
+config OR3_COLS_11
+ bool "11"
+
+config OR3_COLS_12
+ bool "12"
+
+config OR3_COLS_13
+ bool "13"
+
+config OR3_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR3_ROWS_9
+ bool "9"
+
+config OR3_ROWS_10
+ bool "10"
+
+config OR3_ROWS_11
+ bool "11"
+
+config OR3_ROWS_12
+ bool "12"
+
+config OR3_ROWS_13
+ bool "13"
+
+config OR3_ROWS_14
+ bool "14"
+
+config OR3_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR3_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR3_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR3_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR3_TRLX_NORMAL
+ bool "Normal"
+
+config OR3_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR3_EHTR_NORMAL
+ depends on OR3_TRLX_NORMAL
+ bool "Normal"
+
+config OR3_EHTR_1_CYCLE
+ depends on OR3_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR3_EHTR_4_CYCLE
+ depends on OR3_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR3_EHTR_8_CYCLE
+ depends on OR3_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR3_EAD_NONE
+ bool "None"
+
+config OR3_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR3_OR3
+
+config BR3_PORTSIZE
+ hex
+ default 0x800 if BR3_PORTSIZE_8BIT
+ default 0x1000 if BR3_PORTSIZE_16BIT
+ default 0x1800 if BR3_PORTSIZE_32BIT
+
+config BR3_ERRORCHECKING
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if BR3_ERRORCHECKING_DISABLED
+ default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR3_ERRORCHECKING_BOTH
+
+config BR3_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR3_WRITE_PROTECT
+ default 0x100 if BR3_WRITE_PROTECT
+
+config BR3_MACHINE
+ hex
+ default 0x0 if BR3_MACHINE_GPCM
+ default 0x20 if BR3_MACHINE_FCM
+ default 0x60 if BR3_MACHINE_SDRAM
+ default 0x80 if BR3_MACHINE_UPMA
+ default 0xa0 if BR3_MACHINE_UPMB
+ default 0xc0 if BR3_MACHINE_UPMC
+
+config BR3_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR3_ATOMIC_NONE
+ default 0x4 if BR3_ATOMIC_RAWA
+ default 0x8 if BR3_ATOMIC_WARA
+
+config BR3_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR3_OR3
+ default 0x1 if ELBC_BR3_OR3
+
+config OR3_AM
+ hex
+ default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM
+ default 0xffff0000 if OR3_AM_64_KBYTES
+ default 0xfffe0000 if OR3_AM_128_KBYTES
+ default 0xfffc0000 if OR3_AM_256_KBYTES
+ default 0xfff80000 if OR3_AM_512_KBYTES
+ default 0xfff00000 if OR3_AM_1_MBYTES
+ default 0xffe00000 if OR3_AM_2_MBYTES
+ default 0xffc00000 if OR3_AM_4_MBYTES
+ default 0xff800000 if OR3_AM_8_MBYTES
+ default 0xff000000 if OR3_AM_16_MBYTES
+ default 0xfe000000 if OR3_AM_32_MBYTES
+ default 0xfc000000 if OR3_AM_64_MBYTES
+ default 0xf8000000 if OR3_AM_128_MBYTES
+ default 0xf0000000 if OR3_AM_256_MBYTES
+ default 0xe0000000 if OR3_AM_512_MBYTES
+ default 0xc0000000 if OR3_AM_1_GBYTES
+ default 0x80000000 if OR3_AM_2_GBYTES
+ default 0x00000000 if OR3_AM_4_GBYTES
+
+config OR3_XAM
+ hex
+ default 0x0 if !OR3_XAM_SET
+ default 0x6000 if OR3_XAM_SET
+
+config OR3_BCTLD
+ hex
+ default 0x0 if OR3_BCTLD_ASSERTED
+ default 0x1000 if OR3_BCTLD_NOT_ASSERTED
+
+config OR3_BI
+ hex
+ default 0x0 if !BR3_MACHINE_UPM
+ default 0x0 if OR3_BI_BURSTSUPPORT
+ default 0x100 if OR3_BI_BURSTINHIBIT
+
+config OR3_COLS
+ hex
+ default 0x0 if !BR3_MACHINE_SDRAM
+ default 0x0 if OR3_COLS_7
+ default 0x400 if OR3_COLS_8
+ default 0x800 if OR3_COLS_9
+ default 0xc00 if OR3_COLS_10
+ default 0x1000 if OR3_COLS_11
+ default 0x1400 if OR3_COLS_12
+ default 0x1800 if OR3_COLS_13
+ default 0x1c00 if OR3_COLS_14
+
+config OR3_ROWS
+ hex
+ default 0x0 if !BR3_MACHINE_SDRAM
+ default 0x0 if OR3_ROWS_9
+ default 0x40 if OR3_ROWS_10
+ default 0x80 if OR3_ROWS_11
+ default 0xc0 if OR3_ROWS_12
+ default 0x100 if OR3_ROWS_13
+ default 0x140 if OR3_ROWS_14
+ default 0x180 if OR3_ROWS_15
+
+config OR3_PMSEL
+ hex
+ default 0x0 if !BR3_MACHINE_SDRAM
+ default 0x0 if OR3_PMSEL_BTB
+ default 0x20 if OR3_PMSEL_KEPT_OPEN
+
+config OR3_SCY
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM
+ default 0x0 if OR3_SCY_0
+ default 0x10 if OR3_SCY_1
+ default 0x20 if OR3_SCY_2
+ default 0x30 if OR3_SCY_3
+ default 0x40 if OR3_SCY_4
+ default 0x50 if OR3_SCY_5
+ default 0x60 if OR3_SCY_6
+ default 0x70 if OR3_SCY_7
+ default 0x80 if OR3_SCY_8
+ default 0x90 if OR3_SCY_9
+ default 0xa0 if OR3_SCY_10
+ default 0xb0 if OR3_SCY_11
+ default 0xc0 if OR3_SCY_12
+ default 0xd0 if OR3_SCY_13
+ default 0xe0 if OR3_SCY_14
+ default 0xf0 if OR3_SCY_15
+
+config OR3_PGS
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_PGS_SMALL
+ default 0x400 if OR3_PGS_LARGE
+
+config OR3_CSCT
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_CSCT_1_CYCLE
+ default 0x0 if OR3_CSCT_2_CYCLE
+ default 0x200 if OR3_CSCT_4_CYCLE
+ default 0x200 if OR3_CSCT_8_CYCLE
+
+config OR3_CST
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_CST_COINCIDENT
+ default 0x100 if OR3_CST_QUARTER_CLOCK
+ default 0x0 if OR3_CST_HALF_CLOCK
+ default 0x100 if OR3_CST_ONE_CLOCK
+
+config OR3_CHT
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_CHT_HALF_CLOCK
+ default 0x80 if OR3_CHT_ONE_CLOCK
+ default 0x0 if OR3_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR3_CHT_TWO_CLOCK
+
+config OR3_RST
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR3_RST_ONE_CLOCK
+ default 0x0 if OR3_RST_ONE_HALF_CLOCK
+
+config OR3_CSNT
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM
+ default 0x0 if OR3_CSNT_NORMAL
+ default 0x800 if OR3_CSNT_EARLIER
+
+config OR3_ACS
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM
+ default 0x0 if OR3_ACS_SAME_TIME
+ default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER
+
+config OR3_XACS
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM
+ default 0x0 if OR3_XACS_NORMAL
+ default 0x100 if OR3_XACS_EXTENDED
+
+config OR3_SETA
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM
+ default 0x0 if OR3_SETA_INTERNAL
+ default 0x8 if OR3_SETA_EXTERNAL
+
+config OR3_TRLX
+ hex
+ default 0x0 if OR3_TRLX_NORMAL
+ default 0x4 if OR3_TRLX_RELAXED
+
+config OR3_EHTR
+ hex
+ default 0x0 if OR3_EHTR_NORMAL
+ default 0x2 if OR3_EHTR_1_CYCLE
+ default 0x0 if OR3_EHTR_4_CYCLE
+ default 0x2 if OR3_EHTR_8_CYCLE
+
+config OR3_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR3_EAD_NONE
+ default 0x1 if OR3_EAD_EXTRA
--- /dev/null
+menuconfig ELBC_BR4_OR4
+ bool "ELBC BR4/OR4"
+
+if ELBC_BR4_OR4
+
+config BR4_OR4_NAME
+ string "Identifier"
+
+config BR4_OR4_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR4_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR4_PORTSIZE_16BIT
+ depends on !BR4_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR4_PORTSIZE_32BIT
+ depends on !BR4_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR4_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR4_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR4_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR4_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR4_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR4_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR4_MACHINE_GPCM
+ bool "GPCM"
+
+config BR4_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR4_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR4_MACHINE_UPMA
+ select BR4_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR4_MACHINE_UPMB
+ select BR4_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR4_MACHINE_UPMC
+ select BR4_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR4_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR4_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR4_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR4_AM_32_KBYTES
+ depends on !BR4_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR4_AM_64_KBYTES
+ bool "64 kb"
+
+config OR4_AM_128_KBYTES
+ bool "128 kb"
+
+config OR4_AM_256_KBYTES
+ bool "256 kb"
+
+config OR4_AM_512_KBYTES
+ bool "512 kb"
+
+config OR4_AM_1_MBYTES
+ bool "1 mb"
+
+config OR4_AM_2_MBYTES
+ bool "2 mb"
+
+config OR4_AM_4_MBYTES
+ bool "4 mb"
+
+config OR4_AM_8_MBYTES
+ bool "8 mb"
+
+config OR4_AM_16_MBYTES
+ bool "16 mb"
+
+config OR4_AM_32_MBYTES
+ bool "32 mb"
+
+config OR4_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR4_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR4_AM_256_MBYTES
+ bool "256 mb"
+
+config OR4_AM_512_MBYTES
+ depends on BR4_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR4_AM_1_GBYTES
+ bool "1 gb"
+
+config OR4_AM_2_GBYTES
+ depends on BR4_MACHINE_FCM
+ bool "2 gb"
+
+config OR4_AM_4_GBYTES
+ depends on BR4_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR4_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR4_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR4_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR4_MACHINE_GPCM || BR4_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR4_SCY_0
+ bool "No wait states"
+
+config OR4_SCY_1
+ bool "1 wait state"
+
+config OR4_SCY_2
+ bool "2 wait states"
+
+config OR4_SCY_3
+ bool "3 wait states"
+
+config OR4_SCY_4
+ bool "4 wait states"
+
+config OR4_SCY_5
+ bool "5 wait states"
+
+config OR4_SCY_6
+ bool "6 wait states"
+
+config OR4_SCY_7
+ bool "7 wait states"
+
+config OR4_SCY_8
+ depends on BR4_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR4_SCY_9
+ depends on BR4_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR4_SCY_10
+ depends on BR4_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR4_SCY_11
+ depends on BR4_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR4_SCY_12
+ depends on BR4_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR4_SCY_13
+ depends on BR4_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR4_SCY_14
+ depends on BR4_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR4_SCY_15
+ depends on BR4_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM
+
+if BR4_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR4_CSNT_NORMAL
+ bool "Normal"
+
+config OR4_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR4_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR4_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR4_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR4_XACS_NORMAL
+ bool "Normal"
+
+config OR4_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR4_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR4_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR4_MACHINE_GPCM
+
+if BR4_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR4_PGS_SMALL
+ bool "Small page device"
+
+config OR4_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR4_CSCT_1_CYCLE
+ depends on OR4_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR4_CSCT_2_CYCLE
+ depends on OR4_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR4_CSCT_4_CYCLE
+ depends on OR4_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR4_CSCT_8_CYCLE
+ depends on OR4_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR4_CST_COINCIDENT
+ depends on OR4_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR4_CST_QUARTER_CLOCK
+ depends on OR4_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR4_CST_HALF_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR4_CST_ONE_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR4_CHT_HALF_CLOCK
+ depends on OR4_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR4_CHT_ONE_CLOCK
+ depends on OR4_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR4_CHT_ONE_HALF_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR4_CHT_TWO_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR4_RST_THREE_QUARTER_CLOCK
+ depends on OR4_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR4_RST_ONE_HALF_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR4_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR4_MACHINE_FCM
+
+if BR4_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR4_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR4_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR4_MACHINE_UPM
+
+if BR4_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR4_COLS_7
+ bool "7"
+
+config OR4_COLS_8
+ bool "8"
+
+config OR4_COLS_9
+ bool "9"
+
+config OR4_COLS_10
+ bool "10"
+
+config OR4_COLS_11
+ bool "11"
+
+config OR4_COLS_12
+ bool "12"
+
+config OR4_COLS_13
+ bool "13"
+
+config OR4_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR4_ROWS_9
+ bool "9"
+
+config OR4_ROWS_10
+ bool "10"
+
+config OR4_ROWS_11
+ bool "11"
+
+config OR4_ROWS_12
+ bool "12"
+
+config OR4_ROWS_13
+ bool "13"
+
+config OR4_ROWS_14
+ bool "14"
+
+config OR4_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR4_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR4_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR4_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR4_TRLX_NORMAL
+ bool "Normal"
+
+config OR4_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR4_EHTR_NORMAL
+ depends on OR4_TRLX_NORMAL
+ bool "Normal"
+
+config OR4_EHTR_1_CYCLE
+ depends on OR4_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR4_EHTR_4_CYCLE
+ depends on OR4_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR4_EHTR_8_CYCLE
+ depends on OR4_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR4_EAD_NONE
+ bool "None"
+
+config OR4_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR4_OR4
+
+config BR4_PORTSIZE
+ hex
+ default 0x800 if BR4_PORTSIZE_8BIT
+ default 0x1000 if BR4_PORTSIZE_16BIT
+ default 0x1800 if BR4_PORTSIZE_32BIT
+
+config BR4_ERRORCHECKING
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if BR4_ERRORCHECKING_DISABLED
+ default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR4_ERRORCHECKING_BOTH
+
+config BR4_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR4_WRITE_PROTECT
+ default 0x100 if BR4_WRITE_PROTECT
+
+config BR4_MACHINE
+ hex
+ default 0x0 if BR4_MACHINE_GPCM
+ default 0x20 if BR4_MACHINE_FCM
+ default 0x60 if BR4_MACHINE_SDRAM
+ default 0x80 if BR4_MACHINE_UPMA
+ default 0xa0 if BR4_MACHINE_UPMB
+ default 0xc0 if BR4_MACHINE_UPMC
+
+config BR4_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR4_ATOMIC_NONE
+ default 0x4 if BR4_ATOMIC_RAWA
+ default 0x8 if BR4_ATOMIC_WARA
+
+config BR4_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR4_OR4
+ default 0x1 if ELBC_BR4_OR4
+
+config OR4_AM
+ hex
+ default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM
+ default 0xffff0000 if OR4_AM_64_KBYTES
+ default 0xfffe0000 if OR4_AM_128_KBYTES
+ default 0xfffc0000 if OR4_AM_256_KBYTES
+ default 0xfff80000 if OR4_AM_512_KBYTES
+ default 0xfff00000 if OR4_AM_1_MBYTES
+ default 0xffe00000 if OR4_AM_2_MBYTES
+ default 0xffc00000 if OR4_AM_4_MBYTES
+ default 0xff800000 if OR4_AM_8_MBYTES
+ default 0xff000000 if OR4_AM_16_MBYTES
+ default 0xfe000000 if OR4_AM_32_MBYTES
+ default 0xfc000000 if OR4_AM_64_MBYTES
+ default 0xf8000000 if OR4_AM_128_MBYTES
+ default 0xf0000000 if OR4_AM_256_MBYTES
+ default 0xe0000000 if OR4_AM_512_MBYTES
+ default 0xc0000000 if OR4_AM_1_GBYTES
+ default 0x80000000 if OR4_AM_2_GBYTES
+ default 0x00000000 if OR4_AM_4_GBYTES
+
+config OR4_XAM
+ hex
+ default 0x0 if !OR4_XAM_SET
+ default 0x6000 if OR4_XAM_SET
+
+config OR4_BCTLD
+ hex
+ default 0x0 if OR4_BCTLD_ASSERTED
+ default 0x1000 if OR4_BCTLD_NOT_ASSERTED
+
+config OR4_BI
+ hex
+ default 0x0 if !BR4_MACHINE_UPM
+ default 0x0 if OR4_BI_BURSTSUPPORT
+ default 0x100 if OR4_BI_BURSTINHIBIT
+
+config OR4_COLS
+ hex
+ default 0x0 if !BR4_MACHINE_SDRAM
+ default 0x0 if OR4_COLS_7
+ default 0x400 if OR4_COLS_8
+ default 0x800 if OR4_COLS_9
+ default 0xc00 if OR4_COLS_10
+ default 0x1000 if OR4_COLS_11
+ default 0x1400 if OR4_COLS_12
+ default 0x1800 if OR4_COLS_13
+ default 0x1c00 if OR4_COLS_14
+
+config OR4_ROWS
+ hex
+ default 0x0 if !BR4_MACHINE_SDRAM
+ default 0x0 if OR4_ROWS_9
+ default 0x40 if OR4_ROWS_10
+ default 0x80 if OR4_ROWS_11
+ default 0xc0 if OR4_ROWS_12
+ default 0x100 if OR4_ROWS_13
+ default 0x140 if OR4_ROWS_14
+ default 0x180 if OR4_ROWS_15
+
+config OR4_PMSEL
+ hex
+ default 0x0 if !BR4_MACHINE_SDRAM
+ default 0x0 if OR4_PMSEL_BTB
+ default 0x20 if OR4_PMSEL_KEPT_OPEN
+
+config OR4_SCY
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM
+ default 0x0 if OR4_SCY_0
+ default 0x10 if OR4_SCY_1
+ default 0x20 if OR4_SCY_2
+ default 0x30 if OR4_SCY_3
+ default 0x40 if OR4_SCY_4
+ default 0x50 if OR4_SCY_5
+ default 0x60 if OR4_SCY_6
+ default 0x70 if OR4_SCY_7
+ default 0x80 if OR4_SCY_8
+ default 0x90 if OR4_SCY_9
+ default 0xa0 if OR4_SCY_10
+ default 0xb0 if OR4_SCY_11
+ default 0xc0 if OR4_SCY_12
+ default 0xd0 if OR4_SCY_13
+ default 0xe0 if OR4_SCY_14
+ default 0xf0 if OR4_SCY_15
+
+config OR4_PGS
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_PGS_SMALL
+ default 0x400 if OR4_PGS_LARGE
+
+config OR4_CSCT
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_CSCT_1_CYCLE
+ default 0x0 if OR4_CSCT_2_CYCLE
+ default 0x200 if OR4_CSCT_4_CYCLE
+ default 0x200 if OR4_CSCT_8_CYCLE
+
+config OR4_CST
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_CST_COINCIDENT
+ default 0x100 if OR4_CST_QUARTER_CLOCK
+ default 0x0 if OR4_CST_HALF_CLOCK
+ default 0x100 if OR4_CST_ONE_CLOCK
+
+config OR4_CHT
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_CHT_HALF_CLOCK
+ default 0x80 if OR4_CHT_ONE_CLOCK
+ default 0x0 if OR4_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR4_CHT_TWO_CLOCK
+
+config OR4_RST
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR4_RST_ONE_CLOCK
+ default 0x0 if OR4_RST_ONE_HALF_CLOCK
+
+config OR4_CSNT
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM
+ default 0x0 if OR4_CSNT_NORMAL
+ default 0x800 if OR4_CSNT_EARLIER
+
+config OR4_ACS
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM
+ default 0x0 if OR4_ACS_SAME_TIME
+ default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER
+
+config OR4_XACS
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM
+ default 0x0 if OR4_XACS_NORMAL
+ default 0x100 if OR4_XACS_EXTENDED
+
+config OR4_SETA
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM
+ default 0x0 if OR4_SETA_INTERNAL
+ default 0x8 if OR4_SETA_EXTERNAL
+
+config OR4_TRLX
+ hex
+ default 0x0 if OR4_TRLX_NORMAL
+ default 0x4 if OR4_TRLX_RELAXED
+
+config OR4_EHTR
+ hex
+ default 0x0 if OR4_EHTR_NORMAL
+ default 0x2 if OR4_EHTR_1_CYCLE
+ default 0x0 if OR4_EHTR_4_CYCLE
+ default 0x2 if OR4_EHTR_8_CYCLE
+
+config OR4_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR4_EAD_NONE
+ default 0x1 if OR4_EAD_EXTRA
--- /dev/null
+#ifdef CONFIG_ELBC_BR0_OR0
+#define CONFIG_SYS_BR0_PRELIM (\
+ CONFIG_BR0_OR0_BASE |\
+ CONFIG_BR0_PORTSIZE |\
+ CONFIG_BR0_ERRORCHECKING |\
+ CONFIG_BR0_WRITE_PROTECT_BIT |\
+ CONFIG_BR0_MACHINE |\
+ CONFIG_BR0_ATOMIC |\
+ CONFIG_BR0_VALID_BIT \
+)
+#define CONFIG_SYS_OR0_PRELIM (\
+ CONFIG_OR0_AM |\
+ CONFIG_OR0_XAM |\
+ CONFIG_OR0_BCTLD |\
+ CONFIG_OR0_BI |\
+ CONFIG_OR0_COLS |\
+ CONFIG_OR0_ROWS |\
+ CONFIG_OR0_PMSEL |\
+ CONFIG_OR0_SCY |\
+ CONFIG_OR0_PGS |\
+ CONFIG_OR0_CSCT |\
+ CONFIG_OR0_CST |\
+ CONFIG_OR0_CHT |\
+ CONFIG_OR0_RST |\
+ CONFIG_OR0_CSNT |\
+ CONFIG_OR0_ACS |\
+ CONFIG_OR0_XACS |\
+ CONFIG_OR0_SETA |\
+ CONFIG_OR0_TRLX |\
+ CONFIG_OR0_EHTR |\
+ CONFIG_OR0_EAD \
+)
+#endif /* CONFIG_ELBC_BR0_OR0 */
+
+#ifdef CONFIG_ELBC_BR1_OR1
+#define CONFIG_SYS_BR1_PRELIM (\
+ CONFIG_BR1_OR1_BASE |\
+ CONFIG_BR1_PORTSIZE |\
+ CONFIG_BR1_ERRORCHECKING |\
+ CONFIG_BR1_WRITE_PROTECT_BIT |\
+ CONFIG_BR1_MACHINE |\
+ CONFIG_BR1_ATOMIC |\
+ CONFIG_BR1_VALID_BIT \
+)
+#define CONFIG_SYS_OR1_PRELIM (\
+ CONFIG_OR1_AM |\
+ CONFIG_OR1_XAM |\
+ CONFIG_OR1_BCTLD |\
+ CONFIG_OR1_BI |\
+ CONFIG_OR1_COLS |\
+ CONFIG_OR1_ROWS |\
+ CONFIG_OR1_PMSEL |\
+ CONFIG_OR1_SCY |\
+ CONFIG_OR1_PGS |\
+ CONFIG_OR1_CSCT |\
+ CONFIG_OR1_CST |\
+ CONFIG_OR1_CHT |\
+ CONFIG_OR1_RST |\
+ CONFIG_OR1_CSNT |\
+ CONFIG_OR1_ACS |\
+ CONFIG_OR1_XACS |\
+ CONFIG_OR1_SETA |\
+ CONFIG_OR1_TRLX |\
+ CONFIG_OR1_EHTR |\
+ CONFIG_OR1_EAD \
+)
+#endif /* CONFIG_ELBC_BR1_OR1 */
+
+#ifdef CONFIG_ELBC_BR2_OR2
+#define CONFIG_SYS_BR2_PRELIM (\
+ CONFIG_BR2_OR2_BASE |\
+ CONFIG_BR2_PORTSIZE |\
+ CONFIG_BR2_ERRORCHECKING |\
+ CONFIG_BR2_WRITE_PROTECT_BIT |\
+ CONFIG_BR2_MACHINE |\
+ CONFIG_BR2_ATOMIC |\
+ CONFIG_BR2_VALID_BIT \
+)
+#define CONFIG_SYS_OR2_PRELIM (\
+ CONFIG_OR2_AM |\
+ CONFIG_OR2_XAM |\
+ CONFIG_OR2_BCTLD |\
+ CONFIG_OR2_BI |\
+ CONFIG_OR2_COLS |\
+ CONFIG_OR2_ROWS |\
+ CONFIG_OR2_PMSEL |\
+ CONFIG_OR2_SCY |\
+ CONFIG_OR2_PGS |\
+ CONFIG_OR2_CSCT |\
+ CONFIG_OR2_CST |\
+ CONFIG_OR2_CHT |\
+ CONFIG_OR2_RST |\
+ CONFIG_OR2_CSNT |\
+ CONFIG_OR2_ACS |\
+ CONFIG_OR2_XACS |\
+ CONFIG_OR2_SETA |\
+ CONFIG_OR2_TRLX |\
+ CONFIG_OR2_EHTR |\
+ CONFIG_OR2_EAD \
+)
+#endif /* CONFIG_ELBC_BR2_OR2 */
+
+#ifdef CONFIG_ELBC_BR3_OR3
+#define CONFIG_SYS_BR3_PRELIM (\
+ CONFIG_BR3_OR3_BASE |\
+ CONFIG_BR3_PORTSIZE |\
+ CONFIG_BR3_ERRORCHECKING |\
+ CONFIG_BR3_WRITE_PROTECT_BIT |\
+ CONFIG_BR3_MACHINE |\
+ CONFIG_BR3_ATOMIC |\
+ CONFIG_BR3_VALID_BIT \
+)
+#define CONFIG_SYS_OR3_PRELIM (\
+ CONFIG_OR3_AM |\
+ CONFIG_OR3_XAM |\
+ CONFIG_OR3_BCTLD |\
+ CONFIG_OR3_BI |\
+ CONFIG_OR3_COLS |\
+ CONFIG_OR3_ROWS |\
+ CONFIG_OR3_PMSEL |\
+ CONFIG_OR3_SCY |\
+ CONFIG_OR3_PGS |\
+ CONFIG_OR3_CSCT |\
+ CONFIG_OR3_CST |\
+ CONFIG_OR3_CHT |\
+ CONFIG_OR3_RST |\
+ CONFIG_OR3_CSNT |\
+ CONFIG_OR3_ACS |\
+ CONFIG_OR3_XACS |\
+ CONFIG_OR3_SETA |\
+ CONFIG_OR3_TRLX |\
+ CONFIG_OR3_EHTR |\
+ CONFIG_OR3_EAD \
+)
+#endif /* CONFIG_ELBC_BR3_OR3 */
+
+#ifdef CONFIG_ELBC_BR4_OR4
+#define CONFIG_SYS_BR4_PRELIM (\
+ CONFIG_BR4_OR4_BASE |\
+ CONFIG_BR4_PORTSIZE |\
+ CONFIG_BR4_ERRORCHECKING |\
+ CONFIG_BR4_WRITE_PROTECT_BIT |\
+ CONFIG_BR4_MACHINE |\
+ CONFIG_BR4_ATOMIC |\
+ CONFIG_BR4_VALID_BIT \
+)
+#define CONFIG_SYS_OR4_PRELIM (\
+ CONFIG_OR4_AM |\
+ CONFIG_OR4_XAM |\
+ CONFIG_OR4_BCTLD |\
+ CONFIG_OR4_BI |\
+ CONFIG_OR4_COLS |\
+ CONFIG_OR4_ROWS |\
+ CONFIG_OR4_PMSEL |\
+ CONFIG_OR4_SCY |\
+ CONFIG_OR4_PGS |\
+ CONFIG_OR4_CSCT |\
+ CONFIG_OR4_CST |\
+ CONFIG_OR4_CHT |\
+ CONFIG_OR4_RST |\
+ CONFIG_OR4_CSNT |\
+ CONFIG_OR4_ACS |\
+ CONFIG_OR4_XACS |\
+ CONFIG_OR4_SETA |\
+ CONFIG_OR4_TRLX |\
+ CONFIG_OR4_EHTR |\
+ CONFIG_OR4_EAD \
+)
+#endif /* CONFIG_ELBC_BR4_OR4 */
+
+#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
+#endif
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
- (defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
+ (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
#include <linux/immap_qe.h>
void fdt_fixup_muram (void *blob)
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
-#ifdef CONFIG_MPC8313
+#ifdef CONFIG_ARCH_MPC8313
/*
* mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
* h/w (see AN3545). The base device tree in use has rev. 1 ID numbers,
#endif
#ifdef CONFIG_SYS_NS16550
- do_fixup_by_compat_u32(blob, "ns16550",
- "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+ do_fixup_by_compat_u32(blob, "ns16550",
+ "clock-frequency", get_serial_clock(), 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
- (defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
+ (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
fdt_fixup_muram (blob);
#endif
}
--- /dev/null
+menu "HID setup"
+
+menu "HID0 initial"
+
+config HID0_INIT_EMCP
+ bool "Enable machine check int on mcp"
+
+config HID0_INIT_ECPE
+ bool "Enable cache parity errors"
+
+config HID0_INIT_EBA
+ bool "Enable address parity checking"
+
+config HID0_INIT_EBD
+ bool "Enable data parity checking"
+
+choice
+ prompt "HID0 clock configuration"
+
+config HID0_INIT_CLKOUT_OFF
+ bool "Clock output off"
+
+config HID0_INIT_CLKOUT_CORE_HALF
+ bool "Core clock / 2"
+
+config HID0_INIT_CLKOUT_CORE
+ bool "Core clock"
+
+config HID0_INIT_CLKOUT_BUS
+ bool "Bus clock"
+
+endchoice
+
+config HID0_INIT_PAR
+ bool "Disable precharge of artry_out"
+
+config HID0_INIT_DOZE
+ bool "Enable doze mode"
+
+config HID0_INIT_NAP
+ bool "Enable nap mode"
+
+config HID0_INIT_SLEEP
+ bool "Enable sleep mode"
+
+config HID0_INIT_DPM
+ bool "Enable dynamic power management"
+
+config HID0_INIT_ICE
+ bool "Enable instruction cache"
+
+config HID0_INIT_DCE
+ bool "Enable data cache"
+
+config HID0_INIT_ILOCK
+ bool "Lock instruction cache"
+
+config HID0_INIT_DLOCK
+ bool "Lock data cache"
+
+config HID0_INIT_ICFI
+ bool "Flash invalidate instruction cache"
+
+config HID0_INIT_DCFI
+ bool "Flash invalidate data cache"
+
+config HID0_INIT_IFEM
+ bool "Enable m bit on bus for instruction fetches"
+
+config HID0_INIT_DECAREN
+ bool "Decrementer auto reload"
+
+config HID0_INIT_FBIOB
+ bool "Force indirect branch on the bus"
+
+config HID0_INIT_ABE
+ bool "Enable address broadcast"
+
+config HID0_INIT_NOOPTI
+ bool "No-op data cache touch intructions"
+
+endmenu
+
+menu "HID0 final"
+
+config HID0_FINAL_EMCP
+ bool "Enable machine check int on mcp"
+
+config HID0_FINAL_ECPE
+ bool "Enable cache parity errors"
+
+config HID0_FINAL_EBA
+ bool "Enable address parity checking"
+
+config HID0_FINAL_EBD
+ bool "Enable data parity checking"
+
+choice
+ prompt "HID0 clock configuration"
+
+config HID0_FINAL_CLKOUT_OFF
+ bool "Clock output off"
+
+config HID0_FINAL_CLKOUT_CORE_HALF
+ bool "Core clock / 2"
+
+config HID0_FINAL_CLKOUT_CORE
+ bool "Core clock"
+
+config HID0_FINAL_CLKOUT_BUS
+ bool "Bus clock"
+
+endchoice
+
+config HID0_FINAL_PAR
+ bool "Disable precharge of artry_out"
+
+config HID0_FINAL_DOZE
+ bool "Enable doze mode"
+
+config HID0_FINAL_NAP
+ bool "Enable nap mode"
+
+config HID0_FINAL_SLEEP
+ bool "Enable sleep mode"
+
+config HID0_FINAL_DPM
+ bool "Enable dynamic power management"
+
+config HID0_FINAL_ICE
+ bool "Enable instruction cache"
+
+config HID0_FINAL_DCE
+ bool "Enable data cache"
+
+config HID0_FINAL_ILOCK
+ bool "Lock instruction cache"
+
+config HID0_FINAL_DLOCK
+ bool "Lock data cache"
+
+config HID0_FINAL_ICFI
+ bool "Flash invalidate instruction cache"
+
+config HID0_FINAL_DCFI
+ bool "Flash invalidate data cache"
+
+config HID0_FINAL_IFEM
+ bool "Enable m bit on bus for instruction fetches"
+
+config HID0_FINAL_DECAREN
+ bool "Decrementer auto reload"
+
+config HID0_FINAL_FBIOB
+ bool "Force indirect branch on the bus"
+
+config HID0_FINAL_ABE
+ bool "Enable address broadcast"
+
+config HID0_FINAL_NOOPTI
+ bool "No-op data cache touch intructions"
+
+endmenu
+
+config HID0_INIT_EMCP_BIT
+ hex
+ default 0x0 if !HID0_INIT_EMCP
+ default 0x80000000 if HID0_INIT_EMCP
+
+config HID0_INIT_ECPE_BIT
+ hex
+ default 0x0 if !HID0_INIT_ECPE
+ default 0x40000000 if HID0_INIT_ECPE
+
+config HID0_INIT_EBA_BIT
+ hex
+ default 0x0 if !HID0_INIT_EBA
+ default 0x20000000 if HID0_INIT_EBA
+
+config HID0_INIT_EBD_BIT
+ hex
+ default 0x0 if !HID0_INIT_EBD
+ default 0x10000000 if HID0_INIT_EBD
+
+config HID0_INIT_CLKOUT
+ hex
+ default 0x0 if HID0_INIT_CLKOUT_OFF
+ default 0x8000000 if HID0_INIT_CLKOUT_CORE_HALF
+ default 0x2000000 if HID0_INIT_CLKOUT_CORE
+ default 0xa000000 if HID0_INIT_CLKOUT_BUS
+
+config HID0_INIT_PAR_BIT
+ hex
+ default 0x0 if !HID0_INIT_PAR
+ default 0x1000000 if HID0_INIT_PAR
+
+config HID0_INIT_DOZE_BIT
+ hex
+ default 0x0 if !HID0_INIT_DOZE
+ default 0x800000 if HID0_INIT_DOZE
+
+config HID0_INIT_NAP_BIT
+ hex
+ default 0x0 if !HID0_INIT_NAP
+ default 0x400000 if HID0_INIT_NAP
+
+config HID0_INIT_SLEEP_BIT
+ hex
+ default 0x0 if !HID0_INIT_SLEEP
+ default 0x200000 if HID0_INIT_SLEEP
+
+config HID0_INIT_DPM_BIT
+ hex
+ default 0x0 if !HID0_INIT_DPM
+ default 0x100000 if HID0_INIT_DPM
+
+config HID0_INIT_ICE_BIT
+ hex
+ default 0x0 if !HID0_INIT_ICE
+ default 0x8000 if HID0_INIT_ICE
+
+config HID0_INIT_DCE_BIT
+ hex
+ default 0x0 if !HID0_INIT_DCE
+ default 0x4000 if HID0_INIT_DCE
+
+config HID0_INIT_ILOCK_BIT
+ hex
+ default 0x0 if !HID0_INIT_ILOCK
+ default 0x2000 if HID0_INIT_ILOCK
+
+config HID0_INIT_DLOCK_BIT
+ hex
+ default 0x0 if !HID0_INIT_DLOCK
+ default 0x1000 if HID0_INIT_DLOCK
+
+config HID0_INIT_ICFI_BIT
+ hex
+ default 0x0 if !HID0_INIT_ICFI
+ default 0x800 if HID0_INIT_ICFI
+
+config HID0_INIT_DCFI_BIT
+ hex
+ default 0x0 if !HID0_INIT_DCFI
+ default 0x400 if HID0_INIT_DCFI
+
+config HID0_INIT_IFEM_BIT
+ hex
+ default 0x0 if !HID0_INIT_IFEM
+ default 0x80 if HID0_INIT_IFEM
+
+config HID0_INIT_DECAREN_BIT
+ hex
+ default 0x0 if !HID0_INIT_DECAREN
+ default 0x40 if HID0_INIT_DECAREN
+
+config HID0_INIT_FBIOB_BIT
+ hex
+ default 0x0 if !HID0_INIT_FBIOB
+ default 0x10 if HID0_INIT_FBIOB
+
+config HID0_INIT_ABE_BIT
+ hex
+ default 0x0 if !HID0_INIT_ABE
+ default 0x8 if HID0_INIT_ABE
+
+config HID0_INIT_NOOPTI_BIT
+ hex
+ default 0x0 if !HID0_INIT_NOOPTI
+ default 0x1 if HID0_INIT_NOOPTI
+
+config HID0_FINAL_EMCP_BIT
+ hex
+ default 0x0 if !HID0_FINAL_EMCP
+ default 0x80000000 if HID0_FINAL_EMCP
+
+config HID0_FINAL_ECPE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ECPE
+ default 0x40000000 if HID0_FINAL_ECPE
+
+config HID0_FINAL_EBA_BIT
+ hex
+ default 0x0 if !HID0_FINAL_EBA
+ default 0x20000000 if HID0_FINAL_EBA
+
+config HID0_FINAL_EBD_BIT
+ hex
+ default 0x0 if !HID0_FINAL_EBD
+ default 0x10000000 if HID0_FINAL_EBD
+
+config HID0_FINAL_CLKOUT
+ hex
+ default 0x0 if HID0_FINAL_CLKOUT_OFF
+ default 0x8000000 if HID0_FINAL_CLKOUT_CORE_HALF
+ default 0x2000000 if HID0_FINAL_CLKOUT_CORE
+ default 0xa000000 if HID0_FINAL_CLKOUT_BUS
+
+config HID0_FINAL_SBCLK_BIT
+ hex
+ default 0x0 if !HID0_FINAL_SBCLK
+ default 0x8000000 if HID0_FINAL_SBCLK
+
+config HID0_FINAL_ECLK_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ECLK
+ default 0x2000000 if HID0_FINAL_ECLK
+
+config HID0_FINAL_PAR_BIT
+ hex
+ default 0x0 if !HID0_FINAL_PAR
+ default 0x1000000 if HID0_FINAL_PAR
+
+config HID0_FINAL_DOZE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DOZE
+ default 0x800000 if HID0_FINAL_DOZE
+
+config HID0_FINAL_NAP_BIT
+ hex
+ default 0x0 if !HID0_FINAL_NAP
+ default 0x400000 if HID0_FINAL_NAP
+
+config HID0_FINAL_SLEEP_BIT
+ hex
+ default 0x0 if !HID0_FINAL_SLEEP
+ default 0x200000 if HID0_FINAL_SLEEP
+
+config HID0_FINAL_DPM_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DPM
+ default 0x100000 if HID0_FINAL_DPM
+
+config HID0_FINAL_ICE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ICE
+ default 0x8000 if HID0_FINAL_ICE
+
+config HID0_FINAL_DCE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DCE
+ default 0x4000 if HID0_FINAL_DCE
+
+config HID0_FINAL_ILOCK_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ILOCK
+ default 0x2000 if HID0_FINAL_ILOCK
+
+config HID0_FINAL_DLOCK_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DLOCK
+ default 0x1000 if HID0_FINAL_DLOCK
+
+config HID0_FINAL_ICFI_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ICFI
+ default 0x800 if HID0_FINAL_ICFI
+
+config HID0_FINAL_DCFI_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DCFI
+ default 0x400 if HID0_FINAL_DCFI
+
+config HID0_FINAL_IFEM_BIT
+ hex
+ default 0x0 if !HID0_FINAL_IFEM
+ default 0x80 if HID0_FINAL_IFEM
+
+config HID0_FINAL_DECAREN_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DECAREN
+ default 0x40 if HID0_FINAL_DECAREN
+
+config HID0_FINAL_FBIOB_BIT
+ hex
+ default 0x0 if !HID0_FINAL_FBIOB
+ default 0x10 if HID0_FINAL_FBIOB
+
+config HID0_FINAL_ABE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ABE
+ default 0x8 if HID0_FINAL_ABE
+
+config HID0_FINAL_NOOPTI_BIT
+ hex
+ default 0x0 if !HID0_FINAL_NOOPTI
+ default 0x1 if HID0_FINAL_NOOPTI
+
+menu "HID2"
+
+config HID2_LET
+ bool "True little-endian mode"
+
+config HID2_IFEB
+ bool "Instruction fetch burst extension"
+
+config HID2_MESISTATE
+ bool "MESI state enable"
+
+config HID2_IFEC
+ bool "Instruction fetch cancel extension"
+
+config HID2_EBQS
+ bool "BIU queue sharing"
+
+config HID2_EBPX
+ bool "BIU pipeline extension"
+
+if !ARCH_MPC8360
+
+config HID2_ELRW
+ bool "Weighted LRU"
+
+config HID2_NOKS
+ bool "No kill for snoop"
+
+endif
+
+config HID2_HBE
+ bool "High bat enable"
+
+choice
+ prompt "Instruction cache way-lock"
+
+config HID2_IWLCK_NONE
+ bool "No ways locked"
+
+config HID2_IWLCK_0
+ bool "Way 0 locked"
+
+config HID2_IWLCK_1
+ bool "Way 0 through 1 locked"
+
+config HID2_IWLCK_2
+ bool "Way 0 through 2 locked"
+
+if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+
+config HID2_IWLCK_3
+ bool "Way 0 through 3 locked"
+
+config HID2_IWLCK_4
+ bool "Way 0 through 4 locked"
+
+config HID2_IWLCK_5
+ bool "Way 0 through 5 locked"
+
+config HID2_IWLCK_6
+ bool "Way 0 through 6 locked"
+
+endif
+
+endchoice
+
+config HID2_ICWP
+ bool "Instruction cache way protection"
+
+choice
+ prompt "Data cache way-lock"
+
+config HID2_DWLCK_NONE
+ bool "No ways locked"
+
+config HID2_DWLCK_0
+ bool "Way 0 locked"
+
+config HID2_DWLCK_1
+ bool "Way 0 through 1 locked"
+
+config HID2_DWLCK_2
+ bool "Way 0 through 2 locked"
+
+if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+
+config HID2_DWLCK_3
+ bool "Way 0 through 3 locked"
+
+config HID2_DWLCK_4
+ bool "Way 0 through 4 locked"
+
+config HID2_DWLCK_5
+ bool "Way 0 through 5 locked"
+
+config HID2_DWLCK_6
+ bool "Way 0 through 6 locked"
+
+endif
+
+endchoice
+
+config HID2_LET_BIT
+ hex
+ default 0x0 if !HID2_LET
+ default 0x8000000 if HID2_LET
+
+config HID2_IFEB_BIT
+ hex
+ default 0x0 if !HID2_IFEB
+ default 0x4000000 if HID2_IFEB
+
+config HID2_MESISTATE_BIT
+ hex
+ default 0x0 if !HID2_MESISTATE
+ default 0x1000000 if HID2_MESISTATE
+
+config HID2_IFEC_BIT
+ hex
+ default 0x0 if !HID2_IFEC
+ default 0x800000 if HID2_IFEC
+
+config HID2_EBQS_BIT
+ hex
+ default 0x0 if !HID2_EBQS
+ default 0x400000 if HID2_EBQS
+
+config HID2_EBPX_BIT
+ hex
+ default 0x0 if !HID2_EBPX
+ default 0x200000 if HID2_EBPX
+
+config HID2_ELRW_BIT
+ hex
+ default 0x0 if !HID2_ELRW
+ default 0x100000 if HID2_ELRW
+
+config HID2_NOKS_BIT
+ hex
+ default 0x0 if !HID2_NOKS
+ default 0x80000 if HID2_NOKS
+
+config HID2_HBE_BIT
+ hex
+ default 0x0 if !HID2_HBE
+ default 0x40000 if HID2_HBE
+
+config HID2_IWLCK
+ hex
+ default 0x0 if HID2_IWLCK_NONE
+ default 0x2000 if HID2_IWLCK_0
+ default 0x4000 if HID2_IWLCK_1
+ default 0x6000 if HID2_IWLCK_2
+ default 0x8000 if HID2_IWLCK_3
+ default 0xA000 if HID2_IWLCK_4
+ default 0xC000 if HID2_IWLCK_5
+ default 0xE000 if HID2_IWLCK_6
+
+config HID2_ICWP_BIT
+ hex
+ default 0x0 if !HID2_ICWP
+ default 0x1000 if HID2_ICWP
+
+config HID2_DWLCK
+ hex
+ default 0x0 if HID2_DWLCK_NONE
+ default 0x20 if HID2_DWLCK_0
+ default 0x40 if HID2_DWLCK_1
+ default 0x60 if HID2_DWLCK_2
+ default 0x80 if HID2_DWLCK_3
+ default 0xA0 if HID2_DWLCK_4
+ default 0xC0 if HID2_DWLCK_5
+ default 0xE0 if HID2_DWLCK_6
+
+endmenu
+
+endmenu
--- /dev/null
+#define CONFIG_SYS_HID0_FINAL ( \
+ CONFIG_HID0_FINAL_ABE_BIT |\
+ CONFIG_HID0_FINAL_CLKOUT |\
+ CONFIG_HID0_FINAL_DCE_BIT |\
+ CONFIG_HID0_FINAL_DCFI_BIT |\
+ CONFIG_HID0_FINAL_DECAREN_BIT |\
+ CONFIG_HID0_FINAL_DLOCK_BIT |\
+ CONFIG_HID0_FINAL_DOZE_BIT |\
+ CONFIG_HID0_FINAL_DPM_BIT |\
+ CONFIG_HID0_FINAL_EBA_BIT |\
+ CONFIG_HID0_FINAL_EBD_BIT |\
+ CONFIG_HID0_FINAL_ECLK_BIT |\
+ CONFIG_HID0_FINAL_ECPE_BIT |\
+ CONFIG_HID0_FINAL_EMCP_BIT |\
+ CONFIG_HID0_FINAL_FBIOB_BIT |\
+ CONFIG_HID0_FINAL_ICE_BIT |\
+ CONFIG_HID0_FINAL_ICFI_BIT |\
+ CONFIG_HID0_FINAL_IFEM_BIT |\
+ CONFIG_HID0_FINAL_ILOCK_BIT |\
+ CONFIG_HID0_FINAL_NAP_BIT |\
+ CONFIG_HID0_FINAL_NOOPTI_BIT |\
+ CONFIG_HID0_FINAL_PAR_BIT |\
+ CONFIG_HID0_FINAL_SBCLK_BIT |\
+ CONFIG_HID0_FINAL_SLEEP_BIT \
+)
+
+#define CONFIG_SYS_HID0_INIT ( \
+ CONFIG_HID0_INIT_ABE_BIT |\
+ CONFIG_HID0_INIT_CLKOUT |\
+ CONFIG_HID0_INIT_DCE_BIT |\
+ CONFIG_HID0_INIT_DCFI_BIT |\
+ CONFIG_HID0_INIT_DECAREN_BIT |\
+ CONFIG_HID0_INIT_DLOCK_BIT |\
+ CONFIG_HID0_INIT_DOZE_BIT |\
+ CONFIG_HID0_INIT_DPM_BIT |\
+ CONFIG_HID0_INIT_EBA_BIT |\
+ CONFIG_HID0_INIT_EBD_BIT |\
+ CONFIG_HID0_INIT_ECPE_BIT |\
+ CONFIG_HID0_INIT_EMCP_BIT |\
+ CONFIG_HID0_INIT_FBIOB_BIT |\
+ CONFIG_HID0_INIT_ICE_BIT |\
+ CONFIG_HID0_INIT_ICFI_BIT |\
+ CONFIG_HID0_INIT_IFEM_BIT |\
+ CONFIG_HID0_INIT_ILOCK_BIT |\
+ CONFIG_HID0_INIT_NAP_BIT |\
+ CONFIG_HID0_INIT_NOOPTI_BIT |\
+ CONFIG_HID0_INIT_PAR_BIT |\
+ CONFIG_HID0_INIT_SLEEP_BIT \
+)
+
+#ifdef CONFIG_TARGET_IDS8313
+/* IDS8313 defines a reserved bit; keep to not break compatibility */
+#define CONFIG_HID2_SPECIAL 0x00020000
+#else
+#define CONFIG_HID2_SPECIAL 0x0
+#endif
+
+#define CONFIG_SYS_HID2 ( \
+ CONFIG_HID2_LET_BIT |\
+ CONFIG_HID2_IFEB_BIT |\
+ CONFIG_HID2_MESISTATE_BIT |\
+ CONFIG_HID2_IFEC_BIT |\
+ CONFIG_HID2_EBQS_BIT |\
+ CONFIG_HID2_EBPX_BIT |\
+ CONFIG_HID2_ELRW_BIT |\
+ CONFIG_HID2_NOKS_BIT |\
+ CONFIG_HID2_HBE_BIT |\
+ CONFIG_HID2_IWLCK |\
+ CONFIG_HID2_ICWP_BIT |\
+ CONFIG_HID2_DWLCK |\
+ CONFIG_HID2_SPECIAL \
+)
--- /dev/null
+menu "Reset Configuration Word"
+
+choice
+ prompt "Local bus memory controller clock mode"
+
+config LBMC_CLOCK_MODE_1_1
+ bool "1 : 1"
+
+config LBMC_CLOCK_MODE_1_2
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ bool "1 : 2"
+
+endchoice
+
+choice
+ prompt "DDR SDRAM memory controller clock mode"
+
+config DDR_MC_CLOCK_MODE_1_2
+ bool "1 : 2"
+
+config DDR_MC_CLOCK_MODE_1_1
+ depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ bool "1 : 1"
+
+endchoice
+
+if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349
+
+choice
+ prompt "System PLL VCO division"
+
+config SYSTEM_PLL_VCO_DIV_1
+ depends on !ARCH_MPC837X
+ bool "1"
+
+config SYSTEM_PLL_VCO_DIV_2
+ bool "2"
+
+config SYSTEM_PLL_VCO_DIV_4
+ depends on !ARCH_MPC831X
+ bool "4"
+
+config SYSTEM_PLL_VCO_DIV_8
+ depends on !ARCH_MPC831X
+ bool "8"
+
+endchoice
+
+endif
+
+choice
+ prompt "System PLL multiplication factor"
+
+config SYSTEM_PLL_FACTOR_2_1
+ bool "2 : 1"
+
+config SYSTEM_PLL_FACTOR_3_1
+ bool "3 : 1"
+
+config SYSTEM_PLL_FACTOR_4_1
+ bool "4 : 1"
+
+config SYSTEM_PLL_FACTOR_5_1
+ bool "5 : 1"
+
+config SYSTEM_PLL_FACTOR_6_1
+ bool "6 : 1"
+
+config SYSTEM_PLL_FACTOR_7_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "7 : 1"
+
+config SYSTEM_PLL_FACTOR_8_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "8 : 1"
+
+config SYSTEM_PLL_FACTOR_9_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "9 : 1"
+
+config SYSTEM_PLL_FACTOR_10_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "10 : 1"
+
+config SYSTEM_PLL_FACTOR_11_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "11 : 1"
+
+config SYSTEM_PLL_FACTOR_12_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "12 : 1"
+
+config SYSTEM_PLL_FACTOR_13_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "13 : 1"
+
+config SYSTEM_PLL_FACTOR_14_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "14 : 1"
+
+config SYSTEM_PLL_FACTOR_15_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "15 : 1"
+
+config SYSTEM_PLL_FACTOR_16_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360
+ bool "16 : 1"
+
+endchoice
+
+config CORE_PLL_BYPASS
+ bool "Core PLL bypassed"
+
+if !CORE_PLL_BYPASS
+
+choice
+ prompt "Core PLL Ratio"
+
+config CORE_PLL_RATIO_1_1
+ bool "1 : 1"
+
+config CORE_PLL_RATIO_15_1
+ bool "1.5 : 1"
+
+config CORE_PLL_RATIO_2_1
+ bool "2 : 1"
+
+config CORE_PLL_RATIO_25_1
+ bool "2.5 : 1"
+
+config CORE_PLL_RATIO_3_1
+ bool "3 : 1"
+
+endchoice
+
+choice
+ prompt "Core PLL VCO Divider"
+
+config CORE_PLL_VCO_DIVIDER_2
+ bool "2"
+
+config CORE_PLL_VCO_DIVIDER_4
+ bool "4"
+
+config CORE_PLL_VCO_DIVIDER_8
+ depends on !ARCH_MPC8315
+ bool "8"
+
+endchoice
+
+endif
+
+if MPC83XX_QUICC_ENGINE
+
+choice
+ prompt "QUICC Engine PLL VCO Divider"
+
+config QUICC_VCO_DIVIDER_2
+ bool "2"
+
+config QUICC_VCO_DIVIDER_4
+ bool "4"
+
+config QUICC_VCO_DIVIDER_8
+ depends on ARCH_MPC8309
+ bool "8"
+
+endchoice
+
+choice
+ prompt "QUICC Engine PLL division factor"
+
+config QUICC_DIV_FACTOR_1
+ bool "1"
+
+config QUICC_DIV_FACTOR_2
+ bool "2"
+
+endchoice
+
+choice
+ prompt "QUICC Engine PLL multiplication factor"
+
+config QUICC_MULT_FACTOR_2
+ bool "2"
+
+config QUICC_MULT_FACTOR_3
+ bool "3"
+
+config QUICC_MULT_FACTOR_4
+ bool "4"
+
+config QUICC_MULT_FACTOR_5
+ bool "5"
+
+config QUICC_MULT_FACTOR_6
+ bool "6"
+
+config QUICC_MULT_FACTOR_7
+ bool "7"
+
+config QUICC_MULT_FACTOR_8
+ bool "8"
+
+config QUICC_MULT_FACTOR_9
+ depends on ARCH_MPC8360
+ bool "9"
+
+config QUICC_MULT_FACTOR_10
+ depends on ARCH_MPC8360
+ bool "10"
+
+config QUICC_MULT_FACTOR_11
+ depends on ARCH_MPC8360
+ bool "11"
+
+config QUICC_MULT_FACTOR_12
+ depends on ARCH_MPC8360
+ bool "12"
+
+config QUICC_MULT_FACTOR_13
+ depends on ARCH_MPC8360
+ bool "13"
+
+config QUICC_MULT_FACTOR_14
+ depends on ARCH_MPC8360
+ bool "14"
+
+config QUICC_MULT_FACTOR_15
+ depends on ARCH_MPC8360
+ bool "15"
+
+config QUICC_MULT_FACTOR_16
+ depends on ARCH_MPC8360
+ bool "16"
+
+config QUICC_MULT_FACTOR_17
+ depends on ARCH_MPC8360
+ bool "17"
+
+config QUICC_MULT_FACTOR_18
+ depends on ARCH_MPC8360
+ bool "18"
+
+config QUICC_MULT_FACTOR_19
+ depends on ARCH_MPC8360
+ bool "19"
+
+config QUICC_MULT_FACTOR_20
+ depends on ARCH_MPC8360
+ bool "20"
+
+config QUICC_MULT_FACTOR_21
+ depends on ARCH_MPC8360
+ bool "21"
+
+config QUICC_MULT_FACTOR_22
+ depends on ARCH_MPC8360
+ bool "22"
+
+config QUICC_MULT_FACTOR_23
+ depends on ARCH_MPC8360
+ bool "23"
+
+config QUICC_MULT_FACTOR_24
+ depends on ARCH_MPC8360
+ bool "24"
+
+config QUICC_MULT_FACTOR_25
+ depends on ARCH_MPC8360
+ bool "25"
+
+config QUICC_MULT_FACTOR_26
+ depends on ARCH_MPC8360
+ bool "26"
+
+config QUICC_MULT_FACTOR_27
+ depends on ARCH_MPC8360
+ bool "27"
+
+config QUICC_MULT_FACTOR_28
+ depends on ARCH_MPC8360
+ bool "28"
+
+config QUICC_MULT_FACTOR_29
+ depends on ARCH_MPC8360
+ bool "29"
+
+config QUICC_MULT_FACTOR_30
+ depends on ARCH_MPC8360
+ bool "30"
+
+config QUICC_MULT_FACTOR_31
+ depends on ARCH_MPC8360
+ bool "31"
+
+endchoice
+
+endif
+
+if MPC83XX_PCI_SUPPORT
+
+choice
+ prompt "PCI host mode"
+
+config PCI_HOST_MODE_DISABLE
+ bool "Disabled"
+
+config PCI_HOST_MODE_ENABLE
+ bool "Enabled"
+
+endchoice
+
+if ARCH_MPC8349
+
+choice
+ prompt "PCI 64-bit mode"
+
+config PCI_64BIT_MODE_DISABLE
+ bool "Disabled"
+
+config PCI_64BIT_MODE_ENABLE
+ bool "Enabled"
+
+endchoice
+
+endif
+
+choice
+ prompt "PCI internal arbiter 1 mode"
+
+config PCI_INT_ARBITER1_DISABLE
+ bool "Disabled"
+
+config PCI_INT_ARBITER1_ENABLE
+ bool "Enabled"
+
+endchoice
+
+if ARCH_MPC8349
+
+choice
+ prompt "PCI internal arbiter 2 mode"
+
+config PCI_INT_ARBITER2_DISABLE
+ bool "Disabled"
+
+config PCI_INT_ARBITER2_ENABLE
+ bool "Enabled"
+
+endchoice
+
+endif
+
+if ARCH_MPC8360
+
+choice
+ prompt "PCI clock output drive"
+
+config PCI_CLOCK_OUTPUT_DRIVE_DISABLE
+ bool "Disabled"
+
+config PCI_CLOCK_OUTPUT_DRIVE_ENABLE
+ bool "Enabled"
+
+endchoice
+
+endif
+
+endif
+
+choice
+ prompt "Core disable mode"
+
+config CORE_DISABLE_MODE_OFF
+ bool "Off"
+
+config CORE_DISABLE_MODE_ON
+ bool "On"
+
+endchoice
+
+choice
+ prompt "Boot Memory Space"
+
+config BOOT_MEMORY_SPACE_HIGH
+ bool "High"
+
+config BOOT_MEMORY_SPACE_LOW
+ bool "Low"
+
+endchoice
+
+choice
+ prompt "Boot Sequencer Configuration"
+
+config BOOT_SEQUENCER_DISABLED
+ bool "Disabled"
+
+config BOOT_SEQUENCER_NORMAL_I2C
+ bool "Normal I2C"
+
+config BOOT_SEQUENCER_EXTENDED_I2C
+ bool "Extended I2C"
+
+endchoice
+
+choice
+ prompt "Software Watchdog"
+
+config SOFTWARE_WATCHDOG_DISABLED
+ bool "Disabled"
+
+config SOFTWARE_WATCHDOG_ENABLED
+ bool "Enabled"
+
+endchoice
+
+choice
+ prompt "Boot ROM interface location"
+
+config BOOT_ROM_INTERFACE_DDR_SDRAM
+ bool "DDR_SDRAM"
+
+config BOOT_ROM_INTERFACE_PCI1
+ depends on MPC83XX_PCI_SUPPORT
+ bool "PCI1"
+
+config BOOT_ROM_INTERFACE_PCI2
+ depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349
+ bool "PCI2"
+
+config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
+ depends on ARCH_MPC837X
+ bool "PCI2"
+
+config BOOT_ROM_INTERFACE_ESDHC
+ depends on ARCH_MPC8309
+ bool "eSDHC"
+
+config BOOT_ROM_INTERFACE_SPI
+ depends on ARCH_MPC8309
+ bool "SPI"
+
+config BOOT_ROM_INTERFACE_GPCM_8BIT
+ bool "Local bus GPCM - 8-bit ROM"
+
+config BOOT_ROM_INTERFACE_GPCM_16BIT
+ bool "Local bus GPCM - 16-bit ROM"
+
+config BOOT_ROM_INTERFACE_GPCM_32BIT
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ bool "Local bus GPCM - 32-bit ROM"
+
+config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "Local bus NAND Flash- 8-bit small page ROM"
+
+config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "Local bus NAND Flash- 8-bit large page ROM"
+
+endchoice
+
+if MPC83XX_TSEC1_SUPPORT
+
+choice
+ prompt "TSEC1 mode"
+
+config TSEC1_MODE_MII
+ depends on !ARCH_MPC8349
+ bool "MII"
+
+config TSEC1_MODE_RMII
+ depends on ARCH_MPC831X && !ARCH_MPC8349
+ bool "RMII"
+
+config TSEC1_MODE_RGMII
+ bool "RGMII"
+
+config TSEC1_MODE_RTBI
+ depends on ARCH_MPC831X || ARCH_MPC837X
+ bool "RTBI"
+
+config TSEC1_MODE_GMII
+ depends on ARCH_MPC8349
+ bool "GMII"
+
+config TSEC1_MODE_TBI
+ depends on ARCH_MPC8349
+ bool "TBI"
+
+config TSEC1_MODE_SGMII
+ depends on ARCH_MPC831X || ARCH_MPC837X
+ bool "SGMII"
+
+endchoice
+
+endif
+
+if MPC83XX_TSEC2_SUPPORT
+
+choice
+ prompt "TSEC2 mode"
+
+config TSEC2_MODE_MII
+ depends on !ARCH_MPC8349
+ bool "MII"
+
+config TSEC2_MODE_RMII
+ depends on ARCH_MPC831X && !ARCH_MPC8349
+ bool "RMII"
+
+config TSEC2_MODE_RGMII
+ bool "RGMII"
+
+config TSEC2_MODE_RTBI
+ depends on ARCH_MPC831X || ARCH_MPC837X
+ bool "RTBI"
+
+config TSEC2_MODE_GMII
+ depends on ARCH_MPC8349
+ bool "GMII"
+
+config TSEC2_MODE_TBI
+ depends on ARCH_MPC8349
+ bool "TBI"
+
+config TSEC2_MODE_SGMII
+ depends on ARCH_MPC831X || ARCH_MPC837X
+ bool "SGMII"
+
+endchoice
+
+endif
+
+choice
+ prompt "True litle-endian mode"
+
+config TRUE_LITTLE_ENDIAN_BIG_ENDIAN
+ bool "Big-endian"
+
+config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
+ bool "Little-endian"
+
+endchoice
+
+if ARCH_MPC8360
+
+choice
+ prompt "Secondary DDR IO"
+
+config SECONDARY_DDR_IO_DISABLE
+ bool "Disable"
+
+config SECONDARY_DDR_IO_ENABLE
+ bool "Enable"
+
+endchoice
+
+endif
+
+if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360
+
+choice
+ prompt "LALE timing"
+
+config LALE_TIMING_NORMAL
+ bool "Normal"
+
+config LALE_TIMING_EARLIER
+ bool "Earlier"
+
+endchoice
+
+endif
+
+if MPC83XX_LDP_PIN
+
+choice
+ prompt "LDP pin mux state"
+
+config LDP_PIN_MUX_STATE_1
+ bool "Inital value 1"
+
+config LDP_PIN_MUX_STATE_0
+ bool "Inital value 0"
+
+endchoice
+
+endif
+
+endmenu
+
+config LBMC_CLOCK_MODE
+ int
+ default 0 if LBMC_CLOCK_MODE_1_1
+ default 1 if LBMC_CLOCK_MODE_1_2
+
+config DDR_MC_CLOCK_MODE
+ int
+ default 1 if DDR_MC_CLOCK_MODE_1_2
+ default 0 if DDR_MC_CLOCK_MODE_1_1
+
+config SYSTEM_PLL_VCO_DIV
+ int
+ default 0 if ARCH_MPC8349 || ARCH_MPC832X
+ default 2 if ARCH_MPC8313
+ default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
+ default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
+ default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
+ default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X)
+ default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X)
+ default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X)
+ default 3 if SYSTEM_PLL_VCO_DIV_1
+
+config SYSTEM_PLL_FACTOR
+ int
+ default 2 if SYSTEM_PLL_FACTOR_2_1
+ default 3 if SYSTEM_PLL_FACTOR_3_1
+ default 4 if SYSTEM_PLL_FACTOR_4_1
+ default 5 if SYSTEM_PLL_FACTOR_5_1
+ default 6 if SYSTEM_PLL_FACTOR_6_1
+ default 7 if SYSTEM_PLL_FACTOR_7_1
+ default 8 if SYSTEM_PLL_FACTOR_8_1
+ default 9 if SYSTEM_PLL_FACTOR_9_1
+ default 10 if SYSTEM_PLL_FACTOR_10_1
+ default 11 if SYSTEM_PLL_FACTOR_11_1
+ default 12 if SYSTEM_PLL_FACTOR_12_1
+ default 13 if SYSTEM_PLL_FACTOR_13_1
+ default 14 if SYSTEM_PLL_FACTOR_14_1
+ default 15 if SYSTEM_PLL_FACTOR_15_1
+ default 0 if SYSTEM_PLL_FACTOR_16_1
+
+config CORE_PLL_RATIO
+ hex
+ default 0x0 if CORE_PLL_BYPASS
+ default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8
+ default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8
+ default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8
+ default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8
+ default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8
+
+config CORE_DISABLE_MODE
+ int
+ default 0 if CORE_DISABLE_MODE_OFF
+ default 1 if CORE_DISABLE_MODE_ON
+
+config BOOT_MEMORY_SPACE
+ int
+ default 0 if BOOT_MEMORY_SPACE_LOW
+ default 1 if BOOT_MEMORY_SPACE_HIGH
+
+config BOOT_SEQUENCER
+ int
+ default 0 if BOOT_SEQUENCER_DISABLED
+ default 1 if BOOT_SEQUENCER_NORMAL_I2C
+ default 2 if BOOT_SEQUENCER_EXTENDED_I2C
+
+config SOFTWARE_WATCHDOG
+ int
+ default 0 if SOFTWARE_WATCHDOG_DISABLED
+ default 1 if SOFTWARE_WATCHDOG_ENABLED
+
+config BOOT_ROM_INTERFACE
+ hex
+ default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
+ default 0x4 if BOOT_ROM_INTERFACE_PCI1
+ default 0x8 if BOOT_ROM_INTERFACE_PCI2
+ default 0x8 if BOOT_ROM_INTERFACE_ESDHC
+ default 0xc if BOOT_ROM_INTERFACE_SPI
+ default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
+ default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
+ default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
+ default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT
+ default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
+ default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
+
+config TSEC1_MODE
+ hex
+ default 0x0 if !MPC83XX_TSEC1_SUPPORT
+ default 0x0 if TSEC1_MODE_MII
+ default 0x1 if TSEC1_MODE_RMII
+ default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349
+ default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349
+ default 0x6 if TSEC1_MODE_SGMII
+ default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349
+ default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349
+ default 0x2 if TSEC1_MODE_GMII
+ default 0x3 if TSEC1_MODE_TBI
+
+config TSEC2_MODE
+ hex
+ default 0x0 if !MPC83XX_TSEC2_SUPPORT
+ default 0x0 if TSEC2_MODE_MII
+ default 0x1 if TSEC2_MODE_RMII
+ default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349
+ default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349
+ default 0x6 if TSEC2_MODE_SGMII
+ default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349
+ default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349
+ default 0x2 if TSEC2_MODE_GMII
+ default 0x3 if TSEC2_MODE_TBI
+
+config SECONDARY_DDR_IO
+ int
+ default 0 if !ARCH_MPC8360
+ default 0 if SECONDARY_DDR_IO_DISABLE
+ default 1 if SECONDARY_DDR_IO_ENABLE
+
+config TRUE_LITTLE_ENDIAN
+ int
+ default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN
+ default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
+
+config LALE_TIMING
+ int
+ default 0 if ARCH_MPC830X || ARCH_MPC837X
+ default 0 if LALE_TIMING_NORMAL
+ default 1 if LALE_TIMING_EARLIER
+
+config LDP_PIN_MUX_STATE
+ int
+ default 0 if !MPC83XX_LDP_PIN
+ default 0 if LDP_PIN_MUX_STATE_1
+ default 1 if LDP_PIN_MUX_STATE_0
+
+config QUICC_VCO_DIVIDER
+ int
+ default 0 if !MPC83XX_QUICC_ENGINE
+ default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309
+ default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309
+ default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309
+ default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
+ default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
+ default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360
+
+config QUICC_DIV_FACTOR
+ int
+ default 0 if !MPC83XX_QUICC_ENGINE
+ default 0 if QUICC_DIV_FACTOR_1
+ default 1 if QUICC_DIV_FACTOR_2
+
+config QUICC_MULT_FACTOR
+ int
+ default 0 if !MPC83XX_QUICC_ENGINE
+ default 2 if QUICC_MULT_FACTOR_2
+ default 3 if QUICC_MULT_FACTOR_3
+ default 4 if QUICC_MULT_FACTOR_4
+ default 5 if QUICC_MULT_FACTOR_5
+ default 6 if QUICC_MULT_FACTOR_6
+ default 7 if QUICC_MULT_FACTOR_7
+ default 8 if QUICC_MULT_FACTOR_8
+ default 9 if QUICC_MULT_FACTOR_9
+ default 10 if QUICC_MULT_FACTOR_10
+ default 11 if QUICC_MULT_FACTOR_11
+ default 12 if QUICC_MULT_FACTOR_12
+ default 13 if QUICC_MULT_FACTOR_13
+ default 14 if QUICC_MULT_FACTOR_14
+ default 15 if QUICC_MULT_FACTOR_15
+ default 16 if QUICC_MULT_FACTOR_16
+ default 17 if QUICC_MULT_FACTOR_17
+ default 18 if QUICC_MULT_FACTOR_18
+ default 19 if QUICC_MULT_FACTOR_19
+ default 20 if QUICC_MULT_FACTOR_20
+ default 21 if QUICC_MULT_FACTOR_21
+ default 22 if QUICC_MULT_FACTOR_22
+ default 23 if QUICC_MULT_FACTOR_23
+ default 24 if QUICC_MULT_FACTOR_24
+ default 25 if QUICC_MULT_FACTOR_25
+ default 26 if QUICC_MULT_FACTOR_26
+ default 27 if QUICC_MULT_FACTOR_27
+ default 28 if QUICC_MULT_FACTOR_28
+ default 29 if QUICC_MULT_FACTOR_29
+ default 30 if QUICC_MULT_FACTOR_30
+ default 31 if QUICC_MULT_FACTOR_31
+
+config PCI_HOST_MODE
+ int
+ default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
+ default 0 if PCI_HOST_MODE_DISABLE
+ default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
+
+config PCI_64BIT_MODE
+ int
+ default 0 if !ARCH_MPC8349
+ default 0 if PCI_64BIT_MODE_DISABLE
+ default 1 if PCI_64BIT_MODE_ENABLE
+
+config PCI_INT_ARBITER1
+ int
+ default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
+ default 0 if PCI_INT_ARBITER1_DISABLE
+ default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
+
+config PCI_INT_ARBITER2
+ int
+ default 0 if !ARCH_MPC8349
+ default 0 if PCI_INT_ARBITER2_DISABLE
+ default 1 if PCI_INT_ARBITER2_ENABLE
+
+config PCI_CLOCK_OUTPUT_DRIVE
+ int
+ default 0 if !ARCH_MPC8360
+ default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE
+ default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE
--- /dev/null
+#ifdef CONFIG_ARCH_MPC8349
+#define TSEC1_MODE_SHIFT 17
+#define TSEC2_MODE_SHIFT 19
+#else
+#define TSEC1_MODE_SHIFT 18
+#define TSEC2_MODE_SHIFT 21
+#endif
+
+#define CONFIG_SYS_HRCW_LOW (\
+ (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
+ (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
+ (CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\
+ (CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\
+ (CONFIG_CORE_PLL_RATIO << (31 - 15)) |\
+ (CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\
+ (CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\
+ (CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \
+ )
+
+#define CONFIG_SYS_HRCW_HIGH (\
+ (CONFIG_PCI_HOST_MODE << (31 - 0)) |\
+ (CONFIG_PCI_64BIT_MODE << (31 - 1)) |\
+ (CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\
+ (CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\
+ (CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\
+ (CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\
+ (CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\
+ (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
+ (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
+ (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
+ (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\
+ (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\
+ (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
+ (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
+ (CONFIG_LALE_TIMING << (31 - 29)) |\
+ (CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \
+ )
--- /dev/null
+menu "Initial register configuration"
+
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr"
+
+endmenu
--- /dev/null
+menu "LCRR - Clock Ratio Register register"
+
+if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
+
+choice
+ prompt "DLL bypass"
+
+config LCRR_DBYP_UNSET
+ bool "Don't set value"
+
+config LCRR_DBYP_PLL_ENABLED
+ bool "PLL enabled"
+
+config LCRR_DBYP_PLL_BYPASSED
+ bool "PLL bypassed"
+
+endchoice
+
+endif
+
+if ARCH_MPC834X || ARCH_MPC8360
+
+choice
+ prompt "Additional delay cycles for SDRAM control signals"
+
+config LCRR_BUFCMDC_UNSET
+ bool "Don't set value"
+
+config LCRR_BUFCMDC_4
+ bool "4"
+
+config LCRR_BUFCMDC_1
+ bool "1"
+
+config LCRR_BUFCMDC_2
+ bool "2"
+
+config LCRR_BUFCMDC_3
+ bool "3"
+
+endchoice
+
+choice
+ prompt "Extended CAS latency"
+
+config LCRR_ECL_UNSET
+ bool "Don't set value"
+
+config LCRR_ECL_4
+ bool "4"
+
+config LCRR_ECL_5
+ bool "5"
+
+config LCRR_ECL_6
+ bool "6"
+
+config LCRR_ECL_7
+ bool "7"
+
+endchoice
+
+endif # ARCH_MPC834X || ARCH_MPC8360
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address delay cycles"
+
+config LCRR_EADC_UNSET
+ bool "Don't set value"
+
+config LCRR_EADC_4
+ bool "4"
+
+config LCRR_EADC_1
+ bool "1"
+
+config LCRR_EADC_2
+ bool "2"
+
+config LCRR_EADC_3
+ bool "3"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+choice
+ prompt "System clock divider"
+
+config LCRR_CLKDIV_UNSET
+ bool "Don't set value"
+
+config LCRR_CLKDIV_2
+ bool "2"
+
+config LCRR_CLKDIV_4
+ bool "4"
+
+config LCRR_CLKDIV_8
+ bool "8"
+
+endchoice
+
+config LCRR_DBYP
+ hex
+ default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
+ default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
+
+config LCRR_BUFCMDC
+ hex
+ default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
+ default 0x10000000 if LCRR_BUFCMDC_1
+ default 0x20000000 if LCRR_BUFCMDC_2
+ default 0x30000000 if LCRR_BUFCMDC_3
+
+config LCRR_ECL
+ hex
+ default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
+ default 0x1000000 if LCRR_ECL_5
+ default 0x2000000 if LCRR_ECL_6
+ default 0x3000000 if LCRR_ECL_7
+
+config LCRR_EADC
+ hex
+ default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
+ default 0x10000 if LCRR_EADC_1
+ default 0x20000 if LCRR_EADC_2
+ default 0x30000 if LCRR_EADC_3
+
+config LCRR_CLKDIV
+ hex
+ default 0x0 if LCRR_CLKDIV_UNSET
+ default 0x2 if LCRR_CLKDIV_2
+ default 0x4 if LCRR_CLKDIV_4
+ default 0x8 if LCRR_CLKDIV_8
+
+endmenu
--- /dev/null
+menu "SPCR - System priority and configuration register"
+
+choice
+ prompt "Optimize"
+
+config SPCR_OPT_UNSET
+ bool "Don't set value"
+
+config SPCR_OPT_NONE
+ bool "No performance enhancement"
+
+config SPCR_OPT_SPEC_READ
+ bool "Performance enhancement by speculative read"
+
+endchoice
+
+if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X
+
+choice
+ prompt "TSEC emergency priority"
+
+config SPCR_TSECEP_UNSET
+ bool "Don't set value"
+
+config SPCR_TSECEP_0
+ bool "Level 0 (lowest priority)"
+
+config SPCR_TSECEP_1
+ bool "Level 1"
+
+config SPCR_TSECEP_2
+ bool "Level 2"
+
+config SPCR_TSECEP_3
+ bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+if ARCH_MPC8349
+
+choice
+ prompt "TSEC1 emergency priority"
+
+config SPCR_TSEC1EP_UNSET
+ bool "Don't set value"
+
+config SPCR_TSEC1EP_0
+ bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC1EP_1
+ bool "Level 1"
+
+config SPCR_TSEC1EP_2
+ bool "Level 2"
+
+config SPCR_TSEC1EP_3
+ bool "Level 3 (highest priority)"
+
+endchoice
+
+choice
+ prompt "TSEC2 emergency priority"
+
+config SPCR_TSEC2EP_UNSET
+ bool "Don't set value"
+
+config SPCR_TSEC2EP_0
+ bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC2EP_1
+ bool "Level 1"
+
+config SPCR_TSEC2EP_2
+ bool "Level 2"
+
+config SPCR_TSEC2EP_3
+ bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+config SPCR_OPT
+ hex
+ default 0x0 if SPCR_OPT_UNSET
+ default 0x0 if SPCR_OPT_NONE
+ default 0x800000 if SPCR_OPT_SPEC_READ
+
+config SPCR_TSECEP
+ hex
+ default 0x0 if SPCR_TSECEP_UNSET
+ default 0x0 if SPCR_TSECEP_0
+ default 0x100 if SPCR_TSECEP_1
+ default 0x200 if SPCR_TSECEP_2
+ default 0x300 if SPCR_TSECEP_3
+
+config SPCR_TSEC1EP
+ hex
+ default 0x0 if SPCR_TSEC1EP_UNSET
+ default 0x0 if SPCR_TSEC1EP_0
+ default 0x100 if SPCR_TSEC1EP_1
+ default 0x200 if SPCR_TSEC1EP_2
+ default 0x300 if SPCR_TSEC1EP_3
+
+config SPCR_TSEC2EP
+ hex
+ default 0x0 if SPCR_TSEC2EP_UNSET
+ default 0x0 if SPCR_TSEC2EP_0
+ default 0x1 if SPCR_TSEC2EP_1
+ default 0x2 if SPCR_TSEC2EP_2
+ default 0x3 if SPCR_TSEC2EP_3
+
+endmenu
--- /dev/null
+#define SPCR_PCIHPE_MASK 0x10000000
+#define SPCR_PCIPR_MASK 0x03000000
+#define SPCR_OPT_MASK 0x00800000
+#define SPCR_TBEN_MASK 0x00400000
+#define SPCR_COREPR_MASK 0x00300000
+#define SPCR_TSEC1DP_MASK 0x00003000
+#define SPCR_TSEC1BDP_MASK 0x00000C00
+#define SPCR_TSEC1EP_MASK 0x00000300
+#define SPCR_TSEC2DP_MASK 0x00000030
+#define SPCR_TSEC2BDP_MASK 0x0000000C
+#define SPCR_TSEC2EP_MASK 0x00000003
+#define SPCR_TSECDP_MASK 0x00003000
+#define SPCR_TSECBDP_MASK 0x00000C00
+#define SPCR_TSECEP_MASK 0x00000300
+
+ const __be32 spcr_mask =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+ SPCR_OPT_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+ SPCR_TSECEP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+ SPCR_TSEC1EP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+ SPCR_TSEC2EP_MASK |
+#endif
+ 0;
+ const __be32 spcr_val =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+ CONFIG_SPCR_OPT |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+ CONFIG_SPCR_TSECEP |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+ CONFIG_SPCR_TSEC1EP |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+ CONFIG_SPCR_TSEC2EP |
+#endif
+ 0;
+
+ const __be32 lcrr_mask =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+ LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+ LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+ LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+ LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+ LCRR_CLKDIV |
+#endif
+ 0;
+
+ const __be32 lcrr_val =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+ CONFIG_LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+ CONFIG_LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+ CONFIG_LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+ CONFIG_LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+ CONFIG_LCRR_CLKDIV |
+#endif
+ 0;
--- /dev/null
+menu "LBLAW setup"
+
+choice
+ prompt "NAND LAWBAR for NAND SPL"
+
+config NAND_LBLAWBAR_PRELIM_NONE
+ bool "None"
+
+config NAND_LBLAWBAR_PRELIM_0
+ bool "0"
+ depends on LBLAW0
+
+config NAND_LBLAWBAR_PRELIM_1
+ bool "1"
+ depends on LBLAW1
+
+config NAND_LBLAWBAR_PRELIM_2
+ bool "2"
+ depends on LBLAW2
+
+config NAND_LBLAWBAR_PRELIM_3
+ bool "3"
+ depends on LBLAW3
+
+endchoice
+
+menuconfig LBLAW0
+ bool "LBLAW0"
+
+if LBLAW0
+
+config LBLAW0_ENABLE
+ bool "Window enable"
+ default "y"
+
+if !LBLAW0_ENABLE
+
+config LBLAW0_BASE
+ hex
+ default 0x0
+
+endif
+
+if LBLAW0_ENABLE
+
+config LBLAW0_NAME
+ string "Identifier"
+
+config LBLAW0_BASE
+ hex "Window base"
+
+choice
+ prompt "Window size"
+
+config LBLAW0_LENGTH_4_KBYTES
+ bool "4 kb"
+
+config LBLAW0_LENGTH_8_KBYTES
+ bool "8 kb"
+
+config LBLAW0_LENGTH_16_KBYTES
+ bool "16 kb"
+
+config LBLAW0_LENGTH_32_KBYTES
+ bool "32 kb"
+
+config LBLAW0_LENGTH_64_KBYTES
+ bool "64 kb"
+
+config LBLAW0_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config LBLAW0_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config LBLAW0_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config LBLAW0_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config LBLAW0_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config LBLAW0_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config LBLAW0_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config LBLAW0_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config LBLAW0_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config LBLAW0_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config LBLAW0_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config LBLAW0_LENGTH_256_MBYTES
+ bool "256 mb"
+
+config LBLAW0_LENGTH_512_MBYTES
+ bool "512 mb"
+
+config LBLAW0_LENGTH_1_GBYTES
+ bool "1 gb"
+
+config LBLAW0_LENGTH_2_GBYTES
+ bool "2 gb"
+
+endchoice
+
+endif # LBLAW0_ENABLE
+
+endif # LBLAW0
+
+config LBLAW0_ENABLE_BIT
+ hex
+ default 0x0 if !LBLAW0_ENABLE
+ default 0x80000000 if LBLAW0_ENABLE
+
+config LBLAW0_LENGTH
+ hex
+ default 0x0 if !LBLAW0_ENABLE
+ default 0x0000000B if LBLAW0_LENGTH_4_KBYTES
+ default 0x0000000C if LBLAW0_LENGTH_8_KBYTES
+ default 0x0000000D if LBLAW0_LENGTH_16_KBYTES
+ default 0x0000000E if LBLAW0_LENGTH_32_KBYTES
+ default 0x0000000F if LBLAW0_LENGTH_64_KBYTES
+ default 0x00000010 if LBLAW0_LENGTH_128_KBYTES
+ default 0x00000011 if LBLAW0_LENGTH_256_KBYTES
+ default 0x00000012 if LBLAW0_LENGTH_512_KBYTES
+ default 0x00000013 if LBLAW0_LENGTH_1_MBYTES
+ default 0x00000014 if LBLAW0_LENGTH_2_MBYTES
+ default 0x00000015 if LBLAW0_LENGTH_4_MBYTES
+ default 0x00000016 if LBLAW0_LENGTH_8_MBYTES
+ default 0x00000017 if LBLAW0_LENGTH_16_MBYTES
+ default 0x00000018 if LBLAW0_LENGTH_32_MBYTES
+ default 0x00000019 if LBLAW0_LENGTH_64_MBYTES
+ default 0x0000001A if LBLAW0_LENGTH_128_MBYTES
+ default 0x0000001B if LBLAW0_LENGTH_256_MBYTES
+ default 0x0000001C if LBLAW0_LENGTH_512_MBYTES
+ default 0x0000001D if LBLAW0_LENGTH_1_GBYTES
+ default 0x0000001E if LBLAW0_LENGTH_2_GBYTES
+
+menuconfig LBLAW1
+ bool "LBLAW1"
+
+if LBLAW1
+
+config LBLAW1_ENABLE
+ bool "Window enable"
+ default "y"
+
+if !LBLAW1_ENABLE
+
+config LBLAW1_BASE
+ hex
+ default 0x0
+
+endif
+
+if LBLAW1_ENABLE
+
+config LBLAW1_NAME
+ string "Identifier"
+
+config LBLAW1_BASE
+ hex "Window base"
+
+choice
+ prompt "Window size"
+
+config LBLAW1_LENGTH_4_KBYTES
+ bool "4 kb"
+
+config LBLAW1_LENGTH_8_KBYTES
+ bool "8 kb"
+
+config LBLAW1_LENGTH_16_KBYTES
+ bool "16 kb"
+
+config LBLAW1_LENGTH_32_KBYTES
+ bool "32 kb"
+
+config LBLAW1_LENGTH_64_KBYTES
+ bool "64 kb"
+
+config LBLAW1_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config LBLAW1_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config LBLAW1_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config LBLAW1_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config LBLAW1_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config LBLAW1_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config LBLAW1_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config LBLAW1_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config LBLAW1_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config LBLAW1_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config LBLAW1_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config LBLAW1_LENGTH_256_MBYTES
+ bool "256 mb"
+
+config LBLAW1_LENGTH_512_MBYTES
+ bool "512 mb"
+
+config LBLAW1_LENGTH_1_GBYTES
+ bool "1 gb"
+
+config LBLAW1_LENGTH_2_GBYTES
+ bool "2 gb"
+
+endchoice
+
+endif # LBLAW1_ENABLE
+
+endif # LBLAW1
+
+config LBLAW1_ENABLE_BIT
+ hex
+ default 0x0 if !LBLAW1_ENABLE
+ default 0x80000000 if LBLAW1_ENABLE
+
+config LBLAW1_LENGTH
+ hex
+ default 0x0 if !LBLAW1_ENABLE
+ default 0x0000000B if LBLAW1_LENGTH_4_KBYTES
+ default 0x0000000C if LBLAW1_LENGTH_8_KBYTES
+ default 0x0000000D if LBLAW1_LENGTH_16_KBYTES
+ default 0x0000000E if LBLAW1_LENGTH_32_KBYTES
+ default 0x0000000F if LBLAW1_LENGTH_64_KBYTES
+ default 0x00000010 if LBLAW1_LENGTH_128_KBYTES
+ default 0x00000011 if LBLAW1_LENGTH_256_KBYTES
+ default 0x00000012 if LBLAW1_LENGTH_512_KBYTES
+ default 0x00000013 if LBLAW1_LENGTH_1_MBYTES
+ default 0x00000014 if LBLAW1_LENGTH_2_MBYTES
+ default 0x00000015 if LBLAW1_LENGTH_4_MBYTES
+ default 0x00000016 if LBLAW1_LENGTH_8_MBYTES
+ default 0x00000017 if LBLAW1_LENGTH_16_MBYTES
+ default 0x00000018 if LBLAW1_LENGTH_32_MBYTES
+ default 0x00000019 if LBLAW1_LENGTH_64_MBYTES
+ default 0x0000001A if LBLAW1_LENGTH_128_MBYTES
+ default 0x0000001B if LBLAW1_LENGTH_256_MBYTES
+ default 0x0000001C if LBLAW1_LENGTH_512_MBYTES
+ default 0x0000001D if LBLAW1_LENGTH_1_GBYTES
+ default 0x0000001E if LBLAW1_LENGTH_2_GBYTES
+
+menuconfig LBLAW2
+ bool "LBLAW2"
+
+if LBLAW2
+
+config LBLAW2_ENABLE
+ bool "Window enable"
+ default "y"
+
+if !LBLAW2_ENABLE
+
+config LBLAW2_BASE
+ hex
+ default 0x0
+
+endif
+
+if LBLAW2_ENABLE
+
+config LBLAW2_NAME
+ string "Identifier"
+
+config LBLAW2_BASE
+ hex "Window base"
+
+choice
+ prompt "Window size"
+
+config LBLAW2_LENGTH_4_KBYTES
+ bool "4 kb"
+
+config LBLAW2_LENGTH_8_KBYTES
+ bool "8 kb"
+
+config LBLAW2_LENGTH_16_KBYTES
+ bool "16 kb"
+
+config LBLAW2_LENGTH_32_KBYTES
+ bool "32 kb"
+
+config LBLAW2_LENGTH_64_KBYTES
+ bool "64 kb"
+
+config LBLAW2_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config LBLAW2_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config LBLAW2_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config LBLAW2_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config LBLAW2_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config LBLAW2_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config LBLAW2_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config LBLAW2_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config LBLAW2_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config LBLAW2_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config LBLAW2_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config LBLAW2_LENGTH_256_MBYTES
+ bool "256 mb"
+
+config LBLAW2_LENGTH_512_MBYTES
+ bool "512 mb"
+
+config LBLAW2_LENGTH_1_GBYTES
+ bool "1 gb"
+
+config LBLAW2_LENGTH_2_GBYTES
+ bool "2 gb"
+
+endchoice
+
+endif # LBLAW2_ENABLE
+
+endif # LBLAW2
+
+config LBLAW2_ENABLE_BIT
+ hex
+ default 0x0 if !LBLAW2_ENABLE
+ default 0x80000000 if LBLAW2_ENABLE
+
+config LBLAW2_LENGTH
+ hex
+ default 0x0 if !LBLAW2_ENABLE
+ default 0x0000000B if LBLAW2_LENGTH_4_KBYTES
+ default 0x0000000C if LBLAW2_LENGTH_8_KBYTES
+ default 0x0000000D if LBLAW2_LENGTH_16_KBYTES
+ default 0x0000000E if LBLAW2_LENGTH_32_KBYTES
+ default 0x0000000F if LBLAW2_LENGTH_64_KBYTES
+ default 0x00000010 if LBLAW2_LENGTH_128_KBYTES
+ default 0x00000011 if LBLAW2_LENGTH_256_KBYTES
+ default 0x00000012 if LBLAW2_LENGTH_512_KBYTES
+ default 0x00000013 if LBLAW2_LENGTH_1_MBYTES
+ default 0x00000014 if LBLAW2_LENGTH_2_MBYTES
+ default 0x00000015 if LBLAW2_LENGTH_4_MBYTES
+ default 0x00000016 if LBLAW2_LENGTH_8_MBYTES
+ default 0x00000017 if LBLAW2_LENGTH_16_MBYTES
+ default 0x00000018 if LBLAW2_LENGTH_32_MBYTES
+ default 0x00000019 if LBLAW2_LENGTH_64_MBYTES
+ default 0x0000001A if LBLAW2_LENGTH_128_MBYTES
+ default 0x0000001B if LBLAW2_LENGTH_256_MBYTES
+ default 0x0000001C if LBLAW2_LENGTH_512_MBYTES
+ default 0x0000001D if LBLAW2_LENGTH_1_GBYTES
+ default 0x0000001E if LBLAW2_LENGTH_2_GBYTES
+
+menuconfig LBLAW3
+ bool "LBLAW3"
+
+if LBLAW3
+
+config LBLAW3_ENABLE
+ bool "Window enable"
+ default "y"
+
+if !LBLAW3_ENABLE
+
+config LBLAW3_BASE
+ hex
+ default 0x0
+
+endif
+
+if LBLAW3_ENABLE
+
+config LBLAW3_NAME
+ string "Identifier"
+
+config LBLAW3_BASE
+ hex "Window base"
+
+choice
+ prompt "Window size"
+
+config LBLAW3_LENGTH_4_KBYTES
+ bool "4 kb"
+
+config LBLAW3_LENGTH_8_KBYTES
+ bool "8 kb"
+
+config LBLAW3_LENGTH_16_KBYTES
+ bool "16 kb"
+
+config LBLAW3_LENGTH_32_KBYTES
+ bool "32 kb"
+
+config LBLAW3_LENGTH_64_KBYTES
+ bool "64 kb"
+
+config LBLAW3_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config LBLAW3_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config LBLAW3_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config LBLAW3_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config LBLAW3_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config LBLAW3_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config LBLAW3_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config LBLAW3_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config LBLAW3_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config LBLAW3_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config LBLAW3_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config LBLAW3_LENGTH_256_MBYTES
+ bool "256 mb"
+
+config LBLAW3_LENGTH_512_MBYTES
+ bool "512 mb"
+
+config LBLAW3_LENGTH_1_GBYTES
+ bool "1 gb"
+
+config LBLAW3_LENGTH_2_GBYTES
+ bool "2 gb"
+
+endchoice
+
+endif # LBLAW3_ENABLE
+
+endif # LBLAW3
+
+config LBLAW3_ENABLE_BIT
+ hex
+ default 0x0 if !LBLAW3_ENABLE
+ default 0x80000000 if LBLAW3_ENABLE
+
+config LBLAW3_LENGTH
+ hex
+ default 0x0 if !LBLAW3_ENABLE
+ default 0x0000000B if LBLAW3_LENGTH_4_KBYTES
+ default 0x0000000C if LBLAW3_LENGTH_8_KBYTES
+ default 0x0000000D if LBLAW3_LENGTH_16_KBYTES
+ default 0x0000000E if LBLAW3_LENGTH_32_KBYTES
+ default 0x0000000F if LBLAW3_LENGTH_64_KBYTES
+ default 0x00000010 if LBLAW3_LENGTH_128_KBYTES
+ default 0x00000011 if LBLAW3_LENGTH_256_KBYTES
+ default 0x00000012 if LBLAW3_LENGTH_512_KBYTES
+ default 0x00000013 if LBLAW3_LENGTH_1_MBYTES
+ default 0x00000014 if LBLAW3_LENGTH_2_MBYTES
+ default 0x00000015 if LBLAW3_LENGTH_4_MBYTES
+ default 0x00000016 if LBLAW3_LENGTH_8_MBYTES
+ default 0x00000017 if LBLAW3_LENGTH_16_MBYTES
+ default 0x00000018 if LBLAW3_LENGTH_32_MBYTES
+ default 0x00000019 if LBLAW3_LENGTH_64_MBYTES
+ default 0x0000001A if LBLAW3_LENGTH_128_MBYTES
+ default 0x0000001B if LBLAW3_LENGTH_256_MBYTES
+ default 0x0000001C if LBLAW3_LENGTH_512_MBYTES
+ default 0x0000001D if LBLAW3_LENGTH_1_GBYTES
+ default 0x0000001E if LBLAW3_LENGTH_2_GBYTES
+
+endmenu
--- /dev/null
+#if defined(CONFIG_LBLAW0)
+#define CONFIG_SYS_LBLAWBAR0_PRELIM \
+ CONFIG_LBLAW0_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM (\
+ CONFIG_LBLAW0_ENABLE_BIT |\
+ CONFIG_LBLAW0_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW1)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM \
+ CONFIG_LBLAW1_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM (\
+ CONFIG_LBLAW1_ENABLE_BIT |\
+ CONFIG_LBLAW1_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW2)
+#define CONFIG_SYS_LBLAWBAR2_PRELIM \
+ CONFIG_LBLAW2_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM (\
+ CONFIG_LBLAW2_ENABLE_BIT |\
+ CONFIG_LBLAW2_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW3)
+#define CONFIG_SYS_LBLAWBAR3_PRELIM \
+ CONFIG_LBLAW3_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM (\
+ CONFIG_LBLAW3_ENABLE_BIT |\
+ CONFIG_LBLAW3_LENGTH \
+)
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM
+#endif
#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
+int get_pcie_clk(int index)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 pci_sync_in;
+ u8 spmf;
+ u8 clkin_div;
+ u32 sccr;
+ u32 csb_clk;
+ u32 testval;
+
+ clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
+ sccr = im->clk.sccr;
+ pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+ spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+ csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
+
+ if (index)
+ testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
+ else
+ testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
+
+ switch (testval) {
+ case 0:
+ return 0;
+ case 1:
+ return csb_clk;
+ case 2:
+ return csb_clk / 2;
+ case 3:
+ return csb_clk / 3;
+ }
+
+ return 0;
+}
+
static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
/* Hose configure header is memory-mapped */
hose_cfg_base = (void *)pex;
- get_clocks();
/* Configure the PCIE controller core clock ratio */
out_le32(hose_cfg_base + PEX_GCLK_RATIO,
- (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
- / 1000000) * 16) / 333);
+ ((get_pcie_clk(bus) / 1000000) * 16) / 333);
udelay(1000000);
/* Do Type 1 bridge configuration */
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
puts(", 16-bit");
else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
/*
* Set up LAWBAR for all of DDR.
*/
- ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
debug("DDR:bar=0x%08x\n", ecm->bar);
debug("DDR:ar=0x%08x\n", ecm->ar);
/*
* Errata DDR6 work around: input enable 2 cycles earlier.
- * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
+ * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
*/
if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
if (caslat == 2)
else if (caslat == 4)
ddr->debug_reg = 0x202c0000; /* CL=3.0 */
- __asm__ __volatile__ ("sync");
+ sync();
debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
}
#endif
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
- asm("sync;isync");
+ sync();
+ isync();
udelay(600);
#endif
/* Enable controller, and GO! */
ddr->sdram_cfg = sdram_cfg;
- asm("sync;isync");
+ sync();
+ isync();
udelay(500);
debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
#endif /* CONFIG_SPD_EEPROM */
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+static inline u32 mftbu(void)
+{
+ u32 rval;
+
+ asm volatile("mftbu %0" : "=r" (rval));
+ return rval;
+}
+
+static inline u32 mftb(void)
+{
+ u32 rval;
+
+ asm volatile("mftb %0" : "=r" (rval));
+ return rval;
+}
+
/*
* Use timebase counter, get_timer() is not available
* at this point of initialization yet.
/* get the timebase ticks */
do {
- asm volatile ("mftbu %0":"=r" (tbu1):);
- asm volatile ("mftb %0":"=r" (tbl):);
- asm volatile ("mftbu %0":"=r" (tbu2):);
+ tbu1 = mftbu();
+ tbl = mftb();
+ tbu2 = mftbu();
} while (tbu1 != tbu2);
/* convert ticks to ms */
for (p = 0; p < (u64*)(size); p++) {
ppcDWstore((u32*)p, pattern);
}
- __asm__ __volatile__ ("sync");
+ sync();
#endif
t_end = get_tbms();
/* Enable errors for ECC */
ddr->err_disable &= ECC_ERROR_ENABLE;
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+ sync();
+ isync();
}
#endif /* CONFIG_DDR_ECC */
u32 lcrr;
u32 csb_clk;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
u32 usbdr_clk;
#endif
-#ifdef CONFIG_MPC834x
+#ifdef CONFIG_ARCH_MPC834X
u32 usbmph_clk;
#endif
u32 core_clk;
u32 i2c1_clk;
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
u32 i2c2_clk;
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
u32 tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
u32 enc_clk;
#endif
u32 lbiu_clk;
u32 lclk_clk;
u32 mem_clk;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
u32 mem_sec_clk;
#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
#endif
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_83XX_CLKIN)
- pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
+#if defined(CONFIG_SYS_CLK_FREQ)
+ pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif
sccr = im->clk.sccr;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
}
#endif
-#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
usbdr_clk = 0;
}
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
/* unknown SCCR_TSEC2CM value */
return -4;
}
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
tsec2_clk = tsec1_clk;
if (!(sccr & SCCR_TSEC1ON))
tsec2_clk = 0;
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
case 0:
usbmph_clk = 0;
return -6;
}
#endif
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
return -8;
}
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
case 0:
tdm_clk = 0;
}
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
i2c1_clk = tsec2_clk;
-#elif defined(CONFIG_MPC8360)
+#elif defined(CONFIG_ARCH_MPC8360)
i2c1_clk = csb_clk;
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC837X)
i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
i2c1_clk = csb_clk;
#endif
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
pciexp1_clk = 0;
}
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
(1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
mem_sec_clk = csb_clk * (1 +
((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif
#endif
gd->arch.csb_clk = csb_clk;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
gd->arch.tsec1_clk = tsec1_clk;
gd->arch.tsec2_clk = tsec2_clk;
gd->arch.usbdr_clk = usbdr_clk;
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
gd->arch.usbdr_clk = usbdr_clk;
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
gd->arch.usbmph_clk = usbmph_clk;
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
gd->arch.tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
#endif
gd->arch.core_clk = core_clk;
gd->arch.i2c1_clk = i2c1_clk;
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
gd->arch.i2c2_clk = i2c2_clk;
#endif
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
gd->arch.enc_clk = enc_clk;
#endif
gd->arch.lbiu_clk = lbiu_clk;
gd->arch.lclk_clk = lclk_clk;
gd->mem_clk = mem_clk;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
gd->arch.mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_QE)
gd->arch.qe_clk = qe_clk;
gd->arch.brg_clk = brg_clk;
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
gd->arch.pciexp1_clk = pciexp1_clk;
gd->arch.pciexp2_clk = pciexp2_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
gd->arch.sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
return gd->mem_clk;
}
+int get_serial_clock(void)
+{
+ return get_bus_freq(0);
+}
+
static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char buf[32];
printf(" Local Bus: %-4s MHz\n",
strmhz(buf, gd->arch.lclk_clk));
printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
printf(" DDR Secondary: %-4s MHz\n",
strmhz(buf, gd->arch.mem_sec_clk));
#endif
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
printf(" SEC: %-4s MHz\n",
strmhz(buf, gd->arch.enc_clk));
#endif
printf(" I2C1: %-4s MHz\n",
strmhz(buf, gd->arch.i2c1_clk));
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
printf(" I2C2: %-4s MHz\n",
strmhz(buf, gd->arch.i2c2_clk));
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
printf(" TDM: %-4s MHz\n",
strmhz(buf, gd->arch.tdm_clk));
#endif
printf(" SDHC: %-4s MHz\n",
strmhz(buf, gd->arch.sdhc_clk));
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
printf(" TSEC1: %-4s MHz\n",
strmhz(buf, gd->arch.tsec1_clk));
printf(" TSEC2: %-4s MHz\n",
strmhz(buf, gd->arch.tsec2_clk));
printf(" USB DR: %-4s MHz\n",
strmhz(buf, gd->arch.usbdr_clk));
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
printf(" USB DR: %-4s MHz\n",
strmhz(buf, gd->arch.usbdr_clk));
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
printf(" USB MPH: %-4s MHz\n",
strmhz(buf, gd->arch.usbmph_clk));
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
printf(" PCIEXP1: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp1_clk));
printf(" PCIEXP2: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp2_clk));
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
printf(" SATA: %-4s MHz\n",
strmhz(buf, gd->arch.sata_clk));
#endif
#include <common.h>
#include <mpc83xx.h>
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+
DECLARE_GLOBAL_DATA_PTR;
/*
/* system performance tweaking */
-#ifdef CONFIG_SYS_ACR_PIPE_DEP
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ CONFIG_ACR_PIPE_DEP;
#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT
+#ifndef CONFIG_ACR_RPTCNT_UNSET
/* Arbiter repeat count */
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+ CONFIG_ACR_RPTCNT;
#endif
#ifdef CONFIG_SYS_SPCR_OPT
while (*str)
putc(*str++);
}
+
+ulong get_bus_freq(ulong dummy)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+
+ return CONFIG_SYS_CLK_FREQ * spmf;
+}
#include <asm/mmu.h>
#include <asm/u-boot.h>
+#include "hrcw/hrcw.h"
+#include "bats/bats.h"
+#include "hid/hid.h"
+
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
mtspr SRR1, r3
rfi
- .globl ppcDWstore
-ppcDWstore:
- lfd 1, 0(r4)
- stfd 1, 0(r3)
- blr
-
- .globl ppcDWload
-ppcDWload:
- lfd 1, 0(r3)
- stfd 1, 0(r4)
- blr
-
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
#endif /* CONFIG_DEFAULT_IMMR */
--- /dev/null
+menu "System I/O configuration"
+
+if ARCH_MPC8308
+source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308"
+endif
+
+endmenu
--- /dev/null
+choice
+ prompt "SPI group"
+
+config SICR_SPI_SPI
+ bool "SPI"
+
+config SICR_SPI_MSRCID
+ bool "MSRCID"
+
+config SICR_SPI_LSRCID
+ bool "LSRCID"
+
+endchoice
+
+choice
+ prompt "UART group"
+
+config SICR_UART_SPI
+ bool "UART"
+
+config SICR_UART_MSRCID
+ bool "MSRCID"
+
+config SICR_UART_LSRCID
+ bool "LSRCID"
+
+endchoice
+
+choice
+ prompt "IRQ group"
+
+config SICR_IRQ_SPI
+ bool "IRQ"
+
+config SICR_IRQ_MCP_CKSTOP
+ bool "MCP/CKSTOP"
+
+config SICR_IRQ_INTA
+ bool "INTA"
+
+endchoice
+
+choice
+ prompt "I2C2 group"
+
+config SICR_I2C2_I2C
+ bool "IRQ"
+
+config SICR_I2C2_CKSTOP
+ bool "CKSTOP"
+
+endchoice
+
+choice
+ prompt "ETSEC1 A group"
+
+config SICR_ETSEC1_A_TSEC2
+ bool "TSEC1"
+
+config SICR_ETSEC1_A_TSEC_GTX_CLK125
+ bool "TSEC1 GTX_CLK125"
+
+endchoice
+
+choice
+ prompt "eSDHC A group"
+
+config SICR_ESDHC_A_SD
+ bool "SD"
+
+config SICR_ESDHC_A_GTM
+ bool "GTM"
+
+config SICR_ESDHC_A_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "eSDHC B group"
+
+config SICR_ESDHC_B_SD
+ bool "SD"
+
+config SICR_ESDHC_B_GTM
+ bool "GTM"
+
+config SICR_ESDHC_B_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "eSDHC C group"
+
+config SICR_ESDHC_C_SD
+ bool "SD"
+
+config SICR_ESDHC_C_GTM
+ bool "GTM"
+
+config SICR_ESDHC_C_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "GPIO A group"
+
+config SICR_GPIO_A_GPIO
+ bool "GPIO"
+
+config SICR_GPIO_A_TSEC2
+ bool "TSEC2"
+
+endchoice
+
+choice
+ prompt "GPIO B group"
+
+config SICR_GPIO_B_GPIO
+ bool "GPIO"
+
+config SICR_GPIO_B_TSEC2
+ bool "TSEC2"
+
+config SICR_GPIO_B_TSEC_GTX_CLK125
+ bool "TSEC2 GTX_CLK125"
+
+endchoice
+
+choice
+ prompt "IEEE1588 A group"
+
+config SICR_IEEE1588_A_TSEC
+ bool "TSEC"
+
+config SICR_IEEE1588_A_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "USB group"
+
+config SICR_USB_TSEC
+ bool "USB"
+
+endchoice
+
+choice
+ prompt "GTM group"
+
+config SICR_GTM_TSEC
+ bool "GTM"
+
+config SICR_GTM_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "IEEE1588 B group"
+
+config SICR_IEEE1588_B_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "ETSEC2 group"
+
+config SICR_ETSEC2_TSEC2
+ bool "TSEC2"
+
+config SICR_ETSEC2_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "GPIO selection"
+
+config SICR_GPIOSEL_GPIO
+ bool "GPIO_A, GPIO_B"
+
+config SICR_GPIOSEL_IEEE1588
+ bool "IEEE1588_A, IEEE1588_B, ETSEC2"
+
+endchoice
+
+choice
+ prompt "IEEE1588 timer output buffer impedance"
+
+config SICR_TMROBI_3_3_V
+ bool "40 Ohm, 3.3V"
+
+config SICR_TMROBI_2_5_V
+ bool "40 Ohm, 2.5V"
+
+endchoice
+
+choice
+ prompt "TSEC1 output buffer impedance"
+
+config SICR_TMSOBI1_3_3_V
+ bool "40 Ohm, 3.3V"
+
+config SICR_TMSOBI1_2_5_V
+ bool "40 Ohm, 2.5V"
+
+endchoice
+
+choice
+ prompt "TSEC2 output buffer impedance"
+
+config SICR_TMSOBI2_3_3_V
+ bool "40 Ohm, 3.3V"
+
+config SICR_TMSOBI2_2_5_V
+ bool "40 Ohm, 2.5V"
+
+endchoice
+
+config SICRL_SPI
+ hex
+ default 0x0 if SICR_SPI_SPI
+ default 0x10000000 if SICR_SPI_MSRCID
+ default 0x30000000 if SICR_SPI_LSRCID
+
+config SICRL_UART
+ hex
+ default 0x0 if SICR_UART_SPI
+ default 0x4000000 if SICR_UART_MSRCID
+ default 0xc000000 if SICR_UART_LSRCID
+
+config SICRL_IRQ
+ hex
+ default 0x0 if SICR_IRQ_SPI
+ default 0x1000000 if SICR_IRQ_MCP_CKSTOP
+ default 0x3000000 if SICR_IRQ_INTA
+
+config SICRL_I2C2
+ hex
+ default 0x0 if SICR_I2C2_I2C
+ default 0x100000 if SICR_I2C2_CKSTOP
+
+config SICRL_ETSEC1_A
+ hex
+ default 0x0 if SICR_ETSEC1_A_TSEC2
+ default 0x40 if SICR_ETSEC1_A_TSEC_GTX_CLK125
+
+config SICRH_ESDHC_A
+ hex
+ default 0x0 if SICR_ESDHC_A_SD
+ default 0x40000000 if SICR_ESDHC_A_GTM
+ default 0xc0000000 if SICR_ESDHC_A_GPIO
+
+config SICRH_ESDHC_B
+ hex
+ default 0x0 if SICR_ESDHC_B_SD
+ default 0x10000000 if SICR_ESDHC_B_GTM
+ default 0x30000000 if SICR_ESDHC_B_GPIO
+
+config SICRH_ESDHC_C
+ hex
+ default 0x0 if SICR_ESDHC_C_SD
+ default 0x4000000 if SICR_ESDHC_C_GTM
+ default 0xc000000 if SICR_ESDHC_C_GPIO
+
+config SICRH_GPIO_A
+ hex
+ default 0x0 if SICR_GPIO_A_GPIO
+ default 0x1000000 if SICR_GPIO_A_TSEC2
+
+config SICRH_GPIO_B
+ hex
+ default 0x0 if SICR_GPIO_B_GPIO
+ default 0x400000 if SICR_GPIO_B_TSEC2
+ default 0x800000 if SICR_GPIO_B_TSEC_GTX_CLK125
+
+config SICRH_IEEE1588_A
+ hex
+ default 0x100000 if SICR_IEEE1588_A_TSEC
+ default 0x300000 if SICR_IEEE1588_A_GPIO
+
+config SICRH_USB
+ hex
+ default 0x40000 if SICR_USB_TSEC
+
+config SICRH_GTM
+ hex
+ default 0x10000 if SICR_GTM_TSEC
+ default 0x30000 if SICR_GTM_GPIO
+
+config SICRH_IEEE1588_B
+ hex
+ default 0xc000 if SICR_IEEE1588_B_GPIO
+
+config SICRH_ETSEC2
+ hex
+ default 0x1000 if SICR_ETSEC2_TSEC2
+ default 0x3000 if SICR_ETSEC2_GPIO
+
+config SICRH_GPIOSEL
+ hex
+ default 0x0 if SICR_GPIOSEL_GPIO
+ default 0x100 if SICR_GPIOSEL_IEEE1588
+
+config SICRH_TMROBI
+ hex
+ default 0x0 if SICR_TMROBI_3_3_V
+ default 0x10 if SICR_TMROBI_2_5_V
+
+config SICRH_TMSOBI1
+ hex
+ default 0x0 if SICR_TMSOBI1_3_3_V
+ default 0x2 if SICR_TMSOBI1_2_5_V
+
+config SICRH_TMSOBI2
+ hex
+ default 0x0 if SICR_TMSOBI2_3_3_V
+ default 0x1 if SICR_TMSOBI2_2_5_V
--- /dev/null
+#ifdef CONFIG_ARCH_MPC8308
+
+#ifndef CONFIG_SYS_SICRL
+#define CONFIG_SYS_SICRL (\
+ CONFIG_SICRL_SPI |\
+ CONFIG_SICRL_UART |\
+ CONFIG_SICRL_IRQ |\
+ CONFIG_SICRL_I2C2 |\
+ CONFIG_SICRL_ETSEC1_A \
+)
+#endif
+
+#ifndef CONFIG_SYS_SICRH
+#define CONFIG_SYS_SICRH (\
+ CONFIG_SICRH_ESDHC_A |\
+ CONFIG_SICRH_ESDHC_B |\
+ CONFIG_SICRH_ESDHC_C |\
+ CONFIG_SICRH_GPIO_A |\
+ CONFIG_SICRH_GPIO_B |\
+ CONFIG_SICRH_IEEE1588_A |\
+ CONFIG_SICRH_USB |\
+ CONFIG_SICRH_GTM |\
+ CONFIG_SICRH_IEEE1588_B |\
+ CONFIG_SICRH_ETSEC2 |\
+ CONFIG_SICRH_GPIOSEL |\
+ CONFIG_SICRH_TMROBI |\
+ CONFIG_SICRH_TMSOBI1 |\
+ CONFIG_SICRH_TMSOBI2 \
+)
+#endif
+
+#endif
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
+ /*
+ * _end - This is end of u-boot.bin image.
+ * dtb will be appended here to make u-boot-dtb.bin
+ */
+ _end = .;
+
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
- imply CMD_SATA
config TARGET_T2080RDB
bool "Support T2080RDB"
select SUPPORT_SPL
select PHYS_64BIT
imply CMD_SATA
+ imply FSL_SATA
imply PANIC_HANG
config TARGET_T2081QDS
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
- imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
- imply FSL_SATA
config ARCH_T2081
bool
#include <common.h>
#include <asm/fsl_lbc.h>
+#ifdef CONFIG_MPC83xx
+#include "../mpc83xx/elbc/elbc.h"
+#endif
+
#ifdef CONFIG_MPC85xx
/* Boards should provide their own version of this if they use lbc sdram */
static void __lbc_sdram_init(void)
set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
}
- asm volatile("sync" : : : "memory");
+ sync();
/* Mark the ppace entry valid */
ppaace->addr_bitfields |= PAACE_V_VALID;
- asm volatile("sync" : : : "memory");
+ sync();
return 0;
}
out_be32(®s->splah, spaact_lim >> 32);
out_be32(®s->splal, (uint32_t)spaact_lim);
}
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
PAMU_PCR_PE);
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
}
out_be32(®s->splal, 0);
clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE);
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
}
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
}
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
+dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
targets += $(dtb-y)
--- /dev/null
+/*
+ * Gazerbeam CON Device Tree Source
+ *
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include "gdsys/mpc8308.dtsi"
+
+/include/ "gdsys/gazerbeam-base.dtsi"
+
+/include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi"
+/include/ "gdsys/soc/i2c/dallas-rtc.dtsi"
+/include/ "gdsys/soc/lbc/gazerbeam.dtsi"
+/include/ "gdsys/soc/nor/flash-80k-partition.dtsi"
+
+&board_lbc {
+ FPGA0:iocon_uart@1,0 {
+ reg = <0x1 0x0 0x100000>;
+ little-endian;
+ interrupts = <48 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ FPGA1:iocon_uart@2,0 {
+ reg = <0x2 0x0 0x100000>;
+ little-endian;
+ interrupts = <17 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+};
+
+&FPGA0 {
+ compatible = "gdsys,iocon_fpga";
+ #gpio-cells = <2>;
+ gpio-controller;
+ bus = <&FPGA0BUS>;
+ unit_id = <0>;
+ fpga-type = <1>;
+ usb_base = <0x0080>;
+ audio_base = <0x0040>;
+ timebase_base = <0x013c>;
+
+ /*
+ * for every interrupt source there must be a dataset specifying
+ * 1. type (1: standard)
+ * 2. status register offset
+ * 3. mask register offset
+ * 4. default mask
+ */
+ fpga_interrupt_sources =
+ <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
+ <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
+ /*
+ * for every interrupt there must be a dataset specifying
+ * 1. type (1: status, 2: event)
+ * 2. interrupt source index
+ * 3. interrupt register bit
+ * 4. mask register bit
+ */
+ #fpga_interrupt_map-cells = <4>;
+ fpga_interrupt_map =
+ <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
+ <1 0 0 0>, /* 1: VIDEO 0 */
+ <1 0 1 1>, /* 2: VIDEO 1 */
+ <1 0 2 2>, /* 3: VIDEO IC 0 */
+ <1 0 3 3>, /* 4: VIDEO IC 1 */
+ <1 0 4 4>, /* 5: IIC MAIN */
+ <1 0 6 6>, /* 6: IIC VIDEO 0 */
+ <1 0 7 7>, /* 7: IIC VIDEO 1 */
+ <1 1 0 0>, /* 8: OSD 0 */
+ <1 1 1 1>, /* 9: OSD 1 */
+ <1 1 2 2>, /* 10: SPDIF 0 */
+ <1 1 3 3>, /* 11: SPDIF 1 */
+ <1 0 12 12>, /* 12: COMM 0 */
+ <1 0 13 13>, /* 13: COMM 1 */
+ <1 0 10 10>, /* 14: COMM 2 */
+ <1 0 11 11>, /* 15: COMM 3 */
+ <2 0 5 5>, /* 16: MDIO */
+ <1 0 8 8>, /* 17: PHY */
+ <1 1 4 4>, /* 18: RS232 */
+ <1 1 5 5>, /* 19: AUDIO */
+ <1 1 8 8>, /* 20: PROC_AUDIO */
+ <1 1 7 7>, /* 21: USB/ETH-UART INT */
+ <2 1 10 10>, /* 22: AXI Bridge 0 */
+ <2 1 11 11>, /* 23: AXI Bridge 1 */
+ <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
+ <>;
+};
+
+&FPGA1 {
+ compatible = "gdsys,iocon_fpga";
+ #gpio-cells = <2>;
+ gpio-controller;
+ bus = <&FPGA1BUS>;
+ unit_id = <1>;
+ fpga-type = <1>;
+ usb_base = <0x0070>;
+ audio_base = <0x0040>;
+ timebase_base = <0x013c>;
+
+ /*
+ * for every interrupt source there must be a dataset specifying
+ * 1. type (1: standard)
+ * 2. status register offset
+ * 3. mask register offset
+ * 4. default mask
+ */
+ fpga_interrupt_sources =
+ <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
+ <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
+ /*
+ * for every interrupt there must be a dataset specifying
+ * 1. type (1: status, 2: event)
+ * 2. interrupt source index
+ * 3. interrupt register bit
+ * 4. mask register bit
+ */
+ #fpga_interrupt_map-cells = <4>;
+ fpga_interrupt_map =
+ <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
+ <1 0 0 0>, /* 1: VIDEO 0 */
+ <1 0 1 1>, /* 2: VIDEO 1 */
+ <1 0 2 2>, /* 3: VIDEO IC 0 */
+ <1 0 3 3>, /* 4: VIDEO IC 1 */
+ <1 0 4 4>, /* 5: IIC MAIN */
+ <1 0 6 6>, /* 6: IIC VIDEO 0 */
+ <1 0 7 7>, /* 7: IIC VIDEO 1 */
+ <1 1 0 0>, /* 8: OSD 0 */
+ <1 1 1 1>, /* 9: OSD 1 */
+ <1 1 2 2>, /* 10: SPDIF 0 */
+ <1 1 3 3>, /* 11: SPDIF 1 */
+ <1 0 12 12>, /* 12: COMM 0 */
+ <1 0 13 13>, /* 13: COMM 1 */
+ <1 0 10 10>, /* 14: COMM 2 */
+ <1 0 11 11>, /* 15: COMM 3 */
+ <2 0 5 5>, /* 16: MDIO */
+ <1 0 8 8>, /* 17: PHY */
+ <1 1 4 4>, /* 18: RS232 */
+ <1 1 5 5>, /* 19: AUDIO */
+ <1 1 8 8>, /* 20: PROC_AUDIO */
+ <1 1 7 7>, /* 21: USB/ETH-UART INT */
+ <2 1 10 10>, /* 22: AXI Bridge 0 */
+ <2 1 11 11>, /* 23: AXI Bridge 1 */
+ <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
+ <>;
+};
+
+/ {
+ FPGA0BUS: fpga0bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x00002000>;
+
+ compatible = "gdsys,soc";
+
+ fpga0_rs232 {
+ compatible = "gdsys,ihs_trans_rs232";
+ reg = <0x50 0x08>;
+ little-endian;
+ };
+
+ fpga0_uart_usb {
+ compatible = "gdsys,ihs_simple_uart";
+ reg = <0xa0 0x08>;
+ little-endian;
+ fpga_interrupts = <21>;
+ line = <0>;
+ };
+
+ fpga0_iic_main {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x60 0x10>;
+ little-endian;
+ fpga_interrupts = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_dp_video0_redriver: fpga0_dp_video0_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2c>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ fpga0_dp_video1_redriver: fpga0_dp_video1_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2e>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ lm77@48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+ ads1015@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+ ads1015@4b {
+ compatible = "ti,ads1015";
+ reg = <0x4b>;
+ };
+ };
+
+ fpga0_video0 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x100 0x40>;
+ little-endian;
+ fpga_interrupts = <1 8>; /* VIDEO OSD */
+ osd_base = <0x180>;
+ osd_buffer_base = <0x1000>;
+ spdif_audio_base = <0x1e0>;
+ video_index = <0>;
+ video_id = <0>;
+ fpga-force-pos-pol;
+ sync-source;
+ fpga-pb-pixels = <2730>; /* 8192 / 3 */
+ fpga-ra-lines = <2>;
+ video_tx = <&fpga0_dp_video0>;
+ clk_gen = <&fpga0_video0_clkgen>;
+ ddc_ci = <&fpga0_dp_video0>;
+ };
+
+ fpga0_iic_video0 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x1c0 0x10>;
+ little-endian;
+ fpga_interrupts = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_video0_clkgen: fpga0_video0_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <0>;
+ };
+ };
+
+ fpga0_axi_video0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x170 0x10>;
+ little-endian;
+ fpga_interrupts = <22>;
+
+ fpga0_dp_video0: fpga0_dp_video0 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ little-endian;
+ redriver = <&fpga0_dp_video0_redriver>;
+ video_id = <0>;
+ };
+ };
+
+ fpga0_video1 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x200 0x40>;
+ little-endian;
+ fpga_interrupts = <2 9>; /* VIDEO OSD */
+ osd_base = <0x280>;
+ osd_buffer_base = <0x2000>;
+ spdif_audio_base = <0x2e0>;
+ video_index = <1>;
+ video_id = <1>;
+ fpga-force-pos-pol;
+ sync-source;
+ fpga-pb-pixels = <2730>; /* 8192 / 3 */
+ fpga-ra-lines = <2>;
+ video_tx = <&fpga0_dp_video1>;
+ clk_gen = <&fpga0_video1_clkgen>;
+ ddc_ci = <&fpga0_dp_video1>;
+ };
+
+ fpga0_iic_video1 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x2c0 0x10>;
+ little-endian;
+ fpga_interrupts = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_video1_clkgen: fpga0_video1_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <1>;
+ };
+ };
+
+ fpga0_axi_video1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x270 0x10>;
+ little-endian;
+ fpga_interrupts = <23>;
+
+ fpga0_dp_video1: fpga0_dp_video1 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ little-endian;
+ redriver = <&fpga0_dp_video1_redriver>;
+ video_id = <1>;
+ };
+ };
+
+ fpga0_iic_usb {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0xb0 0x10>;
+ little-endian;
+ fpga_interrupts = <24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+
+ fpga0_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = < 0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+ little-endian;
+ irq-model-local;
+ fpga_interrupts = <12 13 14 15>;
+ pollcycle = <200>;
+ nprot_channel = <16>;
+ uart_line = <0>;
+ ep_index = <0>;
+ line_protocol = <1>;
+ };
+
+ fpga0_mdio {
+ compatible = "gdsys,ihs_mdiomaster";
+ reg = <0x0058 0x10>;
+ little-endian;
+ fpga_interrupts = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_phy0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <0>;
+ };
+ fpga0_phy1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <1>;
+ };
+ fpga0_phy2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <2>;
+ };
+ fpga0_phy3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <3>;
+ };
+ };
+
+ };
+
+
+ FPGA1BUS: fpga1bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x00002000>;
+
+ compatible = "gdsys,soc";
+
+ fpga1_uart_usb {
+ compatible = "gdsys,ihs_simple_uart";
+ reg = <0xa0 0x08>;
+ little-endian;
+ fpga_interrupts = <21>;
+ line = <4>; /* TODO check and FIX */
+ };
+
+ fpga1_iic_main {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x60 0x10>;
+ little-endian;
+ fpga_interrupts = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_dp_video0_redriver: fpga1_dp_video0_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2c>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ fpga1_dp_video1_redriver: fpga1_dp_video1_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2e>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ lm77@48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+ ads1015@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+ ads1015@4b {
+ compatible = "ti,ads1015";
+ reg = <0x4b>;
+ };
+ };
+
+ fpga1_video0 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x100 0x40>;
+ little-endian;
+ fpga_interrupts = <1 8>; /* VIDEO OSD */
+ osd_base = <0x180>;
+ osd_buffer_base = <0x1000>;
+ spdif_audio_base = <0x1e0>;
+ video_index = <0>;
+ video_id = <4>;
+ fpga-force-pos-pol;
+ sync-source;
+ fpga-pb-pixels = <2730>; /* 8192 / 3 */
+ fpga-ra-lines = <2>;
+ video_tx = <&fpga1_dp_video0>;
+ clk_gen = <&fpga1_video0_clkgen>;
+ ddc_ci = <&fpga1_dp_video0>;
+ };
+
+ fpga1_iic_video0 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x1c0 0x10>;
+ little-endian;
+ fpga_interrupts = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_video0_clkgen: fpga1_video0_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <4>;
+ };
+ };
+
+ fpga1_axi_video0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x170 0x10>;
+ little-endian;
+ fpga_interrupts = <22>;
+
+ fpga1_dp_video0: fpga1_dp_video0 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ little-endian;
+ redriver = <&fpga1_dp_video0_redriver>;
+ video_id = <4>;
+ };
+ };
+
+ fpga1_video1 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x200 0x40>;
+ little-endian;
+ fpga_interrupts = <2 9>; /* VIDEO OSD */
+ osd_base = <0x280>;
+ osd_buffer_base = <0x2000>;
+ spdif_audio_base = <0x2e0>;
+ video_index = <1>;
+ video_id = <5>;
+ fpga-force-pos-pol;
+ sync-source;
+ fpga-pb-pixels = <2730>; /* 8192 / 3 */
+ fpga-ra-lines = <2>;
+ video_tx = <&fpga1_dp_video1>;
+ clk_gen = <&fpga1_video1_clkgen>;
+ ddc_ci = <&fpga1_dp_video1>;
+ };
+
+ fpga1_iic_video1 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x2c0 0x10>;
+ little-endian;
+ fpga_interrupts = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_video1_clkgen: fpga1_video1_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <5>;
+ };
+ };
+
+ fpga1_axi_video1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x270 0x10>;
+ little-endian;
+ fpga_interrupts = <23>;
+
+ fpga1_dp_video1: fpga1_dp_video1 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ little-endian;
+ redriver = <&fpga1_dp_video1_redriver>;
+ video_id = <5>;
+ };
+ };
+
+ fpga1_iic_usb {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0xb0 0x10>;
+ little-endian;
+ fpga_interrupts = <24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+
+ fpga1_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = < 0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+ little-endian;
+ irq-model-local;
+ fpga_interrupts = <12 13 14 15>;
+ pollcycle = <200>;
+ nprot_channel = <17>;
+ uart_line = <1>;
+ ep_index = <0>;
+ line_protocol = <1>;
+ };
+
+ fpga1_mdio {
+ compatible = "gdsys,ihs_mdiomaster";
+ reg = <0x0058 0x10>;
+ little-endian;
+ fpga_interrupts = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_phy0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <0>;
+ };
+ fpga1_phy1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <1>;
+ };
+ fpga1_phy2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <2>;
+ };
+ fpga1_phy3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <3>;
+ };
+ };
+
+ };
+
+};
+
+#include "gdsys/gazerbeam-uboot.dtsi"
--- /dev/null
+/*
+ * Gazerbeam Device Tree Source
+ *
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "gdsys,gazerbeam";
+ compatible = "fsl,mpc8308rdb";
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ };
+
+ memory {
+ device_type = "memory";
+ };
+};
+
+&enet1 {
+ status = "okay";
+};
+
+&IIC {
+ fsl,preserve-clocking;
+
+ at97sc3205t@29 {
+ compatible = "atmel,at97sc3204t";
+ reg = <0x29>;
+ };
+
+ lm77@48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+
+ ads1015@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+
+ lm77@4a {
+ compatible = "national,lm77";
+ reg = <0x4a>;
+ };
+
+ emc2305@2e {
+ compatible = "smsc,emc2305";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2e>;
+ fan@0 {
+ reg = <0>;
+ };
+ fan@1 {
+ reg = <1>;
+ };
+ fan@2 {
+ reg = <2>;
+ };
+ fan@3 {
+ reg = <3>;
+ };
+ fan@4 {
+ reg = <4>;
+ };
+ };
+
+ emc2305@4c {
+ compatible = "smsc,emc2305";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4c>;
+ fan@0 {
+ reg = <0>;
+ };
+ fan@1 {
+ reg = <1>;
+ };
+ fan@2 {
+ reg = <2>;
+ };
+ fan@3 {
+ reg = <3>;
+ };
+ fan@4 {
+ reg = <4>;
+ };
+ };
+
+ at24c512@54 {
+ compatible = "atmel,24c512";
+ reg = <0x54>;
+ };
+
+ /* PPC-Board */
+ pca9698@22 {
+ compatible = "nxp,pca9698";
+ reg = <0x22>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ /* IO-Board */
+ pca9698@20 {
+ compatible = "nxp,pca9698";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};
+
+&IIC2 {
+ fsl,preserve-clocking;
+
+ status = "okay";
+
+ /* MC2/SC-Board */
+ GPIO_VB0: pca9698@20 {
+ compatible = "nxp,pca9698";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ /* MC4-Board */
+ GPIO_VB1: pca9698@22 {
+ compatible = "nxp,pca9698";
+ reg = <0x22>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};
+
+&SPI {
+ gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0
+ /*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0
+ /*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0
+ /*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0
+ /*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0
+ /*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>;
+
+ m25p16@0 {
+ compatible = "st,n25q128a11";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@1 {
+ compatible = "st,n25q128a11";
+ reg = <0x1>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@2 {
+ compatible = "st,m25p40";
+ reg = <0x2>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@3 {
+ compatible = "st,m25p40";
+ reg = <0x3>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@4 {
+ compatible = "st,m25p40";
+ reg = <0x4>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@5 {
+ compatible = "st,m25p40";
+ reg = <0x5>;
+ spi-max-frequency = <20000000>;
+ };
+};
--- /dev/null
+#include <dt-bindings/memory/mpc83xx-sdram.h>
+#include <dt-bindings/clk/mpc83xx-clk.h>
+
+/ {
+ aliases {
+ i2c0 = &IIC;
+ i2c1 = &IIC2;
+ i2c2 = "/fpga0bus/fpga0_iic_main";
+ i2c3 = "/fpga0bus/fpga0_iic_video0";
+ i2c4 = "/fpga0bus/fpga0_iic_video1";
+ i2c5 = "/fpga0bus/fpga0_iic_usb";
+ gdsys_soc0 = "/fpga0bus";
+ gdsys_soc1 = "/fpga1bus";
+ ioep0 = "/fpga0bus/fpga0_ep0";
+ ioep1 = "/fpga0bus/fpga1_ep0";
+ };
+
+ chosen {
+ stdout-path = &serial1;
+ };
+
+ cpus {
+ compatible = "cpu_bus";
+ u-boot,dm-pre-reloc;
+
+ PowerPC,8308@0 {
+ compatible = "fsl,mpc8308";
+ clocks = <&socclocks MPC83XX_CLK_CORE
+ &socclocks MPC83XX_CLK_CSB>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ board {
+ compatible = "gdsys,board_gazerbeam";
+ csb = <&board_soc>;
+ serdes = <&SERDES>;
+ rxaui0 = <&RXAUI0_0>;
+ rxaui1 = <&RXAUI0_1>;
+ rxaui2 = <&RXAUI0_2>;
+ rxaui3 = <&RXAUI0_3>;
+ rxaui4 = <&RXAUI1_0>;
+ rxaui5 = <&RXAUI1_1>;
+ rxaui6 = <&RXAUI1_2>;
+ rxaui7 = <&RXAUI1_3>;
+ fpga0 = <&FPGA0>;
+ fpga1 = <&FPGA1>;
+ ioep0 = <&IOEP0>;
+ ioep1 = <&IOEP1>;
+
+ ver-gpios = <&PPCPCA 12 0
+ &PPCPCA 13 0
+ &PPCPCA 14 0
+ &PPCPCA 15 0>;
+
+ /* MC2/SC-Board */
+ var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */
+ &GPIO_VB0 11 0>; /* VAR-CON */
+ /* MC4-Board */
+ var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */
+ &GPIO_VB1 11 0>; /* VAR-CON */
+
+ reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
+ };
+
+ socclocks: clocks {
+ compatible = "fsl,mpc8308-clk";
+ #clock-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ timer {
+ compatible = "fsl,mpc83xx-timer";
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+ };
+};
+
+&FPGA0 {
+ reset-gpios = <&PPCPCA 26 0>;
+ done-gpios = <&GPIO_VB0 19 0>;
+};
+
+&FPGA1 {
+ status = "disable";
+};
+
+&FPGA0BUS {
+ ranges = <0x0 0xe0600000 0x00004000>;
+ fpga = <&FPGA0>;
+
+ fpga0_video0 {
+ mode = "640_480_60";
+
+ status = "disabled";
+ };
+
+ RXAUI0_0: fpga0_rxaui@fc0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fc0 0x10>;
+ };
+
+ fpga0_iic_video0 {
+ status = "disabled";
+ };
+
+ fpga0_axi_video0 {
+ status = "disabled";
+ };
+
+ fpga0_video1 {
+ mode = "640_480_60";
+ status = "disabled";
+ };
+
+ fpga0_iic_video1 {
+ status = "disabled";
+ };
+
+ fpga0_axi_video1 {
+ status = "disabled";
+ };
+
+ IOEP0: fpga0_ep0 {
+ };
+
+ RXAUI0_1: fpga0_rxaui@fd0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fd0 0x10>;
+ };
+
+ RXAUI0_2: fpga0_rxaui@fe0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fe0 0x10>;
+ };
+
+ RXAUI0_3: fpga0_rxaui@ff0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0ff0 0x10>;
+ };
+};
+
+&FPGA1BUS {
+ ranges = <0x0 0xe0700000 0x00004000>;
+ fpga = <&FPGA1>;
+
+ status = "disable";
+
+ fpga1_video0 {
+ mode = "640_480_60";
+ };
+
+ RXAUI1_0: fpga0_rxaui@fc0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fc0 0x10>;
+ };
+
+ fpga1_video1 {
+ mode = "640_480_60";
+ };
+
+ IOEP1: fpga1_ep0 {
+ };
+
+ RXAUI1_1: fpga0_rxaui@fd0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fd0 0x10>;
+ };
+
+ RXAUI1_2: fpga0_rxaui@fe0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fe0 0x10>;
+ };
+
+ RXAUI1_3: fpga0_rxaui@ff0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0ff0 0x10>;
+ };
+};
+
+&board_soc {
+ u-boot,dm-pre-reloc;
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+
+ memory@2000 {
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhc@2e000 {
+ clocks = <&socclocks MPC83XX_CLK_SDHC>;
+ clock-names = "per";
+ };
+
+ SERDES: serdes@e3000 {
+ reg = <0xe3000 0x200>;
+ compatible = "fsl,mpc83xx-serdes";
+ proto = "pex";
+ serdes-clk = <100>;
+ vdd;
+ };
+};
+
+&IIC {
+ clocks = <&socclocks MPC83XX_CLK_I2C1>;
+
+ PPCPCA: pca9698@20 {
+ label = "ppc";
+ };
+
+ IOPCA: pca9698@22 {
+ label = "io";
+ };
+
+ at97sc3205t@29 {
+ u-boot,i2c-offset-len = <0>;
+ };
+};
+
+&IIC2 {
+ clocks = <&socclocks MPC83XX_CLK_I2C2>;
+
+ GPIO_VB0: pca9698@20 {
+ label = "mc2-sc";
+ };
+
+ GPIO_VB1: pca9698@22 {
+ label = "mc4";
+ };
+};
+
+&board_soc {
+ u-boot,dm-pre-reloc;
+};
+
+&GPIO_VB0 {
+ u-boot,dm-pre-reloc;
+};
+
+&serial0 {
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+ u-boot,dm-pre-reloc;
+};
+
+&serial1 {
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+ u-boot,dm-pre-reloc;
+};
+
+&pci0 {
+ clocks = <&socclocks MPC83XX_CLK_PCIEXP1>;
+};
--- /dev/null
+/*
+ * Basic platform for gdsys mpc8308 based devices
+ *
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * based on mpc8308rdb
+ * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/memory/mpc83xx-sdram.h>
+
+/ {
+ compatible = "fsl,mpc8308rdb";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8308@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <16384>;
+ i-cache-size = <16384>;
+ timebase-frequency = <0>; // from bootloader
+ bus-frequency = <0>; // from bootloader
+ clock-frequency = <0>; // from bootloader
+ };
+ };
+
+ board_lbc: localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <77 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ board_soc: immr@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8308-immr", "simple-bus";
+ ranges = <0 0xe0000000 0x00100000>;
+ reg = <0xe0000000 0x00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ device_type = "watchdog";
+ compatible = "mpc83xx_wdt";
+ reg = <0x200 0x100>;
+ };
+
+ memory@2000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc83xx-mem-controller";
+ reg = <0x2000 0x1000>;
+ device_type = "memory";
+
+ driver_software_override = <DSO_ENABLE>;
+ p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
+ n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
+ odt_termination_value = <ODT_TERMINATION_150_OHM>;
+ ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
+
+ clock_adjust = <CLOCK_ADJUST_05>;
+
+ read_to_write = <0>;
+ write_to_read = <0>;
+ read_to_read = <0>;
+ write_to_write = <0>;
+ active_powerdown_exit = <2>;
+ precharge_powerdown_exit = <6>;
+ odt_powerdown_exit = <8>;
+ mode_reg_set_cycle = <2>;
+
+ precharge_to_activate = <2>;
+ activate_to_precharge = <6>;
+ activate_to_readwrite = <2>;
+ mcas_latency = <CASLAT_40>;
+ refresh_recovery = <17>;
+ last_data_to_precharge = <2>;
+ activate_to_activate = <2>;
+ last_write_data_to_read = <2>;
+
+ additive_latency = <0>;
+ mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
+ write_latency = <3>;
+ read_to_precharge = <2>;
+ write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
+ minimum_cke_pulse_width = <3>;
+ four_activates_window = <5>;
+
+ self_refresh = <SREN_ENABLE>;
+ sdram_type = <TYPE_DDR2>;
+ databus_width = <DATA_BUS_WIDTH_32>;
+
+ force_self_refresh = <MODE_NORMAL>;
+ dll_reset = <DLL_RESET_ENABLE>;
+ dqs_config = <DQS_TRUE>;
+ odt_config = <ODT_ASSERT_READS>;
+ posted_refreshes = <1>;
+
+ refresh_interval = <2084>;
+ precharge_interval = <256>;
+
+ sdmode = <0x0242>;
+ esdmode = <0x0440>;
+
+ ram@0 {
+ reg = <0x0 0x0 0x8000000>;
+ compatible = "nanya,nt5tu64m16hg";
+
+ odt_rd_cfg = <ODT_RD_NEVER>;
+ odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
+ bank_bits = <3>;
+ row_bits = <13>;
+ col_bits = <10>;
+ };
+ };
+
+ IIC:i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <14 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ };
+
+ IIC2: i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <15 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ status = "disabled";
+ };
+
+ SPI:spi@7000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl,spi";
+ reg = <0x7000 0x1000>;
+ interrupts = <16 0x8>;
+ interrupt-parent = <&ipic>;
+ mode = "cpu";
+ };
+
+ sdhc@2e000 {
+ compatible = "fsl,esdhc", "fsl,mpc8308-esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <42 0x8>;
+ interrupt-parent = <&ipic>;
+ sdhci,auto-cmd12;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <133333333>;
+ interrupts = <9 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <133333333>;
+ interrupts = <10 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ gpio0: gpio@c00 {
+ #gpio-cells = <2>;
+ device_type = "gpio";
+ compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
+ reg = <0xc00 0x18>;
+ interrupts = <74 0x8>;
+ interrupt-parent = <&ipic>;
+ gpio-controller;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: interrupt-controller@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x700 0x100>;
+ device_type = "ipic";
+ };
+
+ ipic-msi@7c0 {
+ compatible = "fsl,ipic-msi";
+ reg = <0x7c0 0x40>;
+ msi-available-ranges = <0x0 0x100>;
+ interrupts = < 0x43 0x8
+ 0x4 0x8
+ 0x51 0x8
+ 0x52 0x8
+ 0x56 0x8
+ 0x57 0x8
+ 0x58 0x8
+ 0x59 0x8 >;
+ interrupt-parent = < &ipic >;
+ };
+
+ dma@2c000 {
+ compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
+ reg = <0x2c000 0x1800>;
+ interrupts = <3 0x8
+ 94 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar", "fsl,tsec";
+ reg = <0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <32 0x8 33 0x8 34 0x8>;
+ interrupt-parent = <&ipic>;
+ tbi-handle = < &tbi0 >;
+ phy-handle = < &phy1 >;
+ fsl,magic-packet;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+ phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy@0 {
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar", "fsl,tsec";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 0x8 36 0x8 37 0x8>;
+ interrupt-parent = <&ipic>;
+ phy-handle = < &phy2 >;
+ status = "disabled";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+ };
+
+ pci0: pcie@e0009000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
+ reg = <0xe0009000 0x00001000
+ 0xb0000000 0x01000000>;
+ ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+ 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
+ bus-range = <0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0 0 0 1 &ipic 1 8
+ 0 0 0 2 &ipic 1 8
+ 0 0 0 3 &ipic 1 8
+ 0 0 0 4 &ipic 1 8>;
+ interrupts = <0x1 0x8>;
+ interrupt-parent = <&ipic>;
+ clock-frequency = <0>;
+
+ pcie@0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ reg = <0 0 0 0 0>;
+ ranges = <0x02000000 0 0xa0000000
+ 0x02000000 0 0xa0000000
+ 0 0x10000000
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00800000>;
+ };
+ };
+};
--- /dev/null
+&IIC {
+ cs4265@4f {
+ compatible = "cirrus,cs4265";
+ reg = <0x0000004f>;
+ };
+};
--- /dev/null
+&IIC {
+ ds1339@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
--- /dev/null
+&board_lbc {
+ ranges = <0x0 0x0 0xfe000000 0x00800000
+ 0x1 0x0 0xe0600000 0x00003000
+ 0x2 0x0 0xe0700000 0x00003000>;
+};
--- /dev/null
+&board_lbc {
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x100000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0x80000>;
+ };
+ env@80000 {
+ reg = <0x80000 0x10000>;
+ };
+ env1@90000 {
+ reg = <0x90000 0x10000>;
+ };
+ };
+};
device_type = "open-pic";
clock-frequency = <0x0>;
};
+
+ esdhc: esdhc@114000 {
+ compatible = "fsl,esdhc";
+ reg = <0x114000 0x1000>;
+ interrupts = <48 2 0 0>;
+ clock-frequency = <0>;
+ sdhci,auto-cmd12;
+ bus-width = <4>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ };
+
+ usb0: usb@210000 {
+ compatible = "fsl-usb2-mph";
+ reg = <0x210000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <44 0x2 0 0>;
+ phy_type = "utmi";
+ };
+
+ usb1: usb@211000 {
+ compatible = "fsl-usb2-dr";
+ reg = <0x211000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <45 0x2 0 0>;
+ dr_mode = "host";
+ phy_type = "utmi";
+ };
+
+ sata0: sata@220000 {
+ compatible = "fsl,pq-sata-v2";
+ reg = <0x220000 0x1000>;
+ interrupts = <68 0x2 0 0>;
+ sata-number = <0x0>;
+ sata-fpdma = <0x0>;
+ };
+
+ sata1: sata@221000 {
+ compatible = "fsl,pq-sata-v2";
+ reg = <0x221000 0x1000>;
+ interrupts = <69 0x2 0 0>;
+ sata-number = <0x0>;
+ sata-fpdma = <0x0>;
+ };
};
};
--- /dev/null
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_POWERPC_CLOCK_H
+#define __ASM_POWERPC_CLOCK_H
+
+/* Make fsl_esdhc driver happy */
+enum mxc_clock {
+ MXC_ESDHC_CLK,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+uint mxc_get_clock(int clk)
+{
+ return gd->arch.sdhc_clk;
+}
+#endif /* __ASM_POWERPC_CLOCK_H */
/*
* The MCP83xx's 1-2 GPIO controllers each with 32 bits.
*/
-#if defined(CONFIG_MPC8313) || defined(CONFIG_MPC8308) || \
- defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
+ defined(CONFIG_ARCH_MPC8315)
#define MPC83XX_GPIO_CTRLRS 1
-#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
#define MPC83XX_GPIO_CTRLRS 2
#else
#define MPC83XX_GPIO_CTRLRS 0
#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)
+struct mpc8xxx_gpio_plat {
+ ulong addr;
+ unsigned long size;
+ uint ngpios;
+};
+
+#ifndef DM_GPIO
void mpc83xx_gpio_init_f(void);
void mpc83xx_gpio_init_r(void);
+#endif /* DM_GPIO */
#endif /* MPC83XX_GPIO_H_ */
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
-#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360)
+#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
#define BR_MS_FCM 0x00000020 /* FCM */
#endif
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#elif defined(CONFIG_MPC85xx)
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
-#if !defined(CONFIG_MPC834x)
+#if !defined(CONFIG_ARCH_MPC834X)
#define BR_ATOM 0x0000000C
#define BR_ATOM_SHIFT 2
#endif
#define UPMB 1
#define UPMC 2
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
#else
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EHTR_CLEAR 0x00000000
#define OR_GPCM_EHTR_SET 0x00000002
-#if !defined(CONFIG_MPC8308)
+#if !defined(CONFIG_ARCH_MPC8308)
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
#endif
#define LSDMR_BSMA1516 (3 << (31 - 10))
#define LSDMR_BSMA1617 (4 << (31 - 10))
#define LSDMR_RFCR5 (3 << (31 - 16))
+#define LSDMR_RFCR8 (5 << (31 - 16))
#define LSDMR_RFCR16 (7 << (31 - 16))
#define LSDMR_PRETOACT3 (3 << (31 - 19))
+#define LSDMR_PRETOACT6 (5 << (31 - 19))
#define LSDMR_PRETOACT7 (7 << (31 - 19))
#define LSDMR_ACTTORW3 (3 << (31 - 22))
#define LSDMR_ACTTORW7 (7 << (31 - 22))
#define LSDMR_ACTTORW6 (6 << (31 - 22))
#define LSDMR_BL8 (1 << (31 - 23))
#define LSDMR_WRC2 (2 << (31 - 27))
+#define LSDMR_WRC3 (3 << (31 - 27))
#define LSDMR_WRC4 (0 << (31 - 27))
#define LSDMR_BUFCMD (1 << (31 - 29))
#define LSDMR_CL3 (3 << (31 - 31))
#else
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
-# elif defined(CONFIG_MPC8309)
+# elif defined(CONFIG_ARCH_MPC8309)
u32 usbdr_clk;
# endif
-# if defined(CONFIG_MPC834x)
+# if defined(CONFIG_ARCH_MPC834X)
u32 usbmph_clk;
-# endif /* CONFIG_MPC834x */
-# if defined(CONFIG_MPC8315)
+# endif /* CONFIG_ARCH_MPC834X */
+# if defined(CONFIG_ARCH_MPC8315)
u32 tdm_clk;
# endif
u32 core_clk;
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
-# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
# endif
-# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
# endif
-# if defined(CONFIG_MPC8360)
+# if defined(CONFIG_ARCH_MPC8360)
u32 mem_sec_clk;
-# endif /* CONFIG_MPC8360 */
+# endif /* CONFIG_ARCH_MPC8360 */
#endif
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 obir; /* Output Buffer Impedance Register */
u8 res8[0xC];
u32 pecr1; /* PCI Express control register 1 */
-#if defined(CONFIG_MPC830x)
+#if defined(CONFIG_ARCH_MPC830X)
u32 sdhccr; /* eSDHC Control Registers for MPC830x */
#else
u32 pecr2; /* PCI Express control register 2 */
#endif
-#if defined(CONFIG_MPC8309)
+#if defined(CONFIG_ARCH_MPC8309)
u32 can_dbg_ctrl;
u32 res9a;
u32 gpr1;
* On Chip ROM
*/
typedef struct rom83xx {
-#if defined(CONFIG_MPC8309)
+#if defined(CONFIG_ARCH_MPC8309)
u8 mem[0x8000];
#else
u8 mem[0x10000];
u8 fixme[0x2000];
} tdmdmac83xx_t;
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
u8 res7[0xC0000];
} immap_t;
-#ifndef CONFIG_MPC834x
+#ifndef CONFIG_ARCH_MPC834X
#ifdef CONFIG_HAS_FSL_MPH_USB
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
#endif
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
u8 res7[0xC0000];
} immap_t;
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8315)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
gpio83xx_t gpio[1]; /* General purpose I/O module */
u8 res0[0x1300];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
- fsl_i2c_t i2c[2]; /* I2C Controllers */
- u8 res1[0x1300];
+ fsl_i2c_t i2c[1]; /* I2C Controllers */
+ u8 res1[0x1400];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res12[0x1CF00];
} immap_t;
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC8308)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[1]; /* Global Timers Module */
+ u8 res0[0x100];
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[1]; /* General purpose I/O module */
+ u8 res1[0x1300];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res2[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res3[0x900];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res4[0x1000];
+ spi8xxx_t spi; /* Serial Peripheral Interface */
+ u8 res5[0x1000];
+ pex83xx_t pciexp[1]; /* PCI Express Controller */
+ u8 res6[0x19000];
+ usb83xx_t usb[1]; /* USB DR Controller */
+ tsec83xx_t tsec[2];
+ u8 res7[0x6000];
+ tdmdmac83xx_t tdmdmac; /* TDM DMAC */
+ sdhc83xx_t sdhc; /* SDHC Controller */
+ u8 res8[0xb4000];
+ serdes83xx_t serdes[1]; /* SerDes Registers */
+ u8 res9[0x1CF00];
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC837X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rom83xx_t rom; /* On Chip ROM */
} immap_t;
-#elif defined(CONFIG_MPC8360)
+#elif defined(CONFIG_ARCH_MPC8360)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
u8 qe[0x100000]; /* QE block */
} immap_t;
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
u8 res8[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
#endif
#define CONFIG_SYS_MPC83xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define CONFIG_SYS_MPC83xx_USB2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
#endif
#include <asm/types.h>
-#if defined(CONFIG_MPC8308) || \
- defined(CONFIG_MPC8313) || \
- defined(CONFIG_MPC8315) || \
- defined(CONFIG_MPC834x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || \
+ defined(CONFIG_ARCH_MPC8313) || \
+ defined(CONFIG_ARCH_MPC8315) || \
+ defined(CONFIG_ARCH_MPC834X) || \
+ defined(CONFIG_ARCH_MPC837X)
typedef struct spi8xxx {
u8 res0[0x20]; /* 0x0-0x01f reserved */
#endif
#endif
-
-/* what kind of prep workstation we are */
-extern int _prep_type;
-/*
- * This is used to identify the board type from a given PReP board
- * vendor. Board revision is also made available.
- */
-extern unsigned char ucSystemType;
-extern unsigned char ucBoardRev;
-extern unsigned char ucBoardRevMaj, ucBoardRevMin;
-
struct task_struct;
-void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
-void release_thread(struct task_struct *);
-
-/*
- * Create a new kernel thread.
- */
-extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-/*
- * Bus types
- */
-#define EISA_bus 0
-#define EISA_bus__is_a_macro /* for versions in ksyms.c */
-#define MCA_bus 0
-#define MCA_bus__is_a_macro /* for versions in ksyms.c */
-
-/* Lazy FPU handling on uni-processor */
-extern struct task_struct *last_task_used_math;
-extern struct task_struct *last_task_used_altivec;
-
-/*
- * this is the minimum allowable io space due to the location
- * of the io areas on prep (first one at 0x80000000) but
- * as soon as I get around to remapping the io areas with the BATs
- * to match the mac we can raise this. -- Cort
- */
-#define TASK_SIZE (0x80000000UL)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-struct thread_struct {
- unsigned long ksp; /* Kernel stack pointer */
- unsigned long wchan; /* Event task is sleeping on */
- struct pt_regs *regs; /* Pointer to saved register state */
- mm_segment_t fs; /* for get_fs() validation */
- void *pgdir; /* root of page-table tree */
- signed long last_syscall;
- double fpr[32]; /* Complete floating point set */
- unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
- unsigned long fpscr; /* Floating point status */
-#ifdef CONFIG_ALTIVEC
- vector128 vr[32]; /* Complete AltiVec set */
- vector128 vscr; /* AltiVec status */
- unsigned long vrsave;
-#endif /* CONFIG_ALTIVEC */
-};
-
-#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
-
-#define INIT_THREAD { \
- INIT_SP, /* ksp */ \
- 0, /* wchan */ \
- (struct pt_regs *)INIT_SP - 1, /* regs */ \
- KERNEL_DS, /*fs*/ \
- swapper_pg_dir, /* pgdir */ \
- 0, /* last_syscall */ \
- {0}, 0, 0 \
-}
-
-/*
- * Note: the vm_start and vm_end fields here should *not*
- * be in kernel space. (Could vm_end == vm_start perhaps?)
- */
-#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
- PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
- 1, NULL, NULL }
-
-/*
- * Return saved PC of a blocked thread. For now, this is the "user" PC
- */
-static inline unsigned long thread_saved_pc(struct thread_struct *t)
-{
- return (t->regs) ? t->regs->nip : 0;
-}
-
-#define copy_segments(tsk, mm) do { } while (0)
-#define release_segments(mm) do { } while (0)
-#define forget_segments() do { } while (0)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
-#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
-
-/*
- * NOTE! The task struct and the stack go together
- */
-#define THREAD_SIZE (2*PAGE_SIZE)
-#define alloc_task_struct() \
- ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
-#define free_task_struct(p) free_pages((unsigned long)(p),1)
-#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
-
-/* in process.c - for early bootup debug -- Cort */
-int ll_printk(const char *, ...);
-void ll_puts(const char *);
-
-#define init_task (init_task_union.task)
-#define init_stack (init_task_union.stack)
-
-/* In misc.c */
-void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
#ifndef CONFIG_CPU_MPC83XX
int prt_83xx_rsr(void);
config TARGET_AX25_AE350
bool "Support ax25-ae350"
+config TARGET_MICROCHIP_ICICLE
+ bool "Support Microchip PolarFire-SoC Icicle Board"
+
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
endchoice
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
+source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/fu540/Kconfig"
# platform-specific options below
default y if RISCV_SMODE
depends on SMP
+config XIP
+ bool "XIP mode"
+ help
+ XIP (eXecute In Place) is a method for executing code directly
+ from a NOR flash memory without copying the code to ram.
+ Say yes here if U-Boot boots from flash directly.
+
config STACK_SIZE_SHIFT
int
default 13
void icache_enable(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
void icache_disable(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence.i\n\t"
void dcache_enable(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
void dcache_disable(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence\n\t"
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
+#ifdef CONFIG_OF_PRIOR_STAGE
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#endif
+#ifndef CONFIG_XIP
u32 hart_lottery __attribute__((section(".data"))) = 0;
/*
* finished initialization of global data.
*/
u32 available_harts_lock = 1;
+#endif
static inline bool supports_extension(char ext)
{
mv sp, a0
#endif
+#ifndef CONFIG_XIP
/*
* Pick hart to initialize global data and run U-Boot. The other harts
* wait for initialization to complete.
li s2, 1
amoswap.w s2, t1, 0(t0)
bnez s2, wait_for_gd_init
+#else
+ bnez tp, secondary_hart_loop
+#endif
+#ifdef CONFIG_OF_PRIOR_STAGE
la t0, prior_stage_fdt_address
SREG s1, 0(t0)
+#endif
jal board_init_f_init_reserve
/* save the boot hart id to global_data */
SREG tp, GD_BOOT_HART(gp)
+#ifndef CONFIG_XIP
la t0, available_harts_lock
fence rw, w
amoswap.w zero, zero, 0(t0)
* secondary_hart_loop.
*/
bnez s2, secondary_hart_loop
+#endif
/* Enable cache */
jal icache_enable
#ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
+#ifndef CONFIG_XIP
ulong available_harts;
+#endif
};
#include <asm-generic/global_data.h>
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ * Authors:
+ * Atish Patra <atish.patra@wdc.com>
+ * Based on arm/lib/image.c
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <errno.h>
+#include <linux/sizes.h>
+#include <linux/stddef.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ASCII version of "RISCV" defined in Linux kernel */
+#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952
+
+struct linux_image_h {
+ uint32_t code0; /* Executable code */
+ uint32_t code1; /* Executable code */
+ uint64_t text_offset; /* Image load offset */
+ uint64_t image_size; /* Effective Image size */
+ uint64_t res1; /* reserved */
+ uint64_t res2; /* reserved */
+ uint64_t res3; /* reserved */
+ uint64_t magic; /* Magic number */
+ uint32_t res4; /* reserved */
+ uint32_t res5; /* reserved */
+};
+
+int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
+ bool force_reloc)
+{
+ struct linux_image_h *lhdr;
+
+ lhdr = (struct linux_image_h *)map_sysmem(image, 0);
+
+ if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
+ puts("Bad Linux RISCV Image magic!\n");
+ return -EINVAL;
+ }
+
+ if (lhdr->image_size == 0) {
+ puts("Image lacks image_size field, error!\n");
+ return -EINVAL;
+ }
+ *size = lhdr->image_size;
+ *relocated_addr = gd->ram_base + lhdr->text_offset;
+
+ unmap_sysmem(lhdr);
+
+ return 0;
+}
continue;
}
+#ifndef CONFIG_XIP
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;
+#endif
gd->arch.ipi[reg].addr = ipi->addr;
gd->arch.ipi[reg].arg0 = ipi->arg0;
menu "SuperH architecture"
depends on SH
-config CPU_SH2
- bool
-
-config CPU_SH2A
- bool
- select CPU_SH2
-
-config CPU_SH3
- bool
-
config CPU_SH4
bool
prompt "Target select"
optional
-config TARGET_RSK7203
- bool "RSK+ 7203"
- select CPU_SH2A
-
-config TARGET_RSK7264
- bool "RSK2+SH7264"
- select CPU_SH2A
-
-config TARGET_RSK7269
- bool "RSK2+SH7269"
- select CPU_SH2A
-
-config TARGET_MPR2
- bool "Magic Panel Release 2 board"
- select CPU_SH3
-
-config TARGET_MS7720SE
- bool "Support ms7720se"
- select CPU_SH3
-
-config TARGET_SHMIN
- bool "SHMIN"
- select CPU_SH3
-
config TARGET_ESPT
bool "Data Technology ESPT-GIGA board"
select CPU_SH4
bool "Renesas AP-325RXA"
select CPU_SH4
-config TARGET_ECOVEC
- bool "EcoVec"
- select CPU_SH4A
-
config TARGET_MIGOR
bool "Migo-R"
select CPU_SH4
bool "SH7763RDP"
select CPU_SH4
-config TARGET_SH7785LCR
- bool "SH7785LCR"
- select CPU_SH4A
-
endchoice
config SYS_ARCH
default "sh"
config SYS_CPU
- default "sh2" if CPU_SH2
- default "sh3" if CPU_SH3
default "sh4" if CPU_SH4
source "arch/sh/lib/Kconfig"
source "board/alphaproject/ap_sh4a_4a/Kconfig"
source "board/espt/Kconfig"
-source "board/mpr2/Kconfig"
-source "board/ms7720se/Kconfig"
source "board/ms7722se/Kconfig"
source "board/ms7750se/Kconfig"
source "board/renesas/MigoR/Kconfig"
source "board/renesas/ap325rxa/Kconfig"
-source "board/renesas/ecovec/Kconfig"
source "board/renesas/r0p7734/Kconfig"
source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig"
-source "board/renesas/rsk7203/Kconfig"
-source "board/renesas/rsk7264/Kconfig"
-source "board/renesas/rsk7269/Kconfig"
source "board/renesas/sh7752evb/Kconfig"
source "board/renesas/sh7753evb/Kconfig"
source "board/renesas/sh7757lcr/Kconfig"
source "board/renesas/sh7763rdp/Kconfig"
-source "board/renesas/sh7785lcr/Kconfig"
-source "board/shmin/Kconfig"
endmenu
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-# Copyright (C) 2008 Renesas Solutions Corp.
-
-obj-y = cpu.o interrupts.o watchdog.o
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2007-2008
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-ENDIANNESS += -EB
-
-ifdef CONFIG_CPU_SH2A
-PLATFORM_CPPFLAGS += -m2a-nofpu -mb
-else # SH2
-PLATFORM_CPPFLAGS += -m3e -mb
-endif
-PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic)
-
-PLATFORM_LDFLAGS += $(ENDIANNESS)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#define STBCR4 0xFFFE040C
-#define cmt_clock_enable() do {\
- writeb(readb(STBCR4) & ~0x04, STBCR4);\
- } while (0)
-#define scif0_enable() do {\
- writeb(readb(STBCR4) & ~0x80, STBCR4);\
- } while (0)
-#define scif3_enable() do {\
- writeb(readb(STBCR4) & ~0x10, STBCR4);\
- } while (0)
-
-int checkcpu(void)
-{
- puts("CPU: SH2\n");
- return 0;
-}
-
-int cpu_init(void)
-{
- /* SCIF enable */
-#if defined(CONFIG_CONS_SCIF3)
- scif3_enable();
-#else
- scif0_enable();
-#endif
- /* CMT clock enable */
- cmt_clock_enable() ;
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- disable_interrupts();
- return 0;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- disable_interrupts();
- reset_cpu(0);
- return 0;
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-
-}
-
-void icache_enable(void)
-{
-}
-
-void icache_disable(void)
-{
-}
-
-int icache_status(void)
-{
- return 0;
-}
-
-void dcache_enable(void)
-{
-}
-
-void dcache_disable(void)
-{
-}
-
-int dcache_status(void)
-{
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#include <common.h>
-
-int interrupt_init(void)
-{
- return 0;
-}
-
-void enable_interrupts(void)
-{
-
-}
-
-int disable_interrupts(void)
-{
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008,2010 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C) 2008,2010 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-
-int watchdog_init(void)
-{
- return 0;
-}
-
-void reset_cpu(unsigned long ignored)
-{
- /* Address error with SR.BL=1 first. */
- trigger_address_error();
-
- while (1)
- ;
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# (C) Copyright 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-
-obj-y = cpu.o interrupts.o watchdog.o
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# (C) Copyright 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-PLATFORM_CPPFLAGS += -m3
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-
-int checkcpu(void)
-{
- puts("CPU: SH3\n");
- return 0;
-}
-
-int cpu_init(void)
-{
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- disable_interrupts();
- return 0;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- disable_interrupts();
- reset_cpu(0);
- return 0;
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-
-}
-
-void icache_enable(void)
-{
-}
-
-void icache_disable(void)
-{
-}
-
-int icache_status(void)
-{
- return 0;
-}
-
-void dcache_enable(void)
-{
-}
-
-void dcache_disable(void)
-{
-}
-
-int dcache_status(void)
-{
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#include <common.h>
-
-int interrupt_init(void)
-{
- return 0;
-}
-
-void enable_interrupts(void)
-{
-
-}
-
-int disable_interrupts(void)
-{
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- *
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-
-int watchdog_init(void)
-{
- return 0;
-}
-
-void reset_cpu(unsigned long ignored)
-{
- /* Address error with SR.BL=1 first. */
- trigger_address_error();
-
- while (1)
- ;
-}
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#if !defined(CONFIG_CPU_SH2)
#include <asm/processor.h>
/* Timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0x8) /* TCNT0 */
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
-#endif
#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#ifndef _ASM_CPU_SH2_H_
-#define _ASM_CPU_SH2_H_
-
-/* cache control */
-#define CCR_CACHE_STOP 0x00000008
-#define CCR_CACHE_ENABLE 0x00000005
-#define CCR_CACHE_ICI 0x00000008
-
-#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
-#define CACHE_OC_WAY_SHIFT 13
-#define CACHE_OC_NUM_ENTRIES 256
-#define CACHE_OC_ENTRY_SHIFT 4
-
-#if defined(CONFIG_CPU_SH7203)
-# include <asm/cpu_sh7203.h>
-#elif defined(CONFIG_CPU_SH7264)
-# include <asm/cpu_sh7264.h>
-#elif defined(CONFIG_CPU_SH7269)
-# include <asm/cpu_sh7269.h>
-#else
-# error "Unknown SH2 variant"
-#endif
-
-#endif /* _ASM_CPU_SH2_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#ifndef _ASM_CPU_SH3_H_
-#define _ASM_CPU_SH3_H_
-
-/* cache control */
-#define CCR_CACHE_STOP 0x00000008
-#define CCR_CACHE_ENABLE 0x00000005
-#define CCR_CACHE_ICI 0x00000008
-
-#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
-#define CACHE_OC_WAY_SHIFT 13
-#define CACHE_OC_NUM_ENTRIES 256
-#define CACHE_OC_ENTRY_SHIFT 4
-
-#if defined(CONFIG_CPU_SH7706)
-#include <asm/cpu_sh7706.h>
-#elif defined(CONFIG_CPU_SH7710)
-#include <asm/cpu_sh7710.h>
-#elif defined(CONFIG_CPU_SH7720)
-#include <asm/cpu_sh7720.h>
-#else
-#error "Unknown SH3 variant"
-#endif
-
-#endif /* _ASM_CPU_SH3_H_ */
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h>
-#elif defined (CONFIG_CPU_SH7724)
-# include <asm/cpu_sh7724.h>
#elif defined (CONFIG_CPU_SH7734)
# include <asm/cpu_sh7734.h>
#elif defined (CONFIG_CPU_SH7752)
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
# include <asm/cpu_sh7780.h>
-#elif defined (CONFIG_CPU_SH7785)
-# include <asm/cpu_sh7785.h>
#else
# error "Unknown SH4 variant"
#endif
+++ /dev/null
-#ifndef _ASM_CPU_SH7203_H_
-#define _ASM_CPU_SH7203_H_
-
-/* Cache */
-#define CCR1 0xFFFC1000
-#define CCR CCR1
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-
-/* SDRAM controller */
-
-/* SCIF */
-#define SCSMR_0 0xFFFE8000
-#define SCIF0_BASE SCSMR_0
-
-/* Timer(CMT) */
-#define CMSTR 0xFFFEC000
-#define CMCSR_0 0xFFFEC002
-#define CMCNT_0 0xFFFEC004
-#define CMCOR_0 0xFFFEC006
-#define CMCSR_1 0xFFFEC008
-#define CMCNT_1 0xFFFEC00A
-#define CMCOR_1 0xFFFEC00C
-
-/* On chip oscillator circuits */
-#define FRQCR 0xA415FF80
-#define WTCNT 0xA415FF84
-#define WTCSR 0xA415FF86
-
-#endif /* _ASM_CPU_SH7203_H_ */
+++ /dev/null
-#ifndef _ASM_CPU_SH7264_H_
-#define _ASM_CPU_SH7264_H_
-
-/* Cache */
-#define CCR1 0xFFFC1000
-#define CCR CCR1
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-
-/* SDRAM controller */
-
-/* SCIF */
-#define SCSMR_3 0xFFFE9800
-#define SCIF3_BASE SCSMR_3
-
-/* Timer(CMT) */
-#define CMSTR 0xFFFEC000
-#define CMCSR_0 0xFFFEC002
-#define CMCNT_0 0xFFFEC004
-#define CMCOR_0 0xFFFEC006
-#define CMCSR_1 0xFFFEC008
-#define CMCNT_1 0xFFFEC00A
-#define CMCOR_1 0xFFFEC00C
-
-/* On chip oscillator circuits */
-#define FRQCR 0xA415FF80
-#define WTCNT 0xA415FF84
-#define WTCSR 0xA415FF86
-
-#endif /* _ASM_CPU_SH7264_H_ */
+++ /dev/null
-#ifndef _ASM_CPU_SH7269_H_
-#define _ASM_CPU_SH7269_H_
-
-/* Cache */
-#define CCR1 0xFFFC1000
-#define CCR CCR1
-
-/* SCIF */
-#define SCSMR_0 0xE8007000
-#define SCIF0_BASE SCSMR_0
-#define SCSMR_1 0xE8007800
-#define SCIF1_BASE SCSMR_1
-#define SCSMR_2 0xE8008000
-#define SCIF2_BASE SCSMR_2
-#define SCSMR_3 0xE8008800
-#define SCIF3_BASE SCSMR_3
-#define SCSMR_7 0xE800A800
-#define SCIF7_BASE SCSMR_7
-
-/* Timer(CMT) */
-#define CMSTR 0xFFFEC000
-#define CMCSR_0 0xFFFEC002
-#define CMCNT_0 0xFFFEC004
-#define CMCOR_0 0xFFFEC006
-
-#endif /* _ASM_CPU_SH7269_H_ */
+++ /dev/null
-#ifndef _ASM_CPU_SH7706_H_
-#define _ASM_CPU_SH7706_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000D
-
-/* MMU and Cache control */
-#define MMUCR 0xFFFFFFE0
-#define CCR 0xFFFFFFEC
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-#define FRQCR 0xffffff80
-#define BCR1 0xffffff60
-#define BCR2 0xffffff62
-#define WCR1 0xffffff64
-#define WCR2 0xffffff66
-#define MCR 0xffffff68
-
-/* SDRAM controller */
-#define DCR 0xffffff6a
-#define RTCSR 0xffffff6e
-#define RTCNT 0xffffff70
-#define RTCOR 0xffffff72
-#define RFCR 0xffffff74
-#define SDMR 0xFFFFD000
-#define CS3_R 0xFFFFE460
-
-/* SCIF */
-#define SCSMR_2 0xA4000150
-#define SCIF0_BASE SCSMR_2
-
-/* Timer */
-#define TMU_BASE 0xFFFFFE90
-
-/* On chip oscillator circuits */
-#define WTCNT 0xFFFFFF84
-#define WTCSR 0xFFFFFF86
-
-#endif /* _ASM_CPU_SH7706_H_ */
+++ /dev/null
-#ifndef _ASM_CPU_SH7710_H_
-#define _ASM_CPU_SH7710_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000D
-
-/* MMU and Cache control */
-#define MMUCR 0xFFFFFFE0
-#define CCR 0xFFFFFFEC
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-#define CMNCR 0xA4FD0000
-#define CS0BCR 0xA4FD0004
-#define CS2BCR 0xA4FD0008
-#define CS3BCR 0xA4FD000C
-#define CS4BCR 0xA4FD0010
-#define CS5ABCR 0xA4FD0014
-#define CS5BBCR 0xA4FD0018
-#define CS6ABCR 0xA4FD001C
-#define CS6BBCR 0xA4FD0020
-#define CS0WCR 0xA4FD0024
-#define CS2WCR 0xA4FD0028
-#define CS3WCR 0xA4FD002C
-#define CS4WCR 0xA4FD0030
-#define CS5AWCR 0xA4FD0034
-#define CS5BWCR 0xA4FD0038
-#define CS6AWCR 0xA4FD003C
-#define CS6BWCR 0xA4FD0040
-
-/* SDRAM controller */
-#define SDCR 0xA4FD0044
-#define RTCSR 0xA4FD0048
-#define RTCNT 0xA4FD004C
-#define RTCOR 0xA4FD0050
-
-/* SCIF */
-#define SCSMR_0 0xA4400000
-#define SCIF0_BASE SCSMR_0
-#define SCSMR_0 0xA4410000
-#define SCIF1_BASE SCSMR_1
-
-/* Timer */
-#define TMU_BASE 0xA412FE90
-
-/* On chip oscillator circuits */
-#define FRQCR 0xA415FF80
-#define WTCNT 0xA415FF84
-#define WTCSR 0xA415FF86
-
-#endif /* _ASM_CPU_SH7710_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007 (C)
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyright 2008 (C)
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * SH7720 Internal I/O register
- */
-
-#ifndef _ASM_CPU_SH7720_H_
-#define _ASM_CPU_SH7720_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000B
-
-/* EXP */
-#define TRA 0xFFFFFFD0
-#define EXPEVT 0xFFFFFFD4
-#define INTEVT 0xFFFFFFD8
-
-/* MMU */
-#define MMUCR 0xFFFFFFE0
-#define PTEH 0xFFFFFFF0
-#define PTEL 0xFFFFFFF4
-#define TTB 0xFFFFFFF8
-
-/* CACHE */
-#define CCR 0xFFFFFFEC
-
-/* INTC */
-#define IPRF 0xA4080000
-#define IPRG 0xA4080002
-#define IPRH 0xA4080004
-#define IPRI 0xA4080006
-#define IPRJ 0xA4080008
-#define IRR5 0xA4080020
-#define IRR6 0xA4080022
-#define IRR7 0xA4080024
-#define IRR8 0xA4080026
-#define IRR9 0xA4080028
-#define IRR0 0xA4140004
-#define IRR1 0xA4140006
-#define IRR2 0xA4140008
-#define IRR3 0xA414000A
-#define IRR4 0xA414000C
-#define ICR1 0xA4140010
-#define ICR2 0xA4140012
-#define PINTER 0xA4140014
-#define IPRC 0xA4140016
-#define IPRD 0xA4140018
-#define IPRE 0xA414001A
-#define ICR0 0xA414FEE0
-#define IPRA 0xA414FEE2
-#define IPRB 0xA414FEE4
-
-/* BSC */
-#define BSC_BASE 0xA4FD0000
-#define CMNCR (BSC_BASE + 0x00)
-#define CS0BCR (BSC_BASE + 0x04)
-#define CS2BCR (BSC_BASE + 0x08)
-#define CS3BCR (BSC_BASE + 0x0C)
-#define CS4BCR (BSC_BASE + 0x10)
-#define CS5ABCR (BSC_BASE + 0x14)
-#define CS5BBCR (BSC_BASE + 0x18)
-#define CS6ABCR (BSC_BASE + 0x1C)
-#define CS6BBCR (BSC_BASE + 0x20)
-#define CS0WCR (BSC_BASE + 0x24)
-#define CS2WCR (BSC_BASE + 0x28)
-#define CS3WCR (BSC_BASE + 0x2C)
-#define CS4WCR (BSC_BASE + 0x30)
-#define CS5AWCR (BSC_BASE + 0x34)
-#define CS5BWCR (BSC_BASE + 0x38)
-#define CS6AWCR (BSC_BASE + 0x3C)
-#define CS6BWCR (BSC_BASE + 0x40)
-#define SDCR (BSC_BASE + 0x44)
-#define RTCSR (BSC_BASE + 0x48)
-#define RTCNR (BSC_BASE + 0x4C)
-#define RTCOR (BSC_BASE + 0x50)
-#define SDMR2 (BSC_BASE + 0x4000)
-#define SDMR3 (BSC_BASE + 0x5000)
-
-/* DMAC */
-
-/* CPG */
-#define UCLKCR 0xA40A0008
-#define FRQCR 0xA415FF80
-
-/* LOW POWER MODE */
-
-/* TMU */
-#define TMU_BASE 0xA412FE90
-
-/* TPU */
-#define TPU_BASE 0xA4480000
-#define TPU_TSTR (TPU_BASE + 0x00)
-#define TPU_TCR0 (TPU_BASE + 0x10)
-#define TPU_TMDR0 (TPU_BASE + 0x14)
-#define TPU_TIOR0 (TPU_BASE + 0x18)
-#define TPU_TIER0 (TPU_BASE + 0x1C)
-#define TPU_TSR0 (TPU_BASE + 0x20)
-#define TPU_TCNT0 (TPU_BASE + 0x24)
-#define TPU_TGRA0 (TPU_BASE + 0x28)
-#define TPU_TGRB0 (TPU_BASE + 0x2C)
-#define TPU_TGRC0 (TPU_BASE + 0x30)
-#define TPU_TGRD0 (TPU_BASE + 0x34)
-#define TPU_TCR1 (TPU_BASE + 0x50)
-#define TPU_TMDR1 (TPU_BASE + 0x54)
-#define TPU_TIOR1 (TPU_BASE + 0x58)
-#define TPU_TIER1 (TPU_BASE + 0x5C)
-#define TPU_TSR1 (TPU_BASE + 0x60)
-#define TPU_TCNT1 (TPU_BASE + 0x64)
-#define TPU_TGRA1 (TPU_BASE + 0x68)
-#define TPU_TGRB1 (TPU_BASE + 0x6C)
-#define TPU_TGRC1 (TPU_BASE + 0x70)
-#define TPU_TGRD1 (TPU_BASE + 0x74)
-#define TPU_TCR2 (TPU_BASE + 0x90)
-#define TPU_TMDR2 (TPU_BASE + 0x94)
-#define TPU_TIOR2 (TPU_BASE + 0x98)
-#define TPU_TIER2 (TPU_BASE + 0x9C)
-#define TPU_TSR2 (TPU_BASE + 0xB0)
-#define TPU_TCNT2 (TPU_BASE + 0xB4)
-#define TPU_TGRA2 (TPU_BASE + 0xB8)
-#define TPU_TGRB2 (TPU_BASE + 0xBC)
-#define TPU_TGRC2 (TPU_BASE + 0xC0)
-#define TPU_TGRD2 (TPU_BASE + 0xC4)
-#define TPU_TCR3 (TPU_BASE + 0xD0)
-#define TPU_TMDR3 (TPU_BASE + 0xD4)
-#define TPU_TIOR3 (TPU_BASE + 0xD8)
-#define TPU_TIER3 (TPU_BASE + 0xDC)
-#define TPU_TSR3 (TPU_BASE + 0xE0)
-#define TPU_TCNT3 (TPU_BASE + 0xE4)
-#define TPU_TGRA3 (TPU_BASE + 0xE8)
-#define TPU_TGRB3 (TPU_BASE + 0xEC)
-#define TPU_TGRC3 (TPU_BASE + 0xF0)
-#define TPU_TGRD3 (TPU_BASE + 0xF4)
-
-/* CMT */
-
-/* SIOF */
-
-/* SCIF */
-#define SCIF0_BASE 0xA4430000
-
-/* SIM */
-
-/* IrDA */
-
-/* IIC */
-
-/* LCDC */
-
-/* USBF */
-
-/* MMCIF */
-
-/* PFC */
-#define PFC_BASE 0xA4050100
-#define PACR (PFC_BASE + 0x00)
-#define PBCR (PFC_BASE + 0x02)
-#define PCCR (PFC_BASE + 0x04)
-#define PDCR (PFC_BASE + 0x06)
-#define PECR (PFC_BASE + 0x08)
-#define PFCR (PFC_BASE + 0x0A)
-#define PGCR (PFC_BASE + 0x0C)
-#define PHCR (PFC_BASE + 0x0E)
-#define PJCR (PFC_BASE + 0x10)
-#define PKCR (PFC_BASE + 0x12)
-#define PLCR (PFC_BASE + 0x14)
-#define PMCR (PFC_BASE + 0x16)
-#define PPCR (PFC_BASE + 0x18)
-#define PRCR (PFC_BASE + 0x1A)
-#define PSCR (PFC_BASE + 0x1C)
-#define PTCR (PFC_BASE + 0x1E)
-#define PUCR (PFC_BASE + 0x20)
-#define PVCR (PFC_BASE + 0x22)
-#define PSELA (PFC_BASE + 0x24)
-#define PSELB (PFC_BASE + 0x26)
-#define PSELC (PFC_BASE + 0x28)
-#define PSELD (PFC_BASE + 0x2A)
-
-/* I/O Port */
-#define PORT_BASE 0xA4050100
-#define PADR (PORT_BASE + 0x40)
-#define PBDR (PORT_BASE + 0x42)
-#define PCDR (PORT_BASE + 0x44)
-#define PDDR (PORT_BASE + 0x46)
-#define PEDR (PORT_BASE + 0x48)
-#define PFDR (PORT_BASE + 0x4A)
-#define PGDR (PORT_BASE + 0x4C)
-#define PHDR (PORT_BASE + 0x4E)
-#define PJDR (PORT_BASE + 0x50)
-#define PKDR (PORT_BASE + 0x52)
-#define PLDR (PORT_BASE + 0x54)
-#define PMDR (PORT_BASE + 0x56)
-#define PPDR (PORT_BASE + 0x58)
-#define PRDR (PORT_BASE + 0x5A)
-#define PSDR (PORT_BASE + 0x5C)
-#define PTDR (PORT_BASE + 0x5E)
-#define PUDR (PORT_BASE + 0x60)
-#define PVDR (PORT_BASE + 0x62)
-
-/* H-UDI */
-
-#endif /* _ASM_CPU_SH7720_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008, 2011 Renesas Solutions Corp.
- *
- * SH7724 Internal I/O register
- */
-
-#ifndef _ASM_CPU_SH7724_H_
-#define _ASM_CPU_SH7724_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000090d
-
-/* EXP */
-#define TRA 0xFF000020
-#define EXPEVT 0xFF000024
-#define INTEVT 0xFF000028
-
-/* MMU */
-#define PTEH 0xFF000000
-#define PTEL 0xFF000004
-#define TTB 0xFF000008
-#define TEA 0xFF00000C
-#define MMUCR 0xFF000010
-#define PASCR 0xFF000070
-#define IRMCR 0xFF000078
-
-/* CACHE */
-#define CCR 0xFF00001C
-#define RAMCR 0xFF000074
-
-/* INTC */
-
-/* BSC */
-#define MMSELR 0xFF800020
-#define CMNCR 0xFEC10000
-#define CS0BCR 0xFEC10004
-#define CS2BCR 0xFEC10008
-#define CS4BCR 0xFEC10010
-#define CS5ABCR 0xFEC10014
-#define CS5BBCR 0xFEC10018
-#define CS6ABCR 0xFEC1001C
-#define CS6BBCR 0xFEC10020
-#define CS0WCR 0xFEC10024
-#define CS2WCR 0xFEC10028
-#define CS4WCR 0xFEC10030
-#define CS5AWCR 0xFEC10034
-#define CS5BWCR 0xFEC10038
-#define CS6AWCR 0xFEC1003C
-#define CS6BWCR 0xFEC10040
-#define RBWTCNT 0xFEC10054
-
-/* SBSC */
-#define SBSC_SDCR 0xFE400008
-#define SBSC_SDWCR 0xFE40000C
-#define SBSC_SDPCR 0xFE400010
-#define SBSC_RTCSR 0xFE400014
-#define SBSC_RTCNT 0xFE400018
-#define SBSC_RTCOR 0xFE40001C
-#define SBSC_RFCR 0xFE400020
-
-/* DSBC */
-#define DBKIND 0xFD000008
-#define DBSTATE 0xFD00000C
-#define DBEN 0xFD000010
-#define DBCMDCNT 0xFD000014
-#define DBCKECNT 0xFD000018
-#define DBCONF 0xFD000020
-#define DBTR0 0xFD000030
-#define DBTR1 0xFD000034
-#define DBTR2 0xFD000038
-#define DBTR3 0xFD00003C
-#define DBRFPDN0 0xFD000040
-#define DBRFPDN1 0xFD000044
-#define DBRFPDN2 0xFD000048
-#define DBRFSTS 0xFD00004C
-#define DBMRCNT 0xFD000060
-#define DBPDCNT0 0xFD000108
-
-/* DMAC */
-
-/* CPG */
-#define FRQCRA 0xA4150000
-#define FRQCRB 0xA4150004
-#define FRQCR FRQCRA
-#define VCLKCR 0xA4150004
-#define SCLKACR 0xA4150008
-#define SCLKBCR 0xA415000C
-#define IRDACLKCR 0xA4150018
-#define PLLCR 0xA4150024
-#define DLLFRQ 0xA4150050
-
-/* LOW POWER MODE */
-#define STBCR 0xA4150020
-#define MSTPCR0 0xA4150030
-#define MSTPCR1 0xA4150034
-#define MSTPCR2 0xA4150038
-
-/* RWDT */
-#define RWTCNT 0xA4520000
-#define RWTCSR 0xA4520004
-#define WTCNT RWTCNT
-
-/* TMU */
-#define TMU_BASE 0xFFD80000
-
-/* TPU */
-
-/* CMT */
-#define CMSTR 0xA44A0000
-#define CMCSR 0xA44A0060
-#define CMCNT 0xA44A0064
-#define CMCOR 0xA44A0068
-
-/* MSIOF */
-
-/* SCIF */
-#define SCIF0_BASE 0xFFE00000
-#define SCIF1_BASE 0xFFE10000
-#define SCIF2_BASE 0xFFE20000
-#define SCIF3_BASE 0xa4e30000
-#define SCIF4_BASE 0xa4e40000
-#define SCIF5_BASE 0xa4e50000
-
-/* RTC */
-/* IrDA */
-/* KEYSC */
-/* USB */
-/* IIC */
-/* FLCTL */
-/* VPU */
-/* VIO(CEU) */
-/* VIO(VEU) */
-/* VIO(BEU) */
-/* 2DG */
-/* LCDC */
-/* VOU */
-/* TSIF */
-/* SIU */
-/* ATAPI */
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PDCR 0xA4050106
-#define PECR 0xA4050108
-#define PFCR 0xA405010A
-#define PGCR 0xA405010C
-#define PHCR 0xA405010E
-#define PJCR 0xA4050110
-#define PKCR 0xA4050112
-#define PLCR 0xA4050114
-#define PMCR 0xA4050116
-#define PNCR 0xA4050118
-#define PQCR 0xA405011A
-#define PRCR 0xA405011C
-#define PSCR 0xA405011E
-#define PTCR 0xA4050140
-#define PUCR 0xA4050142
-#define PVCR 0xA4050144
-#define PWCR 0xA4050146
-#define PXCR 0xA4050148
-#define PYCR 0xA405014A
-#define PZCR 0xA405014C
-#define PSELA 0xA405014E
-#define PSELB 0xA4050150
-#define PSELC 0xA4050152
-#define PSELD 0xA4050154
-#define PSELE 0xA4050156
-#define HIZCRA 0xA4050158
-#define HIZCRB 0xA405015A
-#define HIZCRC 0xA405015C
-#define HIZCRD 0xA405015E
-#define MSELCRA 0xA4050180
-#define MSELCRB 0xA4050182
-#define PULCR 0xA4050184
-#define DRVCRA 0xA405018A
-#define DRVCRB 0xA405018C
-
-/* I/O Port */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-#define PDDR 0xA4050126
-#define PEDR 0xA4050128
-#define PFDR 0xA405012A
-#define PGDR 0xA405012C
-#define PHDR 0xA405012E
-#define PJDR 0xA4050130
-#define PKDR 0xA4050132
-#define PLDR 0xA4050134
-#define PMDR 0xA4050136
-#define PNDR 0xA4050138
-#define PQDR 0xA405013A
-#define PRDR 0xA405013C
-#define PSDR 0xA405013E
-#define PTDR 0xA4050160
-#define PUDR 0xA4050162
-#define PVDR 0xA4050164
-#define PWDR 0xA4050166
-#define PXDR 0xA4050168
-#define PYDR 0xA405016A
-#define PZDR 0xA405016C
-
-/* UBC */
-/* H-UDI */
-
-#endif /* _ASM_CPU_SH7724_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _ASM_CPU_SH7785_H_
-#define _ASM_CPU_SH7785_H_
-
-/*
- * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#define CACHE_OC_NUM_WAYS 1
-#define CCR_CACHE_INIT 0x0000090b
-
-/* Exceptions */
-#define TRA 0xFF000020
-#define EXPEVT 0xFF000024
-#define INTEVT 0xFF000028
-
-/* Cache Controller */
-#define CCR 0xFF00001C
-#define QACR0 0xFF000038
-#define QACR1 0xFF00003C
-#define RAMCR 0xFF000074
-
-/* Watchdog Timer and Reset */
-#define WTCNT WDTCNT
-#define WDTST 0xFFCC0000
-#define WDTCSR 0xFFCC0004
-#define WDTBST 0xFFCC0008
-#define WDTCNT 0xFFCC0010
-#define WDTBCNT 0xFFCC0018
-
-/* Timer Unit */
-#define TMU_BASE 0xFFD80000
-
-/* Serial Communication Interface with FIFO */
-#define SCIF1_BASE 0xffeb0000
-
-/* LBSC */
-#define MMSELR 0xfc400020
-#define LBSC_BASE 0xff800000
-#define BCR (LBSC_BASE + 0x1000)
-#define CS0BCR (LBSC_BASE + 0x2000)
-#define CS1BCR (LBSC_BASE + 0x2010)
-#define CS2BCR (LBSC_BASE + 0x2020)
-#define CS3BCR (LBSC_BASE + 0x2030)
-#define CS4BCR (LBSC_BASE + 0x2040)
-#define CS5BCR (LBSC_BASE + 0x2050)
-#define CS6BCR (LBSC_BASE + 0x2060)
-#define CS0WCR (LBSC_BASE + 0x2008)
-#define CS1WCR (LBSC_BASE + 0x2018)
-#define CS2WCR (LBSC_BASE + 0x2028)
-#define CS3WCR (LBSC_BASE + 0x2038)
-#define CS4WCR (LBSC_BASE + 0x2048)
-#define CS5WCR (LBSC_BASE + 0x2058)
-#define CS6WCR (LBSC_BASE + 0x2068)
-#define CS5PCR (LBSC_BASE + 0x2070)
-#define CS6PCR (LBSC_BASE + 0x2080)
-
-/* PCI Controller */
-#define SH7780_PCIECR 0xFE000008
-#define SH7780_PCIVID 0xFE040000
-#define SH7780_PCIDID 0xFE040002
-#define SH7780_PCICMD 0xFE040004
-#define SH7780_PCISTATUS 0xFE040006
-#define SH7780_PCIRID 0xFE040008
-#define SH7780_PCIPIF 0xFE040009
-#define SH7780_PCISUB 0xFE04000A
-#define SH7780_PCIBCC 0xFE04000B
-#define SH7780_PCICLS 0xFE04000C
-#define SH7780_PCILTM 0xFE04000D
-#define SH7780_PCIHDR 0xFE04000E
-#define SH7780_PCIBIST 0xFE04000F
-#define SH7780_PCIIBAR 0xFE040010
-#define SH7780_PCIMBAR0 0xFE040014
-#define SH7780_PCIMBAR1 0xFE040018
-#define SH7780_PCISVID 0xFE04002C
-#define SH7780_PCISID 0xFE04002E
-#define SH7780_PCICP 0xFE040034
-#define SH7780_PCIINTLINE 0xFE04003C
-#define SH7780_PCIINTPIN 0xFE04003D
-#define SH7780_PCIMINGNT 0xFE04003E
-#define SH7780_PCIMAXLAT 0xFE04003F
-#define SH7780_PCICID 0xFE040040
-#define SH7780_PCINIP 0xFE040041
-#define SH7780_PCIPMC 0xFE040042
-#define SH7780_PCIPMCSR 0xFE040044
-#define SH7780_PCIPMCSRBSE 0xFE040046
-#define SH7780_PCI_CDD 0xFE040047
-#define SH7780_PCICR 0xFE040100
-#define SH7780_PCILSR0 0xFE040104
-#define SH7780_PCILSR1 0xFE040108
-#define SH7780_PCILAR0 0xFE04010C
-#define SH7780_PCILAR1 0xFE040110
-#define SH7780_PCIIR 0xFE040114
-#define SH7780_PCIIMR 0xFE040118
-#define SH7780_PCIAIR 0xFE04011C
-#define SH7780_PCICIR 0xFE040120
-#define SH7780_PCIAINT 0xFE040130
-#define SH7780_PCIAINTM 0xFE040134
-#define SH7780_PCIBMIR 0xFE040138
-#define SH7780_PCIPAR 0xFE0401C0
-#define SH7780_PCIPINT 0xFE0401CC
-#define SH7780_PCIPINTM 0xFE0401D0
-#define SH7780_PCIMBR0 0xFE0401E0
-#define SH7780_PCIMBMR0 0xFE0401E4
-#define SH7780_PCIMBR1 0xFE0401E8
-#define SH7780_PCIMBMR1 0xFE0401EC
-#define SH7780_PCIMBR2 0xFE0401F0
-#define SH7780_PCIMBMR2 0xFE0401F4
-#define SH7780_PCIIOBR 0xFE0401F8
-#define SH7780_PCIIOBMR 0xFE0401FC
-#define SH7780_PCICSCR0 0xFE040210
-#define SH7780_PCICSCR1 0xFE040214
-#define SH7780_PCICSAR0 0xFE040218
-#define SH7780_PCICSAR1 0xFE04021C
-#define SH7780_PCIPDR 0xFE040220
-
-#endif /* _ASM_CPU_SH7780_H_ */
#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
-#if defined(CONFIG_CPU_SH2)
-# include <asm/cpu_sh2.h>
-#elif defined(CONFIG_CPU_SH3)
-# include <asm/cpu_sh3.h>
-#elif defined(CONFIG_CPU_SH4)
# include <asm/cpu_sh4.h>
#endif
-#endif
obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-ifeq ($(CONFIG_CPU_SH2),y)
-obj-y += time_sh2.o
-else
obj-y += time.o
-endif
obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
udivsi3-y := udivsi3_i4i-Os.o
ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y)
-udivsi3-$(CONFIG_CPU_SH3) := udivsi3_i4i.o
udivsi3-$(CONFIG_CPU_SH4) := udivsi3_i4i.o
endif
udivsi3-y += udivsi3.o
.global _start
_start:
-#ifdef CONFIG_CPU_SH2
- .long 0x00000010 /* Ppower ON reset PC*/
- .long 0x00000000
- .long 0x00000010 /* Manual reset PC */
- .long 0x00000000
-#endif
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
#include <asm/processor.h>
#include <asm/io.h>
-#if defined(CONFIG_CPU_SH3)
-#define TSTR 0x2
-#define TCR0 0xc
-#endif /* CONFIG_CPU_SH3 */
-
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
#define TSTR 0x4
#define TCR0 0x10
config X86_RUN_64BIT
bool "64-bit"
select X86_64
- select SUPPORT_SPL
select SPL
select SPL_SEPARATE_BSS
help
config SPL_X86_16BIT_INIT
bool
depends on X86_RESET_VECTOR
- default y if X86_RESET_VECTOR && SPL
+ default y if X86_RESET_VECTOR && SPL && !TPL
help
This is enabled when 16-bit init is in SPL
+config TPL_X86_16BIT_INIT
+ bool
+ depends on X86_RESET_VECTOR
+ default y if X86_RESET_VECTOR && TPL
+ help
+ This is enabled when 16-bit init is in TPL
+
config X86_32BIT_INIT
bool
depends on X86_RESET_VECTOR
For platforms that use Intel FSP for the memory initialization,
please check FSP output HOB via U-Boot command 'fsp hob' to see
if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
- If such GUID does not exist, MRC cache is not avaiable on such
+ If such GUID does not exist, MRC cache is not available on such
platform (eg: Intel Queensbay), which means selecting this option
here does not make any difference.
ifdef CONFIG_$(SPL_)X86_64
head-y := arch/x86/cpu/start64.o
else
+ifeq ($(CONFIG_$(SPL_TPL_)X86_16BIT_INIT),y)
head-y := arch/x86/cpu/start.o
+else
+ifndef CONFIG_SPL
+head-y := arch/x86/cpu/start.o
+else
+ifdef CONFIG_SPL_BUILD
+head-y = arch/x86/cpu/start_from_tpl.o
+else
+head-y = arch/x86/cpu/start_from_spl.o
+endif
+endif
endif
endif
+endif # EFI
-head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o
-head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o
+head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o
+head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o
libs-y += arch/x86/cpu/
libs-y += arch/x86/lib/
ifeq ($(CONFIG_$(SPL_)X86_64),y)
extra-y = start64.o
else
+ifeq ($(CONFIG_$(SPL_TPL_)X86_16BIT_INIT),y)
extra-y = start.o
+else
+ifndef CONFIG_SPL
+extra-y = start.o
+else
+ifdef CONFIG_SPL_BUILD
+extra-y = start_from_tpl.o
+else
+extra-y = start_from_spl.o
endif
-extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o
+endif
+endif
+endif
+
+extra-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += resetvec.o start16.o
obj-y += cpu.o cpu_x86.o
# Copyright (c) 2016 Google, Inc
obj-y += adsp.o
-obj-y += cpu.o
+obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += cpu.o
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += cpu_full.o
+
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+obj-y += cpu_from_spl.o
+obj-y += cpu_full.o
+obj-y += refcode.o
+endif
+ifndef CONFIG_SPL_BUILD
+# obj-y += cpu_from_spl.o
+endif
+endif
+
+ifeq ($(CONFIG_$(SPL_TPL_)X86_32BIT_INIT),)
+#obj-y += cpu_from_spl.o
+endif
+
obj-y += iobp.o
obj-y += lpc.o
obj-y += me.o
obj-y += pch.o
obj-y += pinctrl_broadwell.o
obj-y += power_state.o
-obj-y += refcode.o
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += refcode.o
obj-y += sata.o
-obj-y += sdram.o
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += sdram.o
#include <asm/cpu_x86.h>
#include <asm/cpu_common.h>
#include <asm/intel_regs.h>
+#include <asm/lpc_common.h>
#include <asm/msr.h>
+#include <asm/pci.h>
#include <asm/post.h>
#include <asm/turbo.h>
#include <asm/arch/cpu.h>
#include <asm/arch/pch.h>
#include <asm/arch/rcb.h>
-struct cpu_broadwell_priv {
- bool ht_disabled;
-};
-
-/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
-static const u8 power_limit_time_sec_to_msr[] = {
- [0] = 0x00,
- [1] = 0x0a,
- [2] = 0x0b,
- [3] = 0x4b,
- [4] = 0x0c,
- [5] = 0x2c,
- [6] = 0x4c,
- [7] = 0x6c,
- [8] = 0x0d,
- [10] = 0x2d,
- [12] = 0x4d,
- [14] = 0x6d,
- [16] = 0x0e,
- [20] = 0x2e,
- [24] = 0x4e,
- [28] = 0x6e,
- [32] = 0x0f,
- [40] = 0x2f,
- [48] = 0x4f,
- [56] = 0x6f,
- [64] = 0x10,
- [80] = 0x30,
- [96] = 0x50,
- [112] = 0x70,
- [128] = 0x11,
-};
-
-/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
-static const u8 power_limit_time_msr_to_sec[] = {
- [0x00] = 0,
- [0x0a] = 1,
- [0x0b] = 2,
- [0x4b] = 3,
- [0x0c] = 4,
- [0x2c] = 5,
- [0x4c] = 6,
- [0x6c] = 7,
- [0x0d] = 8,
- [0x2d] = 10,
- [0x4d] = 12,
- [0x6d] = 14,
- [0x0e] = 16,
- [0x2e] = 20,
- [0x4e] = 24,
- [0x6e] = 28,
- [0x0f] = 32,
- [0x2f] = 40,
- [0x4f] = 48,
- [0x6f] = 56,
- [0x10] = 64,
- [0x30] = 80,
- [0x50] = 96,
- [0x70] = 112,
- [0x11] = 128,
-};
-
int arch_cpu_init_dm(void)
{
struct udevice *dev;
return 0;
}
-/*
- * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
- * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
- * when a core is woken up
- */
-static int pcode_ready(void)
-{
- int wait_count;
- const int delay_step = 10;
-
- wait_count = 0;
- do {
- if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
- MAILBOX_RUN_BUSY))
- return 0;
- wait_count += delay_step;
- udelay(delay_step);
- } while (wait_count < 1000);
-
- return -ETIMEDOUT;
-}
-
-static u32 pcode_mailbox_read(u32 command)
-{
- int ret;
-
- ret = pcode_ready();
- if (ret) {
- debug("PCODE: mailbox timeout on wait ready\n");
- return ret;
- }
-
- /* Send command and start transaction */
- writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
-
- ret = pcode_ready();
- if (ret) {
- debug("PCODE: mailbox timeout on completion\n");
- return ret;
- }
-
- /* Read mailbox */
- return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
-}
-
-static int pcode_mailbox_write(u32 command, u32 data)
-{
- int ret;
-
- ret = pcode_ready();
- if (ret) {
- debug("PCODE: mailbox timeout on wait ready\n");
- return ret;
- }
-
- writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
-
- /* Send command and start transaction */
- writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
-
- ret = pcode_ready();
- if (ret) {
- debug("PCODE: mailbox timeout on completion\n");
- return ret;
- }
-
- return 0;
-}
-
-/* @dev is the CPU device */
-static void initialize_vr_config(struct udevice *dev)
-{
- int ramp, min_vid;
- msr_t msr;
-
- debug("Initializing VR config\n");
-
- /* Configure VR_CURRENT_CONFIG */
- msr = msr_read(MSR_VR_CURRENT_CONFIG);
- /*
- * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
- * on ULT systems
- */
- msr.hi &= 0xc0000000;
- msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */
- msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */
- msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
- msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
- /* Leave the max instantaneous current limit (12:0) to default */
- msr_write(MSR_VR_CURRENT_CONFIG, msr);
-
- /* Configure VR_MISC_CONFIG MSR */
- msr = msr_read(MSR_VR_MISC_CONFIG);
- /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
- msr.hi &= ~(0x3ff << (40 - 32));
- msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
- /* Set IOUT_OFFSET to 0 */
- msr.hi &= ~0xff;
- /* Set entry ramp rate to slow */
- msr.hi &= ~(1 << (51 - 32));
- /* Enable decay mode on C-state entry */
- msr.hi |= (1 << (52 - 32));
- /* Set the slow ramp rate */
- msr.hi &= ~(0x3 << (53 - 32));
- /* Configure the C-state exit ramp rate */
- ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "intel,slow-ramp", -1);
- if (ramp != -1) {
- /* Configured slow ramp rate */
- msr.hi |= ((ramp & 0x3) << (53 - 32));
- /* Set exit ramp rate to slow */
- msr.hi &= ~(1 << (50 - 32));
- } else {
- /* Fast ramp rate / 4 */
- msr.hi |= (0x01 << (53 - 32));
- /* Set exit ramp rate to fast */
- msr.hi |= (1 << (50 - 32));
- }
- /* Set MIN_VID (31:24) to allow CPU to have full control */
- msr.lo &= ~0xff000000;
- min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "intel,min-vid", 0);
- msr.lo |= (min_vid & 0xff) << 24;
- msr_write(MSR_VR_MISC_CONFIG, msr);
-
- /* Configure VR_MISC_CONFIG2 MSR */
- msr = msr_read(MSR_VR_MISC_CONFIG2);
- msr.lo &= ~0xffff;
- /*
- * Allow CPU to control minimum voltage completely (15:8) and
- * set the fast ramp voltage in 10mV steps
- */
- if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
- msr.lo |= 0x006a; /* 1.56V */
- else
- msr.lo |= 0x006f; /* 1.60V */
- msr_write(MSR_VR_MISC_CONFIG2, msr);
-
- /* Set C9/C10 VCC Min */
- pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
-}
-
-static int calibrate_24mhz_bclk(void)
-{
- int err_code;
- int ret;
-
- ret = pcode_ready();
- if (ret)
- return ret;
-
- /* A non-zero value initiates the PCODE calibration */
- writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
- writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
- MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
-
- ret = pcode_ready();
- if (ret)
- return ret;
-
- err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
-
- debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
-
- /* Read the calibrated value */
- writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
- MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
-
- ret = pcode_ready();
- if (ret)
- return ret;
-
- debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
- readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
-
- return 0;
-}
-
-static void configure_pch_power_sharing(void)
-{
- u32 pch_power, pch_power_ext, pmsync, pmsync2;
- int i;
-
- /* Read PCH Power levels from PCODE */
- pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
- pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
-
- debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
- pch_power_ext);
-
- pmsync = readl(RCB_REG(PMSYNC_CONFIG));
- pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
-
- /*
- * Program PMSYNC_TPR_CONFIG PCH power limit values
- * pmsync[0:4] = mailbox[0:5]
- * pmsync[8:12] = mailbox[6:11]
- * pmsync[16:20] = mailbox[12:17]
- */
- for (i = 0; i < 3; i++) {
- u32 level = pch_power & 0x3f;
- pch_power >>= 6;
- pmsync &= ~(0x1f << (i * 8));
- pmsync |= (level & 0x1f) << (i * 8);
- }
- writel(pmsync, RCB_REG(PMSYNC_CONFIG));
-
- /*
- * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
- * pmsync2[0:4] = mailbox[23:18]
- * pmsync2[8:12] = mailbox_ext[6:11]
- * pmsync2[16:20] = mailbox_ext[12:17]
- * pmsync2[24:28] = mailbox_ext[18:22]
- */
- pmsync2 &= ~0x1f;
- pmsync2 |= pch_power & 0x1f;
-
- for (i = 1; i < 4; i++) {
- u32 level = pch_power_ext & 0x3f;
- pch_power_ext >>= 6;
- pmsync2 &= ~(0x1f << (i * 8));
- pmsync2 |= (level & 0x1f) << (i * 8);
- }
- writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
-}
-
-static int bsp_init_before_ap_bringup(struct udevice *dev)
-{
- int ret;
-
- initialize_vr_config(dev);
- ret = calibrate_24mhz_bclk();
- if (ret)
- return ret;
- configure_pch_power_sharing();
-
- return 0;
-}
-
-int cpu_config_tdp_levels(void)
-{
- msr_t platform_info;
-
- /* Bits 34:33 indicate how many levels supported */
- platform_info = msr_read(MSR_PLATFORM_INFO);
- return (platform_info.hi >> 1) & 3;
-}
-
-static void set_max_ratio(void)
-{
- msr_t msr, perf_ctl;
-
- perf_ctl.hi = 0;
-
- /* Check for configurable TDP option */
- if (turbo_get_state() == TURBO_ENABLED) {
- msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT);
- perf_ctl.lo = (msr.lo & 0xff) << 8;
- } else if (cpu_config_tdp_levels()) {
- /* Set to nominal TDP ratio */
- msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
- perf_ctl.lo = (msr.lo & 0xff) << 8;
- } else {
- /* Platform Info bits 15:8 give max ratio */
- msr = msr_read(MSR_PLATFORM_INFO);
- perf_ctl.lo = msr.lo & 0xff00;
- }
- msr_write(IA32_PERF_CTL, perf_ctl);
-
- debug("cpu: frequency set to %d\n",
- ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
-}
-
-int broadwell_init(struct udevice *dev)
-{
- struct cpu_broadwell_priv *priv = dev_get_priv(dev);
- int num_threads;
- int num_cores;
- msr_t msr;
- int ret;
-
- msr = msr_read(CORE_THREAD_COUNT_MSR);
- num_threads = (msr.lo >> 0) & 0xffff;
- num_cores = (msr.lo >> 16) & 0xffff;
- debug("CPU has %u cores, %u threads enabled\n", num_cores,
- num_threads);
-
- priv->ht_disabled = num_threads == num_cores;
-
- ret = bsp_init_before_ap_bringup(dev);
- if (ret)
- return ret;
-
- set_max_ratio();
-
- return ret;
-}
-
-static void configure_mca(void)
-{
- msr_t msr;
- const unsigned int mcg_cap_msr = 0x179;
- int i;
- int num_banks;
-
- msr = msr_read(mcg_cap_msr);
- num_banks = msr.lo & 0xff;
- msr.lo = 0;
- msr.hi = 0;
- /*
- * TODO(adurbin): This should only be done on a cold boot. Also, some
- * of these banks are core vs package scope. For now every CPU clears
- * every bank
- */
- for (i = 0; i < num_banks; i++)
- msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
-}
-
-static void enable_lapic_tpr(void)
-{
- msr_t msr;
-
- msr = msr_read(MSR_PIC_MSG_CONTROL);
- msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
- msr_write(MSR_PIC_MSG_CONTROL, msr);
-}
-
-
-static void configure_c_states(void)
-{
- msr_t msr;
-
- msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
- msr.lo |= (1 << 31); /* Timed MWAIT Enable */
- msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */
- msr.lo |= (1 << 29); /* Package c-state Demotion Enable */
- msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
- msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
- msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
- msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
- msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
- /* The deepest package c-state defaults to factory-configured value */
- msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
-
- msr = msr_read(MSR_MISC_PWR_MGMT);
- msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
- msr_write(MSR_MISC_PWR_MGMT, msr);
-
- msr = msr_read(MSR_POWER_CTL);
- msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
- msr.lo |= (1 << 1); /* C1E Enable */
- msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
- msr_write(MSR_POWER_CTL, msr);
-
- /* C-state Interrupt Response Latency Control 0 - package C3 latency */
- msr.hi = 0;
- msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
- msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
-
- /* C-state Interrupt Response Latency Control 1 */
- msr.hi = 0;
- msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
- msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
-
- /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
- msr.hi = 0;
- msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
- msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
-
- /* C-state Interrupt Response Latency Control 3 - package C8 */
- msr.hi = 0;
- msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
- msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
-
- /* C-state Interrupt Response Latency Control 4 - package C9 */
- msr.hi = 0;
- msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
- msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
-
- /* C-state Interrupt Response Latency Control 5 - package C10 */
- msr.hi = 0;
- msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
- msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
-}
-
-static void configure_misc(void)
-{
- msr_t msr;
-
- msr = msr_read(MSR_IA32_MISC_ENABLE);
- msr.lo |= (1 << 0); /* Fast String enable */
- msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
- msr_write(MSR_IA32_MISC_ENABLE, msr);
-
- /* Disable thermal interrupts */
- msr.lo = 0;
- msr.hi = 0;
- msr_write(MSR_IA32_THERM_INTERRUPT, msr);
-
- /* Enable package critical interrupt only */
- msr.lo = 1 << 4;
- msr.hi = 0;
- msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
-}
-
-static void configure_thermal_target(struct udevice *dev)
-{
- int tcc_offset;
- msr_t msr;
-
- tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "intel,tcc-offset", 0);
-
- /* Set TCC activaiton offset if supported */
- msr = msr_read(MSR_PLATFORM_INFO);
- if ((msr.lo & (1 << 30)) && tcc_offset) {
- msr = msr_read(MSR_TEMPERATURE_TARGET);
- msr.lo &= ~(0xf << 24); /* Bits 27:24 */
- msr.lo |= (tcc_offset & 0xf) << 24;
- msr_write(MSR_TEMPERATURE_TARGET, msr);
- }
-}
-
-static void configure_dca_cap(void)
-{
- struct cpuid_result cpuid_regs;
- msr_t msr;
-
- /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
- cpuid_regs = cpuid(1);
- if (cpuid_regs.ecx & (1 << 18)) {
- msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
- msr.lo |= 1;
- msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
- }
-}
-
-static void set_energy_perf_bias(u8 policy)
-{
- msr_t msr;
- int ecx;
-
- /* Determine if energy efficient policy is supported */
- ecx = cpuid_ecx(0x6);
- if (!(ecx & (1 << 3)))
- return;
-
- /* Energy Policy is bits 3:0 */
- msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
- msr.lo &= ~0xf;
- msr.lo |= policy & 0xf;
- msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
-
- debug("cpu: energy policy set to %u\n", policy);
-}
-
-/* All CPUs including BSP will run the following function */
-static void cpu_core_init(struct udevice *dev)
-{
- /* Clear out pending MCEs */
- configure_mca();
-
- /* Enable the local cpu apics */
- enable_lapic_tpr();
-
- /* Configure C States */
- configure_c_states();
-
- /* Configure Enhanced SpeedStep and Thermal Sensors */
- configure_misc();
-
- /* Thermal throttle activation offset */
- configure_thermal_target(dev);
-
- /* Enable Direct Cache Access */
- configure_dca_cap();
-
- /* Set energy policy */
- set_energy_perf_bias(ENERGY_POLICY_NORMAL);
-
- /* Enable Turbo */
- turbo_enable();
-}
-
-/*
- * Configure processor power limits if possible
- * This must be done AFTER set of BIOS_RESET_CPL
- */
-void cpu_set_power_limits(int power_limit_1_time)
-{
- msr_t msr;
- msr_t limit;
- unsigned power_unit;
- unsigned tdp, min_power, max_power, max_time;
- u8 power_limit_1_val;
-
- msr = msr_read(MSR_PLATFORM_INFO);
- if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
- power_limit_1_time = 28;
-
- if (!(msr.lo & PLATFORM_INFO_SET_TDP))
- return;
-
- /* Get units */
- msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
- power_unit = 2 << ((msr.lo & 0xf) - 1);
-
- /* Get power defaults for this SKU */
- msr = msr_read(MSR_PKG_POWER_SKU);
- tdp = msr.lo & 0x7fff;
- min_power = (msr.lo >> 16) & 0x7fff;
- max_power = msr.hi & 0x7fff;
- max_time = (msr.hi >> 16) & 0x7f;
-
- debug("CPU TDP: %u Watts\n", tdp / power_unit);
-
- if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
- power_limit_1_time = power_limit_time_msr_to_sec[max_time];
-
- if (min_power > 0 && tdp < min_power)
- tdp = min_power;
-
- if (max_power > 0 && tdp > max_power)
- tdp = max_power;
-
- power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
-
- /* Set long term power limit to TDP */
- limit.lo = 0;
- limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
- limit.lo |= PKG_POWER_LIMIT_EN;
- limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
- PKG_POWER_LIMIT_TIME_SHIFT;
-
- /* Set short term power limit to 1.25 * TDP */
- limit.hi = 0;
- limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
- limit.hi |= PKG_POWER_LIMIT_EN;
- /* Power limit 2 time is only programmable on server SKU */
-
- msr_write(MSR_PKG_POWER_LIMIT, limit);
-
- /* Set power limit values in MCHBAR as well */
- writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
- writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
-
- /* Set DDR RAPL power limit by copying from MMIO to MSR */
- msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
- msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
- msr_write(MSR_DDR_RAPL_LIMIT, msr);
-
- /* Use nominal TDP values for CPUs with configurable TDP */
- if (cpu_config_tdp_levels()) {
- msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
- limit.hi = 0;
- limit.lo = msr.lo & 0xff;
- msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
- }
-}
-
-static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
-{
- msr_t msr;
-
- msr = msr_read(IA32_PERF_CTL);
- info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000;
- info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
- 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
-
- return 0;
-}
-
-static int broadwell_get_count(struct udevice *dev)
+void board_debug_uart_init(void)
{
- return 4;
-}
+ struct udevice *bus = NULL;
-static int cpu_x86_broadwell_probe(struct udevice *dev)
-{
- if (dev->seq == 0) {
- cpu_core_init(dev);
- return broadwell_init(dev);
- }
+ /* com1 / com2 decode range */
+ pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
- return 0;
+ pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
+ PCI_SIZE_16);
}
-
-static const struct cpu_ops cpu_x86_broadwell_ops = {
- .get_desc = cpu_x86_get_desc,
- .get_info = broadwell_get_info,
- .get_count = broadwell_get_count,
- .get_vendor = cpu_x86_get_vendor,
-};
-
-static const struct udevice_id cpu_x86_broadwell_ids[] = {
- { .compatible = "intel,core-i3-gen5" },
- { }
-};
-
-U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
- .name = "cpu_x86_broadwell",
- .id = UCLASS_CPU,
- .of_match = cpu_x86_broadwell_ids,
- .bind = cpu_x86_bind,
- .probe = cpu_x86_broadwell_probe,
- .ops = &cpu_x86_broadwell_ops,
- .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),
- .flags = DM_FLAG_PRE_RELOC,
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <bloblist.h>
+#include <debug_uart.h>
+#include <handoff.h>
+#include <asm/mtrr.h>
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct spl_handoff *ho;
+
+ ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
+ if (!ho)
+ return log_msg_ret("Missing SPL hand-off info", -ENOENT);
+ handoff_load_dram_size(ho);
+#ifdef CONFIG_TPL
+ /* TODO(sjg@chromium.org): MTRR cannot be adjusted without a hang */
+ mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
+#else
+ mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
+ mtrr_commit(true);
+#endif
+
+ return 0;
+}
+
+int checkcpu(void)
+{
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return 0;
+}
+
+void board_debug_uart_init(void)
+{
+}
+
+int dram_init_banksize(void)
+{
+#ifdef CONFIG_NR_DRAM_BANKS
+ struct spl_handoff *ho;
+
+ ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
+ if (!ho)
+ return log_msg_ret("Missing SPL hand-off info", -ENOENT);
+ handoff_load_dram_banks(ho);
+#endif
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * Based on code from coreboot src/soc/intel/broadwell/cpu.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <cpu.h>
+#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
+#include <asm/msr.h>
+#include <asm/post.h>
+#include <asm/turbo.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/rcb.h>
+
+struct cpu_broadwell_priv {
+ bool ht_disabled;
+};
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+ [0] = 0x00,
+ [1] = 0x0a,
+ [2] = 0x0b,
+ [3] = 0x4b,
+ [4] = 0x0c,
+ [5] = 0x2c,
+ [6] = 0x4c,
+ [7] = 0x6c,
+ [8] = 0x0d,
+ [10] = 0x2d,
+ [12] = 0x4d,
+ [14] = 0x6d,
+ [16] = 0x0e,
+ [20] = 0x2e,
+ [24] = 0x4e,
+ [28] = 0x6e,
+ [32] = 0x0f,
+ [40] = 0x2f,
+ [48] = 0x4f,
+ [56] = 0x6f,
+ [64] = 0x10,
+ [80] = 0x30,
+ [96] = 0x50,
+ [112] = 0x70,
+ [128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+ [0x00] = 0,
+ [0x0a] = 1,
+ [0x0b] = 2,
+ [0x4b] = 3,
+ [0x0c] = 4,
+ [0x2c] = 5,
+ [0x4c] = 6,
+ [0x6c] = 7,
+ [0x0d] = 8,
+ [0x2d] = 10,
+ [0x4d] = 12,
+ [0x6d] = 14,
+ [0x0e] = 16,
+ [0x2e] = 20,
+ [0x4e] = 24,
+ [0x6e] = 28,
+ [0x0f] = 32,
+ [0x2f] = 40,
+ [0x4f] = 48,
+ [0x6f] = 56,
+ [0x10] = 64,
+ [0x30] = 80,
+ [0x50] = 96,
+ [0x70] = 112,
+ [0x11] = 128,
+};
+
+/*
+ * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
+ * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
+ * when a core is woken up
+ */
+static int pcode_ready(void)
+{
+ int wait_count;
+ const int delay_step = 10;
+
+ wait_count = 0;
+ do {
+ if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
+ MAILBOX_RUN_BUSY))
+ return 0;
+ wait_count += delay_step;
+ udelay(delay_step);
+ } while (wait_count < 1000);
+
+ return -ETIMEDOUT;
+}
+
+static u32 pcode_mailbox_read(u32 command)
+{
+ int ret;
+
+ ret = pcode_ready();
+ if (ret) {
+ debug("PCODE: mailbox timeout on wait ready\n");
+ return ret;
+ }
+
+ /* Send command and start transaction */
+ writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+ ret = pcode_ready();
+ if (ret) {
+ debug("PCODE: mailbox timeout on completion\n");
+ return ret;
+ }
+
+ /* Read mailbox */
+ return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
+}
+
+static int pcode_mailbox_write(u32 command, u32 data)
+{
+ int ret;
+
+ ret = pcode_ready();
+ if (ret) {
+ debug("PCODE: mailbox timeout on wait ready\n");
+ return ret;
+ }
+
+ writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
+
+ /* Send command and start transaction */
+ writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+ ret = pcode_ready();
+ if (ret) {
+ debug("PCODE: mailbox timeout on completion\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/* @dev is the CPU device */
+static void initialize_vr_config(struct udevice *dev)
+{
+ int ramp, min_vid;
+ msr_t msr;
+
+ debug("Initializing VR config\n");
+
+ /* Configure VR_CURRENT_CONFIG */
+ msr = msr_read(MSR_VR_CURRENT_CONFIG);
+ /*
+ * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
+ * on ULT systems
+ */
+ msr.hi &= 0xc0000000;
+ msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */
+ msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */
+ msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
+ msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
+ /* Leave the max instantaneous current limit (12:0) to default */
+ msr_write(MSR_VR_CURRENT_CONFIG, msr);
+
+ /* Configure VR_MISC_CONFIG MSR */
+ msr = msr_read(MSR_VR_MISC_CONFIG);
+ /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
+ msr.hi &= ~(0x3ff << (40 - 32));
+ msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
+ /* Set IOUT_OFFSET to 0 */
+ msr.hi &= ~0xff;
+ /* Set entry ramp rate to slow */
+ msr.hi &= ~(1 << (51 - 32));
+ /* Enable decay mode on C-state entry */
+ msr.hi |= (1 << (52 - 32));
+ /* Set the slow ramp rate */
+ msr.hi &= ~(0x3 << (53 - 32));
+ /* Configure the C-state exit ramp rate */
+ ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "intel,slow-ramp", -1);
+ if (ramp != -1) {
+ /* Configured slow ramp rate */
+ msr.hi |= ((ramp & 0x3) << (53 - 32));
+ /* Set exit ramp rate to slow */
+ msr.hi &= ~(1 << (50 - 32));
+ } else {
+ /* Fast ramp rate / 4 */
+ msr.hi |= (0x01 << (53 - 32));
+ /* Set exit ramp rate to fast */
+ msr.hi |= (1 << (50 - 32));
+ }
+ /* Set MIN_VID (31:24) to allow CPU to have full control */
+ msr.lo &= ~0xff000000;
+ min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "intel,min-vid", 0);
+ msr.lo |= (min_vid & 0xff) << 24;
+ msr_write(MSR_VR_MISC_CONFIG, msr);
+
+ /* Configure VR_MISC_CONFIG2 MSR */
+ msr = msr_read(MSR_VR_MISC_CONFIG2);
+ msr.lo &= ~0xffff;
+ /*
+ * Allow CPU to control minimum voltage completely (15:8) and
+ * set the fast ramp voltage in 10mV steps
+ */
+ if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
+ msr.lo |= 0x006a; /* 1.56V */
+ else
+ msr.lo |= 0x006f; /* 1.60V */
+ msr_write(MSR_VR_MISC_CONFIG2, msr);
+
+ /* Set C9/C10 VCC Min */
+ pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
+}
+
+static int calibrate_24mhz_bclk(void)
+{
+ int err_code;
+ int ret;
+
+ ret = pcode_ready();
+ if (ret)
+ return ret;
+
+ /* A non-zero value initiates the PCODE calibration */
+ writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
+ writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
+ MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+ ret = pcode_ready();
+ if (ret)
+ return ret;
+
+ err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
+
+ debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
+
+ /* Read the calibrated value */
+ writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
+ MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+ ret = pcode_ready();
+ if (ret)
+ return ret;
+
+ debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
+ readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
+
+ return 0;
+}
+
+static void configure_pch_power_sharing(void)
+{
+ u32 pch_power, pch_power_ext, pmsync, pmsync2;
+ int i;
+
+ /* Read PCH Power levels from PCODE */
+ pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
+ pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
+
+ debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
+ pch_power_ext);
+
+ pmsync = readl(RCB_REG(PMSYNC_CONFIG));
+ pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
+
+ /*
+ * Program PMSYNC_TPR_CONFIG PCH power limit values
+ * pmsync[0:4] = mailbox[0:5]
+ * pmsync[8:12] = mailbox[6:11]
+ * pmsync[16:20] = mailbox[12:17]
+ */
+ for (i = 0; i < 3; i++) {
+ u32 level = pch_power & 0x3f;
+
+ pch_power >>= 6;
+ pmsync &= ~(0x1f << (i * 8));
+ pmsync |= (level & 0x1f) << (i * 8);
+ }
+ writel(pmsync, RCB_REG(PMSYNC_CONFIG));
+
+ /*
+ * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
+ * pmsync2[0:4] = mailbox[23:18]
+ * pmsync2[8:12] = mailbox_ext[6:11]
+ * pmsync2[16:20] = mailbox_ext[12:17]
+ * pmsync2[24:28] = mailbox_ext[18:22]
+ */
+ pmsync2 &= ~0x1f;
+ pmsync2 |= pch_power & 0x1f;
+
+ for (i = 1; i < 4; i++) {
+ u32 level = pch_power_ext & 0x3f;
+
+ pch_power_ext >>= 6;
+ pmsync2 &= ~(0x1f << (i * 8));
+ pmsync2 |= (level & 0x1f) << (i * 8);
+ }
+ writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
+}
+
+static int bsp_init_before_ap_bringup(struct udevice *dev)
+{
+ int ret;
+
+ initialize_vr_config(dev);
+ ret = calibrate_24mhz_bclk();
+ if (ret)
+ return ret;
+ configure_pch_power_sharing();
+
+ return 0;
+}
+
+static int cpu_config_tdp_levels(void)
+{
+ msr_t platform_info;
+
+ /* Bits 34:33 indicate how many levels supported */
+ platform_info = msr_read(MSR_PLATFORM_INFO);
+ return (platform_info.hi >> 1) & 3;
+}
+
+static void set_max_ratio(void)
+{
+ msr_t msr, perf_ctl;
+
+ perf_ctl.hi = 0;
+
+ /* Check for configurable TDP option */
+ if (turbo_get_state() == TURBO_ENABLED) {
+ msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ } else if (cpu_config_tdp_levels()) {
+ /* Set to nominal TDP ratio */
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ } else {
+ /* Platform Info bits 15:8 give max ratio */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ perf_ctl.lo = msr.lo & 0xff00;
+ }
+ msr_write(IA32_PERF_CTL, perf_ctl);
+
+ debug("cpu: frequency set to %d\n",
+ ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+}
+
+int broadwell_init(struct udevice *dev)
+{
+ struct cpu_broadwell_priv *priv = dev_get_priv(dev);
+ int num_threads;
+ int num_cores;
+ msr_t msr;
+ int ret;
+
+ msr = msr_read(CORE_THREAD_COUNT_MSR);
+ num_threads = (msr.lo >> 0) & 0xffff;
+ num_cores = (msr.lo >> 16) & 0xffff;
+ debug("CPU has %u cores, %u threads enabled\n", num_cores,
+ num_threads);
+
+ priv->ht_disabled = num_threads == num_cores;
+
+ ret = bsp_init_before_ap_bringup(dev);
+ if (ret)
+ return ret;
+
+ set_max_ratio();
+
+ return ret;
+}
+
+static void configure_mca(void)
+{
+ msr_t msr;
+ const unsigned int mcg_cap_msr = 0x179;
+ int i;
+ int num_banks;
+
+ msr = msr_read(mcg_cap_msr);
+ num_banks = msr.lo & 0xff;
+ msr.lo = 0;
+ msr.hi = 0;
+ /*
+ * TODO(adurbin): This should only be done on a cold boot. Also, some
+ * of these banks are core vs package scope. For now every CPU clears
+ * every bank
+ */
+ for (i = 0; i < num_banks; i++)
+ msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_PIC_MSG_CONTROL);
+ msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
+ msr_write(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_c_states(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
+ msr.lo |= (1 << 31); /* Timed MWAIT Enable */
+ msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */
+ msr.lo |= (1 << 29); /* Package c-state Demotion Enable */
+ msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
+ msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
+ msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
+ msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
+ msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
+ /* The deepest package c-state defaults to factory-configured value */
+ msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
+
+ msr = msr_read(MSR_MISC_PWR_MGMT);
+ msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
+ msr_write(MSR_MISC_PWR_MGMT, msr);
+
+ msr = msr_read(MSR_POWER_CTL);
+ msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
+ msr.lo |= (1 << 1); /* C1E Enable */
+ msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
+ msr_write(MSR_POWER_CTL, msr);
+
+ /* C-state Interrupt Response Latency Control 0 - package C3 latency */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
+ msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
+
+ /* C-state Interrupt Response Latency Control 1 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
+ msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
+
+ /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
+ msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
+
+ /* C-state Interrupt Response Latency Control 3 - package C8 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
+ msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
+
+ /* C-state Interrupt Response Latency Control 4 - package C9 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
+ msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
+
+ /* C-state Interrupt Response Latency Control 5 - package C10 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
+ msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
+}
+
+static void configure_misc(void)
+{
+ msr_t msr;
+
+ msr = msr_read(MSR_IA32_MISC_ENABLE);
+ msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr_write(MSR_IA32_MISC_ENABLE, msr);
+
+ /* Disable thermal interrupts */
+ msr.lo = 0;
+ msr.hi = 0;
+ msr_write(MSR_IA32_THERM_INTERRUPT, msr);
+
+ /* Enable package critical interrupt only */
+ msr.lo = 1 << 4;
+ msr.hi = 0;
+ msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void configure_thermal_target(struct udevice *dev)
+{
+ int tcc_offset;
+ msr_t msr;
+
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "intel,tcc-offset", 0);
+
+ /* Set TCC activaiton offset if supported */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ if ((msr.lo & (1 << 30)) && tcc_offset) {
+ msr = msr_read(MSR_TEMPERATURE_TARGET);
+ msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+ msr.lo |= (tcc_offset & 0xf) << 24;
+ msr_write(MSR_TEMPERATURE_TARGET, msr);
+ }
+}
+
+static void configure_dca_cap(void)
+{
+ struct cpuid_result cpuid_regs;
+ msr_t msr;
+
+ /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+ cpuid_regs = cpuid(1);
+ if (cpuid_regs.ecx & (1 << 18)) {
+ msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
+ msr.lo |= 1;
+ msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
+ }
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+ msr_t msr;
+ int ecx;
+
+ /* Determine if energy efficient policy is supported */
+ ecx = cpuid_ecx(0x6);
+ if (!(ecx & (1 << 3)))
+ return;
+
+ /* Energy Policy is bits 3:0 */
+ msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
+ msr.lo &= ~0xf;
+ msr.lo |= policy & 0xf;
+ msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+ debug("cpu: energy policy set to %u\n", policy);
+}
+
+/* All CPUs including BSP will run the following function */
+static void cpu_core_init(struct udevice *dev)
+{
+ /* Clear out pending MCEs */
+ configure_mca();
+
+ /* Enable the local cpu apics */
+ enable_lapic_tpr();
+
+ /* Configure C States */
+ configure_c_states();
+
+ /* Configure Enhanced SpeedStep and Thermal Sensors */
+ configure_misc();
+
+ /* Thermal throttle activation offset */
+ configure_thermal_target(dev);
+
+ /* Enable Direct Cache Access */
+ configure_dca_cap();
+
+ /* Set energy policy */
+ set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+ /* Enable Turbo */
+ turbo_enable();
+}
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void cpu_set_power_limits(int power_limit_1_time)
+{
+ msr_t msr;
+ msr_t limit;
+ uint power_unit;
+ uint tdp, min_power, max_power, max_time;
+ u8 power_limit_1_val;
+
+ msr = msr_read(MSR_PLATFORM_INFO);
+ if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+ power_limit_1_time = 28;
+
+ if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+ return;
+
+ /* Get units */
+ msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
+ power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+ /* Get power defaults for this SKU */
+ msr = msr_read(MSR_PKG_POWER_SKU);
+ tdp = msr.lo & 0x7fff;
+ min_power = (msr.lo >> 16) & 0x7fff;
+ max_power = msr.hi & 0x7fff;
+ max_time = (msr.hi >> 16) & 0x7f;
+
+ debug("CPU TDP: %u Watts\n", tdp / power_unit);
+
+ if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+ power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+ if (min_power > 0 && tdp < min_power)
+ tdp = min_power;
+
+ if (max_power > 0 && tdp > max_power)
+ tdp = max_power;
+
+ power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+ /* Set long term power limit to TDP */
+ limit.lo = 0;
+ limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+ limit.lo |= PKG_POWER_LIMIT_EN;
+ limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+ PKG_POWER_LIMIT_TIME_SHIFT;
+
+ /* Set short term power limit to 1.25 * TDP */
+ limit.hi = 0;
+ limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+ limit.hi |= PKG_POWER_LIMIT_EN;
+ /* Power limit 2 time is only programmable on server SKU */
+
+ msr_write(MSR_PKG_POWER_LIMIT, limit);
+
+ /* Set power limit values in MCHBAR as well */
+ writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
+ writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
+
+ /* Set DDR RAPL power limit by copying from MMIO to MSR */
+ msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
+ msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
+ msr_write(MSR_DDR_RAPL_LIMIT, msr);
+
+ /* Use nominal TDP values for CPUs with configurable TDP */
+ if (cpu_config_tdp_levels()) {
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ limit.hi = 0;
+ limit.lo = msr.lo & 0xff;
+ msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
+ }
+}
+
+static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ msr_t msr;
+
+ msr = msr_read(IA32_PERF_CTL);
+ info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000;
+ info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+ 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+
+ return 0;
+}
+
+static int broadwell_get_count(struct udevice *dev)
+{
+ return 4;
+}
+
+static int cpu_x86_broadwell_probe(struct udevice *dev)
+{
+ if (dev->seq == 0) {
+ cpu_core_init(dev);
+ return broadwell_init(dev);
+ }
+
+ return 0;
+}
+
+static const struct cpu_ops cpu_x86_broadwell_ops = {
+ .get_desc = cpu_x86_get_desc,
+ .get_info = broadwell_get_info,
+ .get_count = broadwell_get_count,
+ .get_vendor = cpu_x86_get_vendor,
+};
+
+static const struct udevice_id cpu_x86_broadwell_ids[] = {
+ { .compatible = "intel,core-i3-gen5" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
+ .name = "cpu_x86_broadwell",
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_broadwell_ids,
+ .bind = cpu_x86_bind,
+ .probe = cpu_x86_broadwell_probe,
+ .ops = &cpu_x86_broadwell_ops,
+ .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),
+ .flags = DM_FLAG_PRE_RELOC,
+};
#include <common.h>
#include <dm.h>
#include <asm/io.h>
+#include <asm/mrc_common.h>
#include <asm/arch/iomap.h>
#include <asm/arch/pch.h>
+#include <asm/arch/pei_data.h>
+
+__weak asmlinkage void sdram_console_tx_byte(unsigned char byte)
+{
+#ifdef DEBUG
+ putc(byte);
+#endif
+}
+
+void broadwell_fill_pei_data(struct pei_data *pei_data)
+{
+ pei_data->pei_version = PEI_VERSION;
+ pei_data->board_type = BOARD_TYPE_ULT;
+ pei_data->pciexbar = MCFG_BASE_ADDRESS;
+ pei_data->smbusbar = SMBUS_BASE_ADDRESS;
+ pei_data->ehcibar = EARLY_EHCI_BAR;
+ pei_data->xhcibar = EARLY_XHCI_BAR;
+ pei_data->gttbar = EARLY_GTT_BAR;
+ pei_data->pmbase = ACPI_BASE_ADDRESS;
+ pei_data->gpiobase = GPIO_BASE_ADDRESS;
+ pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
+ pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
+ pei_data->tx_byte = sdram_console_tx_byte;
+ pei_data->ddr_refresh_2x = 1;
+}
+
+static void pei_data_usb2_port(struct pei_data *pei_data, int port, uint length,
+ uint enable, uint oc_pin, uint location)
+{
+ pei_data->usb2_ports[port].length = length;
+ pei_data->usb2_ports[port].enable = enable;
+ pei_data->usb2_ports[port].oc_pin = oc_pin;
+ pei_data->usb2_ports[port].location = location;
+}
+
+static void pei_data_usb3_port(struct pei_data *pei_data, int port, uint enable,
+ uint oc_pin, uint fixed_eq)
+{
+ pei_data->usb3_ports[port].enable = enable;
+ pei_data->usb3_ports[port].oc_pin = oc_pin;
+ pei_data->usb3_ports[port].fixed_eq = fixed_eq;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /* DQ byte map for Samus board */
+ const u8 dq_map[2][6][2] = {
+ { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+ { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
+ /* DQS CPU<>DRAM map for Samus board */
+ const u8 dqs_map[2][8] = {
+ { 2, 0, 1, 3, 6, 4, 7, 5 },
+ { 2, 1, 0, 3, 6, 5, 4, 7 } };
+
+ pei_data->ec_present = 1;
+
+ /* One installed DIMM per channel */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+ memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+
+ /* P0: HOST PORT */
+ pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
+ USB_PORT_BACK_PANEL);
+ /* P1: HOST PORT */
+ pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
+ USB_PORT_BACK_PANEL);
+ /* P2: RAIDEN */
+ pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_BACK_PANEL);
+ /* P3: SD CARD */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P4: RAIDEN */
+ pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_BACK_PANEL);
+ /* P5: WWAN (Disabled) */
+ pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P6: CAMERA */
+ pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P7: BT */
+ pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+
+ /* P1: HOST PORT */
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P2: HOST PORT */
+ pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+ /* P3: RAIDEN */
+ pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+ /* P4: RAIDEN */
+ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
+}
static int broadwell_northbridge_early_init(struct udevice *dev)
{
static int broadwell_pch_probe(struct udevice *dev)
{
- if (!(gd->flags & GD_FLG_RELOC))
- return broadwell_pch_early_init(dev);
- else
+ if (CONFIG_IS_ENABLED(X86_32BIT_INIT)) {
+ if (!(gd->flags & GD_FLG_RELOC))
+ return broadwell_pch_early_init(dev);
+ else
+ return broadwell_pch_init(dev);
+ } else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
return broadwell_pch_init(dev);
+ } else {
+ return 0;
+ }
}
static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
return 0;
}
+static int broadwell_ioctl(struct udevice *dev, enum pch_req_t req, void *data,
+ int size)
+{
+ switch (req) {
+ case PCH_REQ_PMBASE_INFO: {
+ struct pch_pmbase_info *pm = data;
+ int ret;
+
+ /* Find the base address of the powermanagement registers */
+ ret = dm_pci_read_config16(dev, 0x40, &pm->base);
+ if (ret)
+ return ret;
+ pm->base &= 0xfffe;
+ pm->gpio0_en_ofs = GPE0_EN(0);
+ pm->pm1_sts_ofs = PM1_STS;
+ pm->pm1_cnt_ofs = PM1_CNT;
+
+ return 0;
+ }
+ default:
+ return -ENOSYS;
+ }
+}
+
static const struct pch_ops broadwell_pch_ops = {
.get_spi_base = broadwell_pch_get_spi_base,
.set_spi_protect = broadwell_set_spi_protect,
.get_gpio_base = broadwell_get_gpio_base,
+ .ioctl = broadwell_ioctl,
};
static const struct udevice_id broadwell_pch_ids[] = {
return 0;
}
-void broadwell_fill_pei_data(struct pei_data *pei_data)
-{
- pei_data->pei_version = PEI_VERSION;
- pei_data->board_type = BOARD_TYPE_ULT;
- pei_data->pciexbar = MCFG_BASE_ADDRESS;
- pei_data->smbusbar = SMBUS_BASE_ADDRESS;
- pei_data->ehcibar = EARLY_EHCI_BAR;
- pei_data->xhcibar = EARLY_XHCI_BAR;
- pei_data->gttbar = EARLY_GTT_BAR;
- pei_data->pmbase = ACPI_BASE_ADDRESS;
- pei_data->gpiobase = GPIO_BASE_ADDRESS;
- pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
- pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
- pei_data->tx_byte = sdram_console_tx_byte;
- pei_data->ddr_refresh_2x = 1;
-}
-
-static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
- uint16_t length, uint8_t enable,
- uint8_t oc_pin, uint8_t location)
-{
- pei_data->usb2_ports[port].length = length;
- pei_data->usb2_ports[port].enable = enable;
- pei_data->usb2_ports[port].oc_pin = oc_pin;
- pei_data->usb2_ports[port].location = location;
-}
-
-static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
- uint8_t enable, uint8_t oc_pin,
- uint8_t fixed_eq)
-{
- pei_data->usb3_ports[port].enable = enable;
- pei_data->usb3_ports[port].oc_pin = oc_pin;
- pei_data->usb3_ports[port].fixed_eq = fixed_eq;
-}
-
-void mainboard_fill_pei_data(struct pei_data *pei_data)
-{
- /* DQ byte map for Samus board */
- const u8 dq_map[2][6][2] = {
- { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
- { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
- { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
- { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
- /* DQS CPU<>DRAM map for Samus board */
- const u8 dqs_map[2][8] = {
- { 2, 0, 1, 3, 6, 4, 7, 5 },
- { 2, 1, 0, 3, 6, 5, 4, 7 } };
-
- pei_data->ec_present = 1;
-
- /* One installed DIMM per channel */
- pei_data->dimm_channel0_disabled = 2;
- pei_data->dimm_channel1_disabled = 2;
-
- memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
- memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
-
- /* P0: HOST PORT */
- pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
- USB_PORT_BACK_PANEL);
- /* P1: HOST PORT */
- pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
- USB_PORT_BACK_PANEL);
- /* P2: RAIDEN */
- pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
- USB_PORT_BACK_PANEL);
- /* P3: SD CARD */
- pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
- USB_PORT_INTERNAL);
- /* P4: RAIDEN */
- pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
- USB_PORT_BACK_PANEL);
- /* P5: WWAN (Disabled) */
- pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
- USB_PORT_SKIP);
- /* P6: CAMERA */
- pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
- USB_PORT_INTERNAL);
- /* P7: BT */
- pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
- USB_PORT_INTERNAL);
-
- /* P1: HOST PORT */
- pei_data_usb3_port(pei_data, 0, 1, 0, 0);
- /* P2: HOST PORT */
- pei_data_usb3_port(pei_data, 1, 1, 1, 0);
- /* P3: RAIDEN */
- pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
- /* P4: RAIDEN */
- pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
-}
-
static unsigned long get_top_of_ram(struct udevice *dev)
{
/*
/* Print ME state before MRC */
ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
- if (ret)
+ if (ret) {
+ debug("Cannot get ME (err=%d)\n", ret);
return ret;
+ }
intel_me_status(me_dev);
/* Save ME HSIO version */
- ret = uclass_first_device(UCLASS_PCH, &pch_dev);
- if (ret)
+ ret = uclass_first_device_err(UCLASS_PCH, &pch_dev);
+ if (ret) {
+ debug("Cannot get PCH (err=%d)\n", ret);
return ret;
- if (!pch_dev)
- return -ENODEV;
+ }
power_state_get(pch_dev, &ps);
intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
broadwell_fill_pei_data(pei_data);
mainboard_fill_pei_data(pei_data);
- ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
- if (ret)
+ ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
+ if (ret) {
+ debug("Cannot get Northbridge (err=%d)\n", ret);
return ret;
- if (!dev)
- return -ENODEV;
+ }
size = 256;
ret = mrc_locate_spd(dev, size, &spd_data);
- if (ret)
+ if (ret) {
+ debug("Cannot locate SPD (err=%d)\n", ret);
return ret;
+ }
memcpy(pei_data->spd_data[0][0], spd_data, size);
memcpy(pei_data->spd_data[1][0], spd_data, size);
debug("PEI version %#x\n", pei_data->pei_version);
ret = mrc_common_init(dev, pei_data, true);
- if (ret)
+ if (ret) {
+ debug("mrc_common_init() failed(err=%d)\n", ret);
return ret;
+ }
debug("Memory init done\n");
ret = sdram_find(dev);
- if (ret)
+ if (ret) {
+ debug("sdram_find() failed (err=%d)\n", ret);
return ret;
+ }
gd->ram_size = gd->arch.meminfo.total_32bit_memory;
debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
return 0;
}
-void board_debug_uart_init(void)
-{
- struct udevice *bus = NULL;
-
- /* com1 / com2 decode range */
- pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
-
- pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
- PCI_SIZE_16);
-}
-
static const struct udevice_id broadwell_syscon_ids[] = {
{ .compatible = "intel,me", .data = X86_SYSCON_ME },
{ }
*info = (char *)((struct cb_string *)ptr)->string;
}
+__weak void cb_parse_unhandled(u32 tag, unsigned char *ptr)
+{
+}
+
static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
{
struct cb_header *header;
case CB_TAG_VBNV:
cb_parse_vbnv(ptr, info);
break;
+ default:
+ cb_parse_unhandled(rec->tag, ptr);
+ break;
}
ptr += rec->size;
return gd->arch.x86_mask;
}
-int x86_cpu_init_f(void)
+/* initialise FPU, reset EM, set MP and NE */
+static void setup_cpu_features(void)
{
const u32 em_rst = ~X86_CR0_EM;
const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
- if (ll_boot_init()) {
- /* initialize FPU, reset EM, set MP and NE */
- asm ("fninit\n" \
- "movl %%cr0, %%eax\n" \
- "andl %0, %%eax\n" \
- "orl %1, %%eax\n" \
- "movl %%eax, %%cr0\n" \
- : : "i" (em_rst), "i" (mp_ne_set) : "eax");
- }
+ asm ("fninit\n" \
+ "movl %%cr0, %%eax\n" \
+ "andl %0, %%eax\n" \
+ "orl %1, %%eax\n" \
+ "movl %%eax, %%cr0\n" \
+ : : "i" (em_rst), "i" (mp_ne_set) : "eax");
+}
+static void setup_identity(void)
+{
/* identify CPU via cpuid and store the decoded info into gd->arch */
if (has_cpuid()) {
struct cpu_device_id cpu;
gd->arch.has_mtrr = has_mtrr();
}
- /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
+}
+
+/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
+static void setup_pci_ram_top(void)
+{
gd->pci_ram_top = 0x80000000U;
+}
+
+static void setup_mtrr(void)
+{
+ u64 mtrr_cap;
/* Configure fixed range MTRRs for some legacy regions */
- if (gd->arch.has_mtrr) {
- u64 mtrr_cap;
-
- mtrr_cap = native_read_msr(MTRR_CAP_MSR);
- if (mtrr_cap & MTRR_CAP_FIX) {
- /* Mark the VGA RAM area as uncacheable */
- native_write_msr(MTRR_FIX_16K_A0000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
- MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
-
- /*
- * Mark the PCI ROM area as cacheable to improve ROM
- * execution performance.
- */
- native_write_msr(MTRR_FIX_4K_C0000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
- native_write_msr(MTRR_FIX_4K_C8000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
- native_write_msr(MTRR_FIX_4K_D0000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
- native_write_msr(MTRR_FIX_4K_D8000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
-
- /* Enable the fixed range MTRRs */
- msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
- }
+ if (!gd->arch.has_mtrr)
+ return;
+
+ mtrr_cap = native_read_msr(MTRR_CAP_MSR);
+ if (mtrr_cap & MTRR_CAP_FIX) {
+ /* Mark the VGA RAM area as uncacheable */
+ native_write_msr(MTRR_FIX_16K_A0000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
+ MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+
+ /*
+ * Mark the PCI ROM area as cacheable to improve ROM
+ * execution performance.
+ */
+ native_write_msr(MTRR_FIX_4K_C0000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_C8000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_D0000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_D8000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+
+ /* Enable the fixed range MTRRs */
+ msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
}
+}
+
+int x86_cpu_init_f(void)
+{
+ if (ll_boot_init())
+ setup_cpu_features();
+ setup_identity();
+ setup_mtrr();
+ setup_pci_ram_top();
-#ifdef CONFIG_I8254_TIMER
/* Set up the i8254 timer if required */
- i8254_init();
-#endif
+ if (IS_ENABLED(CONFIG_I8254_TIMER))
+ i8254_init();
+
+ return 0;
+}
+
+int x86_cpu_reinit_f(void)
+{
+ setup_identity();
+ setup_pci_ram_top();
return 0;
}
"Overflow",
"BOUND Range Exceeded",
"Invalid Opcode (Undefined Opcode)",
- "Device Not Avaiable (No Math Coprocessor)",
+ "Device Not Available (No Math Coprocessor)",
"Double Fault",
"Coprocessor Segment Overrun",
"Invalid TSS",
# Copyright (c) 2016 Google, Inc
ifdef CONFIG_HAVE_MRC
-obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += car.o
-obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o
-obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o
-obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o
+obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
endif
obj-y += cpu.o
obj-y += lpc.o
ifndef CONFIG_TARGET_EFI_APP
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
+ifndef CONFIG_$(SPL_)X86_64
obj-y += microcode.o
endif
+endif
obj-y += pch.o
+
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+obj-y += cpu_from_spl.o
+endif
+endif
.align 4
_dt_ucode_base_size:
- /* These next two fields are filled in by ifdtool */
+ /* These next two fields are filled in by binman */
.globl ucode_base
ucode_base: /* Declared in microcode.h */
.long 0 /* microcode base */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
+#include <asm/lapic.h>
+#include <asm/lpc_common.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/post.h>
+#include <asm/microcode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_cpu_init(void)
+{
+ int ret;
+
+ ret = x86_cpu_reinit_f();
+
+ return ret;
+}
return -ENOENT;
return val & RCBA_AUDIO_CONFIG_MASK;
+ case PCH_REQ_PMBASE_INFO: {
+ struct pch_pmbase_info *pm = data;
+ int ret;
+
+ /* Find the base address of the powermanagement registers */
+ ret = dm_pci_read_config16(dev, 0x40, &pm->base);
+ if (ret)
+ return ret;
+ pm->base &= 0xfffe;
+ pm->gpio0_en_ofs = GPE0_EN;
+ pm->pm1_sts_ofs = PM1_STS;
+ pm->pm1_cnt_ofs = PM1_CNT;
+
+ return 0;
+ }
default:
return -ENOSYS;
}
if (sipi_vector > max_vector_loc) {
printf("SIPI vector too large! 0x%08x\n",
sipi_vector);
- return -1;
+ return -ENOSPC;
}
debug("Attempting to start %d APs\n", ap_count);
if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
debug("Not all APs checked in: %d/%d\n",
atomic_read(num_aps), ap_count);
- return -1;
+ return -EIO;
}
return 0;
if (wait_for_aps(&rec->cpus_entered, num_aps,
timeout_us, step_us)) {
debug("MP record %d timeout\n", i);
- ret = -1;
+ ret = -ETIMEDOUT;
}
}
if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
printf("Invalid MP parameters\n");
- return -1;
+ return -EINVAL;
}
num_cpus = cpu_get_count(cpu);
/* Load the SIPI vector */
ret = load_sipi_vector(&ap_count, num_cpus);
if (ap_count == NULL)
- return -1;
+ return -ENOENT;
/*
* Make sure SIPI data hits RAM so the APs that come up will see
/* Re-enter U-Boot by calling board_init_f_r() */
call board_init_f_r
+#ifdef CONFIG_TPL
+.globl jump_to_spl
+.type jump_to_spl, @function
+jump_to_spl:
+ /* Reset stack to the top of CAR space */
+ movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
+#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
+ subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
+#endif
+
+ jmp *%eax
+#endif
+
die:
hlt
jmp die
/*
* 64-bit x86 Startup Code
*
- * (C) Copyright 216 Google, Inc
+ * Copyright 2019 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*/
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * 32-bit x86 Startup Code when running from SPL
+ *
+ * Copyright 2018 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <config.h>
+
+.section .text.start
+.code32
+.globl _start
+.type _start, @function
+_start:
+ /* Set up memory using the existing stack */
+ movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %eax
+#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
+ subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %eax
+#endif
+ /*
+ * We don't subject CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is
+ * already set up. This has the happy side-effect of putting gd in a
+ * new place separate from SPL, so the memset() in
+ * board_init_f_init_reserve() does not cause any problems (otherwise
+ * it would zero out the gd and crash)
+ */
+ call board_init_f_alloc_reserve
+ mov %eax, %esp
+
+ call board_init_f_init_reserve
+
+ xorl %eax, %eax
+ call board_init_f
+ call board_init_f_r
+
+ /* Should not return here */
+ jmp .
+
+.globl board_init_f_r_trampoline
+.type board_init_f_r_trampoline, @function
+board_init_f_r_trampoline:
+ /*
+ * SPL has been executed and SDRAM has been initialised, U-Boot code
+ * has been copied into RAM, BSS has been cleared and relocation
+ * adjustments have been made. It is now time to jump into the in-RAM
+ * copy of U-Boot
+ *
+ * %eax = Address of top of new stack
+ */
+
+ /* Stack grows down from top of SDRAM */
+ movl %eax, %esp
+
+ /* Re-enter U-Boot by calling board_init_f_r() */
+ call board_init_f_r
+
+die:
+ hlt
+ jmp die
+ hlt
+
+ .align 4
+_dt_ucode_base_size:
+ /* These next two fields are filled in by binman */
+.globl ucode_base
+ucode_base: /* Declared in microcode.h */
+ .long 0 /* microcode base */
+.globl ucode_size
+ucode_size: /* Declared in microcode.h */
+ .long 0 /* microcode size */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * 32-bit x86 Startup Code when running from TPL
+ *
+ * Copyright 2018 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <config.h>
+
+.section .text.start
+.code32
+.globl _start
+.type _start, @function
+_start:
+ /* Set up memory using the existing stack */
+ mov %esp, %eax
+ call board_init_f_alloc_reserve
+ mov %eax, %esp
+
+ call board_init_f_init_reserve
+
+ xorl %eax, %eax
+ call board_init_f
+ call board_init_f_r
+
+ /* Should not return here */
+ jmp .
+
+.globl board_init_f_r_trampoline
+.type board_init_f_r_trampoline, @function
+board_init_f_r_trampoline:
+ /*
+ * TPL has been executed: SDRAM has been initialised, BSS has been
+ * cleared.
+ *
+ * %eax = Address of top of new stack
+ */
+
+ /* Stack grows down from top of SDRAM */
+ movl %eax, %esp
+
+ /* Re-enter SPL by calling board_init_f_r() */
+ call board_init_f_r
+
+die:
+ hlt
+ jmp die
+ hlt
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
-#ifdef CONFIG_SPL_X86_16BIT_INIT
+#if defined(CONFIG_SPL_X86_16BIT_INIT) || defined(CONFIG_TPL_X86_16BIT_INIT)
/*
* The following expressions place the 16-bit Real-Mode code and
* Reset Vector at the end of the Flash ROM
{
return 0;
}
+
+int x86_cpu_reinit_f(void)
+{
+ return 0;
+}
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#ifdef CONFIG_CHROMEOS
+#include "chromeos-x86.dtsi"
+#include "flashmap-x86-ro.dtsi"
+#include "flashmap-8mb-rw.dtsi"
+#endif
+
/ {
model = "Google Samus";
compatible = "google,samus", "intel,broadwell";
spi0 = &spi;
usb0 = &usb_0;
usb1 = &usb_1;
+ cros-ec0 = &cros_ec;
};
config {
/* Put this first: it is the default */
gpio_unused: gpio-unused {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
};
gpio_acpi_sci: acpi-sci {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
invert;
};
gpio_acpi_smi: acpi-smi {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
invert;
};
gpio_input: gpio-input {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
};
gpio_input_invert: gpio-input-invert {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
};
gpio_native: gpio-native {
+ u-boot,dm-pre-reloc;
};
gpio_out_high: gpio-out-high {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <1>;
};
gpio_out_low: gpio-out-low {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <0>;
};
gpio_pirq: gpio-pirq {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
};
soc_gpio@0 {
+ u-boot,dm-pre-reloc;
config =
<0 &gpio_unused 0>, /* unused */
<1 &gpio_unused 0>, /* unused */
spd {
#address-cells = <1>;
#size-cells = <0>;
+ u-boot,dm-pre-reloc;
samsung_4 {
reg = <6>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
* columns 10, density 4096 mb, x32
*/
reg = <8>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
};
samsung_8 {
reg = <10>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
* columns 11, density 4096 mb, x16
*/
reg = <12>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
* columns 11, density 8192 mb, x16
*/
reg = <13>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 05 1a 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
* columns 11, density 8192 mb, x16
*/
reg = <15>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 05 1a 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
compatible = "ehci-pci";
};
- pch@1f,0 {
+ pch: pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,broadwell-pch";
u-boot,dm-pre-reloc;
power-enable-gpio = <&gpio_a 23 0>;
spi: spi {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
- spi-flash@0 {
+ fwstore_spi: spi-flash@0 {
+ u-boot,dm-pre-reloc;
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
+ u-boot,dm-pre-reloc;
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
};
#size-cells = <0>;
u-boot,dm-pre-reloc;
intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
- cros-ec@200 {
+ cros_ec: cros-ec {
+ u-boot,dm-pre-reloc;
compatible = "google,cros-ec-lpc";
reg = <0x204 1 0x200 1 0x880 0x80>;
sata@1f,2 {
compatible = "intel,wildcatpoint-ahci";
reg = <0x0000fa00 0 0 0 0>;
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-proper;
intel,sata-mode = "ahci";
intel,sata-port-map = <1>;
intel,sata-port0-gen3-tx = <0x72>;
};
tpm {
+ u-boot,dm-pre-reloc;
reg = <0xfed40000 0x5000>;
compatible = "infineon,slb9635lpc";
+ secdata {
+ u-boot,dm-pre-reloc;
+ compatible = "google,tpm-secdata";
+ };
};
microcode {
+ u-boot,dm-pre-reloc;
update@0 {
+ u-boot,dm-pre-reloc;
#include "microcode/mc0306d4_00000018.dtsi"
};
};
};
};
+
+&rtc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nvdata {
+ u-boot,dm-pre-reloc;
+ compatible = "google,cmos-nvdata";
+ reg = <0x26>;
+ };
+};
/ {
- reset {
+ reset: reset {
compatible = "x86,reset";
u-boot,dm-pre-reloc;
};
/ {
- rtc {
+ rtc: rtc {
compatible = "motorola,mc146818";
u-boot,dm-pre-reloc;
reg = <0x70 2>;
#include <config.h>
-#ifdef CONFIG_ROM_SIZE
+#ifdef CONFIG_CHROMEOS
/ {
binman {
- filename = "u-boot.rom";
- end-at-4gb;
- sort-by-offset;
- pad-byte = <0xff>;
- size = <CONFIG_ROM_SIZE>;
-#ifdef CONFIG_HAVE_INTEL_ME
- intel-descriptor {
- filename = CONFIG_FLASH_DESCRIPTOR_FILE;
- };
- intel-me {
- filename = CONFIG_INTEL_ME_FILE;
+ multiple-images;
+ rom: rom {
};
+ };
+};
+#else
+/ {
+ rom: binman {
+ };
+};
#endif
-#ifdef CONFIG_SPL
- u-boot-spl-with-ucode-ptr {
- offset = <CONFIG_SPL_TEXT_BASE>;
- };
- u-boot-dtb-with-ucode2 {
- type = "u-boot-dtb-with-ucode";
- };
- u-boot {
- offset = <0xfff00000>;
- };
+#ifdef CONFIG_ROM_SIZE
+&rom {
+ filename = "u-boot.rom";
+ end-at-4gb;
+ sort-by-offset;
+ pad-byte = <0xff>;
+ size = <CONFIG_ROM_SIZE>;
+#ifdef CONFIG_HAVE_INTEL_ME
+ intel-descriptor {
+ filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+ };
+ intel-me {
+ filename = CONFIG_INTEL_ME_FILE;
+ };
+#endif
+#ifdef CONFIG_TPL
+ u-boot-tpl-with-ucode-ptr {
+ offset = <CONFIG_TPL_TEXT_BASE>;
+ };
+ u-boot-tpl-dtb {
+ };
+ u-boot-spl {
+ offset = <CONFIG_SPL_TEXT_BASE>;
+ };
+ u-boot-spl-dtb {
+ };
+ u-boot {
+ offset = <CONFIG_SYS_TEXT_BASE>;
+ };
+#elif defined(CONFIG_SPL)
+ u-boot-spl-with-ucode-ptr {
+ offset = <CONFIG_SPL_TEXT_BASE>;
+ };
+ u-boot-dtb-with-ucode2 {
+ type = "u-boot-dtb-with-ucode";
+ };
+ u-boot {
+ /*
+ * TODO(sjg@chromium.org):
+ * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
+ * for boards with textbase in SDRAM we cannot do this. Just use
+ * an assumed-valid value (1MB before the end of flash) here so
+ * that we can actually build an image for coreboot, etc.
+ * We need a better solution, perhaps a separate Kconfig.
+ */
+#if CONFIG_SYS_TEXT_BASE == 0x1110000
+ offset = <0xfff00000>;
#else
- u-boot-with-ucode-ptr {
- offset = <CONFIG_SYS_TEXT_BASE>;
- };
+ offset = <CONFIG_SYS_TEXT_BASE>;
#endif
- u-boot-dtb-with-ucode {
- };
- u-boot-ucode {
- align = <16>;
- };
+ };
+#else
+ u-boot-with-ucode-ptr {
+ offset = <CONFIG_SYS_TEXT_BASE>;
+ };
+#endif
+ u-boot-dtb-with-ucode {
+ };
+ u-boot-ucode {
+ align = <16>;
+ };
#ifdef CONFIG_HAVE_MRC
- intel-mrc {
- offset = <CONFIG_X86_MRC_ADDR>;
- };
+ intel-mrc {
+ offset = <CONFIG_X86_MRC_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_FSP
- intel-fsp {
- filename = CONFIG_FSP_FILE;
- offset = <CONFIG_FSP_ADDR>;
- };
+ intel-fsp {
+ filename = CONFIG_FSP_FILE;
+ offset = <CONFIG_FSP_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_CMC
- intel-cmc {
- filename = CONFIG_CMC_FILE;
- offset = <CONFIG_CMC_ADDR>;
- };
+ intel-cmc {
+ filename = CONFIG_CMC_FILE;
+ offset = <CONFIG_CMC_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_VGA_BIOS
- intel-vga {
- filename = CONFIG_VGA_BIOS_FILE;
- offset = <CONFIG_VGA_BIOS_ADDR>;
- };
+ intel-vga {
+ filename = CONFIG_VGA_BIOS_FILE;
+ offset = <CONFIG_VGA_BIOS_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_VBT
- intel-vbt {
- filename = CONFIG_VBT_FILE;
- offset = <CONFIG_VBT_ADDR>;
- };
+ intel-vbt {
+ filename = CONFIG_VBT_FILE;
+ offset = <CONFIG_VBT_ADDR>;
+ };
#endif
#ifdef CONFIG_HAVE_REFCODE
- intel-refcode {
- offset = <CONFIG_X86_REFCODE_ADDR>;
- };
+ intel-refcode {
+ offset = <CONFIG_X86_REFCODE_ADDR>;
+ };
#endif
-#ifdef CONFIG_SPL
- x86-start16-spl {
- offset = <CONFIG_SYS_X86_START16>;
- };
+#ifdef CONFIG_TPL
+ x86-start16-tpl {
+ offset = <CONFIG_SYS_X86_START16>;
+ };
+#elif defined(CONFIG_SPL)
+ x86-start16-spl {
+ offset = <CONFIG_SYS_X86_START16>;
+ };
#else
- x86-start16 {
- offset = <CONFIG_SYS_X86_START16>;
- };
-#endif
+ x86-start16 {
+ offset = <CONFIG_SYS_X86_START16>;
};
+#endif
};
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Architecture-specific SPL handoff information for x86
+ *
+ * Copyright 2018 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __x86_asm_handoff_h
+#define __x86_asm_handoff_h
+
+struct arch_spl_handoff {
+};
+
+#endif
*/
int mrccache_save(void);
+/**
+ * mrccache_spl_save() - Save to the MRC region from SPL
+ *
+ * When SPL is used to set up the memory controller we want to save the MRC
+ * data in SPL to avoid needing to pass it up to U-Boot proper to save. This
+ * function handles that.
+ *
+ * @return 0 if saved to SPI flash successfully, other error if failed
+ */
+int mrccache_spl_save(void);
+
#endif /* _ASM_MRCCACHE_H */
/*
* Copyright (C) 2017 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
- *
- * This file is required for SPL to build, but is empty.
*/
+
+#ifndef __asm_spl_h
+#define __asm_spl_h
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+
+enum {
+ BOOT_DEVICE_SPI = 10,
+ BOOT_DEVICE_BOARD,
+ BOOT_DEVICE_CROS_VBOOT,
+};
+
+void jump_to_spl(ulong entry);
+
+#endif
/* cpu/.../cpu.c */
int arch_cpu_init(void);
+
+/**
+ * x86_cpu_init_f() - Set up basic features of the x86 CPU
+ *
+ * 0 on success, -ve on error
+ */
int x86_cpu_init_f(void);
+
+/**
+ * x86_cpu_reinit_f() - Set up the CPU a second time
+ *
+ * Once cpu_init_f() has been called (e.g. in SPL) we should not call it
+ * again (e.g. in U-Boot proper) since it sets up the state from scratch.
+ * Call this function in later phases of U-Boot instead. It reads the CPU
+ * identify so that CPU functions can be used correctly, but does not change
+ * anything.
+ *
+ * @return 0 (indicating success, to mimic cpu_init_f())
+ */
+int x86_cpu_reinit_f(void);
+
int cpu_init_f(void);
void setup_gdt(struct global_data *id, u64 *gdt_addr);
/*
obj-$(CONFIG_CMD_ZBOOT) += zimage.o
endif
obj-$(CONFIG_HAVE_FSP) += fsp/
-obj-$(CONFIG_SPL_BUILD) += spl.o
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_TPL_BUILD
+obj-y += tpl.o
+else
+obj-y += spl.o
+endif
+endif
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += div64.o
timestamp_add_now(TS_U_BOOT_START_KERNEL);
#endif
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
-#ifdef CONFIG_BOOTSTAGE_REPORT
+#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT)
bootstage_report();
#endif
.long temp_ram_init_params
temp_ram_init_params:
_dt_ucode_base_size:
- /* These next two fields are filled in by ifdtool */
+ /* These next two fields are filled in by binman */
.globl ucode_base
ucode_base: /* Declared in microcode.h */
.long 0 /* microcode base */
}
/*
- * DM is not avaiable yet at this point, hence call
+ * DM is not available yet at this point, hence call
* CMOS access library which does not depend on DM.
*/
stack = cmos_read32(CMOS_FSP_STACK_ADDR);
int init_cache_f_r(void)
{
-#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP)
+#if (CONFIG_IS_ENABLED(X86_32BIT_INIT) || \
+ (!defined(CONFIG_SPL_BUILD) && \
+ !CONFIG_IS_ENABLED(CONFIG_X86_RUN_64BIT))) && \
+ !defined(CONFIG_HAVE_FSP)
int ret;
ret = mtrr_commit(false);
ulong base_addr;
int ret;
- if (!is_mrc_cache(cur))
+ if (!is_mrc_cache(cur)) {
+ debug("%s: Cache data not valid\n", __func__);
return -EINVAL;
+ }
/* Find the last used block */
base_addr = entry->base + entry->offset;
return 0;
}
-int mrccache_reserve(void)
+static void mrccache_setup(void *data)
{
- struct mrc_data_container *cache;
+ struct mrc_data_container *cache = data;
u16 checksum;
- if (!gd->arch.mrc_output_len)
- return 0;
-
- /* adjust stack pointer to store pure cache data plus the header */
- gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE);
- cache = (struct mrc_data_container *)gd->start_addr_sp;
-
cache->signature = MRC_DATA_SIGNATURE;
cache->data_size = gd->arch.mrc_output_len;
checksum = compute_ip_checksum(gd->arch.mrc_output, cache->data_size);
/* gd->arch.mrc_output now points to the container */
gd->arch.mrc_output = (char *)cache;
+}
+
+int mrccache_reserve(void)
+{
+ if (!gd->arch.mrc_output_len)
+ return 0;
+
+ /* adjust stack pointer to store pure cache data plus the header */
+ gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE);
+ mrccache_setup((void *)gd->start_addr_sp);
gd->start_addr_sp &= ~0xf;
return -ENOENT;
}
- if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2))
+ if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) {
+ debug("%s: Cannot find memory map\n", __func__);
return -EINVAL;
+ }
entry->base = reg[0];
/* Find the place where we put the MRC cache */
mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache");
- if (mrc_node < 0)
+ if (mrc_node < 0) {
+ debug("%s: Cannot find node\n", __func__);
return -EPERM;
+ }
- if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2))
+ if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) {
+ debug("%s: Cannot find address\n", __func__);
return -EINVAL;
+ }
entry->offset = reg[0];
entry->length = reg[1];
debug("%s: Failed: %d\n", __func__, ret);
return ret;
}
+
+int mrccache_spl_save(void)
+{
+ void *data;
+ int size;
+
+ size = gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE;
+ data = malloc(size);
+ if (!data)
+ return log_msg_ret("Allocate MRC cache block", -ENOMEM);
+ mrccache_setup(data);
+ gd->arch.mrc_output = data;
+
+ return mrccache_save();
+}
#include <common.h>
#include <debug_uart.h>
+#include <malloc.h>
#include <spl.h>
#include <asm/cpu.h>
+#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm-generic/sections.h>
static int x86_spl_init(void)
{
+#ifndef CONFIG_TPL
/*
* TODO(sjg@chromium.org): We use this area of RAM for the stack
* and global_data in SPL. Once U-Boot starts up and releocates it
* place it immediately below CONFIG_SYS_TEXT_BASE.
*/
char *ptr = (char *)0x110000;
+#endif
int ret;
debug("%s starting\n", __func__);
debug("%s: spl_init() failed\n", __func__);
return ret;
}
+#ifdef CONFIG_TPL
+ /* Do a mini-init if TPL has already done the full init */
+ ret = x86_cpu_reinit_f();
+#else
ret = arch_cpu_init();
+#endif
if (ret) {
debug("%s: arch_cpu_init() failed\n", __func__);
return ret;
}
+#ifndef CONFIG_TPL
ret = arch_cpu_init_dm();
if (ret) {
debug("%s: arch_cpu_init_dm() failed\n", __func__);
return ret;
}
+#endif
preloader_console_init();
+#ifndef CONFIG_TPL
ret = print_cpuinfo();
if (ret) {
debug("%s: print_cpuinfo() failed\n", __func__);
return ret;
}
+#endif
ret = dram_init();
if (ret) {
debug("%s: dram_init() failed\n", __func__);
return ret;
}
+ if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
+ ret = mrccache_spl_save();
+ if (ret)
+ debug("%s: Failed to write to mrccache (err=%d)\n",
+ __func__, ret);
+ }
+
+#ifndef CONFIG_TPL
memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
(1ULL << 32) - CONFIG_XIP_ROM_SIZE,
CONFIG_XIP_ROM_SIZE);
if (ret) {
- debug("%s: SPI cache setup failed\n", __func__);
+ debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
return ret;
}
+ mtrr_commit(true);
+#endif
return 0;
}
debug("Error %d\n", ret);
hang();
}
-
+#ifdef CONFIG_TPL
+ gd->bd = malloc(sizeof(*gd->bd));
+ if (!gd->bd) {
+ printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
+ hang();
+ }
+ board_init_r(gd, 0);
+#else
/* Uninit CAR and jump to board_init_f_r() */
board_init_f_r_trampoline(gd->start_addr_sp);
+#endif
}
void board_init_f_r(void)
return -EPERM;
}
+#ifdef CONFIG_X86_RUN_64BIT
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
int ret;
while (1)
;
}
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_TPL
+ preloader_console_init();
+#endif
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 Google, Inc
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+#include <asm/cpu.h>
+#include <asm/mtrr.h>
+#include <asm/processor.h>
+#include <asm-generic/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int arch_cpu_init_dm(void)
+{
+ return 0;
+}
+
+static int x86_tpl_init(void)
+{
+ int ret;
+
+ debug("%s starting\n", __func__);
+ ret = spl_init();
+ if (ret) {
+ debug("%s: spl_init() failed\n", __func__);
+ return ret;
+ }
+ ret = arch_cpu_init();
+ if (ret) {
+ debug("%s: arch_cpu_init() failed\n", __func__);
+ return ret;
+ }
+ ret = arch_cpu_init_dm();
+ if (ret) {
+ debug("%s: arch_cpu_init_dm() failed\n", __func__);
+ return ret;
+ }
+ preloader_console_init();
+ ret = print_cpuinfo();
+ if (ret) {
+ debug("%s: print_cpuinfo() failed\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+void board_init_f(ulong flags)
+{
+ int ret;
+
+ ret = x86_tpl_init();
+ if (ret) {
+ debug("Error %d\n", ret);
+ hang();
+ }
+
+ /* Uninit CAR and jump to board_init_f_r() */
+ board_init_r(gd, 0);
+}
+
+void board_init_f_r(void)
+{
+ /* Not used since we never call board_init_f_r_trampoline() */
+ while (1);
+}
+
+u32 spl_boot_device(void)
+{
+ return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
+ BOOT_DEVICE_BOARD;
+}
+
+int spl_start_uboot(void)
+{
+ return 0;
+}
+
+void spl_board_announce_boot_device(void)
+{
+ printf("SPI flash");
+}
+
+static int spl_board_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
+ spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
+ spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
+ spl_image->os = IH_OS_U_BOOT;
+ spl_image->name = "U-Boot";
+
+ debug("Loading to %lx\n", spl_image->load_addr);
+
+ return 0;
+}
+SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+
+int spl_spi_load_image(void)
+{
+ return -EPERM;
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ printf("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
+ jump_to_spl(spl_image->entry_point);
+ while (1)
+ ;
+}
+
+void spl_board_init(void)
+{
+ preloader_console_init();
+}
endchoice
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
source "board/cadence/xtfpga/Kconfig"
endmenu
* enable data/instruction cache for relocated image.
*/
#if XCHAL_HAVE_SPANNING_WAY && \
- (!defined(CONFIG_SYS_DCACHE_OFF) || \
- !defined(CONFIG_SYS_ICACHE_OFF))
+ !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \
+ CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
srli a7, a4, 29
slli a7, a7, 29
addi a7, a7, XCHAL_SPANNING_WAY
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
rdtlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4
addi a8, a8, CA_WRITEBACK
wdtlb a8, a7
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
ritlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4
+++ /dev/null
-if TARGET_ECO5PK
-
-config SYS_BOARD
- default "eco5pk"
-
-config SYS_VENDOR
- default "8dtech"
-
-config SYS_CONFIG_NAME
- default "eco5pk"
-
-endif
+++ /dev/null
-ECO5PK BOARD
-M: Raphael Assenat <raph@8d.com>
-S: Maintained
-F: board/8dtech/eco5pk/
-F: include/configs/eco5pk.h
-F: configs/eco5pk_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Adapted from ti/evm/Makefile
-
-obj-y := eco5pk.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * eco5pk.c - board file for 8D Technology's AM3517 based eco5pk board
- *
- * Based on am3517evm.c
- *
- * Copyright (C) 2011-2012 8D Technologies inc.
- * Copyright (C) 2009 Texas Instruments Incorporated
- */
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <u-boot/crc.h>
-#include <asm/mach-types.h>
-#include "eco5pk.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- gpio_request(30, "RESOUT");
- gpio_direction_output(30, 1);
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_ECO5_PK();
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * eco5.h - Header file for the 8D Technologies ECO5 board.
- *
- * Based on am3517evm.h
- * Based on ti/evm/evm.h
- *
- * Copyright (C) 2011 8D Technologies inc.
- * Copyright (C) 2009 Texas Instruments Incorporated
- */
-
-#ifndef _ECO5PK_H__
-#define _ECO5PK_H__
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "ECO5 Board",
- "NAND",
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_ECO5_PK() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_CKE0), (M0)) \
- MUX_VAL(CP(SDRC_CKE1), (M0)) \
- MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
- /* - ETH_nRESET*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
- /* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- /* - CAM_RESET*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
- /* MMC */\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
- /* McBSP */\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \
- \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
- /* - LCD_INI*/\
- MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
- /* - LCD_ENVDD */\
- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
- /* - LCD_QVGA/nVGA */\
- MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
- /* - LCD_RESB */\
- /* UART */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
- \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
- /* I2C */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
- /* McSPI */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
- /* - LAN_INTR*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
- \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
- /* LCD_EN_BACKLIGHT */\
- MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \
- /* CCDC */\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
- MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
- /* RMII */\
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
- MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
- MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
- /* HECC */\
- MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
- /* HSUSB */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
- /* HDQ */\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
- /* Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
- /* SYS_nRESWARM */\
- MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
- /* - GPIO30 */\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
- /* - PEN_IRQ */\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\
- /* - VIO_1V8*/\
- MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
- \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
- /* JTAG */\
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
- /* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
- /* Die to Die */\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))
-
-#endif
F: include/configs/ax25-ae350.h
F: configs/ae350_rv32_defconfig
F: configs/ae350_rv64_defconfig
+F: configs/ae350_rv32_xip_defconfig
+F: configs/ae350_rv64_xip_defconfig
void *board_fdt_blob_setup(void)
{
- void **ptr = (void *)&prior_stage_fdt_address;
- if (fdt_magic(*ptr) == FDT_MAGIC)
- return (void *)*ptr;
-
return (void *)CONFIG_SYS_FDT_BASE;
}
+++ /dev/null
-if TARGET_IPAM390
-
-config SYS_BOARD
- default "ipam390"
-
-config SYS_VENDOR
- default "Barix"
-
-config SYS_CONFIG_NAME
- default "ipam390"
-
-endif
+++ /dev/null
-IPAM390 BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/Barix/ipam390/
-F: include/configs/ipam390.h
-F: configs/ipam390_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-
-obj-y += ipam390.o
+++ /dev/null
-Summary
-=======
-The README is for the boot procedure on the ipam390 board
-
-In the context of U-Boot, the board is booted in three stages. The initial
-bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits
-in the internal ROM. The RBL initializes the internal memory and then
-depending on the exact board and pin configurations will initialize another
-controller (such as NAND) to continue the boot process by loading
-the secondary program loader (SPL). The SPL will initialize the system
-further (some clocks, SDRAM). As on this board is used the falcon boot
-mode, now 2 ways are possible depending on the GPIO 7_14 input pin,
-connected with the "soft reset switch"
-
-If this pin is logical 1 (high level):
-spl code starts the kernel image without delay
-
-If this pin is logical 0 (low level):
-spl code starts the u-boot image
-
-AIS is an image format defined by TI for the images that are to be loaded
-to memory by the RBL. The image is divided into a series of sections and
-the image's entry point is specified. Each section comes with meta data
-like the target address the section is to be copied to and the size of the
-section, which is used by the RBL to load the image. At the end of the
-image the RBL jumps to the image entry point. The AIS format allows for
-other things such as programming the clocks and SDRAM if the header is
-programmed for it. We do not take advantage of this and instead use SPL as
-it allows for additional flexibility (run-time detect of board revision,
-loading the next image from a different media, etc).
-
-Compilation
-===========
-run "tools/buildman/buildman -k ipam390" in the u-boot source tree.
-Once this build completes you will have a ../current/ipam390/u-boot.ais file
-that needs to be written to the nand flash.
-
-Flashing the images to NAND
-==========================
-The AIS image can be written to NAND flash using the following commands.
-Assuming that the network is configured and enabled and the u-boot.ais file
-is tftp'able.
-
-U-Boot > print upd_uboot
-upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize}
-U-Boot >
-U-Boot > run upd_uboot
-Using DaVinci-EMAC device
-TFTP from server 192.168.1.1; our IP address is 192.168.20.71
-Filename '/tftpboot/ipam390/u-boot.ais'.
-Load address: 0xc0000000
-Loading: ##################################
- 1.5 MiB/s
-done
-Bytes transferred = 493716 (78894 hex)
-
-NAND erase.part: device 0 offset 0x20000, size 0x160000
-Erasing at 0x160000 -- 100% complete.
-OK
-
-NAND write: device 0 offset 0x20000, size 0x78894
- 493716 bytes written: OK
-U-Boot >
-
-Recovery
-========
-
-In the case of a "bricked" board, you need to use the TI tools found
-here[1] to create an uboot-uart-ais.bin file
-
-- cd to the u-boot source tree
-
-- compile the u-boot for the ipam390 board:
-$ tools/buildman/buildman -k ipam390
-
- -> Now we shall have u-boot.bin
-
-- Create u-boot-uart-ais.bin
-$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini ipam390-ais-uart.cfg \
- -o ../current/ipam390/uboot-uart-ais.bin ./u-boot.bin@0xC1080000;
-
-Note: The ipam390-ais-uart.cfg is found in the board directory
-for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg
-
-- We can now run bootloader on IPAM390 via UART using the command below:
-
-$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin
-NOTE: Do not cancel the command execution! The command takes 20+ seconds
-to upload u-boot over serial and run it!
-Outcome:
-Waiting for the OMAP-L138...
-(AIS Parse): Read magic word 0x41504954.
-(AIS Parse): Waiting for BOOTME... (power on or reset target now)
-(AIS Parse): BOOTME received!
-(AIS Parse): Performing Start-Word Sync...
-(AIS Parse): Performing Ping Opcode Sync...
-(AIS Parse): Processing command 0: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 1: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 2: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 3: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 4: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 5: 0x58535901.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Loading section...
-(AIS Parse): Loaded 326516-Byte section to address 0xC1080000.
-(AIS Parse): Processing command 6: 0x58535906.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Performing jump and close...
-(AIS Parse): AIS complete. Jump to address 0xC1080000.
-(AIS Parse): Waiting for DONE...
-(AIS Parse): Boot completed successfully.
-
-Operation completed successfully.
-
-Falcon Bootmode (boot linux without booting U-Boot)
-===================================================
-
-The Falcon Mode extends this way allowing to start the Linux kernel directly
-from SPL. A new command is added to U-Boot to prepare the parameters that SPL
-must pass to the kernel, using ATAGS or Device Tree.
-
-In normal mode, these parameters are generated each time before
-loading the kernel, passing to Linux the address in memory where
-the parameters can be read.
-With Falcon Mode, this snapshot can be saved into persistent storage and SPL is
-informed to load it before running the kernel.
-
-To boot the kernel, these steps under a Falcon-aware U-Boot are required:
-
-1. Boot the board into U-Boot.
-Use the "spl export" command to generate the kernel parameters area or the DT.
-U-Boot runs as when it boots the kernel, but stops before passing the control
-to the kernel.
-
-Here the command sequence for the ipam390 board:
-- load the linux kernel image into ram:
-
-U-Boot > nand read c0100000 2 200000 400000
-
-NAND read: device 0 offset 0x200000, size 0x400000
- 4194304 bytes read: OK
-
-- generate the bootparms image:
-
-U-Boot > spl export atags c0100000
-## Booting kernel from Legacy Image at c0100000 ...
- Image Name: Linux-3.5.1
- Image Type: ARM Linux Kernel Image (uncompressed)
- Data Size: 2504280 Bytes = 2.4 MiB
- Load Address: c0008000
- Entry Point: c0008000
- Verifying Checksum ... OK
- Loading Kernel Image ... OK
-subcommand not supported
-subcommand not supported
-Argument image is now in RAM at: 0xc0000100
-
-- copy the bootparms image into nand:
-
-U-Boot > mtdparts
-
-device nand0 <davinci_nand.0>, # parts = 6
- #: name size offset mask_flags
- 0: u-boot-env 0x00020000 0x00000000 0
- 1: u-boot 0x00160000 0x00020000 0
- 2: bootparms 0x00020000 0x00180000 0
- 3: factory-info 0x00060000 0x001a0000 0
- 4: kernel 0x00400000 0x00200000 0
- 5: rootfs 0x07a00000 0x00600000 0
-
-active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000
-
-defaults:
-mtdids : nand0=davinci_nand.0
-mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs)
-U-Boot > nand erase.part bootparms
-
-NAND erase.part: device 0 offset 0x180000, size 0x20000
-Erasing at 0x180000 -- 100% complete.
-OK
-U-Boot > nand write c0000100 180000 20000
-
-NAND write: device 0 offset 0x180000, size 0x20000
- 131072 bytes written: OK
-U-Boot >
-
-You can use also the predefined U-Boot Environment variable "setbootparms",
-which will do all the above steps in one command:
-
-U-Boot > print setbootparms
-setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000
-U-Boot > run setbootparms
-
-NAND read: device 0 offset 0x200000, size 0x400000
- 4194304 bytes read: OK
-## Booting kernel from Legacy Image at c0100000 ...
- Image Name: Linux-3.5.1
- Image Type: ARM Linux Kernel Image (uncompressed)
- Data Size: 2504280 Bytes = 2.4 MiB
- Load Address: c0008000
- Entry Point: c0008000
- Verifying Checksum ... OK
- Loading Kernel Image ... OK
-subcommand not supported
-subcommand not supported
-Argument image is now in RAM at: 0xc0000100
-
-NAND erase.part: device 0 offset 0x180000, size 0x20000
-Erasing at 0x180000 -- 100% complete.
-OK
-
-NAND write: device 0 offset 0x180000, size 0x20000
- 131072 bytes written: OK
-U-Boot >
-
-Links
-=====
-[1]
- http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/
+++ /dev/null
-; General settings that can be overwritten in the host code
-; that calls the AISGen library.
-[General]
-
-; Can be 8 or 16 - used in emifa
-busWidth=8
-
-; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
-BootMode=UART
-
-; 8,16,24 - used for SPI,I2C
-;AddrWidth=8
-
-; NO_CRC,SECTION_CRC,SINGLE_CRC
-crcCheckType=NO_CRC
-
-; This section allows setting the PLL0 system clock with a
-; specified multiplier and divider as shown. The clock source
-; can also be chosen for internal or external.
-; |------24|------16|-------8|-------0|
-; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV|
-; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7|
-;[PLL0CONFIG]
-;PLL0CFG0 = 0x00180001
-;PLL0CFG1 = 0x00000205
-
-[PLLANDCLOCKCONFIG]
-PLL0CFG0 = 0x00180001
-PLL0CFG1 = 0x00000205
-PERIPHCLKCFG = 0x00000051
-
-; This section allows setting up the PLL1. Usually this will
-; take place as part of the EMIF3a DDR setup. The format of
-; the input args is as follows:
-; |------24|------16|-------8|-------0|
-; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
-; PLL1CFG1: | RSVD | PLLDIV3|
-[PLL1CONFIG]
-PLL1CFG0 = 0x18010001
-PLL1CFG1 = 0x00000002
-
-; This section lets us configure the peripheral interface
-; of the current booting peripheral (I2C, SPI, or UART).
-; Use with caution. The format of the PERIPHCLKCFG field
-; is as follows:
-; SPI: |------24|------16|-------8|-------0|
-; | RSVD |PRESCALE|
-;
-; I2C: |------24|------16|-------8|-------0|
-; | RSVD |PRESCALE| CLKL | CLKH |
-;
-; UART: |------24|------16|-------8|-------0|
-; | RSVD | OSR | DLH | DLL |
-[PERIPHCLKCFG]
-PERIPHCLKCFG = 0x00000051
-
-; This section can be used to configure the PLL1 and the EMIF3a registers
-; for starting the DDR2 interface.
-; See PLL1CONFIG section for the format of the PLL1CFG fields.
-; |------24|------16|-------8|-------0|
-; PLL1CFG0: | PLL1CFG |
-; PLL1CFG1: | PLL1CFG |
-; DDRPHYC1R: | DDRPHYC1R |
-; SDCR: | SDCR |
-; SDTIMR: | SDTIMR |
-; SDTIMR2: | SDTIMR2 |
-; SDRCR: | SDRCR |
-; CLK2XSRC: | CLK2XSRC |
-[EMIF3DDR]
-PLL1CFG0 = 0x18010001
-PLL1CFG1 = 0x00000002
-DDRPHYC1R = 0x000000C2
-SDCR = 0x0017C432
-SDTIMR = 0x26922A09
-SDTIMR2 = 0x4414C722
-SDRCR = 0x00000498
-CLK2XSRC = 0x00000000
-
-; This section can be used to configure the EMIFA to use
-; CS0 as an SDRAM interface. The fields required to do this
-; are given below.
-; |------24|------16|-------8|-------0|
-; SDBCR: | SDBCR |
-; SDTIMR: | SDTIMR |
-; SDRSRPDEXIT: | SDRSRPDEXIT |
-; SDRCR: | SDRCR |
-; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE |
-;[EMIF25SDRAM]
-;SDBCR = 0x00004421
-;SDTIMR = 0x42215810
-;SDRSRPDEXIT = 0x00000009
-;SDRCR = 0x00000410
-;DIV4p5_CLK_ENABLE = 0x00000001
-
-; This section can be used to configure the async chip selects
-; of the EMIFA (CS2-CS5). The fields required to do this
-; are given below.
-; |------24|------16|-------8|-------0|
-; A1CR: | A1CR |
-; A2CR: | A2CR |
-; A3CR: | A3CR |
-; A4CR: | A4CR |
-; NANDFCR: | NANDFCR |
-;[EMIF25ASYNC]
-;A1CR = 0x00000000
-;A2CR = 0x00000000
-;A3CR = 0x00000000
-;A4CR = 0x00000000
-;NANDFCR = 0x00000000
-[EMIF25ASYNC]
-A1CR = 0x00000000
-A2CR = 0x04202110
-A3CR = 0x00000000
-A4CR = 0x00000000
-NANDFCR = 0x00000012
-
-; This section should be used in place of PLL0CONFIG when
-; the I2C, SPI, or UART modes are being used. This ensures that
-; the system PLL and the peripheral's clocks are changed together.
-; See PLL0CONFIG section for the format of the PLL0CFG fields.
-; See PERIPHCLKCFG section for the format of the CLKCFG field.
-; |------24|------16|-------8|-------0|
-; PLL0CFG0: | PLL0CFG |
-; PLL0CFG1: | PLL0CFG |
-; PERIPHCLKCFG: | CLKCFG |
-;[PLLANDCLOCKCONFIG]
-;PLL0CFG0 = 0x00180001
-;PLL0CFG1 = 0x00000205
-;PERIPHCLKCFG = 0x00010032
-
-; This section should be used to setup the power state of modules
-; of the two PSCs. This section can be included multiple times to
-; allow the configuration of any or all of the device modules.
-; |------24|------16|-------8|-------0|
-; LPSCCFG: | PSCNUM | MODULE | PD | STATE |
-;[PSCCONFIG]
-;LPSCCFG=
-
-; This section allows setting of a single PINMUX register.
-; This section can be included multiple times to allow setting
-; as many PINMUX registers as needed.
-; |------24|------16|-------8|-------0|
-; REGNUM: | regNum |
-; MASK: | mask |
-; VALUE: | value |
-;[PINMUX]
-;REGNUM = 5
-;MASK = 0x00FF0000
-;VALUE = 0x00880000
-
-; No Params required - simply include this section for the fast boot
-; function to be called
-;[FASTBOOT]
-
-; This section allows setting up the PLL1. Usually this will
-; take place as part of the EMIF3a DDR setup. The format of
-; the input args is as follows:
-; |------24|------16|-------8|-------0|
-; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
-; PLL1CFG1: | RSVD | PLLDIV3|
-;[PLL1CONFIG]
-;PLL1CFG0 = 0x15010001
-;PLL1CFG1 = 0x00000002
-
-; This section can be used to configure the PLL1 and the EMIF3a registers
-; for starting the DDR2 interface on ARM-boot D800K002 devices.
-; |------24|------16|-------8|-------0|
-; DDRPHYC1R: | DDRPHYC1R |
-; SDCR: | SDCR |
-; SDTIMR: | SDTIMR |
-; SDTIMR2: | SDTIMR2 |
-; SDRCR: | SDRCR |
-; CLK2XSRC: | CLK2XSRC |
-;[ARM_EMIF3DDR_PATCHFXN]
-;DDRPHYC1R = 0x000000C2
-;SDCR = 0x0017C432
-;SDTIMR = 0x26922A09
-;SDTIMR2 = 0x4414C722
-;SDRCR = 0x00000498
-;CLK2XSRC = 0x00000000
-
-; This section can be used to configure the PLL1 and the EMIF3a registers
-; for starting the DDR2 interface on DSP-boot D800K002 devices.
-; |------24|------16|-------8|-------0|
-; DDRPHYC1R: | DDRPHYC1R |
-; SDCR: | SDCR |
-; SDTIMR: | SDTIMR |
-; SDTIMR2: | SDTIMR2 |
-; SDRCR: | SDRCR |
-; CLK2XSRC: | CLK2XSRC |
-;[DSP_EMIF3DDR_PATCHFXN]
-;DDRPHYC1R = 0x000000C4
-;SDCR = 0x08134632
-;SDTIMR = 0x26922A09
-;SDTIMR2 = 0x0014C722
-;SDRCR = 0x00000492
-;CLK2XSRC = 0x00000000
-
-;[INPUTFILE]
-;FILENAME=u-boot.bin
-;LOADADDRESS=0xC1080000
-;ENTRYPOINTADDRESS=0xC1080000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- * Based on:
- * U-Boot:board/davinci/da8xxevm/da850evm.c
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on da830evm.c. Original Copyrights follow:
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/arch/pinmux_defs.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <hwconfig.h>
-#include <bootstage.h>
-#include <asm/mach-types.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define HAS_RMII 1
-#else
-#define HAS_RMII 0
-#endif
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-void dsp_lpsc_on(unsigned domain, unsigned int id)
-{
- dv_reg_p mdstat, mdctl, ptstat, ptcmd;
- struct davinci_psc_regs *psc_regs;
-
- psc_regs = davinci_psc0_regs;
- mdstat = &psc_regs->psc0.mdstat[id];
- mdctl = &psc_regs->psc0.mdctl[id];
- ptstat = &psc_regs->ptstat;
- ptcmd = &psc_regs->ptcmd;
-
- while (*ptstat & (0x1 << domain))
- ;
-
- if ((*mdstat & 0x1f) == 0x03)
- return; /* Already on and enabled */
-
- *mdctl |= 0x03;
-
- *ptcmd = 0x1 << domain;
-
- while (*ptstat & (0x1 << domain))
- ;
- while ((*mdstat & 0x1f) != 0x03)
- ; /* Probably an overkill... */
-}
-
-static void dspwake(void)
-{
- unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
- u32 val;
-
- /* if the device is ARM only, return */
- if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
- return;
-
- if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
- return;
-
- *resetvect++ = 0x1E000; /* DSP Idle */
- /* clear out the next 10 words as NOP */
- memset(resetvect, 0, sizeof(unsigned) * 10);
-
- /* setup the DSP reset vector */
- writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
-
- dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
- val = readl(PSC0_MDCTL + (15 * 4));
- val |= 0x100;
- writel(val, (PSC0_MDCTL + (15 * 4)));
-}
-
-int misc_init_r(void)
-{
- dspwake();
- return 0;
-}
-
-static const struct pinmux_config gpio_pins[] = {
- /* GP7[14] selects bootmode*/
- { pinmux(16), 8, 3 }, /* GP7[14] */
-};
-
-const struct pinmux_resource pinmuxes[] = {
-#ifdef CONFIG_DRIVER_TI_EMAC
- PINMUX_ITEM(emac_pins_mdio),
-#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
- PINMUX_ITEM(emac_pins_rmii),
-#else
- PINMUX_ITEM(emac_pins_mii),
-#endif
-#endif
- PINMUX_ITEM(uart2_pins_txrx),
- PINMUX_ITEM(uart2_pins_rtscts),
- PINMUX_ITEM(uart0_pins_txrx),
- PINMUX_ITEM(uart0_pins_rtscts),
-#ifdef CONFIG_NAND_DAVINCI
- PINMUX_ITEM(emifa_pins_cs3),
- PINMUX_ITEM(emifa_pins_nand),
-#endif
- PINMUX_ITEM(gpio_pins),
-};
-
-const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-
-const struct lpsc_resource lpsc[] = {
- { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
- { DAVINCI_LPSC_EMAC }, /* image download */
- { DAVINCI_LPSC_UART2 }, /* console */
- { DAVINCI_LPSC_UART0 }, /* console */
- { DAVINCI_LPSC_GPIO },
-};
-
-const int lpsc_size = ARRAY_SIZE(lpsc);
-
-#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
-#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
-#endif
-
-#define REV_AM18X_EVM 0x100
-
-/*
- * get_board_rev() - setup to pass kernel board revision information
- * Returns:
- * bit[0-3] Maximum cpu clock rate supported by onboard SoC
- * 0000b - 300 MHz
- * 0001b - 372 MHz
- * 0010b - 408 MHz
- * 0011b - 456 MHz
- */
-u32 get_board_rev(void)
-{
- char *s;
- u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
- u32 rev = 0;
-
- s = env_get("maxcpuclk");
- if (s)
- maxcpuclk = simple_strtoul(s, NULL, 10);
-
- if (maxcpuclk >= 456000000)
- rev = 3;
- else if (maxcpuclk >= 408000000)
- rev = 2;
- else if (maxcpuclk >= 372000000)
- rev = 1;
-#ifdef CONFIG_DA850_AM18X_EVM
- rev |= REV_AM18X_EVM;
-#endif
- return rev;
-}
-
-int board_early_init_f(void)
-{
- /*
- * Power on required peripherals
- * ARM does not have access by default to PSC0 and PSC1
- * assuming here that the DSP bootloader has set the IOPU
- * such that PSC access is available to ARM
- */
- if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
- return 1;
-
- return 0;
-}
-
-int board_init(void)
-{
- irq_init();
-
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /* setup the SUSPSRC for ARM to control emulation suspend */
- writel(readl(&davinci_syscfg_regs->suspsrc) &
- ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
- DAVINCI_SYSCFG_SUSPSRC_UART0),
- &davinci_syscfg_regs->suspsrc);
-
- /* configure pinmux settings */
- if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
- return 1;
-
-#ifdef CONFIG_DRIVER_TI_EMAC
- davinci_emac_mii_mode_sel(HAS_RMII);
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
- /* enable the console UART */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
-#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
- &davinci_uart0_ctrl_regs->pwremu_mgmt);
-#else
- &davinci_uart2_ctrl_regs->pwremu_mgmt);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-/*
- * Initializes on-board ethernet controllers.
- */
-int board_eth_init(bd_t *bis)
-{
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-static int init_led(int gpio, char *name, int val)
-{
- int ret;
-
- ret = gpio_request(gpio, name);
- if (ret)
- return -1;
- ret = gpio_direction_output(gpio, val);
- if (ret)
- return -1;
-
- return gpio;
-}
-
-#define LED_ON 0
-#define LED_OFF 1
-
-#if !defined(CONFIG_SPL_BUILD)
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress(int status)
-{
- static int red;
- static int green;
-
- if (red == 0)
- red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
- if (red != CONFIG_IPAM390_GPIO_LED_RED)
- return;
- if (green == 0)
- green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green",
- LED_OFF);
- if (green != CONFIG_IPAM390_GPIO_LED_GREEN)
- return;
-
- switch (status) {
- case BOOTSTAGE_ID_RUN_OS:
- /*
- * set normal state
- * LED Red : on
- * LED green: off
- */
- gpio_set_value(red, LED_ON);
- gpio_set_value(green, LED_OFF);
- break;
- case BOOTSTAGE_ID_MAIN_LOOP:
- /*
- * U-Boot operation
- * LED Red : on
- * LED green: on
- */
- gpio_set_value(red, LED_ON);
- gpio_set_value(green, LED_ON);
- break;
- }
-}
-#endif
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- int ret;
- int bootmode = 0;
-
- /*
- * GP7[14] selects bootmode:
- * 1: boot linux
- * 0: boot u-boot
- * if error accessing gpio boot U-Boot
- *
- * SPL bootmode
- * 0: boot linux
- * 1: boot u-boot
- */
- ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode");
- if (ret)
- bootmode = 1;
- if (!bootmode) {
- ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE);
- if (ret)
- bootmode = 1;
- }
- if (!bootmode)
- ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE);
- if (!bootmode)
- if (ret == 0)
- bootmode = 1;
- /*
- * LED red : on
- * LED green: off
- */
- init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
- init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
- return bootmode;
-}
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- */
-
-MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
- LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- __start = .;
- *(.vectors)
- arch/arm/cpu/arm926ejs/start.o (.text*)
- *(.text*)
- } >.sram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
- . = ALIGN(4);
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- } >.sram
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sram
-
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- } >.sram
-}
return -1;
}
+ resetc.is_psoc = 1;
rc = dm_i2c_probe(i2cbus,
RSTCTRL_ADDR_PSOC, 0, &resetc.i2cdev);
if (rc) {
#include <fdt_support.h>
#include <environment.h>
-#ifdef CONFIG_WDT_ARMADA_37XX
-#include <wdt.h>
-#endif
-
#include "mox_sp.h"
#define MAX_MOX_MODULES 10
#include <dm/uclass.h>
#include <fdt_support.h>
#include <time.h>
-
-#ifdef CONFIG_ATSHA204A
# include <atsha204a-i2c.h>
-#endif
-
-#ifdef CONFIG_WDT_ORION
-# include <wdt.h>
-#endif
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
-#define OMNIA_I2C_EEPROM_DM_NAME "i2c@11000->i2cmux@70->i2c@0"
-#define OMNIA_I2C_EEPROM 0x54
-#define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0
-#define OMNIA_I2C_EEPROM_ADDRLEN 2
+#define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
+
+#define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
+#define OMNIA_I2C_MCU_CHIP_LEN 1
+
+#define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
+#define OMNIA_I2C_EEPROM_CHIP_LEN 2
#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
-#define OMNIA_I2C_MCU_DM_NAME "i2c@11000->i2cmux@70->i2c@0"
-#define OMNIA_I2C_MCU_ADDR_STATUS 0x1
-#define OMNIA_I2C_MCU_SATA 0x20
-#define OMNIA_I2C_MCU_CARDDET 0x10
-#define OMNIA_I2C_MCU 0x2a
-#define OMNIA_I2C_MCU_WDT_ADDR 0x0b
+enum mcu_commands {
+ CMD_GET_STATUS_WORD = 0x01,
+ CMD_GET_RESET = 0x09,
+ CMD_WATCHDOG_STATE = 0x0b,
+};
+
+enum status_word_bits {
+ CARD_DET_STSBIT = 0x0010,
+ MSATA_IND_STSBIT = 0x0020,
+};
#define OMNIA_ATSHA204_OTP_VERSION 0
#define OMNIA_ATSHA204_OTP_SERIAL 1
#define OMNIA_ATSHA204_OTP_MAC0 3
#define OMNIA_ATSHA204_OTP_MAC1 4
-#define MVTWSI_ARMADA_DEBUG_REG 0x8c
-
/*
* Those values and defines are taken from the Marvell U-Boot version
* "u-boot-2013.01-2014_T3.0"
{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
};
-static bool omnia_detect_sata(void)
+static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
+ uint offset_len)
{
struct udevice *bus, *dev;
- int ret, retry = 3;
- u16 mode;
-
- puts("SERDES0 card detect: ");
+ int ret;
- if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
- puts("Cannot find MCU bus!\n");
- return false;
+ ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
+ if (ret) {
+ printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
+ OMNIA_I2C_BUS_NAME, ret);
+ return NULL;
}
- ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
+ ret = i2c_get_chip(bus, addr, offset_len, &dev);
if (ret) {
- puts("Cannot get MCU chip!\n");
- return false;
+ printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
+ name, ret);
+ return NULL;
}
- for (; retry > 0; --retry) {
- ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2);
- if (!ret)
- break;
- }
+ return dev;
+}
+
+static int omnia_mcu_read(u8 cmd, void *buf, int len)
+{
+ struct udevice *chip;
+
+ chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
+ OMNIA_I2C_MCU_CHIP_LEN);
+ if (!chip)
+ return -ENODEV;
+
+ return dm_i2c_read(chip, cmd, buf, len);
+}
- if (!retry) {
- puts("I2C read failed! Default PEX\n");
+#ifndef CONFIG_SPL_BUILD
+static int omnia_mcu_write(u8 cmd, const void *buf, int len)
+{
+ struct udevice *chip;
+
+ chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
+ OMNIA_I2C_MCU_CHIP_LEN);
+ if (!chip)
+ return -ENODEV;
+
+ return dm_i2c_write(chip, cmd, buf, len);
+}
+
+static bool disable_mcu_watchdog(void)
+{
+ int ret;
+
+ puts("Disabling MCU watchdog... ");
+
+ ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
+ if (ret) {
+ printf("omnia_mcu_write failed: %i\n", ret);
return false;
}
- if (!(mode & OMNIA_I2C_MCU_CARDDET)) {
- puts("NONE\n");
+ puts("disabled\n");
+
+ return true;
+}
+#endif
+
+static bool omnia_detect_sata(void)
+{
+ int ret;
+ u16 stsword;
+
+ puts("MiniPCIe/mSATA card detection... ");
+
+ ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
+ if (ret) {
+ printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
+ ret);
return false;
}
- if (mode & OMNIA_I2C_MCU_SATA) {
- puts("SATA\n");
- return true;
- } else {
- puts("PEX\n");
+ if (!(stsword & CARD_DET_STSBIT)) {
+ puts("none\n");
return false;
}
+
+ if (stsword & MSATA_IND_STSBIT)
+ puts("mSATA\n");
+ else
+ puts("MiniPCIe\n");
+
+ return stsword & MSATA_IND_STSBIT ? true : false;
}
int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
static bool omnia_read_eeprom(struct omnia_eeprom *oep)
{
- struct udevice *bus, *dev;
- int ret, crc, retry = 3;
+ struct udevice *chip;
+ u32 crc;
+ int ret;
+
+ chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
+ OMNIA_I2C_EEPROM_CHIP_LEN);
- if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) {
- puts("Cannot find EEPROM bus\n");
+ if (!chip)
return false;
- }
- ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev);
+ ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
if (ret) {
- puts("Cannot get EEPROM chip\n");
+ printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
return false;
}
- for (; retry > 0; --retry) {
- ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom));
- if (ret)
- continue;
-
- if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
- puts("I2C EEPROM missing magic number!\n");
- continue;
- }
-
- crc = crc32(0, (unsigned char *) oep,
- sizeof(struct omnia_eeprom) - 4);
- if (crc == oep->crc) {
- break;
- } else {
- printf("CRC of EEPROM memory config failed! "
- "calc=0x%04x saved=0x%04x\n", crc, oep->crc);
- }
+ if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
+ printf("bad EEPROM magic number (%08x, should be %08x)\n",
+ oep->magic, OMNIA_I2C_EEPROM_MAGIC);
+ return false;
}
- if (!retry) {
- puts("I2C EEPROM read failed!\n");
+ crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
+ if (crc != oep->crc) {
+ printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
+ oep->crc, crc);
return false;
}
return true;
}
+static int omnia_get_ram_size_gb(void)
+{
+ static int ram_size;
+ struct omnia_eeprom oep;
+
+ if (!ram_size) {
+ /* Get the board config from EEPROM */
+ if (omnia_read_eeprom(&oep)) {
+ debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
+
+ if (oep.ramsize == 0x2)
+ ram_size = 2;
+ else
+ ram_size = 1;
+ } else {
+ /* Hardcoded fallback */
+ puts("Memory config from EEPROM read failed!\n");
+ puts("Falling back to default 1 GiB!\n");
+ ram_size = 1;
+ }
+ }
+
+ return ram_size;
+}
+
/*
* Define the DDR layout / topology here in the board file. This will
* be used by the DDR3 init code in the SPL U-Boot version to configure
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
- static int mem = 0;
- struct omnia_eeprom oep;
-
- /* Get the board config from EEPROM */
- if (mem == 0) {
- if(!omnia_read_eeprom(&oep))
- goto out;
-
- printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
-
- if (oep.ramsize == 0x2)
- mem = 2;
- else
- mem = 1;
- }
-
-out:
- /* Hardcoded fallback */
- if (mem == 0) {
- puts("WARNING: Memory config from EEPROM read failed.\n");
- puts("Falling back to default 1GiB map.\n");
- mem = 1;
- }
-
- /* Return the board topology as defined in the board code */
- if (mem == 1)
- return &board_topology_map_1g;
- if (mem == 2)
+ if (omnia_get_ram_size_gb() == 2)
return &board_topology_map_2g;
-
- return &board_topology_map_1g;
+ else
+ return &board_topology_map_1g;
}
#ifndef CONFIG_SPL_BUILD
printf("Regdomain set to %s\n", rd);
return env_set("regdomain", rd);
}
+
+/*
+ * default factory reset bootcommand on Omnia first sets all the front LEDs
+ * to green and then tries to load the rescue image from SPI flash memory and
+ * boot it
+ */
+#define OMNIA_FACTORY_RESET_BOOTCMD \
+ "i2c dev 2; " \
+ "i2c mw 0x2a.1 0x3 0x1c 1; " \
+ "i2c mw 0x2a.1 0x4 0x1c 1; " \
+ "mw.l 0x01000000 0x00ff000c; " \
+ "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
+ "setenv bootargs \"$bootargs omniarescue=$omnia_reset\"; " \
+ "sf probe; " \
+ "sf read 0x1000000 0x100000 0x700000; " \
+ "bootm 0x1000000; " \
+ "bootz 0x1000000"
+
+static void handle_reset_button(void)
+{
+ int ret;
+ u8 reset_status;
+
+ ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
+ if (ret) {
+ printf("omnia_mcu_read failed: %i, reset status unknown!\n",
+ ret);
+ return;
+ }
+
+ env_set_ulong("omnia_reset", reset_status);
+
+ if (reset_status) {
+ printf("RESET button was pressed, overwriting bootcmd!\n");
+ env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
+ }
+}
#endif
int board_early_init_f(void)
{
- u32 i2c_debug_reg;
-
/* Configure MPP */
writel(0x11111111, MVEBU_MPP_BASE + 0x00);
writel(0x11111111, MVEBU_MPP_BASE + 0x04);
writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
- /*
- * Disable I2C debug mode blocking 0x64 I2C address.
- * Note: that would be redundant once Turris Omnia migrates to DM_I2C,
- * because the mvtwsi driver includes equivalent code.
- */
- i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
- i2c_debug_reg &= ~(1<<18);
- writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
-
return 0;
}
-#ifndef CONFIG_SPL_BUILD
-static bool disable_mcu_watchdog(void)
-{
- struct udevice *bus, *dev;
- int ret, retry = 3;
- uchar buf[1] = {0x0};
-
- if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
- puts("Cannot find MCU bus! Can not disable MCU WDT.\n");
- return false;
- }
-
- ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
- if (ret) {
- puts("Cannot get MCU chip! Can not disable MCU WDT.\n");
- return false;
- }
-
- for (; retry > 0; --retry)
- if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1))
- break;
-
- if (retry <= 0) {
- puts("I2C MCU watchdog failed to disable!\n");
- return false;
- }
-
- return true;
-}
-#endif
-
int board_init(void)
{
- /* adress of boot parameters */
+ /* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
#ifndef CONFIG_SPL_BUILD
- if (disable_mcu_watchdog())
- puts("Disabled MCU startup watchdog.\n");
-
- set_regdomain();
+ disable_mcu_watchdog();
#endif
return 0;
{
#ifndef CONFIG_SPL_BUILD
set_regdomain();
+ handle_reset_button();
#endif
return 0;
}
-#ifdef CONFIG_ATSHA204A
static struct udevice *get_atsha204a_dev(void)
{
- static struct udevice *dev = NULL;
+ static struct udevice *dev;
- if (dev != NULL)
+ if (dev)
return dev;
if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
return dev;
}
-#endif
int checkboard(void)
{
u32 version_num, serial_num;
int err = 1;
-#ifdef CONFIG_ATSHA204A
struct udevice *dev = get_atsha204a_dev();
if (dev) {
err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
OMNIA_ATSHA204_OTP_VERSION,
- (u8 *) &version_num);
+ (u8 *)&version_num);
if (err)
goto out;
err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
OMNIA_ATSHA204_OTP_SERIAL,
- (u8 *) &serial_num);
+ (u8 *)&serial_num);
if (err)
goto out;
}
out:
-#endif
-
+ printf("Turris Omnia:\n");
+ printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
if (err)
- printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
+ printf(" Serial Number: unknown\n");
else
- printf("Board: Turris Omnia SNL %08X%08X\n",
- be32_to_cpu(version_num), be32_to_cpu(serial_num));
+ printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
+ be32_to_cpu(serial_num));
return 0;
}
int misc_init_r(void)
{
-#ifdef CONFIG_ATSHA204A
int err;
struct udevice *dev = get_atsha204a_dev();
u8 mac0[4], mac1[4], mac[6];
eth_env_set_enetaddr("eth2addr", mac);
out:
-#endif
-
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with FPGA bistream";
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA peripheral bitstream";
+ data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+
+ fpga-core-1 {
+ description = "FPGA core bitstream";
+ data = /incbin/("../../../ghrd_10as066n2.core.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA early IO release config";
+ fpga = "fpga-periph-1", "fpga-core-1";
+ };
+ };
+};
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
- /* Reset PHY on GPIOZ_14 */
- clrbits_le32(GX_GPIO_EN(3), BIT(14));
- clrbits_le32(GX_GPIO_OUT(3), BIT(14));
- mdelay(10);
- setbits_le32(GX_GPIO_OUT(3), BIT(14));
-
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
--- /dev/null
+Aries MCVEVK BOARD
+M: Wolfgang Grandegger <wg@aries-embedded.de>
+S: Maintained
+F: board/aries/mcvevk/
+F: include/configs/socfpga_mcvevk.h
+F: configs/socfpga_mcvevk_defconfig
+F: arch/arm/dts/socfpga_cyclone5_mcv.dtsi
+F: arch/arm/dts/socfpga_cyclone5_mcvevk.dts
+F: arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y := socfpga.o
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00000000,
+ 0x18060000,
+ 0x00000060,
+ 0x00000000,
+ 0x00000000,
+ 0x00004000,
+ 0x0C0300C0,
+ 0x00000000,
+ 0x0C000000,
+ 0x0000C030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x06000018,
+ 0x00006018,
+ 0x01806018,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x000C0300,
+ 0x300C0000,
+ 0x300000C0,
+ 0x000000C0,
+ 0x000300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x00018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0300C030,
+ 0x00000000,
+ 0x03000000,
+ 0x0000000C,
+ 0x00000000,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x00000000,
+ 0x00000000,
+ 0x00001806,
+ 0x00000400,
+ 0x0000300C,
+ 0x00C03000,
+ 0x00C00000,
+ 0x00000003,
+ 0x00000C03,
+ 0x00000200,
+ 0x00001806,
+ 0x00601800,
+ 0x80600000,
+ 0x80000001,
+ 0x00000601,
+ 0x00000100,
+ 0x00001000,
+ 0x00300C00,
+ 0xC0300000,
+ 0xC0000000,
+ 0x00000300,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x300C0300,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x0C0300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x00000000,
+ 0x18000000,
+ 0x00018060,
+ 0x06018060,
+ 0x00004000,
+ 0x200300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x00018060,
+ 0x00000000,
+ 0x06000000,
+ 0x00010018,
+ 0x01806018,
+ 0x00001000,
+ 0x0000C030,
+ 0x00000000,
+ 0x03000000,
+ 0x0000000C,
+ 0x00C0300C,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x0C420D80,
+ 0x0C3000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x45034030,
+ 0x12481A01,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A01450,
+ 0x280D0000,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD000001A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000FF0,
+ 0x4810C000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x24086001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x49034030,
+ 0x12481A02,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A00040,
+ 0x280D0002,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD00A281A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A890,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA24,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0x9A28A3D7,
+ 0xF511451E,
+ 0x0356E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x05140680,
+ 0xD749247A,
+ 0x1E9A28A3,
+ 0x88F51145,
+ 0x00034EE3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A890,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00800000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA24,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x86120800,
+ 0x00600240,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xEBCF23D7,
+ 0xF611451E,
+ 0x034E9248,
+ 0x821A038E,
+ 0x0000D000,
+ 0x00000680,
+ 0xD749247A,
+ 0x1E9BCF23,
+ 0x88F61145,
+ 0x00034EE3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820004,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A890,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00800000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010000,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00200000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0x9A28A3D7,
+ 0xF431451E,
+ 0x034E9248,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD749247A,
+ 0x1E9A28A3,
+ 0x88F61145,
+ 0x000356E3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820004,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00800000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020000,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00001000,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x08864000,
+ 0x49247A02,
+ 0xEBCF23DB,
+ 0xF431451E,
+ 0x0356E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD749247A,
+ 0x1EEBCF23,
+ 0x88F43E79,
+ 0x000356A2,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820004,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00004000,
+ 0x00010000,
+ 0x40002080,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x00000000,
+ 0x00000008,
+ 0x00000020,
+ 0x00008000,
+ 0x20001040,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 3, /* EMACIO0 */
+ 3, /* EMACIO1 */
+ 3, /* EMACIO2 */
+ 3, /* EMACIO3 */
+ 3, /* EMACIO4 */
+ 3, /* EMACIO5 */
+ 3, /* EMACIO6 */
+ 3, /* EMACIO7 */
+ 3, /* EMACIO8 */
+ 3, /* EMACIO9 */
+ 3, /* EMACIO10 */
+ 3, /* EMACIO11 */
+ 3, /* EMACIO12 */
+ 3, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 3, /* FLASHIO4 */
+ 3, /* FLASHIO5 */
+ 3, /* FLASHIO6 */
+ 3, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 0, /* GENERALIO3 */
+ 0, /* GENERALIO4 */
+ 1, /* GENERALIO5 */
+ 1, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 2, /* GENERALIO13 */
+ 2, /* GENERALIO14 */
+ 1, /* GENERALIO15 */
+ 1, /* GENERALIO16 */
+ 1, /* GENERALIO17 */
+ 1, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 0, /* MIXED1IO0 */
+ 1, /* MIXED1IO1 */
+ 1, /* MIXED1IO2 */
+ 1, /* MIXED1IO3 */
+ 1, /* MIXED1IO4 */
+ 0, /* MIXED1IO5 */
+ 0, /* MIXED1IO6 */
+ 0, /* MIXED1IO7 */
+ 1, /* MIXED1IO8 */
+ 1, /* MIXED1IO9 */
+ 1, /* MIXED1IO10 */
+ 1, /* MIXED1IO11 */
+ 0, /* MIXED1IO12 */
+ 0, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 1, /* MIXED1IO15 */
+ 1, /* MIXED1IO16 */
+ 1, /* MIXED1IO17 */
+ 1, /* MIXED1IO18 */
+ 0, /* MIXED1IO19 */
+ 0, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 1, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 3125000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 100000000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ 0x4C
+#define RW_MGR_GUARANTEED_READ_CONT 0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7B
+#define RW_MGR_IDLE_LOOP2 0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1 0x61
+#define RW_MGR_READ_B2B_WAIT2 0x6B
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7D
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 99
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 99
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080421,
+ 0x10080520,
+ 0x10090044,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080441,
+ 0x100804c0,
+ 0x100a0024,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+#include <common.h>
# Patrick Bruenn <p.bruenn@beckhoff.com>
obj-y += mx53cx9020.o
-obj-$(CONFIG_VIDEO) += mx53cx9020_video.o
+obj-$(CONFIG_DM_VIDEO) += mx53cx9020_video.o
*/
#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
-#include <asm/arch/clock.h>
#include <asm/mach-imx/mx5_video.h>
#include <ACEX1K.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
#include <asm/gpio.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-#include <input.h>
-#include <fs.h>
-#include <dm/platform_data/serial_mxc.h>
enum LED_GPIOS {
GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
static void setup_gpio_eim(void)
{
+ gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
+ gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
+ gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
gpio_direction_input(GPIO_C3_STATUS);
gpio_direction_input(GPIO_C3_DONE);
gpio_direction_output(GPIO_C3_CONFIG, 1);
static void setup_gpio_sups(void)
{
+ gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
gpio_direction_input(GPIO_SUPS_INT);
static const int BLINK_INTERVALL = 50000;
static void setup_gpio_leds(void)
{
+ gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
+ gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
+ gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
+ gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
+ gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
+ gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
+ gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
+ gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
+ gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
+
gpio_direction_output(GPIO_LED_SD2_R, 0);
gpio_direction_output(GPIO_LED_SD2_B, 0);
gpio_direction_output(GPIO_LED_SD2_G, 0);
}
#endif
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR},
- {MMC_SDHC2_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret;
-
- gpio_direction_input(GPIO_SD1_CD);
- gpio_direction_input(GPIO_SD2_CD);
-
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- ret = !gpio_get_value(GPIO_SD1_CD);
- else
- ret = !gpio_get_value(GPIO_SD2_CD);
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- u32 index;
- int ret;
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
- switch (index) {
- case 0:
- break;
- case 1:
- break;
- default:
- printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return -EINVAL;
- }
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
static int power_init(void)
{
int board_early_init_f(void)
{
- setup_gpio_leds();
- setup_gpio_sups();
- setup_gpio_eim();
- setup_iomux_lcd();
return 0;
}
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
mxc_set_sata_internal_clock();
+ setup_gpio_leds();
+ setup_gpio_sups();
+ setup_gpio_eim();
+ setup_iomux_lcd();
+
return 0;
}
*/
#include <common.h>
-#include <linux/list.h>
-#include <asm/gpio.h>
#include <asm/arch/iomux-mx53.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/video.h>
#define CX9020_DVI_PWD IMX_GPIO_NR(6, 1)
-static struct fb_videomode const vga_640x480 = {
- .name = "VESA_VGA_640x480",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 39721, /* picosecond (25.175 MHz) */
- .left_margin = 40,
- .right_margin = 60,
- .upper_margin = 10,
- .lower_margin = 10,
- .hsync_len = 20,
- .vsync_len = 10,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED
-};
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = NULL,
+ .mode = {
+ .name = "DVI",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 39721, /* picosecond (25.175 MHz) */
+ .left_margin = 40,
+ .right_margin = 60,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 20,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
void setup_iomux_lcd(void)
{
/* Turn on DVI_PWD */
imx_iomux_v3_setup_pad(MX53_PAD_CSI0_DAT15__GPIO6_1);
+ gpio_request(CX9020_DVI_PWD, "CX9020_DVI_PWD");
gpio_direction_output(CX9020_DVI_PWD, 1);
}
-
-int board_video_skip(void)
-{
- const int ret = ipuv3_fb_init(&vga_640x480, 0, IPU_PIX_FMT_RGB24);
- if (ret)
- printf("VESA VG 640x480 cannot be configured: %d\n", ret);
- return ret;
-}
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 Cisco Systems, Inc.
+ * (C) Copyright 2019 Synamedia
*
* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/bootm.h>
-#include <mach/sdhci.h>
#include <mach/timer.h>
#include <mmc.h>
#include <fdtdec.h>
*/
}
-static const phys_addr_t bcmstb_sdhci_address(u32 alias_index)
-{
- int node = 0;
- int ret = 0;
- char sdhci[16] = { 0 };
- const void *fdt = gd->fdt_blob;
- const char *path = NULL;
- struct fdt_resource resource = { 0 };
-
- if (!fdt) {
- printf("%s: Invalid gd->fdt_blob\n", __func__);
- return 0;
- }
-
- node = fdt_path_offset(fdt, "/aliases");
- if (node < 0) {
- printf("%s: Failed to find /aliases node\n", __func__);
- return 0;
- }
-
- sprintf(sdhci, "sdhci%d", alias_index);
- path = fdt_getprop(fdt, node, sdhci, NULL);
- if (!path) {
- printf("%s: Failed to find alias for %s\n", __func__, sdhci);
- return 0;
- }
-
- node = fdt_path_offset(fdt, path);
- if (node < 0) {
- printf("%s: Failed to resolve BCMSTB SDHCI alias\n", __func__);
- return 0;
- }
-
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "host", &resource);
- if (ret) {
- printf("%s: Failed to read BCMSTB SDHCI host resource\n",
- __func__);
- return 0;
- }
-
- return resource.start;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- phys_addr_t sdhci_base_address = 0;
-
- sdhci_base_address = bcmstb_sdhci_address(CONFIG_BCMSTB_SDHCI_INDEX);
-
- if (!sdhci_base_address) {
- sdhci_base_address = BCMSTB_SDHCI_BASE;
- printf("%s: Assuming BCMSTB SDHCI address: 0x%p\n",
- __func__, (void *)sdhci_base_address);
- }
-
- debug("BCMSTB SDHCI base address: 0x%p\n", (void *)sdhci_base_address);
-
- bcmstb_sdhci_init(sdhci_base_address);
-
- return 0;
-}
-
int timer_init(void)
{
gd->arch.timer_rate_hz = readl(BCMSTB_TIMER_FREQUENCY);
+++ /dev/null
-if TARGET_CM_T3517
-
-config SYS_BOARD
- default "cm_t3517"
-
-config SYS_VENDOR
- default "compulab"
-
-config SYS_CONFIG_NAME
- default "cm_t3517"
-
-endif
+++ /dev/null
-CM_T3517 BOARD
-M: Igor Grinberg <grinberg@compulab.co.il>
-S: Maintained
-F: board/compulab/cm_t3517/
-F: include/configs/cm_t3517.h
-F: configs/cm_t3517_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
-#
-# Authors: Igor Grinberg <grinberg@compulab.co.il>
-
-obj-y += cm_t3517.o mux.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
- *
- * Authors: Igor Grinberg <grinberg@compulab.co.il>
- */
-
-#include <common.h>
-#include <environment.h>
-#include <status_led.h>
-#include <net.h>
-#include <netdev.h>
-#include <usb.h>
-#include <mmc.h>
-#include <linux/compiler.h>
-#include <linux/usb/musb.h>
-
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/am35x_def.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/musb.h>
-#include <asm/omap_musb.h>
-#include <asm/ehci-omap.h>
-
-#include "../common/common.h"
-#include "../common/eeprom.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "CM-T3517 board",
- "NAND 128/512M",
-};
-
-#ifdef CONFIG_USB_MUSB_AM35X
-static struct musb_hdrc_config cm_t3517_musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12,
-};
-
-static struct omap_musb_board_data cm_t3517_musb_board_data = {
- .set_phy_power = am35x_musb_phy_power,
- .clear_irq = am35x_musb_clear_irq,
- .reset = am35x_musb_reset,
-};
-
-static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
-#if defined(CONFIG_USB_MUSB_HOST)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_MUSB_GADGET)
- .mode = MUSB_PERIPHERAL,
-#else
-#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
-#endif
- .config = &cm_t3517_musb_config,
- .power = 250,
- .platform_ops = &am35x_ops,
- .board_data = &cm_t3517_musb_board_data,
-};
-
-static void cm_t3517_musb_init(void)
-{
- /*
- * Set up USB clock/mode in the DEVCONF2 register.
- * USB2.0 PHY reference clock is 13 MHz
- */
- clrsetbits_le32(&am35x_scm_general_regs->devconf2,
- CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
- CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
- CONF2_VBDTCTEN | CONF2_DATPOL);
-
- if (!musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
- (void *)AM35XX_IPSS_USBOTGSS_BASE))
- printf("Failed initializing AM35x MUSB!\n");
-}
-#else
-static inline void am3517_evm_musb_init(void) {}
-#endif
-
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
- status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
-#endif
-
- cm_t3517_musb_init();
-
- return 0;
-}
-
-/*
- * Routine: get_board_rev
- * Description: read system revision
- */
-u32 get_board_rev(void)
-{
- return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
-};
-
-int misc_init_r(void)
-{
- cl_print_pcb_info();
- omap_die_id_display();
-
- return 0;
-}
-
-#if defined(CONFIG_MMC)
-#define SB_T35_CD_GPIO 144
-#define SB_T35_WP_GPIO 59
-
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONTROL_EFUSE_EMAC_LSB 0x48002380
-#define CONTROL_EFUSE_EMAC_MSB 0x48002384
-
-static int am3517_get_efuse_enetaddr(u8 *enetaddr)
-{
- u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
- u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
-
- enetaddr[0] = (u8)((msb >> 16) & 0xff);
- enetaddr[1] = (u8)((msb >> 8) & 0xff);
- enetaddr[2] = (u8)(msb & 0xff);
- enetaddr[3] = (u8)((lsb >> 16) & 0xff);
- enetaddr[4] = (u8)((lsb >> 8) & 0xff);
- enetaddr[5] = (u8)(lsb & 0xff);
-
- return is_valid_ethaddr(enetaddr);
-}
-
-static inline int cm_t3517_init_emac(bd_t *bis)
-{
- int ret = cpu_eth_init(bis);
-
- if (ret > 0)
- return ret;
-
- printf("Failed initializing EMAC! ");
- return 0;
-}
-#else /* !CONFIG_DRIVER_TI_EMAC */
-static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
-static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-/*
- * Routine: handle_mac_address
- * Description: prepare MAC address for on-board Ethernet.
- */
-static int cm_t3517_handle_mac_address(void)
-{
- unsigned char enetaddr[6];
- int ret;
-
- ret = eth_env_get_enetaddr("ethaddr", enetaddr);
- if (ret)
- return 0;
-
- ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
- if (ret) {
- ret = am3517_get_efuse_enetaddr(enetaddr);
- if (ret)
- return ret;
- }
-
- if (!is_valid_ethaddr(enetaddr))
- return -1;
-
- return eth_env_set_enetaddr("ethaddr", enetaddr);
-}
-
-#define SB_T35_ETH_RST_GPIO 164
-
-/*
- * Routine: board_eth_init
- * Description: initialize module and base-board Ethernet chips
- */
-int board_eth_init(bd_t *bis)
-{
- int rc = 0, rc1 = 0;
-
- rc1 = cm_t3517_handle_mac_address();
- if (rc1)
- printf("No MAC address found! ");
-
- rc1 = cm_t3517_init_emac(bis);
- if (rc1 > 0)
- rc++;
-
- rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
- NULL, SB_T35_ETH_RST_GPIO);
- if (rc1 > 0)
- rc++;
-
- return rc;
-}
-
-#ifdef CONFIG_USB_EHCI_OMAP
-static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-#define CM_T3517_USB_HUB_RESET_GPIO 152
-#define SB_T35_USB_HUB_RESET_GPIO 98
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
- cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
-
- return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(void)
-{
- cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
- cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
-
- return omap_ehci_hcd_stop();
-}
-#endif /* CONFIG_USB_EHCI_OMAP */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
- *
- * Authors: Igor Grinberg <grinberg@compulab.co.il>
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-
-void set_muxconf_regs(void)
-{
- /* SDRC */
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
-
- /* GPMC */
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
-
- /* SB-T35 Ethernet */
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
- /* DVI enable */
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/
- /* DataImage backlight */
- MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
-
- /* SB-T35 SD/MMC WP GPIO59 */
- MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
- /* SB-T35 Audio Enable GPIO61 */
- MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
- /* SB-T35 Ethernet IRQ GPIO65 */
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/
-
- /* UART3 Console */
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
- /* RTC V3020 nCS GPIO163 */
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
- /* SB-T35 Ethernet nRESET GPIO164 */
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/
-
- /* SB-T35 SD/MMC CD GPIO144 */
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
- /* WIFI nRESET GPIO145 */
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
- /* USB1 PHY Reset GPIO 146 */
- MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/
- /* USB2 PHY Reset GPIO 147 */
- MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
-
- /* MMC1 */
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0));
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0));
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0));
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0));
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0));
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0));
-
- /* DSS */
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));
-
- /* I2C */
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
-
- /* SB-T35 USB HUB Reset GPIO98 */
- MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/
- /* CM-T3517 USB HUB Reset GPIO152 */
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
-
- /* RMII */
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0));
- MUX_VAL(CP(RMII_MDIO_CLK), (M0));
- MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0));
- MUX_VAL(CP(RMII_TXD0), (IDIS | M0));
- MUX_VAL(CP(RMII_TXD1), (IDIS | M0));
- MUX_VAL(CP(RMII_TXEN), (IDIS | M0));
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0));
-
- /* Green LED GPIO186 */
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
-
- /* SPI */
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
- MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
- /* LCD reset GPIO157 */
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
-
- /* RTC V3020 CS Enable GPIO160 */
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
- /* SB-T35 LVDS Transmitter SHDN GPIO162 */
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/
-
- /* USB0 - mUSB */
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0));
- /* USB1 EHCI */
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
- /* USB2 EHCI */
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
-
- /* SYS_BOOT */
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
-}
#define layout_legacy layout_unknown
#endif
-#if defined(CONFIG_CM_T3X) || defined(CONFIG_CM_T3517)
+#if defined(CONFIG_CM_T3X)
struct eeprom_field layout_v1[12] = {
{ "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
{ "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
return -1;
}
- ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET) + 1, 7, addr);
+ ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
if (ret) {
printf("Error - unable to read MAC address from SPI flash.\n");
return -1;
return 0;
}
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
#ifdef CONFIG_MMC_DAVINCI
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+++ /dev/null
-if TARGET_EA20
-
-config SYS_BOARD
- default "ea20"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "ea20"
-
-endif
+++ /dev/null
-EA20 BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/davinci/ea20/
-F: include/configs/ea20.h
-F: configs/ea20_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-
-obj-y += ea20.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de
- *
- * Based on da850evm.c, original Copyrights follow:
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on da830evm.c. Original Copyrights follow:
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/gpio.h>
-#include "../../../drivers/video/da8xx-fb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct da8xx_panel lcd_panel = {
- /* Casio COM57H531x */
- .name = "Casio_COM57H531x",
- .width = 640,
- .height = 480,
- .hfp = 12,
- .hbp = 144,
- .hsw = 30,
- .vfp = 10,
- .vbp = 35,
- .vsw = 3,
- .pxl_clk = 25000000,
- .invert_pxl_clk = 0,
-};
-
-static const struct display_panel disp_panel = {
- QVGA,
- 16,
- 16,
- COLOR_ACTIVE,
-};
-
-static const struct lcd_ctrl_config lcd_cfg = {
- &disp_panel,
- .ac_bias = 255,
- .ac_bias_intrpt = 0,
- .dma_burst_sz = 16,
- .bpp = 16,
- .fdd = 255,
- .tft_alt_mode = 0,
- .stn_565_mode = 0,
- .mono_8bit_mode = 0,
- .invert_line_clock = 1,
- .invert_frm_clock = 1,
- .sync_edge = 0,
- .sync_ctrl = 1,
- .raster_order = 0,
-};
-
-/* SPI0 pin muxer settings */
-static const struct pinmux_config spi1_pins[] = {
- { pinmux(5), 1, 1 },
- { pinmux(5), 1, 2 },
- { pinmux(5), 1, 4 },
- { pinmux(5), 1, 5 }
-};
-
-/* I2C pin muxer settings */
-static const struct pinmux_config i2c_pins[] = {
- { pinmux(4), 2, 2 },
- { pinmux(4), 2, 3 }
-};
-
-/* UART0 pin muxer settings */
-static const struct pinmux_config uart_pins[] = {
- { pinmux(3), 2, 7 },
- { pinmux(3), 2, 6 },
- { pinmux(3), 2, 4 },
- { pinmux(3), 2, 5 }
-};
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define HAS_RMII 1
-static const struct pinmux_config emac_pins[] = {
- { pinmux(14), 8, 2 },
- { pinmux(14), 8, 3 },
- { pinmux(14), 8, 4 },
- { pinmux(14), 8, 5 },
- { pinmux(14), 8, 6 },
- { pinmux(14), 8, 7 },
- { pinmux(15), 8, 1 },
- { pinmux(4), 8, 0 },
- { pinmux(4), 8, 1 }
-};
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-const struct pinmux_config nand_pins[] = {
- { pinmux(7), 1, 0}, /* CS2 */
- { pinmux(7), 0, 1}, /* CS3 in three state*/
- { pinmux(7), 1, 4 }, /* EMA_WE */
- { pinmux(7), 1, 5 }, /* EMA_OE */
- { pinmux(9), 1, 0 }, /* EMA_D[7] */
- { pinmux(9), 1, 1 }, /* EMA_D[6] */
- { pinmux(9), 1, 2 }, /* EMA_D[5] */
- { pinmux(9), 1, 3 }, /* EMA_D[4] */
- { pinmux(9), 1, 4 }, /* EMA_D[3] */
- { pinmux(9), 1, 5 }, /* EMA_D[2] */
- { pinmux(9), 1, 6 }, /* EMA_D[1] */
- { pinmux(9), 1, 7 }, /* EMA_D[0] */
- { pinmux(12), 1, 5 }, /* EMA_A[2] */
- { pinmux(12), 1, 6 }, /* EMA_A[1] */
- { pinmux(6), 1, 0 } /* EMA_CLK */
-};
-#endif
-
-const struct pinmux_config gpio_pins[] = {
- { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
- { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
- { pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/
- { pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */
- { pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/
-};
-
-const struct pinmux_config lcd_pins[] = {
- { pinmux(17), 2, 1 }, /* LCD_D_0 */
- { pinmux(17), 2, 0 }, /* LCD_D_1 */
- { pinmux(16), 2, 7 }, /* LCD_D_2 */
- { pinmux(16), 2, 6 }, /* LCD_D_3 */
- { pinmux(16), 2, 5 }, /* LCD_D_4 */
- { pinmux(16), 2, 4 }, /* LCD_D_5 */
- { pinmux(16), 2, 3 }, /* LCD_D_6 */
- { pinmux(16), 2, 2 }, /* LCD_D_7 */
- { pinmux(18), 2, 1 }, /* LCD_D_8 */
- { pinmux(18), 2, 0 }, /* LCD_D_9 */
- { pinmux(17), 2, 7 }, /* LCD_D_10 */
- { pinmux(17), 2, 6 }, /* LCD_D_11 */
- { pinmux(17), 2, 5 }, /* LCD_D_12 */
- { pinmux(17), 2, 4 }, /* LCD_D_13 */
- { pinmux(17), 2, 3 }, /* LCD_D_14 */
- { pinmux(17), 2, 2 }, /* LCD_D_15 */
- { pinmux(18), 2, 6 }, /* LCD_PCLK */
- { pinmux(19), 2, 0 }, /* LCD_HSYNC */
- { pinmux(19), 2, 1 }, /* LCD_VSYNC */
- { pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */
-};
-
-const struct pinmux_config halten_pin[] = {
- { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */
-};
-
-static const struct pinmux_resource pinmuxes[] = {
-#ifdef CONFIG_SPI_FLASH
- PINMUX_ITEM(spi1_pins),
-#endif
- PINMUX_ITEM(uart_pins),
- PINMUX_ITEM(i2c_pins),
-#ifdef CONFIG_NAND_DAVINCI
- PINMUX_ITEM(nand_pins),
-#endif
-#ifdef CONFIG_VIDEO
- PINMUX_ITEM(lcd_pins),
-#endif
-};
-
-static const struct lpsc_resource lpsc[] = {
- { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
- { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
- { DAVINCI_LPSC_EMAC }, /* image download */
- { DAVINCI_LPSC_UART0 }, /* console */
- { DAVINCI_LPSC_GPIO },
- { DAVINCI_LPSC_LCDC }, /* LCD */
-};
-
-int board_early_init_f(void)
-{
- /* PinMux for GPIO */
- if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
- return 1;
-
- /* Set DISP_ON high to enable LCD output*/
- gpio_direction_output(97, 1);
-
- /* Set the RESETOUTn low */
- gpio_direction_output(111, 0);
-
- /* Set U0_SW0 low for UART0 as console*/
- gpio_direction_output(106, 0);
-
- /* Set U0_SW1 low for UART0 as console*/
- gpio_direction_output(108, 0);
-
- /* Set LCD_B_PWR low to power down LCD Backlight*/
- gpio_direction_output(102, 0);
-
- irq_init();
-
- /*
- * NAND CS setup - cycle counts based on da850evm NAND timings in the
- * Linux kernel @ 25MHz EMIFA
- */
-#ifdef CONFIG_NAND_DAVINCI
- writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(1) |
- DAVINCI_ABCR_WHOLD(0) |
- DAVINCI_ABCR_RSETUP(0) |
- DAVINCI_ABCR_RSTROBE(1) |
- DAVINCI_ABCR_RHOLD(0) |
- DAVINCI_ABCR_TA(0) |
- DAVINCI_ABCR_ASIZE_8BIT),
- &davinci_emif_regs->ab1cr); /* CS2 */
-#endif
-
- /*
- * Power on required peripherals
- * ARM does not have access by default to PSC0 and PSC1
- * assuming here that the DSP bootloader has set the IOPU
- * such that PSC access is available to ARM
- */
- if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
- return 1;
-
- /* setup the SUSPSRC for ARM to control emulation suspend */
- writel(readl(&davinci_syscfg_regs->suspsrc) &
- ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
- DAVINCI_SYSCFG_SUSPSRC_UART0),
- &davinci_syscfg_regs->suspsrc);
-
- /* configure pinmux settings */
- if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
- return 1;
-
-#ifdef CONFIG_DRIVER_TI_EMAC
- if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
- return 1;
-
- davinci_emac_mii_mode_sel(HAS_RMII);
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
- /* enable the console UART */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
- &davinci_uart0_ctrl_regs->pwremu_mgmt);
-
- /*
- * Reconfigure the LCDC priority to the highest to ensure that
- * the throughput/latency requirements for the LCDC are met.
- */
- writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
- &davinci_syscfg_regs->mstpri[2]);
-
-
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int board_init(void)
-{
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_EA20;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- da8xx_video_init(&lcd_panel, &lcd_cfg, 16);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-
-int board_late_init(void)
-{
- unsigned char buf[2];
- int ret;
-
- /* PinMux for HALTEN */
- if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
- return 1;
-
- /* Set HALTEN to high */
- gpio_direction_output(134, 1);
-
- /* Set fixed contrast settings for LCD via I2C potentiometer */
- buf[0] = 0x00;
- buf[1] = 0xd7;
- ret = i2c_write(0x2e, 6, 1, buf, 2);
- if (ret)
- puts("\nContrast Settings FAILED\n");
-
- /* Set LCD_B_PWR high to power up LCD Backlight*/
- gpio_set_value(102, 1);
- return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-/*
- * Initializes on-board ethernet controllers.
- */
-int board_eth_init(bd_t *bis)
-{
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- /*
- * This board has a RMII PHY. However, the MDC line on the SOM
- * must not be disabled (there is no MII PHY on the
- * baseboard) via the GPIO2[6], because this pin
- * disables at the same time the SPI flash.
- */
-
- return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
};
static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
- .p0_mpwldectrl0 = 0x0011000E,
- .p0_mpwldectrl1 = 0x000E001B,
- .p1_mpwldectrl0 = 0x00190015,
- .p1_mpwldectrl1 = 0x00070018,
- .p0_mpdgctrl0 = 0x42720306,
- .p0_mpdgctrl1 = 0x026F0266,
- .p1_mpdgctrl0 = 0x4273030A,
- .p1_mpdgctrl1 = 0x02740240,
- .p0_mprddlctl = 0x45393B3E,
- .p1_mprddlctl = 0x403A3747,
- .p0_mpwrdlctl = 0x40434541,
- .p1_mpwrdlctl = 0x473E4A3B,
+ .p0_mpwldectrl0 = 0x001a001a,
+ .p0_mpwldectrl1 = 0x00260015,
+ .p0_mpdgctrl0 = 0x030c0320,
+ .p0_mpdgctrl1 = 0x03100304,
+ .p0_mprddlctl = 0x432e3538,
+ .p0_mpwrdlctl = 0x363f423d,
+ .p1_mpwldectrl0 = 0x0006001e,
+ .p1_mpwldectrl1 = 0x00050015,
+ .p1_mpdgctrl0 = 0x031c0324,
+ .p1_mpdgctrl1 = 0x030c0258,
+ .p1_mprddlctl = 0x3834313f,
+ .p1_mpwrdlctl = 0x47374a42,
};
static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
SETUP_IOMUX_PADS(usb_pads);
}
+/* Perform DDR DRAM calibration */
+static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+ int ret = 0;
+
+#ifdef CONFIG_MX6_DDRCAL
+ udelay(100);
+ ret = mmdc_do_write_level_calibration(sysinfo);
+ if (ret) {
+ printf("DDR3: Write level calibration error [%d]\n", ret);
+ return ret;
+ }
+
+ ret = mmdc_do_dqs_calibration(sysinfo);
+ if (ret) {
+ printf("DDR3: DQS calibration error [%d]\n", ret);
+ return ret;
+ }
+#endif /* CONFIG_MX6_DDRCAL */
+
+ return ret;
+}
+
/* DRAM */
static void dhcom_spl_dram_init(void)
}
/* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
+ spl_dram_perform_cal(&dhcom_ddr_64bit);
} else if (is_cpu_type(MXC_CPU_MX6DL)) {
mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
}
/* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
+ spl_dram_perform_cal(&dhcom_ddr_64bit);
} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
}
/* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
+ spl_dram_perform_cal(&dhcom_ddr_32bit);
}
}
#include <common.h>
#include <asm/io.h>
#include <fdtdec.h>
-#include <asm/arch/grf_rv1108.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/grf_rv1108.h>
+#include <asm/arch-rockchip/hardware.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
config SYS_TEXT_BASE
default 0x80000000 if !RISCV_SMODE
- default 0x80200000 if RISCV_SMODE
+ default 0x80200000 if RISCV_SMODE && ARCH_RV64I
+ default 0x80400000 if RISCV_SMODE && ARCH_RV32I
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
imply OF_BOARD_SETUP
imply SIFIVE_SERIAL
imply SMP
+ imply PCI
+ imply DM_PCI
+ imply PCIE_ECAM_GENERIC
+ imply CMD_PCI
+ imply E1000
+ imply NVME
endif
default "vme8349"
endif
+
+if TARGET_CADDY2
+
+config SYS_BOARD
+ default "vme8349"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "caddy2"
+
+endif
return -ENXIO;
/* DDR SDRAM - Main memory */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = spd_sdram();
int checkboard(void)
{
-#ifdef VME_CADDY2
+#ifdef CONFIG_TARGET_CADDY2
puts("Board: esd VME-CADDY/2\n");
#else
puts("Board: esd VME-CPU/8349\n");
return 0;
}
-#ifdef VME_CADDY2
+#ifdef CONFIG_TARGET_CADDY2
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
* and VME-CADDY/2) have different SDRAM configurations.
*/
-#ifdef VME_CADDY2
+#ifdef CONFIG_TARGET_CADDY2
#define SMALL_RAM 0xff
#define LARGE_RAM 0x00
#else
SPD_VAL(0x7e, 0x1d), /* 63 */
{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
SPD_VAL(0x00, 0x00), /* 72 */
-#ifdef VME_CADDY2
+#ifdef CONFIG_TARGET_CADDY2
{ "vme-caddy/2 ram " }
#else
{ "vme-cpu/2 ram " }
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(CONFIG_MPC832XEMDS)
+#if defined(CONFIG_TARGET_MPC832XEMDS)
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
#else
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
eieio();
-#if defined(CONFIG_MPC832XEMDS)
+#if defined(CONFIG_TARGET_MPC832XEMDS)
printf("PCI 32bit bus on PMC2 &PMC3\n");
#else
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
eieio();
printf("QOC3 ATM card on PMC0\n");
-#elif defined(CONFIG_MPC832XEMDS)
+#elif defined(CONFIG_TARGET_MPC832XEMDS)
val8 = 0;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf7;
--- /dev/null
+if TARGET_IMX8QM_MEK
+
+config SYS_BOARD
+ default "imx8qm_mek"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx8qm_mek"
+
+source "board/freescale/common/Kconfig"
+
+endif
--- /dev/null
+i.MX8QM MEK BOARD
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/imx8qm_mek/
+F: include/configs/imx8qm_mek.h
+F: configs/imx8qm_mek_defconfig
--- /dev/null
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8qm_mek.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
--- /dev/null
+U-Boot for the NXP i.MX8QM EVK board
+
+Quick Start
+===========
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ cd imx-atf/
+$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
+$ make PLAT=imx8qm bl31
+
+Get scfw_tcm.bin and ahab-container.img
+==============================
+
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
+$ chmod +x imx-sc-firmware-1.1.bin
+$ ./imx-sc-firmware-1.1.bin
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+$ chmod +x firmware-imx-8.0.bin
+$ ./firmware-imx-8.0.bin
+
+Copy the following binaries to U-Boot folder:
+
+$ cp imx-atf/build/imx8qm/release/bl31.bin .
+$ cp u-boot/u-boot.bin .
+
+Copy the following firmwares U-Boot folder :
+
+$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
+$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin .
+
+Build U-Boot
+============
+$ export ATF_LOAD_ADDR=0x80000000
+$ export BL33_LOAD_ADDR=0x80020000
+$ make imx8qm_mek_defconfig
+$ make flash.bin
+$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984
+
+Flash the binary into the SD card
+=================================
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
+
+Boot
+====
+Set Boot switch SW2: 1100.
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+#include <environment.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+ SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+ int ret;
+ /* Set UART0 clock root to 80 MHz */
+ sc_pm_clock_rate_t rate = 80000000;
+
+ /* Power up UART0 */
+ ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
+ if (ret)
+ return ret;
+
+ ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
+ if (ret)
+ return ret;
+
+ /* Enable UART0 clock root */
+ ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
+ if (ret)
+ return ret;
+
+ setup_iomux_uart();
+
+ sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DM_GPIO)
+static void board_gpio_init(void)
+{
+ /* TODO */
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+void build_info(void)
+{
+ u32 sc_build = 0, sc_commit = 0;
+
+ /* Get SCFW build and commit id */
+ sc_misc_build_info(-1, &sc_build, &sc_commit);
+ if (!sc_build) {
+ printf("SCFW does not support build info\n");
+ sc_commit = 0; /* Display 0 when the build info is not supported*/
+ }
+ printf("Build: SCFW %x\n", sc_commit);
+}
+
+int checkboard(void)
+{
+ puts("Board: iMX8QM MEK\n");
+
+ build_info();
+ print_bootinfo();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Power up base board */
+ sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
+
+ board_gpio_init();
+
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+ /* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board_name", "MEK");
+ env_set("board_rev", "iMX8QM");
+#endif
+
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QM */
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-mek-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
--- /dev/null
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int offset;
+
+ uclass_find_first_device(UCLASS_MISC, &dev);
+
+ for (; dev; uclass_find_next_device(&dev)) {
+ if (device_probe(dev))
+ continue;
+ }
+
+ offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
+ while (offset != -FDT_ERR_NOTFOUND) {
+ lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
+ NULL, true);
+ offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+ "nxp,imx8-pd");
+ }
+
+ uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
+
+ for (; dev; uclass_find_next_device(&dev)) {
+ if (device_probe(dev))
+ continue;
+ }
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
void spl_board_init(void)
{
struct udevice *dev;
- int offset;
uclass_find_first_device(UCLASS_MISC, &dev);
continue;
}
- offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
- while (offset != -FDT_ERR_NOTFOUND) {
- lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
- NULL, true);
- offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
- "nxp,imx8-pd");
- }
-
- uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
-
- for (; dev; uclass_find_next_device(&dev)) {
- if (device_probe(dev))
- continue;
- }
-
arch_cpu_init();
board_early_init_f();
--- /dev/null
+if TARGET_LS1028AQDS
+
+config SYS_BOARD
+ default "ls1028a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1028aqds"
+
+config EMMC_BOOT
+ bool "Support for booting from EMMC"
+ default n
+
+config SYS_TEXT_BASE
+ default 0x96000000 if SD_BOOT || EMMC_BOOT
+ default 0x82000000 if TFABOOT
+ default 0x20100000
+
+if FSL_LS_PPA
+config SYS_LS_PPA_FW_ADDR
+ hex "PPA Firmware Addr"
+ default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+ default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A
+if CHAIN_OF_TRUST
+config SYS_LS_PPA_ESBC_ADDR
+ hex "PPA header Addr"
+ default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
+endif
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
+
+if TARGET_LS1028ARDB
+
+config SYS_BOARD
+ default "ls1028a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1028ardb"
+
+config EMMC_BOOT
+ bool "Support for booting from EMMC"
+ default n
+
+config SYS_TEXT_BASE
+ default 0x96000000 if SD_BOOT || EMMC_BOOT
+ default 0x82000000 if TFABOOT
+ default 0x20100000
+
+source "board/freescale/common/Kconfig"
+
+endif
--- /dev/null
+LS1028AQDS BOARD
+M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
+M: Rai Harninder <harninder.rai@nxp.com>
+M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M: Tang Yuantian <andy.tang@nxp.com>
+S: Maintained
+F: board/freescale/ls1028a/
+F: include/configs/ls1028a_common.h
+F: include/configs/ls1028aqds.h
+F: configs/ls1028aqds_tfa_defconfig
+
+LS1028ARDB BOARD
+M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
+M: Rai Harninder <harninder.rai@nxp.com>
+M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M: Tang Yuantian <andy.tang@nxp.com>
+S: Maintained
+F: board/freescale/ls1028a/
+F: include/configs/ls1028a_common.h
+F: include/configs/ls1028ardb.h
+F: configs/ls1028ardb_tfa_defconfig
--- /dev/null
+#
+# Copyright 2019 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1028a.o
+obj-y += ddr.o
--- /dev/null
+Overview
+--------
+The LS1028A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports ARM SoC LS1028A and its
+derivatives.
+
+LS1028A SoC Overview
+--------------------------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+RDB Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+For XSPI NOR boot (default)
+SW2: 1111_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+For SD Boot
+SW2: 1000_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+For eMMC Boot
+SW2: 1001_1000
+SW3: 1111_0000
+SW5: 0011_1001
+
+LS1028ARDB board Overview
+-------------------------
+Processor
+ Two Arm Cortex- A72 processor cores:
+ - Based on 64-bit ARMv8 architecture
+ - Up to 1.3 GHz operation
+ - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
+ data cache
+ - Arranged as a single cluster of two cores sharing a single 1 MB L2
+ cache
+DDR memory
+ - Five onboard 1G x8 discrete memory modules (Four data byte lanes
+ ECC)
+ - 32-bit data and 4-bit ECC
+ - One chip select
+ - Data transfer rates of up to 1.6 GT/s
+ - Single-bit error correction and double-bit error detection ECC (4-bit
+ check word across 32-bit data)
+High-speed serial ports(SerDes)
+ - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
+ Qualcomm AR8033 PHY
+ - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
+ through the NXP F104S8A PHY
+ - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
+ (8 Gbit/s) cards
+ - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
+ slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
+ SATA Gen 3 cards (6 Gbit/s) at a time
+eSDHC
+ - eSDHC1, eSDHC2
+SPI
+ - Connects to two mikroBUS sockets to support mikro-click modules,
+ such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
+ field communications (NFC) controller
+Octal SPI (XSPI)
+ - One 256 MB onboard XSPI serial NOR flash memory
+ - One 512 MB onboard XSPI serial NAND flash memory
+ - Supports a QSPI emulator for offboard QSPI emulation
+I2C
+ - All system devices are accessed via I2C1, which is multiplexed on
+ I2C multiplexer PCA9848 to isolate address conflicts and reduce
+ capacitive load
+ - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
+ thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
+ 1 and 2
+CAN
+ - The two CAN DB9 ports can support CAN FD fast phase at data rates of
+ up to 5 Mbit/s
+Serial audio interface(SAI)
+ - Audio codec SGTL5000 provides headphone and audio LINEOUT for
+ stereo speakers
+ - IEEE1588 interface to support audio on SAI4
+
+QDS Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+For SD Boot
+SW1 : 1000_0000
+SW2 : 1110_0110
+SW3 : 0000_0010
+SW4 : 0000_0000
+SW5 : 0000_0000
+SW6 : 0000_0000
+SW7 : 1111_0011
+SW8 : 1110_0000
+SW9 : 1000_0001
+SW10: 1110_0000
+
+For XSPI Boot
+SW1 : 1111_0000
+SW2 : 0000_0110
+SW3 : 0000_0010
+SW4 : 0000_0000
+SW5 : 0110_0000
+SW6 : 0101_0000
+SW7 : 1111_0011
+SW8 : 1110_0000
+SW9 : 1000_0000
+SW10: 1110_0000
+
+LS1028AQDS board Overview
+-------------------------
+Processor
+ Two Arm Cortex- A72 processor cores:
+ - Based on 64-bit ARMv8 architecture
+ - Up to 1.3 GHz operation
+ - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
+ data cache
+ - Arranged as a single cluster of two cores sharing a single 1 MB L2
+ cache
+DDR memory
+ - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L
+ - Supports a single- or dual-ranked SODIMM or UDIMM connector
+ - 32-bit data and 4-bit ECC
+ - Supports x8/x16 devices
+ - Supports ECC error detection and correction
+ - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to
+ all devices in case of DDR3L or DDR4, respectively. Power can
+ switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or
+ DDR4 devices, respectively
+SerDes (Serializer/Deserializer)
+ - Four-lane (0-3) SerDes:
+ - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
+ Gbit SXGMII, 1 Gbit SGMII
+ - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+ SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII
+ - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+ SGMII
+ - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
+ SGMII, SATA 2.0/3.0
+ - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII
+ add-in cards
+ - Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
+ lane 2 (TX lines) connects to an SMA connector
+ Lane 3 connects to 1x7 header to support SATA devices
+eSDHC
+ - eSDHC1, eSDHC2
+SPI
+ - SPI1 and SPI2 support three onboard SPI flash memory devices:
+ 512 Mbit high-speed flash (with speed of up to 108/54 MHz)
+ memory for storage
+ 4 Mbit low-speed flash memory (with speed of up to 40 MHz)
+ 64 Mbit high-speed flash memory (with speed of up to 104/80
+ MHz)
+ - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of
+ up to 104/80 MHz)
+ - All memories operate at 1.8 V
+ - A header is provided on SPI1 to test SPI slave mode
+I2C
+ - LS1028A supports eight I2C controllers
+Serial audio interface(SAI)
+ Two SAI ports with audio codec SGTL5000:
+ - Include stereo LINEIN with support for external analog input
+ - Provide headphone and line output
+Display
+ - DisplayPort connector to connect the DP data to a 4K display device
+ (computer monitor)
+ - eDP connector to connect the DP data to a 4K display panel
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <hwconfig.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <environment.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+#include "../common/qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int config_board_mux(void)
+{
+#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
+ u8 reg;
+
+ reg = QIXIS_READ(brdcfg[13]);
+ /* Field| Function
+ * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
+ * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
+ * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
+ * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
+ */
+ reg &= ~(0xf0);
+ reg |= 0xb0;
+ QIXIS_WRITE(brdcfg[13], reg);
+
+ reg = QIXIS_READ(brdcfg[15]);
+ /* Field| Function
+ * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
+ * CAN1 | 0= CAN #1 transceiver enabled
+ * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
+ * CAN2 | 0= CAN #2 transceiver enabled
+ */
+ reg &= ~(0xc0);
+ QIXIS_WRITE(brdcfg[15], reg);
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+ ppa_init();
+#endif
+
+#ifndef CONFIG_SYS_EARLY_PCI_INIT
+ pci_init();
+#endif
+
+#if defined(CONFIG_TARGET_LS1028ARDB)
+ u8 val = I2C_MUX_CH_DEFAULT;
+
+ i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
+#endif
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ config_board_mux();
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+ i2c_early_init_f();
+#endif
+
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the two GPP DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+#endif
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_QIXIS
+int checkboard(void)
+{
+#ifdef CONFIG_TFABOOT
+ enum boot_src src = get_boot_src();
+#endif
+ u8 sw;
+
+ int clock;
+ char *board;
+ char buf[64] = {0};
+ static const char *freq[6] = {"100.00", "125.00", "156.25",
+ "161.13", "322.26", "100.00 SS"};
+
+ cpu_name(buf);
+ /* find the board details */
+ sw = QIXIS_READ(id);
+
+ switch (sw) {
+ case 0x46:
+ board = "QDS";
+ break;
+ case 0x47:
+ board = "RDB";
+ break;
+ case 0x49:
+ board = "HSSI";
+ break;
+ default:
+ board = "unknown";
+ break;
+ }
+
+ sw = QIXIS_READ(arch);
+ printf("Board: %s-%s, Version: %c, boot from ",
+ buf, board, (sw & 0xf) + 'A' - 1);
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+#ifdef CONFIG_TFABOOT
+ if (src == BOOT_SOURCE_SD_MMC) {
+ puts("SD\n");
+ } else if (src == BOOT_SOURCE_SD_MMC2) {
+ puts("eMMC\n");
+ } else {
+#endif
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#elif defined(CONFIG_EMMC_BOOT)
+ puts("eMMC\n");
+#else
+ switch (sw) {
+ case 0:
+ case 4:
+ printf("NOR\n");
+ break;
+ case 1:
+ printf("NAND\n");
+ break;
+ default:
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+ break;
+ }
+#endif
+#ifdef CONFIG_TFABOOT
+ }
+#endif
+
+ printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
+ puts("SERDES1 Reference : ");
+
+ sw = QIXIS_READ(brdcfg[2]);
+#ifdef CONFIG_TARGET_LS1028ARDB
+ clock = (sw >> 6) & 3;
+#else
+ clock = (sw >> 4) & 0xf;
+#endif
+
+ printf("Clock1 = %sMHz ", freq[clock]);
+#ifdef CONFIG_TARGET_LS1028ARDB
+ clock = (sw >> 4) & 3;
+#else
+ clock = sw & 0xf;
+#endif
+ printf("Clock2 = %sMHz\n", freq[clock]);
+
+ return 0;
+}
+#endif
int board_init(void)
{
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+ u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
+ /* invert AQR107 IRQ pins polarity */
+ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
+#endif
+
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ CONFIG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)
-if TARGET_MPC8313ERDB
+if TARGET_MPC8313ERDB_NOR
config SYS_BOARD
default "mpc8313erdb"
default "freescale"
config SYS_CONFIG_NAME
- default "MPC8313ERDB"
+ default "MPC8313ERDB_NOR"
+
+endif
+
+if TARGET_MPC8313ERDB_NAND
+
+config SYS_BOARD
+ default "mpc8313erdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8313ERDB_NAND"
endif
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
*/
__udelay(50000);
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
CSBNDS_EA);
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
+ /* LB refresh timer prescal, 266MHz/32 */
+ lbc->mrtpr = 0x20000000;
sync();
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
F: board/freescale/mpc8315erdb/
F: include/configs/MPC8315ERDB.h
F: configs/MPC8315ERDB_defconfig
+F: configs/MPC8315ERDB_NANDSPL_defconfig
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();
default "MPC8349EMDS"
endif
+
+if TARGET_MPC8349EMDS_SDRAM
+
+config SYS_BOARD
+ default "mpc8349emds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8349EMDS_SDRAM"
+
+endif
F: board/freescale/mpc8349emds/
F: include/configs/MPC8349EMDS.h
F: configs/MPC8349EMDS_defconfig
+F: configs/MPC8349EMDS_SDRAM_defconfig
+F: configs/MPC8349EMDS_PCI64_defconfig
+F: configs/MPC8349EMDS_SLAVE_defconfig
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
u32 ddr_size = msize << 20; /* DDR size in bytes */
u32 ddr_size_log2 = __ilog2(ddr_size);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[2].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
+ const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+ LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+ LSDMR_WRC3 | LSDMR_CL3;
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->lbcr = 0x00000000;
+ /* LB refresh timer prescal, 266MHz/32 */
+ lbc->mrtpr = 0x20000000;
+ /* LB sdram refresh timer, about 6us */
+ lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+
+ /* 0x68636733; precharge all the banks */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ /* 0x48636733; auto refresh */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
udelay(100);
/* 0x58636733; mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(PCI_64BIT)
+#if defined(CONFIG_PCI_64BIT)
val8 = 0xf4; /* PMC2:PCI1/64-bit */
-#elif defined(PCI_ALL_PCI1)
+#elif defined(CONFIG_PCI_ALL_PCI1)
val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
-#elif defined(PCI_ONE_PCI1)
+#elif defined(CONFIG_PCI_ONE_PCI1)
val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
#else
val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
-#if defined(PCI_64BIT)
+#if defined(CONFIG_PCI_64BIT)
printf("PCI1: 64-bit on PMC2\n");
-#elif defined(PCI_ALL_PCI1)
+#elif defined(CONFIG_PCI_ALL_PCI1)
printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
-#elif defined(PCI_ONE_PCI1)
+#elif defined(CONFIG_PCI_ONE_PCI1)
printf("PCI1: 32-bit on PMC1\n");
printf("PCI2: 32-bit on PMC2, PMC3\n");
#else
#include <linux/libfdt.h>
#endif
+#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
+#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
+
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPD_EEPROM
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#ifdef CONFIG_SPD_EEPROM
msize = spd_sdram();
#else
int checkboard(void)
{
-#ifdef CONFIG_MPC8349ITX
+#ifdef CONFIG_TARGET_MPC8349ITX
puts("Board: Freescale MPC8349E-mITX\n");
#else
puts("Board: Freescale MPC8349E-mITX-GP\n");
F: board/freescale/mpc837xemds/
F: include/configs/MPC837XEMDS.h
F: configs/MPC837XEMDS_defconfig
+F: configs/MPC837XEMDS_SLAVE_defconfig
F: configs/MPC837XEMDS_HOST_defconfig
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
#if (CONFIG_SYS_DDR_SIZE != 512)
F: board/freescale/mpc837xerdb/
F: include/configs/MPC837XERDB.h
F: configs/MPC837XERDB_defconfig
+F: configs/MPC837XERDB_SLAVE_defconfig
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
-obj-$(CONFIG_IO) += miiphybb.o
-obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
-obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
-obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
-obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
-obj-$(CONFIG_STRIDER) += fanctrl.o
+obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
+obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
+obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o
obj-$(CONFIG_STRIDER_CON) += osd.o
obj-$(CONFIG_STRIDER_CON_DP) += osd.o
+obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
ifdef CONFIG_OSD
obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <i2c.h>
return res;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
/* Chrontel CH7301C DVI Transmitter */
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <asm/io.h>
#include <errno.h>
return 0;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
#include <gdsys_fpga.h>
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+#include <dm.h>
+#include <misc.h>
+#include <regmap.h>
+#include <board.h>
+
+#include "../../../drivers/misc/gdsys_soc.h"
+#include "../../../drivers/misc/gdsys_ioep.h"
+#include "../../../drivers/misc/ihs_fpga.h"
+
+const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2;
+#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
+
+enum status_print_type {
+ STATUS_LOUD = 0,
+ STATUS_SILENT = 1,
+};
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
enum {
- STATE_TX_PACKET_BUILDING = 1<<0,
- STATE_TX_TRANSMITTING = 1<<1,
- STATE_TX_BUFFER_FULL = 1<<2,
- STATE_TX_ERR = 1<<3,
- STATE_RECEIVE_TIMEOUT = 1<<4,
- STATE_PROC_RX_STORE_TIMEOUT = 1<<5,
- STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6,
- STATE_RX_DIST_ERR = 1<<7,
- STATE_RX_LENGTH_ERR = 1<<8,
- STATE_RX_FRAME_CTR_ERR = 1<<9,
- STATE_RX_FCS_ERR = 1<<10,
- STATE_RX_PACKET_DROPPED = 1<<11,
- STATE_RX_DATA_LAST = 1<<12,
- STATE_RX_DATA_FIRST = 1<<13,
- STATE_RX_DATA_AVAILABLE = 1<<15,
+ STATE_TX_PACKET_BUILDING = BIT(0),
+ STATE_TX_TRANSMITTING = BIT(1),
+ STATE_TX_BUFFER_FULL = BIT(2),
+ STATE_TX_ERR = BIT(3),
+ STATE_RECEIVE_TIMEOUT = BIT(4),
+ STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
+ STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
+ STATE_RX_DIST_ERR = BIT(7),
+ STATE_RX_LENGTH_ERR = BIT(8),
+ STATE_RX_FRAME_CTR_ERR = BIT(9),
+ STATE_RX_FCS_ERR = BIT(10),
+ STATE_RX_PACKET_DROPPED = BIT(11),
+ STATE_RX_DATA_LAST = BIT(12),
+ STATE_RX_DATA_FIRST = BIT(13),
+ STATE_RX_DATA_AVAILABLE = BIT(15),
};
enum {
- CTRL_PROC_RECEIVE_ENABLE = 1<<12,
- CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15,
+ IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
+ IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
+ IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
+ IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
};
enum {
- IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5,
- IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6,
- IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7,
- IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8,
+ CTRL_PROC_RECEIVE_ENABLE = BIT(12),
+ CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
};
struct io_generic_packet {
u8 bc;
u16 packet_length;
} __attribute__((__packed__));
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
unsigned long long rx_ctr;
unsigned long long tx_ctr;
unsigned long long err_ctr;
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+struct udevice *dev;
+#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
-static void io_check_status(unsigned int fpga, u16 status, bool silent)
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_check_status(uint fpga, u16 status, enum status_print_type type)
{
u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
err_ctr++;
FPGA_SET_REG(fpga, ep.rx_tx_status, status);
- if (silent)
+ if (type == STATUS_SILENT)
+ return;
+
+ if (status & STATE_RX_PACKET_DROPPED)
+ printf("RX_PACKET_DROPPED, status %04x\n", status);
+
+ if (status & STATE_RX_DIST_ERR)
+ printf("RX_DIST_ERR\n");
+ if (status & STATE_RX_LENGTH_ERR)
+ printf("RX_LENGTH_ERR\n");
+ if (status & STATE_RX_FRAME_CTR_ERR)
+ printf("RX_FRAME_CTR_ERR\n");
+ if (status & STATE_RX_FCS_ERR)
+ printf("RX_FCS_ERR\n");
+
+ if (status & STATE_TX_ERR)
+ printf("TX_ERR\n");
+}
+#else
+static void io_check_status(struct udevice *dev, enum status_print_type type)
+{
+ u16 status = 0;
+ int ret;
+
+ ret = misc_call(dev, 0, NULL, 0, &status, 0);
+ if (!ret)
+ return;
+
+ err_ctr++;
+
+ if (type != STATUS_LOUD)
return;
if (status & STATE_RX_PACKET_DROPPED)
if (status & STATE_TX_ERR)
printf("TX_ERR\n");
}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
-static void io_send(unsigned int fpga, unsigned int size)
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_send(uint fpga, uint size)
{
- unsigned int k;
+ uint k;
struct io_generic_packet packet = {
.source_address = 1,
.packet_type = 1,
tx_ctr++;
}
+#else
+static void io_send(struct udevice *dev, uint size)
+{
+ uint k;
+ u16 buffer[HEADER_WORDS + 128];
+ struct io_generic_packet header = {
+ .source_address = 1,
+ .packet_type = 1,
+ .packet_length = size,
+ };
+ const uint words = (size + 1) / 2;
+
+ memcpy(buffer, &header, 2 * HEADER_WORDS);
+ for (k = 0; k < words; ++k)
+ buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8);
+
+ misc_write(dev, 0, buffer, HEADER_WORDS + words);
+
+ tx_ctr++;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
-static void io_receive(unsigned int fpga)
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_receive(uint fpga)
{
- unsigned int k = 0;
u16 rx_tx_status;
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
FPGA_GET_REG(fpga, ep.receive_data, &rx);
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
-
- ++k;
}
}
+#else
+static void io_receive(struct udevice *dev)
+{
+ u16 buffer[HEADER_WORDS + 128];
-static void io_reflect(unsigned int fpga)
+ if (!misc_read(dev, 0, buffer, 0))
+ rx_ctr++;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_reflect(uint fpga)
{
u16 buffer[128];
- unsigned int k = 0;
- unsigned int n;
+ uint k = 0;
+ uint n;
u16 rx_tx_status;
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
tx_ctr++;
}
+#else
+static void io_reflect(struct udevice *dev)
+{
+ u16 buffer[HEADER_WORDS + 128];
+ struct io_generic_packet *header;
+ if (misc_read(dev, 0, buffer, 0))
+ return;
+
+ header = (struct io_generic_packet *)&buffer;
+
+ misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length);
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
/*
* FPGA io-endpoint reflector
*
*/
int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned int fpga;
- unsigned int rate = 0;
+ uint fpga;
+ uint rate = 0;
unsigned long long last_seen = 0;
if (argc < 2)
if (argc > 2)
rate = simple_strtoul(argv[2], NULL, 10);
- /* enable receive path */
+ /* Enable receive path */
FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
- /* set device address to dummy 1*/
+ /* Set device address to dummy 1*/
FPGA_SET_REG(fpga, ep.device_address, 1);
rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
FPGA_GET_REG(fpga, top_interrupt, &top_int);
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
- io_check_status(fpga, rx_tx_status, true);
+ io_check_status(fpga, rx_tx_status, STATUS_SILENT);
if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
io_reflect(fpga);
return 0;
}
+#else
+/*
+ * FPGA io-endpoint reflector
+ *
+ * Syntax:
+ * ioreflect {reportrate}
+ */
+int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *fpga;
+ struct regmap *map;
+ uint rate = 0;
+ unsigned long long last_seen = 0;
+ if (!dev) {
+ printf("No device selected\n");
+ return 1;
+ }
+
+ gdsys_soc_get_fpga(dev, &fpga);
+ regmap_init_mem(dev_ofnode(dev), &map);
+
+ /* Enable receive path */
+ misc_set_enabled(dev, true);
+
+ rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+ while (1) {
+ uint top_int;
+
+ ihs_fpga_get(map, top_interrupt, &top_int);
+ io_check_status(dev, STATUS_SILENT);
+ if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
+ (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
+ io_reflect(dev);
+
+ if (rate) {
+ if (!(tx_ctr % rate) && (tx_ctr != last_seen))
+ printf("refl %llu, err %llu\n", tx_ctr,
+ err_ctr);
+ last_seen = tx_ctr;
+ }
+
+ if (ctrlc())
+ break;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#define DISP_LINE_LEN 16
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
/*
* FPGA io-endpoint looptest
*
* Syntax:
* ioloop {fpga} {size} {rate}
*/
-#define DISP_LINE_LEN 16
int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned int fpga;
- unsigned int size;
- unsigned int rate = 0;
+ uint fpga;
+ uint size;
+ uint rate = 0;
if (argc < 3)
return CMD_RET_USAGE;
FPGA_GET_REG(fpga, top_interrupt, &top_int);
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
- io_check_status(fpga, rx_tx_status, false);
+ io_check_status(fpga, rx_tx_status, STATUS_LOUD);
if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
io_send(fpga, size);
if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
break;
udelay(1000000 / rate);
if (!(tx_ctr % rate))
- printf("d %lld, tx %llu, rx %llu, err %llu\n",
+ printf("d %llu, tx %llu, rx %llu, err %llu\n",
+ tx_ctr - rx_ctr, tx_ctr, rx_ctr,
+ err_ctr);
+ }
+ }
+
+ return 0;
+}
+#else
+/*
+ * FPGA io-endpoint looptest
+ *
+ * Syntax:
+ * ioloop {size} {rate}
+ */
+int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uint size;
+ uint rate = 0;
+ struct udevice *fpga;
+ struct regmap *map;
+
+ if (!dev) {
+ printf("No device selected\n");
+ return 1;
+ }
+
+ gdsys_soc_get_fpga(dev, &fpga);
+ regmap_init_mem(dev_ofnode(dev), &map);
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /*
+ * packet size is specified since argc > 1
+ */
+ size = simple_strtoul(argv[2], NULL, 10);
+
+ /*
+ * If another parameter, it is the test rate in packets per second.
+ */
+ if (argc > 2)
+ rate = simple_strtoul(argv[3], NULL, 10);
+
+ /* Enable receive path */
+ misc_set_enabled(dev, true);
+
+ rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+ while (1) {
+ uint top_int;
+
+ if (ctrlc())
+ break;
+
+ ihs_fpga_get(map, top_interrupt, &top_int);
+
+ io_check_status(dev, STATUS_LOUD);
+ if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
+ io_send(dev, size);
+ if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
+ io_receive(dev);
+
+ if (rate) {
+ udelay(1000000 / rate);
+ if (!(tx_ctr % rate))
+ printf("d %llu, tx %llu, rx %llu, err %llu\n",
tx_ctr - rx_ctr, tx_ctr, rx_ctr,
err_ctr);
}
}
+ return 0;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+int do_iodev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *ioep = NULL;
+ struct udevice *board;
+ char name[8];
+ int ret;
+
+ if (board_get(&board))
+ return CMD_RET_FAILURE;
+
+ if (argc > 1) {
+ int i = simple_strtoul(argv[1], NULL, 10);
+
+ snprintf(name, sizeof(name), "ioep%d", i);
+
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
+
+ if (ret || !ioep) {
+ printf("Invalid IOEP %d\n", i);
+ return CMD_RET_FAILURE;
+ }
+
+ dev = ioep;
+ } else {
+ int i = 0;
+
+ while (1) {
+ snprintf(name, sizeof(name), "ioep%d", i);
+
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
+
+ if (ret || !ioep)
+ break;
+
+ printf("IOEP %d:\t%s\n", i++, ioep->name);
+ }
+
+ if (dev)
+ printf("\nSelected IOEP: %s\n", dev->name);
+ else
+ puts("\nNo IOEP selected.\n");
+ }
return 0;
}
+#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
U_BOOT_CMD(
ioloop, 4, 0, do_ioloop,
"fpga io-endpoint looptest",
"fpga io-endpoint reflector",
"fpga reportrate"
);
+#else
+U_BOOT_CMD(
+ ioloop, 3, 0, do_ioloop,
+ "fpga io-endpoint looptest",
+ "packetsize [packets/sec]"
+);
+
+U_BOOT_CMD(
+ ioreflect, 2, 0, do_ioreflect,
+ "fpga io-endpoint reflector",
+ "reportrate"
+);
+
+U_BOOT_CMD(
+ iodev, 2, 0, do_iodev,
+ "fpga io-endpoint listing/selection",
+ "[ioep device to select]"
+);
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <asm/io.h>
#include <errno.h>
return 0;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <i2c.h>
val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
i2c_reg_write(addr, FAN_CONFIG, val);
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <gdsys_fpga.h>
return 0;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
#include <gdsys_fpga.h>
#else
#include <fdtdec.h>
+#include <dm.h>
#include <regmap.h>
#endif
struct regmap *map;
u8 *ptr;
- regmap_init_mem(fpga, &map);
+ regmap_init_mem(dev_ofnode(fpga), &map);
ptr = regmap_get_range(map, 0);
return in_le16((u16 *)(ptr + base + addr));
struct regmap *map;
u8 *ptr;
- regmap_init_mem(fpga, &map);
+ regmap_init_mem(dev_ofnode(fpga), &map);
ptr = regmap_get_range(map, 0);
out_le16((u16 *)(ptr + base + addr), val);
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <gdsys_fpga.h>
-enum {
- UNITTYPE_MAIN_SERVER = 0,
- UNITTYPE_MAIN_USER = 1,
- UNITTYPE_VIDEO_SERVER = 2,
- UNITTYPE_VIDEO_USER = 3,
+enum pcb_video_type {
+ PCB_DVI_SL,
+ PCB_DP_165MPIX,
+ PCB_DP_300MPIX,
+ PCB_HDMI,
+ PCB_DP_1_2,
+ PCB_HDMI_2_0,
};
-enum {
- UNITTYPEPCB_DVI = 0,
- UNITTYPEPCB_DP_165 = 1,
- UNITTYPEPCB_DP_300 = 2,
- UNITTYPEPCB_HDMI = 3,
+enum pcb_transmission_type {
+ PCB_CAT_1G,
+ PCB_FIBER_3G,
+ PCB_CAT_10G,
+ PCB_FIBER_10G,
};
-enum {
- COMPRESSION_NONE = 0,
- COMPRESSION_TYPE_1 = 1,
- COMPRESSION_TYPE_1_2 = 3,
- COMPRESSION_TYPE_1_2_3 = 7,
+enum carrier_speed {
+ CARRIER_SPEED_1G,
+ CARRIER_SPEED_3G,
+ CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
+ CARRIER_SPEED_10G,
};
-enum {
- AUDIO_NONE = 0,
- AUDIO_TX = 1,
- AUDIO_RX = 2,
- AUDIO_RXTX = 3,
+enum ram_config {
+ RAM_DDR2_32BIT_295MBPS,
+ RAM_DDR3_32BIT_590MBPS,
+ RAM_DDR3_48BIT_590MBPS,
+ RAM_DDR3_64BIT_1800MBPS,
+ RAM_DDR3_48BIT_1800MBPS,
};
-enum {
- SYSCLK_147456 = 0,
+enum sysclock {
+ SYSCLK_147456,
};
-enum {
- RAM_DDR2_32 = 0,
- RAM_DDR3_32 = 1,
- RAM_DDR3_48 = 2,
+struct fpga_versions {
+ bool video_channel;
+ bool con_side;
+ enum pcb_video_type pcb_video_type;
+ enum pcb_transmission_type pcb_transmission_type;
+ unsigned int hw_version;
};
-enum {
- CARRIER_SPEED_1G = 0,
- CARRIER_SPEED_2_5G = 1,
+struct fpga_features {
+ u8 video_channels;
+ u8 carriers;
+ enum carrier_speed carrier_speed;
+ enum ram_config ram_config;
+ enum sysclock sysclock;
+
+ bool pcm_tx;
+ bool pcm_rx;
+ bool spdif_tx;
+ bool spdif_rx;
+ bool usb2;
+ bool rs232;
+ bool compression_type1;
+ bool compression_type2;
+ bool compression_type3;
+ bool interlace;
+ bool osd;
+ bool compression_pipes;
};
-bool ioep_fpga_has_osd(unsigned int fpga)
+#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
+
+static int get_versions(unsigned int fpga, struct fpga_versions *versions)
{
- u16 fpga_features;
- unsigned feature_osd;
+ enum {
+ VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
+ VERSIONS_FPGA_CON_SIDE = BIT(13),
+ VERSIONS_FPGA_SC = BIT(14),
+ VERSIONS_PCB_CON = BIT(9),
+ VERSIONS_PCB_SC = BIT(8),
+ VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
+ VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
+ VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
+ VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
+ VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
+ VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
+ VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
+ VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
+ VERSIONS_HW_VER_MASK = 0xf << 0,
+ };
+ u16 raw_versions;
+
+ memset(versions, 0, sizeof(struct fpga_versions));
+
+ FPGA_GET_REG(fpga, versions, &raw_versions);
+
+ versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
+ versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
+
+ switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
+ case VERSIONS_PCB_VIDEO_DP_1_2:
+ versions->pcb_video_type = PCB_DP_1_2;
+ break;
+
+ case VERSIONS_PCB_VIDEO_HDMI_2_0:
+ versions->pcb_video_type = PCB_HDMI_2_0;
+ break;
+ }
+
+ switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
+ case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
+ versions->pcb_transmission_type = PCB_FIBER_10G;
+ break;
+
+ case VERSIONS_PCB_TRANSMISSION_CAT_10G:
+ versions->pcb_transmission_type = PCB_CAT_10G;
+ break;
+
+ case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
+ versions->pcb_transmission_type = PCB_FIBER_3G;
+ break;
+
+ case VERSIONS_PCB_TRANSMISSION_CAT_1G:
+ versions->pcb_transmission_type = PCB_CAT_1G;
+ break;
- FPGA_GET_REG(0, fpga_features, &fpga_features);
- feature_osd = fpga_features & (1<<11);
+ }
- return feature_osd;
+ versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
+
+ return 0;
}
-void ioep_fpga_print_info(unsigned int fpga)
+static int get_features(unsigned int fpga, struct fpga_features *features)
{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- unsigned unit_type;
- unsigned unit_type_pcb_video;
- unsigned feature_compression;
- unsigned feature_osd;
- unsigned feature_audio;
- unsigned feature_sysclock;
- unsigned feature_ramconfig;
- unsigned feature_carrier_speed;
- unsigned feature_carriers;
- unsigned feature_video_channels;
-
- FPGA_GET_REG(fpga, versions, &versions);
- FPGA_GET_REG(fpga, fpga_version, &fpga_version);
- FPGA_GET_REG(fpga, fpga_features, &fpga_features);
-
- unit_type = (versions & 0xf000) >> 12;
- unit_type_pcb_video = (versions & 0x01c0) >> 6;
- feature_compression = (fpga_features & 0xe000) >> 13;
- feature_osd = fpga_features & (1<<11);
- feature_audio = (fpga_features & 0x0600) >> 9;
- feature_sysclock = (fpga_features & 0x0180) >> 7;
- feature_ramconfig = (fpga_features & 0x0060) >> 5;
- feature_carrier_speed = fpga_features & (1<<4);
- feature_carriers = (fpga_features & 0x000c) >> 2;
- feature_video_channels = fpga_features & 0x0003;
-
- switch (unit_type) {
- case UNITTYPE_MAIN_SERVER:
- case UNITTYPE_MAIN_USER:
- printf("Mainchannel");
+ enum {
+ FEATURE_SPDIF_RX = BIT(15),
+ FEATURE_SPDIF_TX = BIT(14),
+ FEATURE_PCM_RX = BIT(13),
+ FEATURE_PCM_TX = BIT(12),
+ FEATURE_RAM_MASK = GENMASK(11, 8),
+ FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
+ FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
+ FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
+ FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
+ FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
+ FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
+ FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
+ FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
+ FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
+ FEATURE_CARRIERS_MASK = GENMASK(5, 4),
+ FEATURE_CARRIERS_0 = 0x0 << 4,
+ FEATURE_CARRIERS_1 = 0x1 << 4,
+ FEATURE_CARRIERS_2 = 0x2 << 4,
+ FEATURE_CARRIERS_4 = 0x3 << 4,
+ FEATURE_USB2 = BIT(3),
+ FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
+ FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
+ FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
+ FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
+ FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
+ };
+
+ enum {
+ EXT_FEATURE_OSD = BIT(15),
+ EXT_FEATURE_ETHERNET = BIT(9),
+ EXT_FEATURE_INTERLACE = BIT(8),
+ EXT_FEATURE_RS232 = BIT(7),
+ EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
+ EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
+ EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
+ EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
+ EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
+ EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
+ EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
+ };
+
+ u16 raw_features;
+ u16 raw_extended_features;
+
+ memset(features, 0, sizeof(struct fpga_features));
+
+ FPGA_GET_REG(fpga, fpga_features, &raw_features);
+ FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
+
+ switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
+ case FEATURE_VIDEOCHANNELS_0:
+ features->video_channels = 0;
break;
- case UNITTYPE_VIDEO_SERVER:
- case UNITTYPE_VIDEO_USER:
- printf("Videochannel");
+ case FEATURE_VIDEOCHANNELS_1:
+ features->video_channels = 1;
break;
- default:
- printf("UnitType %d(not supported)", unit_type);
+ case FEATURE_VIDEOCHANNELS_1_1:
+ case FEATURE_VIDEOCHANNELS_2:
+ features->video_channels = 2;
break;
- }
+ };
- switch (unit_type) {
- case UNITTYPE_MAIN_SERVER:
- case UNITTYPE_VIDEO_SERVER:
- printf(" Server");
- if (versions & (1<<4))
- printf(" UC");
+ switch (raw_features & FEATURE_CARRIERS_MASK) {
+ case FEATURE_CARRIERS_0:
+ features->carriers = 0;
break;
- case UNITTYPE_MAIN_USER:
- case UNITTYPE_VIDEO_USER:
- printf(" User");
+ case FEATURE_CARRIERS_1:
+ features->carriers = 1;
break;
- default:
+ case FEATURE_CARRIERS_2:
+ features->carriers = 2;
+ break;
+
+ case FEATURE_CARRIERS_4:
+ features->carriers = 4;
break;
}
- if (versions & (1<<5))
- printf(" Fiber");
- else
- printf(" CAT");
+ switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
+ case FEATURE_CARRIER_SPEED_1G:
+ features->carrier_speed = CARRIER_SPEED_1G;
+ break;
+ case FEATURE_CARRIER_SPEED_2_5G:
+ features->carrier_speed = CARRIER_SPEED_2_5G;
+ break;
+ case FEATURE_CARRIER_SPEED_10G:
+ features->carrier_speed = CARRIER_SPEED_10G;
+ break;
+ }
- switch (unit_type_pcb_video) {
- case UNITTYPEPCB_DVI:
- printf(" DVI,");
+ switch (raw_features & FEATURE_RAM_MASK) {
+ case FEATURE_RAM_DDR2_32BIT_295MBPS:
+ features->ram_config = RAM_DDR2_32BIT_295MBPS;
break;
- case UNITTYPEPCB_DP_165:
- printf(" DP 165MPix/s,");
+ case FEATURE_RAM_DDR3_32BIT_590MBPS:
+ features->ram_config = RAM_DDR3_32BIT_590MBPS;
break;
- case UNITTYPEPCB_DP_300:
- printf(" DP 300MPix/s,");
+ case FEATURE_RAM_DDR3_48BIT_590MBPS:
+ features->ram_config = RAM_DDR3_48BIT_590MBPS;
break;
- case UNITTYPEPCB_HDMI:
- printf(" HDMI,");
+ case FEATURE_RAM_DDR3_64BIT_1800MBPS:
+ features->ram_config = RAM_DDR3_64BIT_1800MBPS;
+ break;
+
+ case FEATURE_RAM_DDR3_48BIT_1800MBPS:
+ features->ram_config = RAM_DDR3_48BIT_1800MBPS;
break;
}
- printf(" FPGA V %d.%02d\n features:",
- fpga_version / 100, fpga_version % 100);
+ features->pcm_tx = raw_features & FEATURE_PCM_TX;
+ features->pcm_rx = raw_features & FEATURE_PCM_RX;
+ features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
+ features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
+ features->usb2 = raw_features & FEATURE_USB2;
+ features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
+ features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1;
+ features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2;
+ features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3;
+ features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
+ features->osd = raw_extended_features & EXT_FEATURE_OSD;
+ features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK;
+
+ return 0;
+}
+
+#else
+
+static int get_versions(unsigned int fpga, struct fpga_versions *versions)
+{
+ enum {
+ /* HW version encoding is a mess, leave it for the moment */
+ VERSIONS_HW_VER_MASK = 0xf << 0,
+ VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
+ VERSIONS_SFP = BIT(5),
+ VERSIONS_VIDEO_MASK = 0x7 << 6,
+ VERSIONS_VIDEO_DVI = 0x0 << 6,
+ VERSIONS_VIDEO_DP_165 = 0x1 << 6,
+ VERSIONS_VIDEO_DP_300 = 0x2 << 6,
+ VERSIONS_VIDEO_HDMI = 0x3 << 6,
+ VERSIONS_UT_MASK = 0xf << 12,
+ VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
+ VERSIONS_UT_MAIN_USER = 0x1 << 12,
+ VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
+ VERSIONS_UT_VIDEO_USER = 0x3 << 12,
+ };
+ u16 raw_versions;
+
+ memset(versions, 0, sizeof(struct fpga_versions));
+
+ FPGA_GET_REG(fpga, versions, &raw_versions);
+
+ switch (raw_versions & VERSIONS_UT_MASK) {
+ case VERSIONS_UT_MAIN_SERVER:
+ versions->video_channel = false;
+ versions->con_side = false;
+ break;
+
+ case VERSIONS_UT_MAIN_USER:
+ versions->video_channel = false;
+ versions->con_side = true;
+ break;
+ case VERSIONS_UT_VIDEO_SERVER:
+ versions->video_channel = true;
+ versions->con_side = false;
+ break;
- switch (feature_compression) {
- case COMPRESSION_NONE:
- printf(" no compression");
+ case VERSIONS_UT_VIDEO_USER:
+ versions->video_channel = true;
+ versions->con_side = true;
break;
- case COMPRESSION_TYPE_1:
- printf(" compression type1(delta)");
+ }
+
+ switch (raw_versions & VERSIONS_VIDEO_MASK) {
+ case VERSIONS_VIDEO_DVI:
+ versions->pcb_video_type = PCB_DVI_SL;
break;
- case COMPRESSION_TYPE_1_2:
- printf(" compression type1(delta), type2(inline)");
+ case VERSIONS_VIDEO_DP_165:
+ versions->pcb_video_type = PCB_DP_165MPIX;
break;
- case COMPRESSION_TYPE_1_2_3:
- printf(" compression type1(delta), type2(inline), type3(intempo)");
+ case VERSIONS_VIDEO_DP_300:
+ versions->pcb_video_type = PCB_DP_300MPIX;
break;
- default:
- printf(" compression %d(not supported)", feature_compression);
+ case VERSIONS_VIDEO_HDMI:
+ versions->pcb_video_type = PCB_HDMI;
break;
}
- printf(", %sosd", feature_osd ? "" : "no ");
+ versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
- switch (feature_audio) {
- case AUDIO_NONE:
- printf(", no audio");
+ if (raw_versions & VERSIONS_SFP)
+ versions->pcb_transmission_type = PCB_FIBER_3G;
+ else
+ versions->pcb_transmission_type = PCB_CAT_1G;
+
+ return 0;
+}
+
+static int get_features(unsigned int fpga, struct fpga_features *features)
+{
+ enum {
+ FEATURE_CARRIER_SPEED_2_5 = BIT(4),
+ FEATURE_RAM_MASK = 0x7 << 5,
+ FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
+ FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
+ FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
+ FEATURE_PCM_AUDIO_TX = BIT(9),
+ FEATURE_PCM_AUDIO_RX = BIT(10),
+ FEATURE_OSD = BIT(11),
+ FEATURE_USB20 = BIT(12),
+ FEATURE_COMPRESSION_MASK = 7 << 13,
+ FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
+ FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
+ FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
+ };
+
+ enum {
+ EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
+ EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
+ EXTENDED_FEATURE_RS232 = BIT(2),
+ EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
+ EXTENDED_FEATURE_INTERLACE = BIT(4),
+ };
+
+ u16 raw_features;
+#ifdef GDSYS_LEGACY_DRIVERS
+ u16 raw_extended_features;
+#endif
+
+ memset(features, 0, sizeof(struct fpga_features));
+
+ FPGA_GET_REG(fpga, fpga_features, &raw_features);
+#ifdef GDSYS_LEGACY_DRIVERS
+ FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
+#endif
+
+ features->video_channels = raw_features & 0x3;
+ features->carriers = (raw_features >> 2) & 0x3;
+
+ features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
+ ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
+
+ switch (raw_features & FEATURE_RAM_MASK) {
+ case FEATURE_RAM_DDR2_32BIT:
+ features->ram_config = RAM_DDR2_32BIT_295MBPS;
break;
- case AUDIO_TX:
- printf(", audio tx");
+ case FEATURE_RAM_DDR3_32BIT:
+ features->ram_config = RAM_DDR3_32BIT_590MBPS;
break;
- case AUDIO_RX:
- printf(", audio rx");
+ case FEATURE_RAM_DDR3_48BIT:
+ features->ram_config = RAM_DDR3_48BIT_590MBPS;
break;
+ }
- case AUDIO_RXTX:
- printf(", audio rx+tx");
+ features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
+ features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
+#ifdef GDSYS_LEGACY_DRIVERS
+ features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX;
+ features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX;
+#endif
+
+ features->usb2 = raw_features & FEATURE_USB20;
+#ifdef GDSYS_LEGACY_DRIVERS
+ features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
+#endif
+
+ features->compression_type1 = false;
+ features->compression_type2 = false;
+ features->compression_type3 = false;
+ switch (raw_features & FEATURE_COMPRESSION_MASK) {
+ case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
+ features->compression_type3 = true;
+ case FEATURE_COMPRESSION_TYPE1_TYPE2:
+ features->compression_type2 = true;
+ case FEATURE_COMPRESSION_TYPE1:
+ features->compression_type1 = true;
break;
+ }
+
+#ifdef GDSYS_LEGACY_DRIVERS
+ features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE;
+#endif
+ features->osd = raw_features & FEATURE_OSD;
+#ifdef GDSYS_LEGACY_DRIVERS
+ features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES;
+#endif
- default:
- printf(", audio %d(not supported)", feature_audio);
+ return 0;
+}
+
+#endif
+
+bool ioep_fpga_has_osd(unsigned int fpga)
+{
+ struct fpga_features features;
+
+ get_features(fpga, &features);
+
+ return features.osd;
+}
+
+void ioep_fpga_print_info(unsigned int fpga)
+{
+ u16 fpga_version;
+ struct fpga_versions versions;
+ struct fpga_features features;
+
+ FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+ get_versions(fpga, &versions);
+ get_features(fpga, &features);
+
+ if (versions.video_channel)
+ printf("Videochannel");
+ else
+ printf("Mainchannel");
+
+ if (versions.con_side)
+ printf(" User");
+ else
+ printf(" Server");
+
+// FIXME
+#if 0
+ if (versions & (1<<4))
+ printf(" UC");
+#endif
+
+ switch(versions.pcb_transmission_type) {
+ case PCB_CAT_1G:
+ case PCB_CAT_10G:
+ printf(" CAT");
+ break;
+ case PCB_FIBER_3G:
+ case PCB_FIBER_10G:
+ printf(" Fiber");
+ break;
+ };
+
+ switch (versions.pcb_video_type) {
+ case PCB_DVI_SL:
+ printf(" DVI,");
+ break;
+ case PCB_DP_165MPIX:
+ printf(" DP 165MPix/s,");
+ break;
+ case PCB_DP_300MPIX:
+ printf(" DP 300MPix/s,");
+ break;
+ case PCB_HDMI:
+ printf(" HDMI,");
+ break;
+ case PCB_DP_1_2:
+ printf(" DP 1.2,");
+ break;
+ case PCB_HDMI_2_0:
+ printf(" HDMI 2.0,");
break;
}
+ printf(" FPGA V %d.%02d\n features: ",
+ fpga_version / 100, fpga_version % 100);
+
+ if (!features.compression_type1 &&
+ !features.compression_type2 &&
+ !features.compression_type3)
+ printf("no compression, ");
+
+ if (features.compression_type1)
+ printf("type1, ");
+
+ if (features.compression_type2)
+ printf("type2, ");
+
+ if (features.compression_type3)
+ printf("type3, ");
+
+ printf("%sosd", features.osd ? "" : "no ");
+
+ if (features.pcm_rx && features.pcm_tx)
+ printf(", pcm rx+tx");
+ else if(features.pcm_rx)
+ printf(", pcm rx");
+ else if(features.pcm_tx)
+ printf(", pcm tx");
+
+ if (features.spdif_rx && features.spdif_tx)
+ printf(", spdif rx+tx");
+ else if(features.spdif_rx)
+ printf(", spdif rx");
+ else if(features.spdif_tx)
+ printf(", spdif tx");
+
puts(",\n ");
- switch (feature_sysclock) {
+ switch (features.sysclock) {
case SYSCLK_147456:
printf("clock 147.456 MHz");
break;
-
- default:
- printf("clock %d(not supported)", feature_sysclock);
- break;
}
- switch (feature_ramconfig) {
- case RAM_DDR2_32:
+ switch (features.ram_config) {
+ case RAM_DDR2_32BIT_295MBPS:
printf(", RAM 32 bit DDR2");
break;
-
- case RAM_DDR3_32:
+ case RAM_DDR3_32BIT_590MBPS:
printf(", RAM 32 bit DDR3");
break;
-
- case RAM_DDR3_48:
+ case RAM_DDR3_48BIT_590MBPS:
+ case RAM_DDR3_48BIT_1800MBPS:
printf(", RAM 48 bit DDR3");
break;
-
- default:
- printf(", RAM %d(not supported)", feature_ramconfig);
+ case RAM_DDR3_64BIT_1800MBPS:
+ printf(", RAM 64 bit DDR3");
break;
}
- printf(", %d carrier(s) %s", feature_carriers,
- feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
+ printf(", %d carrier(s)", features.carriers);
- printf(", %d video channel(s)\n", feature_video_channels);
+ switch(features.carrier_speed) {
+ case CARRIER_SPEED_1G:
+ printf(", 1Gbit/s");
+ break;
+ case CARRIER_SPEED_3G:
+ printf(", 3Gbit/s");
+ break;
+ case CARRIER_SPEED_10G:
+ printf(", 10Gbit/s");
+ break;
+ }
+
+ printf(", %d video channel(s)\n", features.video_channels);
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <asm/io.h>
#include <errno.h>
return 0;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#include <common.h>
-#include <miiphy.h>
-
-#include <asm/io.h>
-
-struct io_bb_pinset {
- int mdio;
- int mdc;
-};
-
-static int io_bb_mii_init(struct bb_miiphy_bus *bus)
-{
- return 0;
-}
-
-static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) | pins->mdio);
-
- return 0;
-}
-
-static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) & ~pins->mdio);
-
- return 0;
-}
-
-static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- if (v)
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | pins->mdio);
- else
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~pins->mdio);
-
- return 0;
-}
-
-static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
-
- return 0;
-}
-
-static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- if (v)
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | pins->mdc);
- else
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~pins->mdc);
-
- return 0;
-}
-
-static int io_bb_delay(struct bb_miiphy_bus *bus)
-{
- udelay(1);
-
- return 0;
-}
-
-struct io_bb_pinset io_bb_pinsets[] = {
- {
- .mdio = CONFIG_SYS_MDIO_PIN,
- .mdc = CONFIG_SYS_MDC_PIN,
- },
-#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
- {
- .mdio = CONFIG_SYS_MDIO1_PIN,
- .mdc = CONFIG_SYS_MDC1_PIN,
- },
-#endif
-};
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- {
- .name = CONFIG_SYS_GBIT_MII_BUSNAME,
- .init = io_bb_mii_init,
- .mdio_active = io_bb_mdio_active,
- .mdio_tristate = io_bb_mdio_tristate,
- .set_mdio = io_bb_set_mdio,
- .get_mdio = io_bb_get_mdio,
- .set_mdc = io_bb_set_mdc,
- .delay = io_bb_delay,
- .priv = &io_bb_pinsets[0],
- },
-#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
- {
- .name = CONFIG_SYS_GBIT_MII1_BUSNAME,
- .init = io_bb_mii_init,
- .mdio_active = io_bb_mdio_active,
- .mdio_tristate = io_bb_mdio_tristate,
- .set_mdio = io_bb_set_mdio,
- .get_mdio = io_bb_get_mdio,
- .set_mdc = io_bb_set_mdc,
- .delay = io_bb_delay,
- .priv = &io_bb_pinsets[1],
- },
-#endif
-};
-
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <i2c.h>
#include <malloc.h>
"size_x(max. " __stringify(MAX_X_CHARS)
") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
);
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
\ No newline at end of file
{ MIICMD_SET, 16, 0x214d },
{ MIICMD_SET, 17, 0xcc0c },
{ MIICMD_SET, 16, 0x2159 },
- { MIICMD_SET, 22, 0x00fb },
- { MIICMD_SET, 7, 0xc00d },
{ MIICMD_SET, 22, 0x0000 },
};
Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
gdsys devices.
+config GDSYS_LEGACY_DRIVERS
+ bool
+ help
+ Enable the gdsys legacy drivers under board/gdsys/common. If this
+ option is not set, all relevant DM drivers must be configured for the
+ device in question.
+
+config SYS_FPGA0_BASE
+ hex
+ default E0600000
+ help
+ The base address of the first FPGA's register map.
+
+config SYS_FPGA0_SIZE
+ hex
+ default 1
+ help
+ The base address of the first FPGA's register map.
+
+config SYS_FPGA1_BASE
+ hex
+ help
+ The base address of the second FPGA's register map.
+
+config SYS_FPGA1_SIZE
+ hex
+ help
+ The base address of the second FPGA's register map.
+
if TARGET_HRCON
config SYS_BOARD
config GDSYS_LEGACY_OSD_CMDS
default y
+config GDSYS_LEGACY_DRIVERS
+ default y
+
endif
if TARGET_STRIDER
config SYS_CONFIG_NAME
default "strider"
+config GDSYS_LEGACY_OSD_CMDS
+ default y
+
+config GDSYS_LEGACY_DRIVERS
+ default y
+
+endif
+
+if TARGET_GAZERBEAM
+
+config SYS_BOARD
+ default "mpc8308"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "gazerbeam"
+
+config SYS_FPGA1_BASE
+ default E0700000
+
+config SYS_FPGA1_SIZE
+ default 1
+
config GDSYS_LEGACY_OSD_CMDS
default y
endif
+if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM
+
+choice
+ prompt "FPGA flavor selection"
+
+config SYS_FPGA_FLAVOR_LEGACY
+ bool "Legacy flavor"
+ help
+ This enables support for the gdsys pre-Gazerbeam FPGA memory layout.
+
+config SYS_FPGA_FLAVOR_GAZERBEAM
+ bool "Gazerbeam flavor"
+ help
+ This enables support for the gdsys FPGA memory layout of the
+ Gazerbeam board.
+
+endchoice
+
+config EXTENDED_FEATURES
+ bool "FPGA extended features"
+ depends on GDSYS_LEGACY_DRIVERS
+ help
+ Enable support for the extended features field of the IHS FPGA.
+
config CMD_IOLOOP
bool "Enable 'ioloop' and 'ioreflect' commands"
help
These commands provide FPGA tests.
+
+endif
F: configs/hrcon_defconfig
F: configs/hrcon_dh_defconfig
F: include/configs/strider.h
+F: configs/strider_defconfig
F: configs/strider_cpu_defconfig
F: configs/strider_cpu_dp_defconfig
F: configs/strider_con_defconfig
F: configs/strider_con_dp_defconfig
+F: configs/gazerbeam_defconfig
# Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
obj-y := mpc8308.o sdram.o
-obj-$(CONFIG_HRCON) += hrcon.o
-obj-$(CONFIG_STRIDER) += strider.o
+obj-$(CONFIG_TARGET_HRCON) += hrcon.o
+obj-$(CONFIG_TARGET_STRIDER) += strider.o
+obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o
--- /dev/null
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <board.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <misc.h>
+#include <tpm-v1.h>
+#include <video_osd.h>
+
+#include "../common/ihs_mdio.h"
+#include "../../../drivers/board/gazerbeam.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ihs_mdio_info ihs_mdio_info[] = {
+ { .fpga = NULL, .name = "ihs0", .base = 0x58 },
+ { .fpga = NULL, .name = "ihs1", .base = 0x58 },
+};
+
+static int get_tpm(struct udevice **devp)
+{
+ int rc;
+
+ rc = uclass_first_device_err(UCLASS_TPM, devp);
+ if (rc) {
+ printf("Could not find TPM (ret=%d)\n", rc);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ struct udevice *board;
+ struct udevice *serdes;
+ int mc = 0;
+ int con = 0;
+
+ if (board_get(&board))
+ puts("Could not find board information device.\n");
+
+ /* Initialize serdes */
+ uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes);
+
+ if (board_detect(board))
+ puts("Device information detection failed.\n");
+
+ board_get_int(board, BOARD_MULTICHANNEL, &mc);
+ board_get_int(board, BOARD_VARIANT, &con);
+
+ if (mc == 2 || mc == 1)
+ dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22");
+
+ if (mc == 4) {
+ dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20");
+ dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0");
+ dev_enable_by_path("/fpga1bus");
+ }
+
+ if (mc == 2 || con == VAR_CON) {
+ dev_enable_by_path("/fpga0bus/fpga0_video1");
+ dev_enable_by_path("/fpga0bus/fpga0_iic_video1");
+ dev_enable_by_path("/fpga0bus/fpga0_axi_video1");
+ }
+
+ if (con == VAR_CON) {
+ dev_enable_by_path("/fpga0bus/fpga0_video0");
+ dev_enable_by_path("/fpga0bus/fpga0_iic_video0");
+ dev_enable_by_path("/fpga0bus/fpga0_axi_video0");
+ }
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ struct udevice *board;
+ char *s = env_get("serial#");
+ int mc = 0;
+ int con = 0;
+
+ if (board_get(&board))
+ puts("Could not find board information device.\n");
+
+ board_get_int(board, BOARD_MULTICHANNEL, &mc);
+ board_get_int(board, BOARD_VARIANT, &con);
+
+ puts("Board: Gazerbeam ");
+ printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC");
+ printf("%s", con == VAR_CON ? "CON" : "CPU");
+
+ if (s) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void display_osd_info(struct udevice *osd,
+ struct video_osd_info *osd_info)
+{
+ printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n",
+ osd->name, osd_info->major_version, osd_info->minor_version,
+ osd_info->width, osd_info->height);
+}
+
+int last_stage_init(void)
+{
+ int fpga_hw_rev = 0;
+ int i;
+ struct udevice *board;
+ struct udevice *osd;
+ struct video_osd_info osd_info;
+ struct udevice *tpm;
+ int ret;
+
+ if (board_get(&board))
+ puts("Could not find board information device.\n");
+
+ if (board) {
+ int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev);
+
+ if (res)
+ printf("Could not determind FPGA HW revision (res = %d)\n", res);
+ }
+
+ env_set_ulong("fpga_hw_rev", fpga_hw_rev);
+
+ ret = get_tpm(&tpm);
+ if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) ||
+ tpm_continue_self_test(tpm)) {
+ printf("TPM init failed\n");
+ }
+
+ if (fpga_hw_rev >= 4) {
+ for (i = 0; i < 4; i++) {
+ struct udevice *rxaui;
+ char name[8];
+
+ snprintf(name, sizeof(name), "rxaui%d", i);
+ /* Disable RXAUI polarity inversion */
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui);
+ if (!ret)
+ misc_set_enabled(rxaui, false);
+ }
+ }
+
+ for (uclass_first_device(UCLASS_VIDEO_OSD, &osd);
+ osd;
+ uclass_next_device(&osd)) {
+ video_osd_get_info(osd, &osd_info);
+ display_osd_info(osd, &osd_info);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
+
+ return 0;
+}
+#endif
#define MAX_MUX_CHANNELS 2
enum {
- MCFPGA_DONE = 1 << 0,
- MCFPGA_INIT_N = 1 << 1,
- MCFPGA_PROGRAM_N = 1 << 2,
- MCFPGA_UPDATE_ENABLE_N = 1 << 3,
- MCFPGA_RESET_N = 1 << 4,
+ MCFPGA_DONE = BIT(0),
+ MCFPGA_INIT_N = BIT(1),
+ MCFPGA_PROGRAM_N = BIT(2),
+ MCFPGA_UPDATE_ENABLE_N = BIT(3),
+ MCFPGA_RESET_N = BIT(4),
};
enum {
GPIO_MDIO = 1 << 15,
};
-unsigned int mclink_fpgacount;
+uint mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
struct {
printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
- if (s != NULL) {
+ if (s) {
puts(", serial# ");
puts(s);
}
int last_stage_init(void)
{
int slaves;
- unsigned int k;
- unsigned int mux_ch;
- unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
+ uint k;
+ uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
u16 fpga_features;
bool hw_type_cat = pca9698_get_value(0x20, 20);
- bool ch0_rgmii2_present = false;
+ bool ch0_rgmii2_present;
FPGA_GET_REG(0, fpga_features, &fpga_features);
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
- unsigned int ctr = 0;
+ uint ctr = 0;
if (i2c_probe(mclink_controllers[k]))
continue;
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
- udelay(100000);
+ mdelay(100);
if (ctr++ > 5) {
- printf("no done for mclink_controller %d\n", k);
+ printf("no done for mclink_controller %u\n", k);
break;
}
}
}
if (hw_type_cat) {
+ uint mux_ch;
int retval;
struct mii_dev *mdiodev = mdio_alloc();
+
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
- udelay(500000);
+ mdelay(500);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
+
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
* provide access to fpga gpios and controls (for I2C bitbang)
* (these may look all too simple but make iocon.h much more readable)
*/
-void fpga_gpio_set(unsigned int bus, int pin)
+void fpga_gpio_set(uint bus, int pin)
{
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
}
-void fpga_gpio_clear(unsigned int bus, int pin)
+void fpga_gpio_clear(uint bus, int pin)
{
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
}
-int fpga_gpio_get(unsigned int bus, int pin)
+int fpga_gpio_get(uint bus, int pin)
{
u16 val;
return val & pin;
}
-void fpga_control_set(unsigned int bus, int pin)
+void fpga_control_set(uint bus, int pin)
{
u16 val;
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
}
-void fpga_control_clear(unsigned int bus, int pin)
+void fpga_control_clear(uint bus, int pin)
{
u16 val;
pca9698_direction_output(0x20, 4, 1);
}
-void mpc8308_set_fpga_reset(unsigned state)
+void mpc8308_set_fpga_reset(uint state)
{
pca9698_set_value(0x20, 4, state ? 0 : 1);
}
/*
* set "startup-finished"-gpios
*/
- setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
- setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+ setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
+ setbits_gpio0_out(BIT(31 - 12));
}
-int mpc8308_get_fpga_done(unsigned fpga)
+int mpc8308_get_fpga_done(uint fpga)
{
return pca9698_get_value(0x20, 19);
}
*/
struct fpga_mii {
- unsigned fpga;
+ uint fpga;
int mdio;
} fpga_mii[] = {
{ 0, 1},
},
};
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
DECLARE_GLOBAL_DATA_PTR;
-int get_fpga_state(unsigned dev)
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+/* as gpio output status cannot be read back, we have to buffer it locally */
+u32 gpio0_out;
+
+void setbits_gpio0_out(u32 mask)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ gpio0_out |= mask;
+ out_be32(&immr->gpio[0].dat, gpio0_out);
+}
+
+void clrbits_gpio0_out(u32 mask)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ gpio0_out &= ~mask;
+ out_be32(&immr->gpio[0].dat, gpio0_out);
+}
+
+int get_fpga_state(uint dev)
{
return gd->arch.fpga_state[dev];
}
int board_early_init_f(void)
{
- unsigned k;
+ uint k;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->arch.fpga_state[k] = 0;
int board_early_init_r(void)
{
- unsigned k;
- unsigned ctr;
+ uint k;
+ uint ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->arch.fpga_state[k] = 0;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
ctr = 0;
while (!mpc8308_get_fpga_done(k)) {
- udelay(100000);
+ mdelay(100);
if (ctr++ > 5) {
gd->arch.fpga_state[k] |=
FPGA_STATE_DONE_FAILED;
if (val == REFLECTION_TESTPATTERN_INV)
break;
- udelay(100000);
+ mdelay(100);
if (ctr++ > 5) {
gd->arch.fpga_state[k] |=
FPGA_STATE_REFLECTION_FAILED;
return 0;
}
+#endif
#ifndef __MPC8308_H_
#define __MPC8308_H_
+void setbits_gpio0_out(u32 mask);
+void clrbits_gpio0_out(u32 mask);
+
/* functions to be provided by board implementation */
void mpc8308_init(void);
void mpc8308_set_fpga_reset(unsigned state);
* board\freescale\mpc8315erdb\sdram.c
*/
+#ifndef CONFIG_MPC83XX_SDRAM
+
#include <common.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ CONFIG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)
return 0;
}
+
+#endif /* !CONFIG_MPC83XX_SDRAM */
GPIO_MDIO = 1 << 15,
};
-unsigned int mclink_fpgacount;
+uint mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
struct {
printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
- if (s != NULL) {
+ if (s) {
puts(", serial# ");
puts(s);
}
int last_stage_init(void)
{
int slaves;
- unsigned int k;
- unsigned int mux_ch;
- unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
+ uint k;
+ uint mux_ch;
+ uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
#ifdef CONFIG_STRIDER_CPU
- unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
+ uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
#endif
bool hw_type_cat = pca9698_get_value(0x20, 18);
#ifdef CONFIG_STRIDER_CON_DP
bool is_dh = pca9698_get_value(0x20, 25);
#endif
- bool ch0_sgmii2_present = false;
+ bool ch0_sgmii2_present;
/* Turn on Analog Devices ADV7611 */
pca9698_direction_output(0x20, 8, 0);
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
- unsigned int ctr = 0;
- unsigned char *mclink_controllers = mclink_controllers_dvi;
+ uint ctr = 0;
+ uchar *mclink_controllers = mclink_controllers_dvi;
#ifdef CONFIG_STRIDER_CPU
if (i2c_probe(mclink_controllers[k])) {
#endif
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
- udelay(100000);
+ mdelay(100);
if (ctr++ > 5) {
printf("no done for mclink_controller %d\n", k);
break;
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
+
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
- udelay(500000);
+ mdelay(500);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
for (k = 1; k <= slaves; ++k)
FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
- udelay(500000);
+ mdelay(500);
#endif
for (k = 1; k <= slaves; ++k) {
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
+
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
* provide access to fpga gpios (for I2C bitbang)
* (these may look all too simple but make iocon.h much more readable)
*/
-void fpga_gpio_set(unsigned int bus, int pin)
+void fpga_gpio_set(uint bus, int pin)
{
FPGA_SET_REG(bus, gpio.set, pin);
}
-void fpga_gpio_clear(unsigned int bus, int pin)
+void fpga_gpio_clear(uint bus, int pin)
{
FPGA_SET_REG(bus, gpio.clear, pin);
}
-int fpga_gpio_get(unsigned int bus, int pin)
+int fpga_gpio_get(uint bus, int pin)
{
u16 val;
}
#ifdef CONFIG_STRIDER_CON_DP
-void fpga_control_set(unsigned int bus, int pin)
+void fpga_control_set(uint bus, int pin)
{
u16 val;
FPGA_SET_REG(bus, control, val | pin);
}
-void fpga_control_clear(unsigned int bus, int pin)
+void fpga_control_clear(uint bus, int pin)
{
u16 val;
pca9698_direction_output(0x20, 26, 1);
}
-void mpc8308_set_fpga_reset(unsigned state)
+void mpc8308_set_fpga_reset(uint state)
{
pca9698_set_value(0x20, 26, state ? 0 : 1);
}
/*
* set "startup-finished"-gpios
*/
- setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
- setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+ setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
+ setbits_gpio0_out(BIT(31 - 12));
}
-int mpc8308_get_fpga_done(unsigned fpga)
+int mpc8308_get_fpga_done(uint fpga)
{
return pca9698_get_value(0x20, 20);
}
*/
struct fpga_mii {
- unsigned fpga;
+ uint fpga;
int mdio;
} fpga_mii[] = {
{ 0, 1},
},
};
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
+config GDSYS_LEGACY_DRIVERS
+ bool
+ help
+ Enable the gdsys legacy drivers under board/gdsys/common. If this
+ option is not set, all relevant DM drivers must be configured for the
+ device in question.
+
if TARGET_CONTROLCENTERD
config SYS_BOARD
config SYS_CONFIG_NAME
default "controlcenterd"
+config GDSYS_LEGACY_DRIVERS
+ default y
+
endif
Chrome OS EC connected on LPC, and it provides a 2560x1700 high
resolution touch-enabled LCD display.
+config TARGET_CHROMEBOOK_SAMUS_TPL
+ bool "Chromebook samus booting from TPL"
+ help
+ This is a version of Samus which boots into TPL, then to SPL and
+ U-Boot proper. This is useful where verified boot must select
+ between different A/B versions of SPL/U-Boot, to allow upgrading of
+ almost all U-Boot code in the field.
+
endchoice
source "board/google/chromebook_link/Kconfig"
-if TARGET_CHROMEBOOK_SAMUS
+if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL
config SYS_BOARD
default "chromebook_samus"
default "broadwell"
config SYS_CONFIG_NAME
- default "chromebook_samus"
+ default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS
+ default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL
config SYS_TEXT_BASE
default 0xffe00000
default 0x40000
endif
+
+if TARGET_CHROMEBOOK_SAMUS_TPL
+
+config BOARD_SPECIFIC_OPTIONS_TPL # dummy
+ def_bool y
+ select SPL
+ select TPL
+
+endif
F: board/google/chromebook_samus/
F: include/configs/chromebook_samus.h
F: configs/chromebook_samus_defconfig
+
+CHROMEBOOK SAMUS TPL BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_samus/
+F: include/configs/chromebook_samus.h
+F: configs/chromebook_samus_tpl_defconfig
+++ /dev/null
-if TARGET_MCX
-
-config SYS_BOARD
- default "mcx"
-
-config SYS_VENDOR
- default "htkw"
-
-config SYS_CONFIG_NAME
- default "mcx"
-
-endif
+++ /dev/null
-MCX BOARD
-M: Anatolij Gustschin <agust@denx.de>
-S: Maintained
-F: board/htkw/mcx/
-F: include/configs/mcx.h
-F: configs/mcx_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
-#
-# Based on ti/evm/Makefile
-
-obj-y := mcx.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- *
- * Based on ti/evm/evm.c
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include <asm/gpio.h>
-#include <asm/omap_gpio.h>
-#include <asm/arch/dss.h>
-#include <asm/arch/clock.h>
-#include <errno.h>
-#include <i2c.h>
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-#include "mcx.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define HOT_WATER_BUTTON 42
-#define LCD_OUTPUT 55
-
-/* Address of the framebuffer in RAM. */
-#define FB_START_ADDRESS 0x88000000
-
-#ifdef CONFIG_USB_EHCI_HCD
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-#endif
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- gpio_direction_output(LCD_OUTPUT, 0);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- if (gpio_request(HOT_WATER_BUTTON, "hot-water-button") < 0) {
- puts("Failed to get hot-water-button pin\n");
- return -ENODEV;
- }
- gpio_direction_input(HOT_WATER_BUTTON);
-
- /*
- * if hot-water-button is pressed
- * change bootcmd
- */
- if (gpio_get_value(HOT_WATER_BUTTON))
- return 0;
-
- env_set("bootcmd", "run swupdate");
-
- return 0;
-}
-#endif
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_MCX();
-}
-
-#if defined(CONFIG_MMC_OMAP_HS)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
-
-static struct panel_config lcd_cfg = {
- .timing_h = PANEL_TIMING_H(40, 40, 48),
- .timing_v = PANEL_TIMING_V(29, 13, 3),
- .pol_freq = 0x00003000, /* Pol Freq */
- .divisor = 0x0001000E,
- .panel_type = 0x01, /* TFT */
- .data_lines = 0x03, /* 24 Bit RGB */
- .load_mode = 0x02, /* Frame Mode */
- .panel_color = 0,
- .lcd_size = PANEL_LCD_SIZE(800, 480),
- .gfx_format = GFXFORMAT_RGB24_UNPACKED,
-};
-
-int board_video_init(void)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- void *fb;
-
- fb = (void *)FB_START_ADDRESS;
-
- lcd_cfg.frame_buffer = fb;
-
- setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
- setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
-
- omap3_dss_panel_config(&lcd_cfg);
- omap3_dss_enable();
-
- return 0;
-}
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- *
- * Based on ti/evm/evm.h
- */
-
-#ifndef _AM3517EVM_H_
-#define _AM3517EVM_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "HTKW mcx Board",
- "NAND",
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_MCX() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_CKE0), (M0)) \
- MUX_VAL(CP(SDRC_CKE1), (M0)) \
- MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
- /*sdrc_strben_dly0*/\
- MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
- /*sdrc_strben_dly1*/\
- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
- /* GPIO_43 LCD buffer enable */ \
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
- /* GPIO_57 TS_PenIRQn */\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
- /* GPIO_58 ETHERNET RESET */\
- MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
- /* GPIO_61 SD-CARD CD */ \
- MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
- /* GPIO_62 Nand write protect, keep enabled */ \
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
- /* GPIO_65 SD-CARD WP */\
- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
- /* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
- /* MMC */\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
- /* GPIO_131 LCD Enable */ \
- MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
- /* GPIO_132 USB host Enable */\
- MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
- /* GPIO_133 HDMI PD */\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
- /* McBSP */\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
- /* GPIO_152 USB phy2 reset */\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
- /* GPIO_153 */\
- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
- /* GPIO_154 USB phy1 reset */\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
- /* GPIO_155 TS_BUSY */\
- /* UART */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
- /* I2C */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) \
- /* GPIO_170 Touchscreen ISR */\
- /* McSPI */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat7 */\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat4 */\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat5 */\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat6 */\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat3 */\
- /* CCDC */\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
- /* CCDC_FIELD: gpio_95, uP-TXD4 */ \
- MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \
- /* CCDC_HD: gpio_96, uP-RTS4# */ \
- MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \
- /* CCDC_VD: gpio_97, uP-CTS4# */ \
- MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \
- /* CCDC_WEN: gpio_98, uP-RXD4 */ \
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
- /* RMII */\
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
- MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
- MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
- /* HECC */\
- MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M0)) \
- /* HSUSB */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
- /* HDQ */\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
- /* Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
- \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
- /* JTAG */\
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
- /* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
- /* hsusb1_stp */ \
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
- /* hsusb1_clk */\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
- /* Die to Die */\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
-
-#endif
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+ (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
sync();
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
/* now check the real size */
disable_addr_trans();
- msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+ msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
enable_addr_trans();
#endif
return msize;
msize = setup_sdram();
- out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
- out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+ out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
+ out_be32(&lbc->mrtpr, 0x20000000);
sync();
gd->ram_size = msize;
if test '${boardsoc}' = 'imx53'; then
setenv bootargs '${bootargs} di=${dig_in} key1=${key1}';
fi;"
+setenv nfsadj "
+if test '${boardsoc}' = 'imx53'; then
+ if test '${boardtype}' = 'hsc'; then
+ setenv bootargs '${bootargs} dsa_core.blacklist=yes';
+ fi;
+fi;"
setenv boot_fitImage "
setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb';
setenv itbcfg "\"#\${fdt_conf}\"";
if run download_kernel; then
run nfsargs;
run addip;
+ run nfsadj;
setenv bootargs '${bootargs}' console=${console};
run boot_fitImage;
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
#include <asm/gpio.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include "kp_id_rev.h"
-#define VBUS_PWR_EN IMX_GPIO_NR(7, 8)
-#define PHY_nRST IMX_GPIO_NR(7, 6)
#define BOOSTER_OFF IMX_GPIO_NR(2, 23)
#define LCD_BACKLIGHT IMX_GPIO_NR(1, 1)
#define KEY1 IMX_GPIO_NR(2, 26)
return 0;
}
-#ifdef CONFIG_USB_EHCI_MX5
-int board_ehci_hcd_init(int port)
-{
- gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN");
- gpio_direction_output(VBUS_PWR_EN, 1);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[] = {
- {MMC_SDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return 1; /* eMMC is always present */
-}
-
-#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
- PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
-
- static const iomux_v3_cfg_t sd3_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
- SD_CMD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
- };
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads));
-
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
- if (ret)
- return ret;
-
- return 0;
-}
-#endif
-
static int power_init(void)
{
struct udevice *dev;
return 0;
}
-void eth_phy_reset(void)
-{
- gpio_request(PHY_nRST, "PHY_nRST");
- gpio_direction_output(PHY_nRST, 1);
- udelay(50);
- gpio_set_value(PHY_nRST, 0);
- udelay(400);
- gpio_set_value(PHY_nRST, 1);
- udelay(50);
-}
-
void board_disable_display(void)
{
gpio_request(LCD_BACKLIGHT, "LCD_BACKLIGHT");
if (ret)
printf("Error %d reading EEPROM content!\n", ret);
- eth_phy_reset();
-
show_eeprom();
read_board_id();
-if TARGET_KM8360
+if TARGET_KMETER1
config SYS_BOARD
default "km83xx"
default "keymile"
config SYS_CONFIG_NAME
- default "km8360"
+ default "kmeter1"
+
+endif
+
+if TARGET_KMCOGE5NE
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmcoge5ne"
+
+endif
+
+if TARGET_KMVECT1
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmvect1"
+
+endif
+
+if TARGET_KMTEGR1
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmtegr1"
endif
default "tuxx1"
endif
+
+if TARGET_KMSUPX5
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmsupx5"
+
+endif
+
+if TARGET_TUGE1
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "tuge1"
+
+endif
+
+if TARGET_KMOPTI2
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmopti2"
+
+endif
+
+if TARGET_KMTEPR2
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmtepr2"
+
+endif
KM83XX BOARD
-M: Holger Brunck <holger.brunck@keymile.com>
+M: Holger Brunck <holger.brunck@ch.abb.com>
S: Maintained
F: board/keymile/km83xx/
F: include/configs/km8360.h
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
-#elif !defined(CONFIG_MPC8309)
+#elif !defined(CONFIG_ARCH_MPC8309)
/* Local Bus */
{0, 16, 1, 0, 3}, /* LA00 */
{0, 17, 1, 0, 3}, /* LA01 */
u32 *mxmr = &lbc->mamr;
#endif
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
unsigned short svid;
/*
* Because of errata in the UCCs, we have to write to the reserved
}
#endif
-#if defined(CONFIG_KMCOGE5NE)
+#if defined(CONFIG_TARGET_KMCOGE5NE)
struct bfticu_iomap *base =
(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
msize = CONFIG_SYS_DDR_SIZE << 20;
disable_addr_trans();
- msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+ msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
enable_addr_trans();
msize /= (1024 * 1024);
if (CONFIG_SYS_DDR_SIZE != msize) {
return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
+ CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
KM_ARM BOARD
-M: Valentin Longchamp <valentin.longchamp@keymile.com>
+M: Valentin Longchamp <valentin.longchamp@ch.abb.com>
S: Maintained
F: board/keymile/km_arm/
F: include/configs/km_kirkwood.h
KMP204X BOARD
-M: Valentin Longchamp <valentin.longchamp@keymile.com>
+M: Valentin Longchamp <valentin.longchamp@ch.abb.com>
S: Maintained
F: board/keymile/kmp204x/
F: include/configs/kmp204x.h
--- /dev/null
+if TARGET_MICROCHIP_ICICLE
+
+config SYS_BOARD
+ default "mpfs_icicle"
+
+config SYS_VENDOR
+ default "microchip"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "microchip_mpfs_icicle"
+
+config SYS_TEXT_BASE
+ default 0x80000000 if !RISCV_SMODE
+ default 0x80200000 if RISCV_SMODE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select GENERIC_RISCV
+ select BOARD_EARLY_INIT_F
+ imply SMP
+ imply SYS_NS16550
+
+endif
--- /dev/null
+Microchip MPFS icicle
+M: Padmarao Begari <padmarao.begari@microchip.com>
+M: Cyril Jean <cyril.jean@microchip.com>
+S: Maintained
+F: board/microchip/mpfs_icicle/
+F: include/configs/microchip_mpfs_icicle.h
+F: configs/microchip_mpfs_icicle_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Microchip Technology Inc.
+# Padmarao Begari <padmarao.begari@microchip.com>
+#
+
+obj-y += mpfs_icicle.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+
+int board_init(void)
+{
+ /* For now nothing to do here. */
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ unsigned int val;
+
+ /* Reset uart peripheral */
+ val = readl(MPFS_SYSREG_SOFT_RESET);
+ val = (val & ~(1u << 5u));
+ writel(val, MPFS_SYSREG_SOFT_RESET);
+
+ return 0;
+}
--- /dev/null
+kwbimage.cfg
--- /dev/null
+CRS305-1G-4S BOARD
+M: Luka Kovacic <me@lukakovacic.xyz>
+S: Maintained
+F: board/mikrotik/crs305-1g-4s/
+F: include/configs/crs305-1g-4s.h
+F: configs/crs305-1g-4s_defconfig
+F: arch/arm/dts/armada-xp-crs305-1g-4s.dts
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y := crs305-1g-4s.o
+extra-y := kwbimage.cfg
+
+quiet_cmd_sed = SED $@
+ cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F)
+
+SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
+$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+ include/config/auto.conf
+ $(call if_changed,sed)
--- /dev/null
+MikroTik CRS305-1G-4S+IN
+========================
+
+CRS305-1G-4S+IN is a 4x SFP+ switch with a Gigabit Ethernet port for management.
+Specifications:
+ - Marvell Prestera 98DX3236 switch with an integrated ARMv7 CPU
+ - 512 MB DDR3 RAM
+ - UART @ 115200bps
+ - 4x SFP+
+ - Gigabit Ethernet (AR8033)
+ - 16 MB SPI flash (Winbond 25Q128JVSM)
+
+Currently supported hardware:
+ - UART boot (using kwboot) and console
+ - SPI boot, environment and load kernel
+
+Planned:
+ - Gigabit Ethernet support
+
+Getting binary.0
+================
+binary.0 (DDR3 init phase) can be retrieved/extracted from the integrated bootloader on the SPI flash.
+Then binary.0 can be replaced with the extracted blob.
--- /dev/null
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * These values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
+ */
+#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) \
+ | BIT(6) | BIT(12) | BIT(13) \
+ | BIT(16) | BIT(17) | BIT(20) \
+ | BIT(29) | BIT(30)))
+#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
+#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) \
+ | BIT(6) | BIT(12) | BIT(13) \
+ | BIT(16) | BIT(17) | BIT(20) \
+ | BIT(29) | BIT(30))
+#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
+#define DB_DX_AC3_GPP_POL_LOW 0x0
+#define DB_DX_AC3_GPP_POL_MID 0x0
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x00142222, MVEBU_MPP_BASE + 0x00);
+ writel(0x11122000, MVEBU_MPP_BASE + 0x04);
+ writel(0x44444004, MVEBU_MPP_BASE + 0x08);
+ writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
+ writel(0x00000001, MVEBU_MPP_BASE + 0x10);
+
+ /*
+ * MVEBU_GPIO0_BASE is the User LED
+ * MVEBU_GPIO1_BASE is the Reset Button (currently not used)
+ */
+
+ /* Set GPP Out value */
+ writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ /* writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); */
+
+ /* Set GPP Polarity */
+ writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ /* writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); */
+
+ /* Set GPP Out Enable */
+ writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ /* writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); */
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_SYS_BOARD "\n");
+
+ return 0;
+}
--- /dev/null
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/mikrotik/crs305-1g-4s/binary.0 0000005b 00000068
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ CONFIG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)
+++ /dev/null
-if TARGET_MPR2
-
-config SYS_BOARD
- default "mpr2"
-
-config SYS_CONFIG_NAME
- default "mpr2"
-
-endif
+++ /dev/null
-MPR2 BOARD
-M: Mark Jonas <mark.jonas@de.bosch.com>
-S: Maintained
-F: board/mpr2/
-F: include/configs/mpr2.h
-F: configs/mpr2_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# (C) Copyright 2008
-# Mark Jonas <mark.jonas@de.bosch.com>
-#
-# board/mpr2/Makefile
-#
-
-obj-y := mpr2.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * board/mpr2/lowlevel_init.S
- */
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
-/*
- * Set frequency multipliers and dividers in FRQCR.
- */
- write16 WTCSR_A, WTCSR_D
-
- write16 WTCNT_A, WTCNT_D
-
- write16 FRQCR_A, FRQCR_D
-
-/*
- * Setup CS0 (Flash).
- */
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
-/*
- * Setup CS3 (SDRAM).
- */
- write32 CS3BCR_A, CS3BCR_D
-
- write32 CS3WCR_A, CS3WCR_D
-
- write32 SDCR_A, SDCR_D1
-
- write32 RTCSR_A, RTCSR_D
-
- write32 RTCNT_A, RTCNT_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 SDCR_A, SDCR_D2
-
- mov.l SDMR3_A, r1
- mov.l SDMR3_D, r0
- add r0, r1
- mov #0, r0
- mov.w r0, @r1
-
- rts
- nop
-
- .align 4
-
-/*
- * Configuration for MPR2 A.3 through A.7
- */
-
-/*
- * PLL Settings
- */
-FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
-WTCNT_D: .word 0x5A00 /* start counting at zero */
-WTCSR_D: .word 0xA507 /* divide by 4096 */
-.align 2
-/*
- * Spansion S29GL256N11 @ 48 MHz
- */
-/* 1 idle cycle inserted, normal space, 16 bit */
-CS0BCR_D: .long 0x12490400
-/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
-CS0WCR_D: .long 0x00000340
-
-/*
- * Samsung K4S511632B-UL75 @ 48 MHz
- * Micron MT48LC32M16A2-75 @ 48 MHz
- */
-/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
-CS3BCR_D: .long 0x10004400
-/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
-CS3WCR_D: .long 0x00000091
-/* no refresh, 13 rows, 10 cols, NO bank active mode */
-SDCR_D1: .long 0x00000012
-SDCR_D2: .long 0x00000812 /* refresh */
-RTCSR_D: .long 0xA55A0008 /* 1/4, once */
-RTCNT_D: .long 0xA55A005D /* count 93 */
-RTCOR_D: .long 0xa55a005d /* count 93 */
-/* mode register CL2, burst read and SINGLE WRITE */
-SDMR3_D: .long 0x440
-
-/*
- * Registers
- */
-
-FRQCR_A: .long 0xA415FF80
-WTCNT_A: .long 0xA415FF84
-WTCSR_A: .long 0xA415FF86
-
-#define BSC_BASE 0xA4FD0000
-CS0BCR_A: .long BSC_BASE + 0x04
-CS3BCR_A: .long BSC_BASE + 0x0C
-CS0WCR_A: .long BSC_BASE + 0x24
-CS3WCR_A: .long BSC_BASE + 0x2C
-SDCR_A: .long BSC_BASE + 0x44
-RTCSR_A: .long BSC_BASE + 0x48
-RTCNT_A: .long BSC_BASE + 0x4C
-RTCOR_A: .long BSC_BASE + 0x50
-SDMR3_A: .long BSC_BASE + 0x5000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * board/mpr2/mpr2.c
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: MPR2\n");
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * For MPR2 A.3 through A.7
- */
-
- /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */
- __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */
- __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */
-
- /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */
- __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */
- __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-
- /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */
- __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */
- __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-
- /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */
- __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */
- __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-
- /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */
- __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */
- __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
-
- /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */
- __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */
-
- /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */
- __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */
-
- /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */
- __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */
-
- /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
- __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */
-
- /* OTH: (00) Other fuction
- * GPO: (01) General Purpose Output
- * GPI: (11) General Purpose Input
- * GPI+: (10) General Purpose Input with internal pull-up
- *-------------------------------------------------------
- * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
- * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */
- __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */
-
- /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
- * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */
- __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */
-
- /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
- * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */
- __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */
-
- /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
- * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */
- __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */
-
- /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
- * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */
- __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */
-
- /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
- * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */
- __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */
-
- /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2);
- * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */
- __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */
-
- /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
- * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */
- __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */
-
- /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
- * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */
- __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */
-
- /* K7 (x); K6 (x); K5 (x); K4 (x)
- * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */
- __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */
-
- /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
- * L3 TCK; L2 (x); L1 (x); L0 (x); */
- __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */
-
- /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET);
- * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */
- __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */
- __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */
-
- /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup);
- * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */
- __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */
- __raw_writeb(0x10, PPDR); /* no current flow through pullup */
-
- /* R7 A25; R6 A24; R5 A23; R4 A22;
- * R3 A21; R2 A20; R1 A19; R0 A0; */
- __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */
-
- /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
- * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */
- __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */
-
- /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
- * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */
- __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */
-
- /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
- * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */
- __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */
-
- /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
- * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */
- __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */
-
- return 0;
-}
+++ /dev/null
-if TARGET_MS7720SE
-
-config SYS_BOARD
- default "ms7720se"
-
-config SYS_CONFIG_NAME
- default "ms7720se"
-
-endif
+++ /dev/null
-MS7720SE BOARD
-M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-S: Maintained
-F: board/ms7720se/
-F: include/configs/ms7720se.h
-F: configs/ms7720se_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# board/ms7720se/Makefile
-#
-
-obj-y := ms7720se.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- write16 WTCSR_A, WTCSR_D
-
- write16 WTCNT_A, WTCNT_D
-
- write16 FRQCR_A, FRQCR_D
-
- write16 UCLKCR_A, UCLKCR_D
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS2BCR_A, CS2BCR_D
-
- write32 CS3BCR_A, CS3BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5ABCR_A, CS5ABCR_D
-
- write32 CS5BBCR_A, CS5BBCR_D
-
- write32 CS6ABCR_A, CS6ABCR_D
-
- write32 CS6BBCR_A, CS6BBCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS2WCR_A, CS2WCR_D
-
- write32 CS3WCR_A, CS3WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5AWCR_A, CS5AWCR_D
-
- write32 CS5BWCR_A, CS5BWCR_D
-
- write32 CS6AWCR_A, CS6AWCR_D
-
- write32 CS6BWCR_A, CS6BWCR_D
-
- write32 SDCR_A, SDCR_D1
-
- write32 RTCSR_A, RTCSR_D
-
- write32 RTCNT_A RTCNT_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 SDCR_A, SDCR_D2
-
- write16 SDMR3_A, SDMR3_D
-
- write16 PCCR_A, PCCR_D
-
- write16 PDCR_A, PDCR_D
-
- write16 PECR_A, PECR_D
-
- write16 PGCR_A, PGCR_D
-
- write16 PHCR_A, PHCR_D
-
- write16 PPCR_A, PPCR_D
-
- write16 PTCR_A, PTCR_D
-
- write16 PVCR_A, PVCR_D
-
- write16 PSELA_A, PSELA_D
-
- write32 CCR_A, CCR_D
-
- write8 LED_A, LED_D
-
- rts
- nop
-
- .align 4
-
-FRQCR_A: .long 0xA415FF80 /* FRQCR Address */
-WTCNT_A: .long 0xA415FF84
-WTCSR_A: .long 0xA415FF86
-UCLKCR_A: .long 0xA40A0008
-FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
-WTCNT_D: .word 0x5A00
-WTCSR_D: .word 0xA506
-UCLKCR_D: .word 0xA5C0
-
-#define BSC_BASE 0xA4FD0000
-CMNCR_A: .long BSC_BASE
-CS0BCR_A: .long BSC_BASE + 0x04
-CS2BCR_A: .long BSC_BASE + 0x08
-CS3BCR_A: .long BSC_BASE + 0x0C
-CS4BCR_A: .long BSC_BASE + 0x10
-CS5ABCR_A: .long BSC_BASE + 0x14
-CS5BBCR_A: .long BSC_BASE + 0x18
-CS6ABCR_A: .long BSC_BASE + 0x1C
-CS6BBCR_A: .long BSC_BASE + 0x20
-CS0WCR_A: .long BSC_BASE + 0x24
-CS2WCR_A: .long BSC_BASE + 0x28
-CS3WCR_A: .long BSC_BASE + 0x2C
-CS4WCR_A: .long BSC_BASE + 0x30
-CS5AWCR_A: .long BSC_BASE + 0x34
-CS5BWCR_A: .long BSC_BASE + 0x38
-CS6AWCR_A: .long BSC_BASE + 0x3C
-CS6BWCR_A: .long BSC_BASE + 0x40
-SDCR_A: .long BSC_BASE + 0x44
-RTCSR_A: .long BSC_BASE + 0x48
-RTCNT_A: .long BSC_BASE + 0x4C
-RTCOR_A: .long BSC_BASE + 0x50
-SDMR3_A: .long BSC_BASE + 0x58C0
-
-CMNCR_D: .long 0x00000010
-CS0BCR_D: .long 0x36DB0400
-CS2BCR_D: .long 0x36DB0400
-CS3BCR_D: .long 0x36DB4600
-CS4BCR_D: .long 0x36DB0400
-CS5ABCR_D: .long 0x36DB0400
-CS5BBCR_D: .long 0x36DB0200
-CS6ABCR_D: .long 0x36DB0400
-CS6BBCR_D: .long 0x36DB0400
-CS0WCR_D: .long 0x00000B01
-CS2WCR_D: .long 0x00000500
-CS3WCR_D: .long 0x00006D1B
-CS4WCR_D: .long 0x00000500
-CS5AWCR_D: .long 0x00000500
-CS5BWCR_D: .long 0x00000500
-CS6AWCR_D: .long 0x00000500
-CS6BWCR_D: .long 0x00000500
-SDCR_D1: .long 0x00000011
-RTCSR_D: .long 0xA55A0010
-RTCNT_D: .long 0xA55A001F
-RTCOR_D: .long 0xA55A001F
-SDMR3_D: .word 0x0000
-.align 2
-SDCR_D2: .long 0x00000811
-
-#define PFC_BASE 0xA4050100
-PCCR_A: .long PFC_BASE + 0x04
-PDCR_A: .long PFC_BASE + 0x06
-PECR_A: .long PFC_BASE + 0x08
-PGCR_A: .long PFC_BASE + 0x0C
-PHCR_A: .long PFC_BASE + 0x0E
-PPCR_A: .long PFC_BASE + 0x18
-PTCR_A: .long PFC_BASE + 0x1E
-PVCR_A: .long PFC_BASE + 0x22
-PSELA_A: .long PFC_BASE + 0x24
-
-PCCR_D: .word 0x0000
-PDCR_D: .word 0x0000
-PECR_D: .word 0x0000
-PGCR_D: .word 0x0000
-PHCR_D: .word 0x0000
-PPCR_D: .word 0x00AA
-PTCR_D: .word 0x0280
-PVCR_D: .word 0x0000
-PSELA_D: .word 0x0000
-.align 2
-
-CCR_A: .long 0xFFFFFFEC
-!CCR_D: .long 0x0000000D
-CCR_D: .long 0x0000000B
-
-LED_A: .long 0xB6800000
-LED_D: .long 0xFF
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2007
- * Kenati Technologies, Inc.
- *
- * board/ms7720se/ms7720se.c
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-#define LED_BASE 0xB0800000
-
-int checkboard(void)
-{
- puts("BOARD: Hitachi UL MS7720SE\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
- outw(value & 0xFF, LED_BASE);
-}
#include <common.h>
#include <asm/io.h>
#include <led.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <miiphy.h>
enum {
BOARD_TYPE_PCB090 = 0xAABBCD00,
return 0;
}
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80A0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 31, 0);
+ return 0;
+}
+
static void do_board_detect(void)
{
u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF;
#include <spi.h>
#include <led.h>
#include <wait_bit.h>
+#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
mscc_gpio_set_alternate(19, 0);
}
+int board_phy_config(struct phy_device *phydev)
+{
+ if (gd->board_type == BOARD_TYPE_PCB123)
+ return 0;
+
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80F0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 31, 0);
+
+ return 0;
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
#include <common.h>
#include <asm/io.h>
#include <led.h>
+#include <miiphy.h>
enum {
BOARD_TYPE_PCB106 = 0xAABBCD00,
return 0;
}
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, 0, 31, 0x10);
+ phy_write(phydev, 0, 18, 0x80F0);
+ while (phy_read(phydev, 0, 18) & 0x8000)
+ ;
+ phy_write(phydev, 0, 14, 0x800);
+ phy_write(phydev, 0, 31, 0);
+ return 0;
+}
+
static void do_board_detect(void)
{
u16 gpio_in_reg;
gd->board_type = BOARD_TYPE_PCB106;
else
gd->board_type = BOARD_TYPE_PCB105;
- mscc_phy_wr(1, 16, 15, 0);
} else {
gd->board_type = BOARD_TYPE_PCB105;
}
+ mscc_phy_wr(1, 16, 31, 0x0);
}
#if defined(CONFIG_MULTI_DTB_FIT)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2018 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+
+U-Boot on Nyan
+==============
+
+Nyan-big is supported by mainline U-Boot. This device is based on Tegra124.
+To build it, use the nyan-big config.
+
+To boot it, connect a USB A-A cable from your computer to the back USB port.
+Connect a servo board. Then with t20_rec and warn_rst held down:
+
+ sudo tegrarcm --bct cbootimage-configs/tegra124/nvidia/norrin/PM370_Hynix_2GB_H5TC4G63AFR_PBA_924MHz_01212014.bct
+ --bootloader u-boot-dtb-tegra.bin --loadaddr 0x80108000
+
+The norrin config is close enough that it works well with Nyan.
int nvidia_board_init(void)
{
clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
- clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
+ clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000);
/* For external MAX98090 audio codec */
clock_external_output(1);
*/
#include <common.h>
+#include <environment.h>
+#include <fdtdec.h>
#include <i2c.h>
+#include <linux/libfdt.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/cboot.h>
#include "../p2571/max77620_init.h"
#include "pinmux-config-p2371-2180.h"
return 0;
}
#endif /* PCI */
+
+static void ft_mac_address_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+ const char *path;
+ int offset, err;
+
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
+ if (err < 0)
+ memset(local_mac, 0, ETH_ALEN);
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ printf("ethernet alias points to absent node %s\n", path);
+ return;
+ }
+
+ if (is_valid_ethaddr(local_mac)) {
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+ ETH_ALEN);
+ if (!err)
+ debug("Local MAC address set: %pM\n", local_mac);
+ }
+
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
+ ETH_ALEN);
+ if (!err)
+ debug("MAC address set: %pM\n", mac);
+ }
+ }
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+ struct fdt_memory fb;
+ int err;
+
+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to get carveout for %s: %d\n", node,
+ err);
+
+ return err;
+ }
+
+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+ &fb);
+ if (err < 0) {
+ printf("failed to set carveout for %s: %d\n", node, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ static const char * const nodes[] = {
+ "/host1x@50000000/dc@54200000",
+ "/host1x@50000000/dc@54240000",
+ };
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to copy carveout for %s: %d\n",
+ nodes[i], err);
+ continue;
+ }
+ }
+}
+
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ ft_mac_address_setup(fdt);
+ ft_carveout_setup(fdt);
+
+ return 0;
+}
*/
#include <common.h>
+#include <environment.h>
+#include <fdtdec.h>
#include <i2c.h>
+#include <linux/libfdt.h>
+#include <asm/arch-tegra/cboot.h>
#include "../p2571/max77620_init.h"
-int tegra_board_init(void)
+void pin_mux_mmc(void)
{
struct udevice *dev;
uchar val;
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
if (ret) {
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
- return ret;
+ return;
}
/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
val = 0xF2;
ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1);
if (ret) {
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
- return ret;
+ return;
}
-
- return 0;
}
+#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
struct udevice *dev;
return 0;
}
+#endif
+
+static void ft_mac_address_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+ const char *path;
+ int offset, err;
+
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
+ if (err < 0)
+ memset(local_mac, 0, ETH_ALEN);
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ printf("ethernet alias points to absent node %s\n", path);
+ return;
+ }
+
+ if (is_valid_ethaddr(local_mac)) {
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+ ETH_ALEN);
+ if (!err)
+ debug("Local MAC address set: %pM\n", local_mac);
+ }
+
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
+ ETH_ALEN);
+ if (!err)
+ debug("MAC address set: %pM\n", mac);
+ }
+ }
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+ struct fdt_memory fb;
+ int err;
+
+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to get carveout for %s: %d\n", node,
+ err);
+
+ return err;
+ }
+
+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+ &fb);
+ if (err < 0) {
+ printf("failed to set carveout for %s: %d\n", node, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ static const char * const nodes[] = {
+ "/host1x@13e00000/display-hub@15200000/display@15200000",
+ "/host1x@13e00000/display-hub@15200000/display@15210000",
+ "/host1x@13e00000/display-hub@15200000/display@15220000",
+ };
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+ printf("copying carveout for %s...\n", nodes[i]);
+
+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to copy carveout for %s: %d\n",
+ nodes[i], err);
+
+ continue;
+ }
+ }
+}
+
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ ft_mac_address_setup(fdt);
+ ft_carveout_setup(fdt);
+
+ return 0;
+}
+++ /dev/null
-if TARGET_CALIMAIN
-
-config SYS_BOARD
- default "calimain"
-
-config SYS_VENDOR
- default "omicron"
-
-config SYS_CONFIG_NAME
- default "calimain"
-
-endif
+++ /dev/null
-CALIMAIN BOARD
-M: Manfred Rudigier <manfred.rudigier@omicronenergy.com>
-M: Christoph Rüdisser <christoph.ruedisser@omicronenergy.com>
-S: Maintained
-F: board/omicron/calimain/
-F: include/configs/calimain.h
-F: configs/calimain_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-
-obj-y := calimain.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 OMICRON electronics GmbH
- *
- * Based on da850evm.c. Original Copyrights follow:
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <net.h>
-#include <netdev.h>
-#include <watchdog.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/arch/pinmux_defs.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/timer_defs.h>
-#include "../../../drivers/gpio/da8xx_gpio.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CALIMAIN_HWVERSION_MASK 0x7f000000
-#define CALIMAIN_HWVERSION_SHIFT 24
-
-/* Hardware version pinmux settings */
-const struct pinmux_config hwversion_pins[] = {
- { pinmux(16), 8, 2 }, /* GP7[15] */
- { pinmux(16), 8, 3 }, /* GP7[14] */
- { pinmux(16), 8, 4 }, /* GP7[13] */
- { pinmux(16), 8, 5 }, /* GP7[12] */
- { pinmux(16), 8, 6 }, /* GP7[11] */
- { pinmux(16), 8, 7 }, /* GP7[10] */
- { pinmux(17), 8, 0 }, /* GP7[9] */
- { pinmux(17), 8, 1 } /* GP7[8] */
-};
-
-const struct pinmux_resource pinmuxes[] = {
- PINMUX_ITEM(uart2_pins_txrx),
- PINMUX_ITEM(emac_pins_mii),
- PINMUX_ITEM(emac_pins_mdio),
- PINMUX_ITEM(emifa_pins_nor),
- PINMUX_ITEM(emifa_pins_cs2),
- PINMUX_ITEM(emifa_pins_cs3),
-};
-
-const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-
-const struct lpsc_resource lpsc[] = {
- { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
- { DAVINCI_LPSC_EMAC }, /* image download */
- { DAVINCI_LPSC_UART2 }, /* console */
- { DAVINCI_LPSC_GPIO },
-};
-
-const int lpsc_size = ARRAY_SIZE(lpsc);
-
-/* read board revision from GPIO7[8..14] */
-u32 get_board_rev(void)
-{
- lpsc_on(DAVINCI_LPSC_GPIO);
- if (davinci_configure_pin_mux(hwversion_pins,
- ARRAY_SIZE(hwversion_pins)) != 0)
- return 0xffffffff;
-
- return (davinci_gpio_bank67->in_data & CALIMAIN_HWVERSION_MASK)
- >> CALIMAIN_HWVERSION_SHIFT;
-}
-
-/*
- * determine the oscillator frequency depending on the board revision
- *
- * rev 0x00 ... 25 MHz oscillator
- * rev 0x01 ... 24 MHz oscillator
- */
-int calimain_get_osc_freq(void)
-{
- u32 rev;
- int freq;
-
- rev = get_board_rev();
- switch (rev) {
- case 0x00:
- freq = 25000000;
- break;
- default:
- freq = 24000000;
- break;
- }
- return freq;
-}
-
-int board_init(void)
-{
- int val;
-
- irq_init();
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-#ifdef CONFIG_DRIVER_TI_EMAC
- /* select emac MII mode */
- val = readl(&davinci_syscfg_regs->cfgchip3);
- val &= ~(1 << 8);
- writel(val, &davinci_syscfg_regs->cfgchip3);
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#ifdef CONFIG_HW_WATCHDOG
- davinci_hw_watchdog_enable();
-#endif
-
- printf("Input clock frequency: %d Hz\n", calimain_get_osc_freq());
- printf("Board revision: %d\n", get_board_rev());
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-/*
- * Initializes on-board ethernet controllers.
- */
-int board_eth_init(bd_t *bis)
-{
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
- davinci_hw_watchdog_reset();
-}
-#endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := draak.o
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := draak.o ../rcar-common/common.o
+endif
return 0;
}
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- return -EINVAL;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := eagle.o
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := eagle.o ../rcar-common/common.o
+endif
return 0;
}
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- return -EINVAL;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := ebisu.o
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := ebisu.o ../rcar-common/common.o
+endif
return 0;
}
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- return -EINVAL;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
+++ /dev/null
-if TARGET_ECOVEC
-
-config SYS_BOARD
- default "ecovec"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "ecovec"
-
-endif
+++ /dev/null
-ECOVEC BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/ecovec/
-F: include/configs/ecovec.h
-F: configs/ecovec_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-#
-
-obj-y := ecovec.o
-extra-y += lowlevel_init.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009, 2011 Renesas Solutions Corp.
- * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
- * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <netdev.h>
-
-/* USB power management register */
-#define UPONCR0 0xA40501D4
-
-int checkboard(void)
-{
- puts("BOARD: ecovec\n");
- return 0;
-}
-
-static void debug_led(u8 led)
-{
- /* PDGR[0-4] is debug LED */
- outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR);
-}
-
-int board_late_init(void)
-{
- u8 mac[6];
- char env_mac[18];
-
- udelay(1000);
-
- /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/
- outw(inw(PLCR) & ~0xFFF0, PLCR);
- outw(inw(PNCR) & ~0x000F, PNCR);
- outw(inw(PXCR) & ~0x0FC0, PXCR);
- outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB);
- outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC);
- outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE);
-
- debug_led(1 << 3);
-
- outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
-
- i2c_set_bus_num(1); /* Use I2C 1 */
-
- /* Read MAC address */
- i2c_read(0x50, 0x10, 0, mac, 6);
-
- /* Set MAC address */
- sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
- env_set("ethaddr", env_mac);
-
- debug_led(0x0F);
-
- return 0;
-}
-
-int board_init(void)
-{
-
- /* LED (PTG) */
- outw((inw(PGCR) & ~0xFF) | 0x55, PGCR);
- outw((inw(HIZCRA) & ~0x02), HIZCRA);
-
- debug_led(1 << 0);
-
- /* SCIF0 (PTF, PTM) */
- outw(inw(PFCR) & ~0x30, PFCR);
- outw(inw(PMCR) & ~0x0C, PMCR);
- outw((inw(PSELA) & ~0x40) | 0x40, PSELA);
-
- debug_led(1 << 1);
-
- /* RMII (PTA) */
- outw((inw(PACR) & ~0x0C) | 0x04, PACR);
- outb((inb(PADR) & ~0x02) | 0x02, PADR);
-
- debug_led(1 << 2);
-
- /* USB host */
- outw((inw(PBCR) & ~0x300) | 0x100, PBCR);
- outb((inb(PBDR) & ~0x10) | 0x10, PBDR);
- outl(inl(MSTPCR2) & ~0x100000, MSTPCR2);
- outw(0x0600, UPONCR0);
-
- debug_led(1 << 3);
-
- /* debug switch */
- outw((inw(PVCR) & ~0x03) | 0x02 , PVCR);
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Renesas Solutions Corp.
- * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
- *
- * board/renesas/ecovec/lowlevel_init.S
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-#include <configs/ecovec.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */
- mov.l PVDR_A, r1
- mov.l PVDR_D, r2
- mov.b @r1, r0
- tst r0, r2
- bt 1f
- mov.l JUMP_A, r1
- jmp @r1
- nop
-
-1:
- /* Disable watchdog */
- write16 RWTCSR_A, RWTCSR_D
-
- /* MMU Disable */
- write32 MMUCR_A, MMUCR_D
-
- /* Setup clocks */
- write32 PLLCR_A, PLLCR_D
- write32 FRQCRA_A, FRQCRA_D
- write32 FRQCRB_A, FRQCRB_D
-
- wait_timer TIMER_D
-
- write32 MMSELR_A, MMSELR_D
-
- /* Srtup BSC */
- write32 CMNCR_A, CMNCR_D
- write32 CS0BCR_A, CS0BCR_D
- write32 CS0WCR_A, CS0WCR_D
-
- wait_timer TIMER_D
-
- /* Setup SDRAM */
- write32 DBPDCNT0_A, DBPDCNT0_D0
- write32 DBCONF_A, DBCONF_D
- write32 DBTR0_A, DBTR0_D
- write32 DBTR1_A, DBTR1_D
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D
- write32 DBKIND_A, DBKIND_D
- write32 DBCKECNT_A, DBCKECNT_D
-
- wait_timer TIMER_D
-
- write32 DBCMDCNT_A, DBCMDCNT_D0
- write32 DBMRCNT_A, DBMRCNT_D0
- write32 DBMRCNT_A, DBMRCNT_D1
- write32 DBMRCNT_A, DBMRCNT_D2
- write32 DBMRCNT_A, DBMRCNT_D3
- write32 DBCMDCNT_A, DBCMDCNT_D0
- write32 DBCMDCNT_A, DBCMDCNT_D1
- write32 DBCMDCNT_A, DBCMDCNT_D1
- write32 DBMRCNT_A, DBMRCNT_D4
- write32 DBMRCNT_A, DBMRCNT_D5
- write32 DBMRCNT_A, DBMRCNT_D6
-
- wait_timer TIMER_D
-
- write32 DBEN_A, DBEN_D
- write32 DBRFPDN1_A, DBRFPDN1_D
- write32 DBRFPDN2_A, DBRFPDN2_D
- write32 DBCMDCNT_A, DBCMDCNT_D0
-
-
- /* Dummy read */
- mov.l DUMMY_A ,r1
- synco
- mov.l @r1, r0
- synco
-
- mov.l SDRAM_A ,r1
- synco
- mov.l @r1, r0
- synco
- wait_timer TIMER_D
-
- add #4, r1
- synco
- mov.l @r1, r0
- synco
- wait_timer TIMER_D
-
- add #4, r1
- synco
- mov.l @r1, r0
- synco
- wait_timer TIMER_D
-
- add #4, r1
- synco
- mov.l @r1, r0
- synco
- wait_timer TIMER_D
-
- write32 DBCMDCNT_A, DBCMDCNT_D0
- write32 DBCMDCNT_A, DBCMDCNT_D1
- write32 DBPDCNT0_A, DBPDCNT0_D1
- write32 DBRFPDN0_A, DBRFPDN0_D
-
- wait_timer TIMER_D
-
- write32 CCR_A, CCR_D
-
- stc sr, r0
- mov.l SR_MASK_D, r1
- and r1, r0
- ldc r0, sr
-
- rts
-
- .align 2
-
-PVDR_A: .long PVDR
-PVDR_D: .long 0x00000001
-JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR
-TIMER_D: .long 64
-RWTCSR_A: .long RWTCSR
-RWTCSR_D: .long 0x0000A507
-MMUCR_A: .long MMUCR
-MMUCR_D: .long 0x00000004
-PLLCR_A: .long PLLCR
-PLLCR_D: .long 0x00004000
-FRQCRA_A: .long FRQCRA
-FRQCRA_D: .long 0x8E003508
-FRQCRB_A: .long FRQCRB
-FRQCRB_D: .long 0x0
-MMSELR_A: .long MMSELR
-MMSELR_D: .long 0xA5A50000
-CMNCR_A: .long CMNCR
-CMNCR_D: .long 0x00000013
-CS0BCR_A: .long CS0BCR
-CS0BCR_D: .long 0x11110400
-CS0WCR_A: .long CS0WCR
-CS0WCR_D: .long 0x00000440
-DBPDCNT0_A: .long DBPDCNT0
-DBPDCNT0_D0: .long 0x00000181
-DBPDCNT0_D1: .long 0x00000080
-DBCONF_A: .long DBCONF
-DBCONF_D: .long 0x015B0002
-DBTR0_A: .long DBTR0
-DBTR0_D: .long 0x03061502
-DBTR1_A: .long DBTR1
-DBTR1_D: .long 0x02020102
-DBTR2_A: .long DBTR2
-DBTR2_D: .long 0x01090305
-DBTR3_A: .long DBTR3
-DBTR3_D: .long 0x00000002
-DBKIND_A: .long DBKIND
-DBKIND_D: .long 0x00000005
-DBCKECNT_A: .long DBCKECNT
-DBCKECNT_D: .long 0x00000001
-DBCMDCNT_A: .long DBCMDCNT
-DBCMDCNT_D0:.long 0x2
-DBCMDCNT_D1:.long 0x4
-DBMRCNT_A: .long DBMRCNT
-DBMRCNT_D0: .long 0x00020000
-DBMRCNT_D1: .long 0x00030000
-DBMRCNT_D2: .long 0x00010040
-DBMRCNT_D3: .long 0x00000532
-DBMRCNT_D4: .long 0x00000432
-DBMRCNT_D5: .long 0x000103C0
-DBMRCNT_D6: .long 0x00010040
-DBEN_A: .long DBEN
-DBEN_D: .long 0x01
-DBRFPDN0_A: .long DBRFPDN0
-DBRFPDN1_A: .long DBRFPDN1
-DBRFPDN2_A: .long DBRFPDN2
-DBRFPDN0_D: .long 0x00010000
-DBRFPDN1_D: .long 0x00000613
-DBRFPDN2_D: .long 0x238C003A
-SDRAM_A: .long 0xa8000000
-DUMMY_A: .long 0x0c400000
-CCR_A: .long CCR
-CCR_D: .long 0x0000090B
-SR_MASK_D: .long 0xEFFFFF0F
--- /dev/null
+if TARGET_GRPEACH
+
+config SYS_BOARD
+ default "grpeach"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "grpeach"
+
+endif
--- /dev/null
+GRPEACH BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/renesas/grpeach/
+F: include/configs/grpeach.h
+F: configs/grpeach_defconfig
--- /dev/null
+#
+# Copyright (C) 2017 Renesas Electronics
+# Copyright (C) 2017 Chris Brandt
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := grpeach.o
+obj-y += lowlevel_init.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Renesas Electronics
+ * Copyright (C) Chris Brandt
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+#define RZA1_WDT_BASE 0xfcfe0000
+#define WTCSR 0x00
+#define WTCNT 0x02
+#define WRCSR 0x04
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_mem_size_base() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ /* Dummy read (must read WRCSR:WOVF at least once before clearing) */
+ readb(RZA1_WDT_BASE + WRCSR);
+
+ writew(0xa500, RZA1_WDT_BASE + WRCSR);
+ writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
+ writew(0x5a00, RZA1_WDT_BASE + WTCNT);
+ writew(0xa578, RZA1_WDT_BASE + WTCSR);
+
+ for (;;)
+ asm volatile("wfi");
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Renesas Electronics
+ * Copyright (C) 2017 Chris Brandt
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+
+/* Watchdog Registers */
+#define RZA1_WDT_BASE 0xFCFE0000
+#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
+#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
+#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
+
+/* Standby controller registers (chapter 55) */
+#define RZA1_STBCR_BASE 0xFCFE0020
+#define STBCR1 (RZA1_STBCR_BASE + 0x00)
+#define STBCR2 (RZA1_STBCR_BASE + 0x04)
+#define STBCR3 (RZA1_STBCR_BASE + 0x400)
+#define STBCR4 (RZA1_STBCR_BASE + 0x404)
+#define STBCR5 (RZA1_STBCR_BASE + 0x408)
+#define STBCR6 (RZA1_STBCR_BASE + 0x40c)
+#define STBCR7 (RZA1_STBCR_BASE + 0x410)
+#define STBCR8 (RZA1_STBCR_BASE + 0x414)
+#define STBCR9 (RZA1_STBCR_BASE + 0x418)
+#define STBCR10 (RZA1_STBCR_BASE + 0x41c)
+#define STBCR11 (RZA1_STBCR_BASE + 0x420)
+#define STBCR12 (RZA1_STBCR_BASE + 0x424)
+#define STBCR13 (RZA1_STBCR_BASE + 0x450)
+
+/* Clock Registers */
+#define RZA1_FRQCR_BASE 0xFCFE0010
+#define FRQCR (RZA1_FRQCR_BASE + 0x00)
+#define FRQCR2 (RZA1_FRQCR_BASE + 0x04)
+
+#define SYSCR1 0xFCFE0400 /* System control register 1 */
+#define SYSCR2 0xFCFE0404 /* System control register 2 */
+#define SYSCR3 0xFCFE0408 /* System control register 3 */
+
+/* Disable WDT */
+#define WTCSR_D 0xA518
+#define WTCNT_D 0x5A00
+
+/* Enable all peripheral clocks */
+#define STBCR3_D 0x00000000
+#define STBCR4_D 0x00000000
+#define STBCR5_D 0x00000000
+#define STBCR6_D 0x00000000
+#define STBCR7_D 0x00000024
+#define STBCR8_D 0x00000005
+#define STBCR9_D 0x00000000
+#define STBCR10_D 0x00000000
+#define STBCR11_D 0x000000c0
+#define STBCR12_D 0x000000f0
+
+/*
+ * Set all system clocks to full speed.
+ * On reset, the CPU will be running at 1/2 speed.
+ * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
+ */
+#define FRQCR_D 0x0035
+#define FRQCR2_D 0x0001
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ /* PL310 init */
+ write32 0x3fffff80, 0x00000001
+
+ /* Disable WDT */
+ write16 WTCSR, WTCSR_D
+ write16 WTCNT, WTCNT_D
+
+ /* Set clocks */
+ write16 FRQCR, FRQCR_D
+ write16 FRQCR2, FRQCR2_D
+
+ /* Enable all peripherals(Standby Control) */
+ write8 STBCR3, STBCR3_D
+ write8 STBCR4, STBCR4_D
+ write8 STBCR5, STBCR5_D
+ write8 STBCR6, STBCR6_D
+ write8 STBCR7, STBCR7_D
+ write8 STBCR8, STBCR8_D
+ write8 STBCR9, STBCR9_D
+ write8 STBCR10, STBCR10_D
+ write8 STBCR11, STBCR11_D
+ write8 STBCR12, STBCR12_D
+
+ /* For serial booting, enable read ahead caching to speed things up */
+#define DRCR_0 0x3FEFA00C
+ write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */
+
+ /* Enable all internal RAM */
+ write8 SYSCR1, 0xFF
+ write8 SYSCR2, 0xFF
+ write8 SYSCR3, 0xFF
+
+ nop
+ /* back to arch calling code */
+ mov pc, lr
+
+ .align 4
#include <common.h>
#include <asm/arch/rmobile.h>
+
+#ifdef CONFIG_RCAR_GEN3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* If the firmware passed a device tree use it for U-Boot DRAM setup. */
+extern u64 rcar_atf_boot_args[];
+
+int dram_init(void)
+{
+ const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
+ const void *blob;
+
+ /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
+ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
+ blob = atf_fdt_blob;
+ else
+ blob = gd->fdt_blob;
+
+ return fdtdec_setup_mem_size_base_fdt(blob);
+}
+
+int dram_init_banksize(void)
+{
+ const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
+ const void *blob;
+
+ /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
+ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
+ blob = atf_fdt_blob;
+ else
+ blob = gd->fdt_blob;
+
+ fdtdec_setup_memory_banksize_fdt(blob);
+
+ return 0;
+}
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R-Car Gen3 recovery SPL
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spl.h>
+
+#define RCAR_CNTC_BASE 0xE6080000
+#define CNTCR_EN BIT(0)
+
+void board_init_f(ulong dummy)
+{
+ writel(CNTCR_EN, RCAR_CNTC_BASE);
+ timer_init();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_UART;
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ debug("image entry point: 0x%lx\n", spl_image->entry_point);
+ if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) {
+ typedef void (*image_entry_arg_t)(int, int, int, int)
+ __attribute__ ((noreturn));
+ image_entry_arg_t image_entry =
+ (image_entry_arg_t)(uintptr_t) spl_image->entry_point;
+ image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0);
+ } else {
+ typedef void __noreturn (*image_entry_noargs_t)(void);
+ image_entry_noargs_t image_entry =
+ (image_entry_noargs_t)spl_image->entry_point;
+ image_entry();
+ }
+}
+
+void s_init(void)
+{
+}
+
+void reset_cpu(ulong addr)
+{
+}
+++ /dev/null
-if TARGET_RSK7203
-
-config SYS_BOARD
- default "rsk7203"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "rsk7203"
-
-endif
+++ /dev/null
-RSK7203 BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/rsk7203/
-F: include/configs/rsk7203.h
-F: configs/rsk7203_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
-# Copyright (C) 2008 Renesas Solutions Corp.
-#
-# u-boot/board/rsk7203/Makefile
-#
-
-obj-y := rsk7203.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Cache setting */
- write32 CCR1_A ,CCR1_D
-
- /* ConfigurePortPins */
- write16 PECRL3_A, PECRL3_D
-
- write16 PCCRL4_A, PCCRL4_D0
-
- write16 PECRL4_A, PECRL4_D0
-
- write16 PEIORL_A, PEIORL_D0
-
- write16 PCIORL_A, PCIORL_D
-
- write16 PFCRH2_A, PFCRH2_D
-
- write16 PFCRH3_A, PFCRH3_D
-
- write16 PFCRH1_A, PFCRH1_D
-
- write16 PFIORH_A, PFIORH_D
-
- write16 PECRL1_A, PECRL1_D0
-
- write16 PEIORL_A, PEIORL_D1
-
- /* Configure Operating Frequency */
- write16 WTCSR_A, WTCSR_D0
-
- write16 WTCSR_A, WTCSR_D1
-
- write16 WTCNT_A, WTCNT_D
-
- /* Set clock mode*/
- write16 FRQCR_A, FRQCR_D
-
- /* Configure Bus And Memory */
-init_bsc_cs0:
- write16 PCCRL4_A, PCCRL4_D1
-
- write16 PECRL1_A, PECRL1_D1
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
-init_bsc_cs1:
- write16 PECRL4_A, PECRL4_D1
-
- write32 CS1WCR_A, CS1WCR_D
-
-init_sdram:
- write16 PCCRL2_A, PCCRL2_D
-
- write16 PCCRL4_A, PCCRL4_D2
-
- write16 PCCRL1_A, PCCRL1_D
-
- write16 PCCRL3_A, PCCRL3_D
-
- write32 CS3BCR_A, CS3BCR_D
-
- write32 CS3WCR_A, CS3WCR_D
-
- write32 SDCR_A, SDCR_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 RTCSR_A, RTCSR_D
-
- /* wait 200us */
- mov.l REPEAT_D, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- mov.l SDRAM_MODE, r1
- mov #0, r0
- mov.l r0, @r1
-
- nop
- rts
-
- .align 4
-
-CCR1_A: .long CCR1
-CCR1_D: .long 0x0000090B
-PCCRL4_A: .long 0xFFFE3910
-PCCRL4_D0: .word 0x0000
-.align 2
-PECRL4_A: .long 0xFFFE3A10
-PECRL4_D0: .word 0x0000
-.align 2
-PECRL3_A: .long 0xFFFE3A12
-PECRL3_D: .word 0x0000
-.align 2
-PEIORL_A: .long 0xFFFE3A06
-PEIORL_D0: .word 0x1C00
-PEIORL_D1: .word 0x1C02
-PCIORL_A: .long 0xFFFE3906
-PCIORL_D: .word 0x4000
-.align 2
-PFCRH2_A: .long 0xFFFE3A8C
-PFCRH2_D: .word 0x0000
-.align 2
-PFCRH3_A: .long 0xFFFE3A8A
-PFCRH3_D: .word 0x0000
-.align 2
-PFCRH1_A: .long 0xFFFE3A8E
-PFCRH1_D: .word 0x0000
-.align 2
-PFIORH_A: .long 0xFFFE3A84
-PFIORH_D: .word 0x0729
-.align 2
-PECRL1_A: .long 0xFFFE3A16
-PECRL1_D0: .word 0x0033
-.align 2
-
-
-WTCSR_A: .long 0xFFFE0000
-WTCSR_D0: .word 0xA518
-WTCSR_D1: .word 0xA51D
-WTCNT_A: .long 0xFFFE0002
-WTCNT_D: .word 0x5A84
-.align 2
-FRQCR_A: .long 0xFFFE0010
-FRQCR_D: .word 0x0104
-.align 2
-
-PCCRL4_D1: .word 0x0010
-PECRL1_D1: .word 0x0133
-
-CMNCR_A: .long 0xFFFC0000
-CMNCR_D: .long 0x00001810
-CS0BCR_A: .long 0xFFFC0004
-CS0BCR_D: .long 0x10000400
-CS0WCR_A: .long 0xFFFC0028
-CS0WCR_D: .long 0x00000B41
-PECRL4_D1: .word 0x0100
-.align 2
-CS1WCR_A: .long 0xFFFC002C
-CS1WCR_D: .long 0x00000B01
-PCCRL4_D2: .word 0x0011
-.align 2
-PCCRL3_A: .long 0xFFFE3912
-PCCRL3_D: .word 0x0011
-.align 2
-PCCRL2_A: .long 0xFFFE3914
-PCCRL2_D: .word 0x1111
-.align 2
-PCCRL1_A: .long 0xFFFE3916
-PCCRL1_D: .word 0x1010
-.align 2
-PDCRL4_A: .long 0xFFFE3990
-PDCRL4_D: .word 0x0011
-.align 2
-PDCRL3_A: .long 0xFFFE3992
-PDCRL3_D: .word 0x00011
-.align 2
-PDCRL2_A: .long 0xFFFE3994
-PDCRL2_D: .word 0x1111
-.align 2
-PDCRL1_A: .long 0xFFFE3996
-PDCRL1_D: .word 0x1000
-.align 2
-CS3BCR_A: .long 0xFFFC0010
-CS3BCR_D: .long 0x00004400
-CS3WCR_A: .long 0xFFFC0034
-CS3WCR_D: .long 0x00002892
-SDCR_A: .long 0xFFFC004C
-SDCR_D: .long 0x00000809
-RTCOR_A: .long 0xFFFC0058
-RTCOR_D: .long 0xA55A0041
-RTCSR_A: .long 0xFFFC0050
-RTCSR_D: .long 0xa55a0010
-
-SDRAM_MODE: .long 0xFFFC5040
-REPEAT_D: .long 0x00009C40
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * u-boot/board/rsk7203/rsk7203.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas Technology RSK7203\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
-
-/*
- * The RSK board has the SMSC9118 wired up 'incorrectly'.
- * Byte-swapping is necessary, and so poor performance is inevitable.
- * This problem cannot evade by the swap function of CHIP, this can
- * evade by software Byte-swapping.
- * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
- * functions necessary to solve this problem.
- */
-u32 pkt_data_pull(struct eth_device *dev, u32 addr)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
- return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
- | swab16(*(addr_16 + 1));
-}
-
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
-{
- addr += dev->iobase;
- *(volatile u16 *)(addr + 2) = swab16((u16)val);
- *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
+++ /dev/null
-if TARGET_RSK7264
-
-config SYS_BOARD
- default "rsk7264"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "rsk7264"
-
-endif
+++ /dev/null
-RSK7264 BOARD
-M: Phil Edworthy <phil.edworthy@renesas.com>
-S: Maintained
-F: board/renesas/rsk7264/
-F: include/configs/rsk7264.h
-F: configs/rsk7264_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Renesas Electronics Europe Ltd.
-#
-
-obj-y := rsk7264.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Renesas Electronics Europe Ltd.
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on board/renesas/rsk7203/lowlevel_init.S
- */
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Cache setting */
- write32 CCR1_A ,CCR1_D
-
- /* io_set_cpg */
- write8 STBCR3_A, STBCR3_D
- write8 STBCR4_A, STBCR4_D
- write8 STBCR5_A, STBCR5_D
- write8 STBCR6_A, STBCR6_D
- write8 STBCR7_A, STBCR7_D
- write8 STBCR8_A, STBCR8_D
-
- /* ConfigurePortPins */
-
- /* Leaving LED1 ON for sanity test */
- write16 PJCR1_A, PJCR1_D1
- write16 PJCR2_A, PJCR2_D
- write16 PJIOR0_A, PJIOR0_D1
- write16 PJDR0_A, PJDR0_D
- write16 PJPR0_A, PJPR0_D
-
- /* Configure EN_PIN & RS_PIN */
- write16 PGCR2_A, PGCR2_D
- write16 PGIOR0_A, PGIOR0_D
-
- /* Configure the port pins connected to UART */
- write16 PJCR1_A, PJCR1_D2
- write16 PJIOR0_A, PJIOR0_D2
-
- /* Configure Operating Frequency */
- write16 WTCSR_A, WTCSR_D0
- write16 WTCSR_A, WTCSR_D1
- write16 WTCNT_A, WTCNT_D
-
- /* Control of RESBANK */
- write16 IBNR_A, IBNR_D
- /* Enable SCIF3 module */
- write16 STBCR4_A, STBCR4_D
-
- /* Set clock mode*/
- write16 FRQCR_A, FRQCR_D
-
- /* Configure Bus And Memory */
-init_bsc_cs0:
-
-pfc_settings:
- write16 PCCR2_A, PCCR2_D
- write16 PCCR1_A, PCCR1_D
- write16 PCCR0_A, PCCR0_D
-
- write16 PBCR0_A, PBCR0_D
- write16 PBCR1_A, PBCR1_D
- write16 PBCR2_A, PBCR2_D
- write16 PBCR3_A, PBCR3_D
- write16 PBCR4_A, PBCR4_D
- write16 PBCR5_A, PBCR5_D
-
- write16 PDCR0_A, PDCR0_D
- write16 PDCR1_A, PDCR1_D
- write16 PDCR2_A, PDCR2_D
- write16 PDCR3_A, PDCR3_D
-
- write32 CS0WCR_A, CS0WCR_D
- write32 CS0BCR_A, CS0BCR_D
-
-init_bsc_cs2:
- write16 PJCR0_A, PJCR0_D
- write32 CS2WCR_A, CS2WCR_D
-
-init_sdram:
- write32 CS3BCR_A, CS3BCR_D
- write32 CS3WCR_A, CS3WCR_D
- write32 SDCR_A, SDCR_D
- write32 RTCOR_A, RTCOR_D
- write32 RTCSR_A, RTCSR_D
-
- /* wait 200us */
- mov.l REPEAT_D, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- mov.l SDRAM_MODE, r1
- mov #0, r0
- mov.l r0, @r1
-
- nop
- rts
-
- .align 4
-
-CCR1_A: .long CCR1
-CCR1_D: .long 0x0000090B
-FRQCR_A: .long 0xFFFE0010
-FRQCR_D: .word 0x1003
-.align 2
-STBCR3_A: .long 0xFFFE0408
-STBCR3_D: .long 0x00000002
-STBCR4_A: .long 0xFFFE040C
-STBCR4_D: .word 0x0000
-.align 2
-STBCR5_A: .long 0xFFFE0410
-STBCR5_D: .long 0x00000010
-STBCR6_A: .long 0xFFFE0414
-STBCR6_D: .long 0x00000002
-STBCR7_A: .long 0xFFFE0418
-STBCR7_D: .long 0x0000002A
-STBCR8_A: .long 0xFFFE041C
-STBCR8_D: .long 0x0000007E
-PJCR1_A: .long 0xFFFE390C
-PJCR1_D1: .word 0x0000
-PJCR1_D2: .word 0x0022
-PJCR2_A: .long 0xFFFE390A
-PJCR2_D: .word 0x0000
-.align 2
-PJIOR0_A: .long 0xFFFE3912
-PJIOR0_D1: .word 0x0FC0
-PJIOR0_D2: .word 0x0FE0
-PJDR0_A: .long 0xFFFE3916
-PJDR0_D: .word 0x0FBF
-.align 2
-PJPR0_A: .long 0xFFFE391A
-PJPR0_D: .long 0x00000FBF
-PGCR2_A: .long 0xFFFE38CA
-PGCR2_D: .word 0x0000
-.align 2
-PGIOR0_A: .long 0xFFFE38D2
-PGIOR0_D: .word 0x03F0
-.align 2
-WTCSR_A: .long 0xFFFE0000
-WTCSR_D0: .word 0x0000
-WTCSR_D1: .word 0x0000
-WTCNT_A: .long 0xFFFE0002
-WTCNT_D: .word 0x0000
-.align 2
-PCCR0_A: .long 0xFFFE384E
-PDCR0_A: .long 0xFFFE386E
-PDCR1_A: .long 0xFFFE386C
-PDCR2_A: .long 0xFFFE386A
-PDCR3_A: .long 0xFFFE3868
-PBCR0_A: .long 0xFFFE382E
-PBCR1_A: .long 0xFFFE382C
-PBCR2_A: .long 0xFFFE382A
-PBCR3_A: .long 0xFFFE3828
-PBCR4_A: .long 0xFFFE3826
-PBCR5_A: .long 0xFFFE3824
-PCCR0_D: .word 0x1111
-PDCR0_D: .word 0x1111
-PDCR1_D: .word 0x1111
-PDCR2_D: .word 0x1111
-PDCR3_D: .word 0x1111
-PBCR0_D: .word 0x1110
-PBCR1_D: .word 0x1111
-PBCR2_D: .word 0x1111
-PBCR3_D: .word 0x1111
-PBCR4_D: .word 0x1111
-PBCR5_D: .word 0x0111
-.align 2
-CS0WCR_A: .long 0xFFFC0028
-CS0WCR_D: .long 0x00000B41
-CS0BCR_A: .long 0xFFFC0004
-CS0BCR_D: .long 0x10000400
-PJCR0_A: .long 0xFFFE390E
-PJCR0_D: .word 0x3300
-.align 2
-CS2WCR_A: .long 0xFFFC0030
-CS2WCR_D: .long 0x00000B01
-PCCR2_A: .long 0xFFFE384A
-PCCR2_D: .word 0x0001
-.align 2
-PCCR1_A: .long 0xFFFE384C
-PCCR1_D: .word 0x1111
-.align 2
-CS3BCR_A: .long 0xFFFC0010
-CS3BCR_D: .long 0x00004400
-CS3WCR_A: .long 0xFFFC0034
-CS3WCR_D: .long 0x0000288A
-SDCR_A: .long 0xFFFC004C
-SDCR_D: .long 0x00000812
-RTCOR_A: .long 0xFFFC0058
-RTCOR_D: .long 0xA55A0046
-RTCSR_A: .long 0xFFFC0050
-RTCSR_D: .long 0xA55A0010
-IBNR_A: .long 0xFFFE080E
-IBNR_D: .word 0x0000
-.align 2
-SDRAM_MODE: .long 0xFFFC5040
-REPEAT_D: .long 0x00000085
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Renesas Electronics Europe Ltd.
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on u-boot/board/rsk7264/rsk7203.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas Technology RSK7264\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
-
-/*
- * The RSK board has the SMSC89218 wired up 'incorrectly'.
- * Byte-swapping is necessary, and so poor performance is inevitable.
- * This problem cannot evade by the swap function of CHIP, this can
- * evade by software Byte-swapping.
- * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
- * functions necessary to solve this problem.
- */
-u32 pkt_data_pull(struct eth_device *dev, u32 addr)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
- return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
- | swab16(*(addr_16 + 1));
-}
-
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
-{
- addr += dev->iobase;
- *(volatile u16 *)(addr + 2) = swab16((u16)val);
- *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
+++ /dev/null
-if TARGET_RSK7269
-
-config SYS_BOARD
- default "rsk7269"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "rsk7269"
-
-endif
+++ /dev/null
-RSK7269 BOARD
-#M: -
-S: Maintained
-F: board/renesas/rsk7269/
-F: include/configs/rsk7269.h
-F: configs/rsk7269_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2012 Renesas Electronics Europe Ltd.
-# Copyright (C) 2012 Phil Edworthy
-#
-
-obj-y := rsk7269.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Renesas Electronics Europe Ltd.
- * Copyright (C) 2012 Phil Edworthy
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on board/renesas/rsk7264/lowlevel_init.S
- */
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Flush and enable caches (data cache in write-through mode) */
- write32 CCR1_A ,CCR1_D
-
- /* Disable WDT */
- write16 WTCSR_A, WTCSR_D
- write16 WTCNT_A, WTCNT_D
-
- /* Disable Register Bank interrupts */
- write16 IBNR_A, IBNR_D
-
- /* Set clocks based on 13.225MHz xtal */
- write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
-
- /* Enable all peripherals */
- write8 STBCR3_A, STBCR3_D
- write8 STBCR4_A, STBCR4_D
- write8 STBCR5_A, STBCR5_D
- write8 STBCR6_A, STBCR6_D
- write8 STBCR7_A, STBCR7_D
- write8 STBCR8_A, STBCR8_D
- write8 STBCR9_A, STBCR9_D
- write8 STBCR10_A, STBCR10_D
-
- /* SCIF7 and IIC2 */
- write16 PJCR3_A, PJCR3_D /* TXD7 */
- write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
-
- /* Configure bus (CS0) */
- write16 PFCR3_A, PFCR3_D /* A24 */
- write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
- write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
- write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
- write32 CS0WCR_A, CS0WCR_D
- write32 CS0BCR_A, CS0BCR_D
-
- /* Configure SDRAM (CS3) */
- write16 PCCR2_A, PCCR2_D /* CS3# */
- write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
- write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
- write32 CS3BCR_A, CS3BCR_D
- write32 CS3WCR_A, CS3WCR_D
- write32 SDCR_A, SDCR_D
- write32 RTCOR_A, RTCOR_D
- write32 RTCSR_A, RTCSR_D
-
- /* Configure ethernet (CS1) */
- write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
- write16 PHCR0_A, PHCR0_D
- write16 PFCR2_A, PFCR2_D /* CS1# */
- write32 CS1BCR_A, CS1BCR_D /* Big endian */
- write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
- write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
- write16 PJIOR1_A, PJIOR1_D
-
- /* wait 200us */
- mov.l REPEAT_D, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- mov.l SDRAM_MODE, r1
- mov #0, r0
- mov.l r0, @r1
-
- nop
- rts
-
- .align 4
-
-CCR1_A: .long CCR1
-CCR1_D: .long 0x0000090B
-
-STBCR3_A: .long 0xFFFE0408
-STBCR4_A: .long 0xFFFE040C
-STBCR5_A: .long 0xFFFE0410
-STBCR6_A: .long 0xFFFE0414
-STBCR7_A: .long 0xFFFE0418
-STBCR8_A: .long 0xFFFE041C
-STBCR9_A: .long 0xFFFE0440
-STBCR10_A: .long 0xFFFE0444
-STBCR3_D: .long 0x0000001A
-STBCR4_D: .long 0x00000000
-STBCR5_D: .long 0x00000000
-STBCR6_D: .long 0x00000000
-STBCR7_D: .long 0x00000012
-STBCR8_D: .long 0x00000009
-STBCR9_D: .long 0x00000000
-STBCR10_D: .long 0x00000010
-
-WTCSR_A: .long 0xFFFE0000
-WTCNT_A: .long 0xFFFE0002
-WTCSR_D: .word 0xA518
-WTCNT_D: .word 0x5A00
-
-IBNR_A: .long 0xFFFE080E
-IBNR_D: .word 0x0000
-.align 2
-FRQCR_A: .long 0xFFFE0010
-FRQCR_D: .word 0x0015
-.align 2
-
-PJCR3_A: .long 0xFFFE3908
-PJCR3_D: .word 0x5000
-.align 2
-PECR1_A: .long 0xFFFE388C
-PECR1_D: .word 0x2011
-.align 2
-
-PFCR3_A: .long 0xFFFE38A8
-PFCR2_A: .long 0xFFFE38AA
-PBCR5_A: .long 0xFFFE3824
-PFCR3_D: .word 0x0010
-PFCR2_D: .word 0x0101
-PBCR5_D: .word 0x0111
-.align 2
-CS0WCR_A: .long 0xFFFC0028
-CS0WCR_D: .long 0x00000341
-CS0BCR_A: .long 0xFFFC0004
-CS0BCR_D: .long 0x00000400
-
-PCCR2_A: .long 0xFFFE384A
-PCCR1_A: .long 0xFFFE384C
-PCCR0_A: .long 0xFFFE384E
-PCCR2_D: .word 0x0001
-PCCR1_D: .word 0x1111
-PCCR0_D: .word 0x1111
-.align 2
-CS3BCR_A: .long 0xFFFC0010
-CS3BCR_D: .long 0x00004400
-CS3WCR_A: .long 0xFFFC0034
-CS3WCR_D: .long 0x00004912
-SDCR_A: .long 0xFFFC004C
-SDCR_D: .long 0x00000811
-RTCOR_A: .long 0xFFFC0058
-RTCOR_D: .long 0xA55A0035
-RTCSR_A: .long 0xFFFC0050
-RTCSR_D: .long 0xA55A0010
-.align 2
-SDRAM_MODE: .long 0xFFFC5460
-REPEAT_D: .long 0x000033F1
-
-PHCR1_A: .long 0xFFFE38EC
-PHCR0_A: .long 0xFFFE38EE
-PHCR1_D: .word 0x2222
-PHCR0_D: .word 0x2222
-.align 2
-CS1BCR_A: .long 0xFFFC0008
-CS1BCR_D: .long 0x00000400
-CS1WCR_A: .long 0xFFFC002C
-CS1WCR_D: .long 0x00000080
-PJDR1_A: .long 0xFFFE3914
-PJDR1_D: .word 0x0000
-.align 2
-PJIOR1_A: .long 0xFFFE3910
-PJIOR1_D: .word 0x8000
-.align 2
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Renesas Electronics Europe Ltd.
- * Copyright (C) 2012 Phil Edworthy
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on u-boot/board/rsk7264/rsk7264.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas RSK7269\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
-
-/*
- * The RSK board has the SMSC89218 wired up 'incorrectly'.
- * Byte-swapping is necessary, and so poor performance is inevitable.
- * This problem cannot evade by the swap function of CHIP, this can
- * evade by software Byte-swapping.
- * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
- * functions necessary to solve this problem.
- */
-u32 pkt_data_pull(struct eth_device *dev, u32 addr)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
- return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
- | swab16(*(addr_16 + 1));
-}
-
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
-{
- addr += dev->iobase;
- *(volatile u16 *)(addr + 2) = swab16((u16)val);
- *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := salvator-x.o
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := salvator-x.o ../rcar-common/common.o
+endif
return 0;
}
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- return -EINVAL;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
You can select the configuration as follows:
- - make sh7785lcr_config
+ - make sh7757lcr_config
This board specific command:
+++ /dev/null
-if TARGET_SH7785LCR
-
-config SYS_BOARD
- default "sh7785lcr"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "sh7785lcr"
-
-endif
+++ /dev/null
-SH7785LCR BOARD
-#M: -
-S: Maintained
-F: board/renesas/sh7785lcr/
-F: include/configs/sh7785lcr.h
-F: configs/sh7785lcr_defconfig
-F: configs/sh7785lcr_32bit_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-
-obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o
-extra-y += lowlevel_init.o
+++ /dev/null
-========================================
-Renesas Technology R0P7785LC0011RL board
-========================================
-
-This board specification:
-=========================
-
-The R0P7785LC0011RL(board config name:sh7785lcr) has the following device:
-
- - SH7785 (SH-4A)
- - DDR2-SDRAM 512MB
- - NOR Flash 64MB
- - 2D Graphic controller
- - SATA controller
- - Ethernet controller
- - USB host/peripheral controller
- - SD controller
- - I2C controller
- - RTC
-
-This board has 2 physical memory maps. It can be changed with DIP switch(S2-5).
-
- phys address | S2-5 = OFF | S2-5 = ON
- -------------------------------+---------------+---------------
- 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
- 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
- 0x06000000 - 0x07ffffff(CS1) | reserved | I2C
- 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
- 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
- 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
- 0x14000000 - 0x17ffffff(CS5) | I2C | USB
- 0x18000000 - 0x1bffffff(CS6) | reserved | SD
- 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
-
-
-configuration for This board:
-=============================
-
-You can choose configuration as follows:
-
- - make sh7785lcr_config
- - make sh7785lcr_32bit_config
-
-When you use "make sh7785lcr_config", there is build U-Boot for 29-bit
-address mode. This mode can use 128MB DDR-SDRAM.
-
-When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit
-extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
-"pmb" command, this mode can use 512MB DDR-SDRAM.
-
- * 32-bit extended address mode PMB mapping *
- a) on start-up
- virt | phys | size | device
- -------------+---------------+---------------+---------------
- 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
- 0xa0000000 | 0x00000000 | 64MB | NOR Flash
- 0xa4000000 | 0x04000000 | 16MB | PLD
- 0xa6000000 | 0x08000000 | 16MB | USB
- 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
-
- b) after "pmb" command
- virt | phys | size | device
- -------------+---------------+---------------+---------------
- 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
- 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
-
-
-This board specific command:
-============================
-
-This board has the following its specific command:
-
- - hwtest
- - printmac
- - setmac
- - pmb (sh7785lcr_32bit_config only)
-
-
-1. hwtest
-
-This is self-check command. This command has the following options:
-
- - all : test all hardware
- - pld : output PLD version
- - led : turn on LEDs
- - dipsw : test DIP switch
- - sm107 : output SM107 version
- - net : check RTL8110 ID
- - sata : check SiI3512 ID
- - net : output PCI slot device ID
-
-i.e)
-=> hwtest led
-turn on LEDs 3, 5, 7, 9
-turn on LEDs 4, 6, 8, 10
-
-=> hwtest net
-Ethernet OK
-
-
-2. printmac
-
-This command outputs MAC address of this board.
-
-i.e)
-=> printmac
-MAC = 00:00:87:**:**:**
-
-
-3. setmac
-
-This command writes MAC address of this board.
-
-i.e)
-=> setmac 00:00:87:**:**:**
-
-
-4. pmb
-
-This command change PMB for DDR-SDRAM all mapping. However you cannot use
-NOR Flash and USB Host on U-Boot when you run this command.
-i.e)
-=> pmb
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-#include <asm/processor.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- wait_timer WAIT_200US
- wait_timer WAIT_200US
-
- /*------- LBSC -------*/
- write32 MMSELR_A, MMSELR_D
-
- /*------- DBSC2 -------*/
- write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
- write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
- write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
- write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
- write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
- write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
- wait_timer WAIT_200US
-
- write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
- write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
- wait_timer WAIT_200US
- write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
- write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
- write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
- write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
- write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
- write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
- write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
- write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
- write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
- wait_timer WAIT_200US
-
- write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
- write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
-
- write32 DBSC2_DBEN_A, DBSC2_DBEN_D
- write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
- write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
- write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
- wait_timer WAIT_200US
-
- /*------- GPIO -------*/
- write16 PACR_A, PXCR_D
- write16 PBCR_A, PXCR_D
- write16 PCCR_A, PXCR_D
- write16 PDCR_A, PXCR_D
- write16 PECR_A, PXCR_D
- write16 PFCR_A, PXCR_D
- write16 PGCR_A, PXCR_D
- write16 PHCR_A, PHCR_D
- write16 PJCR_A, PJCR_D
- write16 PKCR_A, PKCR_D
- write16 PLCR_A, PXCR_D
- write16 PMCR_A, PMCR_D
- write16 PNCR_A, PNCR_D
- write16 PPCR_A, PXCR_D
- write16 PQCR_A, PXCR_D
- write16 PRCR_A, PXCR_D
-
- write8 PEPUPR_A, PEPUPR_D
- write8 PHPUPR_A, PHPUPR_D
- write8 PJPUPR_A, PJPUPR_D
- write8 PKPUPR_A, PKPUPR_D
- write8 PLPUPR_A, PLPUPR_D
- write8 PMPUPR_A, PMPUPR_D
- write8 PNPUPR_A, PNPUPR_D
- write16 PPUPR1_A, PPUPR1_D
- write16 PPUPR2_A, PPUPR2_D
- write16 P1MSELR_A, P1MSELR_D
- write16 P2MSELR_A, P2MSELR_D
-
- /*------- LBSC -------*/
- write32 BCR_A, BCR_D
- write32 CS0BCR_A, CS0BCR_D
- write32 CS0WCR_A, CS0WCR_D
- write32 CS1BCR_A, CS1BCR_D
- write32 CS1WCR_A, CS1WCR_D
- write32 CS4BCR_A, CS4BCR_D
- write32 CS4WCR_A, CS4WCR_D
-
- mov.l PASCR_A, r0
- mov.l @r0, r2
- mov.l PASCR_32BIT_MODE, r1
- tst r1, r2
- bt lbsc_29bit
-
- write32 CS2BCR_A, CS_USB_BCR_D
- write32 CS2WCR_A, CS_USB_WCR_D
- write32 CS3BCR_A, CS_SD_BCR_D
- write32 CS3WCR_A, CS_SD_WCR_D
- write32 CS5BCR_A, CS_I2C_BCR_D
- write32 CS5WCR_A, CS_I2C_WCR_D
- write32 CS6BCR_A, CS0BCR_D
- write32 CS6WCR_A, CS0WCR_D
- bra lbsc_end
- nop
-
-lbsc_29bit:
- write32 CS5BCR_A, CS_USB_BCR_D
- write32 CS5WCR_A, CS_USB_WCR_D
- write32 CS6BCR_A, CS_SD_BCR_D
- write32 CS6WCR_A, CS_SD_WCR_D
-
-lbsc_end:
-#if defined(CONFIG_SH_32BIT)
- /*------- set PMB -------*/
- write32 PASCR_A, PASCR_29BIT_D
- write32 MMUCR_A, MMUCR_D
-
- /*****************************************************************
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x00000000 1 64M 0 0
- * 1 0xa4000000 0x04000000 1 16M 0 0
- * 2 0xa6000000 0x08000000 1 16M 0 0
- * 9 0x88000000 0x48000000 1 128M 1 1
- * 10 0x90000000 0x50000000 1 128M 1 1
- * 11 0x98000000 0x58000000 1 128M 1 1
- * 13 0xa8000000 0x48000000 1 128M 0 0
- * 14 0xb0000000 0x50000000 1 128M 0 0
- * 15 0xb8000000 0x58000000 1 128M 0 0
- */
- write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
- write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
- write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
- write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
- write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
- write32 PMB_DATA_USB_A, PMB_DATA_USB_D
- write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
- write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
- write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
- write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
- write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
- write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
- write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
- write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
- write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
- write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
- write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
- write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
-
- write32 PASCR_A, PASCR_INIT
- mov.l DUMMY_ADDR, r0
- icbi @r0
-#endif
-
- write32 CCR_A, CCR_D
-
- rts
- nop
-
- .align 4
-
-/*------- GPIO -------*/
-/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
-PXCR_D: .word 0x0000
-
-PHCR_D: .word 0x00c0
-PJCR_D: .word 0xc3fc
-PKCR_D: .word 0x03ff
-PMCR_D: .word 0xffff
-PNCR_D: .word 0xf0c3
-
-PEPUPR_D: .long 0xff
-PHPUPR_D: .long 0x00
-PJPUPR_D: .long 0x00
-PKPUPR_D: .long 0x00
-PLPUPR_D: .long 0x00
-PMPUPR_D: .long 0xfc
-PNPUPR_D: .long 0x00
-PPUPR1_D: .word 0xffbf
-PPUPR2_D: .word 0xff00
-P1MSELR_D: .word 0x3780
-P2MSELR_D: .word 0x0000
-
-#define GPIO_BASE 0xffe70000
-PACR_A: .long GPIO_BASE + 0x00
-PBCR_A: .long GPIO_BASE + 0x02
-PCCR_A: .long GPIO_BASE + 0x04
-PDCR_A: .long GPIO_BASE + 0x06
-PECR_A: .long GPIO_BASE + 0x08
-PFCR_A: .long GPIO_BASE + 0x0a
-PGCR_A: .long GPIO_BASE + 0x0c
-PHCR_A: .long GPIO_BASE + 0x0e
-PJCR_A: .long GPIO_BASE + 0x10
-PKCR_A: .long GPIO_BASE + 0x12
-PLCR_A: .long GPIO_BASE + 0x14
-PMCR_A: .long GPIO_BASE + 0x16
-PNCR_A: .long GPIO_BASE + 0x18
-PPCR_A: .long GPIO_BASE + 0x1a
-PQCR_A: .long GPIO_BASE + 0x1c
-PRCR_A: .long GPIO_BASE + 0x1e
-PEPUPR_A: .long GPIO_BASE + 0x48
-PHPUPR_A: .long GPIO_BASE + 0x4e
-PJPUPR_A: .long GPIO_BASE + 0x50
-PKPUPR_A: .long GPIO_BASE + 0x52
-PLPUPR_A: .long GPIO_BASE + 0x54
-PMPUPR_A: .long GPIO_BASE + 0x56
-PNPUPR_A: .long GPIO_BASE + 0x58
-PPUPR1_A: .long GPIO_BASE + 0x60
-PPUPR2_A: .long GPIO_BASE + 0x62
-P1MSELR_A: .long GPIO_BASE + 0x80
-P2MSELR_A: .long GPIO_BASE + 0x82
-
-MMSELR_A: .long 0xfc400020
-#if defined(CONFIG_SH_32BIT)
-MMSELR_D: .long 0xa5a50005
-#else
-MMSELR_D: .long 0xa5a50002
-#endif
-
-/*------- DBSC2 -------*/
-#define DBSC2_BASE 0xfe800000
-DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
-DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
-DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
-DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
-DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
-DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
-DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
-DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
-DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
-DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
-DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
-DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
-DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
-DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
-DDR_DUMMY_ACCESS_A: .long 0x40000000
-
-DBSC2_DBCONF_D: .long 0x00630002
-DBSC2_DBTR0_D: .long 0x050b1f04
-DBSC2_DBTR1_D: .long 0x00040204
-DBSC2_DBTR2_D: .long 0x02100308
-DBSC2_DBFREQ_D1: .long 0x00000000
-DBSC2_DBFREQ_D2: .long 0x00000100
-DBSC2_DBDICODTOCD_D:.long 0x000f0907
-
-DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
-DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
-DBSC2_DBCMDCNT_D_REF: .long 0x00000004
-
-DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
-DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
-DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
-DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
-DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
-DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
-
-DBSC2_DBEN_D: .long 0x00000001
-
-DBSC2_DBPDCNT0_D3: .long 0x00000080
-DBSC2_DBRFCNT1_D: .long 0x00000926
-DBSC2_DBRFCNT2_D: .long 0x00fe00fe
-DBSC2_DBRFCNT0_D: .long 0x00010000
-
-WAIT_200US: .long 33333
-
-/*------- LBSC -------*/
-PASCR_A: .long 0xff000070
-PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
-
-BCR_A: .long BCR
-CS0BCR_A: .long CS0BCR
-CS0WCR_A: .long CS0WCR
-CS1BCR_A: .long CS1BCR
-CS1WCR_A: .long CS1WCR
-CS2BCR_A: .long CS2BCR
-CS2WCR_A: .long CS2WCR
-CS3BCR_A: .long CS3BCR
-CS3WCR_A: .long CS3WCR
-CS4BCR_A: .long CS4BCR
-CS4WCR_A: .long CS4WCR
-CS5BCR_A: .long CS5BCR
-CS5WCR_A: .long CS5WCR
-CS6BCR_A: .long CS6BCR
-CS6WCR_A: .long CS6WCR
-
-BCR_D: .long 0x80000003
-CS0BCR_D: .long 0x22222340
-CS0WCR_D: .long 0x00111118
-CS1BCR_D: .long 0x11111100
-CS1WCR_D: .long 0x33333303
-CS4BCR_D: .long 0x11111300
-CS4WCR_D: .long 0x00101012
-
-/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
-CS_USB_BCR_D: .long 0x11111200
-CS_USB_WCR_D: .long 0x00020005
-
-/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
-CS_SD_BCR_D: .long 0x00000300
-CS_SD_WCR_D: .long 0x00030108
-
-/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
-CS_I2C_BCR_D: .long 0x11111100
-CS_I2C_WCR_D: .long 0x00000003
-
-#if defined(CONFIG_SH_32BIT)
-/*------- set PMB -------*/
-PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
-PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
-PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
-PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
-PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
-PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
-PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
-PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
-PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
-
-PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
-PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
-PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
-PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
-PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
-PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
-PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
-PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
-PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
-
-PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
-PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
-PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
-PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
-PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
-PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
-PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
-PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
-PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
-
-/* ppn ub v s1 s0 c wt */
-PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
-PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
-PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
-PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
-PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
-PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
-
-DUMMY_ADDR: .long 0xa0000000
-PASCR_29BIT_D: .long 0x00000000
-PASCR_INIT: .long 0x80000080 /* check booting mode */
-MMUCR_A: .long 0xff000010
-MMUCR_D: .long 0x00000004 /* clear ITLB */
-#endif /* CONFIG_SH_32BIT */
-
-CCR_A: .long 0xff00001c
-CCR_D: .long 0x0000090b
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr))
-#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr))
-#define PCI_PAR PCIREG_32(0xfe0401c0)
-#define PCI_PDR PCIREG_32(0xfe040220)
-#define PCI_CR PCIREG_32(0xfe040100)
-#define PCI_CONF1 PCIREG_32(0xfe040004)
-
-#define HIGH 1
-#define LOW 0
-
-#define PCI_PROG 0x80
-#define PCI_EEP_ADDRESS (unsigned short)0x0007
-#define PCI_MAC_ADDRESS_SIZE 3
-
-#define TIME1 100
-#define TIME2 20000
-
-#define BIT_DUMMY 0
-#define MAC_EEP_READ 1
-#define MAC_EEP_WRITE 2
-#define MAC_EEP_ERACE 3
-#define MAC_EEP_EWEN 4
-#define MAC_EEP_EWDS 5
-
-/* RTL8169 */
-const unsigned short EEPROM_W_Data_8169_A[] = {
- 0x8129, 0x10ec, 0x8169, 0x1154, 0x032b,
- 0x4020, 0xa101
-};
-const unsigned short EEPROM_W_Data_8169_B[] = {
- 0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#include <common.h>
-#include "rtl8169.h"
-
-static unsigned char *PCI_MEMR;
-
-static void mac_delay(unsigned int cnt)
-{
- udelay(cnt);
-}
-
-static void mac_pci_setup(void)
-{
- unsigned long pci_data;
-
- PCI_PAR = 0x00000010;
- PCI_PDR = 0x00001000;
- PCI_PAR = 0x00000004;
- pci_data = PCI_PDR;
- PCI_PDR = pci_data | 0x00000007;
- PCI_PAR = 0x00000010;
-
- PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0);
-}
-
-static void EECS(int level)
-{
- unsigned char data = *PCI_MEMR;
-
- if (level)
- *PCI_MEMR = data | 0x08;
- else
- *PCI_MEMR = data & 0xf7;
-}
-
-static void EECLK(int level)
-{
- unsigned char data = *PCI_MEMR;
-
- if (level)
- *PCI_MEMR = data | 0x04;
- else
- *PCI_MEMR = data & 0xfb;
-}
-
-static void EEDI(int level)
-{
- unsigned char data = *PCI_MEMR;
-
- if (level)
- *PCI_MEMR = data | 0x02;
- else
- *PCI_MEMR = data & 0xfd;
-}
-
-static inline void sh7785lcr_bitset(unsigned short bit)
-{
- if (bit)
- EEDI(HIGH);
- else
- EEDI(LOW);
-
- EECLK(LOW);
- mac_delay(TIME1);
- EECLK(HIGH);
- mac_delay(TIME1);
- EEDI(LOW);
-}
-
-static inline unsigned char sh7785lcr_bitget(void)
-{
- unsigned char bit;
-
- EECLK(LOW);
- mac_delay(TIME1);
- bit = *PCI_MEMR & 0x01;
- EECLK(HIGH);
- mac_delay(TIME1);
-
- return bit;
-}
-
-static inline void sh7785lcr_setcmd(unsigned char command)
-{
- sh7785lcr_bitset(BIT_DUMMY);
- switch (command) {
- case MAC_EEP_READ:
- sh7785lcr_bitset(1);
- sh7785lcr_bitset(1);
- sh7785lcr_bitset(0);
- break;
- case MAC_EEP_WRITE:
- sh7785lcr_bitset(1);
- sh7785lcr_bitset(0);
- sh7785lcr_bitset(1);
- break;
- case MAC_EEP_ERACE:
- sh7785lcr_bitset(1);
- sh7785lcr_bitset(1);
- sh7785lcr_bitset(1);
- break;
- case MAC_EEP_EWEN:
- sh7785lcr_bitset(1);
- sh7785lcr_bitset(0);
- sh7785lcr_bitset(0);
- break;
- case MAC_EEP_EWDS:
- sh7785lcr_bitset(1);
- sh7785lcr_bitset(0);
- sh7785lcr_bitset(0);
- break;
- default:
- break;
- }
-}
-
-static inline unsigned short sh7785lcr_getdt(void)
-{
- unsigned short data = 0;
- int i;
-
- sh7785lcr_bitget(); /* DUMMY */
- for (i = 0 ; i < 16 ; i++) {
- data <<= 1;
- data |= sh7785lcr_bitget();
- }
- return data;
-}
-
-static inline void sh7785lcr_setadd(unsigned short address)
-{
- sh7785lcr_bitset(address & 0x0020); /* A5 */
- sh7785lcr_bitset(address & 0x0010); /* A4 */
- sh7785lcr_bitset(address & 0x0008); /* A3 */
- sh7785lcr_bitset(address & 0x0004); /* A2 */
- sh7785lcr_bitset(address & 0x0002); /* A1 */
- sh7785lcr_bitset(address & 0x0001); /* A0 */
-}
-
-static inline void sh7785lcr_setdata(unsigned short data)
-{
- sh7785lcr_bitset(data & 0x8000);
- sh7785lcr_bitset(data & 0x4000);
- sh7785lcr_bitset(data & 0x2000);
- sh7785lcr_bitset(data & 0x1000);
- sh7785lcr_bitset(data & 0x0800);
- sh7785lcr_bitset(data & 0x0400);
- sh7785lcr_bitset(data & 0x0200);
- sh7785lcr_bitset(data & 0x0100);
- sh7785lcr_bitset(data & 0x0080);
- sh7785lcr_bitset(data & 0x0040);
- sh7785lcr_bitset(data & 0x0020);
- sh7785lcr_bitset(data & 0x0010);
- sh7785lcr_bitset(data & 0x0008);
- sh7785lcr_bitset(data & 0x0004);
- sh7785lcr_bitset(data & 0x0002);
- sh7785lcr_bitset(data & 0x0001);
-}
-
-static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address,
- unsigned int count)
-{
- unsigned int i;
-
- for (i = 0; i < count; i++) {
- EECS(HIGH);
- EEDI(LOW);
- mac_delay(TIME1);
-
- sh7785lcr_setcmd(MAC_EEP_WRITE);
- sh7785lcr_setadd(address++);
- sh7785lcr_setdata(*(data + i));
-
- EECLK(LOW);
- EEDI(LOW);
- EECS(LOW);
- mac_delay(TIME2);
- }
-}
-
-static void sh7785lcr_macerase(void)
-{
- unsigned int i;
- unsigned short pci_address = 7;
-
- for (i = 0; i < 3; i++) {
- EECS(HIGH);
- EEDI(LOW);
- mac_delay(TIME1);
- sh7785lcr_setcmd(MAC_EEP_ERACE);
- sh7785lcr_setadd(pci_address++);
- mac_delay(TIME1);
- EECLK(LOW);
- EEDI(LOW);
- EECS(LOW);
- }
-
- mac_delay(TIME2);
-
- printf("\n\nErace End\n");
- for (i = 0; i < 10; i++)
- mac_delay(TIME2);
-}
-
-static void sh7785lcr_macwrite(unsigned short *data)
-{
- sh7785lcr_macerase();
-
- sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7);
- sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
- sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54);
-}
-
-void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count)
-{
- unsigned int i;
- unsigned short wk;
-
- for (i = 0 ; i < count; i++) {
- EECS(HIGH);
- EEDI(LOW);
- mac_delay(TIME1);
- sh7785lcr_setcmd(MAC_EEP_READ);
- sh7785lcr_setadd(address++);
- wk = sh7785lcr_getdt();
-
- *buf++ = (unsigned char)(wk & 0xff);
- *buf++ = (unsigned char)((wk >> 8) & 0xff);
- EECLK(LOW);
- EEDI(LOW);
- EECS(LOW);
- }
-}
-
-static void sh7785lcr_macadrd(unsigned char *buf)
-{
- *PCI_MEMR = PCI_PROG;
-
- sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
-}
-
-static void sh7785lcr_eepewen(void)
-{
- *PCI_MEMR = PCI_PROG;
- mac_delay(TIME1);
- EECS(LOW);
- EECLK(LOW);
- EEDI(LOW);
- EECS(HIGH);
- mac_delay(TIME1);
-
- sh7785lcr_setcmd(MAC_EEP_EWEN);
- sh7785lcr_bitset(1);
- sh7785lcr_bitset(1);
- sh7785lcr_bitset(BIT_DUMMY);
- sh7785lcr_bitset(BIT_DUMMY);
- sh7785lcr_bitset(BIT_DUMMY);
- sh7785lcr_bitset(BIT_DUMMY);
-
- EECLK(LOW);
- EEDI(LOW);
- EECS(LOW);
- mac_delay(TIME1);
-}
-
-void mac_write(unsigned short *data)
-{
- mac_pci_setup();
- sh7785lcr_eepewen();
- sh7785lcr_macwrite(data);
-}
-
-void mac_read(void)
-{
- unsigned char data[6];
-
- mac_pci_setup();
- sh7785lcr_macadrd(data);
- printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n",
- data[0], data[1], data[2], data[3], data[4], data[5]);
-}
-
-int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
- unsigned char mac[6];
- char *s, *e;
-
- if (argc != 2)
- return cmd_usage(cmdtp);
-
- s = argv[1];
-
- for (i = 0; i < 6; i++) {
- mac[i] = s ? simple_strtoul(s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
- mac_write((unsigned short *)mac);
-
- return 0;
-}
-
-U_BOOT_CMD(
- setmac, 2, 1, do_set_mac,
- "write MAC address for RTL8110SCL",
- "\n"
- "setmac <mac address> - write MAC address for RTL8110SCL"
-);
-
-int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc != 1)
- return cmd_usage(cmdtp);
-
- mac_read();
-
- return 0;
-}
-
-U_BOOT_CMD(
- printmac, 1, 1, do_print_mac,
- "print MAC address for RTL8110",
- "\n"
- " - print MAC address for RTL8110"
-);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#include <common.h>
-#include <console.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/pci.h>
-
-#if defined(CONFIG_CPU_32BIT)
-#define NOCACHE_OFFSET 0x00000000
-#else
-#define NOCACHE_OFFSET 0xa0000000
-#endif
-#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET)
-#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET)
-#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET)
-
-#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET)
-
-static void test_pld(void)
-{
- printf("PLD version = %04x\n", readb(PLD_VERSR));
-}
-
-static void test_sm107(void)
-{
- printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID));
-}
-
-static void test_led(void)
-{
- printf("turn on LEDs 3, 5, 7, 9\n");
- writeb(0x55, PLD_LEDCR);
- mdelay(2000);
- printf("turn on LEDs 4, 6, 8, 10\n");
- writeb(0xaa, PLD_LEDCR);
- mdelay(2000);
- writeb(0x00, PLD_LEDCR);
-}
-
-static void test_dipsw(void)
-{
- printf("Please DIPSW set = B'0101\n");
- while (readb(PLD_SWSR) != 0x05) {
- if (ctrlc())
- return;
- }
- printf("Please DIPSW set = B'1010\n");
- while (readb(PLD_SWSR) != 0x0A) {
- if (ctrlc())
- return;
- }
- printf("DIPSW OK\n");
-}
-
-static void test_net(void)
-{
- unsigned long data;
-
- writel(0x80000000, 0xfe0401c0);
- data = readl(0xfe040220);
- if (data == 0x816910ec)
- printf("Ethernet OK\n");
- else
- printf("Ethernet NG, data = %08x\n", (unsigned int)data);
-}
-
-static void test_sata(void)
-{
- unsigned long data;
-
- writel(0x80000800, 0xfe0401c0);
- data = readl(0xfe040220);
- if (data == 0x35121095)
- printf("SATA OK\n");
- else
- printf("SATA NG, data = %08x\n", (unsigned int)data);
-}
-
-static void test_pci(void)
-{
- writel(0x80001800, 0xfe0401c0);
- printf("PCI CN1 ID = %08x\n", readl(0xfe040220));
-
- writel(0x80001000, 0xfe0401c0);
- printf("PCI CN2 ID = %08x\n", readl(0xfe040220));
-}
-
-int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *cmd;
-
- if (argc != 2)
- return cmd_usage(cmdtp);
-
- cmd = argv[1];
- switch (cmd[0]) {
- case 'a': /* all */
- test_pld();
- test_led();
- test_dipsw();
- test_sm107();
- test_net();
- test_sata();
- test_pci();
- break;
- case 'p': /* pld or pci */
- if (cmd[1] == 'l')
- test_pld();
- else
- test_pci();
- break;
- case 'l': /* led */
- test_led();
- break;
- case 'd': /* dipsw */
- test_dipsw();
- break;
- case 's': /* sm107 or sata */
- if (cmd[1] == 'm')
- test_sm107();
- else
- test_sata();
- break;
- case 'n': /* net */
- test_net();
- break;
- default:
- return cmd_usage(cmdtp);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- hwtest, 2, 1, do_hw_test,
- "hardware test for R0P7785LC0011RL board",
- "\n"
- "hwtest all - test all hardware\n"
- "hwtest pld - output PLD version\n"
- "hwtest led - turn on LEDs\n"
- "hwtest dipsw - test DIP switch\n"
- "hwtest sm107 - output SM107 version\n"
- "hwtest net - check RTL8110 ID\n"
- "hwtest sata - check SiI3512 ID\n"
- "hwtest pci - output PCI slot device ID"
-);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/pci.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-static struct pci_controller hose;
-void pci_init_board(void)
-{
- pci_sh7780_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_SH_32BIT)
-int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- /* clear ITLB */
- writel(0x00000004, 0xff000010);
-
- /* delete PMB for peripheral */
- writel(0, PMB_ADDR_BASE(0));
- writel(0, PMB_DATA_BASE(0));
- writel(0, PMB_ADDR_BASE(1));
- writel(0, PMB_DATA_BASE(1));
- writel(0, PMB_ADDR_BASE(2));
- writel(0, PMB_DATA_BASE(2));
-
- /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
- writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
- writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
- writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
- writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
-
- return 0;
-}
-
-U_BOOT_CMD(
- pmb, 1, 1, do_pmb,
- "pmb - PMB setting\n",
- "\n"
- " - PMB setting for all SDRAM mapping"
-);
-#endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := ulcb.o cpld.o
+ifdef CONFIG_SPL_BUILD
+obj-y := ../rcar-common/gen3-spl.o
+else
+obj-y := ulcb.o cpld.o ../rcar-common/common.o
+endif
return 0;
}
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- return -EINVAL;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
#ifdef CONFIG_MULTI_DTB_FIT
int board_fit_config_name_match(const char *name)
{
#include <common.h>
#include <dm.h>
#include <asm/io.h>
-#include <asm/arch/uart.h>
-#include <asm/arch/sdram_rk3036.h>
+#include <asm/arch-rockchip/uart.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
void get_ddr_config(struct rk3036_ddr_config *config)
{
--- /dev/null
+Get the Source and prebuild binary
+==================================
+
+ > mkdir ~/evb_rk3229
+ > cd ~/evb_rk3229
+ > git clone git://git.denx.de/u-boot.git
+ > git clone https://github.com/OP-TEE/optee_os.git
+ > git clone https://github.com/rockchip-linux/rkbin.git
+ > git clone https://github.com/rockchip-linux/rkdeveloptool.git
+
+Compile the OP-TEE
+===============
+
+ > cd optee_os
+ > make clean
+ > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x
+ Get tee.bin in this step, copy it to U-Boot root dir:
+ > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin
+
+Compile the U-Boot
+==================
+
+ > cd ../u-boot
+ > export CROSS_COMPILE=arm-linux-gnueabihf-
+ > export ARCH=arm
+ > make evb-rk3229_defconfig
+ > make
+ > make u-boot.itb
+
+ Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step.
+
+Compile the rkdeveloptool
+=======================
+ Follow instructions in latest README
+ > cd ../rkflashtool
+ > autoreconf -i
+ > ./configure
+ > make
+ > sudo make install
+
+ Get rkdeveloptool in you Host in this step.
+
+Both origin binaries and Tool are ready now, choose either option 1 or
+option 2 to deploy U-Boot.
+
+Package the image
+=================
+
+ > cd ../u-boot
+ > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img
+ > cat spl/u-boot-spl.bin >> idbloader.img
+
+ Get idbloader.img in this step.
+
+Flash the image to eMMC
+=======================
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+ > cd ..
+ > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin
+ > rkdeveloptool wl 64 u-boot/idbloader.img
+ > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
+ > rkdeveloptool rd
+
+Flash the image to SD card
+==========================
+ > dd if=u-boot/idbloader.img of=/dev/sdb seek=64
+ > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384
+
+You should be able to get U-Boot log message with OP-TEE boot info.
+
+For more detail, please reference to:
+http://opensource.rock-chips.com/wiki_Boot_option
#include <common.h>
#include <dm.h>
#include <asm/io.h>
-#include <asm/arch/uart.h>
+#include <asm/arch-rockchip/uart.h>
F: include/configs/evb_rk3399.h
F: configs/evb-rk3399_defconfig
F: configs/firefly-rk3399_defconfig
+
+NANOPC-T4
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/nanopc-t4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
+
+NANOPI-M4
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/nanopi-m4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+
+NANOPI-NEO4
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/nanopi-neo4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+
+ORANGEPI-RK3399
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/orangepi-rk3399_defconfig
+F: arch/arm/dts/rk3399-u-boot.dtsi
+F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
+
+ROCK-PI-4
+M: Akash Gajjar <akash@openedev.com>
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/rock-pi-4-rk3399_defconfig
+F: arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
+
+ROCKPRO64
+M: Akash Gajjar <akash@openedev.com>
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/rockpro64-rk3399_defconfig
+F: arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
#include <dm.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
#include <power/regulator.h>
#include <spl.h>
#include <common.h>
#include <asm/io.h>
#include <fdtdec.h>
-#include <asm/arch/grf_rv1108.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/grf_rv1108.h>
+#include <asm/arch-rockchip/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <dm.h>
#include <asm/io.h>
-#include <asm/arch/uart.h>
-#include <asm/arch/sdram_rk3036.h>
+#include <asm/arch-rockchip/uart.h>
+#include <asm/arch-rockchip/sdram_rk3036.h>
#include <asm/gpio.h>
void get_ddr_config(struct rk3036_ddr_config *config)
*/
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3368.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
#include <syscon.h>
int mach_cpu_init(void)
return -1;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#else
u32 ddr_size = msize << 20; /* DDR size in bytes */
u32 ddr_size_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currently any ddr size other than 256 is not supported
#endif
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[2].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+ const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+ LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+ LSDMR_WRC3 | LSDMR_CL3;
puts("\n SDRAM on Local Bus: ");
print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->lbcr = 0x00000000;
+ /* LB refresh timer prescal, 266MHz/32 */
+ lbc->mrtpr = 0x20000000;
+ /* LB sdram refresh timer, about 6us */
+ lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ /* 0x68636733; precharge all the banks */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ /* 0x48636733; auto refresh */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
udelay(100);
/* 0x58636733; mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
+++ /dev/null
-if TARGET_SHMIN
-
-config SYS_BOARD
- default "shmin"
-
-config SYS_CONFIG_NAME
- default "shmin"
-
-endif
+++ /dev/null
-SHMIN BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/shmin/
-F: include/configs/shmin.h
-F: configs/shmin_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2010 Nobuhiro Iwamatsu
-# Copyright (C) 2008 Renesas Solutions Corp.
-#
-# u-boot/board/shmin/Makefile
-#
-
-obj-y := shmin.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Use setting of original bootloader */
- rts
- nop
- .align 2
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 - 2010
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- *
- * board/shmin/shmin.c
- *
- * Copy board_flash_get_legacy() from board/freescale/m54455evb/m54455evb.c
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
- puts("BOARD: T-SH7706LAN ");
- if(readb(0xb0008006) == 0xab)
- puts("v2\n");
- else
- puts("v1\n");
- return 0;
-}
-
-int board_init(void)
-{
- writew(0x2980, BCR2);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return ne2k_register();
-}
-
-void led_set_state(unsigned short value)
-{
-
-}
-
-#if defined(CONFIG_FLASH_CFI_LEGACY)
-#include <flash.h>
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- int sect[] = CONFIG_SYS_ATMEL_SECT;
- int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
- int i, j, k;
-
- if (base != CONFIG_SYS_ATMEL_BASE)
- return 0;
-
- info->flash_id = 0x01000000;
- info->portwidth = 1;
- info->chipwidth = 1;
- info->buffer_size = 1;
- info->erase_blk_tout = 16384;
- info->write_tout = 2;
- info->buffer_write_tout = 5;
- info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
- info->cmd_reset = 0x00F0;
- info->interface = FLASH_CFI_X8;
- info->legacy_unlock = 0;
- info->manufacturer_id = (u16) ATM_MANUFACT;
- info->device_id = ATM_ID_LV040;
- info->device_id2 = 0;
- info->ext_addr = 0;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x0000;
- info->addr_unlock1 = 0x00000555;
- info->addr_unlock2 = 0x000002AA;
- info->name = "CFI conformant";
- info->size = 0;
- info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
- info->start[0] = base;
-
- for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
- info->size += sect[i] * sectsz[i];
- for (j = 0; j < sect[i]; j++, k++) {
- info->start[k + 1] = info->start[k] + sectsz[i];
- info->protect[k] = 0;
- }
- }
-
- return 1;
-}
-#endif /* CONFIG_FLASH_CFI_LEGACY */
config SYS_CONFIG_NAME
default "taurus"
+choice
+ prompt "Board Type AXM/TAURUS"
+ default BOARD_AXM
+
+config BOARD_AXM
+ bool "AXM board type"
+ help
+ Select this, if you want to build for AXM board.
+
+config BOARD_TAURUS
+ bool "TAURUS board type"
+ help
+ Select this, if you want to build for TAURUS board.
+
+endchoice
+
endif
/* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/
if (ram_size == 0x800) {
- printf("\n\r 64MB");
+ printf("\n\r 64MB\n");
sdramc_configure(AT91_SDRAMC_NC_9);
} else {
/* Size already initialized */
- printf("\n\r 128MB");
+ printf("\n\r 128MB\n");
}
}
#endif
return 0;
}
-/* FIXME gpio code here need to handle through DM_GPIO */
-#ifndef CONFIG_DM_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1);
-}
-#endif
-
#ifdef CONFIG_USB_GADGET_AT91
#include <linux/usb/at91_udc.h>
return 0;
}
-#ifndef CONFIG_DM_ETH
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
-#endif
- return rc;
-}
-#endif
-
#if !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_BOARD_AXM)
/*
imply CMD_PING
imply CLK_SIFIVE
imply CLK_SIFIVE_FU540_PRCI
+ imply CLK_SIFIVE_GEMGXL_MGMT
imply DOS_PARTITION
imply EFI_PARTITION
imply IP_DYN
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
#endif
#ifdef CONFIG_PMIC_STPMIC1
-int board_ddr_power_init(void)
+int board_ddr_power_init(enum ddr_type ddr_type)
{
struct udevice *dev;
+ bool buck3_at_1800000v = false;
int ret;
ret = uclass_get_device_by_driver(UCLASS_PMIC,
/* No PMIC on board */
return 0;
- /* VTT = Set LDO3 to sync mode */
- ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
- if (ret < 0)
- return ret;
-
- ret &= ~STPMIC1_LDO3_MODE;
- ret &= ~STPMIC1_LDO12356_VOUT_MASK;
- ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
-
- ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- ret);
- if (ret < 0)
- return ret;
-
- /* VDD_DDR = Set BUCK2 to 1.35V */
- ret = pmic_clrsetbits(dev,
- STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
- STPMIC1_BUCK_VOUT_MASK,
- STPMIC1_BUCK2_1350000V);
- if (ret < 0)
- return ret;
-
- /* Enable VDD_DDR = BUCK2 */
- ret = pmic_clrsetbits(dev,
- STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
- STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
- if (ret < 0)
- return ret;
-
- mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
- /* Enable VREF */
- ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
- STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
- if (ret < 0)
- return ret;
-
- mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
-
- /* Enable LDO3 */
- ret = pmic_clrsetbits(dev,
- STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
- if (ret < 0)
- return ret;
-
- mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+ switch (ddr_type) {
+ case STM32MP_DDR3:
+ /* VTT = Set LDO3 to sync mode */
+ ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+ if (ret < 0)
+ return ret;
+
+ ret &= ~STPMIC1_LDO3_MODE;
+ ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+ ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
+
+ ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ ret);
+ if (ret < 0)
+ return ret;
+
+ /* VDD_DDR = Set BUCK2 to 1.35V */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+ STPMIC1_BUCK_VOUT_MASK,
+ STPMIC1_BUCK2_1350000V);
+ if (ret < 0)
+ return ret;
+
+ /* Enable VDD_DDR = BUCK2 */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+ STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable VREF */
+ ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+ STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable VTT = LDO3 */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ break;
+
+ case STM32MP_LPDDR2:
+ case STM32MP_LPDDR3:
+ /*
+ * configure VDD_DDR1 = LDO3
+ * Set LDO3 to 1.8V
+ * + bypass mode if BUCK3 = 1.8V
+ * + normal mode if BUCK3 != 1.8V
+ */
+ ret = pmic_reg_read(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
+ if (ret < 0)
+ return ret;
+
+ if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
+ buck3_at_1800000v = true;
+
+ ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+ if (ret < 0)
+ return ret;
+
+ ret &= ~STPMIC1_LDO3_MODE;
+ ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+ ret |= STPMIC1_LDO3_1800000;
+ if (buck3_at_1800000v)
+ ret |= STPMIC1_LDO3_MODE;
+
+ ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ ret);
+ if (ret < 0)
+ return ret;
+
+ /* VDD_DDR2 : Set BUCK2 to 1.2V */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+ STPMIC1_BUCK_VOUT_MASK,
+ STPMIC1_BUCK2_1200000V);
+ if (ret < 0)
+ return ret;
+
+ /* Enable VDD_DDR1 = LDO3 */
+ ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable VDD_DDR2 =BUCK2 */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+ STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable VREF */
+ ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+ STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
+
+ break;
+
+ default:
+ break;
+ };
return 0;
}
S: Maintained
F: configs/bananapi_m64_defconfig
+BEELINK GS1
+M: Clément Péron <peron.clem@gmail.com>
+S: Maintained
+F: configs/beelink_gs1_defconfig
+F: arch/arm/dts/sun50i-h6-beelink-gs1.dts
+
COLOMBUS BOARD
M: Maxime Ripard <maxime.ripard@bootlin.com>
S: Maintained
F: configs/A20-Olimex-SOM204-EVB_defconfig
F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+OLIMEX TERES-I BOARD
+M: Jonas Smedegaard <dr@jones.dk>
+M: Icenowy Zheng <icenowy@aosc.io>
+S: Maintained
+F: configs/teres_i_defconfig
+
ORANGEPI LITE2 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
#include <i2c.h>
#include <miiphy.h>
-#include <mmc.h>
#include <netdev.h>
#include <usb.h>
#include <power/pmic.h>
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
-
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
- MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec1_pads[] = {
MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-
+ gpio_request(FEC1_RST_GPIO, "phy_rst");
gpio_direction_output(FEC1_RST_GPIO, 0);
udelay(500);
gpio_set_value(FEC1_RST_GPIO, 1);
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
}
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- /* Assume uSDHC3 emmc is always present */
- return 1;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
int board_early_init_f(void)
{
setup_iomux_uart();
void setup_lcd(void)
{
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+ gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
+ gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
/* Set Brightness to high */
gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
/* Set LCD enable to high */
* Author: Richard Hu <richard.hu@technexion.com>
*/
+#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx7/mx7-ddr.h>
+#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
+#include <fsl_esdhc.h>
#include <spl.h>
#if defined(CONFIG_SPL_BUILD)
void reset_cpu(ulong addr)
{
}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* Assume uSDHC3 emmc is always present */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
#endif
+++ /dev/null
-if TARGET_TWISTER
-
-config SYS_BOARD
- default "twister"
-
-config SYS_VENDOR
- default "technexion"
-
-config SYS_CONFIG_NAME
- default "twister"
-
-endif
+++ /dev/null
-TWISTER BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/technexion/twister/
-F: include/configs/twister.h
-F: configs/twister_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
-#
-# Based on ti/evm/Makefile
-
-obj-y := twister.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2009 TechNexion Ltd.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <i2c.h>
-#include <spl.h>
-#include <mmc.h>
-#include <asm/gpio.h>
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#include "twister.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Timing definitions for Ethernet Controller */
-static const u32 gpmc_smc911[] = {
- NET_GPMC_CONFIG1,
- NET_GPMC_CONFIG2,
- NET_GPMC_CONFIG3,
- NET_GPMC_CONFIG4,
- NET_GPMC_CONFIG5,
- NET_GPMC_CONFIG6,
-};
-
-static const u32 gpmc_XR16L2751[] = {
- XR16L2751_GPMC_CONFIG1,
- XR16L2751_GPMC_CONFIG2,
- XR16L2751_GPMC_CONFIG3,
- XR16L2751_GPMC_CONFIG4,
- XR16L2751_GPMC_CONFIG5,
- XR16L2751_GPMC_CONFIG6,
-};
-
-#ifdef CONFIG_USB_EHCI_OMAP
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-#endif
-
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- /* Chip select 1 and 3 are used for XR16L2751 UART controller */
- enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
- XR16L2751_UART1_BASE, GPMC_SIZE_16M);
-
- enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
- XR16L2751_UART2_BASE, GPMC_SIZE_16M);
-
- gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
-
- return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-int misc_init_r(void)
-{
- char *eth_addr;
- struct tam3517_module_info info;
- int ret;
-
- omap_die_id_display();
-
- eth_addr = env_get("ethaddr");
- if (eth_addr)
- return 0;
-
- TAM3517_READ_EEPROM(&info, ret);
- if (!ret)
- TAM3517_READ_MAC_FROM_EEPROM(&info);
-
- return 0;
-}
-#endif
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_TWISTER();
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_DRIVER_TI_EMAC
- davinci_emac_initialize();
-#endif
- /* init cs for extern lan */
- enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
- CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-#ifdef CONFIG_SMC911X
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#else
- return 0;
-#endif
-}
-
-#if defined(CONFIG_MMC_OMAP_HS)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * Do board specific preparation before SPL
- * Linux boot
- */
-void spl_board_prepare_for_linux(void)
-{
- /* init cs for extern lan */
- enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
- CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-}
-int spl_start_uboot(void)
-{
- int val = 0;
- if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
- gpio_direction_input(SPL_OS_BOOT_KEY);
- val = gpio_get_value(SPL_OS_BOOT_KEY);
- gpio_free(SPL_OS_BOOT_KEY);
- }
- return val;
-}
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2010 TechNexion Ltd.
- */
-
-#ifndef _TAM3517_H_
-#define _TAM3517_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "TAM3517 TWISTER Board",
- "NAND",
-};
-
-#define XR16L2751_GPMC_CONFIG1 0x00000000
-#define XR16L2751_GPMC_CONFIG2 0x001e1e01
-#define XR16L2751_GPMC_CONFIG3 0x00080300
-#define XR16L2751_GPMC_CONFIG4 0x1c091c09
-#define XR16L2751_GPMC_CONFIG5 0x04181f1f
-#define XR16L2751_GPMC_CONFIG6 0x00000FCF
-
-#define XR16L2751_UART1_BASE 0x21000000
-#define XR16L2751_UART2_BASE 0x23000000
-
-/* GPIO used to select between U-Boot and kernel */
-#define SPL_OS_BOOT_KEY 55
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_TWISTER() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_CKE0), (M0)) \
- MUX_VAL(CP(SDRC_CKE1), (M0)) \
- MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
- /*sdrc_strben_dly0*/\
- MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
- /*sdrc_strben_dly1*/\
- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
- MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
- /* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
- /* MMC */\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
- /* CardDetect */\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
- /* McBSP */\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
- \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\
- MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\
- /* UART */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \
- MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
- /* I2C */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
- /* McSPI */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
- \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
- /* CCDC */\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
- MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
- /* RMII */\
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
- MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
- MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
- /* HECC */\
- MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
- /* HSUSB */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
- /* HDQ */\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
- /* Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
- /* - GPIO30 */\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
- /* - VIO_1V8*/\
- MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
- \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
- /* JTAG */\
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
- MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
- /* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
- /* hsusb1_stp */ \
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
- /* hsusb1_clk */\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
- /* hsusb1_dir */\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
- /* hsusb1_nxt */\
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
- /* Die to Die */\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
-
-#endif
+++ /dev/null
-if TARGET_MT_VENTOUX
-
-config SYS_BOARD
- default "mt_ventoux"
-
-config SYS_VENDOR
- default "teejet"
-
-config SYS_CONFIG_NAME
- default "mt_ventoux"
-
-endif
+++ /dev/null
-MT_VENTOUX BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/teejet/mt_ventoux/
-F: include/configs/mt_ventoux.h
-F: configs/mt_ventoux_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
-#
-# Based on ti/evm/Makefile
-
-obj-y := mt_ventoux.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2009 TechNexion Ltd.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fpga.h>
-#include <video_fb.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/dss.h>
-#include <asm/arch/clock.h>
-#include <i2c.h>
-#include <spartan3.h>
-#include <asm/gpio.h>
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-#include "mt_ventoux.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BUZZER 140
-#define SPEAKER 141
-#define USB1_PWR 127
-#define USB2_PWR 149
-
-#ifndef CONFIG_FPGA
-#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
-#endif
-
-#define FPGA_RESET 62
-#define FPGA_PROG 116
-#define FPGA_CCLK 117
-#define FPGA_DIN 118
-#define FPGA_INIT 119
-#define FPGA_DONE 154
-
-#define LCD_PWR 138
-#define LCD_PON_PIN 139
-
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
-static struct {
- u32 xres;
- u32 yres;
-} panel_resolution[] = {
- { 480, 272 },
- { 800, 480 }
-};
-
-static struct panel_config lcd_cfg[] = {
- {
- .timing_h = PANEL_TIMING_H(40, 5, 2),
- .timing_v = PANEL_TIMING_V(8, 8, 2),
- .pol_freq = 0x00003000, /* Pol Freq */
- .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
- .panel_type = 0x01, /* TFT */
- .data_lines = 0x03, /* 24 Bit RGB */
- .load_mode = 0x02, /* Frame Mode */
- .panel_color = 0,
- .gfx_format = GFXFORMAT_RGB24_UNPACKED,
- },
- {
- .timing_h = PANEL_TIMING_H(20, 192, 4),
- .timing_v = PANEL_TIMING_V(2, 20, 10),
- .pol_freq = 0x00004000, /* Pol Freq */
- .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
- .panel_type = 0x01, /* TFT */
- .data_lines = 0x03, /* 24 Bit RGB */
- .load_mode = 0x02, /* Frame Mode */
- .panel_color = 0,
- .gfx_format = GFXFORMAT_RGB24_UNPACKED,
- }
-};
-#endif
-
-/* Timing definitions for FPGA */
-static const u32 gpmc_fpga[] = {
- FPGA_GPMC_CONFIG1,
- FPGA_GPMC_CONFIG2,
- FPGA_GPMC_CONFIG3,
- FPGA_GPMC_CONFIG4,
- FPGA_GPMC_CONFIG5,
- FPGA_GPMC_CONFIG6,
-};
-
-#ifdef CONFIG_USB_EHCI_HCD
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-#endif
-
-
-static inline void fpga_reset(int nassert)
-{
- gpio_set_value(FPGA_RESET, !nassert);
-}
-
-int fpga_pgm_fn(int nassert, int nflush, int cookie)
-{
- debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
-
- gpio_set_value(FPGA_PROG, !nassert);
-
- return nassert;
-}
-
-int fpga_init_fn(int cookie)
-{
- return !gpio_get_value(FPGA_INIT);
-}
-
-int fpga_done_fn(int cookie)
-{
- return gpio_get_value(FPGA_DONE);
-}
-
-int fpga_pre_config_fn(int cookie)
-{
- debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
-
- /* Setting GPIOs for programming Mode */
- gpio_request(FPGA_RESET, "FPGA_RESET");
- gpio_direction_output(FPGA_RESET, 1);
- gpio_request(FPGA_PROG, "FPGA_PROG");
- gpio_direction_output(FPGA_PROG, 1);
- gpio_request(FPGA_CCLK, "FPGA_CCLK");
- gpio_direction_output(FPGA_CCLK, 1);
- gpio_request(FPGA_DIN, "FPGA_DIN");
- gpio_direction_output(FPGA_DIN, 0);
- gpio_request(FPGA_INIT, "FPGA_INIT");
- gpio_direction_input(FPGA_INIT);
- gpio_request(FPGA_DONE, "FPGA_DONE");
- gpio_direction_input(FPGA_DONE);
-
- /* Be sure that signal are deasserted */
- gpio_set_value(FPGA_RESET, 1);
- gpio_set_value(FPGA_PROG, 1);
-
- return 0;
-}
-
-int fpga_post_config_fn(int cookie)
-{
- debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
-
- fpga_reset(true);
- udelay(100);
- fpga_reset(false);
-
- return 0;
-}
-
-/* Write program to the FPGA */
-int fpga_wr_fn(int nassert_write, int flush, int cookie)
-{
- gpio_set_value(FPGA_DIN, nassert_write);
-
- return nassert_write;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- gpio_set_value(FPGA_CCLK, assert_clk);
-
- return assert_clk;
-}
-
-xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
- fpga_pre_config_fn,
- fpga_pgm_fn,
- fpga_clk_fn,
- fpga_init_fn,
- fpga_done_fn,
- fpga_wr_fn,
- fpga_post_config_fn,
-};
-
-xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
- (void *)&mt_ventoux_fpga_fns, 0);
-
-/* Initialize the FPGA */
-static void mt_ventoux_init_fpga(void)
-{
- fpga_pre_config_fn(0);
-
- /* Setting CS1 for FPGA access */
- enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
- FPGA_BASE_ADDR, GPMC_SIZE_128M);
-
- fpga_init();
- fpga_add(fpga_xilinx, &fpga);
-}
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- mt_ventoux_init_fpga();
-
- /* GPIO_140: speaker #mute */
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
- /* GPIO_141: Buzz Hi */
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
-
- /* Turning off the buzzer */
- gpio_request(BUZZER, "BUZZER_MUTE");
- gpio_request(SPEAKER, "SPEAKER");
- gpio_direction_output(BUZZER, 0);
- gpio_direction_output(SPEAKER, 0);
-
- /* Activate USB power */
- gpio_request(USB1_PWR, "USB1_PWR");
- gpio_request(USB2_PWR, "USB2_PWR");
- gpio_direction_output(USB1_PWR, 1);
- gpio_direction_output(USB2_PWR, 1);
-
- return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-int misc_init_r(void)
-{
- char *eth_addr;
- struct tam3517_module_info info;
- int ret;
-
- TAM3517_READ_EEPROM(&info, ret);
- omap_die_id_display();
-
- if (ret)
- return 0;
- eth_addr = env_get("ethaddr");
- if (!eth_addr)
- TAM3517_READ_MAC_FROM_EEPROM(&info);
-
- TAM3517_PRINT_SOM_INFO(&info);
- return 0;
-}
-#endif
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_MT_VENTOUX();
-}
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int board_eth_init(bd_t *bis)
-{
- davinci_emac_initialize();
- return 0;
-}
-
-#if defined(CONFIG_MMC_OMAP_HS) && \
- !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
-int board_video_init(void)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- struct panel_config *panel = &lcd_cfg[0];
- char *s;
- u32 index = 0;
-
- void *fb;
-
- fb = (void *)0x88000000;
-
- s = env_get("panel");
- if (s) {
- index = simple_strtoul(s, NULL, 10);
- if (index < ARRAY_SIZE(lcd_cfg))
- panel = &lcd_cfg[index];
- else
- return 0;
- }
-
- panel->frame_buffer = fb;
- printf("Panel: %dx%d\n", panel_resolution[index].xres,
- panel_resolution[index].yres);
- panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
- (panel_resolution[index].xres - 1);
-
- gpio_request(LCD_PWR, "LCD Power");
- gpio_request(LCD_PON_PIN, "LCD Pon");
- gpio_direction_output(LCD_PWR, 0);
- gpio_direction_output(LCD_PON_PIN, 1);
-
-
- setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
- setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
-
- omap3_dss_panel_config(panel);
- omap3_dss_enable();
-
- return 0;
-}
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Stefano Babic <sbabic@denx.de>
- *
- * Author: Hardy Weng <hardy.weng@technexion.com>
- *
- * Copyright (C) 2010 TechNexion Ltd.
- */
-
-#ifndef _MT_VENTOUX_H_
-#define _MT_VENTOUX_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "Teejet MT_VENTOUX Board",
- "NAND",
-};
-
-/* FPGA CS1 configuration */
-#define FPGA_GPMC_CONFIG1 0x00001200
-#define FPGA_GPMC_CONFIG2 0x00161f00
-#define FPGA_GPMC_CONFIG3 0x00040400
-#define FPGA_GPMC_CONFIG4 0x120c1f08
-#define FPGA_GPMC_CONFIG5 0x001e161f
-#define FPGA_GPMC_CONFIG6 0x96080fcf
-
-#define FPGA_BASE_ADDR 0x20000000
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_MT_VENTOUX() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_CKE0), (M0)) \
- MUX_VAL(CP(SDRC_CKE1), (M0)) \
- MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
- /* GPIO 55 : NFS */\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
- MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \
- /*GPIO_62: FPGA_RESET */ \
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
- /* GPIO_64*/ \
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
- /* CAMERA */\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
- /* MMC */\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
- /* GPIO_126: CardDetect */\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
- /*GPIO_128 */ \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
- /* GPIO_138: LCD_ENVD */\
- MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \
- /* GPIO_139: LCD_PON */\
- /* McBSP */\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) \
- /* GPIO_116: FPGA_PROG */ \
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
- /* GPIO_117: FPGA_CCLK */ \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
- /* GPIO_118: FPGA_DIN */ \
- MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
- /* GPIO_119: FPGA_INIT */ \
- \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \
- /*GPIO_152: Ignition Sense */ \
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \
- /*GPIO_153: Power Button Sense */ \
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \
- /* GPIO_154: FPGA_DONE */ \
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) \
- /* GPIO_155: CA8_irq */ \
- /* UART */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
- /* GPIO_149: USB status 2 */\
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
- /* GPIO_150: USB status 1 */\
- \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \
- /* gpt9_pwm */\
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \
- /* gpt10_pwm */\
- MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \
- /* gpt8_pwm */\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \
- /* gpt11_pwm */\
- \
- MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \
- /*GPIO_163 : TS_PENIRQ*/ \
- MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) \
- /*GPIO_164 : MMC */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
- /* I2C */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
- /* McSPI */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
- \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \
- /* CCDC */\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \
- /* GPIO94 */\
- MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \
- /* GPIO95: #Enable Output */\
- MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \
- /* GPIO 99: #SOM_PWR_OFF */\
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \
- /* GPIO_100: #power out */\
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \
- /* GPIO_102 */\
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \
- /* RMII */\
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
- MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
- MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
- /* HECC */\
- MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
- /* HSUSB */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
- /* HDQ */\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
- /* GPIO_170: auto update */\
- /* Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
- /* - GPIO30 */\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
- MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
- \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \
- /* gpio_10 */\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
- /* JTAG */\
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
- MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
- /* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
- /* hsusb1_stp */ \
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
- /* hsusb1_clk */\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \
- /* gpio_24 */\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
- /* gpio_26 */\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
- /* gpio_29 */\
- /* Die to Die */\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
-
-#endif
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
+#include <asm/arch-rockchip/timer.h>
#include <syscon.h>
int mach_cpu_init(void)
default 0x2000
config ENV_OFFSET
- default 0x3c000 if ENV_IS_IN_SPI_FLASH
+ default 0x3fc000 if ENV_IS_IN_SPI_FLASH
endif
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/setup.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3399.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/grf_rk3399.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/periph.h>
#include <power/regulator.h>
#include <u-boot/sha256.h>
};
static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
configure_module_pin_mux(mii1_pin_mux);
}
/* Beaglebone LT pinmux */
- configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
configure_module_pin_mux(nand_pin_mux);
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074BE4,
.temp_alert_config = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E004008,
+ .emif_ddr_phy_ctlr_1 = 0x00048008,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00000066,
.emif_ddr_ext_phy_ctrl_3 = 0x00000091,
bool "TI K3 based AM654 EVM running on A53"
select ARM64
select SOC_K3_AM6
+ select SYS_DISABLE_DCACHE_OPS
config TARGET_AM654_R5_EVM
bool "TI K3 based AM654 EVM running on R5"
{ 71, MODE(0) }, /* MMC1POW TP124 */
/* EMAC */
- { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
- { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
+ { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
{ 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
+ { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
+ { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
{ 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
- { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
- { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
- { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
- { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
+ { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
{ 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
+ { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
+ { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
+ { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
+ { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
{ 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
- { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
- { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
/* MDIO */
- { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
{ 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
+ { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
/* PWM */
{ 73, MODE(4) }, /* SOC_EHRPWM3A */
{ 135, MODE(0) }, /* SOC_QSPI_CSN0 */
/* EMAC */
- { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
- { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
+ { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
{ 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
+ { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
+ { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
{ 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
- { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
- { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
- { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
- { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
+ { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
{ 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
+ { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
+ { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
+ { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
+ { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
{ 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
- { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
- { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
/* MDIO */
- { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
{ 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
+ { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
{ MAX_PIN_N, }
};
Colibri iMX6ULL
M: Stefan Agner <stefan.agner@toradex.com>
-M: Toradex ARM Support <support.arm@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Toradex AG
+ * Copyright (C) 2018-2019 Toradex AG
*/
#include <common.h>
+
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
-#include <common.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
#include <fdt_support.h>
-#include <fsl_esdhc.h>
#include <imx_thermal.h>
#include <jffs2/load_kernel.h>
#include <linux/sizes.h>
-#include <mmc.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <netdev.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
+
#include "../common/tdx-common.h"
+#include "../common/tdx-cfg-block.h"
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm)
-
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
PAD_CTL_DSE_48ohm)
+#define MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR 0x2290040
+
#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
-#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
-
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
-static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#ifdef CONFIG_FSL_ESDHC
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-#endif
-
-static iomux_v3_cfg_t const usb_cdet_pads[] = {
- MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
#ifdef CONFIG_NAND_MXS
-static iomux_v3_cfg_t const gpmi_pads[] = {
- MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
- MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
-};
-
static void setup_gpmi_nand(void)
{
- imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
-
setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
}
-#endif
+#endif /* CONFIG_NAND_MXS */
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
#endif
#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec2_pads[] = {
- MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
- MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_fec(void)
-{
- imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
-}
-#endif
-
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
-
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
- {USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(USDHC1_CD_GPIO);
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
-
- /* USDHC1 is mmc0 */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
- ARRAY_SIZE(usdhc1_pads));
- gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
- gpio_direction_input(USDHC1_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) than supported by the board\n", i + 1);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_FEC_MXC
-
static int setup_fec(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
- setup_iomux_fec();
-
/* provide the PHY clock from the i.MX 6 */
ret = enable_fec_anatop_clock(1, ENET_50MHZ);
if (ret)
return ret;
- /* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */
+ /* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+ /* give new Ethernet PHY power save mode circuitry time to settle */
+ mdelay(300);
+
return 0;
}
phydev->drv->config(phydev);
return 0;
}
-#endif
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-
- return 0;
-}
+#endif /* CONFIG_FEC_MXC */
int board_init(void)
{
setup_lcd();
#endif
-#ifdef CONFIG_USB_EHCI_MX6
- imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
- gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
-#endif
-
return 0;
}
int board_late_init(void)
{
- int minc, maxc;
-
- if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL)
+#ifdef CONFIG_TDX_CFG_BLOCK
+ /*
+ * If we have a valid config block and it says we are a module with
+ * Wi-Fi/Bluetooth make sure we use the -wifi device tree.
+ */
+ if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT ||
+ tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT)
env_set("variant", "-wifi");
+#endif
+
+ /*
+ * Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the
+ * SOC to request for a lower voltage during sleep. This is necessary
+ * because the voltage is changing too slow for the SOC to wake up
+ * properly.
+ */
+ __raw_writel(0x8080, MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR);
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
}
#endif
-#ifdef CONFIG_USB_EHCI_MX6
-static iomux_v3_cfg_t const usb_otg2_pads[] = {
- MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_ehci_hcd_init(int port)
-{
- switch (port) {
- case 0:
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
- ARRAY_SIZE(usb_otg2_pads));
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-int board_usb_phy_mode(int port)
-{
- switch (port) {
- case 0:
- if (gpio_get_value(USB_CDET_GPIO))
- return USB_INIT_DEVICE;
- else
- return USB_INIT_HOST;
- case 1:
- default:
- return USB_INIT_HOST;
- }
-}
-#endif
-
static struct mxc_serial_platdata mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = 1,
Colibri iMX7
M: Stefan Agner <stefan.agner@toradex.com>
-M: Toradex ARM Support <support.arm@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
Colibri VFxx
M: Stefan Agner <stefan.agner@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
-W: https://www.toradex.com/community
+W: https://www.toradex.com/community
S: Maintained
F: board/toradex/colibri_vf/
F: include/configs/colibri_vf.h
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (c) 2016 Toradex, Inc.
+ * Copyright (c) 2016-2019 Toradex, Inc.
*/
#include <common.h>
#include "tdx-cfg-block.h"
-#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6)
+#if defined(CONFIG_TARGET_APALIS_IMX6) || \
+ defined(CONFIG_TARGET_COLIBRI_IMX6) || \
+ defined(CONFIG_TARGET_COLIBRI_IMX8QXP)
#include <asm/arch/sys_proto.h>
#else
#define is_cpu_type(cpu) (0)
[34] = "Apalis TK1 2GB",
[35] = "Apalis iMX6 Dual 1GB IT",
[36] = "Colibri iMX6ULL 256MB",
- [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / Bluetooth",
- [38] = "Colibri iMX8X",
+ [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT",
+ [38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
[39] = "Colibri iMX7 Dual 1GB (eMMC)",
- [40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT",
+ [40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT",
[41] = "Colibri iMX7 Dual 512MB EPDC",
[42] = "Apalis TK1 4GB",
+ [43] = "Colibri T20 512MB IT SETEK",
+ [44] = "Colibri iMX6ULL 512MB IT",
+ [45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth",
+ [46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
+ [47] = "Apalis iMX8 QuadMax 4GB IT",
+ [48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT",
+ [49] = "Apalis iMX8 QuadPlus 2GB",
+ [50] = "Colibri iMX8 QuadXPlus 2GB IT",
+ [51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth",
+ [52] = "Colibri iMX8 DualX 1GB",
};
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
char it = 'n';
int len;
+ /* Unknown module by default */
+ tdx_hw_tag.prodid = 0;
+
if (cpu_is_pxa27x())
sprintf(message, "Is the module the 312 MHz version? [y/N] ");
else
soc = env_get("soc");
if (!strcmp("mx6", soc)) {
-#ifdef CONFIG_MACH_TYPE
- if (it == 'y' || it == 'Y')
+#ifdef CONFIG_TARGET_APALIS_IMX6
+ if (it == 'y' || it == 'Y') {
if (is_cpu_type(MXC_CPU_MX6Q))
tdx_hw_tag.prodid = APALIS_IMX6Q_IT;
else
tdx_hw_tag.prodid = APALIS_IMX6D_IT;
- else
+ } else {
if (is_cpu_type(MXC_CPU_MX6Q))
tdx_hw_tag.prodid = APALIS_IMX6Q;
else
tdx_hw_tag.prodid = APALIS_IMX6D;
-#else
- if (it == 'y' || it == 'Y')
+ }
+#elif CONFIG_TARGET_COLIBRI_IMX6
+ if (it == 'y' || it == 'Y') {
if (is_cpu_type(MXC_CPU_MX6DL))
tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
- else
+ else if (is_cpu_type(MXC_CPU_MX6SOLO))
tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
- else
+ } else {
if (is_cpu_type(MXC_CPU_MX6DL))
tdx_hw_tag.prodid = COLIBRI_IMX6DL;
- else
+ else if (is_cpu_type(MXC_CPU_MX6SOLO))
tdx_hw_tag.prodid = COLIBRI_IMX6S;
-#endif /* CONFIG_MACH_TYPE */
- } else if (!strcmp("imx7d", soc)) {
+ }
+#elif CONFIG_TARGET_COLIBRI_IMX6ULL
+ char wb = 'n';
+
+ sprintf(message, "Does the module have Wi-Fi / Bluetooth? " \
+ "[y/N] ");
+ len = cli_readline(message);
+ wb = console_buffer[0];
+ if (it == 'y' || it == 'Y') {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
+ } else {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT;
+ else
+ tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
+ }
+#endif
+ } else if (!strcmp("imx7d", soc))
tdx_hw_tag.prodid = COLIBRI_IMX7D;
- } else if (!strcmp("imx7s", soc)) {
+ else if (!strcmp("imx7s", soc))
tdx_hw_tag.prodid = COLIBRI_IMX7S;
- } else if (!strcmp("tegra20", soc)) {
+ else if (is_cpu_type(MXC_CPU_IMX8QXP))
+ tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT;
+ else if (!strcmp("tegra20", soc)) {
if (it == 'y' || it == 'Y')
if (gd->ram_size == 0x10000000)
tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ;
else
tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
+ }
#ifdef CONFIG_MACH_TYPE
- } else if (!strcmp("tegra30", soc)) {
+ else if (!strcmp("tegra30", soc)) {
if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
if (it == 'y' || it == 'Y')
tdx_hw_tag.prodid = APALIS_T30_IT;
else
tdx_hw_tag.prodid = COLIBRI_T30;
}
+ }
#endif /* CONFIG_MACH_TYPE */
- } else if (!strcmp("tegra124", soc)) {
+ else if (!strcmp("tegra124", soc)) {
tdx_hw_tag.prodid = APALIS_TK1_2GB;
} else if (!strcmp("vf500", soc)) {
if (it == 'y' || it == 'Y')
tdx_hw_tag.prodid = COLIBRI_VF61_IT;
else
tdx_hw_tag.prodid = COLIBRI_VF61;
- } else {
+ }
+
+ if (!tdx_hw_tag.prodid) {
printf("Module type not detectable due to unknown SoC\n");
return -1;
}
tdx_hw_tag.ver_minor = console_buffer[2] - '0';
tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
- if (cpu_is_pxa27x() && (tdx_hw_tag.ver_major == 1))
+ if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1)
tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ -
COLIBRI_PXA270_V1_312MHZ);
* On NAND devices, recreation is only allowed if the page is
* empty (config block invalid...)
*/
- printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
+ printf("NAND erase block %d need to be erased before creating" \
+ " a Toradex config block\n",
CONFIG_TDX_CFG_BLOCK_OFFSET /
get_nand_dev_by_index(0)->erasesize);
goto out;
* On NOR devices, recreation is only allowed if the sector is
* empty and write protection is off (config block invalid...)
*/
- printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
+ printf("NOR sector at offset 0x%02x need to be erased and " \
+ "unprotected before creating a Toradex config block\n",
CONFIG_TDX_CFG_BLOCK_OFFSET);
goto out;
#else
COLIBRI_PXA270_V1_520MHZ,
COLIBRI_PXA320,
COLIBRI_PXA300,
- COLIBRI_PXA310,
+ COLIBRI_PXA310, /* 5 */
COLIBRI_PXA320_IT,
COLIBRI_PXA300_XT,
COLIBRI_PXA270_312MHZ,
COLIBRI_PXA270_520MHZ,
- COLIBRI_VF50, /* not currently on sale */
- COLIBRI_VF61,
+ COLIBRI_VF50, /* 10 */
+ COLIBRI_VF61, /* not currently on sale */
COLIBRI_VF61_IT,
COLIBRI_VF50_IT,
COLIBRI_IMX6S,
- COLIBRI_IMX6DL,
+ COLIBRI_IMX6DL, /* 15 */
COLIBRI_IMX6S_IT,
COLIBRI_IMX6DL_IT,
+ /* 18 */
+ /* 19 */
COLIBRI_T20_256MB = 20,
COLIBRI_T20_512MB,
COLIBRI_T20_512MB_IT,
COLIBRI_T30,
COLIBRI_T20_256MB_IT,
- APALIS_T30_2GB,
+ APALIS_T30_2GB, /* 25 */
APALIS_T30_1GB,
APALIS_IMX6Q,
APALIS_IMX6Q_IT,
APALIS_IMX6D,
- COLIBRI_T30_IT,
+ COLIBRI_T30_IT, /* 30 */
APALIS_T30_IT,
COLIBRI_IMX7S,
COLIBRI_IMX7D,
APALIS_TK1_2GB,
- APALIS_IMX6D_IT,
+ APALIS_IMX6D_IT, /* 35 */
COLIBRI_IMX6ULL,
- APALIS_IMX8QM, /* 37 */
- COLIBRI_IMX8X,
+ APALIS_IMX8QM_WIFI_BT_IT,
+ COLIBRI_IMX8QXP_WIFI_BT_IT,
COLIBRI_IMX7D_EMMC,
COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */
COLIBRI_IMX7D_EPDC,
- APALIS_TK1_4GB,
+ APALIS_TK1_4GB, /* not currently on sale */
+ COLIBRI_T20_512MB_IT_SETEK,
+ COLIBRI_IMX6ULL_IT,
+ COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
+ APALIS_IMX8QXP_WIFI_BT_IT,
+ APALIS_IMX8QM_IT,
+ APALIS_IMX8QP_WIFI_BT,
+ APALIS_IMX8QP,
+ COLIBRI_IMX8QXP_IT, /* 50 */
+ COLIBRI_IMX8DX_WIFI_BT,
+ COLIBRI_IMX8DX,
};
extern const char * const toradex_modules[];
reg32 = 0xff000000;
#endif
if (clk->spmr & SPMR_CKID) {
- /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
+ /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR
* fields accordingly */
reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
int cs;
/* during size detection, set up the max DDRLAW size */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE;
im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
/* set CS bounds to maximum size */
for(cs = 0; cs < 4; ++cs) {
set_cs_bounds(cs,
- CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+ CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS),
DDR_MAX_SIZE_PER_CS);
set_cs_config(cs, INITIAL_CS_CONFIG);
debug("\nDetecting Bank%d\n", cs);
bank_size = get_ddr_bank_size(cs,
- (long *)(CONFIG_SYS_DDR_BASE + size));
+ (long *)(CONFIG_SYS_SDRAM_BASE + size));
size += bank_size;
debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
/* set OR0 and BR0 */
- set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
- (-(total_size) & OR_GPCM_AM));
+ set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 |
+ OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM));
set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
(BR_MS_GPCM | BR_PS_32 | BR_V));
#include <dm.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
#include <power/regulator.h>
#include <spl.h>
--- /dev/null
+if TARGET_DART_6UL
+
+config SYS_BOARD
+ default "dart_6ul"
+
+config SYS_VENDOR
+ default "variscite"
+
+config SYS_CONFIG_NAME
+ default "dart_6ul"
+
+endif
--- /dev/null
+MX6UL_DART BOARD
+M: Parthiban Nallathambi <parthitce@gmail.com>
+S: Maintained
+F: arch/arm/dts/imx6ull-dart-6ul.dts
+F: arch/arm/dts/imx6ull-dart-6ul.dtsi
+F: board/variscite/dart_6ul/
+F: configs/variscite_dart6ul_defconfig
+F: include/configs/dart_6ul.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := dart_6ul.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
--- /dev/null
+How to use U-Boot on variscite DART-6UL Evaluation Kit
+------------------------------------------------------
+
+- Configure and build U-Boot for DART-6UL iMX6ULL:
+
+ $ make mrproper
+ $ make variscite_dart6ul_defconfig
+ $ make
+
+ This will generate SPL and u-boot-dtb.img images.
+
+Boot from MMC/SD:
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
+
+ $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+ $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Boot mode settings:
+
+ Boot switch position: SW1 -> 0
+ SW2 -> 0
+
+Boot from eMMC:
+- if bootpart is not enabled by default, to enable under Linux
+ echo 0 >/sys/block/mmcblk1boot0/force_ro
+ mmc bootpart enable 1 1 /dev/mmcblk1boot0
+
+- Flash the SPL and u-boot-dtb.img to mmcblk1boot0
+ $ sudo dd if=SPL of=/dev/mmcblk1boot0 bs=1k seek=1; sync
+ $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk1boot0 bs=1k seek=69; sync
+
+- Boot mode settings:
+
+ Boot switch position: SW1 -> 0
+ SW2 -> 1
+
+- Connect the Serial cable to UART0 and the PC for the console.
+
+- Insert the micro SD card in the board and power it up.
+
+- U-Boot messages should come up.
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2019 Variscite Ltd.
+ * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <linux/bitops.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+#ifdef CONFIG_NAND_MXS
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+static iomux_v3_cfg_t const nand_pads[] = {
+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+
+ clrbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+ /*
+ * config gpmi and bch clock to 100 MHz
+ * bch/gpmi select PLL2 PFD2 400M
+ * 100M = 400M / 4
+ */
+ clrbits_le32(&mxc_ccm->cscmr1,
+ MXC_CCM_CSCMR1_BCH_CLK_SEL |
+ MXC_CCM_CSCMR1_GPMI_CLK_SEL);
+ clrsetbits_le32(&mxc_ccm->cscdr1,
+ MXC_CCM_CSCDR1_BCH_PODF_MASK |
+ MXC_CCM_CSCDR1_GPMI_PODF_MASK,
+ (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+ (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
+ PAD_CTL_SRE_FAST)
+#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
+ PAD_CTL_ODE)
+/*
+ * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
+ * be used for ENET1 or ENET2, cannot be used for both.
+ */
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+ MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+ MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec(int fec_id)
+{
+ if (fec_id == 0)
+ imx_iomux_v3_setup_multiple_pads(fec1_pads,
+ ARRAY_SIZE(fec1_pads));
+ else
+ imx_iomux_v3_setup_multiple_pads(fec2_pads,
+ ARRAY_SIZE(fec2_pads));
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+ ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+ CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+
+#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
+ /* USB Ethernet Gadget */
+ usb_eth_initialize(bis);
+#endif
+ return ret;
+}
+
+static int setup_fec(int fec_id)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ if (fec_id == 0) {
+ /*
+ * Use 50M anatop loopback REF_CLK1 for ENET1,
+ * clear gpr1[13], set gpr1[17].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+ } else {
+ /*
+ * Use 50M anatop loopback REF_CLK2 for ENET2,
+ * clear gpr1[14], set gpr1[18].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+ }
+
+ ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ enable_enet_clk(1);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
+ * 50 MHz RMII clock mode.
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif /* CONFIG_FEC_MXC */
+
+int board_early_init_f(void)
+{
+ setup_iomux_fec(CONFIG_FEC_ENET_DEV);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Variscite DART-6UL Evaluation Kit\n");
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2019 Variscite Ltd.
+ * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <fsl_esdhc.h>
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000008,
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x414C0158,
+ .p0_mprddlctl = 0x40403A3A,
+ .p0_mpwrdlctl = 0x40405A56,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+ /* Enable Audio Clock for SOM codec */
+ writel(0x01130100, (long *)CCM_CCOSR);
+}
+
+static void spl_dram_init(void)
+{
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifndef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+ {
+ .esdhc_base = USDHC1_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+#ifndef CONFIG_NAND_MXS
+ {
+ .esdhc_base = USDHC2_BASE_ADDR,
+ .max_bus_width = 8,
+ },
+#endif
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc1_pads);
+ usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+#ifndef CONFIG_NAND_MXS
+ case 1:
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+#endif
+ default:
+ printf("Warning - USDHC%d controller not supporting\n",
+ i + 1);
+ return 0;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+
+ /* setup GP timer */
+ timer_init();
+
+ setup_iomux_uart();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+ (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
*/
__udelay(50000);
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
out_be32(&im->ddr.csbnds[0].csbnds,
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
CSBNDS_EA));
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
/* now check the real size */
disable_addr_trans ();
- msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+ msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize);
enable_addr_trans ();
#endif
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
- out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
- out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+ out_be32(&lbc->lbcr, 0x00040000);
+ out_be32(&lbc->mrtpr, 0x20000000);
sync();
/* return total bus SDRAM size(bytes) -- DDR */
#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
#define REV_DETECTION IMX_GPIO_NR(2, 28)
+/* Speed defined in Kconfig is only applicable when not using DM_I2C. */
+#ifdef CONFIG_DM_I2C
+#define I2C1_SPEED_NON_DM 0
+#define I2C2_SPEED_NON_DM 0
+#else
+#define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
+#define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
+#endif
+
static bool with_pmic;
int dram_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#if defined(CONFIG_VIDEO_IPUV3)
- setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+ setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
if (is_mx6dq() || is_mx6dqp()) {
- setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info);
- setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info);
+ setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
+ setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
} else {
- setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
- setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
+ setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
+ setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
}
setup_display();
#include <asm/io.h>
#include <common.h>
#include <asm/arch/crm_regs.h>
-#include <usb.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
return 0;
}
-int board_usb_phy_mode(int port)
-{
- return USB_INIT_DEVICE;
-}
-
int board_late_init(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
config CMD_BOOTI
bool "booti"
- depends on ARM64
+ depends on ARM64 || RISCV
default y
help
Boot an AArch64 Linux Kernel image from memory.
Enable the 'cls' command which clears the screen contents
on video frame buffer.
-config CMD_DISPLAY
- bool "Enable the 'display' command, for character displays"
- help
- (this needs porting to driver model)
- This enables the 'display' command which allows a string to be
- displayed on a simple board-specific display. Implement
- display_putc() to use it.
-
config CMD_EFIDEBUG
bool "efidebug - display/configure UEFI environment"
depends on EFI_LOADER
+ select EFI_DEVICE_PATH_TO_TEXT
default n
help
Enable the 'efidebug' command which provides a subset of UEFI
config CMD_UBI
tristate "Enable UBI - Unsorted block images commands"
- select CRC32
select MTD_UBI
help
UBI is a software layer above MTD layer which admits use of LVM-like
tristate "Enable UBIFS - Unsorted block images filesystem commands"
depends on CMD_UBI
default y if CMD_UBI
- select CRC32
select LZO
help
UBIFS is a file system for flash devices which works on top of UBI.
ifdef CONFIG_POST
obj-$(CONFIG_CMD_DIAG) += diag.o
endif
-obj-$(CONFIG_CMD_DISPLAY) += display.o
obj-$(CONFIG_CMD_DTIMG) += dtimg.o
obj-$(CONFIG_CMD_ECHO) += echo.o
obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
print_eths();
#endif
print_baudrate();
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
print_num("TLB addr", gd->arch.tlb_addr);
#endif
print_num("relocaddr", gd->relocaddr);
#include <common.h>
#include <command.h>
+#include <hexdump.h>
#include <malloc.h>
#include <mapmem.h>
#include <linux/ctype.h>
str_ptr += 2;
}
*str_ptr = '\0';
- setenv(varname, str_output);
+ env_set(varname, str_output);
free(str_output);
}
-void decode_hexstring(char *hexstr, u8 *result)
-{
- int i;
- int acc = 0;
-
- for (i = 0; i < strlen(hexstr); ++i) {
- char d = hexstr[i];
- int value;
-
- if (isdigit(d))
- value = (d - '0');
- else
- value = (islower(d) ? toupper(d) : d) - 'A' + 10;
-
- if (i % 2 == 0) {
- acc = value * 16;
- } else {
- result[i / 2] = acc + value;
- acc = 0;
- }
- }
-}
-
void read_from_env_var(char *varname, u8 *result)
{
char *str_value;
- str_value = getenv(varname);
+ str_value = env_get(varname);
if (str_value)
- decode_hexstring(str_value, result);
+ hex2bin(result, str_value, strlen(str_value) / 2);
else
- decode_hexstring(varname, result);
+ hex2bin(result, varname, strlen(varname) / 2);
}
void read_from_mem(ulong addr, u8 *result, ulong len)
*/
#include <common.h>
-#include <bootm.h>
#include <charset.h>
#include <command.h>
#include <dm.h>
#include <linux/libfdt_env.h>
#include <mapmem.h>
#include <memalign.h>
-#include <asm/global_data.h>
#include <asm-generic/sections.h>
-#include <asm-generic/unaligned.h>
#include <linux/linkage.h>
DECLARE_GLOBAL_DATA_PTR;
static struct efi_device_path *bootefi_image_path;
static struct efi_device_path *bootefi_device_path;
-/*
- * Allow unaligned memory access.
- *
- * This routine is overridden by architectures providing this feature.
- */
-void __weak allow_unaligned(void)
-{
-}
-
/*
* Set the load options of an image from an environment variable.
*
/**
* efi_install_fdt() - install fdt passed by a command argument
+ *
+ * If fdt_opt is available, the device tree located at that memory address will
+ * will be installed as configuration table, otherwise the device tree located
+ * at the address indicated by environment variable fdtcontroladdr will be used.
+ *
+ * On architectures (x86) using ACPI tables device trees shall not be installed
+ * as configuration table.
+ *
* @fdt_opt: pointer to argument
* Return: status code
- *
- * If specified, fdt will be installed as configuration table,
- * otherwise no fdt will be passed.
*/
static efi_status_t efi_install_fdt(const char *fdt_opt)
{
static efi_status_t do_bootefi_exec(efi_handle_t handle)
{
efi_status_t ret;
+ efi_uintn_t exit_data_size = 0;
+ u16 *exit_data = NULL;
/* Transfer environment variable as load options */
ret = set_load_options(handle, "bootargs");
if (ret != EFI_SUCCESS)
return ret;
- /* we don't support much: */
- env_set("efi_8be4df61-93ca-11d2-aa0d-00e098032b8c_OsIndicationsSupported",
- "{ro,boot}(blob)0000000000000000");
-
/* Call our payload! */
- ret = EFI_CALL(efi_start_image(handle, NULL, NULL));
+ ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data));
+ printf("## Application terminated, r = %lu\n", ret & ~EFI_ERROR_MASK);
+ if (ret && exit_data) {
+ printf("## %ls\n", exit_data);
+ efi_free_pool(exit_data);
+ }
efi_restore_gd();
}
/**
- * do_efibootmgr() - execute EFI Boot Manager
+ * do_efibootmgr() - execute EFI boot manager
*
- * @fdt_opt: string of fdt start address
* Return: status code
- *
- * Execute EFI Boot Manager
*/
-static int do_efibootmgr(const char *fdt_opt)
+static int do_efibootmgr(void)
{
efi_handle_t handle;
efi_status_t ret;
- /* Allow unaligned memory access */
- allow_unaligned();
-
- switch_to_non_secure_mode();
-
- /* Initialize EFI drivers */
- ret = efi_init_obj_list();
- if (ret != EFI_SUCCESS) {
- printf("Error: Cannot initialize UEFI sub-system, r = %lu\n",
- ret & ~EFI_ERROR_MASK);
- return CMD_RET_FAILURE;
- }
-
- ret = efi_install_fdt(fdt_opt);
- if (ret == EFI_INVALID_PARAMETER)
- return CMD_RET_USAGE;
- else if (ret != EFI_SUCCESS)
- return CMD_RET_FAILURE;
-
ret = efi_bootmgr_load(&handle);
if (ret != EFI_SUCCESS) {
printf("EFI boot manager: Cannot load any image\n");
}
ret = do_bootefi_exec(handle);
- printf("## Application terminated, r = %lu\n", ret & ~EFI_ERROR_MASK);
if (ret != EFI_SUCCESS)
return CMD_RET_FAILURE;
}
/*
- * do_bootefi_image() - execute EFI binary from command line
+ * do_bootefi_image() - execute EFI binary
+ *
+ * Set up memory image for the binary to be loaded, prepare device path, and
+ * then call do_bootefi_exec() to execute it.
*
* @image_opt: string of image start address
- * @fdt_opt: string of fdt start address
* Return: status code
- *
- * Set up memory image for the binary to be loaded, prepare
- * device path and then call do_bootefi_exec() to execute it.
*/
-static int do_bootefi_image(const char *image_opt, const char *fdt_opt)
+static int do_bootefi_image(const char *image_opt)
{
void *image_buf;
struct efi_device_path *device_path, *image_path;
efi_handle_t mem_handle = NULL, handle;
efi_status_t ret;
- /* Allow unaligned memory access */
- allow_unaligned();
-
- switch_to_non_secure_mode();
-
- /* Initialize EFI drivers */
- ret = efi_init_obj_list();
- if (ret != EFI_SUCCESS) {
- printf("Error: Cannot initialize UEFI sub-system, r = %lu\n",
- ret & ~EFI_ERROR_MASK);
- return CMD_RET_FAILURE;
- }
-
- ret = efi_install_fdt(fdt_opt);
- if (ret == EFI_INVALID_PARAMETER)
- return CMD_RET_USAGE;
- else if (ret != EFI_SUCCESS)
- return CMD_RET_FAILURE;
-
#ifdef CONFIG_CMD_BOOTEFI_HELLO
if (!strcmp(image_opt, "hello")) {
char *saddr;
goto out;
ret = do_bootefi_exec(handle);
- printf("## Application terminated, r = %lu\n", ret & ~EFI_ERROR_MASK);
out:
if (mem_handle)
}
/**
- * do_efi_selftest() - execute EFI Selftest
+ * do_efi_selftest() - execute EFI selftest
*
- * @fdt_opt: string of fdt start address
* Return: status code
- *
- * Execute EFI Selftest
*/
-static int do_efi_selftest(const char *fdt_opt)
+static int do_efi_selftest(void)
{
struct efi_loaded_image_obj *image_obj;
struct efi_loaded_image *loaded_image_info;
efi_status_t ret;
- /* Allow unaligned memory access */
- allow_unaligned();
-
- switch_to_non_secure_mode();
-
- /* Initialize EFI drivers */
- ret = efi_init_obj_list();
- if (ret != EFI_SUCCESS) {
- printf("Error: Cannot initialize UEFI sub-system, r = %lu\n",
- ret & ~EFI_ERROR_MASK);
- return CMD_RET_FAILURE;
- }
-
- ret = efi_install_fdt(fdt_opt);
- if (ret == EFI_INVALID_PARAMETER)
- return CMD_RET_USAGE;
- else if (ret != EFI_SUCCESS)
- return CMD_RET_FAILURE;
-
ret = bootefi_test_prepare(&image_obj, &loaded_image_info,
"\\selftest", "efi_selftest");
if (ret != EFI_SUCCESS)
}
#endif /* CONFIG_CMD_BOOTEFI_SELFTEST */
-/* Interpreter command to boot an arbitrary EFI image from memory */
+/**
+ * do_bootefi() - execute `bootefi` command
+ *
+ * @cmdtp: table entry describing command
+ * @flag: bitmap indicating how the command was invoked
+ * @argc: number of arguments
+ * @argv: command line arguments
+ * Return: status code
+ */
static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ efi_status_t ret;
+
if (argc < 2)
return CMD_RET_USAGE;
+ /* Initialize EFI drivers */
+ ret = efi_init_obj_list();
+ if (ret != EFI_SUCCESS) {
+ printf("Error: Cannot initialize UEFI sub-system, r = %lu\n",
+ ret & ~EFI_ERROR_MASK);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = efi_install_fdt(argc > 2 ? argv[2] : NULL);
+ if (ret == EFI_INVALID_PARAMETER)
+ return CMD_RET_USAGE;
+ else if (ret != EFI_SUCCESS)
+ return CMD_RET_FAILURE;
+
if (!strcmp(argv[1], "bootmgr"))
- return do_efibootmgr(argc > 2 ? argv[2] : NULL);
+ return do_efibootmgr();
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
else if (!strcmp(argv[1], "selftest"))
- return do_efi_selftest(argc > 2 ? argv[2] : NULL);
+ return do_efi_selftest();
#endif
- return do_bootefi_image(argv[1], argc > 2 ? argv[2] : NULL);
+ return do_bootefi_image(argv[1]);
}
#ifdef CONFIG_SYS_LONGHELP
bootm_disable_interrupts();
images.os.os = IH_OS_LINUX;
+#ifdef CONFIG_RISCV_SMODE
+ images.os.arch = IH_ARCH_RISCV;
+#elif CONFIG_ARM64
images.os.arch = IH_ARCH_ARM64;
+#endif
ret = do_bootm_states(cmdtp, flag, argc, argv,
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
BOOTM_STATE_RAMDISK |
#ifdef CONFIG_SYS_LONGHELP
static char booti_help_text[] =
"[addr [initrd[:size]] [fdt]]\n"
- " - boot arm64 Linux Image stored in memory\n"
+ " - boot Linux 'Image' stored at 'addr'\n"
"\tThe argument 'initrd' is optional and specifies the address\n"
"\tof an initrd in memory. The optional parameter ':size' allows\n"
"\tspecifying the size of a RAW initrd.\n"
U_BOOT_CMD(
booti, CONFIG_SYS_MAXARGS, 1, do_booti,
- "boot arm64 Linux Image image from memory", booti_help_text
+ "boot Linux kernel 'Image' format from memory", booti_help_text
);
struct uclass *uc;
struct clk clk;
int ret;
+ ulong rate;
/* Device addresses start at 1 */
ret = uclass_get(UCLASS_CLK, &uc);
uclass_foreach_dev(dev, uc) {
memset(&clk, 0, sizeof(clk));
ret = device_probe(dev);
- if (ret) {
- printf("%-30.30s : ? Hz\n", dev->name);
- continue;
- }
+ if (ret)
+ goto noclk;
ret = clk_request(dev, &clk);
- if (ret) {
- printf("%-30.30s : ? Hz\n", dev->name);
- continue;
- }
-
- printf("%-30.30s : %lu Hz\n", dev->name, clk_get_rate(&clk));
+ if (ret)
+ goto noclk;
+ rate = clk_get_rate(&clk);
clk_free(&clk);
+
+ if (rate == -ENODEV)
+ goto noclk;
+
+ printf("%-30.30s : %lu Hz\n", dev->name, rate);
+ continue;
+ noclk:
+ printf("%-30.30s : ? Hz\n", dev->name);
}
return 0;
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <command.h>
-#include <led-display.h>
-
-#undef DEBUG_DISP
-
-int do_display (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
-
- /* Clear display */
- display_set(DISPLAY_CLEAR | DISPLAY_HOME);
-
- if (argc < 2)
- return (0);
-
- for (i = 1; i < argc; i++) {
- char *p = argv[i];
-
- if (i > 1) { /* Insert a space between strings */
- display_putc(' ');
- }
-
- while ((*p)) {
-#ifdef DEBUG_DISP
- putc(*p);
-#endif
- display_putc(*p++);
- }
- }
-
-#ifdef DEBUG_DISP
- putc('\n');
-#endif
-
- return (0);
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
- display, CONFIG_SYS_MAXARGS, 1, do_display,
- "display string on dot matrix display",
- "[<string>]\n"
- " - with <string> argument: display <string> on dot matrix display\n"
- " - without arguments: clear dot matrix display"
-);
#include <efi_loader.h>
#include <environment.h>
#include <exports.h>
+#include <hexdump.h>
#include <malloc.h>
#include <search.h>
#include <linux/ctype.h>
+ sizeof(struct efi_device_path); /* for END */
/* optional data */
- lo.optional_data = (u8 *)(argc == 6 ? "" : argv[6]);
+ if (argc < 6)
+ lo.optional_data = NULL;
+ else
+ lo.optional_data = (const u8 *)argv[6];
size = efi_serialize_load_option(&lo, (u8 **)&data);
if (!size) {
}
ret = EFI_CALL(RT->set_variable(var_name16, &guid,
+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, data));
/**
* show_efi_boot_opt_data() - dump UEFI load option
*
- * @id: Load option number
- * @data: Value of UEFI load option variable
+ * @id: load option number
+ * @data: value of UEFI load option variable
+ * @size: size of the boot option
*
* Decode the value of UEFI load option variable and print information.
*/
-static void show_efi_boot_opt_data(int id, void *data)
+static void show_efi_boot_opt_data(int id, void *data, size_t size)
{
struct efi_load_option lo;
char *label, *p;
utf16_utf8_strncpy(&p, lo.label, label_len16);
printf("Boot%04X:\n", id);
- printf("\tattributes: %c%c%c (0x%08x)\n",
+ printf(" attributes: %c%c%c (0x%08x)\n",
/* ACTIVE */
lo.attributes & LOAD_OPTION_ACTIVE ? 'A' : '-',
/* FORCE RECONNECT */
/* HIDDEN */
lo.attributes & LOAD_OPTION_HIDDEN ? 'H' : '-',
lo.attributes);
- printf("\tlabel: %s\n", label);
+ printf(" label: %s\n", label);
dp_str = efi_dp_str(lo.file_path);
- printf("\tfile_path: %ls\n", dp_str);
+ printf(" file_path: %ls\n", dp_str);
efi_free_pool(dp_str);
- printf("\tdata: %s\n", lo.optional_data);
-
+ printf(" data:\n");
+ print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1,
+ lo.optional_data, size + (u8 *)data -
+ (u8 *)lo.optional_data, true);
free(label);
}
data));
}
if (ret == EFI_SUCCESS)
- show_efi_boot_opt_data(id, data);
+ show_efi_boot_opt_data(id, data, size);
else if (ret == EFI_NOT_FOUND)
printf("Boot%04X: not found\n", id);
free(data);
}
+static int u16_tohex(u16 c)
+{
+ if (c >= '0' && c <= '9')
+ return c - '0';
+ if (c >= 'A' && c <= 'F')
+ return c - 'A' + 10;
+
+ /* not hexadecimal */
+ return -1;
+}
+
/**
* show_efi_boot_dump() - dump all UEFI load options
*
static int do_efi_boot_dump(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- char regex[256];
- char * const regexlist[] = {regex};
- char *variables = NULL, *boot, *value;
- int len;
- int id;
+ u16 *var_name16, *p;
+ efi_uintn_t buf_size, size;
+ efi_guid_t guid;
+ int id, i, digit;
+ efi_status_t ret;
if (argc > 1)
return CMD_RET_USAGE;
- snprintf(regex, 256, "efi_.*-.*-.*-.*-.*_Boot[0-9A-F]+");
-
- /* TODO: use GetNextVariableName? */
- len = hexport_r(&env_htab, '\n', H_MATCH_REGEX | H_MATCH_KEY,
- &variables, 0, 1, regexlist);
-
- if (!len)
- return CMD_RET_SUCCESS;
-
- if (len < 0)
+ buf_size = 128;
+ var_name16 = malloc(buf_size);
+ if (!var_name16)
return CMD_RET_FAILURE;
- boot = variables;
- while (*boot) {
- value = strstr(boot, "Boot") + 4;
- id = (int)simple_strtoul(value, NULL, 16);
- show_efi_boot_opt(id);
- boot = strchr(boot, '\n');
- if (!*boot)
+ var_name16[0] = 0;
+ for (;;) {
+ size = buf_size;
+ ret = EFI_CALL(efi_get_next_variable_name(&size, var_name16,
+ &guid));
+ if (ret == EFI_NOT_FOUND)
break;
- boot++;
+ if (ret == EFI_BUFFER_TOO_SMALL) {
+ buf_size = size;
+ p = realloc(var_name16, buf_size);
+ if (!p) {
+ free(var_name16);
+ return CMD_RET_FAILURE;
+ }
+ var_name16 = p;
+ ret = EFI_CALL(efi_get_next_variable_name(&size,
+ var_name16,
+ &guid));
+ }
+ if (ret != EFI_SUCCESS) {
+ free(var_name16);
+ return CMD_RET_FAILURE;
+ }
+
+ if (memcmp(var_name16, L"Boot", 8))
+ continue;
+
+ for (id = 0, i = 0; i < 4; i++) {
+ digit = u16_tohex(var_name16[4 + i]);
+ if (digit < 0)
+ break;
+ id = (id << 4) + digit;
+ }
+ if (i == 4 && !var_name16[8])
+ show_efi_boot_opt(id);
}
- free(variables);
+
+ free(var_name16);
return CMD_RET_SUCCESS;
}
guid = efi_global_variable_guid;
size = sizeof(u16);
ret = EFI_CALL(RT->set_variable(L"BootNext", &guid,
+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, &bootnext));
guid = efi_global_variable_guid;
ret = EFI_CALL(RT->set_variable(L"BootOrder", &guid,
+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
size, bootorder));
" Example usage:\n"
" gpt write mmc 0 $partitions\n"
" gpt verify mmc 0 $partitions\n"
- " read <interface> <dev>\n"
- " - read GPT into a data structure for manipulation\n"
- " guid <interface> <dev>\n"
+ " gpt guid <interface> <dev>\n"
" - print disk GUID\n"
- " guid <interface> <dev> <varname>\n"
+ " gpt guid <interface> <dev> <varname>\n"
" - set environment variable to disk GUID\n"
" Example usage:\n"
" gpt guid mmc 0\n"
" gpt guid mmc 0 varname\n"
#ifdef CONFIG_CMD_GPT_RENAME
"gpt partition renaming commands:\n"
- "gpt swap <interface> <dev> <name1> <name2>\n"
+ " gpt read <interface> <dev>\n"
+ " - read GPT into a data structure for manipulation\n"
+ " gpt swap <interface> <dev> <name1> <name2>\n"
" - change all partitions named name1 to name2\n"
" and vice-versa\n"
- "gpt rename <interface> <dev> <part> <name>\n"
+ "
gpt rename <interface> <dev> <part> <name>\n"
" - rename the specified partition\n"
" Example usage:\n"
" gpt swap mmc 0 foo bar\n"
if (argc < 2)
return CMD_RET_USAGE;
led_label = argv[1];
- if (*led_label == 'l')
+ if (strncmp(led_label, "list", 4) == 0)
return list_leds();
cmd = argc > 2 ? get_led_cmd(argv[2]) : LEDST_COUNT;
led, 4, 1, do_led,
"manage LEDs",
"<led_label> on|off|toggle" BLINK "\tChange LED state\n"
- "led [<led_label>\tGet LED state\n"
+ "led [<led_label>]\tGet LED state\n"
"led list\t\tshow a list of LEDs"
);
return 0;
}
-static int mdio_write_ranges(struct phy_device *phydev, struct mii_dev *bus,
+static int mdio_write_ranges(struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
int reglo, int reghi, unsigned short data,
int extended)
{
+ struct phy_device *phydev;
int addr, devad, reg;
int err = 0;
for (addr = addrlo; addr <= addrhi; addr++) {
+ phydev = bus->phymap[addr];
+
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
- if (!extended)
+ if (!phydev)
err = bus->write(bus, addr, devad,
reg, data);
+ else if (!extended)
+ err = phy_write_mmd(phydev, devad,
+ reg, data);
else
err = phydev->drv->writeext(phydev,
addr, devad, reg, data);
return err;
}
-static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus,
+static int mdio_read_ranges(struct mii_dev *bus,
int addrlo,
int addrhi, int devadlo, int devadhi,
int reglo, int reghi, int extended)
{
int addr, devad, reg;
+ struct phy_device *phydev;
printf("Reading from bus %s\n", bus->name);
for (addr = addrlo; addr <= addrhi; addr++) {
+ phydev = bus->phymap[addr];
printf("PHY at address %x:\n", addr);
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
int val;
- if (!extended)
+ if (!phydev)
val = bus->read(bus, addr, devad, reg);
+ else if (!extended)
+ val = phy_read_mmd(phydev, devad, reg);
else
val = phydev->drv->readext(phydev, addr,
devad, reg);
bus = phydev->bus;
extended = 1;
} else {
- return -1;
+ return CMD_RET_FAILURE;
}
if (!phydev->drv ||
(!phydev->drv->writeext && (op[0] == 'w')) ||
(!phydev->drv->readext && (op[0] == 'r'))) {
puts("PHY does not have extended functions\n");
- return -1;
+ return CMD_RET_FAILURE;
}
}
}
if (pos > 1)
if (extract_reg_range(argv[pos--], &devadlo, &devadhi,
®lo, ®hi))
- return -1;
+ return CMD_RET_FAILURE;
default:
if (pos > 1)
if (extract_phy_range(&argv[2], pos - 1, &bus,
&phydev, &addrlo, &addrhi))
- return -1;
+ return CMD_RET_FAILURE;
break;
}
switch (op[0]) {
case 'w':
- mdio_write_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
+ mdio_write_ranges(bus, addrlo, addrhi, devadlo, devadhi,
reglo, reghi, data, extended);
break;
case 'r':
- mdio_read_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
+ mdio_read_ranges(bus, addrlo, addrhi, devadlo, devadhi,
reglo, reghi, extended);
break;
}
printf("Bus Speed: %d\n", mmc->clock);
#if CONFIG_IS_ENABLED(MMC_VERBOSE)
- printf("Mode : %s\n", mmc_mode_name(mmc->selected_mode));
+ printf("Mode: %s\n", mmc_mode_name(mmc->selected_mode));
mmc_dump_capabilities("card capabilities", mmc->card_caps);
mmc_dump_capabilities("host capabilities", mmc->host_caps);
#endif
setenv, CONFIG_SYS_MAXARGS, 0, do_env_set,
"set environment variables",
#if defined(CONFIG_CMD_NVEDIT_EFI)
- "-e name [value ...]\n"
+ "-e [-nv] name [value ...]\n"
" - set UEFI variable 'name' to 'value' ...'\n"
+ " 'nv' option makes the variable non-volatile\n"
" - delete UEFI variable 'name' if 'value' not specified\n"
#endif
"setenv [-f] name value ...\n"
if (!tmp_buf)
return -1;
- if (hex2bin((u8 *)tmp_buf, data, len) < 0)
+ if (hex2bin((u8 *)tmp_buf, data, len) < 0) {
+ printf("Error: illegal hexadecimal string\n");
+ free(tmp_buf);
return -1;
+ }
value = tmp_buf;
} else { /* string */
u16 *var_name16 = NULL, *p;
size_t len;
efi_guid_t guid;
+ u32 attributes;
efi_status_t ret;
if (argc == 1)
return CMD_RET_FAILURE;
}
+ attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS;
+ if (!strcmp(argv[1], "-nv")) {
+ attributes |= EFI_VARIABLE_NON_VOLATILE;
+ argc--;
+ argv++;
+ if (argc == 1)
+ return CMD_RET_SUCCESS;
+ }
+
var_name = argv[1];
if (argc == 2) {
/* delete */
for ( ; argc > 0; argc--, argv++)
if (append_value(&value, &size, argv[0]) < 0) {
+ printf("## Failed to process an argument, %s\n",
+ argv[0]);
ret = CMD_RET_FAILURE;
goto out;
}
len = utf8_utf16_strnlen(var_name, strlen(var_name));
var_name16 = malloc((len + 1) * 2);
if (!var_name16) {
+ printf("## Out of memory\n");
ret = CMD_RET_FAILURE;
goto out;
}
utf8_utf16_strncpy(&p, var_name, len + 1);
guid = efi_global_variable_guid;
- ret = EFI_CALL(efi_set_variable(var_name16, &guid,
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
+ ret = EFI_CALL(efi_set_variable(var_name16, &guid, attributes,
size, value));
- ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE);
+ if (ret == EFI_SUCCESS) {
+ ret = CMD_RET_SUCCESS;
+ } else {
+ printf("## Failed to set EFI variable\n");
+ ret = CMD_RET_FAILURE;
+ }
out:
free(value);
free(var_name16);
const char *pxe_default_paths[] = {
#ifdef CONFIG_SYS_SOC
+#ifdef CONFIG_SYS_BOARD
+ "default-" CONFIG_SYS_ARCH "-" CONFIG_SYS_SOC "-" CONFIG_SYS_BOARD,
+#endif
"default-" CONFIG_SYS_ARCH "-" CONFIG_SYS_SOC,
#endif
"default-" CONFIG_SYS_ARCH,
#include <console.h>
#include <g_dnl.h>
#include <usb.h>
-#include <asm/arch/f_rockusb.h>
+#include <asm/arch-rockchip/f_rockusb.h>
static int do_rockusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
config PREBOOT
string "preboot default value"
depends on USE_PREBOOT
+ default ""
help
This is the default of "preboot" environment variable.
obj-y += cli.o
obj-$(CONFIG_FSL_DDR_INTERACTIVE) += cli_simple.o cli_readline.o
+obj-$(CONFIG_STM32MP1_DDR_INTERACTIVE) += cli_simple.o cli_readline.o
obj-$(CONFIG_DFU_OVER_USB) += dfu.o
obj-y += command.o
obj-$(CONFIG_$(SPL_TPL_)LOG) += log.o
#ifdef CONFIG_ARM
__weak int reserve_mmu(void)
{
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
gd->relocaddr -= gd->arch.tlb_size;
memmove(to, from, len);
}
+#if defined(CONFIG_FIT_SIGNATURE)
static int bootm_host_load_image(const void *fit, int req_image_type)
{
const char *fit_uname_config = NULL;
/* Return the first error we found */
return err;
}
+#endif
#endif /* ndef USE_HOSTCC */
uint64_t addr, size;
int total, ret;
uint actualsize;
+ int fdt_memrsv = 0;
if (!blob)
return 0;
fdt_get_mem_rsv(blob, i, &addr, &size);
if (addr == (uintptr_t)blob) {
fdt_del_mem_rsv(blob, i);
+ fdt_memrsv = 1;
break;
}
}
/* Change the fdt header to reflect the correct size */
fdt_set_totalsize(blob, actualsize);
- /* Add the new reservation */
- ret = fdt_add_mem_rsv(blob, map_to_sysmem(blob), actualsize);
- if (ret < 0)
- return ret;
+ if (fdt_memrsv) {
+ /* Add the new reservation */
+ ret = fdt_add_mem_rsv(blob, map_to_sysmem(blob), actualsize);
+ if (ret < 0)
+ return ret;
+ }
return actualsize;
}
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
-struct reg_cell {
- unsigned int r0;
- unsigned int r1;
-};
-
static int fdt_del_subnodes(const void *blob, int parent_offset)
{
int off, ndepth;
{
struct list_head *pentry;
struct part_info *part;
- struct reg_cell cell;
int off, ndepth = 0;
int part_num, ret;
+ int sizecell;
char buf[64];
ret = fdt_del_partitions(blob, parent_offset);
if (ret < 0)
return ret;
+ /*
+ * Check if size/address is 1 or 2 cells.
+ * We assume #address-cells and #size-cells have same value.
+ */
+ sizecell = fdt_getprop_u32_default_node(blob, parent_offset,
+ 0, "#size-cells", 1);
+
/*
* Check if it is nand {}; subnode, adjust
* the offset in this case
goto err_prop;
}
- cell.r0 = cpu_to_fdt32(part->offset);
- cell.r1 = cpu_to_fdt32(part->size);
add_reg:
- ret = fdt_setprop(blob, newoff, "reg", &cell, sizeof(cell));
+ if (sizecell == 2) {
+ ret = fdt_setprop_u64(blob, newoff,
+ "reg", part->offset);
+ if (!ret)
+ ret = fdt_appendprop_u64(blob, newoff,
+ "reg", part->size);
+ } else {
+ ret = fdt_setprop_u32(blob, newoff,
+ "reg", part->offset);
+ if (!ret)
+ ret = fdt_appendprop_u32(blob, newoff,
+ "reg", part->size);
+ }
+
if (ret == -FDT_ERR_NOSPACE) {
ret = fdt_increase_size(blob, 512);
if (!ret)
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
int line_length;
if (lcd_flush_dcache)
supports MMC, NAND and YMODEM and other methods loading of U-Boot
and the Linux Kernel. If unsure, say Y.
+config SPL_SIZE_LIMIT
+ int "Maximum size of SPL image"
+ depends on SPL
+ default 0
+ help
+ Specifies the maximum length of the U-Boot SPL image.
+ If this value is zero, it is ignored.
+
+config SPL_SIZE_LIMIT_SUBTRACT_GD
+ bool "SPL image size check: provide space for global data"
+ depends on SPL_SIZE_LIMIT > 0
+ help
+ If enabled, aligned size of global data is reserved in
+ SPL_SIZE_LIMIT check to ensure such an image does not overflow SRAM
+ if SPL_SIZE_LIMIT describes the size of SRAM available for SPL when
+ pre-reloc global data is put into this SRAM, too.
+
+config SPL_SIZE_LIMIT_SUBTRACT_MALLOC
+ bool "SPL image size check: provide space for malloc() pool before relocation"
+ depends on SPL_SIZE_LIMIT > 0
+ help
+ If enabled, SPL_SYS_MALLOC_F_LEN is reserved in SPL_SIZE_LIMIT check
+ to ensure such an image does not overflow SRAM if SPL_SIZE_LIMIT
+ describes the size of SRAM available for SPL when pre-reloc malloc
+ pool is put into this SRAM, too.
+
+config SPL_SIZE_LIMIT_PROVIDE_STACK
+ hex "SPL image size check: provide stack space before relocation"
+ depends on SPL_SIZE_LIMIT > 0
+ default 0
+ help
+ If set, this size is reserved in SPL_SIZE_LIMIT check to ensure such
+ an image does not overflow SRAM if SPL_SIZE_LIMIT describes the size
+ of SRAM available for SPL when the stack required before reolcation
+ uses this SRAM, too.
+
config HANDOFF
bool "Pass hand-off information from SPL to U-Boot proper"
depends on BLOBLIST
checksum is a 160-bit (20-byte) hash value used to check that the
image contents have not been corrupted or maliciously altered.
While SHA1 is fairly secure it is coming to the end of its life
- due to the expanding computing power avaiable to brute-force
+ due to the expanding computing power available to brute-force
attacks. For more security, consider SHA256.
config SPL_SHA256_SUPPORT
#ifdef CONFIG_SPL_FIT_SIGNATURE
images.verify = 1;
#endif
- fit_image_load(&images, (ulong)header,
+ ret = fit_image_load(&images, (ulong)header,
&fit_uname_fdt, &fit_uname_config,
IH_ARCH_DEFAULT, IH_TYPE_FLATDT, -1,
FIT_LOAD_OPTIONAL, &dt_data, &dt_len);
+ if (ret >= 0)
+ spl_image->fdt_addr = (void *)dt_data;
conf_noffset = fit_conf_get_node((const void *)header,
fit_uname_config);
static int spl_fit_image_get_os(const void *fit, int noffset, uint8_t *os)
{
-#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
+#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY) && !defined(CONFIG_SPL_OS_BOOT)
return -ENOTSUPP;
#else
return fit_image_get_os(fit, noffset, os);
{
int res;
int node_offset;
- int splash_offset;
- int splash_size;
+ const char *splash_file;
+ const void *internal_splash_data;
+ size_t internal_splash_size;
+ int external_splash_addr;
+ int external_splash_size;
+ bool is_splash_external = false;
struct image_header *img_header;
const u32 *fit_header;
u32 fit_size;
return -EINVAL;
}
- node_offset = fit_image_get_node(fit_header, location->name);
+ /* Get the splash image node */
+ splash_file = env_get("splashfile");
+ if (!splash_file)
+ splash_file = SPLASH_SOURCE_DEFAULT_FILE_NAME;
+
+ node_offset = fit_image_get_node(fit_header, splash_file);
if (node_offset < 0) {
debug("Could not find splash image '%s' in FIT\n",
- location->name);
+ splash_file);
return -ENOENT;
}
- res = fit_image_get_data_offset(fit_header, node_offset,
- &splash_offset);
- if (res < 0) {
- printf("Failed to load splash image (err=%d)\n", res);
- return res;
+ /* Extract the splash data from FIT */
+ /* 1. Test if splash is in FIT internal data. */
+ if (!fit_image_get_data(fit_header, node_offset, &internal_splash_data, &internal_splash_size))
+ memmove((void *)bmp_load_addr, internal_splash_data, internal_splash_size);
+ /* 2. Test if splash is in FIT external data with fixed position. */
+ else if (!fit_image_get_data_position(fit_header, node_offset, &external_splash_addr))
+ is_splash_external = true;
+ /* 3. Test if splash is in FIT external data with offset. */
+ else if (!fit_image_get_data_offset(fit_header, node_offset, &external_splash_addr)) {
+ /* Align data offset to 4-byte boundary */
+ fit_size = ALIGN(fdt_totalsize(fit_header), 4);
+ /* External splash offset means the offset by end of FIT header */
+ external_splash_addr += location->offset + fit_size;
+ is_splash_external = true;
+ } else {
+ printf("Failed to get splash image from FIT\n");
+ return -ENODATA;
}
- res = fit_image_get_data_size(fit_header, node_offset, &splash_size);
- if (res < 0) {
- printf("Failed to load splash image (err=%d)\n", res);
- return res;
+ if (is_splash_external) {
+ res = fit_image_get_data_size(fit_header, node_offset, &external_splash_size);
+ if (res < 0) {
+ printf("Failed to get size of splash image (err=%d)\n", res);
+ return res;
+ }
+
+ /* Read in the splash data */
+ location->offset = external_splash_addr;
+ res = splash_storage_read_raw(location, bmp_load_addr, external_splash_size);
+ if (res < 0)
+ return res;
}
- /* Align data offset to 4-byte boundrary */
- fit_size = fdt_totalsize(fit_header);
- fit_size = (fit_size + 3) & ~3;
-
- /* Read in the splash data */
- location->offset = (location->offset + fit_size + splash_offset);
- res = splash_storage_read_raw(location, bmp_load_addr , splash_size);
- if (res < 0)
- return res;
-
return 0;
}
#endif /* CONFIG_FIT */
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
+CONFIG_PHY_REALTEK=y
+CONFIG_SUN8I_EMAC=y
CONFIG_AXP_DLDO3_VOLT=2500
CONFIG_AXP_DLDO4_VOLT=3300
CONFIG_AXP_FLDO1_VOLT=1200
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_JFFS2=y
+CONFIG_DEFAULT_DEVICE_TREE="M52277EVB"
CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_NET is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_JFFS2=y
+CONFIG_DEFAULT_DEVICE_TREE="M52277EVB_stmicro"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=2
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5235EVB"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_LOOPW=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
# CONFIG_NET is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO"
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5272C3"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5275EVB"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5282EVB"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M53017EVB"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5373EVB"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=1
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_mii"
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii"
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii_lowfreq"
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_mii"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=1
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=1
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54451EVB"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=1
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_a66"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_i66"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_intel"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_stm33"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=1
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MII=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475AFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475BFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475CFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475DFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475EFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475FFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5475GFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485AFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485BFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485CFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485DFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485EFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485FFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485GFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="M5485HFE"
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_MPC8xx=y
+CONFIG_SYS_IMMR=0xFF000000
CONFIG_TARGET_MCR3000=y
CONFIG_8xx_GCLK_FREQ=132000000
CONFIG_CMD_IMMAP=y
CONFIG_SYS_BR7_PRELIM_BOOL=y
CONFIG_SYS_BR7_PRELIM=0x1C000001
CONFIG_SYS_OR7_PRELIM=0xFFFF810A
-CONFIG_SYS_IMMR=0xFF000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTCOMMAND=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308RDB=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385_BASE"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
+CONFIG_SICR_GPIO_A_TSEC2=y
+CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8313ERDB_NOR=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2800000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xFA000000
+CONFIG_LBLAW3_NAME="BCSR"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE2800000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8313ERDB_NOR=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2800000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xFA000000
+CONFIG_LBLAW3_NAME="BCSR"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE2800000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8313ERDB_NAND=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_NAND_LBLAWBAR_PRELIM_1=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2800000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xFA000000
+CONFIG_LBLAW3_NAME="BCSR"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="NAND"
+CONFIG_BR0_OR0_BASE=0xE2800000
+CONFIG_BR0_ERRORCHECKING_BOTH=y
+CONFIG_BR0_MACHINE_FCM=y
+CONFIG_OR0_SCY_1=y
+CONFIG_OR0_CSCT_8_CYCLE=y
+CONFIG_OR0_CST_ONE_CLOCK=y
+CONFIG_OR0_CHT_TWO_CLOCK=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FLASH"
+CONFIG_BR1_OR1_BASE=0xFE000000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_8_MBYTES=y
+CONFIG_OR1_SCY_9=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_EHTR_1_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8313ERDB_NAND=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_NAND_LBLAWBAR_PRELIM_1=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2800000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xFA000000
+CONFIG_LBLAW3_NAME="BCSR"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="NAND"
+CONFIG_BR0_OR0_BASE=0xE2800000
+CONFIG_BR0_ERRORCHECKING_BOTH=y
+CONFIG_BR0_MACHINE_FCM=y
+CONFIG_OR0_SCY_1=y
+CONFIG_OR0_CSCT_8_CYCLE=y
+CONFIG_OR0_CST_ONE_CLOCK=y
+CONFIG_OR0_CHT_TWO_CLOCK=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FLASH"
+CONFIG_BR1_OR1_BASE=0xFE000000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_8_MBYTES=y
+CONFIG_OR1_SCY_9=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_EHTR_1_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8315ERDB=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_32_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI_MEM_PHYS"
+CONFIG_BAT4_BASE=0x80000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PCI_MMIO_PHYS"
+CONFIG_BAT5_BASE=0x90000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8323ERDB=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_32_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PCI_MEM_PHYS"
+CONFIG_BAT5_BASE=0x80000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI1_MMIO_PHYS"
+CONFIG_BAT6_BASE=0x90000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_INHIBITED=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_OPT_SPEC_READ=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM_PHYS"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1"
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM_PHYS"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1"
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM_PHYS"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2400000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8349EMDS_SDRAM=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2400000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="SDRAM"
+CONFIG_LBLAW2_LENGTH_64_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="SDRAM"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_PORTSIZE_32BIT=y
+CONFIG_BR2_MACHINE_SDRAM=y
+CONFIG_OR2_COLS_9=y
+CONFIG_OR2_ROWS_13=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_PCI_ONE_PCI1=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_MARVELL=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_MPC8XXX_SPI=y
+CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666666
+CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2400000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_PCI_ONE_PCI1=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2400000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_PCI_ONE_PCI1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349ITX=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="PCI2_MEM"
+CONFIG_BAT3_BASE=0xA0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI2_MMIO"
+CONFIG_BAT4_BASE=0xB0000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_INHIBITED=y
+CONFIG_BAT4_ICACHE_GUARDED=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="VSC7385"
+CONFIG_LBLAW1_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF0000000
+CONFIG_LBLAW3_NAME="CF"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="VSC7385"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_AM_128_KBYTES=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="LED"
+CONFIG_BR2_OR2_BASE=0xF9000000
+CONFIG_OR2_AM_2_MBYTES=y
+CONFIG_OR2_SCY_9=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CF"
+CONFIG_BR3_OR3_BASE=0xF0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_BR3_MACHINE_UPMA=y
+CONFIG_OR3_BI_BURSTINHIBIT=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200"
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349ITX=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="PCI2_MEM"
+CONFIG_BAT3_BASE=0xA0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI2_MMIO"
+CONFIG_BAT4_BASE=0xB0000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_INHIBITED=y
+CONFIG_BAT4_ICACHE_GUARDED=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="VSC7385"
+CONFIG_LBLAW1_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF0000000
+CONFIG_LBLAW3_NAME="CF"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="VSC7385"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_AM_128_KBYTES=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="LED"
+CONFIG_BR2_OR2_BASE=0xF9000000
+CONFIG_OR2_AM_2_MBYTES=y
+CONFIG_OR2_SCY_9=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CF"
+CONFIG_BR3_OR3_BASE=0xF0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_BR3_MACHINE_UPMA=y
+CONFIG_OR3_BI_BURSTINHIBIT=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFEF00000
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349ITX=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="PCI2_MEM"
+CONFIG_BAT3_BASE=0xA0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI2_MMIO"
+CONFIG_BAT4_BASE=0xB0000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_INHIBITED=y
+CONFIG_BAT4_ICACHE_GUARDED=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="VSC7385"
+CONFIG_LBLAW1_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF0000000
+CONFIG_LBLAW3_NAME="CF"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="VSC7385"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_AM_128_KBYTES=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="LED"
+CONFIG_BR2_OR2_BASE=0xF9000000
+CONFIG_OR2_AM_2_MBYTES=y
+CONFIG_OR2_SCY_9=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CF"
+CONFIG_BR3_OR3_BASE=0xF0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_BR3_MACHINE_UPMA=y
+CONFIG_OR3_BI_BURSTINHIBIT=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_6_1=y
+CONFIG_CORE_PLL_RATIO_15_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="BCSR"
+CONFIG_BAT3_BASE=0xF8000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="FLASH"
+CONFIG_BAT4_BASE=0xFE000000
+CONFIG_BAT4_LENGTH_32_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI_MMIO"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xE0600000
+CONFIG_LBLAW3_NAME="NAND"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="NAND"
+CONFIG_BR3_OR3_BASE=0xE0600000
+CONFIG_BR3_ERRORCHECKING_BOTH=y
+CONFIG_BR3_MACHINE_FCM=y
+CONFIG_OR3_BCTLD_NOT_ASSERTED=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_CST_ONE_CLOCK=y
+CONFIG_OR3_CHT_TWO_CLOCK=y
+CONFIG_OR3_RST_ONE_CLOCK=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_6_1=y
+CONFIG_CORE_PLL_RATIO_15_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="BCSR"
+CONFIG_BAT3_BASE=0xF8000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xE0600000
+CONFIG_LBLAW3_NAME="NAND"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="NAND"
+CONFIG_BR3_OR3_BASE=0xE0600000
+CONFIG_BR3_ERRORCHECKING_BOTH=y
+CONFIG_BR3_MACHINE_FCM=y
+CONFIG_OR3_BCTLD_NOT_ASSERTED=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_CST_ONE_CLOCK=y
+CONFIG_OR3_CHT_TWO_CLOCK=y
+CONFIG_OR3_RST_ONE_CLOCK=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_6_1=y
+CONFIG_CORE_PLL_RATIO_15_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="BCSR"
+CONFIG_BAT3_BASE=0xF8000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="FLASH"
+CONFIG_BAT4_BASE=0xFE000000
+CONFIG_BAT4_LENGTH_32_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xE0600000
+CONFIG_LBLAW3_NAME="NAND"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="NAND"
+CONFIG_BR3_OR3_BASE=0xE0600000
+CONFIG_BR3_ERRORCHECKING_BOTH=y
+CONFIG_BR3_MACHINE_FCM=y
+CONFIG_OR3_BCTLD_NOT_ASSERTED=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_CST_ONE_CLOCK=y
+CONFIG_OR3_CHT_TWO_CLOCK=y
+CONFIG_OR3_RST_ONE_CLOCK=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC837XERDB=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="L2_SWITCH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_FSL_SATA=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC837XERDB=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="L2_SWITCH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="FLASH"
+CONFIG_BAT4_BASE=0xFE000000
+CONFIG_BAT4_LENGTH_32_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACH_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI_MMIO"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCIE"
CONFIG_BOOTDELAY=6
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_PHY_MARVELL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_E1000=y
+CONFIG_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_E1000=y
+CONFIG_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xfff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8610HPCD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xeff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xeff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFKW=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFXCAT=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3"
+CONFIG_PHY_REALTEK=y
+CONFIG_SUN8I_EMAC=y
CONFIG_AXP_DCDC5_VOLT=1200
-CONFIG_AXP_DLDO3_VOLT=2500
+CONFIG_AXP_DLDO3_VOLT=3300
CONFIG_AXP_SW_ON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_DM=y
+CONFIG_FSL_AHCI=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_REMOTE=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_MII=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_SYS_CLK_FREQ=66666000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_TQM834X=y
+CONFIG_SYS_IMMR=0xff400000
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="STACK_IN_DCACHE"
+CONFIG_BAT2_BASE=0x20000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="PCI_MEM_BASE"
+CONFIG_BAT3_BASE=0x90000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI_MMIO"
+CONFIG_BAT4_BASE=0xA0000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_ICACHE_GUARDED=y
+CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PCI_IO"
+CONFIG_BAT5_BASE=0xE2000000
+CONFIG_BAT5_LENGTH_16_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="IMMR"
+CONFIG_BAT6_BASE=0xFF400000
+CONFIG_BAT6_LENGTH_1_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_INHIBITED=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="FLASH"
+CONFIG_BAT7_BASE=0x80000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0x80000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_1_GBYTES=y
+CONFIG_LBLAW1=y
+# CONFIG_LBLAW1_ENABLE is not set
+CONFIG_LBLAW2=y
+# CONFIG_LBLAW2_ENABLE is not set
+CONFIG_LBLAW3=y
+# CONFIG_LBLAW3_ENABLE is not set
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0x80000000
+CONFIG_BR0_PORTSIZE_32BIT=y
+CONFIG_OR0_AM_1_GBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_XIP=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_ARCH_RV64I=y
+CONFIG_XIP=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_PCI=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_ETH_SUPPORT=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_TI=y
CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_TI=y
CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_DIAG=y
+CONFIG_DEFAULT_DEVICE_TREE="amcore"
CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_NET is not set
-CONFIG_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SERIAL=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_SYS_I2C_TEGRA=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0xE80C0000
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM_I2C_COMPAT=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX88179=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_JFFS2=y
+CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l"
# CONFIG_NET is not set
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
-CONFIG_SPL_SYS_THUMB_BUILD=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_AT91=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x21000000
CONFIG_TARGET_TAURUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xfffff200
+CONFIG_DEBUG_UART_CLOCK=18432000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068"
CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="\0addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}::off\0addtest=setenv bootargs ${bootargs} loglevel=4 test\0baudrate=115200\0boot_file=setenv bootfile /${project_dir}/kernel/uImage\0boot_retries=0\0bootcmd=run flash_self\0bootdelay=3\0ethact=macb0\0flash_nfs=run nand_kernel;run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0flash_self=run nand_kernel;run setbootargs;upgrade_available;bootm ${kernel_ram};reset\0flash_self_test=run nand_kernel;run setbootargs addtest; upgrade_available;bootm ${kernel_ram};reset\0hostname=systemone\0kernel_Off=0x00200000\0kernel_Off_fallback=0x03800000\0kernel_ram=0x21500000\0kernel_size=0x00400000\0kernel_size_fallback=0x00400000\0loads_echo=1\0nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} ${kernel_size}\0net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0netdev=eth0\0nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs rw nfsroot=${serverip}:${rootpath} at91sam9_wdt.wdt_timeout=16\0partitionset_active=A\0preboot=echo;echo Type 'run flash_self' to use kernel and root filesystem on memory;echo Type 'run flash_nfs' to use kernel from memory and root filesystem over NFS;echo Type 'run net_nfs' to get Kernel over TFTP and mount root filesystem over NFS;echo\0project_dir=systemone\0root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0rootfs=/dev/mtdblock5\0rootfs_fallback=/dev/mtdblock7\0setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops root=${rootfs} rootfstype=jffs2 panic=7 at91sam9_wdt.wdt_timeout=16\0stderr=serial\0stdin=serial\0stdout=serial\0upgrade_available=0\0"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run flash_self"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_NAND=y
+# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SPL_DM=y
+CONFIG_BLK=y
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_ATMEL_USART=y
+CONFIG_WDT=y
+CONFIG_WDT_AT91=y
CONFIG_USE_TINY_PRINTF=y
+CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM23550_W1D=y
CONFIG_SYS_TEXT_BASE=0x9f000000
CONFIG_EFI_PARTITION=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
# CONFIG_EFI_LOADER is not set
CONFIG_CMD_SPI=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H6=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_PSCI_RESET is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_TEXT_BASE=0x20060
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1"
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_SYS_VENDOR="bitmain"
CONFIG_SYS_BOARD="antminer_s9"
CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_ENV_OFFSET=0x300000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_DEBUG_UART=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xEFFFFF0
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
CONFIG_SYS_TEXT_BASE=0x3f401000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c
CONFIG_TARGET_BK4R1=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg"
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c
CONFIG_DM_GPIO=y
CONFIG_VYBRID_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
CONFIG_SYS_I2C_MXC=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_VME8349=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_CADDY2=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="UNKNOWN"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFFC00000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_4_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF0000000
+CONFIG_LBLAW1_NAME="WINDOW1"
+CONFIG_LBLAW1_LENGTH_256_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFFC00000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_4_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="WINDOW1"
+CONFIG_BR1_OR1_BASE=0xF0000000
+CONFIG_BR1_PORTSIZE_32BIT=y
+CONFIG_OR1_AM_256_KBYTES=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
CONFIG_BOOTDELAY=6
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_SYS_TEXT_BASE=0x60000000
-CONFIG_TARGET_CALIMAIN=y
-CONFIG_DA850_LOWLEVEL=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_BOOTDELAY=0
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Calimain > "
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR="\x0b"
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DIAG=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0x01C23000
-CONFIG_DA8XX_GPIO=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_ATF=y
-CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_X86=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
CONFIG_X86_RUN_64BIT=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_TARGET_CHROMEBOOK_LINK64=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
-CONFIG_SPL_DM=y
CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
CONFIG_SPL_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
-CONFIG_SPL_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SOUND=y
+CONFIG_I2S=y
+CONFIG_I2S_ROCKCHIP=y
+CONFIG_SOUND_MAX98090=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_X86=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
-CONFIG_SYS_MALLOC_F_LEN=0x1c00
+CONFIG_SYS_MALLOC_F_LEN=0x1d00
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
--- /dev/null
+CONFIG_X86=y
+CONFIG_SYS_TEXT_BASE=0xffed0000
+CONFIG_SYS_MALLOC_F_LEN=0x1a00
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_TARGET_CHROMEBOOK_SAMUS_TPL=y
+CONFIG_DEBUG_UART=y
+CONFIG_HAVE_MRC=y
+CONFIG_HAVE_REFCODE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_MISC_INIT_R=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_SIZE=0x1000
+CONFIG_BLOBLIST_ADDR=0xff7c0000
+CONFIG_HANDOFF=y
+CONFIG_SPL_TEXT_BASE=0xffe70000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_PCI=y
+CONFIG_SPL_PCH_SUPPORT=y
+CONFIG_TPL_PCI=y
+CONFIG_TPL_PCH_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+# CONFIG_SPL_MAC_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
+# CONFIG_NET is not set
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_TPL_MISC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_SYS_NS16550=y
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
+CONFIG_SOUND_RT5677=y
+CONFIG_SPI=y
+CONFIG_TPL_SYSRESET=y
+CONFIG_TPM_TIS_LPC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_TPM=y
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_MVEBU=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
+++ /dev/null
-CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80008000
-CONFIG_TARGET_CM_T3517=y
-CONFIG_EMIF4=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="CM-T3517 # "
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_EEPROM_LAYOUT=y
-CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3"
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),256k(u-boot-env),4m(kernel),-(fs)"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_OMAP24_I2C_SPEED=400000
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=186
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_MII=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x2D000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_AM35X=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_VIDEO_OMAP3=y
-CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SCSI_AHCI=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=4
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+CONFIG_DEFAULT_DEVICE_TREE="cobra5272"
CONFIG_MTD_NOR_FLASH=y
CONFIG_MII=y
CONFIG_BAUDRATE=19200
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
-# CONFIG_SPL_SYS_THUMB_BUILD is not set
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_TARGET_COLIBRI_IMX6ULL=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
+# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_NAND_TORTURE=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx6ull-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_MXS_DT=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
-CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_FUNCTION_SDP=y
CONFIG_VIDEO=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y
-# CONFIG_EFI_LOADER is not set
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_COLIBRI_PXA270=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_NR_DRAM_BANKS=1
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_CRS305_1G_4S=y
+CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BLK=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPL_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_DA8XX=y
# CONFIG_FAT_WRITE is not set
CONFIG_USE_TINY_PRINTF=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_BLK=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x83F00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_FIT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DNS325=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DOCKSTAR=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DREAMPLUG=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DS109=y
CONFIG_ARM=y
CONFIG_TEGRA=y
-CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA210=y
CONFIG_OF_SYSTEM_SETUP=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_SYS_TEXT_BASE=0xc1080000
-CONFIG_TARGET_EA20=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="ea20 > "
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_DIAG=y
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_SYS_I2C_DAVINCI=y
-# CONFIG_MMC is not set
-CONFIG_NAND=y
-CONFIG_NAND_DAVINCI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=30000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DAVINCI_SPI=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282"
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=8
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_DATE=y
+CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal"
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=8
+++ /dev/null
-CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80008000
-CONFIG_TARGET_ECO5PK=y
-CONFIG_EMIF4=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL=y
-CONFIG_BOOTDELAY=10
-CONFIG_SPL_TEXT_BASE=0x40200000
-# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="ECO5-PK # "
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader-nand),1024k(uboot-nand),256k(params-nand),5120k(kernel),-(ubifs)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_OMAP24_I2C_SPEED=400000
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_OMAP is not set
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_TARGET_ECOVEC=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CPU=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_DM_PCI_COMPAT=y
-CONFIG_RTC_MC146818=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Intel"
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ASPEED=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_ASPEED_AST2500=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3368=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_PX5=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xFF1c0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_SPL_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_BOOTSTAGE_FDT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL=y
+CONFIG_TPL_BOOTROM_SUPPORT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SYSRESET=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_TPL_TIMER=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SYS_TEXT_BASE=0x60000000
+CONFIG_SYS_TEXT_BASE=0x61000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ROCKCHIP_RK322X=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_TARGET_EVB_RK3229=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_STACK_R_ADDR=0x60600000
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="arch/arm/mach-rockchip/fit_spl_optee.its"
CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0x10081000
+CONFIG_SPL_TEXT_BASE=0x60000000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_OPTEE=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_PINCTRL=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
-CONFIG_SPL_ATF=y
-CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
CONFIG_DISPLAY_ROCKCHIP_MIPI=y
CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
-CONFIG_SPL_ATF=y
-CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
-CONFIG_SPL_ATF=y
-CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_FLEA3=y
CONFIG_SYS_TEXT_BASE=0xA0000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ARCH_MT7620=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
+CONFIG_ARCH_MTMIPS=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_MTD=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
CONFIG_CLK=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9c000000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ARCH_MT7620=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
+CONFIG_ARCH_MTMIPS=y
CONFIG_BOOT_ROM=y
CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
+CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_MTD=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
CONFIG_CLK=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
--- /dev/null
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_MALLOC_F_LEN=0x600
+CONFIG_IDENT_STRING=" gazerbeam 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
+CONFIG_MPC83xx=y
+CONFIG_TARGET_GAZERBEAM=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="INIT_RAM"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xE0700000
+CONFIG_LBLAW2_NAME="FPGA1"
+CONFIG_LBLAW2_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA0"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="FPGA1"
+CONFIG_BR2_OR2_BASE=0xE0700000
+CONFIG_BR2_PORTSIZE_16BIT=y
+CONFIG_OR2_AM_1_MBYTES=y
+CONFIG_OR2_SCY_5=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
+CONFIG_SICR_GPIO_A_TSEC2=y
+CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y
+CONFIG_CMD_IOLOOP=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_BINOP=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_AXI=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="gazerbeam"
+CONFIG_DM=y
+CONFIG_REGMAP=y
+CONFIG_AXI=y
+CONFIG_IHS_AXI=y
+CONFIG_CLK=y
+CONFIG_ICS8N3QV01=y
+CONFIG_CPU=y
+CONFIG_CPU_MPC83XX=y
+CONFIG_BOARD=y
+CONFIG_BOARD_GAZERBEAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_MPC8XXX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_IHS=y
+CONFIG_MISC=y
+CONFIG_GDSYS_RXAUI_CTRL=y
+CONFIG_GDSYS_IOEP=y
+CONFIG_MPC83XX_SERDES=y
+CONFIG_GDSYS_SOC=y
+CONFIG_IHS_FPGA=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_MARVELL=y
+CONFIG_DM_ETH=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_RAM=y
+CONFIG_MPC83XX_SDRAM=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_MCP83XX=y
+CONFIG_TIMER=y
+CONFIG_MPC83XX_TIMER=y
+CONFIG_TPM_ATMEL_TWI=y
+CONFIG_TPM_AUTH_SESSIONS=y
+# CONFIG_TPM_V2 is not set
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_LOGICORE_DP_TX=y
+CONFIG_OSD=y
+CONFIG_IHS_VIDEO_OUT=y
+CONFIG_TPM=y
CONFIG_SYS_VPD_EEPROM_SIZE=1024
CONFIG_TARGET_GE_BX50V3=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOUNT_EXT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
-CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_PCI=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_GPLUGD=y
CONFIG_SYS_TEXT_BASE=0x00f00000
CONFIG_NR_DRAM_BANKS=2
--- /dev/null
+CONFIG_ARM=y
+# CONFIG_SPL_SYS_THUMB_BUILD is not set
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_TEXT_BASE=0x18000000
+CONFIG_RZA1=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=50000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_DM_GPIO=y
+CONFIG_RZA1_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_SH_ETHER=y
+CONFIG_PINCTRL=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_TIMER=y
+CONFIG_RENESAS_OSTM_TIMER=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GURUPLUG=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_PHYLIB=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
CONFIG_PHYLIB=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_NR_DRAM_BANKS=0
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_NVRAM=y
CONFIG_SCSI_AHCI=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
# CONFIG_MMC is not set
CONFIG_SCSI=y
CONFIG_CONS_INDEX=0
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" hrcon 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" hrcon dh 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_IB62X0=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_ICONNECT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_BOOTCOUNT_ADDR=0x9
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_IDS8313=y
+CONFIG_SYS_IMMR=0xF0000000
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="INITRAM"
+CONFIG_BAT1_BASE=0xFD000000
+CONFIG_BAT1_LENGTH_256_KBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFF800000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xF0000000
+CONFIG_BAT5_LENGTH_128_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="NAND_MRAM_CPLD"
+CONFIG_BAT6_BASE=0xE0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_NAND_LBLAWBAR_PRELIM_1=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFF800000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE1000000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xE2000000
+CONFIG_LBLAW2_NAME="MRAM"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xE3000000
+CONFIG_LBLAW3_NAME="CPLD"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_10=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE1000000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_SCY_4=y
+CONFIG_OR1_PGS_LARGE=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_RST_ONE_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="MRAM"
+CONFIG_BR2_OR2_BASE=0xE2000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_7=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CPLD"
+CONFIG_BR3_OR3_BASE=0xE3000000
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_CMD_UBI=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_I2C=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x9
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
CONFIG_CMD_UBI=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_PCF8575_GPIO=y
CONFIG_LED=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_FAT_WRITE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
CONFIG_DEBUG_UART_BASE=0x021f0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_IMX8QXP_MEK=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ATHEROS=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_SYS_TEXT_BASE=0xc1080000
-CONFIG_TARGET_IPAM390=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00180000
-CONFIG_CMD_SPL_WRITE_SIZE=0x400
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs)"
-CONFIG_CMD_DIAG=y
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DA8XX_GPIO=y
-# CONFIG_MMC is not set
-CONFIG_NAND=y
-CONFIG_NAND_DAVINCI=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_PHYLIB=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_PHY_TI=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_PHYLIB=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xfff40000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
CONFIG_MPC85xx=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_KM8360=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMCOGE5NE=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_4=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_6=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_LALE_TIMING_EARLIER=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PAXE"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="BFTIC3"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="SDRAM_UPPER"
+CONFIG_BAT7_BASE=0x10000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xA0000000
+CONFIG_LBLAW3_NAME="PAXE"
+CONFIG_LBLAW3_LENGTH_512_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_64_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PAXE"
+CONFIG_BR3_OR3_BASE=0xA0000000
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_ELBC_BR4_OR4=y
+CONFIG_BR4_OR4_NAME="BFTIC3"
+CONFIG_BR4_OR4_BASE=0xB0000000
+CONFIG_OR4_AM_256_MBYTES=y
+CONFIG_OR4_SCY_2=y
+CONFIG_OR4_CSNT_EARLIER=y
+CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR4_TRLX_RELAXED=y
+CONFIG_OR4_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_2=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_KM8360=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMETER1=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_4=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_6=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_LALE_TIMING_EARLIER=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PAXE"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xA0000000
+CONFIG_LBLAW3_NAME="PAXE"
+CONFIG_LBLAW3_LENGTH_512_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_64_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PAXE"
+CONFIG_BR3_OR3_BASE=0xA0000000
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_2=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xfff40000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
CONFIG_MPC85xx=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_TUXX1=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMOPTI2=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_4=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_TUXX1=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMSUPX5=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_SUVD3=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMTEGR1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_5=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_TUXX1=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMTEPR2=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_4=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_SUVD3=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMVECT1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_PORTSIZE_16BIT=y
+CONFIG_BR2_MACHINE_UPMA=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_3=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_PCI=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
+CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL_IMX5=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_MC34708=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=2
CONFIG_MXC_UART=y
CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0x20068000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y
# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_PCI=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ARCH_MT7620=y
+CONFIG_ARCH_MTMIPS=y
CONFIG_BOARD_LINKIT_SMART_7688=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_MIPS=y
CONFIG_SYS_TEXT_BASE=0x9c000000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ARCH_MT7620=y
+CONFIG_ARCH_MTMIPS=y
CONFIG_BOARD_LINKIT_SMART_7688=y
CONFIG_BOOT_ROM=y
CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y
CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028AQDS=y
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_TFABOOT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1028ARDB=y
+CONFIG_SYS_FSL_SDHC_CLK_DIV=1
+CONFIG_TFABOOT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_WDT=y
+CONFIG_WDT_SP805=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:2m(uboot),14m(free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:2m(uboot),14m(free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:2m(uboot),14m(free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:2m(uboot),14m(free)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:2m(uboot),14m(free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_SPL_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SPL_BOARD_INIT=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
+CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_PHY_CORTINA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
# CONFIG_CMD_BMODE is not set
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_RTC_M41T62=y
CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+++ /dev/null
-CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80008000
-# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_TARGET_MCX=y
-CONFIG_EMIF4=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL=y
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL_TEXT_BASE=0x40200000
-# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="mcx # "
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),6m(k_recovery),8m(fs_recovery),-(common_data)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_ULPI_VIEWPORT_OMAP=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_MCS7830=y
-CONFIG_VIDEO_OMAP3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_NETCONSOLE=y
CONFIG_SPL_DM=y
-CONFIG_DM_GPIO=y
CONFIG_XILINX_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_ARCH_RV64I=y
+CONFIG_NR_CPUS=5
+CONFIG_TARGET_MICROCHIP_ICICLE=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_FIT=y
+CONFIG_OF_PRIOR_STAGE=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFC000000
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308_P1M=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFC000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACKINDCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFC000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_64_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xFBFF0000
+CONFIG_LBLAW1_NAME="SJA1000"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xFBFF8000
+CONFIG_LBLAW2_NAME="CPLD"
+CONFIG_LBLAW2_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFC000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_64_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_4=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="SJA1000"
+CONFIG_BR1_OR1_BASE=0xFBFF0000
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_EHTR_1_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="CPLD"
+CONFIG_BR2_OR2_BASE=0xFBFF8000
+CONFIG_OR2_SCY_4=y
+CONFIG_OR2_EHTR_1_CYCLE=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ESDHC_A_GPIO=y
+CONFIG_SICR_ESDHC_B_GPIO=y
+CONFIG_SICR_ESDHC_C_GTM=y
+CONFIG_SICR_GPIO_A_TSEC2=y
+CONFIG_SICR_GPIO_B_TSEC2=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=5
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_TARGET_MPR2=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_MISC is not set
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_TARGET_MS7720SE=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCMCIA=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)"
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
+CONFIG_MSCC_SERVAL_SWITCH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_DM_SERIAL=y
CONFIG_CLK=y
CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_PHY_FIXED=y
CONFIG_DM_SPI=y
CONFIG_MTK_QSPI=y
CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
+++ /dev/null
-CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80008000
-CONFIG_TARGET_MT_VENTOUX=y
-CONFIG_EMIF4=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL_TEXT_BASE=0x40200000
-# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="mt_ventoux => "
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),8m(ubisystem),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FPGA_XILINX=y
-CONFIG_FPGA_SPARTAN3=y
-CONFIG_SYS_OMAP24_I2C_SPEED=400000
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_ULPI_VIEWPORT_OMAP=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_OMAP3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y
+CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_MXC_UART=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_FSL_ESDHC=y
CONFIG_MII=y
CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_SYS_VPD_EEPROM_I2C_BUS=2
CONFIG_SYS_VPD_EEPROM_SIZE=1024
CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg"
CONFIG_BOOTCOUNT_EXT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=10
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
-CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MII=y
CONFIG_PINCTRL_IMX5=y
CONFIG_RTC_S35392A=y
CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
CONFIG_VIDEO_IPUV3=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
# CONFIG_MXC_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y
# CONFIG_MXC_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
+CONFIG_MACPWR="PD6"
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
+CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NAS220=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NSA310S=y
CONFIG_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x81000100
CONFIG_NR_DRAM_BANKS=2
+CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
CONFIG_DEBUG_UART_BASE=0x70006000
CONFIG_DEBUG_UART_CLOCK=408000000
CONFIG_TEGRA124=y
CONFIG_BOOTSTAGE=y
CONFIG_SPL_BOOTSTAGE=y
CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000
CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_LOG_DEFAULT_LEVEL=7
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0x80108000
CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
# CONFIG_CMD_NFS is not set
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_PWM_TEGRA=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
+CONFIG_SOUND=y
+CONFIG_I2S=y
+CONFIG_I2S_TEGRA=y
+CONFIG_SOUND_MAX98090=y
CONFIG_TEGRA114_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_ADC=y
CONFIG_ADC_EXYNOS=y
CONFIG_DFU_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x5000000
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_TCA642X=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=3
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_PWRSEQ=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS4=y
CONFIG_ARM=y
CONFIG_TEGRA=y
-CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA210=y
CONFIG_TARGET_P2371_0000=y
CONFIG_ARM=y
CONFIG_TEGRA=y
-CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA210=y
CONFIG_TARGET_P2371_2180=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # "
CONFIG_ARM=y
CONFIG_TEGRA=y
-CONFIG_SYS_TEXT_BASE=0x80110000
+CONFIG_SYS_TEXT_BASE=0x80080000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA210=y
CONFIG_TARGET_P2571=y
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
-CONFIG_NR_DRAM_BANKS=8
+CONFIG_NR_DRAM_BANKS=1026
CONFIG_TEGRA186=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # "
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80080000
-CONFIG_NR_DRAM_BANKS=8
+CONFIG_NR_DRAM_BANKS=1026
CONFIG_TEGRA186=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # "
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
CONFIG_SYS_I2C_MXC=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_I2C_MXC_I2C4=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_NAND_MXS_DT=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
# CONFIG_CMD_MII is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-hobbit"
CONFIG_DFU_MMC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
# CONFIG_CMD_MII is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_DFU_MMC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
# CONFIG_CMD_MII is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_DFU_MMC=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_POGO_E02=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_PCI=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_MISC_INIT_R=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_ATF=y
-CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
CONFIG_DM_RTC=y
CONFIG_RTC_ISL1208=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_X86=y
CONFIG_SYS_TEXT_BASE=0x1110000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_MAX_CPUS=2
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SPL_SPI_SUPPORT=y
CONFIG_X86_RUN_64BIT=y
CONFIG_TARGET_QEMU_X86_64=y
CONFIG_DEBUG_UART=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
-CONFIG_SPL_DM=y
CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
CONFIG_CPU=y
+CONFIG_NVME=y
CONFIG_SPL_DM_RTC=y
CONFIG_SPI=y
-CONFIG_SPL_TIMER=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN3=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77965-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN3=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77965-m3nulcb.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN3=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
-CONFIG_FIT=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
-CONFIG_SPL_ATF=y
-CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_SYS_PROMPT="rock960 => "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0xC7C0000
-CONFIG_TARGET_RSK7203=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_MISC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0xCFC0000
-CONFIG_TARGET_RSK7264=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC3,115200"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0xDFC0000
-CONFIG_TARGET_RSK7269=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC7,115200"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_TEXT_BASE=0
CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SANDBOX64=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SYS_TEXT_BASE=0
CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SYS_TEXT_BASE=0
CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SYS_TEXT_BASE=0
CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CONSOLE_RECORD=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SANDBOX_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SPMI=y
CONFIG_SPMI_SANDBOX=y
CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_CLK_FREQ=33000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SBC8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_8_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFF800000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_PCI_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_33M"
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SBC8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFF800000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_PCI_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_66M"
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SBC8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFF800000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xfff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SBC8641D=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FF80000
-CONFIG_SH_32BIT=y
-CONFIG_TARGET_SH7785LCR=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC1,115200 root=/dev/nfs ip=dhcp"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x0FF80000
-CONFIG_TARGET_SH7785LCR=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC1,115200 root=/dev/nfs ip=dhcp"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MAC_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8DFB0000
-CONFIG_TARGET_SHMIN=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_PCI=y
CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SPL_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=1
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_SPL_FS_FAT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_VERSION_VARIABLE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FPGA_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
+CONFIG_FS_LOADER=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_IS1=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="denx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MII is not set
CONFIG_CMD_CACHE=y
CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
CONFIG_DM_MMC=y
CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_PHY=y
CONFIG_PHY_STM32_USBPHYC=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_PHY=y
CONFIG_PHY_STM32_USBPHYC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)"
+CONFIG_DEFAULT_DEVICE_TREE="stmark2"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=1
# CONFIG_NET is not set
CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_CF_SPI=y
CONFIG_REGEX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
CONFIG_PCI=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider con 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider con dp 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider cpu 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider cpu dp 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_STV0991=y
CONFIG_SYS_TEXT_BASE=0x00010000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_CADENCE_QSPI=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SUVD3=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_PORTSIZE_16BIT=y
+CONFIG_BR2_MACHINE_UPMA=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_3=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_SYS_VENDOR="opalkelly"
CONFIG_SYS_CONFIG_NAME="syzygy_hub"
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
-CONFIG_SPL_SYS_THUMB_BUILD=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_AT91=y
CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x21000000
CONFIG_TARGET_TAURUS=y
+CONFIG_BOARD_TAURUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xfffff200
+CONFIG_DEBUG_UART_CLOCK=18432000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_SYS_XTRACE="n"
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DFU=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_NAND=y
+# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_MTDPARTS=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SPL_DM=y
+CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_WDT=y
CONFIG_WDT_AT91=y
CONFIG_USE_TINY_PRINTF=y
+CONFIG_HEXDUMP=y
+# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB1_VBUS_PIN="PL7"
+CONFIG_I2C0_ENABLE=y
+CONFIG_SPL_TEXT_BASE=0x10060
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i"
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+# CONFIG_USB_GADGET is not set
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
+CONFIG_SPL_SIZE_LIMIT=30720
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_TINKER_RK3288=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ARM=y
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_TQMA6S=y
CONFIG_WRU4=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=0
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_TUXX1=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_TUGE1=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="TUGE1"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_LZMADEC=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_AES=y
+CONFIG_CMD_HASH=y
CONFIG_CMD_BTRFS=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia"
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SCSI_AHCI=y
-CONFIG_ATSHA204A=y
+CONFIG_AHCI_PCI=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_DM_GPIO=y
+# CONFIG_MVEBU_GPIO is not set
+CONFIG_DM_PCA953X=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
+CONFIG_SCSI=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_WDT=y
CONFIG_WDT_ORION=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_TUXX1=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="TUXX1"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMD_UBIFS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
+CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80008000
-CONFIG_TARGET_TWISTER=y
-CONFIG_EMIF4=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL=y
-CONFIG_BOOTDELAY=10
-CONFIG_SPL_TEXT_BASE=0x40200000
-# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="twister => "
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00800000
-CONFIG_CMD_SPL_WRITE_SIZE=0x400
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_OMAP24_I2C_SPEED=400000
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_MII=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0x2C000000
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_ULPI_VIEWPORT_OMAP=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_PHY=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_OF_LIBFDT=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_SDHCI=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_USB=y
+CONFIG_USB_EHCI_MX5=y
CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x86000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_DART_6UL=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Variscite"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_LZO=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=32000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_VE8313=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_LALE_TIMING_EARLIER=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO_BCSR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="INITRAM_FLASH"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="FPGA_SRAM_NAND"
+CONFIG_BAT7_BASE=0x60000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_NAND_LBLAWBAR_PRELIM_1=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0x61000000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0x61000000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_OR1_BCTLD_NOT_ASSERTED=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_RST_ONE_CLOCK=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="NVRAM"
+CONFIG_BR2_OR2_BASE=0x60000000
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_SCY_3=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="SRAM"
+CONFIG_BR3_OR3_BASE=0x62000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_32_MBYTES=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_LCRR_EADC_3=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-vinco"
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_EFI_PARTITION=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_VME8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="UNKNOWN"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF8000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_128_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF0000000
+CONFIG_LBLAW1_NAME="WINDOW1"
+CONFIG_LBLAW1_LENGTH_256_KBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF8000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_128_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="WINDOW1"
+CONFIG_BR1_OR1_BASE=0xF0000000
+CONFIG_BR1_PORTSIZE_32BIT=y
+CONFIG_OR1_AM_256_KBYTES=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_PCI_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
CONFIG_OPTEE=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_NET is not set
CONFIG_DFU_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_WOODBURN=y
CONFIG_SYS_TEXT_BASE=0xA0000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_WOODBURN_SD=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8
CONFIG_IDENT_STRING="-SPEAr"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_SYS_BOOTCOUNT_ADDR=0xD2801FF8
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN3=y
CONFIG_SYS_I2C_DW=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_nand"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x80
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_MTD_DEVICE=y
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xfff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_XPEDITE517X=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_ENV_SIZE=0x190
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
+CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_DEBUG_UART_BASE=0x0
CONFIG_DEBUG_UART_CLOCK=0
# CONFIG_ZYNQ_DDRC_INIT is not set
-CONFIG_SYS_MALLOC_LEN=0x1000
# CONFIG_CMD_ZYNQ is not set
CONFIG_DEBUG_UART=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
guid_bin = gpt_head->disk_guid.b;
uuid_bin_to_str(guid_bin, guid, UUID_STR_FORMAT_GUID);
+ /* Remember to free pte */
+ free(gpt_pte);
return 0;
}
__func__);
return -1;
}
+
+ /* Free pte before allocating again */
+ free(*gpt_pte);
+
if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
gpt_head, gpt_pte) != 1) {
printf("%s: *** ERROR: Invalid Backup GPT ***\n",
+++ /dev/null
-LED display internal API
-=======================================
-
-This README describes the LED display API.
-
-The API is defined by the include file include/led-display.h
-
-The first step in to define CONFIG_CMD_DISPLAY in the board config file.
-Then you need to provide the following functions to access LED display:
-
-void display_set(int cmd);
-
-This function should control the state of the LED display. Argument is
-an ORed combination of the following values:
- DISPLAY_CLEAR -- clear the display
- DISPLAY_HOME -- set the position to the beginning of display
-
-int display_putc(char c);
-
-This function should display it's parameter on the LED display in the
-current position. Returns the displayed character on success or -1 in
-case of failure.
-
-With this functions defined 'display' command will display it's
-arguments on the LED display (or clear the display if called without
-arguments).
Summary
=======
-This README is about U-Boot support for TI's ARM 926EJS based family of SoCs.
-These SOCs are used for cameras, video security and surveillance, DVR's, etc.
-DaVinci SOC's comprise of DM644x, DM646x, DM35x and DM36x series of SOC's
-Additionally there are some SOCs meant for the audio market which though have
-an OMAP part number are very similar to the DaVinci series of SOC's
-Additionally, some family members contain a TI DSP and/or graphics
-co processors along with a host of other peripherals.
+Note: this document used to be about the entire family of DaVinci SOCs but the
+support for the DM* family and DA830 has since been dropped.
-Currently the following boards are supported:
-
-* TI DaVinci DM644x EVM
-
-* TI DaVinci DM646x EVM
-
-* TI DaVinci DM355 EVM
-
-* TI DaVinci DM365 EVM
+This README is about U-Boot support for TI's DA850 SoC. This SOC has an OMAP
+part number but is very similar to the DaVinci series.
-* TI DA830 EVM
+Currently the following boards are supported:
* TI DA850 EVM
-* DM355 based Leopard board
-
-* DM644x based schmoogie board
-
-* DM644x based sffsdr board
+* TI OMAP-L138 LCDK
-* DM644x based sonata board
+* Lego EV3
Build
=====
-* TI DaVinci DM644x EVM:
-
-make davinci_dvevm_config
-make
-
-* TI DaVinci DM646x EVM:
-
-make davinci_dm6467evm_config
-make
-
-* TI DaVinci DM355 EVM:
-
-make davinci_dm355evm_config
-make
-
-* TI DaVinci DM365 EVM:
-
-make davinci_dm365evm_config
-make
-
-* TI DA830 EVM:
-
-make da830evm_config
-make
-
* TI DA850 EVM:
make da850evm_config
make
-* DM355 based Leopard board:
-
-make davinci_dm355leopard_config
-make
-
-* DM644x based schmoogie board:
+* TI OMAP-L138 LCDK
-make davinci_schmoogie_config
+make omapl138_lcdk_defconfig
make
-* DM644x based sffsdr board:
+* Lego EV3
-make davinci_sffsdr_config
-make
-
-* DM644x based sonata board:
-
-make davinci_sonata_config
+make legoev3_defconfig
make
Bootloaders
===============
-The DaVinci SOC's use 2 bootloaders. The low level initialization
-is done by a UBL(user boot loader). The UBL is written to a NAND/NOR/SPI flash
-by a programmer. During initial bootup, the ROM Bootloader reads the UBL
-from a storage device and loads it into the IRAM. The UBL then loads the U-Boot
-into the RAM.
-The programmers and UBL are always released as part of any standard TI
-software release associated with an SOC.
-
-Alternative boot method (DA850 EVM only):
-For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL)
-is provided to load U-Boot directly from SPI flash. In this case, the
-SPL does the low level initialization that is otherwise done by the SPL.
-To build U-Boot with this SPL, do
-make da850evm_config
-make u-boot.ais
-and program the resulting u-boot.ais file to the SPI flash of the DA850 EVM.
+For DA850 an SPL (secondary program loader, see doc/README.SPL) is provided
+to load U-Boot directly from SPI flash. The SPL takes care of the low level
+initialization.
+
+The SPL is built as u-boot.ais for all DA850 defconfigs. The resulting
+image file can be programmed to the SPI flash of the DA850 EVM/LCDK.
Environment Variables
=====================
Links
=====
-1) TI DaVinci DM355 EVM:
-http://focus.ti.com/docs/prod/folders/print/tms320dm355.html
-http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=203&osCsid=c499af6087317f11b3da19b4e8f1af32
-
-2) TI DaVinci DM365 EVM:
-http://focus.ti.com/docs/prod/folders/print/tms320dm365.html?247SEM=
-http://support.spectrumdigital.com/boards/evmdm365/revc/
-
-3) DaVinci DM355 based leopard board
-http://designsomething.org/leopardboard/default.aspx
-http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=192&osCsid=67c20335668ffc57cb35727106eb24b1
-
-4) TI DaVinci DM6467 EVM:
-http://focus.ti.com/docs/prod/folders/print/tms320dm6467.html
-http://support.spectrumdigital.com/boards/evmdm6467/revf/
-
-5) TI DaVinci DM6446 EVM:
-http://focus.ti.com/docs/prod/folders/print/tms320dm6446.html
-http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=222
-
-6) TI DA830 EVM
-http://focus.ti.com/apps/docs/gencontent.tsp?appId=1&contentId=52385
-http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=214
-
-7) TI DA850 EVM
+1) TI DA850 EVM
http://focus.ti.com/docs/prod/folders/print/omap-l138.html
http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
+2) TI OMAP-L138 LCDK
+http://focus.ti.com/docs/prod/folders/print/omap-l138.html
+http://www.ti.com/tool/TMDXLCDK138
+
Davinci special defines
=======================
For example:
+1. To build RK3288 board:
+
CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all
-(or you can use another cross compiler if you prefer)
+ (or you can use another cross compiler if you prefer)
+
+2. To build RK3399 board:
+
+ Option 1: Package the image with Rockchip miniloader:
+
+ - Compile U-Boot
+
+ => cd /path/to/u-boot
+ => make nanopi-neo4-rk3399_defconfig
+ => make
+ => make u-boot.itb
+
+ - Get the rkbin
+
+ => git clone https://github.com/rockchip-linux/rkbin.git
+
+ - Create trust.img
+
+ => cd /path/to/rkbin
+ => ./tools/trust_merger RKTRUST/RK3399TRUST.ini
+
+ - Create uboot.img
+
+ => cd /path/to/rkbin
+ => ./tools/loaderimage --pack --uboot /path/to/u-boot/u-boot-dtb.bin uboot.img
+
+ (Get trust.img and uboot.img)
+
+ Option 2: Package the image with SPL:
+
+ - We need the Python elftools.elf.elffile library for make_fit_atf.py to work
+
+ => sudo apt-get install python-pyelftools
+
+ - Export cross compiler path for aarch64
+
+ - Compile ATF
+
+ For Puma board.
+ => git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
+ => cd arm-trusted-firmware
+ => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+
+ (copy bl31.bin into U-Boot root dir)
+ => cp build/rk3399/release/bl31/bl31.bin /path/to/u-boot/bl31-rk3399.bin
+
+ For rest of rk3399 boards.
+
+ => git clone https://github.com/ARM-software/arm-trusted-firmware.git
+ => cd arm-trusted-firmware
+
+ (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-)
+ => make realclean
+ => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
+
+ (copy bl31.elf into U-Boot root dir)
+ => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot
+
+ - Compile PMU M0 firmware
+
+ This is optional for most of the rk3399 boards and required only for Puma board.
+
+ => git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
+ => cd rk3399-cortex-m0
+
+ (export cross compiler path for Cortex-M0 PMU)
+ => make CROSS_COMPILE=arm-cortex_m0-eabi-
+
+ (copy rk3399m0.bin into U-Boot root dir)
+ => cp rk3399m0.bin /path/to/u-boot
+
+ - Compile U-Boot
+
+ => cd /path/to/u-boot
+ => make orangepi-rk3399_defconfig
+ => make
+ => make u-boot.itb
+
+ (Get spl/u-boot-spl-dtb.bin, u-boot.itb images and some boards would get
+ spl/u-boot-spl.bin since it doesn't enable CONFIG_SPL_OF_CONTROL
+
+ If TPL enabled on the target, get tpl/u-boot-tpl-dtb.bin or tpl/u-boot-tpl.bin
+ if CONFIG_TPL_OF_CONTROL not enabled)
Writing to the board with USB
=============================
truncate -s %2048 u-boot.bin
cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out
+Booting from an SD card on RK3399
+=================================
+
+To write an image that boots from an SD card (assumed to be /dev/sdc):
+
+Option 1: Package the image with Rockchip miniloader:
+
+ - Create idbloader.img
+
+ => cd /path/to/u-boot
+ => ./tools/mkimage -n rk3399 -T rksd -d /path/to/rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin idbloader.img
+ => cat /path/to/rkbin/bin/rk33/rk3399_miniloader_v1.19.bin >> idbloader.img
+
+ - Write idbloader.img at 64 sector
+
+ => sudo dd if=idbloader.img of=/dev/sdc seek=64
+
+ - Write trust.img at 24576
+
+ => sudo dd if=trust.img of=/dev/sdc seek=24576
+
+ - Write uboot.img at 16384 sector
+
+ => sudo dd if=uboot.img of=/dev/sdc seek=16384
+ => sync
+
+Put this SD (or micro-SD) card into your board and reset it. You should see
+something like:
+
+DDR Version 1.20 20190314
+In
+Channel 0: DDR3, 933MHz
+Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
+no stride
+ch 0 ddrconfig = 0x101, ddrsize = 0x20
+pmugrf_os_reg[2] = 0x10006281, stride = 0x17
+OUT
+Boot1: 2019-03-14, version: 1.19
+CPUId = 0x0
+ChipType = 0x10, 239
+mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000
+mmc: ERROR: Card did not respond to voltage select!
+emmc reinit
+mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000
+mmc: ERROR: Card did not respond to voltage select!
+emmc reinit
+mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000
+mmc: ERROR: Card did not respond to voltage select!
+SdmmcInit=2 1
+mmc0:cmd5,20
+SdmmcInit=0 0
+BootCapSize=0
+UserCapSize=60543MB
+FwPartOffset=2000 , 0
+StorageInit ok = 45266
+SecureMode = 0
+SecureInit read PBA: 0x4
+SecureInit read PBA: 0x404
+SecureInit read PBA: 0x804
+SecureInit read PBA: 0xc04
+SecureInit read PBA: 0x1004
+SecureInit read PBA: 0x1404
+SecureInit read PBA: 0x1804
+SecureInit read PBA: 0x1c04
+SecureInit ret = 0, SecureMode = 0
+atags_set_bootdev: ret:(0)
+GPT 0x3380ec0 signature is wrong
+recovery gpt...
+GPT 0x3380ec0 signature is wrong
+recovery gpt fail!
+LoadTrust Addr:0x4000
+No find bl30.bin
+Load uboot, ReadLba = 2000
+hdr 0000000003380880 + 0x0:0x88,0x41,0x3e,0x97,0xe6,0x61,0x54,0x23,0xe9,0x5a,0xd1,0x2b,0xdc,0x2f,0xf9,0x35,
+
+Load OK, addr=0x200000, size=0x9c9c0
+RunBL31 0x10000
+NOTICE: BL31: v1.3(debug):370ab80
+NOTICE: BL31: Built : 09:23:41, Mar 4 2019
+NOTICE: BL31: Rockchip release version: v1.1
+INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
+INFO: Using opteed sec cpu_context!
+INFO: boot cpu mask: 0
+INFO: plat_rockchip_pmu_init(1181): pd status 3e
+INFO: BL31: Initializing runtime services
+INFO: BL31: Initializing BL32
+INF [0x0] TEE-CORE:init_primary_helper:337: Initializing (1.1.0-195-g8f090d20 #6 Fri Dec 7 06:11:20 UTC 2018 aarch64)
+
+INF [0x0] TEE-CORE:init_primary_helper:338: Release version: 1.2
+
+INF [0x0] TEE-CORE:init_teecore:83: teecore inits done
+INFO: BL31: Preparing for EL3 exit to normal world
+INFO: Entry point address = 0x200000
+INFO: SPSR = 0x3c9
+
+
+U-Boot 2019.04-rc4-00136-gfd121f9641-dirty (Apr 16 2019 - 14:02:47 +0530)
+
+Model: FriendlyARM NanoPi NEO4
+DRAM: 1022 MiB
+MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0
+Loading Environment from MMC... *** Warning - bad CRC, using default environment
+
+In: serial@ff1a0000
+Out: serial@ff1a0000
+Err: serial@ff1a0000
+Model: FriendlyARM NanoPi NEO4
+Net: eth0: ethernet@fe300000
+Hit any key to stop autoboot: 0
+=>
+
+Option 2: Package the image with SPL:
+
+ - Prefix rk3399 header to SPL image
+
+ => cd /path/to/u-boot
+ => ./tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl-dtb.bin out
+
+ - Write prefixed SPL at 64th sector
+
+ => sudo dd if=out of=/dev/sdc seek=64
+
+ - Write U-Boot proper at 16384 sector
+
+ => sudo dd if=u-boot.itb of=/dev/sdc seek=16384
+ => sync
+
+Put this SD (or micro-SD) card into your board and reset it. You should see
+something like:
+
+U-Boot SPL board init
+Trying to boot from MMC1
+
+
+U-Boot 2019.01-00004-g14db5ee998 (Mar 11 2019 - 13:18:41 +0530)
+
+Model: Orange Pi RK3399 Board
+DRAM: 2 GiB
+MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0
+Loading Environment from MMC... OK
+In: serial@ff1a0000
+Out: serial@ff1a0000
+Err: serial@ff1a0000
+Model: Orange Pi RK3399 Board
+Net: eth0: ethernet@fe300000
+Hit any key to stop autoboot: 0
+=>
+
+Option 3: Package the image with TPL:
+
+ - Prefix rk3399 header to TPL image
+
+ => cd /path/to/u-boot
+ => ./tools/mkimage -n rk3399 -T rksd -d tpl/u-boot-tpl-dtb.bin out
+
+ - Concatinate tpl with spl
+
+ => cd /path/to/u-boot
+ => cat ./spl/u-boot-spl-dtb.bin >> out
+
+ - Write tpl+spl at 64th sector
+
+ => sudo dd if=out of=/dev/sdc seek=64
+
+ - Write U-Boot proper at 16384 sector
+
+ => sudo dd if=u-boot.itb of=/dev/sdc seek=16384
+ => sync
+
+Put this SD (or micro-SD) card into your board and reset it. You should see
+something like:
+
+U-Boot TPL board init
+Trying to boot from BOOTROM
+Returning to boot ROM...
+
+U-Boot SPL board init
+Trying to boot from MMC1
+
+
+U-Boot 2019.07-rc1-00241-g5b3244767a (May 08 2019 - 10:51:06 +0530)
+
+Model: Orange Pi RK3399 Board
+DRAM: 2 GiB
+MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0
+Loading Environment from MMC... OK
+In: serial@ff1a0000
+Out: serial@ff1a0000
+Err: serial@ff1a0000
+Model: Orange Pi RK3399 Board
+Net: eth0: ethernet@fe300000
+Hit any key to stop autoboot: 0
+=>
Using fastboot on rk3288
========================
http://rockchip.wikidot.com/partitions
--
+Jagan Teki <jagan@amarulasolutions.com>
+27 Mar 2019
Simon Glass <sjg@chromium.org>
24 June 2015
2.2. Renesas SH7722
This CPU has the SH4AL-DSP core.
- 2.3. Renesas SH7720
- This CPU has the SH3 core.
-
- 2.4. Renesas SH7710/SH7712
- This CPU has the SH3-DSP core and Ethernet controller.
-
- 2.5. Renesas SH7780
+ 2.3. Renesas SH7780
This CPU has the SH4A core.
================================================================================
I plan to support the following CPUs and boards.
5.1. CPUs
- SH7751R(SH4)
- - SH7785(SH4)
5.2. Boards
- Many boards ;-)
controlled with the environment variable "splashfile".
To enable loading the splash image from a FIT image, CONFIG_FIT must be
-enabled. Struct splash_location field 'name' should match the splash image
-name within the FIT and the FIT should start at the 'offset' field address in
-the specified storage.
+enabled. The FIT image has to start at the 'offset' field address in the
+selected splash location. The name of splash image within the FIT shall be
+specified by the environment variable "splashfile".
+
+In case the environment variable "splashfile" is not defined the default name
+'splash.bmp' will be used.
em100 -s -d filename.rom -c W25Q64CV -r
+Flash map for samus / broadwell:
+
+ fffff800 SYS_X86_START16
+ ffff0000 RESET_SEG_START
+ fffd8000 TPL_TEXT_BASE
+ fffa0000 X86_MRC_ADDR
+ fff90000 VGA_BIOS_ADDR
+ ffed0000 SYS_TEXT_BASE
+ ffea0000 X86_REFCODE_ADDR
+ ffe70000 SPL_TEXT_BASE
+ ffbf8000 CONFIG_ENV_OFFSET (environemnt offset)
+ ffbe0000 rw-mrc-cache (Memory-reference-code cache)
+ ffa00000 <spare>
+ ff801000 intel-me (address set by descriptor.bin)
+ ff800000 intel-descriptor
+
---
Intel Crown Bay specific instructions for bare mode:
STMicroelectronics STM32MP1 clock tree initialization
=====================================================
-The STM32MP clock tree initialization is based on device tree information
-for RCC IP and on fixed clocks.
+The STM32MP1 clock tree initialization is based on device tree information
+for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes.
--------------------------------
-RCC CLOCK = st,stm32mp1-rcc-clk
--------------------------------
+RCC IP = st,stm32mp1-rcc
+========================
The RCC IP is both a reset and a clock controller but this documentation only
describes the fields added for clock tree initialization which are not present
-in Linux binding.
+in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
+file.
-Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
-with Linux.
+The added properties for clock tree initialization are:
Required properties:
+- st,clksrc : The clock sources configuration array in a platform specific
+ order.
-- compatible: Should be "st,stm32mp1-rcc-clk"
+ For the STM32MP15x family there are 9 clock sources selector which are
+ configured in the following order:
+ MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
-- st,clksrc : The clock source in this order
+ Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE>
+ from dt-bindings/clock/stm32mp1-clksrc.h.
- for STM32MP15x: 9 clock sources are requested
- MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
-
- with value equals to RCC clock specifier as defined in
- dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE>
-
-- st,clkdiv : The div parameters in this order
- for STM32MP15x: 11 dividers value are requested
+ Example:
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+- st,clkdiv : The clock main dividers value specified in an array
+ in a platform specific order.
+
+ When used, it shall describe the whole clock dividers tree.
+
+ For the STM32MP15x family there are 11 dividers values expected.
+ They shall be configured in the following order:
MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
- with DIV coding defined in RCC associated register RCC_xxxDIVR
-
- most the case, it is:
+ The each divider value uses the DIV coding defined in RCC associated
+ register RCC_xxxDIVR. In most the case, it is:
0x0: not divided
0x1: division by 2
0x2: division by 4
0x3: division by 8
...
- but for RTC MCO1 MCO2, the coding is different:
+ Note that for RTC MCO1 MCO2, the coding is different:
0x0: not divided
0x1: division by 2
0x2: division by 3
0x3: division by 4
...
-Optional Properties:
-- st,pll
- PLL children node for PLL1 to PLL4 : (see ref manual for details)
- with associated index 0 to 3 (st,pll@0 to st,pll@4)
- PLLx is off when the associated node is absent
+ Example:
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
- - Sub-nodes:
+Optional Properties:
+- st,pll : A specific PLL configuration, including frequency.
- - cfg: The parameters for PLL configuration in this order:
- DIVM DIVN DIVP DIVQ DIVR Output
+ PLL children nodes for PLL1 to PLL4 (see ref manual for details)
+ are listed with associated index 0 to 3 (st,pll@0 to st,pll@3).
+ PLLx is off when the associated node is absent.
- with DIV value as defined in RCC spec:
- 0x0: bypass (division by 1)
- 0x1: division by 2
- 0x2: division by 3
- 0x3: division by 4
- ...
+ Here are the available properties for each PLL node:
- and Output = bitfield for each output value = 1:ON/0:OFF
- BIT(0) => output P : DIVPEN
- BIT(1) => output Q : DIVQEN
- BIT(2) => output R : DIVREN
- NB : macro PQR(p,q,r) can be used to build this value
- with p,p,r = 0 or 1
+ - cfg: The parameters for PLL configuration in the following order:
+ DIVM DIVN DIVP DIVQ DIVR Output.
- - frac : Fractional part of the multiplication factor
- (optional, PLL is in integer mode when absent)
+ DIVx values are defined as in RCC spec:
+ 0x0: bypass (division by 1)
+ 0x1: division by 2
+ 0x2: division by 3
+ 0x3: division by 4
+ ...
- - csg : Clock Spreading Generator (optional)
- with parameters in this order:
- MOD_PER INC_STEP SSCG_MODE
+ Output contains a bitfield for each output value (1:ON/0:OFF)
+ BIT(0) => output P : DIVPEN
+ BIT(1) => output Q : DIVQEN
+ BIT(2) => output R : DIVREN
+ NB: macro PQR(p,q,r) can be used to build this value
+ with p,q,r = 0 or 1.
+
+ - frac : Fractional part of the multiplication factor
+ (optional, PLL is in integer mode when absent).
+
+ - csg : Clock Spreading Generator (optional) with parameters in the
+ following order: MOD_PER INC_STEP SSCG_MODE.
+
+ MOD_PER: Modulation Period Adjustment
+ INC_STEP: Modulation Depth Adjustment
+ SSCG_MODE: Spread spectrum clock generator mode, with associated
+ defined from stm32mp1-clksrc.h:
+ - SSCG_MODE_CENTER_SPREAD = 0
+ - SSCG_MODE_DOWN_SPREAD = 1
+
+ Example:
+ st,pll@0 {
+ cfg = < 1 53 0 0 0 1 >;
+ frac = < 0x810 >;
+ };
+ st,pll@1 {
+ cfg = < 1 43 1 0 0 PQR(0,1,1) >;
+ csg = < 10 20 1 >;
+ };
+ st,pll@2 {
+ cfg = < 2 85 3 13 3 0 >;
+ csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
+ };
+ st,pll@3 {
+ cfg = < 2 78 4 7 9 3 >;
+ };
- * MOD_PER: Modulation Period Adjustment
- * INC_STEP: Modulation Depth Adjustment
- * SSCG_MODE: Spread spectrum clock generator mode
- you can use associated defines from stm32mp1-clksrc.h
- * SSCG_MODE_CENTER_SPREAD = 0
- * SSCG_MODE_DOWN_SPREAD = 1
+- st,pkcs : used to configure the peripherals kernel clock selection.
+ The property is a list of peripheral kernel clock source identifiers defined
+ by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file
+ dt-bindings/clock/stm32mp1-clksrc.h.
-- st,pkcs : used to configure the peripherals kernel clock selection
- containing a list of peripheral kernel clock source identifier as defined
- in the file dt-bindings/clock/stm32mp1-clksrc.h
+ st,pkcs may not list all the kernel clocks and has no ordering requirements.
Example:
+ st,pkcs = <
+ CLK_STGEN_HSE
+ CLK_CKPER_HSI
+ CLK_USBPHY_PLL2P
+ CLK_DSI_PLL2Q
+ CLK_I2C46_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ >;
- rcc: rcc@50000000 {
- compatible = "syscon", "simple-mfd";
-
- reg = <0x50000000 0x1000>;
-
- rcc_clk: rcc-clk@50000000 {
- #clock-cells = <1>;
- compatible = "st,stm32mp1-rcc-clk";
-
- st,clksrc = < CLK_MPU_PLL1P
- CLK_AXI_PLL2P
- CLK_MCU_HSI
- CLK_PLL12_HSE
- CLK_PLL3_HSE
- CLK_PLL4_HSE
- CLK_RTC_HSE
- CLK_MCO1_DISABLED
- CLK_MCO2_DISABLED
- >;
-
- st,clkdiv = <
- 1 /*MPU*/
- 0 /*AXI*/
- 0 /*MCU*/
- 1 /*APB1*/
- 1 /*APB2*/
- 1 /*APB3*/
- 1 /*APB4*/
- 5 /*APB5*/
- 23 /*RTC*/
- 0 /*MCO1*/
- 0 /*MCO2*/
- >;
-
- st,pll@0 {
- cfg = < 1 53 0 0 0 1 >;
- frac = < 0x810 >;
- };
- st,pll@1 {
- cfg = < 1 43 1 0 0 PQR(0,1,1) >;
- csg = < 10 20 1 >;
- };
- st,pll@2 {
- cfg = < 2 85 3 13 3 0 >;
- csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
- };
- st,pll@3 {
- cfg = < 2 78 4 7 9 3 >;
- };
- st,pkcs = <
- CLK_STGEN_HSE
- CLK_CKPER_HSI
- CLK_USBPHY_PLL2P
- CLK_DSI_PLL2Q
- >;
- };
- };
-
---------------------------
other clocks = fixed-clock
---------------------------
+==========================
+
The clock tree is also based on 5 fixed-clock in clocks node
used to define the state of associated ST32MP1 oscillators:
-- clk-lsi
-- clk-lse
-- clk-hsi
-- clk-hse
-- clk-csi
+ - clk-lsi
+ - clk-lse
+ - clk-hsi
+ - clk-hse
+ - clk-csi
At boot the clock tree initialization will
-- enable the oscillator present in device tree
-- disable HSI oscillator if the node is absent (always activated by bootrom)
+ - enable oscillators present in device tree
+ - disable HSI oscillator if the node is absent (always activated by bootrom)
Optional properties :
a) for external oscillator: "clk-lse", "clk-hse"
- 4 optional fields are managed
- - "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP)
- - "st,digbypass" Configure the bypass mode as full-swing digital signal
- (DIGBYP)
- - "st,css" Activate the clock security system (HSECSSON, LSECSSON)
- - "st,drive" (only for LSE) value of the drive for the oscillator
- (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h)
-
- Example board file:
+ 4 optional fields are managed
+ - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP)
+ - "st,digbypass" configures the bypass mode as full-swing digital
+ signal (DIGBYP)
+ - "st,css" activates the clock security system (HSECSSON, LSECSSON)
+ - "st,drive" (only for LSE) contains the value of the drive for the
+ oscillator (see LSEDRV_ defined in the file
+ dt-bindings/clock/stm32mp1-clksrc.h)
+ Example board file:
/ {
clocks {
clk_hse: clk-hse {
b) for internal oscillator: "clk-hsi"
- internally HSI clock is fixed to 64MHz for STM32MP157 soc
- in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
- So this clock frequency is used to compute the expected HSI_DIV
- for the clock tree initialisation
-
- ex: for HSIDIV = /1
+ Internally HSI clock is fixed to 64MHz for STM32MP157 SoC.
+ In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC
+ doc). So this clock frequency is used to compute the expected HSI_DIV
+ for the clock tree initialization.
+ Example with HSIDIV = /1:
/ {
clocks {
clk_hsi: clk-hsi {
};
};
- ex: for HSIDIV = /2
-
+ Example with HSIDIV = /2
/ {
clocks {
clk_hsi: clk-hsi {
clock-frequency = <32000000>;
};
};
+
+Example of clock tree initialization
+====================================
+
+/ {
+ clocks {
+ u-boot,dm-pre-reloc;
+ clk_hse: clk-hse {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ st,digbypass;
+ };
+
+ clk_hsi: clk-hsi {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_lse: clk-lse {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_csi: clk-csi {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000000>;
+ };
+ };
+
+ soc {
+
+ rcc: rcc@50000000 {
+ u-boot,dm-pre-reloc;
+ compatible = "st,stm32mp1-rcc", "syscon";
+ reg = <0x50000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pkcs = <
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_DISABLED
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_PLL4P
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_LSE
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_PLL4P
+ CLK_FDCAN_PLL4Q
+ CLK_SAI1_PLL3Q
+ CLK_SAI2_PLL3Q
+ CLK_SAI3_PLL3Q
+ CLK_SAI4_PLL3Q
+ CLK_RNG1_LSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSE
+ >;
+
+ /* VCO = 1300.0 MHz => P = 650 (CPU) */
+ pll1: st,pll@0 {
+ cfg = < 2 80 0 0 0 PQR(1,0,0) >;
+ frac = < 0x800 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
+ R = 533 (DDR) */
+ pll2: st,pll@1 {
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+ frac = < 0x1400 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+ pll3: st,pll@2 {
+ cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+ frac = < 0x1a04 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+ pll4: st,pll@3 {
+ cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+};
- The second index is for writing FPGA configuration data.
- resets : Phandle and reset specifier for the device's reset.
- clocks : Clocks used by the device.
+- altr,bitstream : Fit image file name for both FPGA peripheral bitstream,
+ FPGA core bitstream and full bitstream.
-Example:
+ Full bitstream, consist of peripheral bitstream and core
+ bitstream.
+
+ FPGA peripheral bitstream is used to initialize FPGA IOs,
+ PLL, IO48 and DDR. This bitstream is required to get DDR up
+ running.
+
+ FPGA core bitstream contains FPGA design which is used to
+ program FPGA CRAM and ERAM.
+
+Example: Bundles both peripheral bitstream and core bitstream into FIT image
+ called fit_spl_fpga.itb. This FIT image can be created through running
+ this command: tools/mkimage
+ -E -p 400
+ -f board/altera/arria10-socdk/fit_spl_fpga.its
+ fit_spl_fpga.itb
+
+ For details of describing structure and contents of the FIT image,
+ please refer board/altera/arria10-socdk/fit_spl_fpga.its
+
+- Examples for booting with full release or booting with early IO release, then
+ follow by entering early user mode:
fpga_mgr: fpga-mgr@ffd03000 {
compatible = "altr,socfpga-a10-fpga-mgr";
0xffcfe400 0x20>;
clocks = <&l4_mp_clk>;
resets = <&rst FPGAMGR_RESET>;
+ altr,bitstream = "fit_spl_fpga.itb";
};
info attributes:
----------------
- st,mem-name : name for DDR configuration, simple string for information
-- st,mem-speed : DDR expected speed for the setting in MHz
+- st,mem-speed : DDR expected speed for the setting in kHz
- st,mem-size : DDR mem size in byte
phyc attributes:
----------------
- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
- for STM32MP15x: 10 values are requested in this order
+ for STM32MP15x: 11 values are requested in this order
PGCR
ACIOCR
DXCCR
"ddrphycapb";
st,mem-name = "DDR3 2x4Gb 533MHz";
- st,mem-speed = <533>;
+ st,mem-speed = <533000>;
st,mem-size = <0x40000000>;
st,ctl-reg = <
value is 0, the maximum value is 1800, and it is incremented by 120ps
steps.
+ The KSZ9021 hardware supports a range of skew values from negative to
+ positive, where the specific range is property dependent. All values
+ specified in the devicetree are offset by the minimum value so they
+ can be represented as positive integers in the devicetree since it's
+ difficult to represent a negative number in the devictree.
+
+ The following 4-bit values table applies to all the skew properties:
+
+ Pad Skew Value Delay (ps) Devicetree Value
+ ------------------------------------------------------
+ 0000 -840ps 0
+ 0001 -720ps 120
+ 0010 -600ps 240
+ 0011 -480ps 360
+ 0100 -360ps 480
+ 0101 -240ps 600
+ 0110 -120ps 720
+ 0111 0ps 840
+ 1000 120ps 960
+ 1001 240ps 1080
+ 1010 360ps 1200
+ 1011 480ps 1320
+ 1100 600ps 1440
+ 1101 720ps 1560
+ 1110 840ps 1680
+ 1111 960ps 1800
+
Optional properties:
- rxc-skew-ps : Skew control of RXC pad
--- /dev/null
+Freescale ColdFire UART
+
+Required properties:
+- compatible : should be "fsl,mcf-uart"
+- reg: start address and size of the registers
+
+Example:
+
+soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@fc060000 {
+ compatible = "fsl,mcf-uart";
+ reg = <0xfc060000 0x40>;
+ status = "disabled";
+ };
+};
--- /dev/null
+Freescale ColdFire DSPI controller
+
+Required properties:
+- compatible : "fsl,mcf-dspi"
+- #address-cells: <1>, as required by generic SPI binding
+- #size-cells: <0>, also as required by generic SPI binding
+- reg : offset and length of the register set for the device
+
+Optional properties:
+- spi-max-frequency : max supported spi frequency
+- num-cs : the number of the chipselect signals
+- spi-mode: spi motorola mode, 0 to 3
+- ctar-params: CTAR0 to 7 register configuration, as an array
+ of 8 integer fields for each register, where each register
+ is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
+
+Example:
+
+dspi0: dspi@fc05c000 {
+ compatible = "fsl,mcf-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfc05c000 0x100>;
+ spi-max-frequency = <50000000>;
+ num-cs = <4>;
+ spi-mode = <0>;
+ ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>,
+ <7, 0, 0, 0, 0, 0, 1, 6>,
+ <7, 0, 0, 0, 0, 0, 1, 6>;
+};
alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
alias dinh Dinh Nguyen <dinguyen@kernel.org>
alias hs Heiko Schocher <hs@denx.de>
+alias freenix Peng Fan <peng.fan@nxp.com>
alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
alias jaehoon Jaehoon Chung <jh80.chung@samsung.com>
alias jagan Jagan Teki <jagan@amarulasolutions.com>
alias jhersh Joe Hershberger <joe.hershberger@ni.com>
+alias kevery Kever Yang <kever.yang@rock-chips.com>
alias lukma Lukasz Majewski <lukma@denx.de>
alias macpaul Macpaul Lin <macpaul@andestech.com>
alias marex Marek Vasut <marex@denx.de>
alias ti uboot, trini
alias uniphier uboot, masahiro
alias zynq uboot, monstr
-alias rockchip uboot, sjg, Kever Yang <kever.yang@rock-chips.com>, ptomsich
+alias rockchip uboot, sjg, kevery, ptomsich
alias m68k uboot, alisonwang, angelo_ts
alias coldfire m68k
alias fdt uboot, sjg
alias i2c uboot, hs
alias kconfig uboot, masahiro
-alias mmc uboot, jaehoon
+alias mmc uboot, freenix
alias nand uboot
alias net uboot, jhersh
alias phy uboot, jhersh
source "drivers/bootcount/Kconfig"
+source "drivers/cache/Kconfig"
+
source "drivers/clk/Kconfig"
source "drivers/cpu/Kconfig"
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
-obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
+obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
obj-y += block/
obj-y += board/
obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-$(CONFIG_FASTBOOT) += fastboot/
Enable this driver to support Sata devices through
Synopsys DWC AHCI module.
+config FSL_AHCI
+ bool "Enable Freescale AHCI driver support"
+ select SCSI_AHCI
+ depends on AHCI
+ depends on DM_SCSI
+ help
+ Enable this driver to support Sata devices found in
+ some Freescale PowerPC SoCs.
+
+
config DWC_AHSATA
bool "Enable DWC AHSATA driver support"
select LIBATA
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
+obj-$(CONFIG_FSL_AHCI) += fsl_ahci.o
obj-$(CONFIG_AHCI) += ahci-uclass.o
obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
return base + 0x100 + (port * 0x80);
}
-
-static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
- unsigned int port_idx)
-{
- base = ahci_port_base(base, port_idx);
-
- port->cmd_addr = base;
- port->scr_addr = base + PORT_SCR;
-}
-
-
#define msleep(a) udelay(a * 1000)
static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
continue;
uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
port_mmio = (u8 *)uc_priv->port[i].port_mmio;
- ahci_setup_port(&uc_priv->port[i], mmio, i);
/* make sure port is not active */
tmp = readl(port_mmio + PORT_CMD);
return -1;
}
- mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
+ mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
if (!mem) {
free(pp);
printf("%s: No mem for table!\n", __func__);
return -ENOMEM;
}
-
- /* Aligned to 2048-bytes */
- mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
/*
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NXP PPC SATA platform driver
+ *
+ * (C) Copyright 2019 NXP, Inc.
+ *
+ */
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <dm/lists.h>
+#include <dm.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <libata.h>
+#include <sata.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <fis.h>
+
+#include "fsl_sata.h"
+
+struct fsl_ahci_priv {
+ u32 base;
+ u32 flag;
+ u32 number;
+ fsl_sata_t *fsl_sata;
+};
+
+static int fsl_ahci_bind(struct udevice *dev)
+{
+ return device_bind_driver(dev, "fsl_ahci_scsi", "fsl_ahci_scsi", NULL);
+}
+
+static int fsl_ahci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct fsl_ahci_priv *priv = dev_get_priv(dev);
+
+ priv->number = dev_read_u32_default(dev, "sata-number", -1);
+ priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int ata_wait_register(unsigned __iomem *addr, u32 mask,
+ u32 val, u32 timeout_msec)
+{
+ int i;
+
+ for (i = 0; ((in_le32(addr) & mask) != val) && i < timeout_msec; i++)
+ mdelay(1);
+
+ return (i < timeout_msec) ? 0 : -1;
+}
+
+static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
+{
+ printf("Status FIS dump:\n\r");
+ printf("fis_type: %02x\n\r", s->fis_type);
+ printf("pm_port_i: %02x\n\r", s->pm_port_i);
+ printf("status: %02x\n\r", s->status);
+ printf("error: %02x\n\r", s->error);
+ printf("lba_low: %02x\n\r", s->lba_low);
+ printf("lba_mid: %02x\n\r", s->lba_mid);
+ printf("lba_high: %02x\n\r", s->lba_high);
+ printf("device: %02x\n\r", s->device);
+ printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
+ printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
+ printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
+ printf("res1: %02x\n\r", s->res1);
+ printf("sector_count: %02x\n\r", s->sector_count);
+ printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
+}
+
+static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
+{
+ printf("\n\rSATA: %08x\n\r", (u32)reg);
+ printf("CQR: %08x\n\r", in_le32(®->cqr));
+ printf("CAR: %08x\n\r", in_le32(®->car));
+ printf("CCR: %08x\n\r", in_le32(®->ccr));
+ printf("CER: %08x\n\r", in_le32(®->cer));
+ printf("CQR: %08x\n\r", in_le32(®->cqr));
+ printf("DER: %08x\n\r", in_le32(®->der));
+ printf("CHBA: %08x\n\r", in_le32(®->chba));
+ printf("HStatus: %08x\n\r", in_le32(®->hstatus));
+ printf("HControl: %08x\n\r", in_le32(®->hcontrol));
+ printf("CQPMP: %08x\n\r", in_le32(®->cqpmp));
+ printf("SIG: %08x\n\r", in_le32(®->sig));
+ printf("ICC: %08x\n\r", in_le32(®->icc));
+ printf("SStatus: %08x\n\r", in_le32(®->sstatus));
+ printf("SError: %08x\n\r", in_le32(®->serror));
+ printf("SControl: %08x\n\r", in_le32(®->scontrol));
+ printf("SNotification: %08x\n\r", in_le32(®->snotification));
+ printf("TransCfg: %08x\n\r", in_le32(®->transcfg));
+ printf("TransStatus: %08x\n\r", in_le32(®->transstatus));
+ printf("LinkCfg: %08x\n\r", in_le32(®->linkcfg));
+ printf("LinkCfg1: %08x\n\r", in_le32(®->linkcfg1));
+ printf("LinkCfg2: %08x\n\r", in_le32(®->linkcfg2));
+ printf("LinkStatus: %08x\n\r", in_le32(®->linkstatus));
+ printf("LinkStatus1: %08x\n\r", in_le32(®->linkstatus1));
+ printf("PhyCtrlCfg: %08x\n\r", in_le32(®->phyctrlcfg));
+ printf("SYSPR: %08x\n\r", in_be32(®->syspr));
+}
+
+static int init_sata(struct fsl_ahci_priv *priv)
+{
+ int i;
+ u32 cda;
+ u32 val32;
+ u32 sig;
+ fsl_sata_t *sata;
+ u32 length, align;
+ cmd_hdr_tbl_t *cmd_hdr;
+ fsl_sata_reg_t __iomem *reg;
+
+ int dev = priv->number;
+
+ if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
+ printf("the sata index %d is out of ranges\n\r", dev);
+ return -EINVAL;
+ }
+
+#ifdef CONFIG_MPC85xx
+ if (dev == 0 && (!is_serdes_configured(SATA1))) {
+ printf("SATA%d [dev = %d] is not enabled\n", dev + 1, dev);
+ return -EINVAL;
+ }
+ if (dev == 1 && (!is_serdes_configured(SATA2))) {
+ printf("SATA%d [dev = %d] is not enabled\n", dev + 1, dev);
+ return -EINVAL;
+ }
+#endif
+
+ /* Allocate SATA device driver struct */
+ sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
+ if (!sata) {
+ printf("alloc the sata device struct failed\n\r");
+ return -ENOMEM;
+ }
+ /* Zero all of the device driver struct */
+ memset((void *)sata, 0, sizeof(fsl_sata_t));
+
+ sata->dma_flag = priv->flag;
+ snprintf(sata->name, 12, "SATA%d", dev);
+
+ /* Set the controller register base address to device struct */
+ reg = (fsl_sata_reg_t *)priv->base;
+ sata->reg_base = reg;
+
+ /* Allocate the command header table, 4 bytes aligned */
+ length = sizeof(struct cmd_hdr_tbl);
+ align = SATA_HC_CMD_HDR_TBL_ALIGN;
+ sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
+ if (!sata->cmd_hdr_tbl_offset) {
+ printf("alloc the command header failed\n\r");
+ return -ENOMEM;
+ }
+
+ cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
+ & ~(align - 1));
+ sata->cmd_hdr = cmd_hdr;
+
+ /* Zero all of the command header table */
+ memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
+
+ /* Allocate command descriptor for all command */
+ length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
+ align = SATA_HC_CMD_DESC_ALIGN;
+ sata->cmd_desc_offset = (void *)malloc(length + align);
+ if (!sata->cmd_desc_offset) {
+ printf("alloc the command descriptor failed\n\r");
+ return -ENOMEM;
+ }
+ sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
+ & ~(align - 1));
+ /* Zero all of command descriptor */
+ memset((void *)sata->cmd_desc_offset, 0, length + align);
+
+ /* Link the command descriptor to command header */
+ for (i = 0; i < SATA_HC_MAX_CMD; i++) {
+ cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
+ & ~(CMD_HDR_CDA_ALIGN - 1);
+ cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
+ }
+
+ /* To have safe state, force the controller offline */
+ val32 = in_le32(®->hcontrol);
+ val32 &= ~HCONTROL_ONOFF;
+ val32 |= HCONTROL_FORCE_OFFLINE;
+ out_le32(®->hcontrol, val32);
+
+ /* Wait the controller offline */
+ ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
+
+ /* Set the command header base address to CHBA register to tell DMA */
+ out_le32(®->chba, (u32)cmd_hdr & ~0x3);
+
+ /* Snoop for the command header */
+ val32 = in_le32(®->hcontrol);
+ val32 |= HCONTROL_HDR_SNOOP;
+ out_le32(®->hcontrol, val32);
+
+ /* Disable all of interrupts */
+ val32 = in_le32(®->hcontrol);
+ val32 &= ~HCONTROL_INT_EN_ALL;
+ out_le32(®->hcontrol, val32);
+
+ /* Clear all of interrupts */
+ val32 = in_le32(®->hstatus);
+ out_le32(®->hstatus, val32);
+
+ /* Set the ICC, no interrupt coalescing */
+ out_le32(®->icc, 0x01000000);
+
+ /* No PM attatched, the SATA device direct connect */
+ out_le32(®->cqpmp, 0);
+
+ /* Clear SError register */
+ val32 = in_le32(®->serror);
+ out_le32(®->serror, val32);
+
+ /* Clear CER register */
+ val32 = in_le32(®->cer);
+ out_le32(®->cer, val32);
+
+ /* Clear DER register */
+ val32 = in_le32(®->der);
+ out_le32(®->der, val32);
+
+ /* No device detection or initialization action requested */
+ out_le32(®->scontrol, 0x00000300);
+
+ /* Configure the transport layer, default value */
+ out_le32(®->transcfg, 0x08000016);
+
+ /* Configure the link layer, default value */
+ out_le32(®->linkcfg, 0x0000ff34);
+
+ /* Bring the controller online */
+ val32 = in_le32(®->hcontrol);
+ val32 |= HCONTROL_ONOFF;
+ out_le32(®->hcontrol, val32);
+
+ mdelay(100);
+
+ /* print sata device name */
+ printf("%s ", sata->name);
+
+ /* Wait PHY RDY signal changed for 500ms */
+ ata_wait_register(®->hstatus, HSTATUS_PHY_RDY,
+ HSTATUS_PHY_RDY, 500);
+
+ /* Check PHYRDY */
+ val32 = in_le32(®->hstatus);
+ if (val32 & HSTATUS_PHY_RDY) {
+ sata->link = 1;
+ } else {
+ sata->link = 0;
+ printf("(No RDY)\n\r");
+ return -EINVAL;
+ }
+
+ /* Wait for signature updated, which is 1st D2H */
+ ata_wait_register(®->hstatus, HSTATUS_SIGNATURE,
+ HSTATUS_SIGNATURE, 10000);
+
+ if (val32 & HSTATUS_SIGNATURE) {
+ sig = in_le32(®->sig);
+ debug("Signature updated, the sig =%08x\n\r", sig);
+ sata->ata_device_type = ata_dev_classify(sig);
+ }
+
+ /* Check the speed */
+ val32 = in_le32(®->sstatus);
+ if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
+ printf("(1.5 Gbps)\n\r");
+ else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
+ printf("(3 Gbps)\n\r");
+
+ priv->fsl_sata = sata;
+
+ return 0;
+}
+
+static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata,
+ struct sata_fis_h2d *cfis,
+ int is_ncq, int tag,
+ u8 *buffer, u32 len)
+{
+ cmd_hdr_entry_t *cmd_hdr;
+ cmd_desc_t *cmd_desc;
+ sata_fis_h2d_t *h2d;
+ prd_entry_t *prde;
+ u32 ext_c_ddc;
+ u32 prde_count;
+ u32 val32;
+ u32 ttl;
+ u32 der;
+ int i;
+
+ fsl_sata_reg_t *reg = sata->reg_base;
+
+ /* Check xfer length */
+ if (len > SATA_HC_MAX_XFER_LEN) {
+ printf("max transfer length is 64MB\n\r");
+ return 0;
+ }
+
+ /* Setup the command descriptor */
+ cmd_desc = sata->cmd_desc + tag;
+
+ /* Get the pointer cfis of command descriptor */
+ h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
+
+ /* Zero the cfis of command descriptor */
+ memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
+
+ /* Copy the cfis from user to command descriptor */
+ h2d->fis_type = cfis->fis_type;
+ h2d->pm_port_c = cfis->pm_port_c;
+ h2d->command = cfis->command;
+
+ h2d->features = cfis->features;
+ h2d->features_exp = cfis->features_exp;
+
+ h2d->lba_low = cfis->lba_low;
+ h2d->lba_mid = cfis->lba_mid;
+ h2d->lba_high = cfis->lba_high;
+ h2d->lba_low_exp = cfis->lba_low_exp;
+ h2d->lba_mid_exp = cfis->lba_mid_exp;
+ h2d->lba_high_exp = cfis->lba_high_exp;
+
+ if (!is_ncq) {
+ h2d->sector_count = cfis->sector_count;
+ h2d->sector_count_exp = cfis->sector_count_exp;
+ } else { /* NCQ */
+ h2d->sector_count = (u8)(tag << 3);
+ }
+
+ h2d->device = cfis->device;
+ h2d->control = cfis->control;
+
+ /* Setup the PRD table */
+ prde = (prd_entry_t *)cmd_desc->prdt;
+ memset((void *)prde, 0, sizeof(struct prdt));
+
+ prde_count = 0;
+ ttl = len;
+ for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
+ if (!len)
+ break;
+ prde->dba = cpu_to_le32((u32)buffer & ~0x3);
+ debug("dba = %08x\n\r", (u32)buffer);
+
+ if (len < PRD_ENTRY_MAX_XFER_SZ) {
+ ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
+ debug("ext_c_ddc1 = %08x, len = %08x\n\r",
+ ext_c_ddc, len);
+ prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
+ prde_count++;
+ prde++;
+ } else {
+ ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
+ debug("ext_c_ddc2 = %08x, len = %08x\n\r",
+ ext_c_ddc, len);
+ prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
+ buffer += PRD_ENTRY_MAX_XFER_SZ;
+ len -= PRD_ENTRY_MAX_XFER_SZ;
+ prde_count++;
+ prde++;
+ }
+ }
+
+ /* Setup the command slot of cmd hdr */
+ cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
+
+ cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
+
+ val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
+ val32 |= sizeof(sata_fis_h2d_t);
+ cmd_hdr->prde_fis_len = cpu_to_le32(val32);
+
+ cmd_hdr->ttl = cpu_to_le32(ttl);
+
+ if (!is_ncq)
+ val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
+ else
+ val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP |
+ CMD_HDR_ATTR_FPDMA;
+
+ tag &= CMD_HDR_ATTR_TAG;
+ val32 |= tag;
+
+ debug("attribute = %08x\n\r", val32);
+ cmd_hdr->attribute = cpu_to_le32(val32);
+
+ /* Make sure cmd desc and cmd slot valid before command issue */
+ sync();
+
+ /* PMP*/
+ val32 = (u32)(h2d->pm_port_c & 0x0f);
+ out_le32(®->cqpmp, val32);
+
+ /* Wait no active */
+ if (ata_wait_register(®->car, (1 << tag), 0, 10000))
+ printf("Wait no active time out\n\r");
+
+ /* Issue command */
+ if (!(in_le32(®->cqr) & (1 << tag))) {
+ val32 = 1 << tag;
+ out_le32(®->cqr, val32);
+ }
+
+ /* Wait command completed for 10s */
+ if (ata_wait_register(®->ccr, (1 << tag), (1 << tag), 10000)) {
+ if (!is_ncq)
+ printf("Non-NCQ command time out\n\r");
+ else
+ printf("NCQ command time out\n\r");
+ }
+
+ val32 = in_le32(®->cer);
+
+ if (val32) {
+ fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
+ printf("CE at device\n\r");
+ fsl_sata_dump_regs(reg);
+ der = in_le32(®->der);
+ out_le32(®->cer, val32);
+ out_le32(®->der, der);
+ }
+
+ /* Clear complete flags */
+ val32 = in_le32(®->ccr);
+ out_le32(®->ccr, val32);
+
+ return len;
+}
+
+static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
+ enum cmd_type command_type, int tag, u8 *buffer,
+ u32 len)
+{
+ int rc;
+
+ if (tag > SATA_HC_MAX_CMD || tag < 0) {
+ printf("tag is out of range, tag=%d\n\r", tag);
+ return -1;
+ }
+
+ switch (command_type) {
+ case CMD_ATA:
+ rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
+ return rc;
+ case CMD_NCQ:
+ rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
+ return rc;
+ case CMD_ATAPI:
+ case CMD_VENDOR_BIST:
+ case CMD_BIST:
+ printf("not support now\n\r");
+ return -1;
+ default:
+ break;
+ }
+
+ return -1;
+}
+
+static void fsl_sata_identify(fsl_sata_t *sata, u16 *id)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = ATA_CMD_ID_ATA;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
+ ata_swap_buf_le16(id, ATA_ID_WORDS);
+}
+
+static void fsl_sata_xfer_mode(fsl_sata_t *sata, u16 *id)
+{
+ sata->pio = id[ATA_ID_PIO_MODES];
+ sata->mwdma = id[ATA_ID_MWDMA_MODES];
+ sata->udma = id[ATA_ID_UDMA_MODES];
+ debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio,
+ sata->mwdma, sata->udma);
+}
+
+static void fsl_sata_init_wcache(fsl_sata_t *sata, u16 *id)
+{
+ if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
+ sata->wcache = 1;
+ if (ata_id_has_flush(id))
+ sata->flush = 1;
+ if (ata_id_has_flush_ext(id))
+ sata->flush_ext = 1;
+}
+
+static void fsl_sata_set_features(fsl_sata_t *sata)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+ u8 udma_cap;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = ATA_CMD_SET_FEATURES;
+ cfis->features = SETFEATURES_XFER;
+
+ /* First check the device capablity */
+ udma_cap = (u8)(sata->udma & 0xff);
+ debug("udma_cap %02x\n\r", udma_cap);
+
+ if (udma_cap == ATA_UDMA6)
+ cfis->sector_count = XFER_UDMA_6;
+ if (udma_cap == ATA_UDMA5)
+ cfis->sector_count = XFER_UDMA_5;
+ if (udma_cap == ATA_UDMA4)
+ cfis->sector_count = XFER_UDMA_4;
+ if (udma_cap == ATA_UDMA3)
+ cfis->sector_count = XFER_UDMA_3;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
+}
+
+static u32 fsl_sata_rw_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
+ u8 *buffer, int is_write)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+ u32 block;
+
+ block = start;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
+ cfis->device = ATA_LBA;
+
+ cfis->device |= (block >> 24) & 0xf;
+ cfis->lba_high = (block >> 16) & 0xff;
+ cfis->lba_mid = (block >> 8) & 0xff;
+ cfis->lba_low = block & 0xff;
+ cfis->sector_count = (u8)(blkcnt & 0xff);
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer,
+ ATA_SECT_SIZE * blkcnt);
+ return blkcnt;
+}
+
+static void fsl_sata_flush_cache(fsl_sata_t *sata)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = ATA_CMD_FLUSH;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
+}
+
+static u32 fsl_sata_rw_cmd_ext(fsl_sata_t *sata, u32 start,
+ u32 blkcnt, u8 *buffer, int is_write)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+ u64 block;
+
+ block = (u64)start;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+
+ cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
+ : ATA_CMD_READ_EXT;
+
+ cfis->lba_high_exp = (block >> 40) & 0xff;
+ cfis->lba_mid_exp = (block >> 32) & 0xff;
+ cfis->lba_low_exp = (block >> 24) & 0xff;
+ cfis->lba_high = (block >> 16) & 0xff;
+ cfis->lba_mid = (block >> 8) & 0xff;
+ cfis->lba_low = block & 0xff;
+ cfis->device = ATA_LBA;
+ cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
+ cfis->sector_count = blkcnt & 0xff;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer,
+ ATA_SECT_SIZE * blkcnt);
+ return blkcnt;
+}
+
+static u32 fsl_sata_rw_ncq_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
+ u8 *buffer,
+ int is_write)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+ int ncq_channel;
+ u64 block;
+
+ if (sata->lba48 != 1) {
+ printf("execute FPDMA command on non-LBA48 hard disk\n\r");
+ return -1;
+ }
+
+ block = (u64)start;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+
+ cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
+ : ATA_CMD_FPDMA_READ;
+
+ cfis->lba_high_exp = (block >> 40) & 0xff;
+ cfis->lba_mid_exp = (block >> 32) & 0xff;
+ cfis->lba_low_exp = (block >> 24) & 0xff;
+ cfis->lba_high = (block >> 16) & 0xff;
+ cfis->lba_mid = (block >> 8) & 0xff;
+ cfis->lba_low = block & 0xff;
+
+ cfis->device = ATA_LBA;
+ cfis->features_exp = (blkcnt >> 8) & 0xff;
+ cfis->features = blkcnt & 0xff;
+
+ if (sata->queue_depth >= SATA_HC_MAX_CMD)
+ ncq_channel = SATA_HC_MAX_CMD - 1;
+ else
+ ncq_channel = sata->queue_depth - 1;
+
+ /* Use the latest queue */
+ fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer,
+ ATA_SECT_SIZE * blkcnt);
+ return blkcnt;
+}
+
+static void fsl_sata_flush_cache_ext(fsl_sata_t *sata)
+{
+ struct sata_fis_h2d h2d, *cfis = &h2d;
+
+ memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+ cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+ cfis->pm_port_c = 0x80; /* is command */
+ cfis->command = ATA_CMD_FLUSH_EXT;
+
+ fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
+}
+
+static u32 ata_low_level_rw_lba48(fsl_sata_t *sata, u32 blknr, lbaint_t blkcnt,
+ const void *buffer, int is_write)
+{
+ u32 start, blks;
+ u8 *addr;
+ int max_blks;
+
+ start = blknr;
+ blks = blkcnt;
+ addr = (u8 *)buffer;
+
+ max_blks = ATA_MAX_SECTORS_LBA48;
+ do {
+ if (blks > max_blks) {
+ if (sata->dma_flag != FLAGS_FPDMA)
+ fsl_sata_rw_cmd_ext(sata, start, max_blks,
+ addr, is_write);
+ else
+ fsl_sata_rw_ncq_cmd(sata, start, max_blks,
+ addr, is_write);
+ start += max_blks;
+ blks -= max_blks;
+ addr += ATA_SECT_SIZE * max_blks;
+ } else {
+ if (sata->dma_flag != FLAGS_FPDMA)
+ fsl_sata_rw_cmd_ext(sata, start, blks,
+ addr, is_write);
+ else
+ fsl_sata_rw_ncq_cmd(sata, start, blks,
+ addr, is_write);
+ start += blks;
+ blks = 0;
+ addr += ATA_SECT_SIZE * blks;
+ }
+ } while (blks != 0);
+
+ return blks;
+}
+
+static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt,
+ const void *buffer, int is_write)
+{
+ u32 start, blks;
+ u8 *addr;
+ int max_blks;
+
+ start = blknr;
+ blks = blkcnt;
+ addr = (u8 *)buffer;
+
+ max_blks = ATA_MAX_SECTORS;
+ do {
+ if (blks > max_blks) {
+ fsl_sata_rw_cmd(sata, start, max_blks, addr, is_write);
+ start += max_blks;
+ blks -= max_blks;
+ addr += ATA_SECT_SIZE * max_blks;
+ } else {
+ fsl_sata_rw_cmd(sata, start, blks, addr, is_write);
+ start += blks;
+ blks = 0;
+ addr += ATA_SECT_SIZE * blks;
+ }
+ } while (blks != 0);
+
+ return blks;
+}
+
+/*
+ * SATA interface between low level driver and command layer
+ */
+static int sata_read(fsl_sata_t *sata, ulong blknr, lbaint_t blkcnt,
+ void *buffer)
+{
+ u32 rc;
+
+ if (sata->lba48)
+ rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
+ READ_CMD);
+ else
+ rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
+ READ_CMD);
+ return rc;
+}
+
+static int sata_write(fsl_sata_t *sata, ulong blknr, lbaint_t blkcnt,
+ const void *buffer)
+{
+ u32 rc;
+
+ if (sata->lba48) {
+ rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
+ WRITE_CMD);
+ if (sata->wcache && sata->flush_ext)
+ fsl_sata_flush_cache_ext(sata);
+ } else {
+ rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
+ WRITE_CMD);
+ if (sata->wcache && sata->flush)
+ fsl_sata_flush_cache(sata);
+ }
+
+ return rc;
+}
+
+int sata_getinfo(fsl_sata_t *sata, u16 *id)
+{
+ /* if no detected link */
+ if (!sata->link)
+ return -EINVAL;
+
+#ifdef CONFIG_LBA48
+ /* Check if support LBA48 */
+ if (ata_id_has_lba48(id)) {
+ sata->lba48 = 1;
+ debug("Device support LBA48\n\r");
+ } else {
+ debug("Device supports LBA28\n\r");
+ }
+#endif
+
+ /* Get the NCQ queue depth from device */
+ sata->queue_depth = ata_id_queue_depth(id);
+
+ /* Get the xfer mode from device */
+ fsl_sata_xfer_mode(sata, id);
+
+ /* Get the write cache status from device */
+ fsl_sata_init_wcache(sata, id);
+
+ /* Set the xfer mode to highest speed */
+ fsl_sata_set_features(sata);
+
+ return 0;
+}
+
+static int fsl_scsi_exec(fsl_sata_t *sata, struct scsi_cmd *pccb,
+ bool is_write)
+{
+ int ret;
+ u32 temp;
+ u16 blocks = 0;
+ lbaint_t start = 0;
+ u8 *buffer = pccb->pdata;
+
+ /* Retrieve the base LBA number from the ccb structure. */
+ if (pccb->cmd[0] == SCSI_READ16) {
+ memcpy(&start, pccb->cmd + 2, 8);
+ start = be64_to_cpu(start);
+ } else {
+ memcpy(&temp, pccb->cmd + 2, 4);
+ start = be32_to_cpu(temp);
+ }
+
+ if (pccb->cmd[0] == SCSI_READ16)
+ blocks = (((u16)pccb->cmd[13]) << 8) | ((u16)pccb->cmd[14]);
+ else
+ blocks = (((u16)pccb->cmd[7]) << 8) | ((u16)pccb->cmd[8]);
+
+ debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
+ is_write ? "write" : "read", blocks, start);
+
+ if (is_write)
+ ret = sata_write(sata, start, blocks, buffer);
+ else
+ ret = sata_read(sata, start, blocks, buffer);
+
+ return ret;
+}
+
+static char *fsl_ata_id_strcpy(u16 *target, u16 *src, int len)
+{
+ int i;
+
+ for (i = 0; i < len / 2; i++)
+ target[i] = src[i];
+
+ return (char *)target;
+}
+
+static int fsl_ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
+ struct scsi_cmd *pccb,
+ fsl_sata_t *sata)
+{
+ u8 port;
+ u16 *idbuf;
+
+ ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
+
+ /* Clean ccb data buffer */
+ memset(pccb->pdata, 0, pccb->datalen);
+
+ if (pccb->datalen <= 35)
+ return 0;
+
+ /* Read id from sata */
+ port = pccb->target;
+
+ fsl_sata_identify(sata, (u16 *)tmpid);
+
+ if (!uc_priv->ataid[port]) {
+ uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
+ if (!uc_priv->ataid[port]) {
+ printf("%s: No memory for ataid[port]\n", __func__);
+ return -ENOMEM;
+ }
+ }
+
+ idbuf = uc_priv->ataid[port];
+
+ memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
+
+ memcpy(&pccb->pdata[8], "ATA ", 8);
+ fsl_ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
+ fsl_ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
+
+ sata_getinfo(sata, (u16 *)idbuf);
+#ifdef DEBUG
+ ata_dump_id(idbuf);
+#endif
+ return 0;
+}
+
+/*
+ * SCSI READ CAPACITY10 command operation.
+ */
+static int fsl_ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
+ struct scsi_cmd *pccb)
+{
+ u32 cap;
+ u64 cap64;
+ u32 block_size;
+
+ if (!uc_priv->ataid[pccb->target]) {
+ printf("scsi_ahci: SCSI READ CAPACITY10 command failure.");
+ printf("\tNo ATA info!\n");
+ printf("\tPlease run SCSI command INQUIRY first!\n");
+ return -EPERM;
+ }
+
+ cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
+ if (cap64 > 0x100000000ULL)
+ cap64 = 0xffffffff;
+
+ cap = cpu_to_be32(cap64);
+ memcpy(pccb->pdata, &cap, sizeof(cap));
+
+ block_size = cpu_to_be32((u32)512);
+ memcpy(&pccb->pdata[4], &block_size, 4);
+
+ return 0;
+}
+
+/*
+ * SCSI READ CAPACITY16 command operation.
+ */
+static int fsl_ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
+ struct scsi_cmd *pccb)
+{
+ u64 cap;
+ u64 block_size;
+
+ if (!uc_priv->ataid[pccb->target]) {
+ printf("scsi_ahci: SCSI READ CAPACITY16 command failure.");
+ printf("\tNo ATA info!\n");
+ printf("\tPlease run SCSI command INQUIRY first!\n");
+ return -EPERM;
+ }
+
+ cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
+ cap = cpu_to_be64(cap);
+ memcpy(pccb->pdata, &cap, sizeof(cap));
+
+ block_size = cpu_to_be64((u64)512);
+ memcpy(&pccb->pdata[8], &block_size, 8);
+
+ return 0;
+}
+
+/*
+ * SCSI TEST UNIT READY command operation.
+ */
+static int fsl_ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
+ struct scsi_cmd *pccb)
+{
+ return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
+}
+
+static int fsl_ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
+{
+ struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent);
+ struct fsl_ahci_priv *priv = dev_get_priv(dev->parent);
+ fsl_sata_t *sata = priv->fsl_sata;
+ int ret;
+
+ switch (pccb->cmd[0]) {
+ case SCSI_READ16:
+ case SCSI_READ10:
+ ret = fsl_scsi_exec(sata, pccb, 0);
+ break;
+ case SCSI_WRITE10:
+ ret = fsl_scsi_exec(sata, pccb, 1);
+ break;
+ case SCSI_RD_CAPAC10:
+ ret = fsl_ata_scsiop_read_capacity10(uc_priv, pccb);
+ break;
+ case SCSI_RD_CAPAC16:
+ ret = fsl_ata_scsiop_read_capacity16(uc_priv, pccb);
+ break;
+ case SCSI_TST_U_RDY:
+ ret = fsl_ata_scsiop_test_unit_ready(uc_priv, pccb);
+ break;
+ case SCSI_INQUIRY:
+ ret = fsl_ata_scsiop_inquiry(uc_priv, pccb, sata);
+ break;
+ default:
+ printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
+ return -ENOTSUPP;
+ }
+
+ if (ret) {
+ debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int fsl_ahci_probe(struct udevice *dev)
+{
+ struct fsl_ahci_priv *priv = dev_get_priv(dev);
+ struct udevice *child_dev;
+ struct scsi_platdata *uc_plat;
+
+ device_find_first_child(dev, &child_dev);
+ if (!child_dev)
+ return -ENODEV;
+ uc_plat = dev_get_uclass_platdata(child_dev);
+ uc_plat->base = priv->base;
+ uc_plat->max_lun = 1;
+ uc_plat->max_id = 1;
+
+ return init_sata(priv);
+}
+
+struct scsi_ops fsl_scsi_ops = {
+ .exec = fsl_ahci_scsi_exec,
+};
+
+static const struct udevice_id fsl_ahci_ids[] = {
+ { .compatible = "fsl,pq-sata-v2" },
+ { }
+};
+
+U_BOOT_DRIVER(fsl_ahci_scsi) = {
+ .name = "fsl_ahci_scsi",
+ .id = UCLASS_SCSI,
+ .ops = &fsl_scsi_ops,
+};
+
+U_BOOT_DRIVER(fsl_ahci) = {
+ .name = "fsl_ahci",
+ .id = UCLASS_AHCI,
+ .of_match = fsl_ahci_ids,
+ .bind = fsl_ahci_bind,
+ .ofdata_to_platdata = fsl_ahci_ofdata_to_platdata,
+ .probe = fsl_ahci_probe,
+ .priv_auto_alloc_size = sizeof(struct fsl_ahci_priv),
+};
int wcache;
int flush;
int flush_ext;
+ u32 dma_flag;
} fsl_sata_t;
#define READ_CMD 0
#include <ahci.h>
#include <scsi.h>
#include <asm/io.h>
+#include <linux/ioport.h>
/* Vendor Specific Register Offsets */
#define AHCI_VEND_PCFG 0xA4
#define LS1021_CEVA_PHY4_CFG 0x064a080b
#define LS1021_CEVA_PHY5_CFG 0x2aa86470
-/* for ls1088a */
-#define LS1088_ECC_DIS_ADDR_CH2 0x100520
-#define LS1088_ECC_DIS_VAL_CH2 0x40000000
-
-/* ecc addr-val pair */
-#define ECC_DIS_ADDR_CH2 0x20140520
+/* ecc val pair */
+#define ECC_DIS_VAL_CH1 0x00020000
#define ECC_DIS_VAL_CH2 0x80000000
-#define SATA_ECC_REG_ADDR 0x20220520
-#define SATA_ECC_DISABLE 0x00020000
+#define ECC_DIS_VAL_CH3 0x40000000
enum ceva_soc {
CEVA_1V84,
CEVA_LS1012A,
CEVA_LS1021A,
+ CEVA_LS1028A,
CEVA_LS1043A,
CEVA_LS1046A,
CEVA_LS1088A,
struct ceva_sata_priv {
ulong base;
+ ulong ecc_base;
enum ceva_soc soc;
ulong flag;
};
static int ceva_init_sata(struct ceva_sata_priv *priv)
{
+ ulong ecc_addr = priv->ecc_base;
ulong base = priv->base;
ulong tmp;
break;
case CEVA_LS1021A:
- writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR);
+ if (!ecc_addr)
+ return -EINVAL;
+ writel(ECC_DIS_VAL_CH1, ecc_addr);
writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
- if (priv->flag & FLAG_COHERENT)
- writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC);
break;
case CEVA_LS1012A:
case CEVA_LS1043A:
case CEVA_LS1046A:
- writel(ECC_DIS_VAL_CH2, ECC_DIS_ADDR_CH2);
+ if (!ecc_addr)
+ return -EINVAL;
+ writel(ECC_DIS_VAL_CH2, ecc_addr);
/* fallthrough */
case CEVA_LS2080A:
writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
- if (priv->flag & FLAG_COHERENT)
- writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
break;
+ case CEVA_LS1028A:
case CEVA_LS1088A:
- writel(LS1088_ECC_DIS_VAL_CH2, LS1088_ECC_DIS_ADDR_CH2);
+ if (!ecc_addr)
+ return -EINVAL;
+ writel(ECC_DIS_VAL_CH3, ecc_addr);
writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
- if (priv->flag & FLAG_COHERENT)
- writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
break;
}
+ if (priv->flag & FLAG_COHERENT)
+ writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
+
return 0;
}
{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
{ .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
+ { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
{ .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
{ .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
+ struct resource res_regs;
+ int ret;
if (dev_read_bool(dev, "dma-coherent"))
priv->flag |= FLAG_COHERENT;
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
+ ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs);
+ if (ret)
+ priv->ecc_base = 0;
+ else
+ priv->ecc_base = res_regs.start;
+
priv->soc = dev_get_driver_data(dev);
+ debug("ccsr-sata-base %lx\t ecc-base %lx\n",
+ priv->base,
+ priv->ecc_base);
+
return 0;
}
struct udevice *i2c_bus;
struct udevice *dummy;
char *listname;
- int mc4, mc2, sc, con;
+ int mc4, mc2, sc, mc2_sc, con;
int gpio_num;
int res;
return -EIO;
}
- mc2 = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy);
+ mc2_sc = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy);
mc4 = !dm_i2c_probe(i2c_bus, MC4_EXPANDER_ADDR, 0, &dummy);
- if (mc2 && mc4) {
+ if (mc2_sc && mc4) {
debug("%s: Board hardware configuration inconsistent.\n",
dev->name);
return -EINVAL;
}
- listname = mc2 ? "var-gpios-mc2" : "var-gpios-mc4";
+ listname = mc2_sc ? "var-gpios-mc2" : "var-gpios-mc4";
gpio_num = gpio_request_list_by_name(dev, listname, priv->var_gpios,
ARRAY_SIZE(priv->var_gpios),
return sc;
}
- con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]);
- if (con < 0) {
- debug("%s: Error while reading 'con' GPIO (err = %d)",
- dev->name, con);
- return con;
- }
+ mc2 = mc2_sc ? (sc ? 0 : 1) : 0;
if ((sc && mc2) || (sc && mc4) || (!sc && !mc2 && !mc4)) {
debug("%s: Board hardware configuration inconsistent.\n",
return -EINVAL;
}
+ con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]);
+ if (con < 0) {
+ debug("%s: Error while reading 'con' GPIO (err = %d)",
+ dev->name, con);
+ return con;
+ }
+
priv->variant = con ? VAR_CON : VAR_CPU;
priv->multichannel = mc4 ? 4 : (mc2 ? 2 : (sc ? 1 : 0));
--- /dev/null
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+ bool "Enable Driver Model for Cache controllers"
+ depends on DM
+ help
+ Enable driver model for cache controllers that are found on
+ most CPU's. Cache is memory that the CPU can access directly and
+ is usually located on the same chip. This uclass can be used for
+ configuring settings that be found from a device tree file.
+
+config L2X0_CACHE
+ tristate "PL310 cache driver"
+ select CACHE
+ depends on ARM
+ help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
+endmenu
--- /dev/null
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+
+#include <asm/io.h>
+#include <asm/pl310.h>
+
+static void l2c310_of_parse_and_init(struct udevice *dev)
+{
+ u32 tag[3] = { 0, 0, 0 };
+ u32 saved_reg, prefetch;
+ struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+ /* Disable the L2 Cache */
+ clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
+
+ saved_reg = readl(®s->pl310_aux_ctrl);
+ if (!dev_read_u32(dev, "prefetch-data", &prefetch)) {
+ if (prefetch)
+ saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+ else
+ saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+ }
+
+ if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
+ if (prefetch)
+ saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+ else
+ saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+ }
+
+ saved_reg |= dev_read_bool(dev, "arm,shared-override");
+ writel(saved_reg, ®s->pl310_aux_ctrl);
+
+ saved_reg = readl(®s->pl310_tag_latency_ctrl);
+ if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+ saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+ L310_LATENCY_CTRL_WR(tag[1] - 1) |
+ L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+ writel(saved_reg, ®s->pl310_tag_latency_ctrl);
+
+ saved_reg = readl(®s->pl310_data_latency_ctrl);
+ if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+ saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+ L310_LATENCY_CTRL_WR(tag[1] - 1) |
+ L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+ writel(saved_reg, ®s->pl310_data_latency_ctrl);
+
+ /* Enable the L2 cache */
+ setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+ l2c310_of_parse_and_init(dev);
+
+ return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+ { .compatible = "arm,pl310-cache" },
+ {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+ .name = "pl310_cache",
+ .id = UCLASS_CACHE,
+ .of_match = l2x0_ids,
+ .probe = l2x0_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+
+int cache_get_info(struct udevice *dev, struct cache_info *info)
+{
+ struct cache_ops *ops = cache_get_ops(dev);
+
+ if (!ops->get_info)
+ return -ENOSYS;
+
+ return ops->get_info(dev, info);
+}
+
+UCLASS_DRIVER(cache) = {
+ .id = UCLASS_CACHE,
+ .name = "cache",
+ .post_bind = dm_scan_fdt_dev,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+ info->base = 0x11223344;
+
+ return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+ .get_info = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+ { .compatible = "sandbox,cache" },
+ { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+ .name = "cache_sandbox",
+ .id = UCLASS_CACHE,
+ .of_match = sandbox_cache_ids,
+ .ops = &sandbox_cache_ops,
+};
return 0;
}
-static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
- int index, struct clk *clk)
+static int clk_get_by_index_tail(int ret, ofnode node,
+ struct ofnode_phandle_args *args,
+ const char *list_name, int index,
+ struct clk *clk)
{
- int ret;
- struct ofnode_phandle_args args;
struct udevice *dev_clk;
const struct clk_ops *ops;
- debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
-
assert(clk);
clk->dev = NULL;
+ if (ret)
+ goto err;
- ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
- index, &args);
- if (ret) {
- debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
- __func__, ret);
- return ret;
- }
-
- ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
+ ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
if (ret) {
debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
__func__, ret);
ops = clk_dev_ops(dev_clk);
if (ops->of_xlate)
- ret = ops->of_xlate(clk, &args);
+ ret = ops->of_xlate(clk, args);
else
- ret = clk_of_xlate_default(clk, &args);
+ ret = clk_of_xlate_default(clk, args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
return ret;
}
return clk_request(dev_clk, clk);
+err:
+ debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
+ __func__, ofnode_get_name(node), list_name, index, ret);
+ return ret;
+}
+
+static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
+ int index, struct clk *clk)
+{
+ int ret;
+ struct ofnode_phandle_args args;
+
+ debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
+
+ assert(clk);
+ clk->dev = NULL;
+
+ ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
+ index, &args);
+ if (ret) {
+ debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+
+ return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
+ index > 0, clk);
}
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
- return clk_get_by_indexed_prop(dev, "clocks", index, clk);
+ struct ofnode_phandle_args args;
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
+ index, &args);
+
+ return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
+ index > 0, clk);
+}
+
+int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
+{
+ struct ofnode_phandle_args args;
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
+ index > 0, &args);
+
+ return clk_get_by_index_tail(ret, node, &args, "clocks",
+ index > 0, clk);
}
int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
}
+static __maybe_unused int pll_set_rate(struct udevice *dev,
+ int pll_id,
+ int div_id,
+ unsigned long clk_rate)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+ unsigned int pllcfg[PLLCFG_NB];
+ ofnode plloff;
+ char name[12];
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ enum stm32mp1_plltype type = pll[pll_id].plltype;
+ int divm, divn, divy;
+ int ret;
+ ulong fck_ref;
+ u32 fracv;
+ u64 value;
+
+ if (div_id > _DIV_NB)
+ return -EINVAL;
+
+ sprintf(name, "st,pll@%d", pll_id);
+ plloff = dev_read_subnode(dev, name);
+ if (!ofnode_valid(plloff))
+ return -FDT_ERR_NOTFOUND;
+
+ ret = ofnode_read_u32_array(plloff, "cfg",
+ pllcfg, PLLCFG_NB);
+ if (ret < 0)
+ return -FDT_ERR_NOTFOUND;
+
+ fck_ref = pll_get_fref_ck(priv, pll_id);
+
+ divm = pllcfg[PLLCFG_M];
+ /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
+ divy = pllcfg[PLLCFG_P + div_id];
+
+ /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
+ * So same final result than PLL2 et 4
+ * with FRACV
+ * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
+ * / (DIVy + 1) * (DIVM + 1)
+ * value = (DIVN + 1) * 2^13 + FRACV / 2^13
+ * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
+ */
+ value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
+ value = lldiv(value, fck_ref);
+
+ divn = (value >> 13) - 1;
+ if (divn < DIVN_MIN ||
+ divn > stm32mp1_pll[type].divn_max) {
+ pr_err("divn invalid = %d", divn);
+ return -EINVAL;
+ }
+ fracv = value - ((divn + 1) << 13);
+ pllcfg[PLLCFG_N] = divn;
+
+ /* reconfigure PLL */
+ pll_stop(priv, pll_id);
+ pll_config(priv, pll_id, pllcfg, fracv);
+ pll_start(priv, pll_id);
+ pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
+
+ return 0;
+}
+
static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
{
u32 address = priv->base + (clksrc >> 4);
int p;
switch (clk->id) {
+#if defined(STM32MP1_CLOCK_TREE_INIT) && \
+ defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
+ case DDRPHYC:
+ break;
+#endif
case LTDC_PX:
case DSI_PX:
break;
return -EINVAL;
switch (p) {
+#if defined(STM32MP1_CLOCK_TREE_INIT) && \
+ defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
+ case _PLL2_R: /* DDRPHYC */
+ {
+ /* only for change DDR clock in interactive mode */
+ ulong result;
+
+ set_clksrc(priv, CLK_AXI_HSI);
+ result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
+ set_clksrc(priv, CLK_AXI_PLL2P);
+ return result;
+ }
+#endif
case _PLL4_Q:
/* for LTDC_PX and DSI_PX case */
return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
+
+ifdef CONFIG_CLK_IMX8
+obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
+obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
+endif
#include <dt-bindings/soc/imx_rsrc.h>
#include <misc.h>
-struct imx8_clks {
- ulong id;
- const char *name;
-};
-
-#if CONFIG_IS_ENABLED(CMD_CLK)
-static struct imx8_clks imx8_clk_names[] = {
- { IMX8QXP_A35_DIV, "A35_DIV" },
- { IMX8QXP_I2C0_CLK, "I2C0" },
- { IMX8QXP_I2C1_CLK, "I2C1" },
- { IMX8QXP_I2C2_CLK, "I2C2" },
- { IMX8QXP_I2C3_CLK, "I2C3" },
- { IMX8QXP_UART0_CLK, "UART0" },
- { IMX8QXP_UART1_CLK, "UART1" },
- { IMX8QXP_UART2_CLK, "UART2" },
- { IMX8QXP_UART3_CLK, "UART3" },
- { IMX8QXP_SDHC0_CLK, "SDHC0" },
- { IMX8QXP_SDHC1_CLK, "SDHC1" },
- { IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
- { IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
- { IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
- { IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
- { IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
- { IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
- { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
- { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
-};
-#endif
+#include "clk-imx8.h"
-static ulong imx8_clk_get_rate(struct clk *clk)
+__weak ulong imx8_clk_get_rate(struct clk *clk)
{
- sc_pm_clk_t pm_clk;
- ulong rate;
- u16 resource;
- int ret;
-
- debug("%s(#%lu)\n", __func__, clk->id);
-
- switch (clk->id) {
- case IMX8QXP_A35_DIV:
- resource = SC_R_A35;
- pm_clk = SC_PM_CLK_CPU;
- break;
- case IMX8QXP_I2C0_CLK:
- resource = SC_R_I2C_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C1_CLK:
- resource = SC_R_I2C_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C2_CLK:
- resource = SC_R_I2C_2;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C3_CLK:
- resource = SC_R_I2C_3;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_SDHC0_IPG_CLK:
- case IMX8QXP_SDHC0_CLK:
- case IMX8QXP_SDHC0_DIV:
- resource = SC_R_SDHC_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_SDHC1_IPG_CLK:
- case IMX8QXP_SDHC1_CLK:
- case IMX8QXP_SDHC1_DIV:
- resource = SC_R_SDHC_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART0_IPG_CLK:
- case IMX8QXP_UART0_CLK:
- resource = SC_R_UART_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART1_CLK:
- resource = SC_R_UART_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART2_CLK:
- resource = SC_R_UART_2;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART3_CLK:
- resource = SC_R_UART_3;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_ENET0_IPG_CLK:
- case IMX8QXP_ENET0_AHB_CLK:
- case IMX8QXP_ENET0_REF_DIV:
- case IMX8QXP_ENET0_PTP_CLK:
- resource = SC_R_ENET_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_ENET1_IPG_CLK:
- case IMX8QXP_ENET1_AHB_CLK:
- case IMX8QXP_ENET1_REF_DIV:
- case IMX8QXP_ENET1_PTP_CLK:
- resource = SC_R_ENET_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- default:
- if (clk->id < IMX8QXP_UART0_IPG_CLK ||
- clk->id >= IMX8QXP_CLK_END) {
- printf("%s(Invalid clk ID #%lu)\n",
- __func__, clk->id);
- return -EINVAL;
- }
- return -ENOTSUPP;
- };
-
- ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
- (sc_pm_clock_rate_t *)&rate);
- if (ret) {
- printf("%s err %d\n", __func__, ret);
- return ret;
- }
-
- return rate;
+ return 0;
}
-static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
{
- sc_pm_clk_t pm_clk;
- u32 new_rate = rate;
- u16 resource;
- int ret;
-
- debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
-
- switch (clk->id) {
- case IMX8QXP_I2C0_CLK:
- resource = SC_R_I2C_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C1_CLK:
- resource = SC_R_I2C_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C2_CLK:
- resource = SC_R_I2C_2;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C3_CLK:
- resource = SC_R_I2C_3;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART0_CLK:
- resource = SC_R_UART_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART1_CLK:
- resource = SC_R_UART_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART2_CLK:
- resource = SC_R_UART_2;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART3_CLK:
- resource = SC_R_UART_3;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_SDHC0_IPG_CLK:
- case IMX8QXP_SDHC0_CLK:
- case IMX8QXP_SDHC0_DIV:
- resource = SC_R_SDHC_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_SDHC1_SEL:
- case IMX8QXP_SDHC0_SEL:
- return 0;
- case IMX8QXP_SDHC1_IPG_CLK:
- case IMX8QXP_SDHC1_CLK:
- case IMX8QXP_SDHC1_DIV:
- resource = SC_R_SDHC_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_ENET0_IPG_CLK:
- case IMX8QXP_ENET0_AHB_CLK:
- case IMX8QXP_ENET0_REF_DIV:
- case IMX8QXP_ENET0_PTP_CLK:
- resource = SC_R_ENET_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_ENET1_IPG_CLK:
- case IMX8QXP_ENET1_AHB_CLK:
- case IMX8QXP_ENET1_REF_DIV:
- case IMX8QXP_ENET1_PTP_CLK:
- resource = SC_R_ENET_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- default:
- if (clk->id < IMX8QXP_UART0_IPG_CLK ||
- clk->id >= IMX8QXP_CLK_END) {
- printf("%s(Invalid clk ID #%lu)\n",
- __func__, clk->id);
- return -EINVAL;
- }
- return -ENOTSUPP;
- };
-
- ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
- if (ret) {
- printf("%s err %d\n", __func__, ret);
- return ret;
- }
-
- return new_rate;
+ return 0;
}
-static int __imx8_clk_enable(struct clk *clk, bool enable)
+__weak int __imx8_clk_enable(struct clk *clk, bool enable)
{
- sc_pm_clk_t pm_clk;
- u16 resource;
- int ret;
-
- debug("%s(#%lu)\n", __func__, clk->id);
-
- switch (clk->id) {
- case IMX8QXP_I2C0_CLK:
- resource = SC_R_I2C_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C1_CLK:
- resource = SC_R_I2C_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C2_CLK:
- resource = SC_R_I2C_2;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_I2C3_CLK:
- resource = SC_R_I2C_3;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART0_CLK:
- resource = SC_R_UART_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART1_CLK:
- resource = SC_R_UART_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART2_CLK:
- resource = SC_R_UART_2;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_UART3_CLK:
- resource = SC_R_UART_3;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_SDHC0_IPG_CLK:
- case IMX8QXP_SDHC0_CLK:
- case IMX8QXP_SDHC0_DIV:
- resource = SC_R_SDHC_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_SDHC1_IPG_CLK:
- case IMX8QXP_SDHC1_CLK:
- case IMX8QXP_SDHC1_DIV:
- resource = SC_R_SDHC_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_ENET0_IPG_CLK:
- case IMX8QXP_ENET0_AHB_CLK:
- case IMX8QXP_ENET0_REF_DIV:
- case IMX8QXP_ENET0_PTP_CLK:
- resource = SC_R_ENET_0;
- pm_clk = SC_PM_CLK_PER;
- break;
- case IMX8QXP_ENET1_IPG_CLK:
- case IMX8QXP_ENET1_AHB_CLK:
- case IMX8QXP_ENET1_REF_DIV:
- case IMX8QXP_ENET1_PTP_CLK:
- resource = SC_R_ENET_1;
- pm_clk = SC_PM_CLK_PER;
- break;
- default:
- if (clk->id < IMX8QXP_UART0_IPG_CLK ||
- clk->id >= IMX8QXP_CLK_END) {
- printf("%s(Invalid clk ID #%lu)\n",
- __func__, clk->id);
- return -EINVAL;
- }
- return -ENOTSUPP;
- }
-
- ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
- if (ret) {
- printf("%s err %d\n", __func__, ret);
- return ret;
- }
-
- return 0;
+ return -ENOTSUPP;
}
static int imx8_clk_disable(struct clk *clk)
printf("Clk\t\tHz\n");
- for (i = 0; i < ARRAY_SIZE(imx8_clk_names); i++) {
+ for (i = 0; i < num_clks; i++) {
clk.id = imx8_clk_names[i].id;
ret = clk_request(dev, &clk);
if (ret < 0) {
static const struct udevice_id imx8_clk_ids[] = {
{ .compatible = "fsl,imx8qxp-clk" },
+ { .compatible = "fsl,imx8qm-clk" },
{ },
};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+struct imx8_clks {
+ ulong id;
+ const char *name;
+};
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+extern struct imx8_clks imx8_clk_names[];
+extern int num_clks;
+#endif
+
+ulong imx8_clk_get_rate(struct clk *clk);
+ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate);
+int __imx8_clk_enable(struct clk *clk, bool enable);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/clock.h>
+#include <dt-bindings/clock/imx8qm-clock.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <misc.h>
+
+#include "clk-imx8.h"
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+struct imx8_clks imx8_clk_names[] = {
+ { IMX8QM_A53_DIV, "A53_DIV" },
+ { IMX8QM_UART0_CLK, "UART0" },
+ { IMX8QM_UART1_CLK, "UART1" },
+ { IMX8QM_UART2_CLK, "UART2" },
+ { IMX8QM_UART3_CLK, "UART3" },
+ { IMX8QM_SDHC0_CLK, "SDHC0" },
+ { IMX8QM_SDHC1_CLK, "SDHC1" },
+ { IMX8QM_SDHC2_CLK, "SDHC2" },
+ { IMX8QM_ENET0_AHB_CLK, "ENET0_AHB" },
+ { IMX8QM_ENET0_IPG_CLK, "ENET0_IPG" },
+ { IMX8QM_ENET0_REF_DIV, "ENET0_REF" },
+ { IMX8QM_ENET0_PTP_CLK, "ENET0_PTP" },
+ { IMX8QM_ENET1_AHB_CLK, "ENET1_AHB" },
+ { IMX8QM_ENET1_IPG_CLK, "ENET1_IPG" },
+ { IMX8QM_ENET1_REF_DIV, "ENET1_REF" },
+ { IMX8QM_ENET1_PTP_CLK, "ENET1_PTP" },
+};
+
+int num_clks = ARRAY_SIZE(imx8_clk_names);
+#endif
+
+ulong imx8_clk_get_rate(struct clk *clk)
+{
+ sc_pm_clk_t pm_clk;
+ ulong rate;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ switch (clk->id) {
+ case IMX8QM_A53_DIV:
+ resource = SC_R_A53;
+ pm_clk = SC_PM_CLK_CPU;
+ break;
+ case IMX8QM_I2C0_CLK:
+ resource = SC_R_I2C_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C1_CLK:
+ resource = SC_R_I2C_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C2_CLK:
+ resource = SC_R_I2C_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C3_CLK:
+ resource = SC_R_I2C_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_SDHC0_IPG_CLK:
+ case IMX8QM_SDHC0_CLK:
+ case IMX8QM_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_SDHC1_IPG_CLK:
+ case IMX8QM_SDHC1_CLK:
+ case IMX8QM_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART0_IPG_CLK:
+ case IMX8QM_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART1_CLK:
+ resource = SC_R_UART_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART2_CLK:
+ resource = SC_R_UART_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART3_CLK:
+ resource = SC_R_UART_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_ENET0_IPG_CLK:
+ case IMX8QM_ENET0_AHB_CLK:
+ case IMX8QM_ENET0_REF_DIV:
+ case IMX8QM_ENET0_PTP_CLK:
+ resource = SC_R_ENET_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_ENET1_IPG_CLK:
+ case IMX8QM_ENET1_AHB_CLK:
+ case IMX8QM_ENET1_REF_DIV:
+ case IMX8QM_ENET1_PTP_CLK:
+ resource = SC_R_ENET_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ default:
+ if (clk->id < IMX8QM_UART0_IPG_CLK ||
+ clk->id >= IMX8QM_CLK_END) {
+ printf("%s(Invalid clk ID #%lu)\n",
+ __func__, clk->id);
+ return -EINVAL;
+ }
+ return -ENOTSUPP;
+ };
+
+ ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
+ (sc_pm_clock_rate_t *)&rate);
+ if (ret) {
+ printf("%s err %d\n", __func__, ret);
+ return ret;
+ }
+
+ return rate;
+}
+
+ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ sc_pm_clk_t pm_clk;
+ u32 new_rate = rate;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ switch (clk->id) {
+ case IMX8QM_I2C0_CLK:
+ resource = SC_R_I2C_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C1_CLK:
+ resource = SC_R_I2C_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C2_CLK:
+ resource = SC_R_I2C_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C3_CLK:
+ resource = SC_R_I2C_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART1_CLK:
+ resource = SC_R_UART_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART2_CLK:
+ resource = SC_R_UART_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART3_CLK:
+ resource = SC_R_UART_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_SDHC0_IPG_CLK:
+ case IMX8QM_SDHC0_CLK:
+ case IMX8QM_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_SDHC1_IPG_CLK:
+ case IMX8QM_SDHC1_CLK:
+ case IMX8QM_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_ENET0_IPG_CLK:
+ case IMX8QM_ENET0_AHB_CLK:
+ case IMX8QM_ENET0_REF_DIV:
+ case IMX8QM_ENET0_PTP_CLK:
+ case IMX8QM_ENET0_ROOT_DIV:
+ resource = SC_R_ENET_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_ENET1_IPG_CLK:
+ case IMX8QM_ENET1_AHB_CLK:
+ case IMX8QM_ENET1_REF_DIV:
+ case IMX8QM_ENET1_PTP_CLK:
+ case IMX8QM_ENET1_ROOT_DIV:
+ resource = SC_R_ENET_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ default:
+ if (clk->id < IMX8QM_UART0_IPG_CLK ||
+ clk->id >= IMX8QM_CLK_END) {
+ printf("%s(Invalid clk ID #%lu)\n",
+ __func__, clk->id);
+ return -EINVAL;
+ }
+ return -ENOTSUPP;
+ };
+
+ ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
+ if (ret) {
+ printf("%s err %d\n", __func__, ret);
+ return ret;
+ }
+
+ return new_rate;
+}
+
+int __imx8_clk_enable(struct clk *clk, bool enable)
+{
+ sc_pm_clk_t pm_clk;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ switch (clk->id) {
+ case IMX8QM_I2C0_CLK:
+ resource = SC_R_I2C_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C1_CLK:
+ resource = SC_R_I2C_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C2_CLK:
+ resource = SC_R_I2C_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_I2C3_CLK:
+ resource = SC_R_I2C_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART1_CLK:
+ resource = SC_R_UART_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART2_CLK:
+ resource = SC_R_UART_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_UART3_CLK:
+ resource = SC_R_UART_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_SDHC0_IPG_CLK:
+ case IMX8QM_SDHC0_CLK:
+ case IMX8QM_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_SDHC1_IPG_CLK:
+ case IMX8QM_SDHC1_CLK:
+ case IMX8QM_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_ENET0_IPG_CLK:
+ case IMX8QM_ENET0_AHB_CLK:
+ case IMX8QM_ENET0_REF_DIV:
+ case IMX8QM_ENET0_PTP_CLK:
+ resource = SC_R_ENET_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QM_ENET1_IPG_CLK:
+ case IMX8QM_ENET1_AHB_CLK:
+ case IMX8QM_ENET1_REF_DIV:
+ case IMX8QM_ENET1_PTP_CLK:
+ resource = SC_R_ENET_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ default:
+ if (clk->id < IMX8QM_UART0_IPG_CLK ||
+ clk->id >= IMX8QM_CLK_END) {
+ printf("%s(Invalid clk ID #%lu)\n",
+ __func__, clk->id);
+ return -EINVAL;
+ }
+ return -ENOTSUPP;
+ }
+
+ ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
+ if (ret) {
+ printf("%s err %d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/clock.h>
+#include <dt-bindings/clock/imx8qxp-clock.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <misc.h>
+
+#include "clk-imx8.h"
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+struct imx8_clks imx8_clk_names[] = {
+ { IMX8QXP_A35_DIV, "A35_DIV" },
+ { IMX8QXP_I2C0_CLK, "I2C0" },
+ { IMX8QXP_I2C1_CLK, "I2C1" },
+ { IMX8QXP_I2C2_CLK, "I2C2" },
+ { IMX8QXP_I2C3_CLK, "I2C3" },
+ { IMX8QXP_UART0_CLK, "UART0" },
+ { IMX8QXP_UART1_CLK, "UART1" },
+ { IMX8QXP_UART2_CLK, "UART2" },
+ { IMX8QXP_UART3_CLK, "UART3" },
+ { IMX8QXP_SDHC0_CLK, "SDHC0" },
+ { IMX8QXP_SDHC1_CLK, "SDHC1" },
+ { IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
+ { IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
+ { IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
+ { IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
+ { IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
+ { IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
+ { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
+ { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
+};
+
+int num_clks = ARRAY_SIZE(imx8_clk_names);
+#endif
+
+ulong imx8_clk_get_rate(struct clk *clk)
+{
+ sc_pm_clk_t pm_clk;
+ ulong rate;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ switch (clk->id) {
+ case IMX8QXP_A35_DIV:
+ resource = SC_R_A35;
+ pm_clk = SC_PM_CLK_CPU;
+ break;
+ case IMX8QXP_I2C0_CLK:
+ resource = SC_R_I2C_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C1_CLK:
+ resource = SC_R_I2C_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C2_CLK:
+ resource = SC_R_I2C_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C3_CLK:
+ resource = SC_R_I2C_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC0_IPG_CLK:
+ case IMX8QXP_SDHC0_CLK:
+ case IMX8QXP_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC1_IPG_CLK:
+ case IMX8QXP_SDHC1_CLK:
+ case IMX8QXP_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART0_IPG_CLK:
+ case IMX8QXP_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART1_CLK:
+ resource = SC_R_UART_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART2_CLK:
+ resource = SC_R_UART_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART3_CLK:
+ resource = SC_R_UART_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_ENET0_IPG_CLK:
+ case IMX8QXP_ENET0_AHB_CLK:
+ case IMX8QXP_ENET0_REF_DIV:
+ case IMX8QXP_ENET0_PTP_CLK:
+ resource = SC_R_ENET_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_ENET1_IPG_CLK:
+ case IMX8QXP_ENET1_AHB_CLK:
+ case IMX8QXP_ENET1_REF_DIV:
+ case IMX8QXP_ENET1_PTP_CLK:
+ resource = SC_R_ENET_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ default:
+ if (clk->id < IMX8QXP_UART0_IPG_CLK ||
+ clk->id >= IMX8QXP_CLK_END) {
+ printf("%s(Invalid clk ID #%lu)\n",
+ __func__, clk->id);
+ return -EINVAL;
+ }
+ return -ENOTSUPP;
+ };
+
+ ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
+ (sc_pm_clock_rate_t *)&rate);
+ if (ret) {
+ printf("%s err %d\n", __func__, ret);
+ return ret;
+ }
+
+ return rate;
+}
+
+ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ sc_pm_clk_t pm_clk;
+ u32 new_rate = rate;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ switch (clk->id) {
+ case IMX8QXP_I2C0_CLK:
+ resource = SC_R_I2C_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C1_CLK:
+ resource = SC_R_I2C_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C2_CLK:
+ resource = SC_R_I2C_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C3_CLK:
+ resource = SC_R_I2C_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART1_CLK:
+ resource = SC_R_UART_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART2_CLK:
+ resource = SC_R_UART_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART3_CLK:
+ resource = SC_R_UART_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC0_IPG_CLK:
+ case IMX8QXP_SDHC0_CLK:
+ case IMX8QXP_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC1_SEL:
+ case IMX8QXP_SDHC0_SEL:
+ return 0;
+ case IMX8QXP_SDHC1_IPG_CLK:
+ case IMX8QXP_SDHC1_CLK:
+ case IMX8QXP_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_ENET0_IPG_CLK:
+ case IMX8QXP_ENET0_AHB_CLK:
+ case IMX8QXP_ENET0_REF_DIV:
+ case IMX8QXP_ENET0_PTP_CLK:
+ resource = SC_R_ENET_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_ENET1_IPG_CLK:
+ case IMX8QXP_ENET1_AHB_CLK:
+ case IMX8QXP_ENET1_REF_DIV:
+ case IMX8QXP_ENET1_PTP_CLK:
+ resource = SC_R_ENET_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ default:
+ if (clk->id < IMX8QXP_UART0_IPG_CLK ||
+ clk->id >= IMX8QXP_CLK_END) {
+ printf("%s(Invalid clk ID #%lu)\n",
+ __func__, clk->id);
+ return -EINVAL;
+ }
+ return -ENOTSUPP;
+ };
+
+ ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
+ if (ret) {
+ printf("%s err %d\n", __func__, ret);
+ return ret;
+ }
+
+ return new_rate;
+}
+
+int __imx8_clk_enable(struct clk *clk, bool enable)
+{
+ sc_pm_clk_t pm_clk;
+ u16 resource;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ switch (clk->id) {
+ case IMX8QXP_I2C0_CLK:
+ resource = SC_R_I2C_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C1_CLK:
+ resource = SC_R_I2C_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C2_CLK:
+ resource = SC_R_I2C_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_I2C3_CLK:
+ resource = SC_R_I2C_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART0_CLK:
+ resource = SC_R_UART_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART1_CLK:
+ resource = SC_R_UART_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART2_CLK:
+ resource = SC_R_UART_2;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_UART3_CLK:
+ resource = SC_R_UART_3;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC0_IPG_CLK:
+ case IMX8QXP_SDHC0_CLK:
+ case IMX8QXP_SDHC0_DIV:
+ resource = SC_R_SDHC_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_SDHC1_IPG_CLK:
+ case IMX8QXP_SDHC1_CLK:
+ case IMX8QXP_SDHC1_DIV:
+ resource = SC_R_SDHC_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_ENET0_IPG_CLK:
+ case IMX8QXP_ENET0_AHB_CLK:
+ case IMX8QXP_ENET0_REF_DIV:
+ case IMX8QXP_ENET0_PTP_CLK:
+ resource = SC_R_ENET_0;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ case IMX8QXP_ENET1_IPG_CLK:
+ case IMX8QXP_ENET1_AHB_CLK:
+ case IMX8QXP_ENET1_REF_DIV:
+ case IMX8QXP_ENET1_PTP_CLK:
+ resource = SC_R_ENET_1;
+ pm_clk = SC_PM_CLK_PER;
+ break;
+ default:
+ if (clk->id < IMX8QXP_UART0_IPG_CLK ||
+ clk->id >= IMX8QXP_CLK_END) {
+ printf("%s(Invalid clk ID #%lu)\n",
+ __func__, clk->id);
+ return -EINVAL;
+ }
+ return -ENOTSUPP;
+ }
+
+ ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
+ if (ret) {
+ printf("%s err %d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
struct regmap *map;
};
+static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
+ ulong rate, ulong current_rate);
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
#define NUM_CLKS 178
MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
+ MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25),
+ MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
/* Peripheral Gates */
MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
return ((parent_rate_mhz * m / n) >> od) * 1000000;
}
+static struct parm meson_pcie_pll_parm[3] = {
+ {HHI_PCIE_PLL_CNTL0, 0, 8}, /* pm */
+ {HHI_PCIE_PLL_CNTL0, 10, 5}, /* pn */
+ {HHI_PCIE_PLL_CNTL0, 16, 5}, /* pod */
+};
+
+static ulong meson_pcie_pll_get_rate(struct clk *clk)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct parm *pm, *pn, *pod;
+ unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
+ u16 n, m, od;
+ uint reg;
+
+ pm = &meson_pcie_pll_parm[0];
+ pn = &meson_pcie_pll_parm[1];
+ pod = &meson_pcie_pll_parm[2];
+
+ regmap_read(priv->map, pn->reg_off, ®);
+ n = PARM_GET(pn->width, pn->shift, reg);
+
+ regmap_read(priv->map, pm->reg_off, ®);
+ m = PARM_GET(pm->width, pm->shift, reg);
+
+ regmap_read(priv->map, pod->reg_off, ®);
+ od = PARM_GET(pod->width, pod->shift, reg);
+
+ return ((parent_rate_mhz * m / n) / 2 / od / 2) * 1000000;
+}
+
static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
{
ulong rate;
case CLKID_CLK81:
rate = meson_clk81_get_rate(clk);
break;
+ case CLKID_PCIE_PLL:
+ rate = meson_pcie_pll_get_rate(clk);
+ break;
default:
if (gates[id].reg != 0) {
/* a clock gate */
return meson_clk_get_rate_by_id(clk, clk->id);
}
+static ulong meson_pcie_pll_set_rate(struct clk *clk, ulong rate)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x30090496);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001100);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x000100c0);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000048);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000068);
+ udelay(20);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x008100c0);
+ udelay(10);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x34090496);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x14090496);
+ udelay(10);
+ regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001000);
+ regmap_update_bits(priv->map, HHI_PCIE_PLL_CNTL0,
+ 0x1f << 16, 9 << 16);
+
+ return 100000000;
+}
+
+static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
+ ulong rate, ulong current_rate)
+{
+ if (current_rate == rate)
+ return 0;
+
+ switch (id) {
+ /* Fixed clocks */
+ case CLKID_PCIE_PLL:
+ return meson_pcie_pll_set_rate(clk, rate);
+
+ default:
+ return -ENOENT;
+ }
+
+ return -EINVAL;
+}
+
+
+static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
+{
+ ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
+ int ret;
+
+ if (IS_ERR_VALUE(current_rate))
+ return current_rate;
+
+ debug("%s: setting rate of %ld from %ld to %ld\n",
+ __func__, clk->id, current_rate, rate);
+
+ ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+
+ debug("clock %lu has new rate %lu\n", clk->id,
+ meson_clk_get_rate_by_id(clk, clk->id));
+
+ return 0;
+}
+
static int meson_clk_probe(struct udevice *dev)
{
struct meson_clk *priv = dev_get_priv(dev);
.disable = meson_clk_disable,
.enable = meson_clk_enable,
.get_rate = meson_clk_get_rate,
+ .set_rate = meson_clk_set_rate,
};
static const struct udevice_id meson_clk_ids[] = {
return priv->speed[clk->id];
}
+static int mpc83xx_clk_enable(struct clk *clk)
+{
+ /* MPC83xx clocks are always enabled */
+ return 0;
+}
+
int get_clocks(void)
{
/* Empty implementation to keep the prototype in common.h happy */
const struct clk_ops mpc83xx_clk_ops = {
.request = mpc83xx_clk_request,
.get_rate = mpc83xx_clk_get_rate,
+ .enable = mpc83xx_clk_enable,
};
static const struct udevice_id mpc83xx_clk_match[] = {
#include <errno.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3036.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3036.h>
+#include <asm/arch-rockchip/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <linux/log2.h>
#include <errno.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3128.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3128.h>
+#include <asm/arch-rockchip/hardware.h>
#include <bitfield.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3128-cru.h>
#include <mapmem.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3188.h>
-#include <asm/arch/grf_rk3188.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3188.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
+#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3188-cru.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <errno.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk322x.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk322x.h>
+#include <asm/arch-rockchip/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/log2.h>
assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
- assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
+ assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
- assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
+ assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
rk_clrsetreg(&cru->cru_clksel_con[0],
BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
+ case SCLK_EMMC_SAMPLE:
con = readl(&cru->cru_clksel_con[11]);
mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
con = readl(&cru->cru_clksel_con[12]);
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
+ case SCLK_EMMC_SAMPLE:
rk_clrsetreg(&cru->cru_clksel_con[11],
EMMC_PLL_MASK,
mux << EMMC_PLL_SHIFT);
#include <mapmem.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm.h>
#include <errno.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3328.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/grf_rk3328.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3328.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/io.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3328-cru.h>
#include <mapmem.h>
#include <syscon.h>
#include <bitfield.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3368.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
+#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>
#include <syscon.h>
#include <bitfield.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3399.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3399-cru.h>
rate = rk3399_spi_get_clk(priv->cru, clk->id);
break;
case SCLK_UART0:
+ case SCLK_UART1:
case SCLK_UART2:
+ case SCLK_UART3:
return 24000000;
break;
case PCLK_HDMI_CTRL:
#include <errno.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rv1108.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rv1108.h>
+#include <asm/arch-rockchip/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rv1108-cru.h>
Supports the Power Reset Clock interface (PRCI) IP block found in
FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
enable this driver.
+
+config CLK_SIFIVE_GEMGXL_MGMT
+ bool "GEMGXL management for SiFive FU540 SoCs"
+ depends on CLK_SIFIVE
+ help
+ Supports the GEMGXL management IP block found in FU540 SoCs to
+ control GEM TX clock operation mode for 10/100/1000 Mbps.
obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o
obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o
+
+obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT) += gemgxl-mgmt.o
* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
*/
+#include <common.h>
#include <asm/io.h>
#include <clk-uclass.h>
#include <clk.h>
-#include <common.h>
#include <div64.h>
#include <dm.h>
#include <errno.h>
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/io.h>
+
+struct gemgxl_mgmt_regs {
+ __u32 tx_clk_sel;
+};
+
+struct gemgxl_mgmt_platdata {
+ struct gemgxl_mgmt_regs *regs;
+};
+
+static int gemgxl_mgmt_ofdata_to_platdata(struct udevice *dev)
+{
+ struct gemgxl_mgmt_platdata *plat = dev_get_platdata(dev);
+
+ plat->regs = (struct gemgxl_mgmt_regs *)dev_read_addr(dev);
+
+ return 0;
+}
+
+static ulong gemgxl_mgmt_set_rate(struct clk *clk, ulong rate)
+{
+ struct gemgxl_mgmt_platdata *plat = dev_get_platdata(clk->dev);
+
+ /*
+ * GEMGXL TX clock operation mode:
+ *
+ * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
+ * and output clock on GMII output signal GTX_CLK
+ * 1 = MII mode. Use MII input signal TX_CLK in TX logic
+ */
+ writel(rate != 125000000, &plat->regs->tx_clk_sel);
+
+ return 0;
+}
+
+const struct clk_ops gemgxl_mgmt_ops = {
+ .set_rate = gemgxl_mgmt_set_rate,
+};
+
+static const struct udevice_id gemgxl_mgmt_match[] = {
+ { .compatible = "sifive,cadencegemgxlmgmt0", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sifive_gemgxl_mgmt) = {
+ .name = "sifive-gemgxl-mgmt",
+ .id = UCLASS_CLK,
+ .of_match = gemgxl_mgmt_match,
+ .ofdata_to_platdata = gemgxl_mgmt_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct gemgxl_mgmt_platdata),
+ .ops = &gemgxl_mgmt_ops,
+};
return 0;
}
-int ofnode_read_u32_default(ofnode node, const char *propname, u32 def)
+u32 ofnode_read_u32_default(ofnode node, const char *propname, u32 def)
{
assert(ofnode_valid(node));
ofnode_read_u32(node, propname, &def);
return -EINVAL;
}
-fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
+fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size)
{
int na, ns;
uint flags;
prop_val = of_get_address(ofnode_to_np(node), index,
- NULL, &flags);
+ (u64 *)size, &flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
ns = ofnode_read_simple_size_cells(ofnode_get_parent(node));
return fdtdec_get_addr_size_fixed(gd->fdt_blob,
ofnode_to_offset(node), "reg",
- index, na, ns, NULL, true);
+ index, na, ns, size, true);
}
return FDT_ADDR_T_NONE;
}
+fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
+{
+ fdt_size_t size;
+
+ return ofnode_get_addr_size_index(node, index, &size);
+}
+
fdt_addr_t ofnode_get_addr(ofnode node)
{
return ofnode_get_addr_index(node, 0);
ns = of_n_size_cells(np);
*sizep = of_read_number(prop + na, ns);
- if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0)
+ if (CONFIG_IS_ENABLED(OF_TRANSLATE) && ns > 0)
return of_translate_address(np, prop);
else
return of_read_number(prop, na);
{
int ret;
- ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
+ ret = dm_scan_fdt(blob, pre_reloc_only);
if (ret) {
debug("dm_scan_fdt() failed: %d\n", ret);
return ret;
-config ALTERA_SDRAM
- bool "SoCFPGA DDR SDRAM driver"
- depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select RAM if TARGET_SOCFPGA_GEN5
- select SPL_RAM if TARGET_SOCFPGA_GEN5
+config SPL_ALTERA_SDRAM
+ bool "SoCFPGA DDR SDRAM driver in SPL"
+ depends on SPL
+ depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10
+ select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
+ select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
help
Enable DDR SDRAM controller for the SoCFPGA devices.
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
# Copyright (C) 2014 Altera Corporation <www.altera.com>
-ifdef CONFIG_ALTERA_SDRAM
+ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <div64.h>
#include <fdtdec.h>
-#include <asm/io.h>
+#include <ram.h>
+#include <reset.h>
+#include "sdram_s10.h"
#include <wait_bit.h>
#include <asm/arch/firewall_s10.h>
-#include <asm/arch/sdram_s10.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
#include <linux/sizes.h>
+struct altera_sdram_priv {
+ struct ram_info info;
+ struct reset_ctl_bulk resets;
+};
+
+struct altera_sdram_platdata {
+ void __iomem *hmc;
+ void __iomem *ddr_sch;
+ void __iomem *iomhc;
+};
+
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_system_manager *sysmgr_regs =
DDR_CONFIG(1, 4, 10, 17),
};
-static u32 hmc_readl(u32 reg)
+static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
{
- return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg)));
+ return readl(plat->iomhc + reg);
}
-static u32 hmc_ecc_readl(u32 reg)
+static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
{
- return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
+ return readl(plat->hmc + reg);
}
-static u32 hmc_ecc_writel(u32 data, u32 reg)
+static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+ u32 data, u32 reg)
{
- return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
+ return writel(data, plat->hmc + reg);
}
-static u32 ddr_sch_writel(u32 data, u32 reg)
+static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+ u32 reg)
{
- return writel(data,
- (void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg));
+ return writel(data, plat->ddr_sch + reg);
}
int match_ddr_conf(u32 ddr_conf)
return 0;
}
-static int emif_clear(void)
+static int emif_clear(struct altera_sdram_platdata *plat)
{
- hmc_ecc_writel(0, RSTHANDSHAKECTRL);
+ hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
- return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
+ return wait_for_bit_le32((const void *)(plat->hmc +
RSTHANDSHAKESTAT),
DDR_HMC_RSTHANDSHAKE_MASK,
false, 1000, false);
}
-static int emif_reset(void)
+static int emif_reset(struct altera_sdram_platdata *plat)
{
u32 c2s, s2c, ret;
- c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
- s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
+ c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
+ s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
- c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1),
- hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS));
+ c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
+ hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
+ hmc_readl(plat, DRAMSTS));
- if (s2c && emif_clear()) {
+ if (s2c && emif_clear(plat)) {
printf("DDR: emif_clear() failed\n");
return -1;
}
debug("DDR: Triggerring emif reset\n");
- hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
+ hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
/* if seq2core[3] = 0, we are good */
- ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
+ ret = wait_for_bit_le32((const void *)(plat->hmc +
RSTHANDSHAKESTAT),
DDR_HMC_SEQ2CORE_INT_RESP_MASK,
false, 1000, false);
return ret;
}
- ret = emif_clear();
+ ret = emif_clear(plat);
if (ret) {
printf("DDR: emif_clear() failed\n");
return ret;
debug("DDR: SDRAM size check passed!\n");
}
+/**
+ * sdram_calculate_size() - Calculate SDRAM size
+ *
+ * Calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ */
+static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
+{
+ u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
+
+ phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+ DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
+ DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
+ DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
+ DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
+
+ size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
+ DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
+
+ return size;
+}
+
/**
* sdram_mmr_init_full() - Function to initialize SDRAM MMR
*
* Initialize the SDRAM MMR.
*/
-int sdram_mmr_init_full(unsigned int unused)
+static int sdram_mmr_init_full(struct udevice *dev)
{
+ struct altera_sdram_platdata *plat = dev->platdata;
+ struct altera_sdram_priv *priv = dev_get_priv(dev);
u32 update_value, io48_value, ddrioctl;
u32 i;
int ret;
return -1;
}
- /* release DDR scheduler from reset */
- socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
-
/* Try 3 times to do a calibration */
for (i = 0; i < 3; i++) {
- ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
+ ret = wait_for_bit_le32((const void *)(plat->hmc +
DDRCALSTAT),
DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
false);
if (!ret)
break;
- emif_reset();
+ emif_reset(plat);
}
if (ret) {
}
debug("DDR: Calibration success\n");
- u32 ctrlcfg0 = hmc_readl(CTRLCFG0);
- u32 ctrlcfg1 = hmc_readl(CTRLCFG1);
- u32 dramaddrw = hmc_readl(DRAMADDRW);
- u32 dramtim0 = hmc_readl(DRAMTIMING0);
- u32 caltim0 = hmc_readl(CALTIMING0);
- u32 caltim1 = hmc_readl(CALTIMING1);
- u32 caltim2 = hmc_readl(CALTIMING2);
- u32 caltim3 = hmc_readl(CALTIMING3);
- u32 caltim4 = hmc_readl(CALTIMING4);
- u32 caltim9 = hmc_readl(CALTIMING9);
+ u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
+ u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
+ u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
+ u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
+ u32 caltim0 = hmc_readl(plat, CALTIMING0);
+ u32 caltim1 = hmc_readl(plat, CALTIMING1);
+ u32 caltim2 = hmc_readl(plat, CALTIMING2);
+ u32 caltim3 = hmc_readl(plat, CALTIMING3);
+ u32 caltim4 = hmc_readl(plat, CALTIMING4);
+ u32 caltim9 = hmc_readl(plat, CALTIMING9);
/*
* Configure the DDR IO size [0xFFCFB008]
* bit[9:6] = Minor Release #
* bit[14:10] = Major Release #
*/
- update_value = hmc_readl(NIOSRESERVED0);
- hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL);
- ddrioctl = hmc_ecc_readl(DDRIOCTRL);
+ update_value = hmc_readl(plat, NIOSRESERVED0);
+ hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
+ ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
/* enable HPS interface to HMC */
- hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
+ hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
/* Set the DDR Configuration */
io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
update_value = match_ddr_conf(io48_value);
if (update_value)
- ddr_sch_writel(update_value, DDR_SCH_DDRCONF);
+ ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
/* Configure HMC dramaddrw */
- hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH);
+ hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
/*
* Configure DDR timing
CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
CALTIMING4_CFG_PCH_TO_VALID(caltim4));
- ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
+ ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
(update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
(io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
DDR_SCH_DDRTIMING);
/* Configure DDR mode [precharge = 0] */
- ddr_sch_writel(((ddrioctl ? 0 : 1) <<
+ ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
DDR_SCH_DDRMODE);
/* Configure the read latency */
- ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
+ ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
DDR_READ_LATENCY_DELAY,
DDR_SCH_READ_LATENCY);
* Configuring timing values concerning activate commands
* [FAWBANK alway 1 because always 4 bank DDR]
*/
- ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
+ ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
DDR_SCH_ACTIVATE_RRD_OFF) |
(CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
DDR_SCH_ACTIVATE_FAW_OFF) |
* Configuring timing values concerning device to device data bus
* ownership change
*/
- ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
+ ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
(CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
DDR_SCH_DEVTODEV);
/* assigning the SDRAM size */
- unsigned long long size = sdram_calculate_size();
+ unsigned long long size = sdram_calculate_size(plat);
/* If the size is invalid, use default Config size */
if (size <= 0)
hw_size = PHYS_SDRAM_1_SIZE;
/* Enable or disable the SDRAM ECC */
if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
- setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
+ setbits_le32(plat->hmc + ECCCTRL1,
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
- clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
+ clrbits_le32(plat->hmc + ECCCTRL1,
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
- setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
+ setbits_le32(plat->hmc + ECCCTRL2,
(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
- writel(DDR_HMC_ERRINTEN_INTMASK,
- SOCFPGA_SDR_ADDRESS + ERRINTENS);
+ hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
/* Enable non-secure writes to HMC Adapter for SDRAM ECC */
writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
if (!cpu_has_been_warmreset())
sdram_init_ecc_bits(&bd);
} else {
- clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
+ clrbits_le32(plat->hmc + ECCCTRL1,
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
- clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
+ clrbits_le32(plat->hmc + ECCCTRL2,
(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
}
sdram_size_check(&bd);
+ priv->info.base = bd.bi_dram[0].start;
+ priv->info.size = gd->ram_size;
+
debug("DDR: HMC init success\n");
return 0;
}
-/**
- * sdram_calculate_size() - Calculate SDRAM size
- *
- * Calculate SDRAM device size based on SDRAM controller parameters.
- * Size is specified in bytes.
- */
-phys_size_t sdram_calculate_size(void)
+static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
{
- u32 dramaddrw = hmc_readl(DRAMADDRW);
+ struct altera_sdram_platdata *plat = dev->platdata;
+ fdt_addr_t addr;
- phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
- DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
- DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
- DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
- DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->ddr_sch = (void __iomem *)addr;
- size *= (2 << (hmc_ecc_readl(DDRIOCTRL) &
- DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->iomhc = (void __iomem *)addr;
- return size;
+ addr = dev_read_addr_index(dev, 2);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->hmc = (void __iomem *)addr;
+
+ return 0;
}
+
+static int altera_sdram_probe(struct udevice *dev)
+{
+ int ret;
+ struct altera_sdram_priv *priv = dev_get_priv(dev);
+
+ ret = reset_get_bulk(dev, &priv->resets);
+ if (ret) {
+ dev_err(dev, "Can't get reset: %d\n", ret);
+ return -ENODEV;
+ }
+ reset_deassert_bulk(&priv->resets);
+
+ if (sdram_mmr_init_full(dev) != 0) {
+ puts("SDRAM init failed.\n");
+ goto failed;
+ }
+
+ return 0;
+
+failed:
+ reset_release_bulk(&priv->resets);
+ return -ENODEV;
+}
+
+static int altera_sdram_get_info(struct udevice *dev,
+ struct ram_info *info)
+{
+ struct altera_sdram_priv *priv = dev_get_priv(dev);
+
+ info->base = priv->info.base;
+ info->size = priv->info.size;
+
+ return 0;
+}
+
+static struct ram_ops altera_sdram_ops = {
+ .get_info = altera_sdram_get_info,
+};
+
+static const struct udevice_id altera_sdram_ids[] = {
+ { .compatible = "altr,sdr-ctl-s10" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(altera_sdram) = {
+ .name = "altr_sdr_ctl",
+ .id = UCLASS_RAM,
+ .of_match = altera_sdram_ids,
+ .ops = &altera_sdram_ops,
+ .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
+ .probe = altera_sdram_probe,
+ .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _SDRAM_S10_H_
+#define _SDRAM_S10_H_
+
+#define DDR_TWR 15
+#define DDR_READ_LATENCY_DELAY 40
+#define DDR_ACTIVATE_FAWBANK 0x1
+
+/* ECC HMC registers */
+#define DDRIOCTRL 0x8
+#define DDRCALSTAT 0xc
+#define DRAMADDRWIDTH 0xe0
+#define ECCCTRL1 0x100
+#define ECCCTRL2 0x104
+#define ERRINTEN 0x110
+#define ERRINTENS 0x114
+#define INTMODE 0x11c
+#define INTSTAT 0x120
+#define AUTOWB_CORRADDR 0x138
+#define ECC_REG2WRECCDATABUS 0x144
+#define ECC_DIAGON 0x150
+#define ECC_DECSTAT 0x154
+#define HPSINTFCSEL 0x210
+#define RSTHANDSHAKECTRL 0x214
+#define RSTHANDSHAKESTAT 0x218
+
+#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003
+#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0)
+#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
+#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8)
+#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0)
+#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8)
+#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0)
+#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16)
+#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0)
+#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0)
+#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1)
+#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0)
+#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
+#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
+#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
+#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
+#define DDR_HMC_CORE2SEQ_INT_REQ 0xF
+#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
+#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
+
+#define DDR_HMC_ERRINTEN_INTMASK \
+ (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \
+ DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
+
+/* NOC DDR scheduler */
+#define DDR_SCH_ID_COREID 0
+#define DDR_SCH_ID_REVID 0x4
+#define DDR_SCH_DDRCONF 0x8
+#define DDR_SCH_DDRTIMING 0xc
+#define DDR_SCH_DDRMODE 0x10
+#define DDR_SCH_READ_LATENCY 0x14
+#define DDR_SCH_ACTIVATE 0x38
+#define DDR_SCH_DEVTODEV 0x3c
+#define DDR_SCH_DDR4TIMING 0x40
+
+#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0
+#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6
+#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12
+#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18
+#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21
+#define DDR_SCH_DDRTIMING_WRTORD_OFF 26
+#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31
+#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1
+#define DDR_SCH_ACTIVATE_RRD_OFF 0
+#define DDR_SCH_ACTIVATE_FAW_OFF 4
+#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10
+#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0
+#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2
+#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
+
+/* HMC MMR IO48 registers */
+#define CTRLCFG0 0x28
+#define CTRLCFG1 0x2c
+#define DRAMTIMING0 0x50
+#define CALTIMING0 0x7c
+#define CALTIMING1 0x80
+#define CALTIMING2 0x84
+#define CALTIMING3 0x88
+#define CALTIMING4 0x8c
+#define CALTIMING9 0xa0
+#define DRAMADDRW 0xa8
+#define DRAMSTS 0xec
+#define NIOSRESERVED0 0x110
+#define NIOSRESERVED1 0x114
+#define NIOSRESERVED2 0x118
+
+#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
+ (((x) >> 0) & 0x1F)
+#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
+ (((x) >> 5) & 0x1F)
+#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
+ (((x) >> 10) & 0xF)
+#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
+ (((x) >> 14) & 0x3)
+#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
+ (((x) >> 16) & 0x7)
+
+#define CTRLCFG0_CFG_MEMTYPE(x) \
+ (((x) >> 0) & 0xF)
+#define CTRLCFG0_CFG_DIMM_TYPE(x) \
+ (((x) >> 4) & 0x7)
+#define CTRLCFG0_CFG_AC_POS(x) \
+ (((x) >> 7) & 0x3)
+#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
+ (((x) >> 9) & 0x1F)
+
+#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
+ (((x) >> 0) & 0x1F)
+#define CTRLCFG1_CFG_ADDR_ORDER(x) \
+ (((x) >> 5) & 0x3)
+#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
+ (((x) >> 7) & 0x1)
+
+#define DRAMTIMING0_CFG_TCL(x) \
+ (((x) >> 0) & 0x7F)
+
+#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
+ (((x) >> 0) & 0x3F)
+#define CALTIMING0_CFG_ACT_TO_PCH(x) \
+ (((x) >> 6) & 0x3F)
+#define CALTIMING0_CFG_ACT_TO_ACT(x) \
+ (((x) >> 12) & 0x3F)
+#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
+ (((x) >> 18) & 0x3F)
+
+#define CALTIMING1_CFG_RD_TO_RD(x) \
+ (((x) >> 0) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
+ (((x) >> 6) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
+ (((x) >> 12) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_WR(x) \
+ (((x) >> 18) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_WR_DC(x) \
+ (((x) >> 24) & 0x3F)
+
+#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
+ (((x) >> 0) & 0x3F)
+#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
+ (((x) >> 6) & 0x3F)
+#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
+ (((x) >> 12) & 0x3F)
+#define CALTIMING2_CFG_WR_TO_WR(x) \
+ (((x) >> 18) & 0x3F)
+#define CALTIMING2_CFG_WR_TO_WR_DC(x) \
+ (((x) >> 24) & 0x3F)
+
+#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
+ (((x) >> 0) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_RD(x) \
+ (((x) >> 6) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
+ (((x) >> 12) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_RD_DB(x) \
+ (((x) >> 18) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_PCH(x) \
+ (((x) >> 24) & 0x3F)
+
+#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
+ (((x) >> 0) & 0x3F)
+#define CALTIMING4_CFG_PCH_TO_VALID(x) \
+ (((x) >> 6) & 0x3F)
+#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
+ (((x) >> 12) & 0x3F)
+#define CALTIMING4_CFG_ARF_TO_VALID(x) \
+ (((x) >> 18) & 0xFF)
+#define CALTIMING4_CFG_PDN_TO_VALID(x) \
+ (((x) >> 26) & 0x3F)
+
+#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
+ (((x) >> 0) & 0xFF)
+
+/* Firewall DDR scheduler MPFE */
+#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
+#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
+
+#endif /* _SDRAM_S10_H_ */
* 0x80_8000_0000 ~ 0xff_ffff_ffff
*/
#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#ifdef CONFIG_MPC83xx
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#else
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
#endif
+#endif
#ifdef CONFIG_PPC
#include <asm/fsl_law.h>
+menu "i.MX8M DDR controllers"
+ depends on ARCH_IMX8M
+
config IMX8M_DRAM
bool "imx8m dram"
info into memory for low power use. OCRAM_S is used for this
purpose on i.MX8MM.
default 0x180000
+endmenu
return tmp;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
{
uint32_t addr;
pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id);
- if (udma_is_chan_running(uc)) {
- dev_warn(ud->dev, "chan%d: tchan%d is running!\n", uc->id,
- uc->tchan->id);
- udma_stop(uc);
- if (udma_is_chan_running(uc))
- dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
- }
-
return 0;
}
pr_debug("chan%d: got rchan%d\n", uc->id, uc->rchan->id);
- if (udma_is_chan_running(uc)) {
- dev_warn(ud->dev, "chan%d: rchan%d is running!\n", uc->id,
- uc->rchan->id);
- udma_stop(uc);
- if (udma_is_chan_running(uc))
- dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
- }
-
return 0;
}
pr_debug("chan%d: got t/rchan%d pair\n", uc->id, chan_id);
- if (udma_is_chan_running(uc)) {
- dev_warn(ud->dev, "chan%d: t/rchan%d pair is running!\n",
- uc->id, chan_id);
- udma_stop(uc);
- if (udma_is_chan_running(uc))
- dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
- }
-
return 0;
}
}
}
+ if (udma_is_chan_running(uc)) {
+ dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
+ udma_stop(uc);
+ if (udma_is_chan_running(uc)) {
+ dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
+ goto err_free_res;
+ }
+ }
+
/* PSI-L pairing */
ret = udma_navss_psil_pair(ud, uc->src_thread, uc->dst_thread);
if (ret) {
u32 tc_ring_id;
int ret;
- if (!metadata)
+ if (metadata)
packet_data = *((struct ti_udma_drv_packet_data *)metadata);
if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
int ret;
/* Receive the response */
- ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_ms);
+ ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_ms * 1000);
if (ret) {
dev_err(info->dev, "%s: Message receive failed. ret = %d\n",
__func__, ret);
info = handle_to_ti_sci_info(handle);
- xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_VERSION, 0x0,
+ xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_VERSION,
+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&hdr, sizeof(struct ti_sci_msg_hdr),
sizeof(*rev_info));
if (IS_ERR(xfer)) {
info = handle_to_ti_sci_info(handle);
- /* Response is expected, so need of any flags */
- xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_GET_DEVICE_STATE, 0,
+ xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_GET_DEVICE_STATE,
+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
info = handle_to_ti_sci_info(handle);
- xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_FWL_GET,
- TISCI_MSG_FWL_CHANGE_OWNER,
+ xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_FWL_CHANGE_OWNER,
+ TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
*/
-
#include <asm/io.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/sdram.h>
#include <asm/arch/misc.h>
#include <altera.h>
+#include <asm/arch/pinmux.h>
#include <common.h>
+#include <dm/ofnode.h>
#include <errno.h>
+#include <fs_loader.h>
#include <wait_bit.h>
#include <watchdog.h>
#define COMPRESSION_OFFSET 229
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
#define FPGA_TIMEOUT_CNT 0x1000000
+#define DEFAULT_DDR_LOAD_ADDRESS 0x400
+
+DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_fpga_manager *fpga_manager_base =
(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
1, FPGA_TIMEOUT_MSEC, false);
}
-static int is_fpgamgr_early_user_mode(void)
+int is_fpgamgr_early_user_mode(void)
{
return (readl(&fpga_manager_base->imgcfg_stat) &
ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
i++;
}
- debug("Additional %i sync word needed\n", i);
+ debug("FPGA: Additional %i sync word needed\n", i);
/* restoring original CDRATIO */
fpgamgr_set_cd_ratio(cd_ratio);
compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
compress = !compress;
- debug("header word %d = %08x\n", 69, rbf_data[69]);
- debug("header word %d = %08x\n", 229, rbf_data[229]);
- debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
+ debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
+ debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
+ debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
+ compress);
/*
* from the register map description of cdratio in imgcfg_ctrl_02:
printf("nstatus == 0 while waiting for condone\n");
return -EPERM;
}
+ WATCHDOG_RESET();
}
if (i == FPGA_TIMEOUT_CNT)
printf("FPGA: Poll CD failed with error code %d\n", status);
return -EPERM;
}
- WATCHDOG_RESET();
/* Ensure the FPGA entering user mode */
status = fpgamgr_program_poll_usermode();
return 0;
}
-/*
- * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
+ofnode get_fpga_mgr_ofnode(ofnode from)
+{
+ return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
+}
+
+const char *get_fpga_filename(void)
+{
+ const char *fpga_filename = NULL;
+
+ ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
+
+ if (ofnode_valid(fpgamgr_node))
+ fpga_filename = ofnode_read_string(fpgamgr_node,
+ "altr,bitstream");
+
+ return fpga_filename;
+}
+
+static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
+{
+ /*
+ * Magic ID starting at:
+ * -> 1st dword[15:0] in periph.rbf
+ * -> 2nd dword[15:0] in core.rbf
+ * Note: dword == 32 bits
+ */
+ u32 word_reading_max = 2;
+ u32 i;
+
+ for (i = 0; i < word_reading_max; i++) {
+ if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
+ rbf->security = unencrypted;
+ } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
+ rbf->security = encrypted;
+ } else if (*(buffer + i + 1) ==
+ FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
+ rbf->security = unencrypted;
+ } else if (*(buffer + i + 1) ==
+ FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
+ rbf->security = encrypted;
+ } else {
+ rbf->security = invalid;
+ continue;
+ }
+
+ /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
+ if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
+ rbf->section = periph_section;
+ break;
+ } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
+ rbf->section = core_section;
+ break;
+ } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
+ rbf->section = periph_section;
+ break;
+ } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
+ rbf->section = core_section;
+ break;
+ }
+
+ rbf->section = unknown;
+ break;
+
+ WATCHDOG_RESET();
+ }
+}
+
+#ifdef CONFIG_FS_LOADER
+static int first_loading_rbf_to_buffer(struct udevice *dev,
+ struct fpga_loadfs_info *fpga_loadfs,
+ u32 *buffer, size_t *buffer_bsize)
+{
+ u32 *buffer_p = (u32 *)*buffer;
+ u32 *loadable = buffer_p;
+ size_t buffer_size = *buffer_bsize;
+ size_t fit_size;
+ int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
+ const char *fpga_node_name = NULL;
+ const char *uname = NULL;
+
+ /* Load image header into buffer */
+ ret = request_firmware_into_buf(dev,
+ fpga_loadfs->fpga_fsinfo->filename,
+ buffer_p, sizeof(struct image_header),
+ 0);
+ if (ret < 0) {
+ debug("FPGA: Failed to read image header from flash.\n");
+ return -ENOENT;
+ }
+
+ if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
+ debug("FPGA: No FDT magic was found.\n");
+ return -EBADF;
+ }
+
+ fit_size = fdt_totalsize(buffer_p);
+
+ if (fit_size > buffer_size) {
+ debug("FPGA: FIT image is larger than available buffer.\n");
+ debug("Please use FIT external data or increasing buffer.\n");
+ return -ENOMEM;
+ }
+
+ /* Load entire FIT into buffer */
+ ret = request_firmware_into_buf(dev,
+ fpga_loadfs->fpga_fsinfo->filename,
+ buffer_p, fit_size, 0);
+ if (ret < 0)
+ return ret;
+
+ ret = fit_check_format(buffer_p);
+ if (!ret) {
+ debug("FPGA: No valid FIT image was found.\n");
+ return -EBADF;
+ }
+
+ confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
+ images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
+ if (confs_noffset < 0 || images_noffset < 0) {
+ debug("FPGA: No Configurations or images nodes were found.\n");
+ return -ENOENT;
+ }
+
+ /* Get default configuration unit name from default property */
+ confs_noffset = fit_conf_get_node(buffer_p, NULL);
+ if (confs_noffset < 0) {
+ debug("FPGA: No default configuration was found in config.\n");
+ return -ENOENT;
+ }
+
+ count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
+ FIT_FPGA_PROP);
+ if (count < 0) {
+ debug("FPGA: Invalid configuration format for FPGA node.\n");
+ return count;
+ }
+ debug("FPGA: FPGA node count: %d\n", count);
+
+ for (i = 0; i < count; i++) {
+ images_noffset = fit_conf_get_prop_node_index(buffer_p,
+ confs_noffset,
+ FIT_FPGA_PROP, i);
+ uname = fit_get_name(buffer_p, images_noffset, NULL);
+ if (uname) {
+ debug("FPGA: %s\n", uname);
+
+ if (strstr(uname, "fpga-periph") &&
+ (!is_fpgamgr_early_user_mode() ||
+ is_fpgamgr_user_mode())) {
+ fpga_node_name = uname;
+ printf("FPGA: Start to program ");
+ printf("peripheral/full bitstream ...\n");
+ break;
+ } else if (strstr(uname, "fpga-core") &&
+ (is_fpgamgr_early_user_mode() &&
+ !is_fpgamgr_user_mode())) {
+ fpga_node_name = uname;
+ printf("FPGA: Start to program core ");
+ printf("bitstream ...\n");
+ break;
+ }
+ }
+ WATCHDOG_RESET();
+ }
+
+ if (!fpga_node_name) {
+ debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
+ return 1;
+ }
+
+ images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
+ if (images_noffset < 0) {
+ debug("FPGA: No node '%s' was found in FIT.\n",
+ fpga_node_name);
+ return -ENOENT;
+ }
+
+ if (!fit_image_get_data_position(buffer_p, images_noffset,
+ &rbf_offset)) {
+ debug("FPGA: Data position was found.\n");
+ } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
+ &rbf_offset)) {
+ /*
+ * For FIT with external data, figure out where
+ * the external images start. This is the base
+ * for the data-offset properties in each image.
+ */
+ rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
+ debug("FPGA: Data offset was found.\n");
+ } else {
+ debug("FPGA: No data position/offset was found.\n");
+ return -ENOENT;
+ }
+
+ ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
+ if (ret < 0) {
+ debug("FPGA: No data size was found (err=%d).\n", ret);
+ return -ENOENT;
+ }
+
+ if (gd->ram_size < rbf_size) {
+ debug("FPGA: Using default OCRAM buffer and size.\n");
+ } else {
+ ret = fit_image_get_load(buffer_p, images_noffset,
+ (ulong *)loadable);
+ if (ret < 0) {
+ buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
+ debug("FPGA: No loadable was found.\n");
+ debug("FPGA: Using default DDR load address: 0x%x .\n",
+ DEFAULT_DDR_LOAD_ADDRESS);
+ } else {
+ buffer_p = (u32 *)*loadable;
+ debug("FPGA: Found loadable address = 0x%x.\n",
+ *loadable);
+ }
+
+ buffer_size = rbf_size;
+ }
+
+ debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
+ rbf_offset, rbf_size);
+
+ fpga_loadfs->remaining = rbf_size;
+
+ /*
+ * Determine buffer size vs bitstream size, and calculating number of
+ * chunk by chunk transfer is required due to smaller buffer size
+ * compare to bitstream
+ */
+ if (rbf_size <= buffer_size) {
+ /* Loading whole bitstream into buffer */
+ buffer_size = rbf_size;
+ fpga_loadfs->remaining = 0;
+ } else {
+ fpga_loadfs->remaining -= buffer_size;
+ }
+
+ fpga_loadfs->offset = rbf_offset;
+ /* Loading bitstream into buffer */
+ ret = request_firmware_into_buf(dev,
+ fpga_loadfs->fpga_fsinfo->filename,
+ buffer_p, buffer_size,
+ fpga_loadfs->offset);
+ if (ret < 0) {
+ debug("FPGA: Failed to read bitstream from flash.\n");
+ return -ENOENT;
+ }
+
+ /* Getting info about bitstream types */
+ get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
+
+ /* Update next reading bitstream offset */
+ fpga_loadfs->offset += buffer_size;
+
+ /* Update the final addr for bitstream */
+ *buffer = (u32)buffer_p;
+
+ /* Update the size of bitstream to be programmed into FPGA */
+ *buffer_bsize = buffer_size;
+
+ return 0;
+}
+
+static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
+ struct fpga_loadfs_info *fpga_loadfs,
+ u32 *buffer, size_t *buffer_bsize)
+{
+ int ret = 0;
+ u32 *buffer_p = (u32 *)*buffer;
+
+ /* Read the bitstream chunk by chunk. */
+ if (fpga_loadfs->remaining > *buffer_bsize) {
+ fpga_loadfs->remaining -= *buffer_bsize;
+ } else {
+ *buffer_bsize = fpga_loadfs->remaining;
+ fpga_loadfs->remaining = 0;
+ }
+
+ ret = request_firmware_into_buf(dev,
+ fpga_loadfs->fpga_fsinfo->filename,
+ buffer_p, *buffer_bsize,
+ fpga_loadfs->offset);
+ if (ret < 0) {
+ debug("FPGA: Failed to read bitstream from flash.\n");
+ return -ENOENT;
+ }
+
+ /* Update next reading bitstream offset */
+ fpga_loadfs->offset += *buffer_bsize;
+
+ return 0;
+}
+
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+ u32 offset)
+{
+ struct fpga_loadfs_info fpga_loadfs;
+ struct udevice *dev;
+ int status, ret, size;
+ u32 buffer = (uintptr_t)buf;
+ size_t buffer_sizebytes = bsize;
+ size_t buffer_sizebytes_ori = bsize;
+ size_t total_sizeof_image = 0;
+ ofnode node;
+ const fdt32_t *phandle_p;
+ u32 phandle;
+
+ node = get_fpga_mgr_ofnode(ofnode_null());
+
+ if (ofnode_valid(node)) {
+ phandle_p = ofnode_get_property(node, "firmware-loader", &size);
+ if (!phandle_p) {
+ node = ofnode_path("/chosen");
+ if (!ofnode_valid(node)) {
+ debug("FPGA: /chosen node was not found.\n");
+ return -ENOENT;
+ }
+
+ phandle_p = ofnode_get_property(node, "firmware-loader",
+ &size);
+ if (!phandle_p) {
+ debug("FPGA: firmware-loader property was not");
+ debug(" found.\n");
+ return -ENOENT;
+ }
+ }
+ } else {
+ debug("FPGA: FPGA manager node was not found.\n");
+ return -ENOENT;
+ }
+
+ phandle = fdt32_to_cpu(*phandle_p);
+ ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
+ phandle, &dev);
+ if (ret)
+ return ret;
+
+ memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
+
+ fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
+ fpga_loadfs.offset = offset;
+
+ printf("FPGA: Checking FPGA configuration setting ...\n");
+
+ /*
+ * Note: Both buffer and buffer_sizebytes values can be altered by
+ * function below.
+ */
+ ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
+ &buffer_sizebytes);
+ if (ret == 1) {
+ printf("FPGA: Skipping configuration ...\n");
+ return 0;
+ } else if (ret) {
+ return ret;
+ }
+
+ if (fpga_loadfs.rbfinfo.section == core_section &&
+ !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
+ debug("FPGA : Must be in Early Release mode to program ");
+ debug("core bitstream.\n");
+ return -EPERM;
+ }
+
+ /* Disable all signals from HPS peripheral controller to FPGA */
+ writel(0, &system_manager_base->fpgaintf_en_global);
+
+ /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset();
+
+ if (fpga_loadfs.rbfinfo.section == periph_section) {
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
+ if (status) {
+ debug("FPGA: Init with peripheral bitstream failed.\n");
+ return -EPERM;
+ }
+ }
+
+ /* Transfer bitstream to FPGA Manager */
+ fpgamgr_program_write((void *)buffer, buffer_sizebytes);
+
+ total_sizeof_image += buffer_sizebytes;
+
+ while (fpga_loadfs.remaining) {
+ ret = subsequent_loading_rbf_to_buffer(dev,
+ &fpga_loadfs,
+ &buffer,
+ &buffer_sizebytes_ori);
+
+ if (ret)
+ return ret;
+
+ /* Transfer data to FPGA Manager */
+ fpgamgr_program_write((void *)buffer,
+ buffer_sizebytes_ori);
+
+ total_sizeof_image += buffer_sizebytes_ori;
+
+ WATCHDOG_RESET();
+ }
+
+ if (fpga_loadfs.rbfinfo.section == periph_section) {
+ if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
+ config_pins(gd->fdt_blob, "shared");
+ puts("FPGA: Early Release Succeeded.\n");
+ } else {
+ debug("FPGA: Failed to see Early Release.\n");
+ return -EIO;
+ }
+
+ /* For monolithic bitstream */
+ if (is_fpgamgr_user_mode()) {
+ /* Ensure the FPGA entering config done */
+ status = fpgamgr_program_finish();
+ if (status)
+ return status;
+
+ config_pins(gd->fdt_blob, "fpga");
+ puts("FPGA: Enter user mode.\n");
+ }
+ } else if (fpga_loadfs.rbfinfo.section == core_section) {
+ /* Ensure the FPGA entering config done */
+ status = fpgamgr_program_finish();
+ if (status)
+ return status;
+
+ config_pins(gd->fdt_blob, "fpga");
+ puts("FPGA: Enter user mode.\n");
+ } else {
+ debug("FPGA: Config Error: Unsupported bitstream type.\n");
+ return -ENOEXEC;
+ }
+
+ return (int)total_sizeof_image;
+}
+
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
+{
+ fpga_fs_info fpga_fsinfo;
+
+ fpga_fsinfo.filename = get_fpga_filename();
+
+ if (fpga_fsinfo.filename)
+ socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
+}
+#endif
+
+/* This function is used to load the core bitstream from the OCRAM. */
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
- int status;
+ unsigned long status;
+ struct rbf_info rbfinfo;
- /* disable all signals from hps peripheral controller to fpga */
+ memset(&rbfinfo, 0, sizeof(rbfinfo));
+
+ /* Disable all signals from hps peripheral controller to fpga */
writel(0, &system_manager_base->fpgaintf_en_global);
- /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset();
- /* Initialize the FPGA Manager */
- status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
- if (status)
- return status;
+ /* Getting info about bitstream types */
+ get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
+
+ if (rbfinfo.section == periph_section) {
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
+ if (status)
+ return status;
+ }
- /* Write the RBF data to FPGA Manager */
+ if (rbfinfo.section == core_section &&
+ !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
+ debug("FPGA : Must be in early release mode to program ");
+ debug("core bitstream.\n");
+ return -EPERM;
+ }
+
+ /* Write the bitstream to FPGA Manager */
fpgamgr_program_write(rbf_data, rbf_size);
- return fpgamgr_program_finish();
+ status = fpgamgr_program_finish();
+ if (status) {
+ config_pins(gd->fdt_blob, "fpga");
+ puts("FPGA: Enter user mode.\n");
+ }
+
+ return status;
}
help
This driver supports the GPIO banks on Renesas RCar SoCs.
+config RZA1_GPIO
+ bool "Renesas RZ/A1 GPIO driver"
+ depends on DM_GPIO && RZA1
+ help
+ This driver supports the GPIO banks on Renesas RZ/A1 R7S72100 SoCs.
+
config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
depends on DM_GPIO
config MT7621_GPIO
bool "MediaTek MT7621 GPIO driver"
- depends on DM_GPIO && ARCH_MT7620
+ depends on DM_GPIO && SOC_MT7628
default y
help
Say yes here to support MediaTek MT7621 compatible GPIOs.
obj-$(CONFIG_PCA9698) += pca9698.o
obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o
obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o
+obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o
obj-$(CONFIG_S5P) += s5p_gpio.o
obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
#include <errno.h>
#include <reset.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define GPIO_SWPORT_DR(p) (0x00 + (p) * 0xc)
#define GPIO_SWPORT_DDR(p) (0x04 + (p) * 0xc)
#define GPIO_INTEN 0x30
static int gpio_dwapb_bind(struct udevice *dev)
{
struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
- const void *blob = gd->fdt_blob;
struct udevice *subdev;
fdt_addr_t base;
- int ret, node, bank = 0;
+ int ret, bank = 0;
+ ofnode node;
/* If this is a child device, there is nothing to do here */
if (plat)
return -ENXIO;
}
- for (node = fdt_first_subnode(blob, dev_of_offset(dev));
- node > 0;
- node = fdt_next_subnode(blob, node)) {
- if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+ for (node = dev_read_first_subnode(dev); ofnode_valid(node);
+ node = dev_read_next_subnode(node)) {
+ if (!ofnode_read_bool(node, "gpio-controller"))
continue;
plat = devm_kcalloc(dev, 1, sizeof(*plat), GFP_KERNEL);
plat->base = base;
plat->bank = bank;
- plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0);
- plat->name = fdt_stringlist_get(blob, node, "bank-name", 0,
- NULL);
- if (!plat->name) {
+ plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
+
+ if (ofnode_read_string_index(node, "bank-name", 0,
+ &plat->name)) {
/*
* Fall back to node name. This means accessing pins
* via bank name won't work.
*/
- plat->name = fdt_get_name(blob, node, NULL);
+ plat->name = ofnode_get_name(node);
}
- ret = device_bind(dev, dev->driver, plat->name,
- plat, -1, &subdev);
+ ret = device_bind_ofnode(dev, dev->driver, plat->name,
+ plat, node, &subdev);
if (ret)
return ret;
- dev_set_of_offset(subdev, node);
bank++;
}
#include <common.h>
#include <clk.h>
#include <dm.h>
+#include <dm/pinctrl.h>
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
static int rcar_gpio_request(struct udevice *dev, unsigned offset,
const char *label)
{
- struct rcar_gpio_priv *priv = dev_get_priv(dev);
- struct udevice *pctldev;
- int ret;
-
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pctldev);
- if (ret)
- return ret;
+ return pinctrl_gpio_request(dev, offset);
+}
- return sh_pfc_config_mux_for_gpio(pctldev, priv->pfc_offset + offset);
+static int rcar_gpio_free(struct udevice *dev, unsigned offset)
+{
+ return pinctrl_gpio_free(dev, offset);
}
static const struct dm_gpio_ops rcar_gpio_ops = {
.request = rcar_gpio_request,
+ .free = rcar_gpio_free,
.direction_input = rcar_gpio_direction_input,
.direction_output = rcar_gpio_direction_output,
.get_value = rcar_gpio_get_value,
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#define P(bank) (0x0000 + (bank) * 4)
+#define PSR(bank) (0x0100 + (bank) * 4)
+#define PPR(bank) (0x0200 + (bank) * 4)
+#define PM(bank) (0x0300 + (bank) * 4)
+#define PMC(bank) (0x0400 + (bank) * 4)
+#define PFC(bank) (0x0500 + (bank) * 4)
+#define PFCE(bank) (0x0600 + (bank) * 4)
+#define PNOT(bank) (0x0700 + (bank) * 4)
+#define PMSR(bank) (0x0800 + (bank) * 4)
+#define PMCSR(bank) (0x0900 + (bank) * 4)
+#define PFCAE(bank) (0x0A00 + (bank) * 4)
+#define PIBC(bank) (0x4000 + (bank) * 4)
+#define PBDC(bank) (0x4100 + (bank) * 4)
+#define PIPC(bank) (0x4200 + (bank) * 4)
+
+#define RZA1_MAX_GPIO_PER_BANK 16
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct r7s72100_gpio_priv {
+ void __iomem *regs;
+ int bank;
+};
+
+static int r7s72100_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
+
+ return !!(readw(priv->regs + PPR(priv->bank)) & BIT(offset));
+}
+
+static int r7s72100_gpio_set_value(struct udevice *dev, unsigned line,
+ int value)
+{
+ struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
+
+ writel(BIT(line + 16) | (value ? BIT(line) : 0),
+ priv->regs + PSR(priv->bank));
+
+ return 0;
+}
+
+static void r7s72100_gpio_set_direction(struct udevice *dev, unsigned line,
+ bool output)
+{
+ struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
+
+ writel(BIT(line + 16), priv->regs + PMCSR(priv->bank));
+ writel(BIT(line + 16) | (output ? 0 : BIT(line)),
+ priv->regs + PMSR(priv->bank));
+
+ clrsetbits_le16(priv->regs + PIBC(priv->bank), BIT(line),
+ output ? 0 : BIT(line));
+}
+
+static int r7s72100_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ r7s72100_gpio_set_direction(dev, offset, false);
+ return 0;
+}
+
+static int r7s72100_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ /* write GPIO value to output before selecting output mode of pin */
+ r7s72100_gpio_set_value(dev, offset, value);
+ r7s72100_gpio_set_direction(dev, offset, true);
+
+ return 0;
+}
+
+static int r7s72100_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
+
+ if (readw(priv->regs + PM(priv->bank)) & BIT(offset))
+ return GPIOF_INPUT;
+ else
+ return GPIOF_OUTPUT;
+}
+
+static const struct dm_gpio_ops r7s72100_gpio_ops = {
+ .direction_input = r7s72100_gpio_direction_input,
+ .direction_output = r7s72100_gpio_direction_output,
+ .get_value = r7s72100_gpio_get_value,
+ .set_value = r7s72100_gpio_set_value,
+ .get_function = r7s72100_gpio_get_function,
+};
+
+static int r7s72100_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
+ struct fdtdec_phandle_args args;
+ int node = dev_of_offset(dev);
+ int ret;
+
+ fdt_addr_t addr_base;
+
+ uc_priv->bank_name = dev->name;
+ dev = dev_get_parent(dev);
+ addr_base = devfdt_get_addr(dev);
+ if (addr_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = (void __iomem *)addr_base;
+
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
+ NULL, 3, 0, &args);
+ priv->bank = ret == 0 ? (args.args[1] / RZA1_MAX_GPIO_PER_BANK) : -1;
+ uc_priv->gpio_count = ret == 0 ? args.args[2] : RZA1_MAX_GPIO_PER_BANK;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(r7s72100_gpio) = {
+ .name = "r7s72100-gpio",
+ .id = UCLASS_GPIO,
+ .ops = &r7s72100_gpio_ops,
+ .priv_auto_alloc_size = sizeof(struct r7s72100_gpio_priv),
+ .probe = r7s72100_gpio_probe,
+};
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/gpio.h>
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
channels and operating on standard mode up to 100 kbits/s and fast
mode up to 400 kbits/s.
-if SYS_I2C_MXC
+# These settings are not used with DM_I2C, however SPL doesn't use
+# DM_I2C even if DM_I2C is enabled, and so might use these settings even
+# when main u-boot does not!
+if SYS_I2C_MXC && (!DM_I2C || SPL)
config SYS_I2C_MXC_I2C1
bool "NXP MXC I2C1"
help
#include <i2c.h>
#ifdef CONFIG_DM_I2C
#include <dm.h>
-#include <fpgamap.h>
-#include "../misc/gdsys_soc.h"
+#include <regmap.h>
#else
#include <gdsys_fpga.h>
#endif
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv {
uint speed;
- phys_addr_t addr;
+ struct regmap *map;
};
-enum {
- REG_INTERRUPT_STATUS = 0x00,
- REG_INTERRUPT_ENABLE_CONTROL = 0x02,
- REG_WRITE_MAILBOX_EXT = 0x04,
- REG_WRITE_MAILBOX = 0x06,
- REG_READ_MAILBOX_EXT = 0x08,
- REG_READ_MAILBOX = 0x0A,
+struct ihs_i2c_regs {
+ u16 interrupt_status;
+ u16 interrupt_enable_control;
+ u16 write_mailbox_ext;
+ u16 write_mailbox;
+ u16 read_mailbox_ext;
+ u16 read_mailbox;
};
+#define ihs_i2c_set(map, member, val) \
+ regmap_set(map, struct ihs_i2c_regs, member, val)
+
+#define ihs_i2c_get(map, member, valp) \
+ regmap_get(map, struct ihs_i2c_regs, member, valp)
+
#else /* !CONFIG_DM_I2C */
DECLARE_GLOBAL_DATA_PTR;
uint ctr = 0;
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv *priv = dev_get_priv(dev);
- struct udevice *fpga;
-
- gdsys_soc_get_fpga(dev, &fpga);
#endif
#ifdef CONFIG_DM_I2C
- fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_GET_REG(interrupt_status, &val);
#endif
while (!(val & (I2CINT_ERROR_EV
| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
udelay(10);
- if (ctr++ > 5000)
- return 1;
+ if (ctr++ > 5000) {
+ debug("%s: timed out\n", __func__);
+ return -ETIMEDOUT;
+ }
#ifdef CONFIG_DM_I2C
- fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_GET_REG(interrupt_status, &val);
#endif
}
- return (val & I2CINT_ERROR_EV) ? 1 : 0;
+ return (val & I2CINT_ERROR_EV) ? -EIO : 0;
}
#ifdef CONFIG_DM_I2C
{
u16 val;
u16 data;
+ int res;
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv *priv = dev_get_priv(dev);
- struct udevice *fpga;
-
- gdsys_soc_get_fpga(dev, &fpga);
#endif
/* Clear interrupt status */
data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
#ifdef CONFIG_DM_I2C
- fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data,
- FPGAMAP_SIZE_16);
- fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_set(priv->map, interrupt_status, data);
+ ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_SET_REG(interrupt_status, data);
I2C_GET_REG(interrupt_status, &val);
if (len > 1)
val |= buffer[1] << 8;
#ifdef CONFIG_DM_I2C
- fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_set(priv->map, write_mailbox_ext, val);
#else
I2C_SET_REG(write_mailbox_ext, val);
#endif
| (is_last ? 0 : I2CMB_HOLD_BUS);
#ifdef CONFIG_DM_I2C
- fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data,
- FPGAMAP_SIZE_16);
+ ihs_i2c_set(priv->map, write_mailbox, data);
#else
I2C_SET_REG(write_mailbox, data);
#endif
#ifdef CONFIG_DM_I2C
- if (wait_for_int(dev, read))
+ res = wait_for_int(dev, read);
#else
- if (wait_for_int(read))
+ res = wait_for_int(read);
#endif
- return 1;
+ if (res) {
+ if (res == -ETIMEDOUT)
+ debug("%s: time out while waiting for event\n", __func__);
+
+ return res;
+ }
/* If we want to read, get the bytes from the mailbox */
if (read) {
#ifdef CONFIG_DM_I2C
- fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_get(priv->map, read_mailbox_ext, &val);
#else
I2C_GET_REG(read_mailbox_ext, &val);
#endif
int read)
#endif
{
+ int res;
+
while (len) {
int transfer = min(len, 2);
bool is_last = len <= transfer;
#ifdef CONFIG_DM_I2C
- if (ihs_i2c_transfer(dev, chip, data, transfer, read,
- hold_bus ? false : is_last))
- return 1;
+ res = ihs_i2c_transfer(dev, chip, data, transfer, read,
+ hold_bus ? false : is_last);
#else
- if (ihs_i2c_transfer(chip, data, transfer, read,
- hold_bus ? false : is_last))
- return 1;
+ res = ihs_i2c_transfer(chip, data, transfer, read,
+ hold_bus ? false : is_last);
#endif
+ if (res)
+ return res;
data += transfer;
len -= transfer;
int alen, uchar *buffer, int len, int read)
#endif
{
+ int res;
+
/* Don't hold the bus if length of data to send/receive is zero */
+ if (len <= 0)
+ return -EINVAL;
+
#ifdef CONFIG_DM_I2C
- if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len))
- return 1;
+ res = ihs_i2c_address(dev, chip, addr, alen, len);
#else
- if (len <= 0 || ihs_i2c_address(chip, addr, alen, len))
- return 1;
+ res = ihs_i2c_address(chip, addr, alen, len);
#endif
+ if (res)
+ return res;
#ifdef CONFIG_DM_I2C
return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
int ihs_i2c_probe(struct udevice *bus)
{
struct ihs_i2c_priv *priv = dev_get_priv(bus);
- int addr;
-
- addr = dev_read_u32_default(bus, "reg", -1);
- priv->addr = addr;
+ regmap_init_mem(dev_ofnode(bus), &priv->map);
return 0;
}
struct ihs_i2c_priv *priv = dev_get_priv(bus);
if (speed != priv->speed && priv->speed != 0)
- return 1;
+ return -EINVAL;
priv->speed = speed;
* actucal data) or one message (just data)
*/
if (nmsgs > 2 || nmsgs == 0) {
- debug("%s: Only one or two messages are supported.", __func__);
- return -1;
+ debug("%s: Only one or two messages are supported\n", __func__);
+ return -ENOTSUPP;
}
omsg = nmsgs == 1 ? &dummy : msg;
u32 chip_flags)
{
uchar buffer[2];
+ int res;
- if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true))
- return 1;
+ res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
+ if (res)
+ return res;
return 0;
}
static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
uchar buffer[2];
+ int res;
- if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true))
- return 1;
+ res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
+ if (res)
+ return res;
return 0;
}
unsigned int speed)
{
if (speed != adap->speed)
- return 1;
+ return -EINVAL;
return speed;
}
do {
control = readl(&twsi->control);
if (control & MVTWSI_CONTROL_IFLG) {
+ /*
+ * On Armada 38x it seems that the controller works as
+ * if it first set the MVTWSI_CONTROL_IFLAG in the
+ * control register and only after that it changed the
+ * status register.
+ * This sometimes caused weird bugs which only appeared
+ * on selected I2C speeds and even then only sometimes.
+ * We therefore add here a simple ndealy(100), which
+ * seems to fix this weird bug.
+ */
+ ndelay(100);
status = readl(&twsi->status);
if (status == expected_status)
return 0;
return ret;
}
+/* Will generate a STOP after the last byte if "last" is true, i.e. this is the
+ * final message of a transaction. If not, it switches the bus back to TX mode
+ * and does not send a STOP, leaving the bus in a state where a repeated start
+ * and address can be sent for another message.
+ */
static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
- int len)
+ int len, bool last)
{
int ret;
unsigned int temp;
return ret;
}
- /*
- * It must generate STOP before read I2DR to prevent
- * controller from generating another clock cycle
- */
if (i == (len - 1)) {
- i2c_imx_stop(i2c_bus);
+ /* Final byte has already been received by master! When
+ * we read it from I2DR, the master will start another
+ * cycle. We must program it first to send a STOP or
+ * switch to TX to avoid this.
+ */
+ if (last) {
+ i2c_imx_stop(i2c_bus);
+ } else {
+ /* Final read, no stop, switch back to tx */
+ temp = readb(base + (I2CR << reg_shift));
+ temp |= I2CR_MTX | I2CR_TX_NO_AK;
+ writeb(temp, base + (I2CR << reg_shift));
+ }
} else if (i == (len - 2)) {
+ /* Master has already recevied penultimate byte. When
+ * we read it from I2DR, master will start RX of final
+ * byte. We must set TX_NO_AK now so it does not ACK
+ * that final byte.
+ */
temp = readb(base + (I2CR << reg_shift));
temp |= I2CR_TX_NO_AK;
writeb(temp, base + (I2CR << reg_shift));
}
+
writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
buf[i] = readb(base + (I2DR << reg_shift));
}
debug(" 0x%02x", buf[ret]);
debug("\n");
- i2c_imx_stop(i2c_bus);
+ /* It is not clear to me that this is necessary */
+ if (last)
+ i2c_imx_stop(i2c_bus);
return 0;
}
#ifndef CONFIG_DM_I2C
/*
* Read data from I2C device
+ *
+ * The transactions use the syntax defined in the Linux kernel I2C docs.
+ *
+ * If alen is > 0, then this function will send a transaction of the form:
+ * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
+ * This is a normal I2C register read: writing the register address, then doing
+ * a repeated start and reading the data.
+ *
+ * If alen == 0, then we get this transaction:
+ * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
+ * This is somewhat unusual, though valid, transaction. It addresses the chip
+ * in write mode, but doesn't actually write any register address or data, then
+ * does a repeated start and reads data.
+ *
+ * If alen < 0, then we get this transaction:
+ * S Chip Rd [A] [data] A ... NA P
+ * The chip is addressed in read mode and then data is read. No register
+ * address is written first. This is perfectly valid on most devices and
+ * required on some (usually those that don't act like an array of registers).
*/
static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
int alen, u8 *buf, int len)
return ret;
}
- ret = i2c_read_data(i2c_bus, chip, buf, len);
+ ret = i2c_read_data(i2c_bus, chip, buf, len, true);
i2c_imx_stop(i2c_bus);
return ret;
/*
* Write data to I2C device
+ *
+ * If alen > 0, we get this transaction:
+ * S Chip Wr [A] addr [A] data [A] ... [A] P
+ * An ordinary write register command.
+ *
+ * If alen == 0, then we get this:
+ * S Chip Wr [A] data [A] ... [A] P
+ * This is a simple I2C write.
+ *
+ * If alen < 0, then we get this:
+ * S data [A] ... [A] P
+ * This is most likely NOT something that should be used. It doesn't send the
+ * chip address first, so in effect, the first byte of data will be used as the
+ * address.
*/
static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
int alen, const u8 *buf, int len)
return 0;
}
+/* Sends: S Addr Wr [A|NA] P */
static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
u32 chip_flags)
{
ulong base = i2c_bus->base;
int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+ int read_mode;
- /*
- * Here the 3rd parameter addr and the 4th one alen are set to 0,
- * because here we only want to send out chip address. The register
- * address is wrapped in msg.
+ /* Here address len is set to -1 to not send any address at first.
+ * Otherwise i2c_init_transfer will send the chip address with write
+ * mode set. This is wrong if the 1st message is read.
*/
- ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
+ ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
if (ret < 0) {
debug("i2c_init_transfer error: %d\n", ret);
return ret;
}
+ read_mode = -1; /* So it's always different on the first message */
for (; nmsgs > 0; nmsgs--, msg++) {
- bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
- debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
- if (msg->flags & I2C_M_RD)
- ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
- msg->len);
- else {
- ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
- msg->len);
- if (ret)
- break;
- if (next_is_read) {
- /* Reuse ret */
+ const int msg_is_read = !!(msg->flags & I2C_M_RD);
+
+ debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
+ msg->len, msg_is_read ? 'R' : 'W');
+
+ if (msg_is_read != read_mode) {
+ /* Send repeated start if not 1st message */
+ if (read_mode != -1) {
+ debug("i2c_xfer: [RSTART]\n");
ret = readb(base + (I2CR << reg_shift));
ret |= I2CR_RSTA;
writeb(ret, base + (I2CR << reg_shift));
-
- ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
- if (ret < 0) {
- i2c_imx_stop(i2c_bus);
- break;
- }
}
+ debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
+ msg_is_read ? 'R' : 'W');
+ ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
+ if (ret < 0) {
+ debug("i2c_xfer: [STOP]\n");
+ i2c_imx_stop(i2c_bus);
+ break;
+ }
+ read_mode = msg_is_read;
}
+
+ if (msg->flags & I2C_M_RD)
+ ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
+ msg->len, nmsgs == 1 ||
+ (msg->flags & I2C_M_STOP));
+ else
+ ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
+ msg->len);
+
+ if (ret < 0)
+ break;
}
if (ret)
#include <errno.h>
#include <i2c.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/i2c.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/i2c.h>
+#include <asm/arch-rockchip/periph.h>
#include <dm/pinctrl.h>
#include <linux/sizes.h>
af_delay_max = setup->analog_filter ?
STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
- sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
+ sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
af_delay_min - (setup->dnf + 3) * i2cclk;
sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
p_prev = p;
list_add_tail(&v->node, solutions);
+ break;
}
}
+
+ if (p_prev == p)
+ break;
}
}
set of generic read, write and ioctl methods may be used to
access the device.
+config SPL_MISC
+ bool "Enable Driver Model for Misc drivers in SPL"
+ depends on SPL_DM
+ help
+ Enable driver model for miscellaneous devices. This class is
+ used only for those do not fit other more general classes. A
+ set of generic read, write and ioctl methods may be used to
+ access the device.
+
+config TPL_MISC
+ bool "Enable Driver Model for Misc drivers in TPL"
+ depends on TPL_DM
+ help
+ Enable driver model for miscellaneous devices. This class is
+ used only for those do not fit other more general classes. A
+ set of generic read, write and ioctl methods may be used to
+ access the device.
+
config ALTERA_SYSID
bool "Altera Sysid support"
depends on MISC
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
+config SPL_CROS_EC
+ bool "Enable Chrome OS EC in SPL"
+ help
+ Enable access to the Chrome OS EC in SPL. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
+config TPL_CROS_EC
+ bool "Enable Chrome OS EC in TPL"
+ help
+ Enable access to the Chrome OS EC in TPL. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
config CROS_EC_I2C
bool "Enable Chrome OS EC I2C driver"
depends on CROS_EC
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
+config SPL_CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver in SPL"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
+config TPL_CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver in TPL"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
config CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver"
depends on CROS_EC && SANDBOX
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
+config SPL_CROS_EC_SANDBOX
+ bool "Enable Chrome OS EC sandbox driver in SPL"
+ depends on SPL_CROS_EC && SANDBOX
+ help
+ Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
+ keyboard (use the -l flag to enable the LCD), verified boot context,
+ EC flash read/write/erase support and a few other things. It is
+ enough to perform a Chrome OS verified boot on sandbox.
+
+config TPL_CROS_EC_SANDBOX
+ bool "Enable Chrome OS EC sandbox driver in TPL"
+ depends on TPL_CROS_EC && SANDBOX
+ help
+ Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
+ keyboard (use the -l flag to enable the LCD), verified boot context,
+ EC flash read/write/erase support and a few other things. It is
+ enough to perform a Chrome OS verified boot on sandbox.
+
config CROS_EC_SPI
bool "Enable Chrome OS EC SPI driver"
depends on CROS_EC
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_MISC) += misc-uclass.o
+
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o
+
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_CROS_EC) += cros_ec.o
-obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
-obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
endif
UCLASS_DRIVER(cros_ec) = {
.id = UCLASS_CROS_EC,
- .name = "cros_ec",
+ .name = "cros-ec",
.per_device_auto_alloc_size = sizeof(struct cros_ec_dev),
.post_bind = dm_scan_fdt_dev,
.flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
struct gdsys_rxaui_ctrl_priv {
struct regmap *map;
+ bool state;
};
int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val)
struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev);
u16 state;
+ priv->state = !priv->state;
+
rxaui_ctrl_get(priv->map, ctrl_1, &state);
if (val)
rxaui_ctrl_set(priv->map, ctrl_1, state);
- return 0;
+ return !priv->state;
}
static const struct misc_ops gdsys_rxaui_ctrl_ops = {
{
struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev);
- regmap_init_mem(dev, &priv->map);
+ regmap_init_mem(dev_ofnode(dev), &priv->map);
+
+ priv->state = false;
return 0;
}
# SPDX-License-Identifier: GPL-2.0+
obj-y += scu_api.o scu.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <console.h>
+#include <errno.h>
+#include <fuse.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FSL_ECC_WORD_START_1 0x10
+#define FSL_ECC_WORD_END_1 0x10F
+
+#ifdef CONFIG_IMX8QXP
+#define FSL_ECC_WORD_START_2 0x220
+#define FSL_ECC_WORD_END_2 0x31F
+
+#define FSL_QXP_FUSE_GAP_START 0x110
+#define FSL_QXP_FUSE_GAP_END 0x21F
+#endif
+
+#define FSL_SIP_OTP_READ 0xc200000A
+#define FSL_SIP_OTP_WRITE 0xc200000B
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ return fuse_sense(bank, word, val);
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ unsigned long ret = 0, value = 0;
+
+ if (bank != 0) {
+ printf("Invalid bank argument, ONLY bank 0 is supported\n");
+ return -EINVAL;
+ }
+
+ ret = call_imx_sip_ret2(FSL_SIP_OTP_READ, (unsigned long)word, &value,
+ 0, 0);
+ *val = (u32)value;
+
+ return ret;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+ if (bank != 0) {
+ printf("Invalid bank argument, ONLY bank 0 is supported\n");
+ return -EINVAL;
+ }
+
+ if (IS_ENABLED(CONFIG_IMX8QXP)) {
+ if (word >= FSL_QXP_FUSE_GAP_START &&
+ word <= FSL_QXP_FUSE_GAP_END) {
+ printf("Invalid word argument for this SoC\n");
+ return -EINVAL;
+ }
+ }
+
+ if ((word >= FSL_ECC_WORD_START_1 && word <= FSL_ECC_WORD_END_1) ||
+ (word >= FSL_ECC_WORD_START_2 && word <= FSL_ECC_WORD_END_2)) {
+ puts("Warning: Words in this index range have ECC protection\n"
+ "and can only be programmed once per word. Individual bit\n"
+ "operations will be rejected after the first one.\n"
+ "\n\n Really program this word? <y/N>\n");
+
+ if (!confirm_yesno()) {
+ puts("Word programming aborted\n");
+ return -EPERM;
+ }
+ }
+
+ return call_imx_sip(FSL_SIP_OTP_WRITE, (unsigned long)word,
+ (unsigned long)val, 0);
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+ printf("Override fuse to i.MX8 in u-boot is forbidden\n");
+ return -EPERM;
+}
int ret;
struct udevice *child;
int node;
+ char *clk_compatible, *iomuxc_compatible;
+
+ if (IS_ENABLED(CONFIG_IMX8QXP)) {
+ clk_compatible = "fsl,imx8qxp-clk";
+ iomuxc_compatible = "fsl,imx8qxp-iomuxc";
+ } else if (IS_ENABLED(CONFIG_IMX8QM)) {
+ clk_compatible = "fsl,imx8qm-clk";
+ iomuxc_compatible = "fsl,imx8qm-iomuxc";
+ } else {
+ return -EINVAL;
+ }
debug("%s(dev=%p)\n", __func__, dev);
- node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "fsl,imx8qxp-clk");
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, clk_compatible);
if (node < 0)
panic("No clk node found\n");
plat->clk = child;
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "fsl,imx8qxp-iomuxc");
+ iomuxc_compatible);
if (node < 0)
panic("No iomuxc node found\n");
struct ocotp_regs *regs;
int ret;
+ if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) {
+ printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
+ return -EPERM;
+ }
+
ret = prepare_read(®s, bank, word, val, __func__);
if (ret)
return ret;
/* Only bank 0 and 1 are redundancy mode, others are ECC mode */
if (bank != 0 && bank != 1) {
- ret = fuse_sense(bank, word, &val);
- if (ret)
- return ret;
-
- if (val != 0) {
- printf("mxc_ocotp: The word has been programmed, no more write\n");
- return -EPERM;
+ if ((soc_rev() < CHIP_REV_2_0) ||
+ ((soc_rev() >= CHIP_REV_2_0) &&
+ bank != 9 && bank != 10 && bank != 28)) {
+ ret = fuse_sense(bank, word, &val);
+ if (ret)
+ return ret;
+
+ if (val != 0) {
+ printf("mxc_ocotp: The word has been programmed, no more write\n");
+ return -EPERM;
+ }
}
}
#endif
Enable support for reading, writing and programming the
key for the Replay Protection Memory Block partition in eMMC.
+config SUPPORT_EMMC_BOOT
+ bool "Support some additional features of the eMMC boot partitions"
+ help
+ Enable support for eMMC boot partitions. This also enables
+ extensions within the mmc command.
+
config MMC_IO_VOLTAGE
bool "Support IO voltage configuration"
help
This enables support for the SDMA (Single Operation DMA) defined
in the SD Host Controller Standard Specification Version 1.00 .
+config MMC_SDHCI_ADMA
+ bool "Support SDHCI ADMA2"
+ depends on MMC_SDHCI
+ help
+ This enables support for the ADMA (Advanced DMA) defined
+ in the SD Host Controller Standard Specification Version 3.00
+
+config SPL_MMC_SDHCI_ADMA
+ bool "Support SDHCI ADMA2 in SPL"
+ depends on MMC_SDHCI
+ help
+ This enables support for the ADMA (Advanced DMA) defined
+ in the SD Host Controller Standard Specification Version 3.00 in SPL.
+
config MMC_SDHCI_ATMEL
bool "Atmel SDHCI controller support"
depends on ARCH_AT91
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 Cisco Systems, Inc.
+ * (C) Copyright 2019 Synamedia
*
* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
*/
#include <common.h>
+#include <dm.h>
#include <mach/sdhci.h>
#include <malloc.h>
#include <sdhci.h>
*/
#define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000
-static char *BCMSTB_SDHCI_NAME = "bcmstb-sdhci";
-
/*
* This driver has only been tested with eMMC devices; SD devices may
* not work.
*/
-int bcmstb_sdhci_init(phys_addr_t regbase)
+struct sdhci_bcmstb_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+static int sdhci_bcmstb_bind(struct udevice *dev)
{
- struct sdhci_host *host = NULL;
+ struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
- host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
- if (!host) {
- printf("%s: Failed to allocate memory\n", __func__);
- return 1;
- }
- memset(host, 0, sizeof(*host));
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static int sdhci_bcmstb_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ fdt_addr_t base;
+ int ret;
- host->name = BCMSTB_SDHCI_NAME;
- host->ioaddr = (void *)regbase;
- host->quirks = 0;
+ base = devfdt_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
- host->cfg.part_type = PART_TYPE_DOS;
+ host->name = dev->name;
+ host->ioaddr = (void *)base;
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
- return add_sdhci(host,
- BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
- BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
+ ret = sdhci_setup_cfg(&plat->cfg, host,
+ BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
+ BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
+ if (ret)
+ return ret;
+
+ upriv->mmc = &plat->mmc;
+ host->mmc = &plat->mmc;
+ host->mmc->priv = host;
+
+ return sdhci_probe(dev);
}
+
+static const struct udevice_id sdhci_bcmstb_match[] = {
+ { .compatible = "brcm,bcm7425-sdhci" },
+ { .compatible = "brcm,sdhci-brcmstb" },
+ { }
+};
+
+U_BOOT_DRIVER(sdhci_bcmstb) = {
+ .name = "sdhci-bcmstb",
+ .id = UCLASS_MMC,
+ .of_match = sdhci_bcmstb_match,
+ .ops = &sdhci_ops,
+ .bind = sdhci_bcmstb_bind,
+ .probe = sdhci_bcmstb_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+ .platdata_auto_alloc_size = sizeof(struct sdhci_bcmstb_plat),
+};
dwmci_set_idma_desc(cur_idmac, flags, cnt,
(ulong)bounce_buffer + (i * PAGE_SIZE));
+ cur_idmac++;
if (blk_cnt <= 8)
break;
blk_cnt -= 8;
- cur_idmac++;
i++;
} while(1);
data_end = (ulong)cur_idmac;
- flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
+ flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
ctrl = dwmci_readl(host, DWMCI_CTRL);
ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
return 0;
}
+static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
+{
+ unsigned int timeout;
+
+ timeout = size * 8 * 1000; /* counting in bits and msec */
+ timeout *= 2; /* wait twice as long */
+ timeout /= mmc->clock;
+ timeout /= mmc->bus_width;
+ timeout /= mmc->ddr_mode ? 2 : 1;
+ timeout = (timeout < 1000) ? 1000 : timeout;
+
+ return timeout;
+}
+
static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
{
+ struct mmc *mmc = host->mmc;
int ret = 0;
- u32 timeout = 240000;
- u32 mask, size, i, len = 0;
+ u32 timeout, mask, size, i, len = 0;
u32 *buf = NULL;
ulong start = get_timer(0);
u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
RX_WMARK_SHIFT) + 1) * 2;
- size = data->blocksize * data->blocks / 4;
+ size = data->blocksize * data->blocks;
if (data->flags == MMC_DATA_READ)
buf = (unsigned int *)data->dest;
else
buf = (unsigned int *)data->src;
+ timeout = dwmci_get_timeout(mmc, size);
+
+ size /= 4;
+
for (;;) {
mask = dwmci_readl(host, DWMCI_RINTSTS);
/* Error during data transfer. */
dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
} else {
if (data->flags == MMC_DATA_READ) {
- bounce_buffer_start(&bbstate, (void*)data->dest,
+ ret = bounce_buffer_start(&bbstate,
+ (void*)data->dest,
data->blocksize *
data->blocks, GEN_BB_WRITE);
} else {
- bounce_buffer_start(&bbstate, (void*)data->src,
+ ret = bounce_buffer_start(&bbstate,
+ (void*)data->src,
data->blocksize *
data->blocks, GEN_BB_READ);
}
+
+ if (ret)
+ return ret;
+
dwmci_prepare_data(host, data, cur_idmac,
bbstate.bounce_buffer);
}
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return -ETIMEDOUT;
}
+ } else {
+#ifdef CONFIG_DM_GPIO
+ if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
+ printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+ return -ETIMEDOUT;
+ }
+#endif
}
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
#endif
#if CONFIG_IS_ENABLED(DM_MMC)
+#ifndef CONFIG_PPC
#include <asm/arch/clock.h>
+#endif
__weak void init_clk_usdhc(u32 index)
{
}
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
-
+#ifdef CONFIG_PPC
+ priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
+#else
priv->esdhc_regs = (struct fsl_esdhc *)addr;
+#endif
priv->dev = dev;
priv->mode = -1;
if (data) {
#endif
}
- priv->wp_enable = 1;
-
+ if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
+ priv->wp_enable = 1;
+ } else {
+ priv->wp_enable = 0;
#ifdef CONFIG_DM_GPIO
- ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
GPIOD_IS_IN);
- if (ret)
- priv->wp_enable = 0;
#endif
+ }
priv->vs18_enable = 0;
priv->sdhc_clk = clk_get_rate(&priv->per_clk);
} else {
+#ifndef CONFIG_PPC
priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+#else
+ priv->sdhc_clk = gd->arch.sdhc_clk;
+#endif
if (priv->sdhc_clk <= 0) {
dev_err(dev, "Unable to get clk for %s\n", dev->name);
return -EINVAL;
/* SCC registers */
#define RENESAS_SDHI_SCC_DTCNTL 0x800
-#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
-#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
-#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
+#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
+#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
+#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
#define RENESAS_SDHI_SCC_TAPSET 0x804
#define RENESAS_SDHI_SCC_DT2FF 0x808
#define RENESAS_SDHI_SCC_CKSEL 0x80c
-#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
-#define RENESAS_SDHI_SCC_RVSCNTL 0x810
-#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
+#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
+#define RENESAS_SDHI_SCC_RVSCNTL 0x810
+#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
#define RENESAS_SDHI_SCC_RVSREQ 0x814
-#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
+#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
#define RENESAS_SDHI_SCC_SMPCMP 0x818
-#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
-#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
-#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
+#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
+#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
+#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
+#define RENESAS_SDHI_SCC_TMPPORT3 0x828
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
+#define RENESAS_SDHI_SCC_TMPPORT4 0x82c
+#define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
+#define RENESAS_SDHI_SCC_TMPPORT5 0x830
+#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
+#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
+#define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
+#define RENESAS_SDHI_SCC_TMPPORT6 0x834
+#define RENESAS_SDHI_SCC_TMPPORT7 0x838
+#define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
+#define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
+#define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
#define RENESAS_SDHI_MAX_TAP 3
+static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
+{
+ /* read mode */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
+ (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
+ RENESAS_SDHI_SCC_TMPPORT5);
+
+ /* access start and stop */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
+ RENESAS_SDHI_SCC_TMPPORT4);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
+
+ return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
+}
+
+static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
+{
+ /* write mode */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
+ (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
+ RENESAS_SDHI_SCC_TMPPORT5);
+ tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
+
+ /* access start and stop */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
+ RENESAS_SDHI_SCC_TMPPORT4);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
+}
+
+static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
+{
+ u32 calib_code;
+
+ if (!priv->adjust_hs400_enable)
+ return;
+
+ if (!priv->needs_adjust_hs400)
+ return;
+
+ /*
+ * Enabled Manual adjust HS400 mode
+ *
+ * 1) Disabled Write Protect
+ * W(addr=0x00, WP_DISABLE_CODE)
+ * 2) Read Calibration code and adjust
+ * R(addr=0x26) - adjust value
+ * 3) Enabled Manual Calibration
+ * W(addr=0x22, manual mode | Calibration code)
+ * 4) Set Offset value to TMPPORT3 Reg
+ */
+ sd_scc_tmpport_write32(priv, 0x00,
+ RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
+ calib_code = sd_scc_tmpport_read32(priv, 0x26);
+ calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
+ if (calib_code > priv->adjust_hs400_calibrate)
+ calib_code -= priv->adjust_hs400_calibrate;
+ else
+ calib_code = 0;
+ sd_scc_tmpport_write32(priv, 0x22,
+ RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
+ calib_code);
+ tmio_sd_writel(priv, priv->adjust_hs400_offset,
+ RENESAS_SDHI_SCC_TMPPORT3);
+
+ /* Clear flag */
+ priv->needs_adjust_hs400 = false;
+}
+
+static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
+{
+
+ /* Disabled Manual adjust HS400 mode
+ *
+ * 1) Disabled Write Protect
+ * W(addr=0x00, WP_DISABLE_CODE)
+ * 2) Disabled Manual Calibration
+ * W(addr=0x22, 0)
+ * 3) Clear offset value to TMPPORT3 Reg
+ */
+ sd_scc_tmpport_write32(priv, 0x00,
+ RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
+ sd_scc_tmpport_write32(priv, 0x22, 0);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
+}
+
static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
{
u32 reg;
RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
+ /* Disable HS400 mode adjustment */
+ renesas_sdhi_adjust_hs400_mode_disable(priv);
+
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg |= TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
+ /* Disable HS400 mode adjustment */
+ if (!hs400)
+ renesas_sdhi_adjust_hs400_mode_disable(priv);
+
tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
RENESAS_SDHI_SCC_DTCNTL_TAPEN,
RENESAS_SDHI_SCC_DTCNTL);
reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+ /* Execute adjust hs400 offset after setting to HS400 mode */
+ if (hs400)
+ priv->needs_adjust_hs400 = true;
+
return 0;
}
bool select = false;
u32 reg;
+ priv->needs_adjust_hs400 = false;
+
/* Clear SCC_RVSREQ */
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
}
#endif
+static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ int ret;
+
+ ret = tmio_sd_send_cmd(dev, cmd, data);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+
+ if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
+ renesas_sdhi_adjust_hs400_mode_enable(priv);
+#endif
+
+ return 0;
+}
+
static const struct dm_mmc_ops renesas_sdhi_ops = {
- .send_cmd = tmio_sd_send_cmd,
+ .send_cmd = renesas_sdhi_send_cmd,
.set_ios = renesas_sdhi_set_ios,
.get_cd = tmio_sd_get_cd,
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
return;
- /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */
+ /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() <= 1)))
+ (rmobile_get_cpu_rev_fraction() <= 2)))
plat->cfg.host_caps &= ~MMC_MODE_HS400;
+ /* M3W ES1.x for x>2 can use HS400 with manual adjustment */
+ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ (rmobile_get_cpu_rev_integer() == 1) &&
+ (rmobile_get_cpu_rev_fraction() > 2)) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_offset = 0;
+ priv->adjust_hs400_calibrate = 0x9;
+ }
+
+ /* M3N can use HS400 with manual adjustment */
+ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_offset = 0;
+ priv->adjust_hs400_calibrate = 0x0;
+ }
+
+ /* E3 can use HS400 with manual adjustment */
+ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_offset = 0;
+ priv->adjust_hs400_calibrate = 0x2;
+ }
+
/* H3 ES2.0 uses 4 tuning taps */
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() == 2))
#include <pwrseq.h>
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/periph.h>
#include <linux/err.h>
struct rockchip_mmc_plat {
}
}
-static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
- unsigned int start_addr)
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len,
+ bool end)
+{
+ struct sdhci_adma_desc *desc;
+ u8 attr;
+
+ desc = &host->adma_desc_table[host->desc_slot];
+
+ attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
+ if (!end)
+ host->desc_slot++;
+ else
+ attr |= ADMA_DESC_ATTR_END;
+
+ desc->attr = attr;
+ desc->len = len;
+ desc->reserved = 0;
+ desc->addr_lo = (dma_addr_t)buf;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ desc->addr_hi = (u64)buf >> 32;
+#endif
+}
+
+static void sdhci_prepare_adma_table(struct sdhci_host *host,
+ struct mmc_data *data)
+{
+ uint trans_bytes = data->blocksize * data->blocks;
+ uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
+ int i = desc_count;
+ char *buf;
+
+ host->desc_slot = 0;
+
+ if (data->flags & MMC_DATA_READ)
+ buf = data->dest;
+ else
+ buf = (char *)data->src;
+
+ while (--i) {
+ sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false);
+ buf += ADMA_MAX_LEN;
+ trans_bytes -= ADMA_MAX_LEN;
+ }
+
+ sdhci_adma_desc(host, buf, trans_bytes, true);
+
+ flush_cache((dma_addr_t)host->adma_desc_table,
+ ROUND(desc_count * sizeof(struct sdhci_adma_desc),
+ ARCH_DMA_MINALIGN));
+}
+#elif defined(CONFIG_MMC_SDHCI_SDMA)
+static void sdhci_prepare_adma_table(struct sdhci_host *host,
+ struct mmc_data *data)
+{}
+#endif
+#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
+static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
+ int *is_aligned, int trans_bytes)
{
- unsigned int stat, rdy, mask, timeout, block = 0;
- bool transfer_done = false;
-#ifdef CONFIG_MMC_SDHCI_SDMA
unsigned char ctrl;
+
+ if (data->flags == MMC_DATA_READ)
+ host->start_addr = (dma_addr_t)data->dest;
+ else
+ host->start_addr = (dma_addr_t)data->src;
+
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
+ if (host->flags & USE_ADMA64)
+ ctrl |= SDHCI_CTRL_ADMA64;
+ else if (host->flags & USE_ADMA)
+ ctrl |= SDHCI_CTRL_ADMA32;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ if (host->flags & USE_SDMA) {
+ if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
+ (host->start_addr & 0x7) != 0x0) {
+ *is_aligned = 0;
+ host->start_addr = (unsigned long)aligned_buffer;
+ if (data->flags != MMC_DATA_READ)
+ memcpy(aligned_buffer, data->src, trans_bytes);
+ }
+
+#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
+ /*
+ * Always use this bounce-buffer when
+ * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
+ */
+ *is_aligned = 0;
+ host->start_addr = (unsigned long)aligned_buffer;
+ if (data->flags != MMC_DATA_READ)
+ memcpy(aligned_buffer, data->src, trans_bytes);
+#endif
+ sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
+
+ } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
+ sdhci_prepare_adma_table(host, data);
+
+ sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS);
+ if (host->flags & USE_ADMA64)
+ sdhci_writel(host, (u64)host->adma_addr >> 32,
+ SDHCI_ADMA_ADDRESS_HI);
+ }
+
+ flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
+}
+#else
+static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
+ int *is_aligned, int trans_bytes)
+{}
#endif
+static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
+{
+ dma_addr_t start_addr = host->start_addr;
+ unsigned int stat, rdy, mask, timeout, block = 0;
+ bool transfer_done = false;
timeout = 1000000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
continue;
}
}
-#ifdef CONFIG_MMC_SDHCI_SDMA
- if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
+ if ((host->flags & USE_DMA) && !transfer_done &&
+ (stat & SDHCI_INT_DMA_END)) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
- start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
- start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
- sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
+ if (host->flags & USE_SDMA) {
+ start_addr &=
+ ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
+ start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
+ sdhci_writel(host, start_addr,
+ SDHCI_DMA_ADDRESS);
+ }
}
-#endif
if (timeout-- > 0)
udelay(10);
else {
int ret = 0;
int trans_bytes = 0, is_aligned = 1;
u32 mask, flags, mode;
- unsigned int time = 0, start_addr = 0;
+ unsigned int time = 0;
int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
ulong start = get_timer(0);
+ host->start_addr = 0;
/* Timeout unit - ms */
static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
if (data->flags == MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
-#ifdef CONFIG_MMC_SDHCI_SDMA
- if (data->flags == MMC_DATA_READ)
- start_addr = (unsigned long)data->dest;
- else
- start_addr = (unsigned long)data->src;
- if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
- (start_addr & 0x7) != 0x0) {
- is_aligned = 0;
- start_addr = (unsigned long)aligned_buffer;
- if (data->flags != MMC_DATA_READ)
- memcpy(aligned_buffer, data->src, trans_bytes);
+ if (host->flags & USE_DMA) {
+ mode |= SDHCI_TRNS_DMA;
+ sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
}
-#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
- /*
- * Always use this bounce-buffer when
- * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
- */
- is_aligned = 0;
- start_addr = (unsigned long)aligned_buffer;
- if (data->flags != MMC_DATA_READ)
- memcpy(aligned_buffer, data->src, trans_bytes);
-#endif
-
- sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
- mode |= SDHCI_TRNS_DMA;
-#endif
sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
data->blocksize),
SDHCI_BLOCK_SIZE);
}
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
-#ifdef CONFIG_MMC_SDHCI_SDMA
- if (data) {
- trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
- flush_cache(start_addr, trans_bytes);
- }
-#endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
start = get_timer(0);
do {
ret = -1;
if (!ret && data)
- ret = sdhci_transfer_data(host, data, start_addr);
+ ret = sdhci_transfer_data(host, data);
if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
udelay(1000);
__func__);
return -EINVAL;
}
+
+ host->flags |= USE_SDMA;
+#endif
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+ if (!(caps & SDHCI_CAN_DO_ADMA2)) {
+ printf("%s: Your controller doesn't support SDMA!!\n",
+ __func__);
+ return -EINVAL;
+ }
+ host->adma_desc_table = (struct sdhci_adma_desc *)
+ memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
+
+ host->adma_addr = (dma_addr_t)host->adma_desc_table;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ host->flags |= USE_ADMA64;
+#else
+ host->flags |= USE_ADMA;
+#endif
#endif
if (host->quirks & SDHCI_QUIRK_REG32_RW)
host->version =
#if CONFIG_IS_ENABLED(RENESAS_SDHI)
u8 tap_set;
u8 nrtaps;
+ bool needs_adjust_hs400;
+ bool adjust_hs400_enable;
+ u8 adjust_hs400_offset;
+ u8 adjust_hs400_calibrate;
#endif
ulong (*clk_get_rate)(struct tmio_sd_priv *);
};
return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
}
-static void nand_flash_init(void)
-{
- /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
- * Instead, have your board_init() set EMIF timings, based on its
- * knowledge of the clocks and what devices are hooked up ... and
- * don't even do that unless no UBL handled it.
- */
-#ifdef CONFIG_SOC_DM644X
- u_int32_t acfg1 = 0x3ffffffc;
-
- /*------------------------------------------------------------------*
- * NAND FLASH CHIP TIMEOUT @ 459 MHz *
- * *
- * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
- * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
- * *
- *------------------------------------------------------------------*/
- acfg1 = 0
- | (0 << 31) /* selectStrobe */
- | (0 << 30) /* extWait */
- | (1 << 26) /* writeSetup 10 ns */
- | (3 << 20) /* writeStrobe 40 ns */
- | (1 << 17) /* writeHold 10 ns */
- | (1 << 13) /* readSetup 10 ns */
- | (5 << 7) /* readStrobe 60 ns */
- | (1 << 4) /* readHold 10 ns */
- | (3 << 2) /* turnAround ?? ns */
- | (0 << 0) /* asyncSize 8-bit bus */
- ;
-
- __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
-
- /* NAND flash on CS2 */
- __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
-#endif
-}
-
void davinci_nand_init(struct nand_chip *nand)
{
#if defined CONFIG_KEYSTONE_RBL_NAND
nand->write_buf = nand_davinci_write_buf;
nand->dev_ready = nand_davinci_dev_ready;
-
- nand_flash_init();
}
int board_nand_init(struct nand_chip *chip) __attribute__((weak));
#include <asm/fsl_lbc.h>
#include <nand.h>
+#ifdef CONFIG_MPC83xx
+#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
+#endif
+
#define WINDOW_SIZE 8192
static void nand_wait(void)
/*
* Cache management functions
*/
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
{
uint32_t addr = (uint32_t)info->data_buf;
SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_OUT(len, buf, 1));
- size_t remaining = len;
int ret;
/* get transfer protocols. */
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
op.addr.nbytes = 0;
- while (remaining) {
- op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
- ret = spi_mem_adjust_op_size(nor->spi, &op);
- if (ret)
- return ret;
-
- ret = spi_mem_exec_op(nor->spi, &op);
- if (ret)
- return ret;
+ ret = spi_mem_adjust_op_size(nor->spi, &op);
+ if (ret)
+ return ret;
+ op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
- op.addr.val += op.data.nbytes;
- remaining -= op.data.nbytes;
- op.data.buf.out += op.data.nbytes;
- }
+ ret = spi_mem_exec_op(nor->spi, &op);
+ if (ret)
+ return ret;
- return len;
+ return op.data.nbytes;
}
/*
goto write_err;
*retlen += written;
i += written;
- if (written != page_remain) {
- ret = -EIO;
- goto write_err;
- }
}
write_err:
config MTD_UBI
bool "Enable UBI - Unsorted block images"
- select CRC32
select RBTREE
select MTD_PARTITIONS
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
+config FMAN_ENET
+ bool "Freescale FMan ethernet support"
+ depends on ARM || PPC
+ help
+ This driver support the Freescale FMan Ethernet controller
+
config FTMAC100
bool "Ftmac100 Ethernet Support"
help
config MT7628_ETH
bool "MediaTek MT7628 Ethernet Interface"
- depends on ARCH_MT7620
+ depends on SOC_MT7628
help
The MediaTek MT7628 ethernet interface is used on MT7628 and
MT7688 based boards.
*/
#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
- !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning Cache line size is larger than descriptor size
#endif
#endif
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
CONFIG_SYS_FMAN_FW_ADDR, rc);
}
-#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
struct spi_flash *ucode_flash;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
#include <phy.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/grf_rk322x.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/grf_rk3328.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/grf_rk3399.h>
-#include <asm/arch/grf_rv1108.h>
+#include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk322x.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/grf_rk3328.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/grf_rv1108.h>
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include "designware.h"
priv = (struct ldpaa_eth_priv *)malloc(sizeof(struct ldpaa_eth_priv));
if (!priv) {
printf("ldpaa_eth_priv malloc() failed\n");
+ free(net_dev);
return -ENOMEM;
}
memset(priv, 0, sizeof(struct ldpaa_eth_priv));
/**
* macb_linkspd_cb - Linkspeed change callback function
- * @regs: Base Register of MACB devices
+ * @dev/@regs: MACB udevice (DM version) or
+ * Base Register of MACB devices (non-DM version)
* @speed: Linkspeed
* Returns 0 when operation success and negative errno number
* when operation failed.
*/
+#ifdef CONFIG_DM_ETH
+int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
+{
+#ifdef CONFIG_CLK
+ struct clk tx_clk;
+ ulong rate;
+ int ret;
+
+ /*
+ * "tx_clk" is an optional clock source for MACB.
+ * Ignore if it does not exist in DT.
+ */
+ ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
+ if (ret)
+ return 0;
+
+ switch (speed) {
+ case _10BASET:
+ rate = 2500000; /* 2.5 MHz */
+ break;
+ case _100BASET:
+ rate = 25000000; /* 25 MHz */
+ break;
+ case _1000BASET:
+ rate = 125000000; /* 125 MHz */
+ break;
+ default:
+ /* does not change anything */
+ return 0;
+ }
+
+ if (tx_clk.dev) {
+ ret = clk_set_rate(&tx_clk, rate);
+ if (ret)
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+#else
int __weak macb_linkspd_cb(void *regs, unsigned int speed)
{
return 0;
}
+#endif
#ifdef CONFIG_DM_ETH
static int macb_phy_init(struct udevice *dev, const char *name)
macb_writel(macb, NCFGR, ncfgr);
+#ifdef CONFIG_DM_ETH
+ ret = macb_linkspd_cb(dev, _1000BASET);
+#else
ret = macb_linkspd_cb(macb->regs, _1000BASET);
+#endif
if (ret)
return ret;
ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
if (speed) {
ncfgr |= MACB_BIT(SPD);
+#ifdef CONFIG_DM_ETH
+ ret = macb_linkspd_cb(dev, _100BASET);
+#else
ret = macb_linkspd_cb(macb->regs, _100BASET);
+#endif
} else {
+#ifdef CONFIG_DM_ETH
+ ret = macb_linkspd_cb(dev, _10BASET);
+#else
ret = macb_linkspd_cb(macb->regs, _10BASET);
+#endif
}
if (ret)
select PHYLIB
help
This driver supports the Servalt network switch device.
+
+config MSCC_SERVAL_SWITCH
+ bool "Serval switch driver"
+ depends on DM_ETH && ARCH_MSCC
+ select PHYLIB
+ help
+ This driver supports the Serval network switch device.
-obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o
-obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o mscc_mac_table.o
+obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o
obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o
obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o
+obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o mscc_mac_table.o
#include <net.h>
#include <wait_bit.h>
-#include "mscc_miim.h"
#include "mscc_xfer.h"
#include "mscc_mac_table.h"
+#define GCB_MIIM_MII_STATUS 0x0
+#define GCB_MIIM_STAT_BUSY BIT(3)
+#define GCB_MIIM_MII_CMD 0x8
+#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
+#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
+#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
+#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
+#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
+#define GCB_MIIM_MII_CMD_VLD BIT(31)
+#define GCB_MIIM_DATA 0xC
+#define GCB_MIIM_DATA_ERROR (0x2 << 16)
+
#define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x))
#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
#define PGID_UNICAST 29
#define PGID_SRC 80
-enum luton_target {
- PORT0,
- PORT1,
- PORT2,
- PORT3,
- PORT4,
- PORT5,
- PORT6,
- PORT7,
- PORT8,
- PORT9,
- PORT10,
- PORT11,
- PORT12,
- PORT13,
- PORT14,
- PORT15,
- PORT16,
- PORT17,
- PORT18,
- PORT19,
- PORT20,
- PORT21,
- PORT22,
- PORT23,
- SYS,
+static const char * const regs_names[] = {
+ "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10", "port11", "port12", "port13", "port14",
+ "port15", "port16", "port17", "port18", "port19", "port20", "port21",
+ "port22", "port23",
+ "sys", "ana", "rew", "gcb", "qs", "hsio",
+};
+
+#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
+#define MAX_PORT 24
+
+enum luton_ctrl_regs {
+ SYS = MAX_PORT,
ANA,
REW,
GCB,
QS,
- HSIO,
- TARGET_MAX,
+ HSIO
};
-#define MAX_PORT (PORT23 - PORT0 + 1)
+#define MIN_INT_PORT 0
+#define PORT10 10
+#define PORT11 11
+#define MAX_INT_PORT 12
+#define MIN_EXT_PORT MAX_INT_PORT
+#define MAX_EXT_PORT MAX_PORT
-#define MIN_INT_PORT PORT0
-#define MAX_INT_PORT (PORT11 - PORT0 + 1)
-#define MIN_EXT_PORT PORT12
-#define MAX_EXT_PORT MAX_PORT
+#define LUTON_MIIM_BUS_COUNT 2
-enum luton_mdio_target {
- MIIM,
- TARGET_MDIO_MAX,
+struct luton_phy_port_t {
+ size_t phy_addr;
+ struct mii_dev *bus;
+ u8 serdes_index;
+ u8 phy_mode;
};
-enum luton_phy_id {
- INTERNAL,
- EXTERNAL,
- NUM_PHY,
+struct luton_private {
+ void __iomem *regs[REGS_NAMES_COUNT];
+ struct mii_dev *bus[LUTON_MIIM_BUS_COUNT];
+ struct luton_phy_port_t ports[MAX_PORT];
};
-struct luton_private {
- void __iomem *regs[TARGET_MAX];
- struct mii_dev *bus[NUM_PHY];
+struct mscc_miim_dev {
+ void __iomem *regs;
+ phys_addr_t miim_base;
+ unsigned long miim_size;
+ struct mii_dev *bus;
};
static const unsigned long luton_regs_qs[] = {
[MSCC_ANA_TABLES_MACACCESS] = 0x11b8,
};
-static struct mscc_miim_dev miim[NUM_PHY];
+static struct mscc_miim_dev miim[LUTON_MIIM_BUS_COUNT];
+static int miim_count = -1;
-static struct mii_dev *luton_mdiobus_init(struct udevice *dev,
- int mdiobus_id)
+static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+{
+ return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
+ GCB_MIIM_STAT_BUSY, false, 250, false);
+}
+
+static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ u32 val;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
+ GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
+ miim->regs + GCB_MIIM_MII_CMD);
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ val = readl(miim->regs + GCB_MIIM_DATA);
+ if (val & GCB_MIIM_DATA_ERROR) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = val & 0xFFFF;
+ out:
+ return ret;
+}
+
+static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret < 0)
+ goto out;
+
+ writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
+ GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
+ GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
+ out:
+ return ret;
+}
+
+static struct mii_dev *serval_mdiobus_init(phys_addr_t miim_base,
+ unsigned long miim_size)
{
- unsigned long phy_size[NUM_PHY];
- phys_addr_t phy_base[NUM_PHY];
- struct ofnode_phandle_args phandle;
- ofnode eth_node, node, mdio_node;
- struct resource res;
struct mii_dev *bus;
- fdt32_t faddr;
- int i;
bus = mdio_alloc();
if (!bus)
return NULL;
- /* gather only the first mdio bus */
- eth_node = dev_read_first_subnode(dev);
- node = ofnode_first_subnode(eth_node);
- ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
- &phandle);
- mdio_node = ofnode_get_parent(phandle.node);
-
- for (i = 0; i < TARGET_MDIO_MAX; i++) {
- if (ofnode_read_resource(mdio_node, i, &res)) {
- pr_err("%s: get OF resource failed\n", __func__);
- return NULL;
- }
-
- faddr = cpu_to_fdt32(res.start);
- phy_base[i] = ofnode_translate_address(mdio_node, &faddr);
- phy_size[i] = res.end - res.start;
- }
+ ++miim_count;
+ sprintf(bus->name, "miim-bus%d", miim_count);
- strcpy(bus->name, "miim-internal");
- miim[mdiobus_id].regs = ioremap(phy_base[mdiobus_id],
- phy_size[mdiobus_id]);
- bus->priv = &miim[mdiobus_id];
+ miim[miim_count].regs = ioremap(miim_base, miim_size);
+ miim[miim_count].miim_base = miim_base;
+ miim[miim_count].miim_size = miim_size;
+ bus->priv = &miim[miim_count];
bus->read = mscc_miim_read;
bus->write = mscc_miim_write;
if (mdio_register(bus))
return NULL;
- else
- return bus;
+
+ miim[miim_count].bus = bus;
+ return bus;
}
static void luton_stop(struct udevice *dev)
writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
ANA_PORT_VLAN_CFG_POP_CNT(1) |
MAC_VID,
- priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+ priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
/* Enable switching to/from port */
- setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port - PORT0),
+ setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port),
SYS_SWITCH_PORT_MODE_PORT_ENA);
}
writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
ANA_PORT_VLAN_CFG_POP_CNT(1) |
MAC_VID,
- priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+ priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
/* Enable switching to/from port */
- setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port - PORT0),
+ setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port),
SYS_SWITCH_PORT_MODE_PORT_ENA);
}
writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
ANA_PORT_VLAN_CFG_POP_CNT(1) |
MAC_VID,
- priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+ priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
/* Enable switching to/from port */
- setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port - PORT0),
+ setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port),
SYS_SWITCH_PORT_MODE_PORT_ENA);
}
-static void serdes6g_write(struct luton_private *priv, u32 addr)
+static void serdes6g_write(void __iomem *base, u32 addr)
{
u32 data;
writel(HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT |
HSIO_MCB_SERDES6G_CFG_ADDR(addr),
- priv->regs[HSIO] + HSIO_MCB_SERDES6G_CFG);
+ base + HSIO_MCB_SERDES6G_CFG);
do {
- data = readl(priv->regs[HSIO] + HSIO_MCB_SERDES6G_CFG);
+ data = readl(base + HSIO_MCB_SERDES6G_CFG);
} while (data & HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT);
-
- mdelay(100);
}
-static void serdes6g_cfg(struct luton_private *priv)
+static void serdes6g_setup(void __iomem *base, uint32_t addr,
+ phy_interface_t interface)
{
writel(HSIO_RCOMP_CFG_CFG0_MODE_SEL(0x3) |
HSIO_RCOMP_CFG_CFG0_RUN_CAL,
- priv->regs[HSIO] + HSIO_RCOMP_CFG_CFG0);
+ base + HSIO_RCOMP_CFG_CFG0);
- while (readl(priv->regs[HSIO] + HSIO_RCOMP_STATUS) &
+ while (readl(base + HSIO_RCOMP_STATUS) &
HSIO_RCOMP_STATUS_BUSY)
;
HSIO_SERDES6G_ANA_CFG_OB_CFG_POST0(0x10) |
HSIO_SERDES6G_ANA_CFG_OB_CFG_POL |
HSIO_SERDES6G_ANA_CFG_OB_CFG_ENA1V_MODE,
- priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_OB_CFG);
+ base + HSIO_SERDES6G_ANA_CFG_OB_CFG);
writel(HSIO_SERDES6G_ANA_CFG_OB_CFG1_LEV(0x18) |
HSIO_SERDES6G_ANA_CFG_OB_CFG1_ENA_CAS(0x1),
- priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_OB_CFG1);
+ base + HSIO_SERDES6G_ANA_CFG_OB_CFG1);
writel(HSIO_SERDES6G_ANA_CFG_IB_CFG_RESISTOR_CTRL(0xc) |
HSIO_SERDES6G_ANA_CFG_IB_CFG_VBCOM(0x4) |
HSIO_SERDES6G_ANA_CFG_IB_CFG_VBAC(0x5) |
HSIO_SERDES6G_ANA_CFG_IB_CFG_RT(0xf) |
HSIO_SERDES6G_ANA_CFG_IB_CFG_RF(0x4),
- priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_IB_CFG);
+ base + HSIO_SERDES6G_ANA_CFG_IB_CFG);
writel(HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST |
HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSDC |
HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSAC |
HSIO_SERDES6G_ANA_CFG_IB_CFG1_ANEG_MODE |
HSIO_SERDES6G_ANA_CFG_IB_CFG1_CHF |
HSIO_SERDES6G_ANA_CFG_IB_CFG1_C(0x4),
- priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_IB_CFG1);
+ base + HSIO_SERDES6G_ANA_CFG_IB_CFG1);
writel(HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_ANA(0x5) |
HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_HYST(0x5) |
HSIO_SERDES6G_ANA_CFG_DES_CFG_MBTR_CTRL(0x2) |
HSIO_SERDES6G_ANA_CFG_DES_CFG_PHS_CTRL(0x6),
- priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_DES_CFG);
+ base + HSIO_SERDES6G_ANA_CFG_DES_CFG);
writel(HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_ENA |
HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_CTRL_DATA(0x78),
- priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_PLL_CFG);
+ base + HSIO_SERDES6G_ANA_CFG_PLL_CFG);
writel(HSIO_SERDES6G_ANA_CFG_COMMON_CFG_IF_MODE(0x30) |
HSIO_SERDES6G_ANA_CFG_COMMON_CFG_ENA_LANE,
- priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_COMMON_CFG);
+ base + HSIO_SERDES6G_ANA_CFG_COMMON_CFG);
/*
* There are 4 serdes6g, configure all except serdes6g0, therefore
* the address is b1110
*/
- serdes6g_write(priv, 0xe);
+ serdes6g_write(base, addr);
- writel(readl(priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_COMMON_CFG) |
+ writel(readl(base + HSIO_SERDES6G_ANA_CFG_COMMON_CFG) |
HSIO_SERDES6G_ANA_CFG_COMMON_CFG_SYS_RST,
- priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_COMMON_CFG);
- serdes6g_write(priv, 0xe);
+ base + HSIO_SERDES6G_ANA_CFG_COMMON_CFG);
+ serdes6g_write(base, addr);
- clrbits_le32(priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_IB_CFG1,
+ clrbits_le32(base + HSIO_SERDES6G_ANA_CFG_IB_CFG1,
HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST);
writel(HSIO_SERDES6G_DIG_CFG_MISC_CFG_LANE_RST,
- priv->regs[HSIO] + HSIO_SERDES6G_DIG_CFG_MISC_CFG);
- serdes6g_write(priv, 0xe);
+ base + HSIO_SERDES6G_DIG_CFG_MISC_CFG);
+ serdes6g_write(base, addr);
+}
+
+static void serdes_setup(struct luton_private *priv)
+{
+ size_t mask;
+ int i = 0;
+
+ for (i = 0; i < MAX_PORT; ++i) {
+ if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff)
+ continue;
+
+ mask = BIT(priv->ports[i].serdes_index);
+ serdes6g_setup(priv->regs[HSIO], mask, priv->ports[i].phy_mode);
+ }
}
static int luton_switch_init(struct luton_private *priv)
setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
SYS_SYSTEM_RST_CORE_ENA);
- /* Setup the Serdes6g macros */
- serdes6g_cfg(priv);
+ /* Setup the Serdes macros */
+ serdes_setup(priv);
return 0;
}
writel(2000000000 / 4,
priv->regs[SYS] + SYS_FRM_AGING);
- for (i = PORT0; i < MAX_PORT; i++) {
+ for (i = 0; i < MAX_PORT; i++) {
if (i < PORT10)
luton_gmii_port_init(priv, i);
else
return byte_cnt;
}
+static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
+{
+ int i = 0;
+
+ for (i = 0; i < LUTON_MIIM_BUS_COUNT; ++i)
+ if (miim[i].miim_base == base && miim[i].miim_size == size)
+ return miim[i].bus;
+
+ return NULL;
+}
+
+static void add_port_entry(struct luton_private *priv, size_t index,
+ size_t phy_addr, struct mii_dev *bus,
+ u8 serdes_index, u8 phy_mode)
+{
+ priv->ports[index].phy_addr = phy_addr;
+ priv->ports[index].bus = bus;
+ priv->ports[index].serdes_index = serdes_index;
+ priv->ports[index].phy_mode = phy_mode;
+}
+
static int luton_probe(struct udevice *dev)
{
struct luton_private *priv = dev_get_priv(dev);
- int i;
-
- struct {
- enum luton_target id;
- char *name;
- } reg[] = {
- { PORT0, "port0" },
- { PORT1, "port1" },
- { PORT2, "port2" },
- { PORT3, "port3" },
- { PORT4, "port4" },
- { PORT5, "port5" },
- { PORT6, "port6" },
- { PORT7, "port7" },
- { PORT8, "port8" },
- { PORT9, "port9" },
- { PORT10, "port10" },
- { PORT11, "port11" },
- { PORT12, "port12" },
- { PORT13, "port13" },
- { PORT14, "port14" },
- { PORT15, "port15" },
- { PORT16, "port16" },
- { PORT17, "port17" },
- { PORT18, "port18" },
- { PORT19, "port19" },
- { PORT20, "port20" },
- { PORT21, "port21" },
- { PORT22, "port22" },
- { PORT23, "port23" },
- { SYS, "sys" },
- { ANA, "ana" },
- { REW, "rew" },
- { GCB, "gcb" },
- { QS, "qs" },
- { HSIO, "hsio" },
- };
+ int i, ret;
+ struct resource res;
+ fdt32_t faddr;
+ phys_addr_t addr_base;
+ unsigned long addr_size;
+ ofnode eth_node, node, mdio_node;
+ size_t phy_addr;
+ struct mii_dev *bus;
+ struct ofnode_phandle_args phandle;
+ struct phy_device *phy;
if (!priv)
return -EINVAL;
- for (i = 0; i < ARRAY_SIZE(reg); i++) {
- priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
- if (!priv->regs[reg[i].id]) {
+ /* Get registers and map them to the private structure */
+ for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
+ priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
+ if (!priv->regs[i]) {
debug
("Error can't get regs base addresses for %s\n",
- reg[i].name);
+ regs_names[i]);
return -ENOMEM;
}
}
writel(0, priv->regs[GCB] + GCB_DEVCPU_RST_SOFT_CHIP_RST);
/* Ports with ext phy don't need to reset clk */
- for (i = PORT0; i < MAX_INT_PORT; i++) {
+ for (i = 0; i < MAX_INT_PORT; i++) {
if (i < PORT10)
clrbits_le32(priv->regs[i] + DEV_GMII_PORT_MODE_CLK,
DEV_GMII_PORT_MODE_CLK_PHY_RST);
GCB_MISC_STAT_PHY_READY, true, 500, false))
return -EACCES;
- priv->bus[INTERNAL] = luton_mdiobus_init(dev, INTERNAL);
- for (i = 0; i < MAX_INT_PORT; i++) {
- phy_connect(priv->bus[INTERNAL], i, dev,
- PHY_INTERFACE_MODE_NONE);
+ /* Initialize miim buses */
+ memset(&miim, 0x0, sizeof(miim) * LUTON_MIIM_BUS_COUNT);
+
+ /* iterate all the ports and find out on which bus they are */
+ i = 0;
+ eth_node = dev_read_first_subnode(dev);
+ for (node = ofnode_first_subnode(eth_node);
+ ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ if (ofnode_read_resource(node, 0, &res))
+ return -ENOMEM;
+ i = res.start;
+
+ ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
+ 0, 0, &phandle);
+ if (ret)
+ continue;
+
+ /* Get phy address on mdio bus */
+ if (ofnode_read_resource(phandle.node, 0, &res))
+ return -ENOMEM;
+ phy_addr = res.start;
+
+ /* Get mdio node */
+ mdio_node = ofnode_get_parent(phandle.node);
+
+ if (ofnode_read_resource(mdio_node, 0, &res))
+ return -ENOMEM;
+ faddr = cpu_to_fdt32(res.start);
+
+ addr_base = ofnode_translate_address(mdio_node, &faddr);
+ addr_size = res.end - res.start;
+
+ /* If the bus is new then create a new bus */
+ if (!get_mdiobus(addr_base, addr_size))
+ priv->bus[miim_count] =
+ serval_mdiobus_init(addr_base, addr_size);
+
+ /* Connect mdio bus with the port */
+ bus = get_mdiobus(addr_base, addr_size);
+
+ /* Get serdes info */
+ ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
+ 3, 0, &phandle);
+ if (ret)
+ add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff);
+ else
+ add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
+ phandle.args[2]);
+ }
+
+ for (i = 0; i < MAX_PORT; i++) {
+ if (!priv->ports[i].bus)
+ continue;
+
+ phy = phy_connect(priv->ports[i].bus,
+ priv->ports[i].phy_addr, dev,
+ PHY_INTERFACE_MODE_NONE);
+ if (phy && i >= MAX_INT_PORT)
+ board_phy_config(phy);
}
/*
* coma_mode is need on only one phy, because all the other phys
* will be affected.
*/
- mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0x10);
- mscc_miim_write(priv->bus[INTERNAL], 0, 0, 14, 0x800);
- mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0);
+ mscc_miim_write(priv->ports[0].bus, 0, 0, 31, 0x10);
+ mscc_miim_write(priv->ports[0].bus, 0, 0, 14, 0x800);
+ mscc_miim_write(priv->ports[0].bus, 0, 0, 31, 0);
return 0;
}
struct luton_private *priv = dev_get_priv(dev);
int i;
- for (i = 0; i < NUM_PHY; i++) {
+ for (i = 0; i < LUTON_MIIM_BUS_COUNT; i++) {
mdio_unregister(priv->bus[i]);
mdio_free(priv->bus[i]);
}
#include <net.h>
#include <wait_bit.h>
-#include "mscc_miim.h"
#include "mscc_xfer.h"
#include "mscc_mac_table.h"
#define PHY_STAT 0x4
#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0)
+#define GCB_MIIM_MII_STATUS 0x0
+#define GCB_MIIM_STAT_BUSY BIT(3)
+#define GCB_MIIM_MII_CMD 0x8
+#define GCB_MIIM_MII_CMD_SCAN BIT(0)
+#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
+#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
+#define GCB_MIIM_MII_CMD_SINGLE_SCAN BIT(3)
+#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
+#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
+#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
+#define GCB_MIIM_MII_CMD_VLD BIT(31)
+#define GCB_MIIM_DATA 0xC
+#define GCB_MIIM_DATA_ERROR (0x3 << 16)
+
#define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x))
#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
#define ANA_PGID(x) (0x8c00 + 4 * (x))
+#define HSIO_ANA_SERDES1G_DES_CFG 0x4c
+#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1)
+#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5)
+#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8)
+#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13)
+#define HSIO_ANA_SERDES1G_IB_CFG 0x50
+#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x)
+#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6)
+#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9)
+#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11)
+#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13)
+#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24)
+#define HSIO_ANA_SERDES1G_OB_CFG 0x54
+#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x)
+#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4)
+#define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10)
+#define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13)
+#define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17)
+#define HSIO_ANA_SERDES1G_SER_CFG 0x58
+#define HSIO_ANA_SERDES1G_COMMON_CFG 0x5c
+#define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0)
+#define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18)
+#define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31)
+#define HSIO_ANA_SERDES1G_PLL_CFG 0x60
+#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7)
+#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
+#define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21)
+#define HSIO_DIG_SERDES1G_DFT_CFG0 0x68
+#define HSIO_DIG_SERDES1G_MISC_CFG 0x7c
+#define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0)
+#define HSIO_MCB_SERDES1G_CFG 0x88
+#define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31)
+#define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x)
+#define HSIO_HW_CFGSTAT_HW_CFG 0x10c
+
#define SYS_FRM_AGING 0x574
#define SYS_FRM_AGING_ENA BIT(20)
#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
#define IFH_INJ_BYPASS BIT(31)
-#define IFH_TAG_TYPE_C 0
-#define MAC_VID 1
+#define IFH_TAG_TYPE_C 0
+#define MAC_VID 1
#define CPU_PORT 11
-#define INTERNAL_PORT_MSK 0xF
+#define INTERNAL_PORT_MSK 0x2FF
#define IFH_LEN 4
#define ETH_ALEN 6
-#define PGID_BROADCAST 13
-#define PGID_UNICAST 14
-#define PGID_SRC 80
+#define PGID_BROADCAST 13
+#define PGID_UNICAST 14
+#define PGID_SRC 80
-enum ocelot_target {
- ANA,
- QS,
- QSYS,
+static const char * const regs_names[] = {
+ "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7",
+ "port8", "port9", "port10", "sys", "rew", "qs", "hsio", "qsys", "ana",
+};
+
+#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
+#define MAX_PORT 11
+
+enum ocelot_ctrl_regs {
+ SYS = MAX_PORT,
REW,
- SYS,
+ QS,
HSIO,
- PORT0,
- PORT1,
- PORT2,
- PORT3,
- TARGET_MAX,
+ QSYS,
+ ANA,
};
-#define MAX_PORT (PORT3 - PORT0)
+#define OCELOT_MIIM_BUS_COUNT 2
-enum ocelot_mdio_target {
- MIIM,
- PHY,
- TARGET_MDIO_MAX,
+struct ocelot_phy_port_t {
+ size_t phy_addr;
+ struct mii_dev *bus;
+ u8 serdes_index;
+ u8 phy_mode;
};
-enum ocelot_phy_id {
- INTERNAL,
- EXTERNAL,
- NUM_PHY,
+struct ocelot_private {
+ void __iomem *regs[REGS_NAMES_COUNT];
+ struct mii_dev *bus[OCELOT_MIIM_BUS_COUNT];
+ struct ocelot_phy_port_t ports[MAX_PORT];
};
-struct ocelot_private {
- void __iomem *regs[TARGET_MAX];
- struct mii_dev *bus[NUM_PHY];
+struct mscc_miim_dev {
+ void __iomem *regs;
+ phys_addr_t miim_base;
+ unsigned long miim_size;
+ struct mii_dev *bus;
};
+static struct mscc_miim_dev miim[OCELOT_MIIM_BUS_COUNT];
+static int miim_count = -1;
+
static const unsigned long ocelot_regs_qs[] = {
[MSCC_QS_XTR_RD] = 0x8,
[MSCC_QS_XTR_FLUSH] = 0x18,
[MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
};
-static struct mscc_miim_dev miim[NUM_PHY];
-
static void mscc_phy_reset(void)
{
- writel(0, miim[INTERNAL].phy_regs + PHY_CFG);
+ writel(0, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG);
writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
- | PHY_CFG_ENA, miim[INTERNAL].phy_regs + PHY_CFG);
- if (wait_for_bit_le32(miim[INTERNAL].phy_regs + PHY_STAT,
- PHY_STAT_SUPERVISOR_COMPLETE,
+ | PHY_CFG_ENA, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG);
+ if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + PERF_PHY_CFG) +
+ PHY_STAT, PHY_STAT_SUPERVISOR_COMPLETE,
true, 2000, false)) {
pr_err("Timeout in phy reset\n");
}
}
-/* For now only setup the internal mdio bus */
-static struct mii_dev *ocelot_mdiobus_init(struct udevice *dev)
+static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+{
+ return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
+ GCB_MIIM_STAT_BUSY, false, 250, false);
+}
+
+static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ u32 val;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
+ GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
+ miim->regs + GCB_MIIM_MII_CMD);
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ val = readl(miim->regs + GCB_MIIM_DATA);
+ if (val & GCB_MIIM_DATA_ERROR) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = val & 0xFFFF;
+ out:
+ return ret;
+}
+
+static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret < 0)
+ goto out;
+
+ writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
+ GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
+ GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
+ out:
+ return ret;
+}
+
+static struct mii_dev *ocelot_mdiobus_init(phys_addr_t miim_base,
+ unsigned long miim_size)
{
- unsigned long phy_size[TARGET_MAX];
- phys_addr_t phy_base[TARGET_MAX];
- struct ofnode_phandle_args phandle;
- ofnode eth_node, node, mdio_node;
- struct resource res;
struct mii_dev *bus;
- fdt32_t faddr;
- int i;
bus = mdio_alloc();
if (!bus)
return NULL;
- /* gathered only the first mdio bus */
- eth_node = dev_read_first_subnode(dev);
- node = ofnode_first_subnode(eth_node);
- ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
- &phandle);
- mdio_node = ofnode_get_parent(phandle.node);
-
- for (i = 0; i < TARGET_MDIO_MAX; i++) {
- if (ofnode_read_resource(mdio_node, i, &res)) {
- pr_err("%s: get OF resource failed\n", __func__);
- return NULL;
- }
- faddr = cpu_to_fdt32(res.start);
- phy_base[i] = ofnode_translate_address(mdio_node, &faddr);
- phy_size[i] = res.end - res.start;
- }
+ ++miim_count;
+ sprintf(bus->name, "miim-bus%d", miim_count);
- strcpy(bus->name, "miim-internal");
- miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);
- miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);
- bus->priv = &miim[INTERNAL];
+ miim[miim_count].regs = ioremap(miim_base, miim_size);
+ miim[miim_count].miim_base = miim_base;
+ miim[miim_count].miim_size = miim_size;
+ bus->priv = &miim[miim_count];
bus->read = mscc_miim_read;
bus->write = mscc_miim_write;
if (mdio_register(bus))
return NULL;
- else
- return bus;
+
+ miim[miim_count].bus = bus;
+ return bus;
}
__weak void mscc_switch_reset(void)
/* Make VLAN aware for CPU traffic */
writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
- MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+ MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
/* Enable the port in the core */
- setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port - PORT0),
+ setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
QSYS_SWITCH_PORT_MODE_PORT_ENA);
}
+static void serdes1g_write(void __iomem *base, u32 addr)
+{
+ u32 data;
+
+ writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
+ HSIO_MCB_SERDES1G_CFG_ADDR(addr),
+ base + HSIO_MCB_SERDES1G_CFG);
+
+ do {
+ data = readl(base + HSIO_MCB_SERDES1G_CFG);
+ } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
+}
+
+static void serdes1g_setup(void __iomem *base, uint32_t addr,
+ phy_interface_t interface)
+{
+ writel(0x34, base + HSIO_HW_CFGSTAT_HW_CFG);
+
+ writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
+ writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
+ writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
+ HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
+ HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
+ HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
+ HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
+ base + HSIO_ANA_SERDES1G_IB_CFG);
+ writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
+ HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
+ HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
+ HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
+ base + HSIO_ANA_SERDES1G_DES_CFG);
+ writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
+ HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
+ HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
+ HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
+ HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
+ base + HSIO_ANA_SERDES1G_OB_CFG);
+ writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
+ HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
+ base + HSIO_ANA_SERDES1G_COMMON_CFG);
+ writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
+ HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
+ HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
+ base + HSIO_ANA_SERDES1G_PLL_CFG);
+ writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
+ base + HSIO_DIG_SERDES1G_MISC_CFG);
+
+ serdes1g_write(base, addr);
+
+ writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
+ HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
+ HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
+ base + HSIO_ANA_SERDES1G_COMMON_CFG);
+ serdes1g_write(base, addr);
+
+ writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
+ serdes1g_write(base, addr);
+}
+
+static void serdes_setup(struct ocelot_private *priv)
+{
+ size_t mask;
+ int i = 0;
+
+ for (i = 0; i < MAX_PORT; ++i) {
+ if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff)
+ continue;
+
+ mask = BIT(priv->ports[i].serdes_index);
+ serdes1g_setup(priv->regs[HSIO], mask,
+ priv->ports[i].phy_mode);
+ }
+}
+
static int ocelot_switch_init(struct ocelot_private *priv)
{
/* Reset switch & memories */
setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
SYS_SYSTEM_RST_CORE_ENA);
+ serdes_setup(priv);
return 0;
}
* Put fron ports in "port isolation modes" - i.e. they cant send
* to other ports - via the PGID sorce masks.
*/
- for (i = 0; i <= MAX_PORT; i++)
+ for (i = 0; i < MAX_PORT; i++)
writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
/* Flush queues */
writel(SYS_FRM_AGING_ENA | (20000000 / 65),
priv->regs[SYS] + SYS_FRM_AGING);
- for (i = PORT0; i <= PORT3; i++)
+ for (i = 0; i < MAX_PORT; i++)
ocelot_port_init(priv, i);
ocelot_cpu_capture_setup(priv);
return byte_cnt;
}
+static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
+{
+ int i = 0;
+
+ for (i = 0; i < OCELOT_MIIM_BUS_COUNT; ++i)
+ if (miim[i].miim_base == base && miim[i].miim_size == size)
+ return miim[i].bus;
+
+ return NULL;
+}
+
+static void add_port_entry(struct ocelot_private *priv, size_t index,
+ size_t phy_addr, struct mii_dev *bus,
+ u8 serdes_index, u8 phy_mode)
+{
+ priv->ports[index].phy_addr = phy_addr;
+ priv->ports[index].bus = bus;
+ priv->ports[index].serdes_index = serdes_index;
+ priv->ports[index].phy_mode = phy_mode;
+}
+
+static int external_bus(struct ocelot_private *priv, size_t port_index)
+{
+ return priv->ports[port_index].serdes_index != 0xff;
+}
+
static int ocelot_probe(struct udevice *dev)
{
struct ocelot_private *priv = dev_get_priv(dev);
- int ret, i;
+ int i, ret;
+ struct resource res;
+ fdt32_t faddr;
+ phys_addr_t addr_base;
+ unsigned long addr_size;
+ ofnode eth_node, node, mdio_node;
+ size_t phy_addr;
+ struct mii_dev *bus;
+ struct ofnode_phandle_args phandle;
+ struct phy_device *phy;
+
+ if (!priv)
+ return -EINVAL;
- struct {
- enum ocelot_target id;
- char *name;
- } reg[] = {
- { SYS, "sys" },
- { REW, "rew" },
- { QSYS, "qsys" },
- { ANA, "ana" },
- { QS, "qs" },
- { HSIO, "hsio" },
- { PORT0, "port0" },
- { PORT1, "port1" },
- { PORT2, "port2" },
- { PORT3, "port3" },
- };
-
- for (i = 0; i < ARRAY_SIZE(reg); i++) {
- priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
- if (!priv->regs[reg[i].id]) {
- pr_err
- ("Error %d: can't get regs base addresses for %s\n",
- ret, reg[i].name);
+ for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
+ priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
+ if (!priv->regs[i]) {
+ debug
+ ("Error can't get regs base addresses for %s\n",
+ regs_names[i]);
return -ENOMEM;
}
}
- priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);
+ /* Initialize miim buses */
+ memset(&miim, 0x0, sizeof(struct mscc_miim_dev) *
+ OCELOT_MIIM_BUS_COUNT);
+
+ /* iterate all the ports and find out on which bus they are */
+ i = 0;
+ eth_node = dev_read_first_subnode(dev);
+ for (node = ofnode_first_subnode(eth_node); ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ if (ofnode_read_resource(node, 0, &res))
+ return -ENOMEM;
+ i = res.start;
+
+ ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
+ &phandle);
+
+ /* Get phy address on mdio bus */
+ if (ofnode_read_resource(phandle.node, 0, &res))
+ return -ENOMEM;
+ phy_addr = res.start;
+
+ /* Get mdio node */
+ mdio_node = ofnode_get_parent(phandle.node);
+
+ if (ofnode_read_resource(mdio_node, 0, &res))
+ return -ENOMEM;
+ faddr = cpu_to_fdt32(res.start);
+
+ addr_base = ofnode_translate_address(mdio_node, &faddr);
+ addr_size = res.end - res.start;
+
+ /* If the bus is new then create a new bus */
+ if (!get_mdiobus(addr_base, addr_size))
+ priv->bus[miim_count] =
+ ocelot_mdiobus_init(addr_base, addr_size);
+
+ /* Connect mdio bus with the port */
+ bus = get_mdiobus(addr_base, addr_size);
+
+ /* Get serdes info */
+ ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
+ 3, 0, &phandle);
+ if (ret)
+ add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff);
+ else
+ add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
+ phandle.args[2]);
+ }
+
mscc_phy_reset();
- for (i = 0; i < 4; i++) {
- phy_connect(priv->bus[INTERNAL], i, dev,
- PHY_INTERFACE_MODE_NONE);
+ for (i = 0; i < MAX_PORT; i++) {
+ if (!priv->ports[i].bus)
+ continue;
+
+ phy = phy_connect(priv->ports[i].bus,
+ priv->ports[i].phy_addr, dev,
+ PHY_INTERFACE_MODE_NONE);
+ if (phy && external_bus(priv, i))
+ board_phy_config(phy);
}
return 0;
struct ocelot_private *priv = dev_get_priv(dev);
int i;
- for (i = 0; i < NUM_PHY; i++) {
+ for (i = 0; i < OCELOT_MIIM_BUS_COUNT; i++) {
mdio_unregister(priv->bus[i]);
mdio_free(priv->bus[i]);
}
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <dm/of_addr.h>
+#include <fdt_support.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <miiphy.h>
+#include <net.h>
+#include <wait_bit.h>
+
+#include "mscc_xfer.h"
+#include "mscc_mac_table.h"
+
+#define GCB_MIIM_MII_STATUS 0x0
+#define GCB_MIIM_STAT_BUSY BIT(3)
+#define GCB_MIIM_MII_CMD 0x8
+#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1)
+#define GCB_MIIM_MII_CMD_OPR_READ BIT(2)
+#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4)
+#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20)
+#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25)
+#define GCB_MIIM_MII_CMD_VLD BIT(31)
+#define GCB_MIIM_DATA 0xC
+#define GCB_MIIM_DATA_ERROR (0x2 << 16)
+
+#define ANA_PORT_VLAN_CFG(x) (0xc000 + 0x100 * (x))
+#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
+#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
+#define ANA_PORT_PORT_CFG(x) (0xc070 + 0x100 * (x))
+#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
+#define ANA_PGID(x) (0x9c00 + 4 * (x))
+
+#define HSIO_ANA_SERDES1G_DES_CFG 0x3c
+#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1)
+#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5)
+#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8)
+#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13)
+#define HSIO_ANA_SERDES1G_IB_CFG 0x40
+#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x)
+#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6)
+#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9)
+#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11)
+#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13)
+#define HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19)
+#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24)
+#define HSIO_ANA_SERDES1G_OB_CFG 0x44
+#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x)
+#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4)
+#define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10)
+#define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13)
+#define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17)
+#define HSIO_ANA_SERDES1G_SER_CFG 0x48
+#define HSIO_ANA_SERDES1G_COMMON_CFG 0x4c
+#define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0)
+#define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18)
+#define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31)
+#define HSIO_ANA_SERDES1G_PLL_CFG 0x50
+#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7)
+#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
+#define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21)
+#define HSIO_DIG_SERDES1G_DFT_CFG0 0x58
+#define HSIO_DIG_SERDES1G_MISC_CFG 0x6c
+#define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0)
+#define HSIO_MCB_SERDES1G_CFG 0x74
+#define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31)
+#define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x)
+
+#define SYS_FRM_AGING 0x584
+#define SYS_FRM_AGING_ENA BIT(20)
+#define SYS_SYSTEM_RST_CFG 0x518
+#define SYS_SYSTEM_RST_MEM_INIT BIT(5)
+#define SYS_SYSTEM_RST_MEM_ENA BIT(6)
+#define SYS_SYSTEM_RST_CORE_ENA BIT(7)
+#define SYS_PORT_MODE(x) (0x524 + 0x4 * (x))
+#define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 4)
+#define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 2)
+#define SYS_PAUSE_CFG(x) (0x65c + 0x4 * (x))
+#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
+
+#define QSYS_SWITCH_PORT_MODE(x) (0x15a34 + 0x4 * (x))
+#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(13)
+#define QSYS_EGR_NO_SHARING 0x15a9c
+#define QSYS_QMAP 0x15adc
+
+/* Port registers */
+#define DEV_CLOCK_CFG 0x0
+#define DEV_CLOCK_CFG_LINK_SPEED_1000 1
+#define DEV_MAC_ENA_CFG 0x10
+#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
+#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
+#define DEV_MAC_IFG_CFG 0x24
+#define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8)
+#define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4)
+#define DEV_MAC_IFG_CFG_RX_IFG1(x) (x)
+#define PCS1G_CFG 0x3c
+#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
+#define PCS1G_MODE_CFG 0x40
+#define PCS1G_SD_CFG 0x44
+#define PCS1G_ANEG_CFG 0x48
+#define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16)
+
+#define QS_XTR_GRP_CFG(x) (4 * (x))
+#define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
+#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
+#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
+#define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
+#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
+
+#define IFH_INJ_BYPASS BIT(31)
+#define IFH_TAG_TYPE_C 0
+#define MAC_VID 1
+#define CPU_PORT 11
+#define INTERNAL_PORT_MSK 0xFF
+#define IFH_LEN 4
+#define ETH_ALEN 6
+#define PGID_BROADCAST 13
+#define PGID_UNICAST 14
+
+static const char *const regs_names[] = {
+ "port0", "port1", "port2", "port3", "port4", "port5", "port6",
+ "port7", "port8", "port9", "port10",
+ "ana", "qs", "qsys", "rew", "sys", "hsio",
+};
+
+#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
+#define MAX_PORT 11
+
+enum serval_ctrl_regs {
+ ANA = MAX_PORT,
+ QS,
+ QSYS,
+ REW,
+ SYS,
+ HSIO,
+};
+
+#define SERVAL_MIIM_BUS_COUNT 2
+
+struct serval_phy_port_t {
+ size_t phy_addr;
+ struct mii_dev *bus;
+ u8 serdes_index;
+ u8 phy_mode;
+};
+
+struct serval_private {
+ void __iomem *regs[REGS_NAMES_COUNT];
+ struct mii_dev *bus[SERVAL_MIIM_BUS_COUNT];
+ struct serval_phy_port_t ports[MAX_PORT];
+};
+
+struct mscc_miim_dev {
+ void __iomem *regs;
+ phys_addr_t miim_base;
+ unsigned long miim_size;
+ struct mii_dev *bus;
+};
+
+static const unsigned long serval_regs_qs[] = {
+ [MSCC_QS_XTR_RD] = 0x8,
+ [MSCC_QS_XTR_FLUSH] = 0x18,
+ [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
+ [MSCC_QS_INJ_WR] = 0x2c,
+ [MSCC_QS_INJ_CTRL] = 0x34,
+};
+
+static const unsigned long serval_regs_ana_table[] = {
+ [MSCC_ANA_TABLES_MACHDATA] = 0x9b34,
+ [MSCC_ANA_TABLES_MACLDATA] = 0x9b38,
+ [MSCC_ANA_TABLES_MACACCESS] = 0x9b3c,
+};
+
+static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT];
+static int miim_count = -1;
+
+static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+{
+ return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS,
+ GCB_MIIM_STAT_BUSY, false, 250, false);
+}
+
+static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ u32 val;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
+ GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ,
+ miim->regs + GCB_MIIM_MII_CMD);
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ val = readl(miim->regs + GCB_MIIM_DATA);
+ if (val & GCB_MIIM_DATA_ERROR) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = val & 0xFFFF;
+ out:
+ return ret;
+}
+
+static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret < 0)
+ goto out;
+
+ writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) |
+ GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) |
+ GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD);
+ out:
+ return ret;
+}
+
+static struct mii_dev *serval_mdiobus_init(phys_addr_t miim_base,
+ unsigned long miim_size)
+{
+ struct mii_dev *bus;
+
+ bus = mdio_alloc();
+ if (!bus)
+ return NULL;
+
+ ++miim_count;
+ sprintf(bus->name, "miim-bus%d", miim_count);
+
+ miim[miim_count].regs = ioremap(miim_base, miim_size);
+ miim[miim_count].miim_base = miim_base;
+ miim[miim_count].miim_size = miim_size;
+ bus->priv = &miim[miim_count];
+ bus->read = mscc_miim_read;
+ bus->write = mscc_miim_write;
+
+ if (mdio_register(bus))
+ return NULL;
+
+ miim[miim_count].bus = bus;
+ return bus;
+}
+
+static void serval_cpu_capture_setup(struct serval_private *priv)
+{
+ int i;
+
+ /* map the 8 CPU extraction queues to CPU port 11 */
+ writel(0, priv->regs[QSYS] + QSYS_QMAP);
+
+ for (i = 0; i <= 1; i++) {
+ /*
+ * Do byte-swap and expect status after last data word
+ * Extraction: Mode: manual extraction) | Byte_swap
+ */
+ writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
+ priv->regs[QS] + QS_XTR_GRP_CFG(i));
+ /*
+ * Injection: Mode: manual extraction | Byte_swap
+ */
+ writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
+ priv->regs[QS] + QS_INJ_GRP_CFG(i));
+ }
+
+ for (i = 0; i <= 1; i++)
+ /* Enable IFH insertion/parsing on CPU ports */
+ writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
+ SYS_PORT_MODE_INCL_XTR_HDR(1),
+ priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
+ /*
+ * Setup the CPU port as VLAN aware to support switching frames
+ * based on tags
+ */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
+
+ /* Disable learning (only RECV_ENA must be set) */
+ writel(ANA_PORT_PORT_CFG_RECV_ENA,
+ priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
+
+ /* Enable switching to/from cpu port */
+ setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
+ QSYS_SWITCH_PORT_MODE_PORT_ENA);
+
+ /* No pause on CPU port - not needed (off by default) */
+ clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
+ SYS_PAUSE_CFG_PAUSE_ENA);
+
+ setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
+}
+
+static void serval_port_init(struct serval_private *priv, int port)
+{
+ void __iomem *regs = priv->regs[port];
+
+ /* Enable PCS */
+ writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
+
+ /* Disable Signal Detect */
+ writel(0, regs + PCS1G_SD_CFG);
+
+ /* Enable MAC RX and TX */
+ writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
+ regs + DEV_MAC_ENA_CFG);
+
+ /* Clear sgmii_mode_ena */
+ writel(0, regs + PCS1G_MODE_CFG);
+
+ /*
+ * Clear sw_resolve_ena(bit 0) and set adv_ability to
+ * something meaningful just in case
+ */
+ writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
+
+ /* Set MAC IFG Gaps */
+ writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
+ DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
+
+ /* Set link speed and release all resets */
+ writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
+
+ /* Make VLAN aware for CPU traffic */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
+
+ /* Enable the port in the core */
+ setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
+ QSYS_SWITCH_PORT_MODE_PORT_ENA);
+}
+
+static void serdes_write(void __iomem *base, u32 addr)
+{
+ u32 data;
+
+ writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
+ HSIO_MCB_SERDES1G_CFG_ADDR(addr),
+ base + HSIO_MCB_SERDES1G_CFG);
+
+ do {
+ data = readl(base + HSIO_MCB_SERDES1G_CFG);
+ } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
+
+ mdelay(100);
+}
+
+static void serdes1g_setup(void __iomem *base, uint32_t addr,
+ phy_interface_t interface)
+{
+ writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
+ writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
+ writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
+ HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
+ HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
+ HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
+ HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
+ base + HSIO_ANA_SERDES1G_IB_CFG);
+ writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
+ HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
+ HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
+ HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
+ base + HSIO_ANA_SERDES1G_DES_CFG);
+ writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
+ HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
+ HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
+ HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
+ HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
+ base + HSIO_ANA_SERDES1G_OB_CFG);
+ writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
+ HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
+ base + HSIO_ANA_SERDES1G_COMMON_CFG);
+ writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
+ HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
+ HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
+ base + HSIO_ANA_SERDES1G_PLL_CFG);
+ writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
+ base + HSIO_DIG_SERDES1G_MISC_CFG);
+ serdes_write(base, addr);
+
+ writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
+ HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
+ HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
+ base + HSIO_ANA_SERDES1G_COMMON_CFG);
+ serdes_write(base, addr);
+
+ writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
+ serdes_write(base, addr);
+}
+
+static void serdes_setup(struct serval_private *priv)
+{
+ size_t mask;
+ int i = 0;
+
+ for (i = 0; i < MAX_PORT; ++i) {
+ if (!priv->ports[i].bus)
+ continue;
+
+ mask = BIT(priv->ports[i].serdes_index);
+ serdes1g_setup(priv->regs[HSIO], mask,
+ priv->ports[i].phy_mode);
+ }
+}
+
+static int serval_switch_init(struct serval_private *priv)
+{
+ /* Reset switch & memories */
+ writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
+ priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
+
+ if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
+ SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
+ pr_err("Timeout in memory reset\n");
+ return -EIO;
+ }
+
+ /* Enable switch core */
+ setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
+ SYS_SYSTEM_RST_CORE_ENA);
+
+ serdes_setup(priv);
+
+ return 0;
+}
+
+static int serval_initialize(struct serval_private *priv)
+{
+ int ret, i;
+
+ /* Initialize switch memories, enable core */
+ ret = serval_switch_init(priv);
+ if (ret)
+ return ret;
+
+ /* Flush queues */
+ mscc_flush(priv->regs[QS], serval_regs_qs);
+
+ /* Setup frame ageing - "2 sec" - The unit is 6.5us on serval */
+ writel(SYS_FRM_AGING_ENA | (20000000 / 65),
+ priv->regs[SYS] + SYS_FRM_AGING);
+
+ for (i = 0; i < MAX_PORT; i++)
+ serval_port_init(priv, i);
+
+ serval_cpu_capture_setup(priv);
+
+ debug("Ports enabled\n");
+
+ return 0;
+}
+
+static int serval_write_hwaddr(struct udevice *dev)
+{
+ struct serval_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
+ pdata->enetaddr, PGID_UNICAST);
+
+ writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
+
+ return 0;
+}
+
+static int serval_start(struct udevice *dev)
+{
+ struct serval_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff };
+ int ret;
+
+ ret = serval_initialize(priv);
+ if (ret)
+ return ret;
+
+ /* Set MAC address tables entries for CPU redirection */
+ mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, mac,
+ PGID_BROADCAST);
+
+ writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
+ priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
+
+ /* It should be setup latter in serval_write_hwaddr */
+ mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
+ pdata->enetaddr, PGID_UNICAST);
+
+ writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
+ return 0;
+}
+
+static void serval_stop(struct udevice *dev)
+{
+ writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+}
+
+static int serval_send(struct udevice *dev, void *packet, int length)
+{
+ struct serval_private *priv = dev_get_priv(dev);
+ u32 ifh[IFH_LEN];
+ u32 *buf = packet;
+
+ /*
+ * Generate the IFH for frame injection
+ *
+ * The IFH is a 128bit-value
+ * bit 127: bypass the analyzer processing
+ * bit 57-67: destination mask
+ * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
+ * bit 20-27: cpu extraction queue mask
+ * bit 16: tag type 0: C-tag, 1: S-tag
+ * bit 0-11: VID
+ */
+ ifh[0] = IFH_INJ_BYPASS;
+ ifh[1] = (0x07);
+ ifh[2] = (0x7f) << 25;
+ ifh[3] = (IFH_TAG_TYPE_C << 16);
+
+ return mscc_send(priv->regs[QS], serval_regs_qs,
+ ifh, IFH_LEN, buf, length);
+}
+
+static int serval_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct serval_private *priv = dev_get_priv(dev);
+ u32 *rxbuf = (u32 *)net_rx_packets[0];
+ int byte_cnt = 0;
+
+ byte_cnt = mscc_recv(priv->regs[QS], serval_regs_qs, rxbuf, IFH_LEN,
+ false);
+
+ *packetp = net_rx_packets[0];
+
+ return byte_cnt;
+}
+
+static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
+{
+ int i = 0;
+
+ for (i = 0; i < SERVAL_MIIM_BUS_COUNT; ++i)
+ if (miim[i].miim_base == base && miim[i].miim_size == size)
+ return miim[i].bus;
+
+ return NULL;
+}
+
+static void add_port_entry(struct serval_private *priv, size_t index,
+ size_t phy_addr, struct mii_dev *bus,
+ u8 serdes_index, u8 phy_mode)
+{
+ priv->ports[index].phy_addr = phy_addr;
+ priv->ports[index].bus = bus;
+ priv->ports[index].serdes_index = serdes_index;
+ priv->ports[index].phy_mode = phy_mode;
+}
+
+static int serval_probe(struct udevice *dev)
+{
+ struct serval_private *priv = dev_get_priv(dev);
+ int i, ret;
+ struct resource res;
+ fdt32_t faddr;
+ phys_addr_t addr_base;
+ unsigned long addr_size;
+ ofnode eth_node, node, mdio_node;
+ size_t phy_addr;
+ struct mii_dev *bus;
+ struct ofnode_phandle_args phandle;
+ struct phy_device *phy;
+
+ if (!priv)
+ return -EINVAL;
+
+ /* Get registers and map them to the private structure */
+ for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
+ priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
+ if (!priv->regs[i]) {
+ debug
+ ("Error can't get regs base addresses for %s\n",
+ regs_names[i]);
+ return -ENOMEM;
+ }
+ }
+
+ /* Initialize miim buses */
+ memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT);
+
+ /* iterate all the ports and find out on which bus they are */
+ i = 0;
+ eth_node = dev_read_first_subnode(dev);
+ for (node = ofnode_first_subnode(eth_node);
+ ofnode_valid(node);
+ node = ofnode_next_subnode(node)) {
+ if (ofnode_read_resource(node, 0, &res))
+ return -ENOMEM;
+ i = res.start;
+
+ ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
+ 0, 0, &phandle);
+ if (ret)
+ continue;
+
+ /* Get phy address on mdio bus */
+ if (ofnode_read_resource(phandle.node, 0, &res))
+ return -ENOMEM;
+ phy_addr = res.start;
+
+ /* Get mdio node */
+ mdio_node = ofnode_get_parent(phandle.node);
+
+ if (ofnode_read_resource(mdio_node, 0, &res))
+ return -ENOMEM;
+ faddr = cpu_to_fdt32(res.start);
+
+ addr_base = ofnode_translate_address(mdio_node, &faddr);
+ addr_size = res.end - res.start;
+
+ /* If the bus is new then create a new bus */
+ if (!get_mdiobus(addr_base, addr_size))
+ priv->bus[miim_count] =
+ serval_mdiobus_init(addr_base, addr_size);
+
+ /* Connect mdio bus with the port */
+ bus = get_mdiobus(addr_base, addr_size);
+
+ /* Get serdes info */
+ ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
+ 3, 0, &phandle);
+ if (ret)
+ return -ENOMEM;
+
+ add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
+ phandle.args[2]);
+ }
+
+ for (i = 0; i < MAX_PORT; i++) {
+ if (!priv->ports[i].bus)
+ continue;
+
+ phy = phy_connect(priv->ports[i].bus,
+ priv->ports[i].phy_addr, dev,
+ PHY_INTERFACE_MODE_NONE);
+ if (phy)
+ board_phy_config(phy);
+ }
+
+ return 0;
+}
+
+static int serval_remove(struct udevice *dev)
+{
+ struct serval_private *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < SERVAL_MIIM_BUS_COUNT; i++) {
+ mdio_unregister(priv->bus[i]);
+ mdio_free(priv->bus[i]);
+ }
+
+ return 0;
+}
+
+static const struct eth_ops serval_ops = {
+ .start = serval_start,
+ .stop = serval_stop,
+ .send = serval_send,
+ .recv = serval_recv,
+ .write_hwaddr = serval_write_hwaddr,
+};
+
+static const struct udevice_id mscc_serval_ids[] = {
+ {.compatible = "mscc,vsc7418-switch"},
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(serval) = {
+ .name = "serval-switch",
+ .id = UCLASS_ETH,
+ .of_match = mscc_serval_ids,
+ .probe = serval_probe,
+ .remove = serval_remove,
+ .ops = &serval_ops,
+ .priv_auto_alloc_size = sizeof(struct serval_private),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
&priv->rst_gpio, GPIOD_IS_OUT);
}
} else {
- subnode = ofnode_find_subnode(dev_ofnode(dev), "phy-handle");
- if (!ofnode_valid(subnode)) {
+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0,
+ 0, &args);
+ if (ret) {
printf("error: phy-handle is not specified\n");
return ret;
}
- priv->phy_addr = ofnode_read_s32_default(subnode, "reg", -1);
+ priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1);
if (priv->phy_addr < 0) {
printf("error: phy address is not specified\n");
return ret;
bool "Micrel Ethernet PHYs support"
help
Enable support for the GbE PHYs manufactured by Micrel (now
- a part of Microchip). This includes drivers for the KSZ804,
- KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, KSZ8721
- either/or KSZ9021 (see the "Micrel KSZ9021 family support"
- config option for details), and KSZ9031 (if configured).
+ a part of Microchip). This includes drivers for the KSZ804, KSZ8031,
+ KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx
+ family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel
+ KSZ90x1 family support" is selected).
if PHY_MICREL
config PHY_MICREL_KSZ9021
bool
- select PHY_GIGE
select PHY_MICREL_KSZ90X1
config PHY_MICREL_KSZ9031
bool
- select PHY_GIGE
select PHY_MICREL_KSZ90X1
config PHY_MICREL_KSZ90X1
delays configured in the device tree will be applied to the
PHY during initialization.
- This should not be enabled at the same time with PHY_MICREL_KSZ8XXX
- as the KSZ9021 and KS8721 share the same ID.
-
config PHY_MICREL_KSZ8XXX
bool "Micrel KSZ8xxx family support"
- default y if !PHY_MICREL_KSZ90X1
help
- Enable support for the 8000 series GbE PHYs manufactured by Micrel
+ Enable support for the 8000 series 10/100 PHYs manufactured by Micrel
(now a part of Microchip). This includes drivers for the KSZ804,
KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
- This should not be enabled at the same time with PHY_MICREL_KSZ90X1
- as the KSZ9021 and KS8721 share the same ID.
-
endif # PHY_MICREL
config PHY_MSCC
If unsure, say N.
+config RTL8211F_PHY_FORCE_EEE_RXC_ON
+ bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
+ depends on PHY_REALTEK
+ default n
+ help
+ The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
+ transitions to/from a lower power consumption level (Low Power Idle
+ mode) based on link utilization. When no packets are being
+ transmitted, the system goes to Low Power Idle mode to save power.
+
+ Under particular circumstances this setting can cause issues where
+ the PHY is unable to transmit or receive any packet when in LPI mode.
+ The problem is caused when the PHY is configured to stop receiving
+ the xMII clock while it is signaling LPI. For some PHYs the bit
+ configuring this behavior is set by the Linux kernel, causing the
+ issue in U-Boot on reboot if the PHY retains the register value.
+
+ Default n, which means that the PHY state is not changed. To work
+ around the issues, change this setting to y.
+
config PHY_SMSC
bool "Microchip(SMSC) Ethernet PHYs support"
AQUANTIA_SYSTEM_INTERFACE_SR);
/* If SI is USXGMII then start USXGMII autoneg */
if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) {
+ reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
+ AQUANTIA_VENDOR_PROVISIONING_REG);
+
+ reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
+
phy_write(phydev, MDIO_MMD_PHYXS,
AQUANTIA_VENDOR_PROVISIONING_REG,
- AQUANTIA_USX_AUTONEG_CONTROL_ENA);
+ reg_val1);
printf("%s: system interface USXGMII\n",
phydev->dev->name);
} else {
.shutdown = &genphy_shutdown,
};
-/* Micrel used the exact same part number for the KSZ9021. */
+/* Micrel used the exact same model number for the KSZ9021,
+ * so the revision number is used to distinguish them.
+ */
static struct phy_driver KS8721_driver = {
.name = "Micrel KS8721BL",
- .uid = 0x221610,
- .mask = 0xfffff0,
+ .uid = 0x221618,
+ .mask = 0xfffffc,
.features = PHY_BASIC_FEATURES,
.config = &genphy_config,
.startup = &genphy_startup,
#define CTRL1000_CONFIG_MASTER (1 << 11)
#define CTRL1000_MANUAL_CONFIG (1 << 12)
+#define KSZ9021_PS_TO_REG 120
+
/* KSZ9031 PHY Registers */
#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
#define MII_KSZ9031_MMD_REG_DATA 0x0e
+#define KSZ9031_PS_TO_REG 60
+
static int ksz90xx_startup(struct phy_device *phydev)
{
unsigned phy_ctl;
};
static int ksz90x1_of_config_group(struct phy_device *phydev,
- struct ksz90x1_ofcfg *ofcfg)
+ struct ksz90x1_ofcfg *ofcfg,
+ int ps_to_regval)
{
struct udevice *dev = phydev->dev;
struct phy_driver *drv = phydev->drv;
- const int ps_to_regval = 60;
int val[4];
int i, changed = 0, offset, max;
u16 regval = 0;
+ ofnode node;
if (!drv || !drv->writeext)
return -EOPNOTSUPP;
+ /* Look for a PHY node under the Ethernet node */
+ node = dev_read_subnode(dev, "ethernet-phy");
+ if (!ofnode_valid(node)) {
+ /* No node found, look in the Ethernet node */
+ node = dev_ofnode(dev);
+ }
+
for (i = 0; i < ofcfg->grpsz; i++) {
- val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
+ val[i] = ofnode_read_u32_default(node, ofcfg->grp[i].name, ~0);
offset = ofcfg->grp[i].off;
if (val[i] == -1) {
/* Default register value for KSZ9021 */
int i, ret = 0;
for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
- ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+ ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
+ KSZ9021_PS_TO_REG);
if (ret)
return ret;
}
int i, ret = 0;
for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
- ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+ ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
+ KSZ9031_PS_TO_REG);
if (ret)
return ret;
}
static struct phy_driver ksz9021_driver = {
.name = "Micrel ksz9021",
.uid = 0x221610,
- .mask = 0xfffff0,
+ .mask = 0xfffffe,
.features = PHY_GBIT_FEATURES,
.config = &ksz9021_config,
.startup = &ksz90xx_startup,
int phy_init(void)
{
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ /*
+ * The pointers inside phy_drivers also needs to be updated incase of
+ * manual reloc, without which these points to some invalid
+ * pre reloc address and leads to invalid accesses, hangs.
+ */
+ struct list_head *head = &phy_drivers;
+
+ head->next = (void *)head->next + gd->reloc_off;
+ head->prev = (void *)head->prev + gd->reloc_off;
+#endif
+
#ifdef CONFIG_B53_SWITCH
phy_b53_init();
#endif
drv->readext += gd->reloc_off;
if (drv->writeext)
drv->writeext += gd->reloc_off;
+ if (drv->read_mmd)
+ drv->read_mmd += gd->reloc_off;
+ if (drv->write_mmd)
+ drv->write_mmd += gd->reloc_off;
#endif
return 0;
}
dev->drv = get_phy_driver(dev, interface);
- phy_probe(dev);
+ if (phy_probe(dev)) {
+ printf("%s, PHY probe failed\n", __func__);
+ return NULL;
+ }
if (addr >= 0 && addr < PHY_MAX_ADDR)
bus->phymap[addr] = dev;
#define PHY_RTL8211x_FORCE_MASTER BIT(1)
#define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
+#define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
return 0;
}
+static int rtl8211f_probe(struct phy_device *phydev)
+{
+#ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON
+ phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON;
+#endif
+
+ return 0;
+}
+
/* RealTek RTL8211x */
static int rtl8211x_config(struct phy_device *phydev)
{
{
u16 reg;
+ if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
+ unsigned int reg;
+
+ reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
+ reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
+ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
+ }
+
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
phy_write(phydev, MDIO_DEVAD_NONE,
.uid = 0x1cc916,
.mask = 0xffffff,
.features = PHY_GBIT_FEATURES,
+ .probe = &rtl8211f_probe,
.config = &rtl8211f_config,
.startup = &rtl8211f_startup,
.shutdown = &genphy_shutdown,
#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
#define MII_DP83867_CFG2_MASK 0x003F
-#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
-#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
-
-/* MMD Access Control register fields */
-#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
-#define MII_MMD_CTRL_ADDR 0x0000 /* Address */
-#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
-#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
-#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
-
/* User setting - can be taken from DTS */
#define DEFAULT_RX_ID_DELAY DP83867_RGMIIDCTL_2_25_NS
#define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS
int clk_output_sel;
};
-/**
- * phy_read_mmd_indirect - reads data from the MMD registers
- * @phydev: The PHY device bus
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- *
- * Description: it reads data from the MMD registers (clause 22 to access to
- * clause 45) of the specified phy address.
- * To read these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Read reg 14 // Read MMD data
- */
-int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr)
-{
- int value = -1;
-
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Read the content of the MMD's selected register */
- value = phy_read(phydev, addr, MII_MMD_DATA);
- return value;
-}
-
-/**
- * phy_write_mmd_indirect - writes data to the MMD registers
- * @phydev: The PHY device
- * @prtad: MMD Address
- * @devad: MMD DEVAD
- * @addr: PHY address on the MII bus
- * @data: data to write in the MMD register
- *
- * Description: Write data from the MMD registers of the specified
- * phy address.
- * To write these registers we have:
- * 1) Write reg 13 // DEVAD
- * 2) Write reg 14 // MMD Address
- * 3) Write reg 13 // MMD Data Command for MMD DEVAD
- * 3) Write reg 14 // Write MMD data
- */
-void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
- int devad, int addr, u32 data)
-{
- /* Write the desired MMD Devad */
- phy_write(phydev, addr, MII_MMD_CTRL, devad);
-
- /* Write the desired MMD register address */
- phy_write(phydev, addr, MII_MMD_DATA, prtad);
-
- /* Select the Function : DATA with no post increment */
- phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
-
- /* Write the data into MMD's selected register */
- phy_write(phydev, addr, MII_MMD_DATA, data);
-}
-
static int dp83867_config_port_mirroring(struct phy_device *phydev)
{
struct dp83867_private *dp83867 =
(struct dp83867_private *)phydev->priv;
u16 val;
- val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
val |= DP83867_CFG4_PORT_MIRROR_EN;
else
val &= ~DP83867_CFG4_PORT_MIRROR_EN;
- phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
- phydev->addr, val);
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
return 0;
}
/* Optional configuration */
+ node = phy_get_ofnode(phydev);
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
/*
* Keep the default value if ti,clk-output-sel is not set
* or to high
ofnode_read_u32_default(node, "ti,clk-output-sel",
DP83867_CLK_O_SEL_REF_CLK);
- node = phy_get_ofnode(phydev);
- if (!ofnode_valid(node))
- return -EINVAL;
-
if (ofnode_read_bool(node, "ti,max-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
else if (ofnode_read_bool(node, "ti,min-output-impedance"))
/* Clock output selection if muxing property is set */
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
- val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
- DP83867_DEVADDR, phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
val |= (dp83867->clk_output_sel <<
DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
- phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
- DP83867_DEVADDR, phydev->addr, val);
+ phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG, val);
}
return 0;
/* Mode 1 or 2 workaround */
if (dp83867->rxctrl_strap_quirk) {
- val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
- DP83867_DEVADDR, phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR,
+ DP83867_CFG4);
val &= ~BIT(7);
- phy_write_mmd_indirect(phydev, DP83867_CFG4,
- DP83867_DEVADDR, phydev->addr, val);
+ phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_CFG4, val);
}
if (phy_interface_is_rgmii(phydev)) {
* register's bit 11 (marked as RESERVED).
*/
- bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1,
- DP83867_DEVADDR, phydev->addr);
+ bs = phy_read_mmd(phydev, DP83867_DEVADDR,
+ DP83867_STRAP_STS1);
val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
if (bs & DP83867_STRAP_STS1_RESERVED) {
val &= ~DP83867_PHYCR_RESERVED_MASK;
MII_DP83867_CFG2_SPEEDOPT_INTLOW);
phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
- phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
- DP83867_DEVADDR, phydev->addr, 0x0);
+ phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_RGMIICTL, 0x0);
phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
DP83867_PHYCTRL_SGMIIEN |
}
if (phy_interface_is_rgmii(phydev)) {
- val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
- DP83867_DEVADDR, phydev->addr);
+ val = phy_read_mmd(phydev, DP83867_DEVADDR,
+ DP83867_RGMIICTL);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
val |= DP83867_RGMII_RX_CLK_DELAY_EN;
- phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
- DP83867_DEVADDR, phydev->addr, val);
+ phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_RGMIICTL, val);
delay = (dp83867->rx_id_delay |
(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
- phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
- DP83867_DEVADDR, phydev->addr, delay);
+ phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_RGMIIDCTL, delay);
if (dp83867->io_impedance >= 0) {
- val = phy_read_mmd_indirect(phydev,
- DP83867_IO_MUX_CFG,
- DP83867_DEVADDR,
- phydev->addr);
+ val = phy_read_mmd(phydev,
+ DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG);
val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
val |= dp83867->io_impedance &
DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
- phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
- DP83867_DEVADDR, phydev->addr,
- val);
+ phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_IO_MUX_CFG, val);
}
}
#define CSR_OPS 0x0000000F
#define CSR_OPS_CONFIG BIT(1)
+#define APSR_TDM BIT(14)
+
#define TCCR_TSRQ0 BIT(0)
#define RFLR_RFL_MIN 0x05EE
/* FIFO size set */
writel(0x00222210, eth->iobase + RAVB_REG_TGC);
- /* Delay CLK: 2ns */
- if (pdata->max_speed == 1000)
- writel(BIT(14), eth->iobase + RAVB_REG_APSR);
+ /* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
+ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) ||
+ (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
+ return 0;
+
+ if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
+ (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))
+ writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);
return 0;
}
{"RTL-8168/8111g", 0x4c, 0xff7e1880,},
{"RTL-8101e", 0x34, 0xff7e1880,},
{"RTL-8100e", 0x32, 0xff7e1880,},
+ {"RTL-8168h/8111h", 0x54, 0xff7e1880,},
};
enum _DescStatusBit {
*/
#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
- !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning cache-line size is larger than descriptor size
#endif
#endif
}
#endif
+#ifdef CONFIG_DM_ETH
+static int rtl8169_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ unsigned int i;
+
+ RTL_W8(Cfg9346, Cfg9346_Unlock);
+
+ for (i = 0; i < MAC_ADDR_LEN; i++)
+ RTL_W8(MAC0 + i, plat->enetaddr[i]);
+
+ RTL_W8(Cfg9346, Cfg9346_Lock);
+
+ return 0;
+}
+#endif
+
/**************************************************************************
INIT - Look for an adapter, this routine's visible to the outside
***************************************************************************/
.send = rtl8169_eth_send,
.recv = rtl8169_eth_recv,
.stop = rtl8169_eth_stop,
+ .write_hwaddr = rtl8169_write_hwaddr,
};
static const struct udevice_id rtl8169_eth_ids[] = {
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
-#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
flush_dcache_range((u32)addr, \
(u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(port_info, 1, RTRATE);
-#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
priv->iobase = pdata->iobase;
+#if CONFIG_IS_ENABLED(CLK)
ret = clk_get_by_index(udev, 0, &priv->clk);
if (ret < 0)
return ret;
+#endif
ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
if (!ret) {
eth->port_info[eth->port].iobase =
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
+#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&priv->clk);
if (ret)
goto err_mdio_register;
+#endif
ret = sh_eth_phy_config(udev);
if (ret) {
return 0;
err_phy_config:
+#if CONFIG_IS_ENABLED(CLK)
clk_disable(&priv->clk);
+#endif
err_mdio_register:
mdio_free(mdiodev);
return ret;
struct sh_eth_dev *eth = &priv->shdev;
struct sh_eth_info *port_info = ð->port_info[eth->port];
+#if CONFIG_IS_ENABLED(CLK)
clk_disable(&priv->clk);
+#endif
free(port_info->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
}
static const struct udevice_id sh_ether_ids[] = {
+ { .compatible = "renesas,ether-r7s72100" },
{ .compatible = "renesas,ether-r8a7790" },
{ .compatible = "renesas,ether-r8a7791" },
{ .compatible = "renesas,ether-r8a7793" },
[RMII_MII] = 0x0790,
};
+static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
+ [EDSR] = 0x0000,
+ [EDMR] = 0x0400,
+ [EDTRR] = 0x0408,
+ [EDRRR] = 0x0410,
+ [EESR] = 0x0428,
+ [EESIPR] = 0x0430,
+ [TDLAR] = 0x0010,
+ [TDFAR] = 0x0014,
+ [TDFXR] = 0x0018,
+ [TDFFR] = 0x001c,
+ [RDLAR] = 0x0030,
+ [RDFAR] = 0x0034,
+ [RDFXR] = 0x0038,
+ [RDFFR] = 0x003c,
+ [TRSCER] = 0x0438,
+ [RMFCR] = 0x0440,
+ [TFTR] = 0x0448,
+ [FDR] = 0x0450,
+ [RMCR] = 0x0458,
+ [RPADIR] = 0x0460,
+ [FCFTR] = 0x0468,
+ [CSMR] = 0x04E4,
+
+ [ECMR] = 0x0500,
+ [ECSR] = 0x0510,
+ [ECSIPR] = 0x0518,
+ [PIR] = 0x0520,
+ [PSR] = 0x0528,
+ [PIPR] = 0x052c,
+ [RFLR] = 0x0508,
+ [APR] = 0x0554,
+ [MPR] = 0x0558,
+ [PFTCR] = 0x055c,
+ [PFRCR] = 0x0560,
+ [TPAUSER] = 0x0564,
+ [GECMR] = 0x05b0,
+ [BCULR] = 0x05b4,
+ [MAHR] = 0x05c0,
+ [MALR] = 0x05c8,
+ [TROCR] = 0x0700,
+ [CDCR] = 0x0708,
+ [LCCR] = 0x0710,
+ [CEFCR] = 0x0740,
+ [FRECR] = 0x0748,
+ [TSFRCR] = 0x0750,
+ [TLFRCR] = 0x0758,
+ [RFCR] = 0x0760,
+ [CERCR] = 0x0768,
+ [CEECR] = 0x0770,
+ [MAFCR] = 0x0778,
+ [RMII_MII] = 0x0790,
+};
+
static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[ECMR] = 0x0100,
[RFLR] = 0x0108,
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xfef00000
#endif
-#elif defined(CONFIG_CPU_SH7724)
-#define SH_ETH_TYPE_ETHER
-#define BASE_IO_ADDR 0xA4600000
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000
const u16 *reg_offset = sh_eth_offset_gigabit;
#elif defined(SH_ETH_TYPE_ETHER)
const u16 *reg_offset = sh_eth_offset_fast_sh4;
+#elif defined(SH_ETH_TYPE_RZ)
+ const u16 *reg_offset = sh_eth_offset_rz;
#else
#error
#endif
struct phy_device *phydev;
struct mii_dev *bus;
struct clk tx_clk;
+ struct clk ephy_clk;
struct reset_ctl tx_rst;
+ struct reset_ctl ephy_rst;
#ifdef CONFIG_DM_GPIO
struct gpio_desc reset_gpio;
#endif
static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int ret;
ret = clk_enable(&priv->tx_clk);
}
}
- if (priv->variant == H3_EMAC) {
- /* Only H3/H5 have clock controls for internal EPHY */
- if (priv->use_internal_phy) {
- /* Set clock gating for ephy */
- setbits_le32(&ccm->bus_gate4,
- BIT(AHB_GATE_OFFSET_EPHY));
-
- /* Deassert EPHY */
- setbits_le32(&ccm->ahb_reset2_cfg,
- BIT(AHB_RESET_OFFSET_EPHY));
+ /* Only H3/H5 have clock controls for internal EPHY */
+ if (clk_valid(&priv->ephy_clk)) {
+ ret = clk_enable(&priv->ephy_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable EPHY TX clock\n");
+ return ret;
+ }
+ }
+
+ if (reset_valid(&priv->ephy_rst)) {
+ ret = reset_deassert(&priv->ephy_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert EPHY TX clock\n");
+ return ret;
}
}
.stop = sun8i_emac_eth_stop,
};
+static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
+{
+ int node, ret;
+
+ /* look for mdio-mux node for internal PHY node */
+ node = fdt_path_offset(gd->fdt_blob,
+ "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
+ if (node < 0) {
+ debug("failed to get mdio-mux with internal PHY\n");
+ return node;
+ }
+
+ ret = fdt_node_check_compatible(gd->fdt_blob, node,
+ "allwinner,sun8i-h3-mdio-internal");
+ if (ret < 0) {
+ debug("failed to find mdio-internal node\n");
+ return ret;
+ }
+
+ ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0,
+ &priv->ephy_clk);
+ if (ret) {
+ dev_err(dev, "failed to get EPHY TX clock\n");
+ return ret;
+ }
+
+ ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0,
+ &priv->ephy_rst);
+ if (ret) {
+ dev_err(dev, "failed to get EPHY TX reset\n");
+ return ret;
+ }
+
+ priv->use_internal_phy = true;
+
+ return 0;
+}
+
static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
{
struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
}
if (priv->variant == H3_EMAC) {
- int parent = fdt_parent_offset(gd->fdt_blob, offset);
-
- if (parent >= 0 &&
- !fdt_node_check_compatible(gd->fdt_blob, parent,
- "allwinner,sun8i-h3-mdio-internal"))
- priv->use_internal_phy = true;
+ ret = sun8i_get_ephy_nodes(priv);
+ if (ret)
+ return ret;
}
priv->interface = pdata->phy_interface;
phy_id |= tmp & 0x0000ffff;
- switch (phy_id) {
-#ifdef PHY_KSZ8873
- case PHY_KSZ8873:
- sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = ksz8873_init_phy;
- phy[i].is_phy_connected = ksz8873_is_phy_connected;
- phy[i].get_link_speed = ksz8873_get_link_speed;
- phy[i].auto_negotiate = ksz8873_auto_negotiate;
- break;
-#endif
-#ifdef PHY_LXT972
- case PHY_LXT972:
- sprintf(phy[i].name, "LXT972 @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = lxt972_init_phy;
- phy[i].is_phy_connected = lxt972_is_phy_connected;
- phy[i].get_link_speed = lxt972_get_link_speed;
- phy[i].auto_negotiate = lxt972_auto_negotiate;
- break;
-#endif
-#ifdef PHY_DP83848
- case PHY_DP83848:
- sprintf(phy[i].name, "DP83848 @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = dp83848_init_phy;
- phy[i].is_phy_connected = dp83848_is_phy_connected;
- phy[i].get_link_speed = dp83848_get_link_speed;
- phy[i].auto_negotiate = dp83848_auto_negotiate;
- break;
-#endif
-#ifdef PHY_ET1011C
- case PHY_ET1011C:
- sprintf(phy[i].name, "ET1011C @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = gen_init_phy;
- phy[i].is_phy_connected = gen_is_phy_connected;
- phy[i].get_link_speed = et1011c_get_link_speed;
- phy[i].auto_negotiate = gen_auto_negotiate;
- break;
-#endif
- default:
- sprintf(phy[i].name, "GENERIC @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = gen_init_phy;
- phy[i].is_phy_connected = gen_is_phy_connected;
- phy[i].get_link_speed = gen_get_link_speed;
- phy[i].auto_negotiate = gen_auto_negotiate;
- }
+ sprintf(phy[i].name, "GENERIC @ 0x%02x",
+ active_phy_addr[i]);
+ phy[i].init = gen_init_phy;
+ phy[i].is_phy_connected = gen_is_phy_connected;
+ phy[i].get_link_speed = gen_get_link_speed;
+ phy[i].auto_negotiate = gen_auto_negotiate;
debug("Ethernet PHY: %s\n", phy[i].name);
int ret;
int shift = NVME_CAP_MPSMIN(dev->cap) + 12;
- ret = nvme_identify(dev, 0, 1, (dma_addr_t)ctrl);
+ ret = nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl);
if (ret)
return -EIO;
ns->dev = ndev;
/* extract the namespace id from the block device name */
ns->ns_id = trailing_strtol(udev->name) + 1;
- if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)id))
+ if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id))
return -EIO;
flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK;
ALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl));
struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl;
- if (nvme_identify(dev, 0, 1, (dma_addr_t)ctrl))
+ if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl))
return -EIO;
print_optional_admin_cmd(le16_to_cpu(ctrl->oacs), ns->devnum);
print_optional_nvm_cmd(le16_to_cpu(ctrl->oncs), ns->devnum);
print_format_nvme_attributes(ctrl->fna, ns->devnum);
- if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)id))
+ if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)(long)id))
return -EIO;
print_formats(id, ns);
Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is
also used to access EHCI USB controller on the SoC.
+config PCI_RCAR_GEN3
+ bool "Renesas RCar Gen3 PCIe driver"
+ depends on DM_PCI
+ depends on RCAR_GEN3
+ help
+ Say Y here if you want to enable PCIe controller support on
+ Renesas RCar Gen3 SoCs.
+
config PCI_SANDBOX
bool "Sandbox PCI support"
depends on SANDBOX && DM_PCI
PCIe controllers. The PCIe may works in RC or EP mode according to
RCW[HOST_AGT_PEX] setting.
+config PCIE_LAYERSCAPE_GEN4
+ bool "Layerscape Gen4 PCIe support"
+ depends on DM_PCI
+ help
+ Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or
+ several PCIe controllers. The PCIe controller can work in RC or
+ EP mode according to RCW[HOST_AGT_PEX] setting.
+
config PCIE_INTEL_FPGA
bool "Intel FPGA PCIe support"
depends on DM_PCI
obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o
obj-$(CONFIG_SH4_PCI) += pci_sh4.o
obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
+ pcie_layerscape_gen4_fixup.o
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RCar Gen3 PCIEC driver
+ *
+ * Copyright (C) 2018-2019 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on Linux PCIe driver for Renesas R-Car SoCs
+ * Copyright (C) 2014 Renesas Electronics Europe Ltd
+ *
+ * Based on:
+ * arch/sh/drivers/pci/pcie-sh7786.c
+ * arch/sh/drivers/pci/ops-sh7786.c
+ * Copyright (C) 2009 - 2011 Paul Mundt
+ *
+ * Author: Phil Edworthy <phil.edworthy@renesas.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci.h>
+#include <wait_bit.h>
+
+#define PCIECAR 0x000010
+#define PCIECCTLR 0x000018
+#define CONFIG_SEND_ENABLE BIT(31)
+#define TYPE0 (0 << 8)
+#define TYPE1 BIT(8)
+#define PCIECDR 0x000020
+#define PCIEMSR 0x000028
+#define PCIEINTXR 0x000400
+#define PCIEPHYSR 0x0007f0
+#define PHYRDY BIT(0)
+#define PCIEMSITXR 0x000840
+
+/* Transfer control */
+#define PCIETCTLR 0x02000
+#define CFINIT 1
+#define PCIETSTR 0x02004
+#define DATA_LINK_ACTIVE 1
+#define PCIEERRFR 0x02020
+#define UNSUPPORTED_REQUEST BIT(4)
+#define PCIEMSIFR 0x02044
+#define PCIEMSIALR 0x02048
+#define MSIFE 1
+#define PCIEMSIAUR 0x0204c
+#define PCIEMSIIER 0x02050
+
+/* root port address */
+#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
+
+/* local address reg & mask */
+#define PCIELAR(x) (0x02200 + ((x) * 0x20))
+#define PCIELAMR(x) (0x02208 + ((x) * 0x20))
+#define LAM_PREFETCH BIT(3)
+#define LAM_64BIT BIT(2)
+#define LAR_ENABLE BIT(1)
+
+/* PCIe address reg & mask */
+#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
+#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
+#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
+#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
+#define PAR_ENABLE BIT(31)
+#define IO_SPACE BIT(8)
+
+/* Configuration */
+#define PCICONF(x) (0x010000 + ((x) * 0x4))
+#define PMCAP(x) (0x010040 + ((x) * 0x4))
+#define EXPCAP(x) (0x010070 + ((x) * 0x4))
+#define VCCAP(x) (0x010100 + ((x) * 0x4))
+
+/* link layer */
+#define IDSETR1 0x011004
+#define TLCTLR 0x011048
+#define MACSR 0x011054
+#define SPCHGFIN BIT(4)
+#define SPCHGFAIL BIT(6)
+#define SPCHGSUC BIT(7)
+#define LINK_SPEED (0xf << 16)
+#define LINK_SPEED_2_5GTS (1 << 16)
+#define LINK_SPEED_5_0GTS (2 << 16)
+#define MACCTLR 0x011058
+#define SPEED_CHANGE BIT(24)
+#define SCRAMBLE_DISABLE BIT(27)
+#define MACS2R 0x011078
+#define MACCGSPSETR 0x011084
+#define SPCNGRSN BIT(31)
+
+/* R-Car H1 PHY */
+#define H1_PCIEPHYADRR 0x04000c
+#define WRITE_CMD BIT(16)
+#define PHY_ACK BIT(24)
+#define RATE_POS 12
+#define LANE_POS 8
+#define ADR_POS 0
+#define H1_PCIEPHYDOUTR 0x040014
+
+/* R-Car Gen2 PHY */
+#define GEN2_PCIEPHYADDR 0x780
+#define GEN2_PCIEPHYDATA 0x784
+#define GEN2_PCIEPHYCTRL 0x78c
+
+#define INT_PCI_MSI_NR 32
+
+#define RCONF(x) (PCICONF(0) + (x))
+#define RPMCAP(x) (PMCAP(0) + (x))
+#define REXPCAP(x) (EXPCAP(0) + (x))
+#define RVCCAP(x) (VCCAP(0) + (x))
+
+#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
+#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
+#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
+
+#define RCAR_PCI_MAX_RESOURCES 4
+#define MAX_NR_INBOUND_MAPS 6
+
+#define PCI_EXP_FLAGS 2 /* Capabilities register */
+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
+
+enum {
+ RCAR_PCI_ACCESS_READ,
+ RCAR_PCI_ACCESS_WRITE,
+};
+
+struct rcar_gen3_pcie_priv {
+ fdt_addr_t regs;
+};
+
+static void rcar_rmw32(struct udevice *dev, int where, u32 mask, u32 data)
+{
+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ int shift = 8 * (where & 3);
+
+ clrsetbits_le32(priv->regs + (where & ~3),
+ mask << shift, data << shift);
+}
+
+static u32 rcar_read_conf(struct udevice *dev, int where)
+{
+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ int shift = 8 * (where & 3);
+
+ return readl(priv->regs + (where & ~3)) >> shift;
+}
+
+static int rcar_pcie_config_access(struct udevice *udev,
+ unsigned char access_type,
+ pci_dev_t bdf, int where, ulong *data)
+{
+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(udev);
+ u32 reg = where & ~3;
+
+ /* Clear errors */
+ clrbits_le32(priv->regs + PCIEERRFR, 0);
+
+ /* Set the PIO address */
+ writel((bdf << 8) | reg, priv->regs + PCIECAR);
+
+ /* Enable the configuration access */
+ if (!PCI_BUS(bdf))
+ writel(CONFIG_SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR);
+ else
+ writel(CONFIG_SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR);
+
+ /* Check for errors */
+ if (readl(priv->regs + PCIEERRFR) & UNSUPPORTED_REQUEST)
+ return -ENODEV;
+
+ /* Check for master and target aborts */
+ if (rcar_read_conf(udev, RCONF(PCI_STATUS)) &
+ (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
+ return -ENODEV;
+
+ if (access_type == RCAR_PCI_ACCESS_READ)
+ *data = readl(priv->regs + PCIECDR);
+ else
+ writel(*data, priv->regs + PCIECDR);
+
+ /* Disable the configuration access */
+ writel(0, priv->regs + PCIECCTLR);
+
+ return 0;
+}
+
+static int rcar_gen3_pcie_addr_valid(pci_dev_t d, uint where)
+{
+ u32 slot;
+
+ if (PCI_FUNC(d))
+ return -EINVAL;
+
+ slot = PCI_DEV(d);
+ if (slot != 1)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int rcar_gen3_pcie_read_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong *val,
+ enum pci_size_t size)
+{
+ ulong reg;
+ int ret;
+
+ ret = rcar_gen3_pcie_addr_valid(bdf, where);
+ if (ret) {
+ *val = pci_get_ff(size);
+ return 0;
+ }
+
+ ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_READ,
+ bdf, where, ®);
+ if (ret != 0)
+ reg = 0xffffffffUL;
+
+ *val = pci_conv_32_to_size(reg, where, size);
+
+ return ret;
+}
+
+static int rcar_gen3_pcie_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong val,
+ enum pci_size_t size)
+{
+ ulong data;
+ int ret;
+
+ ret = rcar_gen3_pcie_addr_valid(bdf, where);
+ if (ret)
+ return ret;
+
+ data = pci_conv_32_to_size(val, where, size);
+
+ ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_WRITE,
+ bdf, where, &data);
+
+ return ret;
+}
+
+static int rcar_gen3_pcie_wait_for_phyrdy(struct udevice *dev)
+{
+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+
+ return wait_for_bit_le32((void *)priv->regs + PCIEPHYSR, PHYRDY,
+ true, 50, false);
+}
+
+static int rcar_gen3_pcie_wait_for_dl(struct udevice *dev)
+{
+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+
+ return wait_for_bit_le32((void *)priv->regs + PCIETSTR,
+ DATA_LINK_ACTIVE, true, 50, false);
+}
+
+static int rcar_gen3_pcie_hw_init(struct udevice *dev)
+{
+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ int ret;
+
+ /* Begin initialization */
+ writel(0, priv->regs + PCIETCTLR);
+
+ /* Set mode */
+ writel(1, priv->regs + PCIEMSR);
+
+ ret = rcar_gen3_pcie_wait_for_phyrdy(dev);
+ if (ret)
+ return ret;
+
+ /*
+ * Initial header for port config space is type 1, set the device
+ * class to match. Hardware takes care of propagating the IDSETR
+ * settings, so there is no need to bother with a quirk.
+ */
+ writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1);
+
+ /*
+ * Setup Secondary Bus Number & Subordinate Bus Number, even though
+ * they aren't used, to avoid bridge being detected as broken.
+ */
+ rcar_rmw32(dev, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
+ rcar_rmw32(dev, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
+
+ /* Initialize default capabilities. */
+ rcar_rmw32(dev, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
+ rcar_rmw32(dev, REXPCAP(PCI_EXP_FLAGS),
+ PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
+ rcar_rmw32(dev, RCONF(PCI_HEADER_TYPE), 0x7f,
+ PCI_HEADER_TYPE_BRIDGE);
+
+ /* Enable data link layer active state reporting */
+ rcar_rmw32(dev, REXPCAP(PCI_EXP_LNKCAP),
+ PCI_EXP_LNKCAP_DLLLARC, PCI_EXP_LNKCAP_DLLLARC);
+
+ /* Write out the physical slot number = 0 */
+ rcar_rmw32(dev, REXPCAP(PCI_EXP_SLTCAP),
+ PCI_EXP_SLTCAP_PSN, 0);
+
+ /* Set the completion timer timeout to the maximum 50ms. */
+ rcar_rmw32(dev, TLCTLR + 1, 0x3f, 50);
+
+ /* Terminate list of capabilities (Next Capability Offset=0) */
+ rcar_rmw32(dev, RVCCAP(0), 0xfff00000, 0);
+
+ /* Finish initialization - establish a PCI Express link */
+ writel(CFINIT, priv->regs + PCIETCTLR);
+
+ return rcar_gen3_pcie_wait_for_dl(dev);
+}
+
+static int rcar_gen3_pcie_probe(struct udevice *dev)
+{
+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(dev);
+ struct clk pci_clk;
+ u32 mask;
+ int i, cnt, ret;
+
+ ret = clk_get_by_index(dev, 0, &pci_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&pci_clk);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < hose->region_count; i++) {
+ if (hose->regions[i].flags != PCI_REGION_SYS_MEMORY)
+ continue;
+
+ if (hose->regions[i].phys_start == 0)
+ continue;
+
+ mask = (hose->regions[i].size - 1) & ~0xf;
+ mask |= LAR_ENABLE;
+ writel(hose->regions[i].phys_start, priv->regs + PCIEPRAR(0));
+ writel(hose->regions[i].phys_start, priv->regs + PCIELAR(0));
+ writel(mask, priv->regs + PCIELAMR(0));
+ break;
+ }
+
+ writel(0, priv->regs + PCIEPRAR(4));
+ writel(0, priv->regs + PCIELAR(4));
+ writel(0, priv->regs + PCIELAMR(4));
+
+ ret = rcar_gen3_pcie_hw_init(dev);
+ if (ret)
+ return ret;
+
+ for (i = 0, cnt = 0; i < hose->region_count; i++) {
+ if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
+ continue;
+
+ writel(0, priv->regs + PCIEPTCTLR(cnt));
+ writel((hose->regions[i].size - 1) & ~0x7f,
+ priv->regs + PCIEPAMR(cnt));
+ writel(upper_32_bits(hose->regions[i].phys_start),
+ priv->regs + PCIEPAUR(cnt));
+ writel(lower_32_bits(hose->regions[i].phys_start),
+ priv->regs + PCIEPALR(cnt));
+ mask = PAR_ENABLE;
+ if (hose->regions[i].flags == PCI_REGION_IO)
+ mask |= IO_SPACE;
+ writel(mask, priv->regs + PCIEPTCTLR(cnt));
+
+ cnt++;
+ }
+
+ return 0;
+}
+
+static int rcar_gen3_pcie_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
+
+ priv->regs = devfdt_get_addr_index(dev, 0);
+ if (!priv->regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops rcar_gen3_pcie_ops = {
+ .read_config = rcar_gen3_pcie_read_config,
+ .write_config = rcar_gen3_pcie_write_config,
+};
+
+static const struct udevice_id rcar_gen3_pcie_ids[] = {
+ { .compatible = "renesas,pcie-rcar-gen3" },
+ { }
+};
+
+U_BOOT_DRIVER(rcar_gen3_pcie) = {
+ .name = "rcar_gen3_pcie",
+ .id = UCLASS_PCI,
+ .of_match = rcar_gen3_pcie_ids,
+ .ops = &rcar_gen3_pcie_ops,
+ .probe = rcar_gen3_pcie_probe,
+ .ofdata_to_platdata = rcar_gen3_pcie_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct rcar_gen3_pcie_priv),
+};
PCI_DEV(dm_pci_get_bdf(dev)));
break;
#endif
-#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
+ !defined(CONFIG_TARGET_CADDY2)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
PCI_DEV(dev));
break;
#endif
-#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
+ !defined(CONFIG_TARGET_CADDY2)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
goto err;
#endif
} else {
-#if defined(CONFIG_X86) && CONFIG_IS_ENABLED(X86_32BIT_INIT)
+#if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL)
bios_set_interrupt_handler(0x15, int15_handler);
bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * PCIe Gen4 driver for NXP Layerscape SoCs
+ * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm.h>
+#include <linux/sizes.h>
+
+#include "pcie_layerscape_gen4.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+LIST_HEAD(ls_pcie_g4_list);
+
+static u64 bar_size[4] = {
+ PCIE_BAR0_SIZE,
+ PCIE_BAR1_SIZE,
+ PCIE_BAR2_SIZE,
+ PCIE_BAR4_SIZE
+};
+
+static int ls_pcie_g4_ltssm(struct ls_pcie_g4 *pcie)
+{
+ u32 state;
+
+ state = pf_ctrl_readl(pcie, PCIE_LTSSM_STA) & LTSSM_STATE_MASK;
+
+ return state;
+}
+
+static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)
+{
+ int ltssm;
+
+ ltssm = ls_pcie_g4_ltssm(pcie);
+ if (ltssm != LTSSM_PCIE_L0)
+ return 0;
+
+ return 1;
+}
+
+static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)
+{
+ ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);
+}
+
+static void ls_pcie_g4_cfg_set_target(struct ls_pcie_g4 *pcie, u32 target)
+{
+ ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);
+ ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
+}
+
+static int ls_pcie_g4_outbound_win_set(struct ls_pcie_g4 *pcie, int idx,
+ int type, u64 phys, u64 bus_addr,
+ pci_size_t size)
+{
+ u32 val;
+ u32 size_h, size_l;
+
+ if (idx >= PAB_WINS_NUM)
+ return -EINVAL;
+
+ size_h = upper_32_bits(~(size - 1));
+ size_l = lower_32_bits(~(size - 1));
+
+ val = ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
+ val &= ~((AXI_AMAP_CTRL_TYPE_MASK << AXI_AMAP_CTRL_TYPE_SHIFT) |
+ (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT) |
+ AXI_AMAP_CTRL_EN);
+ val |= ((type & AXI_AMAP_CTRL_TYPE_MASK) << AXI_AMAP_CTRL_TYPE_SHIFT) |
+ ((size_l >> AXI_AMAP_CTRL_SIZE_SHIFT) <<
+ AXI_AMAP_CTRL_SIZE_SHIFT) | AXI_AMAP_CTRL_EN;
+
+ ccsr_writel(pcie, PAB_AXI_AMAP_CTRL(idx), val);
+
+ ccsr_writel(pcie, PAB_AXI_AMAP_AXI_WIN(idx), lower_32_bits(phys));
+ ccsr_writel(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(idx), upper_32_bits(phys));
+ ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
+ ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
+ ccsr_writel(pcie, PAB_EXT_AXI_AMAP_SIZE(idx), size_h);
+
+ return 0;
+}
+
+static int ls_pcie_g4_rc_inbound_win_set(struct ls_pcie_g4 *pcie, int idx,
+ int type, u64 phys, u64 bus_addr,
+ pci_size_t size)
+{
+ u32 val;
+ pci_size_t win_size = ~(size - 1);
+
+ val = ccsr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
+
+ val &= ~(PEX_AMAP_CTRL_TYPE_MASK << PEX_AMAP_CTRL_TYPE_SHIFT);
+ val &= ~(PEX_AMAP_CTRL_EN_MASK << PEX_AMAP_CTRL_EN_SHIFT);
+ val = (val | (type << PEX_AMAP_CTRL_TYPE_SHIFT));
+ val = (val | (1 << PEX_AMAP_CTRL_EN_SHIFT));
+
+ ccsr_writel(pcie, PAB_PEX_AMAP_CTRL(idx),
+ val | lower_32_bits(win_size));
+
+ ccsr_writel(pcie, PAB_EXT_PEX_AMAP_SIZE(idx), upper_32_bits(win_size));
+ ccsr_writel(pcie, PAB_PEX_AMAP_AXI_WIN(idx), lower_32_bits(phys));
+ ccsr_writel(pcie, PAB_EXT_PEX_AMAP_AXI_WIN(idx), upper_32_bits(phys));
+ ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
+ ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
+
+ return 0;
+}
+
+static void ls_pcie_g4_dump_wins(struct ls_pcie_g4 *pcie, int wins)
+{
+ int i;
+
+ for (i = 0; i < wins; i++) {
+ debug("APIO Win%d:\n", i);
+ debug("\tLOWER PHYS: 0x%08x\n",
+ ccsr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(i)));
+ debug("\tUPPER PHYS: 0x%08x\n",
+ ccsr_readl(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(i)));
+ debug("\tLOWER BUS: 0x%08x\n",
+ ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_L(i)));
+ debug("\tUPPER BUS: 0x%08x\n",
+ ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(i)));
+ debug("\tSIZE: 0x%08x\n",
+ ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)) &
+ (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT));
+ debug("\tEXT_SIZE: 0x%08x\n",
+ ccsr_readl(pcie, PAB_EXT_AXI_AMAP_SIZE(i)));
+ debug("\tPARAM: 0x%08x\n",
+ ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(i)));
+ debug("\tCTRL: 0x%08x\n",
+ ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)));
+ }
+}
+
+static void ls_pcie_g4_setup_wins(struct ls_pcie_g4 *pcie)
+{
+ struct pci_region *io, *mem, *pref;
+ int idx = 1;
+
+ /* INBOUND WIN */
+ ls_pcie_g4_rc_inbound_win_set(pcie, 0, IB_TYPE_MEM_F, 0, 0, SIZE_1T);
+
+ /* OUTBOUND WIN 0: CFG */
+ ls_pcie_g4_outbound_win_set(pcie, 0, PAB_AXI_TYPE_CFG,
+ pcie->cfg_res.start, 0,
+ fdt_resource_size(&pcie->cfg_res));
+
+ pci_get_regions(pcie->bus, &io, &mem, &pref);
+
+ if (io)
+ /* OUTBOUND WIN: IO */
+ ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_IO,
+ io->phys_start, io->bus_start,
+ io->size);
+
+ if (mem)
+ /* OUTBOUND WIN: MEM */
+ ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
+ mem->phys_start, mem->bus_start,
+ mem->size);
+
+ if (pref)
+ /* OUTBOUND WIN: perf MEM */
+ ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
+ pref->phys_start, pref->bus_start,
+ pref->size);
+
+ ls_pcie_g4_dump_wins(pcie, idx);
+}
+
+/* Return 0 if the address is valid, -errno if not valid */
+static int ls_pcie_g4_addr_valid(struct ls_pcie_g4 *pcie, pci_dev_t bdf)
+{
+ struct udevice *bus = pcie->bus;
+
+ if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+ return -ENODEV;
+
+ if (!pcie->enabled)
+ return -ENXIO;
+
+ if (PCI_BUS(bdf) < bus->seq)
+ return -EINVAL;
+
+ if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_g4_link_up(pcie)))
+ return -EINVAL;
+
+ if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
+ return -EINVAL;
+
+ return 0;
+}
+
+void *ls_pcie_g4_conf_address(struct ls_pcie_g4 *pcie, pci_dev_t bdf,
+ int offset)
+{
+ struct udevice *bus = pcie->bus;
+ u32 target;
+
+ if (PCI_BUS(bdf) == bus->seq) {
+ if (offset < INDIRECT_ADDR_BNDRY) {
+ ccsr_set_page(pcie, 0);
+ return pcie->ccsr + offset;
+ }
+
+ ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
+ return pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset);
+ }
+
+ target = PAB_TARGET_BUS(PCI_BUS(bdf) - bus->seq) |
+ PAB_TARGET_DEV(PCI_DEV(bdf)) |
+ PAB_TARGET_FUNC(PCI_FUNC(bdf));
+
+ ls_pcie_g4_cfg_set_target(pcie, target);
+
+ return pcie->cfg + offset;
+}
+
+static int ls_pcie_g4_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct ls_pcie_g4 *pcie = dev_get_priv(bus);
+ void *address;
+ int ret = 0;
+
+ if (ls_pcie_g4_addr_valid(pcie, bdf)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ address = ls_pcie_g4_conf_address(pcie, bdf, offset);
+
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = readb(address);
+ break;
+ case PCI_SIZE_16:
+ *valuep = readw(address);
+ break;
+ case PCI_SIZE_32:
+ *valuep = readl(address);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int ls_pcie_g4_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct ls_pcie_g4 *pcie = dev_get_priv(bus);
+ void *address;
+
+ if (ls_pcie_g4_addr_valid(pcie, bdf))
+ return 0;
+
+ address = ls_pcie_g4_conf_address(pcie, bdf, offset);
+
+ switch (size) {
+ case PCI_SIZE_8:
+ writeb(value, address);
+ return 0;
+ case PCI_SIZE_16:
+ writew(value, address);
+ return 0;
+ case PCI_SIZE_32:
+ writel(value, address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie)
+{
+ u32 val;
+
+ /* Fix class code */
+ val = ccsr_readl(pcie, GPEX_CLASSCODE);
+ val &= ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT);
+ val |= PCI_CLASS_BRIDGE_PCI << GPEX_CLASSCODE_SHIFT;
+ ccsr_writel(pcie, GPEX_CLASSCODE, val);
+
+ /* Enable APIO and Memory/IO/CFG Wins */
+ val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
+ val |= APIO_EN | MEM_WIN_EN | IO_WIN_EN | CFG_WIN_EN;
+ ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
+
+ ls_pcie_g4_setup_wins(pcie);
+
+ pcie->stream_id_cur = 0;
+}
+
+static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,
+ int bar, u64 phys)
+{
+ u32 val;
+
+ /* PF BAR1 is for MSI-X and only need to enable */
+ if (bar == 1) {
+ ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), BAR_AMAP_EN);
+ return;
+ }
+
+ val = upper_32_bits(phys);
+ ccsr_writel(pcie, PAB_EXT_PEX_BAR_AMAP(pf, bar), val);
+ val = lower_32_bits(phys) | BAR_AMAP_EN;
+ ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), val);
+}
+
+static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
+{
+ u64 phys;
+ int bar;
+ u32 val;
+
+ if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)
+ return;
+
+ phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
+ for (bar = 0; bar < PF_BAR_NUM; bar++) {
+ ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);
+ phys += PCIE_BAR_SIZE;
+ }
+
+ /* OUTBOUND: map MEM */
+ ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,
+ pcie->cfg_res.start +
+ CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
+ CONFIG_SYS_PCI_MEMORY_SIZE);
+
+ val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));
+ val &= ~FUNC_NUM_PCIE_MASK;
+ val |= pf;
+ ccsr_writel(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf), val);
+}
+
+static void ls_pcie_g4_ep_enable_bar(struct ls_pcie_g4 *pcie, int pf,
+ int bar, bool vf_bar, bool enable)
+{
+ u32 val;
+ u32 bar_pos = BAR_POS(bar, pf, vf_bar);
+
+ val = ccsr_readl(pcie, GPEX_BAR_ENABLE);
+ if (enable)
+ val |= 1 << bar_pos;
+ else
+ val &= ~(1 << bar_pos);
+ ccsr_writel(pcie, GPEX_BAR_ENABLE, val);
+}
+
+static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf,
+ int bar, bool vf_bar, u64 size)
+{
+ u32 bar_pos = BAR_POS(bar, pf, vf_bar);
+ u32 mask_l = lower_32_bits(~(size - 1));
+ u32 mask_h = upper_32_bits(~(size - 1));
+
+ ccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos);
+ ccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l);
+ ccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);
+}
+
+static void ls_pcie_g4_ep_setup_bar(struct ls_pcie_g4 *pcie, int pf,
+ int bar, bool vf_bar, u64 size)
+{
+ bool en = size ? true : false;
+
+ ls_pcie_g4_ep_enable_bar(pcie, pf, bar, vf_bar, en);
+ ls_pcie_g4_ep_set_bar_size(pcie, pf, bar, vf_bar, size);
+}
+
+static void ls_pcie_g4_ep_setup_bars(struct ls_pcie_g4 *pcie, int pf)
+{
+ int bar;
+
+ /* Setup PF BARs */
+ for (bar = 0; bar < PF_BAR_NUM; bar++)
+ ls_pcie_g4_ep_setup_bar(pcie, pf, bar, false, bar_size[bar]);
+
+ if (!pcie->sriov_support)
+ return;
+
+ /* Setup VF BARs */
+ for (bar = 0; bar < VF_BAR_NUM; bar++)
+ ls_pcie_g4_ep_setup_bar(pcie, pf, bar, true, bar_size[bar]);
+}
+
+static void ls_pcie_g4_set_sriov(struct ls_pcie_g4 *pcie, int pf)
+{
+ unsigned int val;
+
+ val = ccsr_readl(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf));
+ val &= ~(TTL_VF_MASK << TTL_VF_SHIFT);
+ val |= PCIE_VF_NUM << TTL_VF_SHIFT;
+ val &= ~(INI_VF_MASK << INI_VF_SHIFT);
+ val |= PCIE_VF_NUM << INI_VF_SHIFT;
+ ccsr_writel(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf), val);
+
+ val = ccsr_readl(pcie, PCIE_SRIOV_VF_OFFSET_STRIDE);
+ val += PCIE_VF_NUM * pf - pf;
+ ccsr_writel(pcie, GPEX_SRIOV_VF_OFFSET_STRIDE(pf), val);
+}
+
+static void ls_pcie_g4_setup_ep(struct ls_pcie_g4 *pcie)
+{
+ u32 pf, sriov;
+ u32 val;
+ int i;
+
+ /* Enable APIO and Memory Win */
+ val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
+ val |= APIO_EN | MEM_WIN_EN;
+ ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
+
+ sriov = ccsr_readl(pcie, PCIE_SRIOV_CAPABILITY);
+ if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
+ pcie->sriov_support = 1;
+
+ pf = pcie->sriov_support ? PCIE_PF_NUM : 1;
+
+ for (i = 0; i < pf; i++) {
+ ls_pcie_g4_ep_setup_bars(pcie, i);
+ ls_pcie_g4_ep_setup_wins(pcie, i);
+ if (pcie->sriov_support)
+ ls_pcie_g4_set_sriov(pcie, i);
+ }
+
+ ls_pcie_g4_ep_enable_cfg(pcie);
+ ls_pcie_g4_dump_wins(pcie, pf);
+}
+
+static int ls_pcie_g4_probe(struct udevice *dev)
+{
+ struct ls_pcie_g4 *pcie = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ u32 link_ctrl_sta;
+ u32 val;
+ int ret;
+
+ pcie->bus = dev;
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "ccsr", &pcie->ccsr_res);
+ if (ret) {
+ printf("ls-pcie-g4: resource \"ccsr\" not found\n");
+ return ret;
+ }
+
+ pcie->idx = (pcie->ccsr_res.start - PCIE_SYS_BASE_ADDR) /
+ PCIE_CCSR_SIZE;
+
+ list_add(&pcie->list, &ls_pcie_g4_list);
+
+ pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
+ if (!pcie->enabled) {
+ printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ return 0;
+ }
+
+ pcie->ccsr = map_physmem(pcie->ccsr_res.start,
+ fdt_resource_size(&pcie->ccsr_res),
+ MAP_NOCACHE);
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "config", &pcie->cfg_res);
+ if (ret) {
+ printf("%s: resource \"config\" not found\n", dev->name);
+ return ret;
+ }
+
+ pcie->cfg = map_physmem(pcie->cfg_res.start,
+ fdt_resource_size(&pcie->cfg_res),
+ MAP_NOCACHE);
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "lut", &pcie->lut_res);
+ if (ret) {
+ printf("ls-pcie-g4: resource \"lut\" not found\n");
+ return ret;
+ }
+
+ pcie->lut = map_physmem(pcie->lut_res.start,
+ fdt_resource_size(&pcie->lut_res),
+ MAP_NOCACHE);
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "pf_ctrl", &pcie->pf_ctrl_res);
+ if (ret) {
+ printf("ls-pcie-g4: resource \"pf_ctrl\" not found\n");
+ return ret;
+ }
+
+ pcie->pf_ctrl = map_physmem(pcie->pf_ctrl_res.start,
+ fdt_resource_size(&pcie->pf_ctrl_res),
+ MAP_NOCACHE);
+
+ pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+
+ debug("%s ccsr:%lx, cfg:0x%lx, big-endian:%d\n",
+ dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg,
+ pcie->big_endian);
+
+ pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
+
+ if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
+ printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+ ls_pcie_g4_setup_ep(pcie);
+ } else {
+ printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+ ls_pcie_g4_setup_ctrl(pcie);
+ }
+
+ /* Enable Amba & PEX PIO */
+ val = ccsr_readl(pcie, PAB_CTRL);
+ val |= PAB_CTRL_APIO_EN | PAB_CTRL_PPIO_EN;
+ ccsr_writel(pcie, PAB_CTRL, val);
+
+ val = ccsr_readl(pcie, PAB_PEX_PIO_CTRL(0));
+ val |= PPIO_EN;
+ ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val);
+
+ if (!ls_pcie_g4_link_up(pcie)) {
+ /* Let the user know there's no PCIe link */
+ printf(": no link\n");
+ return 0;
+ }
+
+ /* Print the negotiated PCIe link width */
+ link_ctrl_sta = ccsr_readl(pcie, PCIE_LINK_CTRL_STA);
+ printf(": x%d gen%d\n",
+ (link_ctrl_sta >> PCIE_LINK_WIDTH_SHIFT & PCIE_LINK_WIDTH_MASK),
+ (link_ctrl_sta >> PCIE_LINK_SPEED_SHIFT) & PCIE_LINK_SPEED_MASK);
+
+ return 0;
+}
+
+static const struct dm_pci_ops ls_pcie_g4_ops = {
+ .read_config = ls_pcie_g4_read_config,
+ .write_config = ls_pcie_g4_write_config,
+};
+
+static const struct udevice_id ls_pcie_g4_ids[] = {
+ { .compatible = "fsl,lx2160a-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pcie_layerscape_gen4) = {
+ .name = "pcie_layerscape_gen4",
+ .id = UCLASS_PCI,
+ .of_match = ls_pcie_g4_ids,
+ .ops = &ls_pcie_g4_ops,
+ .probe = ls_pcie_g4_probe,
+ .priv_auto_alloc_size = sizeof(struct ls_pcie_g4),
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * PCIe Gen4 driver for NXP Layerscape SoCs
+ * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
+ */
+
+#ifndef _PCIE_LAYERSCAPE_GEN4_H_
+#define _PCIE_LAYERSCAPE_GEN4_H_
+#include <pci.h>
+#include <dm.h>
+
+#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
+#define CONFIG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL)
+#endif
+
+#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
+#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
+#endif
+
+#define PCIE_PF_NUM 2
+#define PCIE_VF_NUM 32
+
+#define LS_G4_PF0 0
+#define LS_G4_PF1 1
+#define PF_BAR_NUM 4
+#define VF_BAR_NUM 4
+#define PCIE_BAR_SIZE (8 * 1024) /* 8K */
+#define PCIE_BAR0_SIZE PCIE_BAR_SIZE
+#define PCIE_BAR1_SIZE PCIE_BAR_SIZE
+#define PCIE_BAR2_SIZE PCIE_BAR_SIZE
+#define PCIE_BAR4_SIZE PCIE_BAR_SIZE
+#define SIZE_1T (1024 * 1024 * 1024 * 1024ULL)
+
+/* GPEX CSR */
+#define GPEX_CLASSCODE 0x474
+#define GPEX_CLASSCODE_SHIFT 16
+#define GPEX_CLASSCODE_MASK 0xffff
+
+#define GPEX_CFG_READY 0x4b0
+#define PCIE_CONFIG_READY BIT(0)
+
+#define GPEX_BAR_ENABLE 0x4d4
+#define GPEX_BAR_SIZE_LDW 0x4d8
+#define GPEX_BAR_SIZE_UDW 0x4dC
+#define GPEX_BAR_SELECT 0x4e0
+
+#define BAR_POS(bar, pf, vf_bar) \
+ ((bar) + (pf) * PF_BAR_NUM + (vf_bar) * PCIE_PF_NUM * PF_BAR_NUM)
+
+#define GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf) (0x644 + (pf) * 4)
+#define TTL_VF_MASK 0xffff
+#define TTL_VF_SHIFT 16
+#define INI_VF_MASK 0xffff
+#define INI_VF_SHIFT 0
+#define GPEX_SRIOV_VF_OFFSET_STRIDE(pf) (0x704 + (pf) * 4)
+
+/* PAB CSR */
+#define PAB_CTRL 0x808
+#define PAB_CTRL_APIO_EN BIT(0)
+#define PAB_CTRL_PPIO_EN BIT(1)
+#define PAB_CTRL_MAX_BRST_LEN_SHIFT 4
+#define PAB_CTRL_MAX_BRST_LEN_MASK 0x3
+#define PAB_CTRL_PAGE_SEL_SHIFT 13
+#define PAB_CTRL_PAGE_SEL_MASK 0x3f
+#define PAB_CTRL_FUNC_SEL_SHIFT 19
+#define PAB_CTRL_FUNC_SEL_MASK 0x1ff
+
+#define PAB_RST_CTRL 0x820
+#define PAB_BR_STAT 0x80c
+
+/* AXI PIO Engines */
+#define PAB_AXI_PIO_CTRL(idx) (0x840 + 0x10 * (idx))
+#define APIO_EN BIT(0)
+#define MEM_WIN_EN BIT(1)
+#define IO_WIN_EN BIT(2)
+#define CFG_WIN_EN BIT(3)
+#define PAB_AXI_PIO_STAT(idx) (0x844 + 0x10 * (idx))
+#define PAB_AXI_PIO_SL_CMD_STAT(idx) (0x848 + 0x10 * (idx))
+#define PAB_AXI_PIO_SL_ADDR_STAT(idx) (0x84c + 0x10 * (idx))
+#define PAB_AXI_PIO_SL_EXT_ADDR_STAT(idx) (0xb8a0 + 0x4 * (idx))
+
+/* PEX PIO Engines */
+#define PAB_PEX_PIO_CTRL(idx) (0x8c0 + 0x10 * (idx))
+#define PPIO_EN BIT(0)
+#define PAB_PEX_PIO_STAT(idx) (0x8c4 + 0x10 * (idx))
+#define PAB_PEX_PIO_MT_STAT(idx) (0x8c8 + 0x10 * (idx))
+
+#define INDIRECT_ADDR_BNDRY 0xc00
+#define PAGE_IDX_SHIFT 10
+#define PAGE_ADDR_MASK 0x3ff
+
+#define OFFSET_TO_PAGE_IDX(off) \
+ (((off) >> PAGE_IDX_SHIFT) & PAB_CTRL_PAGE_SEL_MASK)
+
+#define OFFSET_TO_PAGE_ADDR(off) \
+ (((off) & PAGE_ADDR_MASK) | INDIRECT_ADDR_BNDRY)
+
+/* APIO WINs */
+#define PAB_AXI_AMAP_CTRL(idx) (0xba0 + 0x10 * (idx))
+#define PAB_EXT_AXI_AMAP_SIZE(idx) (0xbaf0 + 0x4 * (idx))
+#define PAB_AXI_AMAP_AXI_WIN(idx) (0xba4 + 0x10 * (idx))
+#define PAB_EXT_AXI_AMAP_AXI_WIN(idx) (0x80a0 + 0x4 * (idx))
+#define PAB_AXI_AMAP_PEX_WIN_L(idx) (0xba8 + 0x10 * (idx))
+#define PAB_AXI_AMAP_PEX_WIN_H(idx) (0xbac + 0x10 * (idx))
+#define PAB_AXI_AMAP_PCI_HDR_PARAM(idx) (0x5ba0 + 0x4 * (idx))
+#define FUNC_NUM_PCIE_MASK GENMASK(7, 0)
+
+#define AXI_AMAP_CTRL_EN BIT(0)
+#define AXI_AMAP_CTRL_TYPE_SHIFT 1
+#define AXI_AMAP_CTRL_TYPE_MASK 0x3
+#define AXI_AMAP_CTRL_SIZE_SHIFT 10
+#define AXI_AMAP_CTRL_SIZE_MASK 0x3fffff
+
+#define PAB_TARGET_BUS(x) (((x) & 0xff) << 24)
+#define PAB_TARGET_DEV(x) (((x) & 0x1f) << 19)
+#define PAB_TARGET_FUNC(x) (((x) & 0x7) << 16)
+
+#define PAB_AXI_TYPE_CFG 0x00
+#define PAB_AXI_TYPE_IO 0x01
+#define PAB_AXI_TYPE_MEM 0x02
+#define PAB_AXI_TYPE_ATOM 0x03
+
+#define PAB_WINS_NUM 256
+
+/* PPIO WINs RC mode */
+#define PAB_PEX_AMAP_CTRL(idx) (0x4ba0 + 0x10 * (idx))
+#define PAB_EXT_PEX_AMAP_SIZE(idx) (0xbef0 + 0x04 * (idx))
+#define PAB_PEX_AMAP_AXI_WIN(idx) (0x4ba4 + 0x10 * (idx))
+#define PAB_EXT_PEX_AMAP_AXI_WIN(idx) (0xb4a0 + 0x04 * (idx))
+#define PAB_PEX_AMAP_PEX_WIN_L(idx) (0x4ba8 + 0x10 * (idx))
+#define PAB_PEX_AMAP_PEX_WIN_H(idx) (0x4bac + 0x10 * (idx))
+
+#define IB_TYPE_MEM_F 0x2
+#define IB_TYPE_MEM_NF 0x3
+
+#define PEX_AMAP_CTRL_TYPE_SHIFT 0x1
+#define PEX_AMAP_CTRL_EN_SHIFT 0x0
+#define PEX_AMAP_CTRL_TYPE_MASK 0x3
+#define PEX_AMAP_CTRL_EN_MASK 0x1
+
+/* PPIO WINs EP mode */
+#define PAB_PEX_BAR_AMAP(pf, bar) \
+ (0x1ba0 + 0x20 * (pf) + 4 * (bar))
+#define BAR_AMAP_EN BIT(0)
+#define PAB_EXT_PEX_BAR_AMAP(pf, bar) \
+ (0x84a0 + 0x20 * (pf) + 4 * (bar))
+
+/* CCSR registers */
+#define PCIE_LINK_CTRL_STA 0x5c
+#define PCIE_LINK_SPEED_SHIFT 16
+#define PCIE_LINK_SPEED_MASK 0x0f
+#define PCIE_LINK_WIDTH_SHIFT 20
+#define PCIE_LINK_WIDTH_MASK 0x3f
+#define PCIE_SRIOV_CAPABILITY 0x2a0
+#define PCIE_SRIOV_VF_OFFSET_STRIDE 0x2b4
+
+/* LUT registers */
+#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
+#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
+#define PCIE_LUT_ENABLE BIT(31)
+#define PCIE_LUT_ENTRY_COUNT 32
+
+/* PF control registers */
+#define PCIE_LTSSM_STA 0x7fc
+#define LTSSM_STATE_MASK 0x7f
+#define LTSSM_PCIE_L0 0x2d /* L0 state */
+
+#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
+#define PCIE_SYS_BASE_ADDR 0x3400000
+#define PCIE_CCSR_SIZE 0x0100000
+
+struct ls_pcie_g4 {
+ int idx;
+ struct list_head list;
+ struct udevice *bus;
+ struct fdt_resource ccsr_res;
+ struct fdt_resource cfg_res;
+ struct fdt_resource lut_res;
+ struct fdt_resource pf_ctrl_res;
+ void __iomem *ccsr;
+ void __iomem *cfg;
+ void __iomem *lut;
+ void __iomem *pf_ctrl;
+ bool big_endian;
+ bool enabled;
+ int next_lut_index;
+ struct pci_controller hose;
+ int stream_id_cur;
+ int mode;
+ int sriov_support;
+};
+
+extern struct list_head ls_pcie_g4_list;
+
+static inline void lut_writel(struct ls_pcie_g4 *pcie, unsigned int value,
+ unsigned int offset)
+{
+ if (pcie->big_endian)
+ out_be32(pcie->lut + offset, value);
+ else
+ out_le32(pcie->lut + offset, value);
+}
+
+static inline u32 lut_readl(struct ls_pcie_g4 *pcie, unsigned int offset)
+{
+ if (pcie->big_endian)
+ return in_be32(pcie->lut + offset);
+ else
+ return in_le32(pcie->lut + offset);
+}
+
+static inline void ccsr_set_page(struct ls_pcie_g4 *pcie, u8 pg_idx)
+{
+ u32 val;
+
+ val = in_le32(pcie->ccsr + PAB_CTRL);
+ val &= ~(PAB_CTRL_PAGE_SEL_MASK << PAB_CTRL_PAGE_SEL_SHIFT);
+ val |= (pg_idx & PAB_CTRL_PAGE_SEL_MASK) << PAB_CTRL_PAGE_SEL_SHIFT;
+
+ out_le32(pcie->ccsr + PAB_CTRL, val);
+}
+
+static inline unsigned int ccsr_readl(struct ls_pcie_g4 *pcie, u32 offset)
+{
+ if (offset < INDIRECT_ADDR_BNDRY) {
+ ccsr_set_page(pcie, 0);
+ return in_le32(pcie->ccsr + offset);
+ }
+
+ ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
+ return in_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset));
+}
+
+static inline void ccsr_writel(struct ls_pcie_g4 *pcie, u32 offset, u32 value)
+{
+ if (offset < INDIRECT_ADDR_BNDRY) {
+ ccsr_set_page(pcie, 0);
+ out_le32(pcie->ccsr + offset, value);
+ } else {
+ ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
+ out_le32(pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset), value);
+ }
+}
+
+static inline unsigned int pf_ctrl_readl(struct ls_pcie_g4 *pcie, u32 offset)
+{
+ if (pcie->big_endian)
+ return in_be32(pcie->pf_ctrl + offset);
+ else
+ return in_le32(pcie->pf_ctrl + offset);
+}
+
+static inline void pf_ctrl_writel(struct ls_pcie_g4 *pcie, u32 offset,
+ u32 value)
+{
+ if (pcie->big_endian)
+ out_be32(pcie->pf_ctrl + offset, value);
+ else
+ out_le32(pcie->pf_ctrl + offset, value);
+}
+
+#endif /* _PCIE_LAYERSCAPE_GEN4_H_ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * PCIe Gen4 driver for NXP Layerscape SoCs
+ * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/io.h>
+#include <errno.h>
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#ifdef CONFIG_ARM
+#include <asm/arch/clock.h>
+#endif
+#include "pcie_layerscape_gen4.h"
+
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+/*
+ * Return next available LUT index.
+ */
+static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
+{
+ if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
+ return pcie->next_lut_index++;
+
+ return -ENOSPC; /* LUT is full */
+}
+
+/* returns the next available streamid for pcie, -errno if failed */
+static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie)
+{
+ int stream_id = pcie->stream_id_cur;
+
+ if (stream_id > FSL_PEX_STREAM_ID_NUM)
+ return -EINVAL;
+
+ pcie->stream_id_cur++;
+
+ return stream_id | ((pcie->idx + 1) << 11);
+}
+
+/*
+ * Program a single LUT entry
+ */
+static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
+ u32 devid, u32 streamid)
+{
+ /* leave mask as all zeroes, want to match all bits */
+ lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
+ lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
+}
+
+/*
+ * An msi-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie_g4 *pcie,
+ u32 devid, u32 streamid)
+{
+ u32 *prop;
+ u32 phandle;
+ int nodeoff;
+
+#ifdef CONFIG_FSL_PCIE_COMPAT
+ nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
+ pcie->ccsr_res.start);
+#else
+#error "No CONFIG_FSL_PCIE_COMPAT defined"
+#endif
+ if (nodeoff < 0) {
+ debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
+ return;
+ }
+
+ /* get phandle to MSI controller */
+ prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
+ if (!prop) {
+ debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
+ __func__, pcie->idx);
+ return;
+ }
+ phandle = fdt32_to_cpu(*prop);
+
+ /* set one msi-map row */
+ fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
+ fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
+ fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
+ fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
+}
+
+/*
+ * An iommu-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie_g4 *pcie,
+ u32 devid, u32 streamid)
+{
+ u32 *prop;
+ u32 iommu_map[4];
+ int nodeoff;
+ int lenp;
+
+#ifdef CONFIG_FSL_PCIE_COMPAT
+ nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
+ pcie->ccsr_res.start);
+#else
+#error "No CONFIG_FSL_PCIE_COMPAT defined"
+#endif
+ if (nodeoff < 0) {
+ debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
+ return;
+ }
+
+ /* get phandle to iommu controller */
+ prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp);
+ if (!prop) {
+ debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
+ __func__, pcie->idx);
+ return;
+ }
+
+ /* set iommu-map row */
+ iommu_map[0] = cpu_to_fdt32(devid);
+ iommu_map[1] = *++prop;
+ iommu_map[2] = cpu_to_fdt32(streamid);
+ iommu_map[3] = cpu_to_fdt32(1);
+
+ if (devid == 0)
+ fdt_setprop_inplace(blob, nodeoff, "iommu-map", iommu_map, 16);
+ else
+ fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
+}
+
+static void fdt_fixup_pcie(void *blob)
+{
+ struct udevice *dev, *bus;
+ struct ls_pcie_g4 *pcie;
+ int streamid;
+ int index;
+ pci_dev_t bdf;
+
+ /* Scan all known buses */
+ for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
+ for (bus = dev; device_is_on_pci_bus(bus);)
+ bus = bus->parent;
+ pcie = dev_get_priv(bus);
+
+ streamid = ls_pcie_g4_next_streamid(pcie);
+ if (streamid < 0) {
+ debug("ERROR: no stream ids free\n");
+ continue;
+ }
+
+ index = ls_pcie_g4_next_lut_index(pcie);
+ if (index < 0) {
+ debug("ERROR: no LUT indexes free\n");
+ continue;
+ }
+
+ /* the DT fixup must be relative to the hose first_busno */
+ bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, streamid);
+ /* update iommu-map in device tree */
+ fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8, streamid);
+ }
+}
+#endif
+
+static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
+{
+ int off;
+
+ off = fdt_node_offset_by_compat_reg(blob, "fsl,lx2160a-pcie-ep",
+ pcie->ccsr_res.start);
+
+ if (off < 0) {
+ debug("%s: ERROR: failed to find pcie compatiable\n",
+ __func__);
+ return;
+ }
+
+ if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ else
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
+{
+ int off;
+
+#ifdef CONFIG_FSL_PCIE_COMPAT
+ off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
+ pcie->ccsr_res.start);
+#else
+#error "No CONFIG_FSL_PCIE_COMPAT defined"
+#endif
+ if (off < 0) {
+ debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
+ return;
+ }
+
+ if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ else
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
+{
+ ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
+ ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
+}
+
+/* Fixup Kernel DT for PCIe */
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+ struct ls_pcie_g4 *pcie;
+
+ list_for_each_entry(pcie, &ls_pcie_g4_list, list)
+ ft_pcie_layerscape_gen4_setup(blob, pcie);
+
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
+ fdt_fixup_pcie(blob);
+#endif
+}
+
+#else /* !CONFIG_OF_BOARD_SETUP */
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+}
+#endif
This is the generic phy driver for the Amlogic Meson GXL
USB2 and USB3 PHYS.
+config MESON_G12A_USB_PHY
+ bool "Amlogic Meson G12A USB PHYs"
+ depends on PHY && ARCH_MESON && MESON_G12A
+ imply REGMAP
+ help
+ This is the generic phy driver for the Amlogic Meson G12A
+ USB2 and USB3 PHYS.
+
config MSM8916_USB_PHY
bool "Qualcomm MSM8916 USB PHY support"
depends on PHY
obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
+obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Meson G12A USB2 PHY driver
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron@baylibre.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <reset.h>
+#include <clk.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+
+#define PHY_CTRL_R0 0x0
+#define PHY_CTRL_R1 0x4
+#define PHY_CTRL_R2 0x8
+#define PHY_CTRL_R3 0xc
+#define PHY_CTRL_R4 0x10
+#define PHY_CTRL_R5 0x14
+#define PHY_CTRL_R6 0x18
+#define PHY_CTRL_R7 0x1c
+#define PHY_CTRL_R8 0x20
+#define PHY_CTRL_R9 0x24
+#define PHY_CTRL_R10 0x28
+#define PHY_CTRL_R11 0x2c
+#define PHY_CTRL_R12 0x30
+#define PHY_CTRL_R13 0x34
+#define PHY_CTRL_R14 0x38
+#define PHY_CTRL_R15 0x3c
+#define PHY_CTRL_R16 0x40
+#define PHY_CTRL_R17 0x44
+#define PHY_CTRL_R18 0x48
+#define PHY_CTRL_R19 0x4c
+#define PHY_CTRL_R20 0x50
+#define PHY_CTRL_R21 0x54
+#define PHY_CTRL_R22 0x58
+#define PHY_CTRL_R23 0x5c
+
+#define RESET_COMPLETE_TIME 1000
+#define PLL_RESET_COMPLETE_TIME 100
+
+struct phy_meson_g12a_usb2_priv {
+ struct regmap *regmap;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ struct udevice *phy_supply;
+#endif
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+#endif
+ struct reset_ctl reset;
+};
+
+
+static int phy_meson_g12a_usb2_power_on(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->phy_supply) {
+ int ret = regulator_set_enable(priv->phy_supply, true);
+ if (ret)
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static int phy_meson_g12a_usb2_power_off(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->phy_supply) {
+ int ret = regulator_set_enable(priv->phy_supply, false);
+ if (ret) {
+ pr_err("Error disabling PHY supply\n");
+ return ret;
+ }
+ }
+#endif
+
+ return 0;
+}
+
+static int phy_meson_g12a_usb2_init(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = reset_assert(&priv->reset);
+ udelay(1);
+ ret |= reset_deassert(&priv->reset);
+ if (ret)
+ return ret;
+
+ udelay(RESET_COMPLETE_TIME);
+
+ /* usb2_otg_aca_en == 0 */
+ regmap_update_bits(priv->regmap, PHY_CTRL_R21, BIT(2), 0);
+
+ /* PLL Setup : 24MHz * 20 / 1 = 480MHz */
+ regmap_write(priv->regmap, PHY_CTRL_R16, 0x39400414);
+ regmap_write(priv->regmap, PHY_CTRL_R17, 0x927e0000);
+ regmap_write(priv->regmap, PHY_CTRL_R18, 0xac5f49e5);
+
+ udelay(PLL_RESET_COMPLETE_TIME);
+
+ /* UnReset PLL */
+ regmap_write(priv->regmap, PHY_CTRL_R16, 0x19400414);
+
+ /* PHY Tuning */
+ regmap_write(priv->regmap, PHY_CTRL_R20, 0xfe18);
+ regmap_write(priv->regmap, PHY_CTRL_R4, 0x8000fff);
+
+ /* Tuning Disconnect Threshold */
+ regmap_write(priv->regmap, PHY_CTRL_R3, 0x34);
+
+ /* Analog Settings */
+ regmap_write(priv->regmap, PHY_CTRL_R14, 0);
+ regmap_write(priv->regmap, PHY_CTRL_R13, 0x78000);
+
+ return 0;
+}
+
+static int phy_meson_g12a_usb2_exit(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = reset_assert(&priv->reset);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+struct phy_ops meson_g12a_usb2_phy_ops = {
+ .init = phy_meson_g12a_usb2_init,
+ .exit = phy_meson_g12a_usb2_exit,
+ .power_on = phy_meson_g12a_usb2_power_on,
+ .power_off = phy_meson_g12a_usb2_power_off,
+};
+
+int meson_g12a_usb2_phy_probe(struct udevice *dev)
+{
+ struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_index(dev, 0, &priv->reset);
+ if (ret == -ENOTSUPP)
+ return 0;
+ else if (ret)
+ return ret;
+
+ ret = reset_deassert(&priv->reset);
+ if (ret) {
+ reset_release_all(&priv->reset, 1);
+ return ret;
+ }
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ clk_free(&priv->clk);
+ return ret;
+ }
+#endif
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get PHY regulator\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id meson_g12a_usb2_phy_ids[] = {
+ { .compatible = "amlogic,g12a-usb2-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_g12a_usb2_phy) = {
+ .name = "meson_g12a_usb2_phy",
+ .id = UCLASS_PHY,
+ .of_match = meson_g12a_usb2_phy_ids,
+ .probe = meson_g12a_usb2_phy_probe,
+ .ops = &meson_g12a_usb2_phy_ops,
+ .priv_auto_alloc_size = sizeof(struct phy_meson_g12a_usb2_priv),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Meson G12A USB3+PCIE Combo PHY driver
+ *
+ * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron@baylibre.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <regmap.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <reset.h>
+#include <bitfield.h>
+#include <generic-phy.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
+#define PHY_R0 0x00
+ #define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
+ #define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
+
+#define PHY_R1 0x04
+ #define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0)
+ #define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5)
+ #define PHY_R1_PHY_RX1_EQ GENMASK(12, 10)
+ #define PHY_R1_PHY_RX0_EQ GENMASK(15, 13)
+ #define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16)
+ #define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21)
+ #define PHY_R1_PHY_REF_CLKDIV2 BIT(24)
+ #define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25)
+
+#define PHY_R2 0x08
+ #define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0)
+ #define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6)
+ #define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12)
+ #define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18)
+
+#define PHY_R4 0x10
+ #define PHY_R4_PHY_CR_WRITE BIT(0)
+ #define PHY_R4_PHY_CR_READ BIT(1)
+ #define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2)
+ #define PHY_R4_PHY_CR_CAP_DATA BIT(18)
+ #define PHY_R4_PHY_CR_CAP_ADDR BIT(19)
+
+#define PHY_R5 0x14
+ #define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0)
+ #define PHY_R5_PHY_CR_ACK BIT(16)
+ #define PHY_R5_PHY_BS_OUT BIT(17)
+
+struct phy_g12a_usb3_pcie_priv {
+ struct regmap *regmap;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+#endif
+ struct reset_ctl_bulk resets;
+};
+
+static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv,
+ unsigned int addr)
+{
+ unsigned int val, reg;
+ int ret;
+
+ reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr);
+
+ regmap_write(priv->regmap, PHY_R4, reg);
+ regmap_write(priv->regmap, PHY_R4, reg);
+
+ regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR);
+
+ ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
+ (val & PHY_R5_PHY_CR_ACK),
+ 5, 1000);
+ if (ret)
+ return ret;
+
+ regmap_write(priv->regmap, PHY_R4, reg);
+
+ ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
+ !(val & PHY_R5_PHY_CR_ACK),
+ 5, 1000);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int
+phy_g12a_usb3_pcie_cr_bus_read(struct phy_g12a_usb3_pcie_priv *priv,
+ unsigned int addr, unsigned int *data)
+{
+ unsigned int val;
+ int ret;
+
+ ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
+ if (ret)
+ return ret;
+
+ regmap_write(priv->regmap, PHY_R4, 0);
+ regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ);
+
+ ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
+ (val & PHY_R5_PHY_CR_ACK),
+ 5, 1000);
+ if (ret)
+ return ret;
+
+ *data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val);
+
+ regmap_write(priv->regmap, PHY_R4, 0);
+
+ ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
+ !(val & PHY_R5_PHY_CR_ACK),
+ 5, 1000);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int
+phy_g12a_usb3_pcie_cr_bus_write(struct phy_g12a_usb3_pcie_priv *priv,
+ unsigned int addr, unsigned int data)
+{
+ unsigned int val, reg;
+ int ret;
+
+ ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
+ if (ret)
+ return ret;
+
+ reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data);
+
+ regmap_write(priv->regmap, PHY_R4, reg);
+ regmap_write(priv->regmap, PHY_R4, reg);
+
+ regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA);
+
+ ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
+ (val & PHY_R5_PHY_CR_ACK),
+ 5, 1000);
+ if (ret)
+ return ret;
+
+ regmap_write(priv->regmap, PHY_R4, reg);
+
+ ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
+ (val & PHY_R5_PHY_CR_ACK) == 0,
+ 5, 1000);
+ if (ret)
+ return ret;
+
+ regmap_write(priv->regmap, PHY_R4, reg);
+
+ regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE);
+
+ ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
+ (val & PHY_R5_PHY_CR_ACK),
+ 5, 1000);
+ if (ret)
+ return ret;
+
+ regmap_write(priv->regmap, PHY_R4, reg);
+
+ ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
+ (val & PHY_R5_PHY_CR_ACK) == 0,
+ 5, 1000);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int
+phy_g12a_usb3_pcie_cr_bus_update_bits(struct phy_g12a_usb3_pcie_priv *priv,
+ uint offset, uint mask, uint val)
+{
+ uint reg;
+ int ret;
+
+ ret = phy_g12a_usb3_pcie_cr_bus_read(priv, offset, ®);
+ if (ret)
+ return ret;
+
+ reg &= ~mask;
+
+ return phy_g12a_usb3_pcie_cr_bus_write(priv, offset, reg | val);
+}
+
+static int phy_meson_g12a_usb3_init(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
+ unsigned int data;
+ int ret;
+
+ /* TOFIX Handle PCIE mode */
+
+ ret = reset_assert_bulk(&priv->resets);
+ udelay(1);
+ ret |= reset_deassert_bulk(&priv->resets);
+ if (ret)
+ return ret;
+
+ /* Switch PHY to USB3 */
+ regmap_update_bits(priv->regmap, PHY_R0,
+ PHY_R0_PCIE_USB3_SWITCH,
+ PHY_R0_PCIE_USB3_SWITCH);
+
+ /*
+ * WORKAROUND: There is SSPHY suspend bug due to
+ * which USB enumerates
+ * in HS mode instead of SS mode. Workaround it by asserting
+ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
+ * mode
+ */
+ ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x102d,
+ BIT(7), BIT(7));
+ if (ret)
+ return ret;
+
+ ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x1010, 0xff0, 20);
+ if (ret)
+ return ret;
+
+ /*
+ * Fix RX Equalization setting as follows
+ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
+ * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
+ */
+ ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1006, &data);
+ if (ret)
+ return ret;
+
+ data &= ~BIT(6);
+ data |= BIT(7);
+ data &= ~(0x7 << 8);
+ data |= (0x3 << 8);
+ data |= (1 << 11);
+ ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1006, data);
+ if (ret)
+ return ret;
+
+ /*
+ * Set EQ and TX launch amplitudes as follows
+ * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
+ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
+ * LANE0.TX_OVRD_DRV_LO.EN set to 1.
+ */
+ ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1002, &data);
+ if (ret)
+ return ret;
+
+ data &= ~0x3f80;
+ data |= (0x16 << 7);
+ data &= ~0x7f;
+ data |= (0x7f | BIT(14));
+ ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1002, data);
+ if (ret)
+ return ret;
+
+ /*
+ * MPLL_LOOP_CTL.PROP_CNTRL = 8
+ */
+ ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x30,
+ 0xf << 4, 8 << 4);
+ if (ret)
+ return ret;
+
+ regmap_update_bits(priv->regmap, PHY_R2,
+ PHY_R2_PHY_TX_VBOOST_LVL,
+ FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
+
+ regmap_update_bits(priv->regmap, PHY_R1,
+ PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
+ FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
+ FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
+
+ return ret;
+}
+
+static int phy_meson_g12a_usb3_exit(struct phy *phy)
+{
+ struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
+
+ return reset_assert_bulk(&priv->resets);
+}
+
+struct phy_ops meson_g12a_usb3_pcie_phy_ops = {
+ .init = phy_meson_g12a_usb3_init,
+ .exit = phy_meson_g12a_usb3_exit,
+};
+
+int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)
+{
+ struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
+ if (ret)
+ return ret;
+
+ ret = reset_get_bulk(dev, &priv->resets);
+ if (ret == -ENOTSUPP)
+ return 0;
+ else if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ clk_free(&priv->clk);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id meson_g12a_usb3_pcie_phy_ids[] = {
+ { .compatible = "amlogic,g12a-usb3-pcie-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_g12a_usb3_pcie_phy) = {
+ .name = "meson_g12a_usb3_pcie_phy",
+ .id = UCLASS_PHY,
+ .of_match = meson_g12a_usb3_pcie_phy_ids,
+ .probe = meson_g12a_usb3_pcie_phy_probe,
+ .ops = &meson_g12a_usb3_pcie_phy_ops,
+ .priv_auto_alloc_size = sizeof(struct phy_g12a_usb3_pcie_priv),
+};
static const struct udevice_id imx8_pinctrl_match[] = {
{ .compatible = "fsl,imx8qxp-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info },
+ { .compatible = "fsl,imx8qm-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info },
{ /* sentinel */ }
};
ofnode node;
int ret;
+ if (!dev_of_valid(dev))
+ return 0;
+
dev_for_each_subnode(node, dev) {
if (pre_reloc_only &&
!ofnode_pre_reloc(node))
}
#endif
+static int
+pinctrl_gpio_get_pinctrl_and_offset(struct udevice *dev, unsigned offset,
+ struct udevice **pctldev,
+ unsigned int *pin_selector)
+{
+ struct ofnode_phandle_args args;
+ unsigned gpio_offset, pfc_base, pfc_pins;
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
+ 0, &args);
+ if (ret) {
+ dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL,
+ args.node, pctldev);
+ if (ret) {
+ dev_dbg(dev,
+ "%s: uclass_get_device_by_of_offset failed: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ gpio_offset = args.args[0];
+ pfc_base = args.args[1];
+ pfc_pins = args.args[2];
+
+ if (offset < gpio_offset || offset > gpio_offset + pfc_pins) {
+ dev_dbg(dev,
+ "%s: GPIO can not be mapped to pincontrol pin\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ offset -= gpio_offset;
+ offset += pfc_base;
+ *pin_selector = offset;
+
+ return 0;
+}
+
+/**
+ * pinctrl_gpio_request() - request a single pin to be used as GPIO
+ *
+ * @dev: GPIO peripheral device
+ * @offset: the GPIO pin offset from the GPIO controller
+ * @return: 0 on success, or negative error code on failure
+ */
+int pinctrl_gpio_request(struct udevice *dev, unsigned offset)
+{
+ const struct pinctrl_ops *ops;
+ struct udevice *pctldev;
+ unsigned int pin_selector;
+ int ret;
+
+ ret = pinctrl_gpio_get_pinctrl_and_offset(dev, offset,
+ &pctldev, &pin_selector);
+ if (ret)
+ return ret;
+
+ ops = pinctrl_get_ops(pctldev);
+ if (!ops || !ops->gpio_request_enable)
+ return -ENOTSUPP;
+
+ return ops->gpio_request_enable(pctldev, pin_selector);
+}
+
+/**
+ * pinctrl_gpio_free() - free a single pin used as GPIO
+ *
+ * @dev: GPIO peripheral device
+ * @offset: the GPIO pin offset from the GPIO controller
+ * @return: 0 on success, or negative error code on failure
+ */
+int pinctrl_gpio_free(struct udevice *dev, unsigned offset)
+{
+ const struct pinctrl_ops *ops;
+ struct udevice *pctldev;
+ unsigned int pin_selector;
+ int ret;
+
+ ret = pinctrl_gpio_get_pinctrl_and_offset(dev, offset,
+ &pctldev, &pin_selector);
+ if (ret)
+ return ret;
+
+ ops = pinctrl_get_ops(pctldev);
+ if (!ops || !ops->gpio_disable_free)
+ return -ENOTSUPP;
+
+ return ops->gpio_disable_free(pctldev, pin_selector);
+}
+
/**
* pinctrl_select_state_simple() - simple implementation of pinctrl_select_state
*
config PINCTRL_PFC
bool "Renesas pin control drivers"
depends on DM && ARCH_RMOBILE
+ default n if CPU_RZA1
help
Enable support for clock present on Renesas RCar SoCs.
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_PFC_R7S72100
+ bool "Renesas RZ/A1 R7S72100 pin control driver"
+ depends on CPU_RZA1
+ default y if CPU_RZA1
+ help
+ Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
endif
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
+obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * R7S72100 processor support
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#define P(bank) (0x0000 + (bank) * 4)
+#define PSR(bank) (0x0100 + (bank) * 4)
+#define PPR(bank) (0x0200 + (bank) * 4)
+#define PM(bank) (0x0300 + (bank) * 4)
+#define PMC(bank) (0x0400 + (bank) * 4)
+#define PFC(bank) (0x0500 + (bank) * 4)
+#define PFCE(bank) (0x0600 + (bank) * 4)
+#define PNOT(bank) (0x0700 + (bank) * 4)
+#define PMSR(bank) (0x0800 + (bank) * 4)
+#define PMCSR(bank) (0x0900 + (bank) * 4)
+#define PFCAE(bank) (0x0A00 + (bank) * 4)
+#define PIBC(bank) (0x4000 + (bank) * 4)
+#define PBDC(bank) (0x4100 + (bank) * 4)
+#define PIPC(bank) (0x4200 + (bank) * 4)
+
+#define RZA1_PINS_PER_PORT 16
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct r7s72100_pfc_platdata {
+ void __iomem *base;
+};
+
+static void r7s72100_pfc_set_function(struct udevice *dev, u16 bank, u16 line,
+ u16 func, u16 inbuf, u16 bidir)
+{
+ struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
+
+ clrsetbits_le16(plat->base + PFCAE(bank), BIT(line),
+ (func & BIT(2)) ? BIT(line) : 0);
+ clrsetbits_le16(plat->base + PFCE(bank), BIT(line),
+ (func & BIT(1)) ? BIT(line) : 0);
+ clrsetbits_le16(plat->base + PFC(bank), BIT(line),
+ (func & BIT(0)) ? BIT(line) : 0);
+
+ clrsetbits_le16(plat->base + PIBC(bank), BIT(line),
+ inbuf ? BIT(line) : 0);
+ clrsetbits_le16(plat->base + PBDC(bank), BIT(line),
+ bidir ? BIT(line) : 0);
+
+ setbits_le32(plat->base + PMCSR(bank), BIT(line + 16) | BIT(line));
+
+ setbits_le16(plat->base + PIPC(bank), BIT(line));
+}
+
+static int r7s72100_pfc_set_state(struct udevice *dev, struct udevice *config)
+{
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(config);
+ u32 cells[32];
+ u16 bank, line, func;
+ int i, count, bidir;
+
+ count = fdtdec_get_int_array_count(blob, node, "pinmux",
+ cells, ARRAY_SIZE(cells));
+ if (count < 0) {
+ printf("%s: bad pinmux array %d\n", __func__, count);
+ return -EINVAL;
+ }
+
+ if (count > ARRAY_SIZE(cells)) {
+ printf("%s: unsupported pinmux array count %d\n",
+ __func__, count);
+ return -EINVAL;
+ }
+
+ for (i = 0 ; i < count; i++) {
+ func = (cells[i] >> 16) & 0xf;
+ if (func == 0 || func > 8) {
+ printf("Invalid cell %i in node %s!\n",
+ count, ofnode_get_name(dev_ofnode(config)));
+ continue;
+ }
+
+ func = (func - 1) & 0x7;
+
+ bank = (cells[i] / RZA1_PINS_PER_PORT) & 0xff;
+ line = cells[i] % RZA1_PINS_PER_PORT;
+
+ bidir = 0;
+ if (bank == 3 && line == 3 && func == 1)
+ bidir = 1;
+
+ r7s72100_pfc_set_function(dev, bank, line, func, 0, bidir);
+ }
+
+ return 0;
+}
+
+const struct pinctrl_ops r7s72100_pfc_ops = {
+ .set_state = r7s72100_pfc_set_state,
+};
+
+static int r7s72100_pfc_probe(struct udevice *dev)
+{
+ struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
+ fdt_addr_t addr_base;
+ ofnode node;
+
+ addr_base = devfdt_get_addr(dev);
+ if (addr_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->base = (void __iomem *)addr_base;
+
+ dev_for_each_subnode(node, dev) {
+ struct udevice *cdev;
+
+ if (!ofnode_read_bool(node, "gpio-controller"))
+ continue;
+
+ device_bind_driver_to_node(dev, "r7s72100-gpio",
+ ofnode_get_name(node),
+ node, &cdev);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id r7s72100_pfc_match[] = {
+ { .compatible = "renesas,r7s72100-ports" },
+ {}
+};
+
+U_BOOT_DRIVER(r7s72100_pfc) = {
+ .name = "r7s72100_pfc",
+ .id = UCLASS_PINCTRL,
+ .of_match = r7s72100_pfc_match,
+ .probe = r7s72100_pfc_probe,
+ .platdata_auto_alloc_size = sizeof(struct r7s72100_pfc_platdata),
+ .ops = &r7s72100_pfc_ops,
+};
return priv->pfc.info->functions[selector].name;
}
-int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
+static int sh_pfc_gpio_request_enable(struct udevice *dev,
+ unsigned pin_selector)
{
struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
struct sh_pfc_pinctrl *pmx = &priv->pmx;
struct sh_pfc *pfc = &priv->pfc;
struct sh_pfc_pin_config *cfg;
const struct sh_pfc_pin *pin = NULL;
- int i, idx;
+ int i, ret, idx;
for (i = 1; i < pfc->info->nr_pins; i++) {
if (priv->pfc.info->pins[i].pin != pin_selector)
if (cfg->type != PINMUX_TYPE_NONE)
return -EBUSY;
- return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
+ ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
+ if (ret)
+ return ret;
+
+ cfg->type = PINMUX_TYPE_GPIO;
+
+ return 0;
+}
+
+static int sh_pfc_gpio_disable_free(struct udevice *dev,
+ unsigned pin_selector)
+{
+ struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
+ struct sh_pfc_pinctrl *pmx = &priv->pmx;
+ struct sh_pfc *pfc = &priv->pfc;
+ struct sh_pfc_pin_config *cfg;
+ const struct sh_pfc_pin *pin = NULL;
+ int i, idx;
+
+ for (i = 1; i < pfc->info->nr_pins; i++) {
+ if (priv->pfc.info->pins[i].pin != pin_selector)
+ continue;
+
+ pin = &priv->pfc.info->pins[i];
+ break;
+ }
+
+ if (!pin)
+ return -EINVAL;
+
+ idx = sh_pfc_get_pin_index(pfc, pin->pin);
+ cfg = &pmx->configs[idx];
+
+ cfg->type = PINMUX_TYPE_NONE;
+
+ return 0;
}
static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
.pinmux_set = sh_pfc_pinctrl_pin_set,
.pinmux_group_set = sh_pfc_pinctrl_group_set,
.set_state = pinctrl_generic_set_state,
+
+ .gpio_request_enable = sh_pfc_gpio_request_enable,
+ .gpio_disable_free = sh_pfc_gpio_disable_free,
};
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *bit);
-int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
#include "pinctrl-rockchip.h"
+static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3036_PULL_OFFSET 0x118
#define RK3036_PULL_PINS_PER_REG 16
#define RK3036_PULL_BANK_STRIDE 8
*bit = pin_num % RK3036_PULL_PINS_PER_REG;
};
+static int rk3036_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit;
+ u32 data;
+
+ if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
+ pull != PIN_CONFIG_BIAS_DISABLE)
+ return -ENOTSUPP;
+
+ rk3036_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ data = BIT(bit + 16);
+ if (pull == PIN_CONFIG_BIAS_DISABLE)
+ data |= BIT(bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
static struct rockchip_pin_bank rk3036_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
};
static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
- .pin_banks = rk3036_pin_banks,
- .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
- .label = "RK3036-GPIO",
- .type = RK3036,
- .grf_mux_offset = 0xa8,
- .pull_calc_reg = rk3036_calc_pull_reg_and_bit,
+ .pin_banks = rk3036_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
+ .grf_mux_offset = 0xa8,
+ .set_mux = rk3036_set_mux,
+ .set_pull = rk3036_set_pull,
};
static const struct udevice_id rk3036_pinctrl_ids[] = {
},
};
+static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data, route_reg, route_val;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+ if (bank->recalced_mask & BIT(pin))
+ rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+
+ if (bank->route_mask & BIT(pin)) {
+ if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+ &route_val)) {
+ ret = regmap_write(regmap, route_reg, route_val);
+ if (ret)
+ return ret;
+ }
+ }
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3128_PULL_OFFSET 0x118
#define RK3128_PULL_PINS_PER_REG 16
#define RK3128_PULL_BANK_STRIDE 8
*bit = pin_num % RK3128_PULL_PINS_PER_REG;
}
+static int rk3128_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit;
+ u32 data;
+
+ if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
+ pull != PIN_CONFIG_BIAS_DISABLE)
+ return -ENOTSUPP;
+
+ rk3128_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ data = BIT(bit + 16);
+ if (pull == PIN_CONFIG_BIAS_DISABLE)
+ data |= BIT(bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
static struct rockchip_pin_bank rk3128_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
- .label = "RK3128-GPIO",
- .type = RK3128,
.grf_mux_offset = 0xa8,
.iomux_recalced = rk3128_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
.iomux_routes = rk3128_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
- .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
+ .set_mux = rk3128_set_mux,
+ .set_pull = rk3128_set_pull,
};
static const struct udevice_id rk3128_pinctrl_ids[] = {
#include "pinctrl-rockchip.h"
+static int rk3188_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3188_PULL_OFFSET 0x164
#define RK3188_PULL_PMU_OFFSET 0x64
}
}
+static int rk3188_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3188_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
static struct rockchip_pin_bank rk3188_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
PIN_BANK(1, 32, "gpio1"),
};
static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
- .pin_banks = rk3188_pin_banks,
- .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
- .label = "RK3188-GPIO",
- .type = RK3188,
- .grf_mux_offset = 0x60,
- .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
+ .pin_banks = rk3188_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
+ .grf_mux_offset = 0x60,
+ .set_mux = rk3188_set_mux,
+ .set_pull = rk3188_set_pull,
};
static const struct udevice_id rk3188_pinctrl_ids[] = {
},
};
+static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data, route_reg, route_val;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+ if (bank->route_mask & BIT(pin)) {
+ if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+ &route_val)) {
+ ret = regmap_write(regmap, route_reg, route_val);
+ if (ret)
+ return ret;
+ }
+ }
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3228_PULL_OFFSET 0x100
static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
+static int rk3228_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3228_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3228_DRV_GRF_OFFSET 0x200
static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
+static int rk3228_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+ int type = bank->drv[pin_num / 8].drv_type;
+
+ rk3228_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ ret = rockchip_translate_drive_value(type, strength);
+ if (ret < 0) {
+ debug("unsupported driver strength %d\n", strength);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+ return ret;
+}
+
static struct rockchip_pin_bank rk3228_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
};
static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
- .pin_banks = rk3228_pin_banks,
- .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
- .label = "RK3228-GPIO",
- .type = RK3288,
- .grf_mux_offset = 0x0,
- .iomux_routes = rk3228_mux_route_data,
- .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
- .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
- .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
+ .pin_banks = rk3228_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
+ .grf_mux_offset = 0x0,
+ .iomux_routes = rk3228_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
+ .set_mux = rk3228_set_mux,
+ .set_pull = rk3228_set_pull,
+ .set_drive = rk3228_set_drive,
};
static const struct udevice_id rk3228_pinctrl_ids[] = {
#include <dm.h>
#include <dm/pinctrl.h>
#include <regmap.h>
-#include <syscon.h>
#include "pinctrl-rockchip.h"
},
};
+static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data, route_reg, route_val;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+ if (bank->route_mask & BIT(pin)) {
+ if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+ &route_val)) {
+ ret = regmap_write(regmap, route_reg, route_val);
+ if (ret)
+ return ret;
+ }
+ }
+
+ /* bank0 is special, there are no higher 16 bit writing bits. */
+ if (bank->bank_num == 0) {
+ regmap_read(regmap, reg, &data);
+ data &= ~(mask << bit);
+ } else {
+ /* enable the write to the equivalent lower bits */
+ data = (mask << (bit + 16));
+ }
+
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3288_PULL_OFFSET 0x140
#define RK3288_PULL_PMU_OFFSET 0x64
if (bank->bank_num == 0) {
*regmap = priv->regmap_pmu;
*reg = RK3288_PULL_PMU_OFFSET;
-
- *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
- *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3288_PULL_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
- *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+ }
+
+ *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
+ *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+}
+
+static int rk3288_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3288_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
- *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
- *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+ /* bank0 is special, there are no higher 16 bit writing bits */
+ if (bank->bank_num == 0) {
+ regmap_read(regmap, reg, &data);
+ data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
+ } else {
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
}
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
}
#define RK3288_DRV_PMU_OFFSET 0x70
if (bank->bank_num == 0) {
*regmap = priv->regmap_pmu;
*reg = RK3288_DRV_PMU_OFFSET;
-
- *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
- *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
- *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3288_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
- *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+ }
- *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
- *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+ *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+ *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
+ *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+}
+
+static int rk3288_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+ int type = bank->drv[pin_num / 8].drv_type;
+
+ rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ ret = rockchip_translate_drive_value(type, strength);
+ if (ret < 0) {
+ debug("unsupported driver strength %d\n", strength);
+ return ret;
+ }
+
+ /* bank0 is special, there are no higher 16 bit writing bits. */
+ if (bank->bank_num == 0) {
+ regmap_read(regmap, reg, &data);
+ data &= ~(((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << bit);
+ } else {
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
}
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+ return ret;
}
static struct rockchip_pin_bank rk3288_pin_banks[] = {
- PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
- IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
- IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
- IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
- IOMUX_UNROUTED,
- DRV_TYPE_WRITABLE_32BIT,
- DRV_TYPE_WRITABLE_32BIT,
- DRV_TYPE_WRITABLE_32BIT,
- 0,
- PULL_TYPE_WRITABLE_32BIT,
- PULL_TYPE_WRITABLE_32BIT,
- PULL_TYPE_WRITABLE_32BIT,
- 0
+ PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_UNROUTED
),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
IOMUX_UNROUTED,
};
static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
- .pin_banks = rk3288_pin_banks,
- .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
- .label = "RK3288-GPIO",
- .type = RK3288,
- .grf_mux_offset = 0x0,
- .pmu_mux_offset = 0x84,
- .iomux_routes = rk3288_mux_route_data,
- .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
- .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
- .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
+ .pin_banks = rk3288_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
+ .grf_mux_offset = 0x0,
+ .pmu_mux_offset = 0x84,
+ .iomux_routes = rk3288_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
+ .set_mux = rk3288_set_mux,
+ .set_pull = rk3288_set_pull,
+ .set_drive = rk3288_set_drive,
};
static const struct udevice_id rk3288_pinctrl_ids[] = {
},
};
+static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data, route_reg, route_val;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+ if (bank->recalced_mask & BIT(pin))
+ rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+
+ if (bank->route_mask & BIT(pin)) {
+ if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+ &route_val)) {
+ ret = regmap_write(regmap, route_reg, route_val);
+ if (ret)
+ return ret;
+ }
+ }
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3328_PULL_OFFSET 0x100
static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
+static int rk3328_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3328_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3328_DRV_GRF_OFFSET 0x200
static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
+static int rk3328_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+ int type = bank->drv[pin_num / 8].drv_type;
+
+ rk3328_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ ret = rockchip_translate_drive_value(type, strength);
+ if (ret < 0) {
+ debug("unsupported driver strength %d\n", strength);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3328_SCHMITT_BITS_PER_PIN 1
#define RK3328_SCHMITT_PINS_PER_REG 16
#define RK3328_SCHMITT_BANK_STRIDE 8
return 0;
}
+static int rk3328_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg;
+ u8 bit;
+ u32 data;
+
+ rk3328_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ /* enable the write to the equivalent lower bits */
+ data = BIT(bit + 16) | (enable << bit);
+
+ return regmap_write(regmap, reg, data);
+}
+
static struct rockchip_pin_bank rk3328_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
};
static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
- .pin_banks = rk3328_pin_banks,
- .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
- .label = "RK3328-GPIO",
- .type = RK3288,
- .grf_mux_offset = 0x0,
- .iomux_recalced = rk3328_mux_recalced_data,
- .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
- .iomux_routes = rk3328_mux_route_data,
- .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
- .pull_calc_reg = rk3328_calc_pull_reg_and_bit,
- .drv_calc_reg = rk3328_calc_drv_reg_and_bit,
- .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
+ .pin_banks = rk3328_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
+ .grf_mux_offset = 0x0,
+ .iomux_recalced = rk3328_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
+ .iomux_routes = rk3328_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
+ .set_mux = rk3328_set_mux,
+ .set_pull = rk3328_set_pull,
+ .set_drive = rk3328_set_drive,
+ .set_schmitt = rk3328_set_schmitt,
};
static const struct udevice_id rk3328_pinctrl_ids[] = {
#include "pinctrl-rockchip.h"
+static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3368_PULL_GRF_OFFSET 0x100
#define RK3368_PULL_PMU_OFFSET 0x10
if (bank->bank_num == 0) {
*regmap = priv->regmap_pmu;
*reg = RK3368_PULL_PMU_OFFSET;
-
- *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
- *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3368_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
- *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+ }
+
+ *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
- *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+ *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
+ *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+}
+
+static int rk3368_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3368_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
}
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
}
#define RK3368_DRV_PMU_OFFSET 0x20
if (bank->bank_num == 0) {
*regmap = priv->regmap_pmu;
*reg = RK3368_DRV_PMU_OFFSET;
-
- *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
- *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
- *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3368_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
- *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+ }
- *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
- *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+ *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+ *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
+ *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+}
+
+static int rk3368_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+ int type = bank->drv[pin_num / 8].drv_type;
+
+ rk3368_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ ret = rockchip_translate_drive_value(type, strength);
+ if (ret < 0) {
+ debug("unsupported driver strength %d\n", strength);
+ return ret;
}
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
}
static struct rockchip_pin_bank rk3368_pin_banks[] = {
};
static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
- .pin_banks = rk3368_pin_banks,
- .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
- .label = "RK3368-GPIO",
- .type = RK3368,
- .grf_mux_offset = 0x0,
- .pmu_mux_offset = 0x0,
- .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
- .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
+ .pin_banks = rk3368_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
+ .grf_mux_offset = 0x0,
+ .pmu_mux_offset = 0x0,
+ .set_mux = rk3368_set_mux,
+ .set_pull = rk3368_set_pull,
+ .set_drive = rk3368_set_drive,
};
static const struct udevice_id rk3368_pinctrl_ids[] = {
},
};
+static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data, route_reg, route_val;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+ if (bank->route_mask & BIT(pin)) {
+ if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+ &route_val)) {
+ ret = regmap_write(regmap, route_reg, route_val);
+ if (ret)
+ return ret;
+ }
+ }
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
*reg = RK3399_PULL_PMU_OFFSET;
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
-
- *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
- *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
} else {
*regmap = priv->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
- *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+ }
+
+ *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
+ *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+}
+
+static int rk3399_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
- *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
- *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
+ rk3399_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
}
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
}
static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = (pin_num % 8) * 2;
}
+static int rk3399_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data, rmask_bits, temp;
+ u8 bit;
+ int drv_type = bank->drv[pin_num / 8].drv_type;
+
+ rk3399_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ ret = rockchip_translate_drive_value(drv_type, strength);
+ if (ret < 0) {
+ debug("unsupported driver strength %d\n", strength);
+ return ret;
+ }
+
+ switch (drv_type) {
+ case DRV_TYPE_IO_1V8_3V0_AUTO:
+ case DRV_TYPE_IO_3V3_ONLY:
+ rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
+ switch (bit) {
+ case 0 ... 12:
+ /* regular case, nothing to do */
+ break;
+ case 15:
+ /*
+ * drive-strength offset is special, as it is spread
+ * over 2 registers, the bit data[15] contains bit 0
+ * of the value while temp[1:0] contains bits 2 and 1
+ */
+ data = (ret & 0x1) << 15;
+ temp = (ret >> 0x1) & 0x3;
+
+ data |= BIT(31);
+ ret = regmap_write(regmap, reg, data);
+ if (ret)
+ return ret;
+
+ temp |= (0x3 << 16);
+ reg += 0x4;
+ ret = regmap_write(regmap, reg, temp);
+
+ return ret;
+ case 18 ... 21:
+ /* setting fully enclosed in the second register */
+ reg += 4;
+ bit -= 16;
+ break;
+ default:
+ debug("unsupported bit: %d for pinctrl drive type: %d\n",
+ bit, drv_type);
+ return -EINVAL;
+ }
+ break;
+ case DRV_TYPE_IO_DEFAULT:
+ case DRV_TYPE_IO_1V8_OR_3V0:
+ case DRV_TYPE_IO_1V8_ONLY:
+ rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
+ break;
+ default:
+ debug("unsupported pinctrl drive type: %d\n",
+ drv_type);
+ return -EINVAL;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << rmask_bits) - 1) << (bit + 16);
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
static struct rockchip_pin_bank rk3399_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
IOMUX_SOURCE_PMU,
};
static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
- .pin_banks = rk3399_pin_banks,
- .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
- .label = "RK3399-GPIO",
- .type = RK3399,
- .grf_mux_offset = 0xe000,
- .pmu_mux_offset = 0x0,
- .grf_drv_offset = 0xe100,
- .pmu_drv_offset = 0x80,
- .iomux_routes = rk3399_mux_route_data,
- .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
- .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
- .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
+ .pin_banks = rk3399_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
+ .grf_mux_offset = 0xe000,
+ .pmu_mux_offset = 0x0,
+ .grf_drv_offset = 0xe100,
+ .pmu_drv_offset = 0x80,
+ .iomux_routes = rk3399_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
+ .set_mux = rk3399_set_mux,
+ .set_pull = rk3399_set_pull,
+ .set_drive = rk3399_set_drive,
};
static const struct udevice_id rk3399_pinctrl_ids[] = {
return 0;
}
-static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
- int *reg, u8 *bit, int *mask)
+void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
+ int *reg, u8 *bit, int *mask)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
*bit = data->bit;
}
-static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
- int mux, u32 *reg, u32 *value)
+bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
+ int mux, u32 *reg, u32 *value)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
return true;
}
-static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
+int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
{
int offset = 0;
static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
int iomux_num = (pin / 8);
- struct regmap *regmap;
- int reg, ret, mask, mux_type;
- u8 bit;
- u32 data, route_reg, route_val;
+ int ret;
ret = rockchip_verify_mux(bank, pin, mux);
if (ret < 0)
debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
- regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
- ? priv->regmap_pmu : priv->regmap_base;
+ if (!ctrl->set_mux)
+ return -ENOTSUPP;
- /* get basic quadrupel of mux registers and the correct reg inside */
- mux_type = bank->iomux[iomux_num].type;
- reg = bank->iomux[iomux_num].offset;
- reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
-
- if (bank->recalced_mask & BIT(pin))
- rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
-
- if (bank->route_mask & BIT(pin)) {
- if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
- &route_val)) {
- ret = regmap_write(regmap, route_reg, route_val);
- if (ret)
- return ret;
- }
- }
-
- if (mux_type & IOMUX_WRITABLE_32BIT) {
- regmap_read(regmap, reg, &data);
- data &= ~(mask << bit);
- } else {
- data = (mask << (bit + 16));
- }
-
- data |= (mux & mask) << bit;
- ret = regmap_write(regmap, reg, data);
+ ret = ctrl->set_mux(bank, pin, mux);
return ret;
}
{ 4, 7, 10, 13, 16, 19, 22, 26 }
};
-static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
- int pin_num, int strength)
+int rockchip_translate_drive_value(int type, int strength)
{
- struct rockchip_pinctrl_priv *priv = bank->priv;
- struct rockchip_pin_ctrl *ctrl = priv->ctrl;
- struct regmap *regmap;
- int reg, ret, i;
- u32 data, rmask_bits, temp;
- u8 bit;
- /* Where need to clean the special mask for rockchip_perpin_drv_list */
- int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK);
-
- debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
- pin_num, strength);
-
- ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
+ int i, ret;
ret = -EINVAL;
- for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
- if (rockchip_perpin_drv_list[drv_type][i] == strength) {
+ for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
+ if (rockchip_perpin_drv_list[type][i] == strength) {
ret = i;
break;
- } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
- ret = rockchip_perpin_drv_list[drv_type][i];
+ } else if (rockchip_perpin_drv_list[type][i] < 0) {
+ ret = rockchip_perpin_drv_list[type][i];
break;
}
}
- if (ret < 0) {
- debug("unsupported driver strength %d\n", strength);
- return ret;
- }
-
- switch (drv_type) {
- case DRV_TYPE_IO_1V8_3V0_AUTO:
- case DRV_TYPE_IO_3V3_ONLY:
- rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
- switch (bit) {
- case 0 ... 12:
- /* regular case, nothing to do */
- break;
- case 15:
- /*
- * drive-strength offset is special, as it is spread
- * over 2 registers, the bit data[15] contains bit 0
- * of the value while temp[1:0] contains bits 2 and 1
- */
- data = (ret & 0x1) << 15;
- temp = (ret >> 0x1) & 0x3;
-
- data |= BIT(31);
- ret = regmap_write(regmap, reg, data);
- if (ret)
- return ret;
+ return ret;
+}
- temp |= (0x3 << 16);
- reg += 0x4;
- ret = regmap_write(regmap, reg, temp);
+static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
- return ret;
- case 18 ... 21:
- /* setting fully enclosed in the second register */
- reg += 4;
- bit -= 16;
- break;
- default:
- debug("unsupported bit: %d for pinctrl drive type: %d\n",
- bit, drv_type);
- return -EINVAL;
- }
- break;
- case DRV_TYPE_IO_DEFAULT:
- case DRV_TYPE_IO_1V8_OR_3V0:
- case DRV_TYPE_IO_1V8_ONLY:
- rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
- break;
- default:
- debug("unsupported pinctrl drive type: %d\n",
- drv_type);
- return -EINVAL;
- }
+ debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
+ pin_num, strength);
- if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) {
- regmap_read(regmap, reg, &data);
- data &= ~(((1 << rmask_bits) - 1) << bit);
- } else {
- /* enable the write to the equivalent lower bits */
- data = ((1 << rmask_bits) - 1) << (bit + 16);
- }
+ if (!ctrl->set_drive)
+ return -ENOTSUPP;
- data |= (ret << bit);
- ret = regmap_write(regmap, reg, data);
- return ret;
+ return ctrl->set_drive(bank, pin_num, strength);
}
static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
},
};
+int rockchip_translate_pull_value(int type, int pull)
+{
+ int i, ret;
+
+ ret = -EINVAL;
+ for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
+ i++) {
+ if (rockchip_pull_list[type][i] == pull) {
+ ret = i;
+ break;
+ }
+ }
+
+ return ret;
+}
+
static int rockchip_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
- struct regmap *regmap;
- int reg, ret, i, pull_type;
- u8 bit;
- u32 data;
debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
pin_num, pull);
- ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
+ if (!ctrl->set_pull)
+ return -ENOTSUPP;
- switch (ctrl->type) {
- case RK3036:
- case RK3128:
- data = BIT(bit + 16);
- if (pull == PIN_CONFIG_BIAS_DISABLE)
- data |= BIT(bit);
- ret = regmap_write(regmap, reg, data);
- break;
- case RV1108:
- case RK3188:
- case RK3288:
- case RK3368:
- case RK3399:
- /*
- * Where need to clean the special mask for
- * rockchip_pull_list.
- */
- pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK);
- ret = -EINVAL;
- for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
- i++) {
- if (rockchip_pull_list[pull_type][i] == pull) {
- ret = i;
- break;
- }
- }
-
- if (ret < 0) {
- debug("unsupported pull setting %d\n", pull);
- return ret;
- }
-
- if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) {
- regmap_read(regmap, reg, &data);
- data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
- } else {
- /* enable the write to the equivalent lower bits */
- data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
- }
-
- data |= (ret << bit);
- ret = regmap_write(regmap, reg, data);
- break;
- default:
- debug("unsupported pinctrl type\n");
- return -EINVAL;
- }
-
- return ret;
+ return ctrl->set_pull(bank, pin_num, pull);
}
static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
{
struct rockchip_pinctrl_priv *priv = bank->priv;
struct rockchip_pin_ctrl *ctrl = priv->ctrl;
- struct regmap *regmap;
- int reg, ret;
- u8 bit;
- u32 data;
debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
pin_num, enable);
- ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
- if (ret)
- return ret;
-
- /* enable the write to the equivalent lower bits */
- data = BIT(bit + 16) | (enable << bit);
-
- return regmap_write(regmap, reg, data);
-}
-
-/*
- * Pinconf_ops handling
- */
-static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
- unsigned int pull)
-{
- switch (ctrl->type) {
- case RK3036:
- case RK3128:
- return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
- pull == PIN_CONFIG_BIAS_DISABLE);
- case RV1108:
- case RK3188:
- case RK3288:
- case RK3368:
- case RK3399:
- return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
- }
+ if (!ctrl->set_schmitt)
+ return -ENOTSUPP;
- return false;
+ return ctrl->set_schmitt(bank, pin_num, enable);
}
/* set the pin config settings for a specified pin */
static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
u32 pin, u32 param, u32 arg)
{
- struct rockchip_pinctrl_priv *priv = bank->priv;
- struct rockchip_pin_ctrl *ctrl = priv->ctrl;
int rc;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
- rc = rockchip_set_pull(bank, pin, param);
- if (rc)
- return rc;
- break;
-
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_BUS_HOLD:
- if (!rockchip_pinconf_pull_valid(ctrl, param))
- return -ENOTSUPP;
-
- if (!arg)
- return -EINVAL;
-
rc = rockchip_set_pull(bank, pin, param);
if (rc)
return rc;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
- if (!ctrl->drv_calc_reg)
- return -ENOTSUPP;
-
rc = rockchip_set_drive_perpin(bank, pin, arg);
if (rc < 0)
return rc;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (!ctrl->schmitt_calc_reg)
- return -ENOTSUPP;
-
rc = rockchip_set_schmitt(bank, pin, arg);
if (rc < 0)
return rc;
{ "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+ { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
- { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
- { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
};
#include <linux/types.h>
-enum rockchip_pinctrl_type {
- RV1108,
- RK3036,
- RK3128,
- RK3188,
- RK3288,
- RK3368,
- RK3399,
-};
-
/**
* Encode variants of iomux registers into a type variable
*/
#define IOMUX_SOURCE_PMU BIT(2)
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
-#define IOMUX_WRITABLE_32BIT BIT(5)
/**
* Defined some common pins constants
int offset;
};
-#define DRV_TYPE_IO_MASK GENMASK(31, 16)
-#define DRV_TYPE_WRITABLE_32BIT BIT(31)
-
/**
* enum type index corresponding to rockchip_perpin_drv_list arrays index.
*/
DRV_TYPE_MAX
};
-#define PULL_TYPE_IO_MASK GENMASK(31, 16)
-#define PULL_TYPE_WRITABLE_32BIT BIT(31)
-
/**
* enum type index corresponding to rockchip_pull_list arrays index.
*/
}, \
}
-#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \
- iom2, iom3, drv0, drv1, drv2, \
- drv3, pull0, pull1, pull2, \
- pull3) \
- { \
- .bank_num = id, \
- .nr_pins = pins, \
- .name = label, \
- .iomux = { \
- { .type = iom0, .offset = -1 }, \
- { .type = iom1, .offset = -1 }, \
- { .type = iom2, .offset = -1 }, \
- { .type = iom3, .offset = -1 }, \
- }, \
- .drv = { \
- { .drv_type = drv0, .offset = -1 }, \
- { .drv_type = drv1, .offset = -1 }, \
- { .drv_type = drv2, .offset = -1 }, \
- { .drv_type = drv3, .offset = -1 }, \
- }, \
- .pull_type[0] = pull0, \
- .pull_type[1] = pull1, \
- .pull_type[2] = pull2, \
- .pull_type[3] = pull3, \
- }
-
#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
label, iom0, iom1, iom2, \
iom3, drv0, drv1, drv2, \
struct rockchip_pin_bank *pin_banks;
u32 nr_banks;
u32 nr_pins;
- char *label;
- enum rockchip_pinctrl_type type;
int grf_mux_offset;
int pmu_mux_offset;
int grf_drv_offset;
struct rockchip_mux_route_data *iomux_routes;
u32 niomux_routes;
- void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
- int pin_num, struct regmap **regmap,
- int *reg, u8 *bit);
- void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
- int pin_num, struct regmap **regmap,
- int *reg, u8 *bit);
- int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
- int pin_num, struct regmap **regmap,
- int *reg, u8 *bit);
+ int (*set_mux)(struct rockchip_pin_bank *bank,
+ int pin, int mux);
+ int (*set_pull)(struct rockchip_pin_bank *bank,
+ int pin_num, int pull);
+ int (*set_drive)(struct rockchip_pin_bank *bank,
+ int pin_num, int strength);
+ int (*set_schmitt)(struct rockchip_pin_bank *bank,
+ int pin_num, int enable);
};
/**
extern const struct pinctrl_ops rockchip_pinctrl_ops;
int rockchip_pinctrl_probe(struct udevice *dev);
+void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
+ int *reg, u8 *bit, int *mask);
+bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
+ int mux, u32 *reg, u32 *value);
+int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask);
+int rockchip_translate_drive_value(int type, int strength);
+int rockchip_translate_pull_value(int type, int pull);
#endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */
},
};
+static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+ if (bank->recalced_mask & BIT(pin))
+ rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RV1108_PULL_PMU_OFFSET 0x10
#define RV1108_PULL_OFFSET 0x110
*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
}
+static int rv1108_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rv1108_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RV1108_DRV_PMU_OFFSET 0x20
#define RV1108_DRV_GRF_OFFSET 0x210
*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
}
+static int rv1108_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+ int type = bank->drv[pin_num / 8].drv_type;
+
+ rv1108_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ ret = rockchip_translate_drive_value(type, strength);
+ if (ret < 0) {
+ debug("unsupported driver strength %d\n", strength);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+ return ret;
+}
+
#define RV1108_SCHMITT_PMU_OFFSET 0x30
#define RV1108_SCHMITT_GRF_OFFSET 0x388
#define RV1108_SCHMITT_BANK_STRIDE 8
return 0;
}
+static int rv1108_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg;
+ u8 bit;
+ u32 data;
+
+ rv1108_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ /* enable the write to the equivalent lower bits */
+ data = BIT(bit + 16) | (enable << bit);
+
+ return regmap_write(regmap, reg, data);
+}
+
static struct rockchip_pin_bank rv1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks = rv1108_pin_banks,
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
- .label = "RV1108-GPIO",
- .type = RV1108,
.grf_mux_offset = 0x10,
.pmu_mux_offset = 0x0,
.iomux_recalced = rv1108_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
- .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
- .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
- .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
+ .set_mux = rv1108_set_mux,
+ .set_pull = rv1108_set_pull,
+ .set_drive = rv1108_set_drive,
+ .set_schmitt = rv1108_set_schmitt,
};
static const struct udevice_id rv1108_pinctrl_ids[] = {
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/pwm.h>
+#include <asm/arch-rockchip/pwm.h>
#include <power/regulator.h>
struct rk_pwm_priv {
#
# QUICC Engine Drivers
#
+config QE
+ bool "Enable support for QUICC Engine"
+ depends on PPC
+ default y if ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || ARCH_P1021 \
+ || ARCH_P1025
+ help
+ Chose this option to add support for the QUICC Engine.
+
config U_QE
bool "Enable support for U QUICC Engine"
default y if (ARCH_LS1021A && !SD_BOOT && !NAND_BOOT && !QSPI_BOOT) \
|| (TARGET_LS1043ARDB && !SPL_NO_QE && !NAND_BOOT && !QSPI_BOOT)
help
Choose this option to add support for U QUICC Engine.
+
+choice
+ prompt "QUICC Engine FMan ethernet firmware location"
+ depends on FMAN_ENET || QE
+ default SYS_QE_FMAN_FW_IN_ROM
+
+config SYS_QE_FMAN_FW_IN_NOR
+ bool "NOR flash"
+
+config SYS_QE_FMAN_FW_IN_NAND
+ bool "NAND flash"
+
+config SYS_QE_FMAN_FW_IN_SPIFLASH
+ bool "SPI flash"
+
+config SYS_QE_FMAN_FW_IN_MMC
+ bool "MMC"
+
+config SYS_QE_FMAN_FW_IN_REMOTE
+ bool "Remote memory location (PCI)"
+
+config SYS_QE_FMAN_FW_IN_ROM
+ bool "Firmware is already in ROM"
+
+endchoice
*/
static u8 thread_snum[] = {
/* Evthreads 16-29 are not supported in MPC8309 */
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
switch (odt_rd_cfg) {
case ODT_RD_ONLY_OTHER_DIMM:
- if (!IS_ENABLED(CONFIG_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
case ODT_RD_NEVER:
case ODT_RD_ONLY_CURRENT:
case ODT_RD_ONLY_OTHER_CS:
- if (!IS_ENABLED(CONFIG_MPC830x) &&
- !IS_ENABLED(CONFIG_MPC831x) &&
- !IS_ENABLED(CONFIG_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
switch (odt_wr_cfg) {
case ODT_WR_ONLY_OTHER_DIMM:
- if (!IS_ENABLED(CONFIG_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;
case ODT_WR_NEVER:
case ODT_WR_ONLY_CURRENT:
case ODT_WR_ONLY_OTHER_CS:
- if (!IS_ENABLED(CONFIG_MPC830x) &&
- !IS_ENABLED(CONFIG_MPC831x) &&
- !IS_ENABLED(CONFIG_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3368.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/ddr_rk3368.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3368.h>
+#include <asm/arch-rockchip/grf_rk3368.h>
+#include <asm/arch-rockchip/ddr_rk3368.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/arch-rockchip/sdram_common.h>
struct dram_info {
struct ram_info info;
move_to_access_state(pctl);
/* TODO(prt): could detect rank in training... */
+#ifdef CONFIG_TARGET_EVB_PX5
+ params->chan.rank = 1;
+#else
params->chan.rank = 2;
+#endif
/* TODO(prt): bus width is not auto-detected (yet)... */
params->chan.bw = 2; /* 32bit wide bus */
params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
#include <dm.h>
#include <ram.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3128.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3128.h>
+#include <asm/arch-rockchip/sdram_common.h>
struct dram_info {
struct ram_info info;
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3188.h>
-#include <asm/arch/ddr_rk3188.h>
-#include <asm/arch/grf_rk3188.h>
-#include <asm/arch/pmu_rk3188.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3188.h>
+#include <asm/arch-rockchip/ddr_rk3188.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
+#include <asm/arch-rockchip/pmu_rk3188.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/arch-rockchip/sdram_common.h>
#include <linux/err.h>
struct chan_info {
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk322x.h>
-#include <asm/arch/grf_rk322x.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sdram_rk322x.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/uart.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk322x.h>
+#include <asm/arch-rockchip/grf_rk322x.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/sdram_rk322x.h>
+#include <asm/arch-rockchip/timer.h>
+#include <asm/arch-rockchip/uart.h>
+#include <asm/arch-rockchip/sdram_common.h>
#include <asm/types.h>
#include <linux/err.h>
struct regmap *map;
};
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
/*
* [7:6] bank(n:n bit bank)
* [5:4] row(13+n)
return 0;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_TPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_platdata(struct udevice *dev)
static int rk322x_dmc_probe(struct udevice *dev)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
struct rk322x_sdram_params *plat = dev_get_platdata(dev);
int ret;
struct udevice *dev_clk;
struct dram_info *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_platdata(dev);
if (ret)
.id = UCLASS_RAM,
.of_match = rk322x_dmc_ids,
.ops = &rk322x_dmc_ops,
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
.ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata,
#endif
.probe = rk322x_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_TPL_BUILD
.platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params),
#endif
};
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/ddr_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/ddr_rk3288.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/pmu_rk3288.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/arch-rockchip/sdram_common.h>
#include <linux/err.h>
#include <power/regulator.h>
#include <power/rk8xx_pmic.h>
#include <dm.h>
#include <ram.h>
#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3328.h>
-#include <asm/arch/sdram_common.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3328.h>
+#include <asm/arch-rockchip/sdram_common.h>
struct dram_info {
struct ram_info info;
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sdram_common.h>
-#include <asm/arch/sdram_rk3399.h>
-#include <asm/arch/cru_rk3399.h>
-#include <asm/arch/grf_rk3399.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_rk3399.h>
+#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
#include <linux/err.h>
#include <time.h>
};
struct dram_info {
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
struct chan_info chan[2];
struct clk ddr_clk;
struct rk3399_cru *cru;
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
struct rockchip_dmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int rk3399_dmc_probe(struct udevice *dev)
{
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
if (rk3399_dmc_init(dev))
return 0;
#else
.id = UCLASS_RAM,
.of_match = rk3399_dmc_ids,
.ops = &rk3399_dmc_ops,
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
.ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
#endif
.probe = rk3399_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_TPL_BUILD) || \
+ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
.platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
#endif
};
family: support for LPDDR2, LPDDR3 and DDR3
the SDRAM parameters for controleur and phy need to be provided
in device tree (computed by DDR tuning tools)
+
+config STM32MP1_DDR_INTERACTIVE
+ bool "STM32MP1 DDR driver : interactive support"
+ depends on STM32MP1_DDR
+ help
+ activate interactive support in STM32MP1 DDR controller driver
+ used for DDR tuning tools
+ to enter in intercative mode type 'd' during SPL DDR driver
+ initialisation
+
+config STM32MP1_DDR_INTERACTIVE_FORCE
+ bool "STM32MP1 DDR driver : force interactive mode"
+ depends on STM32MP1_DDR_INTERACTIVE
+ default n
+ help
+ force interactive mode in STM32MP1 DDR controller driver
+ skip the polling of character 'd' in console
+ useful when SPL is loaded in sysram
+ directly by programmer
+
+config STM32MP1_DDR_TESTS
+ bool "STM32MP1 DDR driver : tests support"
+ depends on STM32MP1_DDR_INTERACTIVE
+ default y
+ help
+ activate test support for interactive support in
+ STM32MP1 DDR controller driver: command test
+
+config STM32MP1_DDR_TUNING
+ bool "STM32MP1 DDR driver : support of tuning"
+ depends on STM32MP1_DDR_INTERACTIVE
+ default y
+ help
+ activate tuning command in STM32MP1 DDR interactive mode
+ used for DDR tuning tools
+ - DQ Deskew algorithm
+ - DQS Trimming
obj-y += stm32mp1_ram.o
obj-y += stm32mp1_ddr.o
+
+obj-$(CONFIG_STM32MP1_DDR_INTERACTIVE) += stm32mp1_interactive.o
+obj-$(CONFIG_STM32MP1_DDR_TESTS) += stm32mp1_tests.o
+obj-$(CONFIG_STM32MP1_DDR_TUNING) += stm32mp1_tuning.o
+
+ifneq ($(DDR_INTERACTIVE),)
+CFLAGS_stm32mp1_interactive.o += -DCONFIG_STM32MP1_DDR_INTERACTIVE_FORCE=y
+endif
offsetof(struct stm32mp1_ddrphy, x),\
offsetof(struct y, x)}
+#define DDR_REG_DYN(x) \
+ {#x,\
+ offsetof(struct stm32mp1_ddrctl, x),\
+ INVALID_OFFSET}
+
+#define DDRPHY_REG_DYN(x) \
+ {#x,\
+ offsetof(struct stm32mp1_ddrphy, x),\
+ INVALID_OFFSET}
+
+/***********************************************************
+ * PARAMETERS: value get from device tree :
+ * size / order need to be aligned with binding
+ * modification NOT ALLOWED !!!
+ ***********************************************************/
+#define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */
+#define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */
+#define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */
+#define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */
+
+#define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
+#define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
+#define DDRPHY_REG_CAL_SIZE 12 /* st,phy-cal */
+
#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
-static const struct reg_desc ddr_reg[] = {
+static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
DDRCTL_REG_REG(mstr),
DDRCTL_REG_REG(mrctrl0),
DDRCTL_REG_REG(mrctrl1),
};
#define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
-static const struct reg_desc ddr_timing[] = {
+static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
DDRCTL_REG_TIMING(rfshtmg),
DDRCTL_REG_TIMING(dramtmg0),
DDRCTL_REG_TIMING(dramtmg1),
};
#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map)
-static const struct reg_desc ddr_map[] = {
+static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
DDRCTL_REG_MAP(addrmap1),
DDRCTL_REG_MAP(addrmap2),
DDRCTL_REG_MAP(addrmap3),
};
#define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
-static const struct reg_desc ddr_perf[] = {
+static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
DDRCTL_REG_PERF(sched),
DDRCTL_REG_PERF(sched1),
DDRCTL_REG_PERF(perfhpr1),
};
#define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
-static const struct reg_desc ddrphy_reg[] = {
+static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
DDRPHY_REG_REG(pgcr),
DDRPHY_REG_REG(aciocr),
DDRPHY_REG_REG(dxccr),
};
#define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
-static const struct reg_desc ddrphy_timing[] = {
+static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
DDRPHY_REG_TIMING(ptr0),
DDRPHY_REG_TIMING(ptr1),
DDRPHY_REG_TIMING(ptr2),
};
#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
-static const struct reg_desc ddrphy_cal[] = {
+static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = {
DDRPHY_REG_CAL(dx0dllcr),
DDRPHY_REG_CAL(dx0dqtr),
DDRPHY_REG_CAL(dx0dqstr),
DDRPHY_REG_CAL(dx3dqstr),
};
+/**************************************************************
+ * DYNAMIC REGISTERS: only used for debug purpose (read/modify)
+ **************************************************************/
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
+static const struct reg_desc ddr_dyn[] = {
+ DDR_REG_DYN(stat),
+ DDR_REG_DYN(init0),
+ DDR_REG_DYN(dfimisc),
+ DDR_REG_DYN(dfistat),
+ DDR_REG_DYN(swctl),
+ DDR_REG_DYN(swstat),
+ DDR_REG_DYN(pctrl_0),
+ DDR_REG_DYN(pctrl_1),
+};
+
+#define DDR_REG_DYN_SIZE ARRAY_SIZE(ddr_dyn)
+
+static const struct reg_desc ddrphy_dyn[] = {
+ DDRPHY_REG_DYN(pir),
+ DDRPHY_REG_DYN(pgsr),
+ DDRPHY_REG_DYN(zq0sr0),
+ DDRPHY_REG_DYN(zq0sr1),
+ DDRPHY_REG_DYN(dx0gsr0),
+ DDRPHY_REG_DYN(dx0gsr1),
+ DDRPHY_REG_DYN(dx1gsr0),
+ DDRPHY_REG_DYN(dx1gsr1),
+ DDRPHY_REG_DYN(dx2gsr0),
+ DDRPHY_REG_DYN(dx2gsr1),
+ DDRPHY_REG_DYN(dx3gsr0),
+ DDRPHY_REG_DYN(dx3gsr1),
+};
+
+#define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn)
+
+#endif
+
+/*****************************************************************
+ * REGISTERS ARRAY: used to parse device tree and interactive mode
+ *****************************************************************/
enum reg_type {
REG_REG,
REG_TIMING,
REGPHY_REG,
REGPHY_TIMING,
REGPHY_CAL,
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
+/* dynamic registers => managed in driver or not changed,
+ * can be dumped in interactive mode
+ */
+ REG_DYN,
+ REGPHY_DYN,
+#endif
REG_TYPE_NB
};
const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
[REG_REG] = {
- "static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE},
+ "static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
[REG_TIMING] = {
- "timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE},
+ "timing", ddr_timing, DDRCTL_REG_TIMING_SIZE, DDR_BASE},
[REG_PERF] = {
- "perf", ddr_perf, ARRAY_SIZE(ddr_perf), DDR_BASE},
+ "perf", ddr_perf, DDRCTL_REG_PERF_SIZE, DDR_BASE},
[REG_MAP] = {
- "map", ddr_map, ARRAY_SIZE(ddr_map), DDR_BASE},
+ "map", ddr_map, DDRCTL_REG_MAP_SIZE, DDR_BASE},
[REGPHY_REG] = {
- "static", ddrphy_reg, ARRAY_SIZE(ddrphy_reg), DDRPHY_BASE},
+ "static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
[REGPHY_TIMING] = {
- "timing", ddrphy_timing, ARRAY_SIZE(ddrphy_timing), DDRPHY_BASE},
+ "timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
[REGPHY_CAL] = {
- "cal", ddrphy_cal, ARRAY_SIZE(ddrphy_cal), DDRPHY_BASE},
+ "cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE},
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
+[REG_DYN] = {
+ "dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
+[REGPHY_DYN] = {
+ "dyn", ddrphy_dyn, DDRPHY_REG_DYN_SIZE, DDRPHY_BASE},
+#endif
+
};
const char *base_name[] = {
}
}
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
+static void stm32mp1_dump_reg_desc(u32 base_addr, const struct reg_desc *desc)
+{
+ unsigned int *ptr;
+
+ ptr = (unsigned int *)(base_addr + desc->offset);
+ printf("%s= 0x%08x\n", desc->name, readl(ptr));
+}
+
+static void stm32mp1_dump_param_desc(u32 par_addr, const struct reg_desc *desc)
+{
+ unsigned int *ptr;
+
+ ptr = (unsigned int *)(par_addr + desc->par_offset);
+ printf("%s= 0x%08x\n", desc->name, readl(ptr));
+}
+
+static const struct reg_desc *found_reg(const char *name, enum reg_type *type)
+{
+ unsigned int i, j;
+ const struct reg_desc *desc;
+
+ for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
+ desc = ddr_registers[i].desc;
+ for (j = 0; j < ddr_registers[i].size; j++) {
+ if (strcmp(name, desc[j].name) == 0) {
+ *type = i;
+ return &desc[j];
+ }
+ }
+ }
+ *type = REG_TYPE_NB;
+ return NULL;
+}
+
+int stm32mp1_dump_reg(const struct ddr_info *priv,
+ const char *name)
+{
+ unsigned int i, j;
+ const struct reg_desc *desc;
+ u32 base_addr;
+ enum base_type p_base;
+ enum reg_type type;
+ const char *p_name;
+ enum base_type filter = NONE_BASE;
+ int result = -1;
+
+ if (name) {
+ if (strcmp(name, base_name[DDR_BASE]) == 0)
+ filter = DDR_BASE;
+ else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
+ filter = DDRPHY_BASE;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
+ p_base = ddr_registers[i].base;
+ p_name = ddr_registers[i].name;
+ if (!name || (filter == p_base || !strcmp(name, p_name))) {
+ result = 0;
+ desc = ddr_registers[i].desc;
+ base_addr = get_base_addr(priv, p_base);
+ printf("==%s.%s==\n", base_name[p_base], p_name);
+ for (j = 0; j < ddr_registers[i].size; j++)
+ stm32mp1_dump_reg_desc(base_addr, &desc[j]);
+ }
+ }
+ if (result) {
+ desc = found_reg(name, &type);
+ if (desc) {
+ p_base = ddr_registers[type].base;
+ base_addr = get_base_addr(priv, p_base);
+ stm32mp1_dump_reg_desc(base_addr, desc);
+ result = 0;
+ }
+ }
+ return result;
+}
+
+void stm32mp1_edit_reg(const struct ddr_info *priv,
+ char *name, char *string)
+{
+ unsigned long *ptr, value;
+ enum reg_type type;
+ enum base_type base;
+ const struct reg_desc *desc;
+ u32 base_addr;
+
+ desc = found_reg(name, &type);
+
+ if (!desc) {
+ printf("%s not found\n", name);
+ return;
+ }
+ if (strict_strtoul(string, 16, &value) < 0) {
+ printf("invalid value %s\n", string);
+ return;
+ }
+ base = ddr_registers[type].base;
+ base_addr = get_base_addr(priv, base);
+ ptr = (unsigned long *)(base_addr + desc->offset);
+ writel(value, ptr);
+ printf("%s= 0x%08x\n", desc->name, readl(ptr));
+}
+
+static u32 get_par_addr(const struct stm32mp1_ddr_config *config,
+ enum reg_type type)
+{
+ u32 par_addr = 0x0;
+
+ switch (type) {
+ case REG_REG:
+ par_addr = (u32)&config->c_reg;
+ break;
+ case REG_TIMING:
+ par_addr = (u32)&config->c_timing;
+ break;
+ case REG_PERF:
+ par_addr = (u32)&config->c_perf;
+ break;
+ case REG_MAP:
+ par_addr = (u32)&config->c_map;
+ break;
+ case REGPHY_REG:
+ par_addr = (u32)&config->p_reg;
+ break;
+ case REGPHY_TIMING:
+ par_addr = (u32)&config->p_timing;
+ break;
+ case REGPHY_CAL:
+ par_addr = (u32)&config->p_cal;
+ break;
+ case REG_DYN:
+ case REGPHY_DYN:
+ case REG_TYPE_NB:
+ par_addr = (u32)NULL;
+ break;
+ }
+
+ return par_addr;
+}
+
+int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
+ const char *name)
+{
+ unsigned int i, j;
+ const struct reg_desc *desc;
+ u32 par_addr;
+ enum base_type p_base;
+ enum reg_type type;
+ const char *p_name;
+ enum base_type filter = NONE_BASE;
+ int result = -EINVAL;
+
+ if (name) {
+ if (strcmp(name, base_name[DDR_BASE]) == 0)
+ filter = DDR_BASE;
+ else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
+ filter = DDRPHY_BASE;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
+ par_addr = get_par_addr(config, i);
+ if (!par_addr)
+ continue;
+ p_base = ddr_registers[i].base;
+ p_name = ddr_registers[i].name;
+ if (!name || (filter == p_base || !strcmp(name, p_name))) {
+ result = 0;
+ desc = ddr_registers[i].desc;
+ printf("==%s.%s==\n", base_name[p_base], p_name);
+ for (j = 0; j < ddr_registers[i].size; j++)
+ stm32mp1_dump_param_desc(par_addr, &desc[j]);
+ }
+ }
+ if (result) {
+ desc = found_reg(name, &type);
+ if (desc) {
+ par_addr = get_par_addr(config, type);
+ if (par_addr) {
+ stm32mp1_dump_param_desc(par_addr, desc);
+ result = 0;
+ }
+ }
+ }
+ return result;
+}
+
+void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
+ char *name, char *string)
+{
+ unsigned long *ptr, value;
+ enum reg_type type;
+ const struct reg_desc *desc;
+ u32 par_addr;
+
+ desc = found_reg(name, &type);
+ if (!desc) {
+ printf("%s not found\n", name);
+ return;
+ }
+ if (strict_strtoul(string, 16, &value) < 0) {
+ printf("invalid value %s\n", string);
+ return;
+ }
+ par_addr = get_par_addr(config, type);
+ if (!par_addr) {
+ printf("no parameter %s\n", name);
+ return;
+ }
+ ptr = (unsigned long *)(par_addr + desc->par_offset);
+ writel(value, ptr);
+ printf("%s= 0x%08x\n", desc->name, readl(ptr));
+}
+#endif
+
+__weak bool stm32mp1_ddr_interactive(void *priv,
+ enum stm32mp1_ddr_interact_step step,
+ const struct stm32mp1_ddr_config *config)
+{
+ return false;
+}
+
+#define INTERACTIVE(step)\
+ stm32mp1_ddr_interactive(priv, step, config)
+
static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
{
u32 pgsr;
/* self-refresh due to software => check also STAT.selfref_type */
if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
- stat |= DDRCTRL_STAT_SELFREF_TYPE_SR;
+ val |= DDRCTRL_STAT_SELFREF_TYPE_SR;
} else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
/* normal mode: handle also automatic self refresh */
mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
}
/* board-specific DDR power initializations. */
-__weak int board_ddr_power_init(void)
+__weak int board_ddr_power_init(enum ddr_type ddr_type)
{
return 0;
}
const struct stm32mp1_ddr_config *config)
{
u32 pir;
- int ret;
+ int ret = -EINVAL;
- ret = board_ddr_power_init();
+ if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
+ ret = board_ddr_power_init(STM32MP_DDR3);
+ else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2)
+ ret = board_ddr_power_init(STM32MP_LPDDR2);
+ else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3)
+ ret = board_ddr_power_init(STM32MP_LPDDR3);
if (ret)
panic("ddr power init failed\n");
+start:
debug("name = %s\n", config->info.name);
- debug("speed = %d MHz\n", config->info.speed);
+ debug("speed = %d kHz\n", config->info.speed);
debug("size = 0x%x\n", config->info.size);
/*
* 1. Program the DWC_ddr_umctl2 registers
/* 1.2. start CLOCK */
if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
- panic("invalid DRAM clock : %d MHz\n",
+ panic("invalid DRAM clock : %d kHz\n",
config->info.speed);
/* 1.3. deassert reset */
*/
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
-/* 1.4. wait 4 cycles for synchronization */
- asm(" nop");
- asm(" nop");
- asm(" nop");
- asm(" nop");
+/* 1.4. wait 128 cycles to permit initialization of end logic */
+ udelay(2);
+ /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
+
+ if (INTERACTIVE(STEP_DDR_RESET))
+ goto start;
/* 1.5. initialize registers ddr_umctl2 */
/* Stop uMCTL2 before PHY is ready */
set_reg(priv, REG_PERF, &config->c_perf);
+ if (INTERACTIVE(STEP_CTL_INIT))
+ goto start;
+
/* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
set_reg(priv, REGPHY_TIMING, &config->p_timing);
set_reg(priv, REGPHY_CAL, &config->p_cal);
+ if (INTERACTIVE(STEP_PHY_INIT))
+ goto start;
+
/* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE
* Perform DDR PHY DRAM initialization and Gate Training Evaluation
*/
/* enable uMCTL2 AXI port 0 and 1 */
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
+
+ if (INTERACTIVE(STEP_DDR_READY))
+ goto start;
}
struct stm32mp1_ddr_info {
const char *name;
- u16 speed; /* in MHZ */
+ u32 speed; /* in kHZ */
u32 size; /* memory size in byte = col * row * width */
};
struct stm32mp1_ddrphy_cal p_cal;
};
-int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed);
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
/* DDRCTRL REGISTERS */
#define DDRCTRL_MSTR_DDR3 BIT(0)
+#define DDRCTRL_MSTR_LPDDR2 BIT(2)
+#define DDRCTRL_MSTR_LPDDR3 BIT(3)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12)
#define DDRPHYC_DXNGCR_DXEN BIT(0)
+#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30)
#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)
#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <console.h>
+#include <cli.h>
+#include <clk.h>
+#include <malloc.h>
+#include <ram.h>
+#include <reset.h>
+#include "stm32mp1_ddr.h"
+#include "stm32mp1_tests.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ddr_command {
+ DDR_CMD_HELP,
+ DDR_CMD_INFO,
+ DDR_CMD_FREQ,
+ DDR_CMD_RESET,
+ DDR_CMD_PARAM,
+ DDR_CMD_PRINT,
+ DDR_CMD_EDIT,
+ DDR_CMD_STEP,
+ DDR_CMD_NEXT,
+ DDR_CMD_GO,
+ DDR_CMD_TEST,
+ DDR_CMD_TUNING,
+ DDR_CMD_UNKNOWN,
+};
+
+const char *step_str[] = {
+ [STEP_DDR_RESET] = "DDR_RESET",
+ [STEP_CTL_INIT] = "DDR_CTRL_INIT_DONE",
+ [STEP_PHY_INIT] = "DDR PHY_INIT_DONE",
+ [STEP_DDR_READY] = "DDR_READY",
+ [STEP_RUN] = "RUN"
+};
+
+enum ddr_command stm32mp1_get_command(char *cmd, int argc)
+{
+ const char *cmd_string[DDR_CMD_UNKNOWN] = {
+ [DDR_CMD_HELP] = "help",
+ [DDR_CMD_INFO] = "info",
+ [DDR_CMD_FREQ] = "freq",
+ [DDR_CMD_RESET] = "reset",
+ [DDR_CMD_PARAM] = "param",
+ [DDR_CMD_PRINT] = "print",
+ [DDR_CMD_EDIT] = "edit",
+ [DDR_CMD_STEP] = "step",
+ [DDR_CMD_NEXT] = "next",
+ [DDR_CMD_GO] = "go",
+#ifdef CONFIG_STM32MP1_DDR_TESTS
+ [DDR_CMD_TEST] = "test",
+#endif
+#ifdef CONFIG_STM32MP1_DDR_TUNING
+ [DDR_CMD_TUNING] = "tuning",
+#endif
+ };
+ /* min and max number of argument */
+ const char cmd_arg[DDR_CMD_UNKNOWN][2] = {
+ [DDR_CMD_HELP] = { 0, 0 },
+ [DDR_CMD_INFO] = { 0, 255 },
+ [DDR_CMD_FREQ] = { 0, 1 },
+ [DDR_CMD_RESET] = { 0, 0 },
+ [DDR_CMD_PARAM] = { 0, 2 },
+ [DDR_CMD_PRINT] = { 0, 1 },
+ [DDR_CMD_EDIT] = { 2, 2 },
+ [DDR_CMD_STEP] = { 0, 1 },
+ [DDR_CMD_NEXT] = { 0, 0 },
+ [DDR_CMD_GO] = { 0, 0 },
+#ifdef CONFIG_STM32MP1_DDR_TESTS
+ [DDR_CMD_TEST] = { 0, 255 },
+#endif
+#ifdef CONFIG_STM32MP1_DDR_TUNING
+ [DDR_CMD_TUNING] = { 0, 255 },
+#endif
+ };
+ int i;
+
+ for (i = 0; i < DDR_CMD_UNKNOWN; i++)
+ if (!strcmp(cmd, cmd_string[i])) {
+ if (argc - 1 < cmd_arg[i][0]) {
+ printf("no enought argument (min=%d)\n",
+ cmd_arg[i][0]);
+ return DDR_CMD_UNKNOWN;
+ } else if (argc - 1 > cmd_arg[i][1]) {
+ printf("too many argument (max=%d)\n",
+ cmd_arg[i][1]);
+ return DDR_CMD_UNKNOWN;
+ } else {
+ return i;
+ }
+ }
+
+ printf("unknown command %s\n", cmd);
+ return DDR_CMD_UNKNOWN;
+}
+
+static void stm32mp1_do_usage(void)
+{
+ const char *usage = {
+ "commands:\n\n"
+ "help displays help\n"
+ "info displays DDR information\n"
+ "info <param> <val> changes DDR information\n"
+ " with <param> = step, name, size or speed\n"
+ "freq displays the DDR PHY frequency in kHz\n"
+ "freq <freq> changes the DDR PHY frequency\n"
+ "param [type|reg] prints input parameters\n"
+ "param <reg> <val> edits parameters in step 0\n"
+ "print [type|reg] dumps registers\n"
+ "edit <reg> <val> modifies one register\n"
+ "step lists the available step\n"
+ "step <n> go to the step <n>\n"
+ "next goes to the next step\n"
+ "go continues the U-Boot SPL execution\n"
+ "reset reboots machine\n"
+#ifdef CONFIG_STM32MP1_DDR_TESTS
+ "test [help] | <n> [...] lists (with help) or executes test <n>\n"
+#endif
+#ifdef CONFIG_STM32MP1_DDR_TUNING
+ "tuning [help] | <n> [...] lists (with help) or execute tuning <n>\n"
+#endif
+ "\nwith for [type|reg]:\n"
+ " all registers if absent\n"
+ " <type> = ctl, phy\n"
+ " or one category (static, timing, map, perf, cal, dyn)\n"
+ " <reg> = name of the register\n"
+ };
+
+ puts(usage);
+}
+
+static bool stm32mp1_check_step(enum stm32mp1_ddr_interact_step step,
+ enum stm32mp1_ddr_interact_step expected)
+{
+ if (step != expected) {
+ printf("invalid step %d:%s expecting %d:%s\n",
+ step, step_str[step],
+ expected,
+ step_str[expected]);
+ return false;
+ }
+ return true;
+}
+
+static void stm32mp1_do_info(struct ddr_info *priv,
+ struct stm32mp1_ddr_config *config,
+ enum stm32mp1_ddr_interact_step step,
+ int argc, char * const argv[])
+{
+ unsigned long value;
+ static char *ddr_name;
+
+ if (argc == 1) {
+ printf("step = %d : %s\n", step, step_str[step]);
+ printf("name = %s\n", config->info.name);
+ printf("size = 0x%x\n", config->info.size);
+ printf("speed = %d kHz\n", config->info.speed);
+ return;
+ }
+
+ if (argc < 3) {
+ printf("no enought parameter\n");
+ return;
+ }
+ if (!strcmp(argv[1], "name")) {
+ u32 i, name_len = 0;
+
+ for (i = 2; i < argc; i++)
+ name_len += strlen(argv[i]) + 1;
+ if (ddr_name)
+ free(ddr_name);
+ ddr_name = malloc(name_len);
+ config->info.name = ddr_name;
+ if (!ddr_name) {
+ printf("alloc error, length %d\n", name_len);
+ return;
+ }
+ strcpy(ddr_name, argv[2]);
+ for (i = 3; i < argc; i++) {
+ strcat(ddr_name, " ");
+ strcat(ddr_name, argv[i]);
+ }
+ printf("name = %s\n", ddr_name);
+ return;
+ }
+ if (!strcmp(argv[1], "size")) {
+ if (strict_strtoul(argv[2], 16, &value) < 0) {
+ printf("invalid value %s\n", argv[2]);
+ } else {
+ config->info.size = value;
+ printf("size = 0x%x\n", config->info.size);
+ }
+ return;
+ }
+ if (!strcmp(argv[1], "speed")) {
+ if (strict_strtoul(argv[2], 10, &value) < 0) {
+ printf("invalid value %s\n", argv[2]);
+ } else {
+ config->info.speed = value;
+ printf("speed = %d kHz\n", config->info.speed);
+ value = clk_get_rate(&priv->clk);
+ printf("DDRPHY = %ld kHz\n", value / 1000);
+ }
+ return;
+ }
+ printf("argument %s invalid\n", argv[1]);
+}
+
+static bool stm32mp1_do_freq(struct ddr_info *priv,
+ int argc, char * const argv[])
+{
+ unsigned long ddrphy_clk;
+
+ if (argc == 2) {
+ if (strict_strtoul(argv[1], 0, &ddrphy_clk) < 0) {
+ printf("invalid argument %s", argv[1]);
+ return false;
+ }
+ if (clk_set_rate(&priv->clk, ddrphy_clk * 1000)) {
+ printf("ERROR: update failed!\n");
+ return false;
+ }
+ }
+ ddrphy_clk = clk_get_rate(&priv->clk);
+ printf("DDRPHY = %ld kHz\n", ddrphy_clk / 1000);
+ if (argc == 2)
+ return true;
+ return false;
+}
+
+static void stm32mp1_do_param(enum stm32mp1_ddr_interact_step step,
+ const struct stm32mp1_ddr_config *config,
+ int argc, char * const argv[])
+{
+ switch (argc) {
+ case 1:
+ stm32mp1_dump_param(config, NULL);
+ break;
+ case 2:
+ if (stm32mp1_dump_param(config, argv[1]))
+ printf("invalid argument %s\n",
+ argv[1]);
+ break;
+ case 3:
+ if (!stm32mp1_check_step(step, STEP_DDR_RESET))
+ return;
+ stm32mp1_edit_param(config, argv[1], argv[2]);
+ break;
+ }
+}
+
+static void stm32mp1_do_print(struct ddr_info *priv,
+ int argc, char * const argv[])
+{
+ switch (argc) {
+ case 1:
+ stm32mp1_dump_reg(priv, NULL);
+ break;
+ case 2:
+ if (stm32mp1_dump_reg(priv, argv[1]))
+ printf("invalid argument %s\n",
+ argv[1]);
+ break;
+ }
+}
+
+static int stm32mp1_do_step(enum stm32mp1_ddr_interact_step step,
+ int argc, char * const argv[])
+{
+ int i;
+ unsigned long value;
+
+ switch (argc) {
+ case 1:
+ for (i = 0; i < ARRAY_SIZE(step_str); i++)
+ printf("%d:%s\n", i, step_str[i]);
+ break;
+
+ case 2:
+ if ((strict_strtoul(argv[1], 0,
+ &value) < 0) ||
+ value >= ARRAY_SIZE(step_str)) {
+ printf("invalid argument %s\n",
+ argv[1]);
+ goto end;
+ }
+
+ if (value != STEP_DDR_RESET &&
+ value <= step) {
+ printf("invalid target %d:%s, current step is %d:%s\n",
+ (int)value, step_str[value],
+ step, step_str[step]);
+ goto end;
+ }
+ printf("step to %d:%s\n",
+ (int)value, step_str[value]);
+ return (int)value;
+ };
+
+end:
+ return step;
+}
+
+#if defined(CONFIG_STM32MP1_DDR_TESTS) || defined(CONFIG_STM32MP1_DDR_TUNING)
+static const char * const s_result[] = {
+ [TEST_PASSED] = "Pass",
+ [TEST_FAILED] = "Failed",
+ [TEST_ERROR] = "Error"
+};
+
+static void stm32mp1_ddr_subcmd(struct ddr_info *priv,
+ int argc, char *argv[],
+ const struct test_desc array[],
+ const int array_nb)
+{
+ int i;
+ unsigned long value;
+ int result;
+ char string[50] = "";
+
+ if (argc == 1) {
+ printf("%s:%d\n", argv[0], array_nb);
+ for (i = 0; i < array_nb; i++)
+ printf("%d:%s:%s\n",
+ i, array[i].name, array[i].usage);
+ return;
+ }
+ if (argc > 1 && !strcmp(argv[1], "help")) {
+ printf("%s:%d\n", argv[0], array_nb);
+ for (i = 0; i < array_nb; i++)
+ printf("%d:%s:%s:%s\n", i,
+ array[i].name, array[i].usage, array[i].help);
+ return;
+ }
+
+ if ((strict_strtoul(argv[1], 0, &value) < 0) ||
+ value >= array_nb) {
+ sprintf(string, "invalid argument %s",
+ argv[1]);
+ result = TEST_FAILED;
+ goto end;
+ }
+
+ if (argc > (array[value].max_args + 2)) {
+ sprintf(string, "invalid nb of args %d, max %d",
+ argc - 2, array[value].max_args);
+ result = TEST_FAILED;
+ goto end;
+ }
+
+ printf("execute %d:%s\n", (int)value, array[value].name);
+ clear_ctrlc();
+ result = array[value].fct(priv->ctl, priv->phy,
+ string, argc - 2, &argv[2]);
+
+end:
+ printf("Result: %s [%s]\n", s_result[result], string);
+}
+#endif
+
+bool stm32mp1_ddr_interactive(void *priv,
+ enum stm32mp1_ddr_interact_step step,
+ const struct stm32mp1_ddr_config *config)
+{
+ const char *prompt = "DDR>";
+ char buffer[CONFIG_SYS_CBSIZE];
+ char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
+ int argc;
+ static int next_step = -1;
+
+ if (next_step < 0 && step == STEP_DDR_RESET) {
+#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE_FORCE
+ gd->flags &= ~(GD_FLG_SILENT |
+ GD_FLG_DISABLE_CONSOLE);
+ next_step = STEP_DDR_RESET;
+#else
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ if (tstc() && (getc() == 'd')) {
+ next_step = STEP_DDR_RESET;
+ break;
+ }
+ if (get_timer(start) > 100)
+ break;
+ }
+#endif
+ }
+
+ debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
+
+ if (next_step < 0)
+ return false;
+
+ if (step < 0 || step > ARRAY_SIZE(step_str)) {
+ printf("** step %d ** INVALID\n", step);
+ return false;
+ }
+
+ printf("%d:%s\n", step, step_str[step]);
+ printf("%s\n", prompt);
+
+ if (next_step > step)
+ return false;
+
+ while (next_step == step) {
+ cli_readline_into_buffer(prompt, buffer, 0);
+ argc = cli_simple_parse_line(buffer, argv);
+ if (!argc)
+ continue;
+
+ switch (stm32mp1_get_command(argv[0], argc)) {
+ case DDR_CMD_HELP:
+ stm32mp1_do_usage();
+ break;
+
+ case DDR_CMD_INFO:
+ stm32mp1_do_info(priv,
+ (struct stm32mp1_ddr_config *)config,
+ step, argc, argv);
+ break;
+
+ case DDR_CMD_FREQ:
+ if (stm32mp1_do_freq(priv, argc, argv))
+ next_step = STEP_DDR_RESET;
+ break;
+
+ case DDR_CMD_RESET:
+ do_reset(NULL, 0, 0, NULL);
+ break;
+
+ case DDR_CMD_PARAM:
+ stm32mp1_do_param(step, config, argc, argv);
+ break;
+
+ case DDR_CMD_PRINT:
+ stm32mp1_do_print(priv, argc, argv);
+ break;
+
+ case DDR_CMD_EDIT:
+ stm32mp1_edit_reg(priv, argv[1], argv[2]);
+ break;
+
+ case DDR_CMD_GO:
+ next_step = STEP_RUN;
+ break;
+
+ case DDR_CMD_NEXT:
+ next_step = step + 1;
+ break;
+
+ case DDR_CMD_STEP:
+ next_step = stm32mp1_do_step(step, argc, argv);
+ break;
+
+#ifdef CONFIG_STM32MP1_DDR_TESTS
+ case DDR_CMD_TEST:
+ if (!stm32mp1_check_step(step, STEP_DDR_READY))
+ continue;
+ stm32mp1_ddr_subcmd(priv, argc, argv, test, test_nb);
+ break;
+#endif
+
+#ifdef CONFIG_STM32MP1_DDR_TUNING
+ case DDR_CMD_TUNING:
+ if (!stm32mp1_check_step(step, STEP_DDR_READY))
+ continue;
+ stm32mp1_ddr_subcmd(priv, argc, argv,
+ tuning, tuning_nb);
+ break;
+#endif
+
+ default:
+ break;
+ }
+ }
+ return next_step == STEP_DDR_RESET;
+}
"ddrphyc" /* LAST clock => used for get_rate() */
};
-int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed)
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
{
unsigned long ddrphy_clk;
unsigned long ddr_clk;
priv->clk = clk;
ddrphy_clk = clk_get_rate(&priv->clk);
- debug("DDR: mem_speed (%d MHz), RCC %d MHz\n",
- mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+ debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000));
/* max 10% frequency delta */
- ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000);
- if (ddr_clk > (mem_speed * 1000 * 100)) {
- pr_err("DDR expected freq %d MHz, current is %d MHz\n",
- mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+ ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
+ if (ddr_clk > (mem_speed * 100)) {
+ pr_err("DDR expected freq %d kHz, current is %d kHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000));
return -EINVAL;
}
debug("%s: %s[0x%x] = %d\n", __func__,
param[idx].name, param[idx].size, ret);
if (ret) {
- pr_err("%s: Cannot read %s\n",
- __func__, param[idx].name);
+ pr_err("%s: Cannot read %s, error=%d\n",
+ __func__, param[idx].name, ret);
return -EINVAL;
}
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+#include <common.h>
+#include <console.h>
+#include <asm/io.h>
+#include <linux/log2.h>
+#include "stm32mp1_tests.h"
+
+#define ADDR_INVALID 0xFFFFFFFF
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int get_bufsize(char *string, int argc, char *argv[], int arg_nb,
+ size_t *bufsize, size_t default_size)
+{
+ unsigned long value;
+
+ if (argc > arg_nb) {
+ if (strict_strtoul(argv[arg_nb], 0, &value) < 0) {
+ sprintf(string, "invalid %d parameter %s",
+ arg_nb, argv[arg_nb]);
+ return -1;
+ }
+ if (value > STM32_DDR_SIZE || value == 0) {
+ sprintf(string, "invalid size %s", argv[arg_nb]);
+ return -1;
+ }
+ if (value & 0x3) {
+ sprintf(string, "unaligned size %s",
+ argv[arg_nb]);
+ return -1;
+ }
+ *bufsize = value;
+ } else {
+ if (default_size != STM32_DDR_SIZE)
+ *bufsize = default_size;
+ else
+ *bufsize = get_ram_size((long *)STM32_DDR_BASE,
+ STM32_DDR_SIZE);
+ }
+ return 0;
+}
+
+static int get_nb_loop(char *string, int argc, char *argv[], int arg_nb,
+ u32 *nb_loop, u32 default_nb_loop)
+{
+ unsigned long value;
+
+ if (argc > arg_nb) {
+ if (strict_strtoul(argv[arg_nb], 0, &value) < 0) {
+ sprintf(string, "invalid %d parameter %s",
+ arg_nb, argv[arg_nb]);
+ return -1;
+ }
+ if (value == 0)
+ printf("WARNING: infinite loop requested\n");
+ *nb_loop = value;
+ } else {
+ *nb_loop = default_nb_loop;
+ }
+
+ return 0;
+}
+
+static int get_addr(char *string, int argc, char *argv[], int arg_nb,
+ u32 *addr)
+{
+ unsigned long value;
+
+ if (argc > arg_nb) {
+ if (strict_strtoul(argv[arg_nb], 16, &value) < 0) {
+ sprintf(string, "invalid %d parameter %s",
+ arg_nb, argv[arg_nb]);
+ return -1;
+ }
+ if (value < STM32_DDR_BASE) {
+ sprintf(string, "too low address %s", argv[arg_nb]);
+ return -1;
+ }
+ if (value & 0x3 && value != ADDR_INVALID) {
+ sprintf(string, "unaligned address %s",
+ argv[arg_nb]);
+ return -1;
+ }
+ *addr = value;
+ } else {
+ *addr = STM32_DDR_BASE;
+ }
+
+ return 0;
+}
+
+static int get_pattern(char *string, int argc, char *argv[], int arg_nb,
+ u32 *pattern, u32 default_pattern)
+{
+ unsigned long value;
+
+ if (argc > arg_nb) {
+ if (strict_strtoul(argv[arg_nb], 16, &value) < 0) {
+ sprintf(string, "invalid %d parameter %s",
+ arg_nb, argv[arg_nb]);
+ return -1;
+ }
+ *pattern = value;
+ } else {
+ *pattern = default_pattern;
+ }
+
+ return 0;
+}
+
+static u32 check_addr(u32 addr, u32 value)
+{
+ u32 data = readl(addr);
+
+ if (value != data) {
+ printf("0x%08x: 0x%08x <=> 0x%08x", addr, data, value);
+ data = readl(addr);
+ printf("(2nd read: 0x%08x)", data);
+ if (value == data)
+ printf("- read error");
+ else
+ printf("- write error");
+ printf("\n");
+ return -1;
+ }
+ return 0;
+}
+
+static int progress(u32 offset)
+{
+ if (!(offset & 0xFFFFFF)) {
+ putc('.');
+ if (ctrlc()) {
+ printf("\ntest interrupted!\n");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static int test_loop_end(u32 *loop, u32 nb_loop, u32 progress)
+{
+ (*loop)++;
+ if (nb_loop && *loop >= nb_loop)
+ return 1;
+ if ((*loop) % progress)
+ return 0;
+ /* allow to interrupt the test only for progress step */
+ if (ctrlc()) {
+ printf("test interrupted!\n");
+ return 1;
+ }
+ printf("loop #%d\n", *loop);
+ return 0;
+}
+
+/**********************************************************************
+ *
+ * Function: memTestDataBus()
+ *
+ * Description: Test the data bus wiring in a memory region by
+ * performing a walking 1's test at a fixed address
+ * within that region. The address is selected
+ * by the caller.
+ *
+ * Notes:
+ *
+ * Returns: 0 if the test succeeds.
+ * A non-zero result is the first pattern that failed.
+ *
+ **********************************************************************/
+static u32 databus(u32 *address)
+{
+ u32 pattern;
+ u32 read_value;
+
+ /* Perform a walking 1's test at the given address. */
+ for (pattern = 1; pattern != 0; pattern <<= 1) {
+ /* Write the test pattern. */
+ writel(pattern, address);
+
+ /* Read it back (immediately is okay for this test). */
+ read_value = readl(address);
+ debug("%x: %x <=> %x\n",
+ (u32)address, read_value, pattern);
+
+ if (read_value != pattern)
+ return pattern;
+ }
+
+ return 0;
+}
+
+/**********************************************************************
+ *
+ * Function: memTestAddressBus()
+ *
+ * Description: Test the address bus wiring in a memory region by
+ * performing a walking 1's test on the relevant bits
+ * of the address and checking for aliasing. This test
+ * will find single-bit address failures such as stuck
+ * -high, stuck-low, and shorted pins. The base address
+ * and size of the region are selected by the caller.
+ *
+ * Notes: For best results, the selected base address should
+ * have enough LSB 0's to guarantee single address bit
+ * changes. For example, to test a 64-Kbyte region,
+ * select a base address on a 64-Kbyte boundary. Also,
+ * select the region size as a power-of-two--if at all
+ * possible.
+ *
+ * Returns: NULL if the test succeeds.
+ * A non-zero result is the first address at which an
+ * aliasing problem was uncovered. By examining the
+ * contents of memory, it may be possible to gather
+ * additional information about the problem.
+ *
+ **********************************************************************/
+static u32 *addressbus(u32 *address, u32 nb_bytes)
+{
+ u32 mask = (nb_bytes / sizeof(u32) - 1);
+ u32 offset;
+ u32 test_offset;
+ u32 read_value;
+
+ u32 pattern = 0xAAAAAAAA;
+ u32 antipattern = 0x55555555;
+
+ /* Write the default pattern at each of the power-of-two offsets. */
+ for (offset = 1; (offset & mask) != 0; offset <<= 1)
+ writel(pattern, &address[offset]);
+
+ /* Check for address bits stuck high. */
+ test_offset = 0;
+ writel(antipattern, &address[test_offset]);
+
+ for (offset = 1; (offset & mask) != 0; offset <<= 1) {
+ read_value = readl(&address[offset]);
+ debug("%x: %x <=> %x\n",
+ (u32)&address[offset], read_value, pattern);
+ if (read_value != pattern)
+ return &address[offset];
+ }
+
+ writel(pattern, &address[test_offset]);
+
+ /* Check for address bits stuck low or shorted. */
+ for (test_offset = 1; (test_offset & mask) != 0; test_offset <<= 1) {
+ writel(antipattern, &address[test_offset]);
+ if (readl(&address[0]) != pattern)
+ return &address[test_offset];
+
+ for (offset = 1; (offset & mask) != 0; offset <<= 1) {
+ if (readl(&address[offset]) != pattern &&
+ offset != test_offset)
+ return &address[test_offset];
+ }
+ writel(pattern, &address[test_offset]);
+ }
+
+ return NULL;
+}
+
+/**********************************************************************
+ *
+ * Function: memTestDevice()
+ *
+ * Description: Test the integrity of a physical memory device by
+ * performing an increment/decrement test over the
+ * entire region. In the process every storage bit
+ * in the device is tested as a zero and a one. The
+ * base address and the size of the region are
+ * selected by the caller.
+ *
+ * Notes:
+ *
+ * Returns: NULL if the test succeeds.
+ *
+ * A non-zero result is the first address at which an
+ * incorrect value was read back. By examining the
+ * contents of memory, it may be possible to gather
+ * additional information about the problem.
+ *
+ **********************************************************************/
+static u32 *memdevice(u32 *address, u32 nb_bytes)
+{
+ u32 offset;
+ u32 nb_words = nb_bytes / sizeof(u32);
+
+ u32 pattern;
+ u32 antipattern;
+
+ puts("Fill with pattern");
+ /* Fill memory with a known pattern. */
+ for (pattern = 1, offset = 0; offset < nb_words; pattern++, offset++) {
+ writel(pattern, &address[offset]);
+ if (progress(offset))
+ return NULL;
+ }
+
+ puts("\nCheck and invert pattern");
+ /* Check each location and invert it for the second pass. */
+ for (pattern = 1, offset = 0; offset < nb_words; pattern++, offset++) {
+ if (readl(&address[offset]) != pattern)
+ return &address[offset];
+
+ antipattern = ~pattern;
+ writel(antipattern, &address[offset]);
+ if (progress(offset))
+ return NULL;
+ }
+
+ puts("\nCheck inverted pattern");
+ /* Check each location for the inverted pattern and zero it. */
+ for (pattern = 1, offset = 0; offset < nb_words; pattern++, offset++) {
+ antipattern = ~pattern;
+ if (readl(&address[offset]) != antipattern)
+ return &address[offset];
+ if (progress(offset))
+ return NULL;
+ }
+ printf("\n");
+
+ return NULL;
+}
+
+static enum test_result databuswalk0(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ int i;
+ u32 loop = 0, nb_loop;
+ u32 addr;
+ u32 error = 0;
+ u32 data;
+
+ if (get_nb_loop(string, argc, argv, 0, &nb_loop, 100))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 1, &addr))
+ return TEST_ERROR;
+
+ printf("running %d loops at 0x%x\n", nb_loop, addr);
+ while (!error) {
+ for (i = 0; i < 32; i++)
+ writel(~(1 << i), addr + 4 * i);
+ for (i = 0; i < 32; i++) {
+ data = readl(addr + 4 * i);
+ if (~(1 << i) != data) {
+ error |= 1 << i;
+ debug("%x: error %x expected %x => error:%x\n",
+ addr + 4 * i, data, ~(1 << i), error);
+ }
+ }
+ if (test_loop_end(&loop, nb_loop, 1000))
+ break;
+ for (i = 0; i < 32; i++)
+ writel(0, addr + 4 * i);
+ }
+ if (error) {
+ sprintf(string, "loop %d: error for bits 0x%x",
+ loop, error);
+ return TEST_FAILED;
+ }
+ sprintf(string, "no error for %d loops", loop);
+ return TEST_PASSED;
+}
+
+static enum test_result databuswalk1(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ int i;
+ u32 loop = 0, nb_loop;
+ u32 addr;
+ u32 error = 0;
+ u32 data;
+
+ if (get_nb_loop(string, argc, argv, 0, &nb_loop, 100))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 1, &addr))
+ return TEST_ERROR;
+ printf("running %d loops at 0x%x\n", nb_loop, addr);
+ while (!error) {
+ for (i = 0; i < 32; i++)
+ writel(1 << i, addr + 4 * i);
+ for (i = 0; i < 32; i++) {
+ data = readl(addr + 4 * i);
+ if ((1 << i) != data) {
+ error |= 1 << i;
+ debug("%x: error %x expected %x => error:%x\n",
+ addr + 4 * i, data, (1 << i), error);
+ }
+ }
+ if (test_loop_end(&loop, nb_loop, 1000))
+ break;
+ for (i = 0; i < 32; i++)
+ writel(0, addr + 4 * i);
+ }
+ if (error) {
+ sprintf(string, "loop %d: error for bits 0x%x",
+ loop, error);
+ return TEST_FAILED;
+ }
+ sprintf(string, "no error for %d loops", loop);
+ return TEST_PASSED;
+}
+
+static enum test_result test_databus(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 addr;
+ u32 error;
+
+ if (get_addr(string, argc, argv, 0, &addr))
+ return TEST_ERROR;
+ error = databus((u32 *)addr);
+ if (error) {
+ sprintf(string, "0x%x: error for bits 0x%x",
+ addr, error);
+ return TEST_FAILED;
+ }
+ sprintf(string, "address 0x%x", addr);
+ return TEST_PASSED;
+}
+
+static enum test_result test_addressbus(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 addr;
+ u32 bufsize;
+ u32 error;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (!is_power_of_2(bufsize)) {
+ sprintf(string, "size 0x%x is not a power of 2",
+ (u32)bufsize);
+ return TEST_ERROR;
+ }
+ if (get_addr(string, argc, argv, 1, &addr))
+ return TEST_ERROR;
+
+ error = (u32)addressbus((u32 *)addr, bufsize);
+ if (error) {
+ sprintf(string, "0x%x: error for address 0x%x",
+ addr, error);
+ return TEST_FAILED;
+ }
+ sprintf(string, "address 0x%x, size 0x%x",
+ addr, bufsize);
+ return TEST_PASSED;
+}
+
+static enum test_result test_memdevice(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 addr;
+ size_t bufsize;
+ u32 error;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 1, &addr))
+ return TEST_ERROR;
+ error = (u32)memdevice((u32 *)addr, (unsigned long)bufsize);
+ if (error) {
+ sprintf(string, "0x%x: error for address 0x%x",
+ addr, error);
+ return TEST_FAILED;
+ }
+ sprintf(string, "address 0x%x, size 0x%x",
+ addr, bufsize);
+ return TEST_PASSED;
+}
+
+/**********************************************************************
+ *
+ * Function: sso
+ *
+ * Description: Test the Simultaneous Switching Output.
+ * Verifies succes sive reads and writes to the same memory word,
+ * holding one bit constant while toggling all other data bits
+ * simultaneously
+ * => stress the data bus over an address range
+ *
+ * The CPU writes to each address in the given range.
+ * For each bit, first the CPU holds the bit at 1 while
+ * toggling the other bits, and then the CPU holds the bit at 0
+ * while toggling the other bits.
+ * After each write, the CPU reads the address that was written
+ * to verify that it contains the correct data
+ *
+ **********************************************************************/
+static enum test_result test_sso(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ int i, j;
+ u32 addr, bufsize, remaining, offset;
+ u32 error = 0;
+ u32 data;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 1, &addr))
+ return TEST_ERROR;
+
+ printf("running sso at 0x%x length 0x%x", addr, bufsize);
+ offset = addr;
+ remaining = bufsize;
+ while (remaining) {
+ for (i = 0; i < 32; i++) {
+ /* write pattern. */
+ for (j = 0; j < 6; j++) {
+ switch (j) {
+ case 0:
+ case 2:
+ data = 1 << i;
+ break;
+ case 3:
+ case 5:
+ data = ~(1 << i);
+ break;
+ case 1:
+ data = ~0x0;
+ break;
+ case 4:
+ data = 0x0;
+ break;
+ }
+
+ writel(data, offset);
+ error = check_addr(offset, data);
+ if (error)
+ goto end;
+ }
+ }
+ offset += 4;
+ remaining -= 4;
+ if (progress(offset << 7))
+ goto end;
+ }
+ puts("\n");
+
+end:
+ if (error) {
+ sprintf(string, "error for pattern 0x%x @0x%x",
+ data, offset);
+ return TEST_FAILED;
+ }
+ sprintf(string, "no error for sso at 0x%x length 0x%x", addr, bufsize);
+ return TEST_PASSED;
+}
+
+/**********************************************************************
+ *
+ * Function: Random
+ *
+ * Description: Verifies r/w with pseudo-ramdom value on one region
+ * + write the region (individual access)
+ * + memcopy to the 2nd region (try to use burst)
+ * + verify the 2 regions
+ *
+ **********************************************************************/
+static enum test_result test_random(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 addr, offset, value = 0;
+ size_t bufsize;
+ u32 loop = 0, nb_loop;
+ u32 error = 0;
+ unsigned int seed;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 2, &addr))
+ return TEST_ERROR;
+
+ printf("running %d loops at 0x%x\n", nb_loop, addr);
+ while (!error) {
+ seed = rand();
+ for (offset = addr; offset < addr + bufsize; offset += 4)
+ writel(rand(), offset);
+
+ memcpy((void *)addr + bufsize, (void *)addr, bufsize);
+
+ srand(seed);
+ for (offset = addr; offset < addr + 2 * bufsize; offset += 4) {
+ if (offset == (addr + bufsize))
+ srand(seed);
+ value = rand();
+ error = check_addr(offset, value);
+ if (error)
+ break;
+ if (progress(offset))
+ return TEST_FAILED;
+ }
+ if (test_loop_end(&loop, nb_loop, 100))
+ break;
+ }
+
+ if (error) {
+ sprintf(string,
+ "loop %d: error for address 0x%x: 0x%x expected 0x%x",
+ loop, offset, readl(offset), value);
+ return TEST_FAILED;
+ }
+ sprintf(string, "no error for %d loops, size 0x%x",
+ loop, bufsize);
+ return TEST_PASSED;
+}
+
+/**********************************************************************
+ *
+ * Function: noise
+ *
+ * Description: Verifies r/w while forcing switching of all data bus lines.
+ * optimised 4 iteration write/read/write/read cycles...
+ * for pattern and inversed pattern
+ *
+ **********************************************************************/
+void do_noise(u32 addr, u32 pattern, u32 *result)
+{
+ __asm__("push {R0-R11}");
+ __asm__("mov r0, %0" : : "r" (addr));
+ __asm__("mov r1, %0" : : "r" (pattern));
+ __asm__("mov r11, %0" : : "r" (result));
+
+ __asm__("mvn r2, r1");
+
+ __asm__("str r1, [r0]");
+ __asm__("ldr r3, [r0]");
+ __asm__("str r2, [r0]");
+ __asm__("ldr r4, [r0]");
+
+ __asm__("str r1, [r0]");
+ __asm__("ldr r5, [r0]");
+ __asm__("str r2, [r0]");
+ __asm__("ldr r6, [r0]");
+
+ __asm__("str r1, [r0]");
+ __asm__("ldr r7, [r0]");
+ __asm__("str r2, [r0]");
+ __asm__("ldr r8, [r0]");
+
+ __asm__("str r1, [r0]");
+ __asm__("ldr r9, [r0]");
+ __asm__("str r2, [r0]");
+ __asm__("ldr r10, [r0]");
+
+ __asm__("stmia R11!, {R3-R10}");
+
+ __asm__("pop {R0-R11}");
+}
+
+static enum test_result test_noise(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 addr, pattern;
+ u32 result[8];
+ int i;
+ enum test_result res = TEST_PASSED;
+
+ if (get_pattern(string, argc, argv, 0, &pattern, 0xFFFFFFFF))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 1, &addr))
+ return TEST_ERROR;
+
+ printf("running noise for 0x%x at 0x%x\n", pattern, addr);
+
+ do_noise(addr, pattern, result);
+
+ for (i = 0; i < 0x8;) {
+ if (check_addr((u32)&result[i++], pattern))
+ res = TEST_FAILED;
+ if (check_addr((u32)&result[i++], ~pattern))
+ res = TEST_FAILED;
+ }
+
+ return res;
+}
+
+/**********************************************************************
+ *
+ * Function: noise_burst
+ *
+ * Description: Verifies r/w while forcing switching of all data bus lines.
+ * optimised write loop witrh store multiple to use burst
+ * for pattern and inversed pattern
+ *
+ **********************************************************************/
+void do_noise_burst(u32 addr, u32 pattern, size_t bufsize)
+{
+ __asm__("push {R0-R9}");
+ __asm__("mov r0, %0" : : "r" (addr));
+ __asm__("mov r1, %0" : : "r" (pattern));
+ __asm__("mov r9, %0" : : "r" (bufsize));
+
+ __asm__("mvn r2, r1");
+ __asm__("mov r3, r1");
+ __asm__("mov r4, r2");
+ __asm__("mov r5, r1");
+ __asm__("mov r6, r2");
+ __asm__("mov r7, r1");
+ __asm__("mov r8, r2");
+
+ __asm__("loop1:");
+ __asm__("stmia R0!, {R1-R8}");
+ __asm__("stmia R0!, {R1-R8}");
+ __asm__("stmia R0!, {R1-R8}");
+ __asm__("stmia R0!, {R1-R8}");
+ __asm__("subs r9, r9, #128");
+ __asm__("bge loop1");
+ __asm__("pop {R0-R9}");
+}
+
+/* chunk size enough to allow interruption with Ctrl-C*/
+#define CHUNK_SIZE 0x8000000
+static enum test_result test_noise_burst(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 addr, offset, pattern;
+ size_t bufsize, remaining, size;
+ int i;
+ enum test_result res = TEST_PASSED;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (get_pattern(string, argc, argv, 1, &pattern, 0xFFFFFFFF))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 2, &addr))
+ return TEST_ERROR;
+
+ printf("running noise burst for 0x%x at 0x%x + 0x%x",
+ pattern, addr, bufsize);
+
+ offset = addr;
+ remaining = bufsize;
+ size = CHUNK_SIZE;
+ while (remaining) {
+ if (remaining < size)
+ size = remaining;
+ do_noise_burst(offset, pattern, size);
+ remaining -= size;
+ offset += size;
+ if (progress(offset)) {
+ res = TEST_FAILED;
+ goto end;
+ }
+ }
+ puts("\ncheck buffer");
+ for (i = 0; i < bufsize;) {
+ if (check_addr(addr + i, pattern))
+ res = TEST_FAILED;
+ i += 4;
+ if (check_addr(addr + i, ~pattern))
+ res = TEST_FAILED;
+ i += 4;
+ if (progress(i)) {
+ res = TEST_FAILED;
+ goto end;
+ }
+ }
+end:
+ puts("\n");
+ return res;
+}
+
+/**********************************************************************
+ *
+ * Function: pattern test
+ *
+ * Description: optimized loop for read/write pattern (array of 8 u32)
+ *
+ **********************************************************************/
+#define PATTERN_SIZE 8
+static enum test_result test_loop(const u32 *pattern, u32 *address,
+ const u32 bufsize)
+{
+ int i;
+ int j;
+ enum test_result res = TEST_PASSED;
+ u32 *offset, testsize, remaining;
+
+ offset = address;
+ remaining = bufsize;
+ while (remaining) {
+ testsize = bufsize > 0x1000000 ? 0x1000000 : bufsize;
+
+ __asm__("push {R0-R10}");
+ __asm__("mov r0, %0" : : "r" (pattern));
+ __asm__("mov r1, %0" : : "r" (offset));
+ __asm__("mov r2, %0" : : "r" (testsize));
+ __asm__("ldmia r0!, {R3-R10}");
+
+ __asm__("loop2:");
+ __asm__("stmia r1!, {R3-R10}");
+ __asm__("stmia r1!, {R3-R10}");
+ __asm__("stmia r1!, {R3-R10}");
+ __asm__("stmia r1!, {R3-R10}");
+ __asm__("subs r2, r2, #8");
+ __asm__("bge loop2");
+ __asm__("pop {R0-R10}");
+
+ offset += testsize;
+ remaining -= testsize;
+ if (progress((u32)offset)) {
+ res = TEST_FAILED;
+ goto end;
+ }
+ }
+
+ puts("\ncheck buffer");
+ for (i = 0; i < bufsize; i += PATTERN_SIZE * 4) {
+ for (j = 0; j < PATTERN_SIZE; j++, address++)
+ if (check_addr((u32)address, pattern[j])) {
+ res = TEST_FAILED;
+ goto end;
+ }
+ if (progress(i)) {
+ res = TEST_FAILED;
+ goto end;
+ }
+ }
+
+end:
+ puts("\n");
+ return res;
+}
+
+const u32 pattern_div1_x16[PATTERN_SIZE] = {
+ 0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,
+ 0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF
+};
+
+const u32 pattern_div2_x16[PATTERN_SIZE] = {
+ 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000,
+ 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, 0x00000000
+};
+
+const u32 pattern_div4_x16[PATTERN_SIZE] = {
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000
+};
+
+const u32 pattern_div4_x32[PATTERN_SIZE] = {
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+const u32 pattern_mostly_zero_x16[PATTERN_SIZE] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x0000FFFF,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+const u32 pattern_mostly_zero_x32[PATTERN_SIZE] = {
+ 0x00000000, 0x00000000, 0x00000000, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
+
+const u32 pattern_mostly_one_x16[PATTERN_SIZE] = {
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000FFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
+};
+
+const u32 pattern_mostly_one_x32[PATTERN_SIZE] = {
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
+};
+
+#define NB_PATTERN 5
+static enum test_result test_freq_pattern(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ const u32 * const patterns_x16[NB_PATTERN] = {
+ pattern_div1_x16,
+ pattern_div2_x16,
+ pattern_div4_x16,
+ pattern_mostly_zero_x16,
+ pattern_mostly_one_x16,
+ };
+ const u32 * const patterns_x32[NB_PATTERN] = {
+ pattern_div2_x16,
+ pattern_div4_x16,
+ pattern_div4_x32,
+ pattern_mostly_zero_x32,
+ pattern_mostly_one_x32
+ };
+ const char *patterns_comments[NB_PATTERN] = {
+ "switching at frequency F/1",
+ "switching at frequency F/2",
+ "switching at frequency F/4",
+ "mostly zero",
+ "mostly one"
+ };
+
+ enum test_result res = TEST_PASSED, pattern_res;
+ int i, bus_width;
+ const u32 **patterns;
+ u32 bufsize;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+
+ switch (readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
+ case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
+ case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
+ bus_width = 16;
+ break;
+ default:
+ bus_width = 32;
+ break;
+ }
+
+ printf("running test pattern at 0x%08x length 0x%x width = %d\n",
+ STM32_DDR_BASE, bufsize, bus_width);
+
+ patterns =
+ (const u32 **)(bus_width == 16 ? patterns_x16 : patterns_x32);
+
+ for (i = 0; i < NB_PATTERN; i++) {
+ printf("test data pattern %s:", patterns_comments[i]);
+ pattern_res = test_loop(patterns[i], (u32 *)STM32_DDR_BASE,
+ bufsize);
+ if (pattern_res != TEST_PASSED) {
+ printf("Failed\n");
+ return pattern_res;
+ }
+ printf("Passed\n");
+ }
+
+ return res;
+}
+
+/**********************************************************************
+ *
+ * Function: pattern test with size
+ *
+ * Description: loop for write pattern
+ *
+ **********************************************************************/
+
+static enum test_result test_loop_size(const u32 *pattern, u32 size,
+ u32 *address,
+ const u32 bufsize)
+{
+ int i, j;
+ enum test_result res = TEST_PASSED;
+ u32 *p = address;
+
+ for (i = 0; i < bufsize; i += size * 4) {
+ for (j = 0; j < size ; j++, p++)
+ *p = pattern[j];
+ if (progress(i)) {
+ res = TEST_FAILED;
+ goto end;
+ }
+ }
+
+ puts("\ncheck buffer");
+ p = address;
+ for (i = 0; i < bufsize; i += size * 4) {
+ for (j = 0; j < size; j++, p++)
+ if (check_addr((u32)p, pattern[j])) {
+ res = TEST_FAILED;
+ goto end;
+ }
+ if (progress(i)) {
+ res = TEST_FAILED;
+ goto end;
+ }
+ }
+
+end:
+ puts("\n");
+ return res;
+}
+
+static enum test_result test_checkboard(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ enum test_result res = TEST_PASSED;
+ u32 bufsize, nb_loop, loop = 0, addr;
+ int i;
+
+ u32 checkboard[2] = {0x55555555, 0xAAAAAAAA};
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 2, &addr))
+ return TEST_ERROR;
+
+ printf("running %d loops at 0x%08x length 0x%x\n",
+ nb_loop, addr, bufsize);
+ while (1) {
+ for (i = 0; i < 2; i++) {
+ res = test_loop_size(checkboard, 2, (u32 *)addr,
+ bufsize);
+ if (res)
+ return res;
+ checkboard[0] = ~checkboard[0];
+ checkboard[1] = ~checkboard[1];
+ }
+ if (test_loop_end(&loop, nb_loop, 1))
+ break;
+ }
+ sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+ loop, addr, bufsize);
+
+ return res;
+}
+
+static enum test_result test_blockseq(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ enum test_result res = TEST_PASSED;
+ u32 bufsize, nb_loop, loop = 0, addr, value;
+ int i;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 2, &addr))
+ return TEST_ERROR;
+
+ printf("running %d loops at 0x%08x length 0x%x\n",
+ nb_loop, addr, bufsize);
+ while (1) {
+ for (i = 0; i < 256; i++) {
+ value = i | i << 8 | i << 16 | i << 24;
+ printf("pattern = %08x", value);
+ res = test_loop_size(&value, 1, (u32 *)addr, bufsize);
+ if (res != TEST_PASSED)
+ return res;
+ }
+ if (test_loop_end(&loop, nb_loop, 1))
+ break;
+ }
+ sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+ loop, addr, bufsize);
+
+ return res;
+}
+
+static enum test_result test_walkbit0(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ enum test_result res = TEST_PASSED;
+ u32 bufsize, nb_loop, loop = 0, addr, value;
+ int i;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 2, &addr))
+ return TEST_ERROR;
+
+ printf("running %d loops at 0x%08x length 0x%x\n",
+ nb_loop, addr, bufsize);
+ while (1) {
+ for (i = 0; i < 64; i++) {
+ if (i < 32)
+ value = 1 << i;
+ else
+ value = 1 << (63 - i);
+
+ printf("pattern = %08x", value);
+ res = test_loop_size(&value, 1, (u32 *)addr, bufsize);
+ if (res != TEST_PASSED)
+ return res;
+ }
+ if (test_loop_end(&loop, nb_loop, 1))
+ break;
+ }
+ sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+ loop, addr, bufsize);
+
+ return res;
+}
+
+static enum test_result test_walkbit1(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ enum test_result res = TEST_PASSED;
+ u32 bufsize, nb_loop, loop = 0, addr, value;
+ int i;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 2, &addr))
+ return TEST_ERROR;
+
+ printf("running %d loops at 0x%08x length 0x%x\n",
+ nb_loop, addr, bufsize);
+ while (1) {
+ for (i = 0; i < 64; i++) {
+ if (i < 32)
+ value = ~(1 << i);
+ else
+ value = ~(1 << (63 - i));
+
+ printf("pattern = %08x", value);
+ res = test_loop_size(&value, 1, (u32 *)addr, bufsize);
+ if (res != TEST_PASSED)
+ return res;
+ }
+ if (test_loop_end(&loop, nb_loop, 1))
+ break;
+ }
+ sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+ loop, addr, bufsize);
+
+ return res;
+}
+
+/*
+ * try to catch bad bits which are dependent on the current values of
+ * surrounding bits in either the same word32
+ */
+static enum test_result test_bitspread(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ enum test_result res = TEST_PASSED;
+ u32 bufsize, nb_loop, loop = 0, addr, bitspread[4];
+ int i, j;
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 2, &addr))
+ return TEST_ERROR;
+
+ printf("running %d loops at 0x%08x length 0x%x\n",
+ nb_loop, addr, bufsize);
+ while (1) {
+ for (i = 1; i < 32; i++) {
+ for (j = 0; j < i; j++) {
+ if (i < 32)
+ bitspread[0] = (1 << i) | (1 << j);
+ else
+ bitspread[0] = (1 << (63 - i)) |
+ (1 << (63 - j));
+ bitspread[1] = bitspread[0];
+ bitspread[2] = ~bitspread[0];
+ bitspread[3] = ~bitspread[0];
+ printf("pattern = %08x", bitspread[0]);
+
+ res = test_loop_size(bitspread, 4, (u32 *)addr,
+ bufsize);
+ if (res != TEST_PASSED)
+ return res;
+ }
+ }
+ if (test_loop_end(&loop, nb_loop, 1))
+ break;
+ }
+ sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+ loop, addr, bufsize);
+
+ return res;
+}
+
+static enum test_result test_bitflip(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ enum test_result res = TEST_PASSED;
+ u32 bufsize, nb_loop, loop = 0, addr;
+ int i;
+
+ u32 bitflip[4];
+
+ if (get_bufsize(string, argc, argv, 0, &bufsize, 4 * 1024))
+ return TEST_ERROR;
+ if (get_nb_loop(string, argc, argv, 1, &nb_loop, 1))
+ return TEST_ERROR;
+ if (get_addr(string, argc, argv, 2, &addr))
+ return TEST_ERROR;
+
+ printf("running %d loops at 0x%08x length 0x%x\n",
+ nb_loop, addr, bufsize);
+ while (1) {
+ for (i = 0; i < 32; i++) {
+ bitflip[0] = 1 << i;
+ bitflip[1] = bitflip[0];
+ bitflip[2] = ~bitflip[0];
+ bitflip[3] = bitflip[2];
+ printf("pattern = %08x", bitflip[0]);
+
+ res = test_loop_size(bitflip, 4, (u32 *)addr, bufsize);
+ if (res != TEST_PASSED)
+ return res;
+ }
+ if (test_loop_end(&loop, nb_loop, 1))
+ break;
+ }
+ sprintf(string, "no error for %d loops at 0x%08x length 0x%x",
+ loop, addr, bufsize);
+
+ return res;
+}
+
+/**********************************************************************
+ *
+ * Function: infinite read access to DDR
+ *
+ * Description: continuous read the same pattern at the same address
+ *
+ **********************************************************************/
+static enum test_result test_read(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 *addr;
+ u32 data;
+ u32 loop = 0;
+ bool random = false;
+
+ if (get_addr(string, argc, argv, 0, (u32 *)&addr))
+ return TEST_ERROR;
+
+ if ((u32)addr == ADDR_INVALID) {
+ printf("random ");
+ random = true;
+ }
+
+ printf("running at 0x%08x\n", (u32)addr);
+
+ while (1) {
+ if (random)
+ addr = (u32 *)(STM32_DDR_BASE +
+ (rand() & (STM32_DDR_SIZE - 1) & ~0x3));
+ data = readl(addr);
+ if (test_loop_end(&loop, 0, 1000))
+ break;
+ }
+ sprintf(string, "0x%x: %x", (u32)addr, data);
+
+ return TEST_PASSED;
+}
+
+/**********************************************************************
+ *
+ * Function: infinite write access to DDR
+ *
+ * Description: continuous write the same pattern at the same address
+ *
+ **********************************************************************/
+static enum test_result test_write(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 *addr;
+ u32 data = 0xA5A5AA55;
+ u32 loop = 0;
+ bool random = false;
+
+ if (get_addr(string, argc, argv, 0, (u32 *)&addr))
+ return TEST_ERROR;
+
+ if ((u32)addr == ADDR_INVALID) {
+ printf("random ");
+ random = true;
+ }
+
+ printf("running at 0x%08x\n", (u32)addr);
+
+ while (1) {
+ if (random) {
+ addr = (u32 *)(STM32_DDR_BASE +
+ (rand() & (STM32_DDR_SIZE - 1) & ~0x3));
+ data = rand();
+ }
+ writel(data, addr);
+ if (test_loop_end(&loop, 0, 1000))
+ break;
+ }
+ sprintf(string, "0x%x: %x", (u32)addr, data);
+
+ return TEST_PASSED;
+}
+
+#define NB_TEST_INFINITE 2
+static enum test_result test_all(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ enum test_result res = TEST_PASSED, result;
+ int i, nb_error = 0;
+ u32 loop = 0, nb_loop;
+
+ if (get_nb_loop(string, argc, argv, 0, &nb_loop, 1))
+ return TEST_ERROR;
+
+ while (!nb_error) {
+ /* execute all the test except the lasts which are infinite */
+ for (i = 1; i < test_nb - NB_TEST_INFINITE; i++) {
+ printf("execute %d:%s\n", (int)i, test[i].name);
+ result = test[i].fct(ctl, phy, string, 0, NULL);
+ printf("result %d:%s = ", (int)i, test[i].name);
+ if (result != TEST_PASSED) {
+ nb_error++;
+ res = TEST_FAILED;
+ puts("Failed");
+ } else {
+ puts("Passed");
+ }
+ puts("\n\n");
+ }
+ printf("loop %d: %d/%d test failed\n\n\n",
+ loop + 1, nb_error, test_nb - NB_TEST_INFINITE);
+ if (test_loop_end(&loop, nb_loop, 1))
+ break;
+ }
+ if (res != TEST_PASSED) {
+ sprintf(string, "loop %d: %d/%d test failed", loop, nb_error,
+ test_nb - NB_TEST_INFINITE);
+ } else {
+ sprintf(string, "loop %d: %d tests passed", loop,
+ test_nb - NB_TEST_INFINITE);
+ }
+ return res;
+}
+
+/****************************************************************
+ * TEST Description
+ ****************************************************************/
+
+const struct test_desc test[] = {
+ {test_all, "All", "[loop]", "Execute all tests", 1 },
+ {test_databus, "Simple DataBus", "[addr]",
+ "Verifies each data line by walking 1 on fixed address",
+ 1
+ },
+ {databuswalk0, "DataBusWalking0", "[loop] [addr]",
+ "Verifies each data bus signal can be driven low (32 word burst)",
+ 2
+ },
+ {databuswalk1, "DataBusWalking1", "[loop] [addr]",
+ "Verifies each data bus signal can be driven high (32 word burst)",
+ 2
+ },
+ {test_addressbus, "AddressBus", "[size] [addr]",
+ "Verifies each relevant bits of the address and checking for aliasing",
+ 2
+ },
+ {test_memdevice, "MemDevice", "[size] [addr]",
+ "Test the integrity of a physical memory (test every storage bit in the region)",
+ 2
+ },
+ {test_sso, "SimultaneousSwitchingOutput", "[size] [addr] ",
+ "Stress the data bus over an address range",
+ 2
+ },
+ {test_noise, "Noise", "[pattern] [addr]",
+ "Verifies r/w while forcing switching of all data bus lines.",
+ 3
+ },
+ {test_noise_burst, "NoiseBurst", "[size] [pattern] [addr]",
+ "burst transfers while forcing switching of the data bus lines",
+ 3
+ },
+ {test_random, "Random", "[size] [loop] [addr]",
+ "Verifies r/w and memcopy(burst for pseudo random value.",
+ 3
+ },
+ {test_freq_pattern, "FrequencySelectivePattern ", "[size]",
+ "write & test patterns: Mostly Zero, Mostly One and F/n",
+ 1
+ },
+ {test_blockseq, "BlockSequential", "[size] [loop] [addr]",
+ "test incremental pattern",
+ 3
+ },
+ {test_checkboard, "Checkerboard", "[size] [loop] [addr]",
+ "test checker pattern",
+ 3
+ },
+ {test_bitspread, "BitSpread", "[size] [loop] [addr]",
+ "test Bit Spread pattern",
+ 3
+ },
+ {test_bitflip, "BitFlip", "[size] [loop] [addr]",
+ "test Bit Flip pattern",
+ 3
+ },
+ {test_walkbit0, "WalkingOnes", "[size] [loop] [addr]",
+ "test Walking Ones pattern",
+ 3
+ },
+ {test_walkbit1, "WalkingZeroes", "[size] [loop] [addr]",
+ "test Walking Zeroes pattern",
+ 3
+ },
+ /* need to the the 2 last one (infinite) : skipped for test all */
+ {test_read, "infinite read", "[addr]",
+ "basic test : infinite read access", 1},
+ {test_write, "infinite write", "[addr]",
+ "basic test : infinite write access", 1},
+};
+
+const int test_nb = ARRAY_SIZE(test);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _RAM_STM32MP1_TESTS_H_
+#define _RAM_STM32MP1_TESTS_H_
+
+#include "stm32mp1_ddr_regs.h"
+
+enum test_result {
+ TEST_PASSED,
+ TEST_FAILED,
+ TEST_ERROR
+};
+
+struct test_desc {
+ enum test_result (*fct)(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string,
+ int argc, char *argv[]);
+ const char *name;
+ const char *usage;
+ const char *help;
+ u8 max_args;
+};
+
+extern const struct test_desc test[];
+extern const int test_nb;
+
+extern const struct test_desc tuning[];
+extern const int tuning_nb;
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ */
+#include <common.h>
+#include <console.h>
+#include <clk.h>
+#include <ram.h>
+#include <reset.h>
+#include <asm/io.h>
+
+#include "stm32mp1_ddr_regs.h"
+#include "stm32mp1_ddr.h"
+#include "stm32mp1_tests.h"
+
+#define MAX_DQS_PHASE_IDX _144deg
+#define MAX_DQS_UNIT_IDX 7
+#define MAX_GSL_IDX 5
+#define MAX_GPS_IDX 3
+
+/* Number of bytes used in this SW. ( min 1--> max 4). */
+#define NUM_BYTES 4
+
+enum dqs_phase_enum {
+ _36deg = 0,
+ _54deg = 1,
+ _72deg = 2,
+ _90deg = 3,
+ _108deg = 4,
+ _126deg = 5,
+ _144deg = 6
+};
+
+/* BIST Result struct */
+struct BIST_result {
+ /* Overall test result:
+ * 0 Fail (any bit failed) ,
+ * 1 Success (All bits success)
+ */
+ bool test_result;
+ /* 1: true, all fail / 0: False, not all bits fail */
+ bool all_bits_fail;
+ bool bit_i_test_result[8]; /* 0 fail / 1 success */
+};
+
+/* a struct that defines tuning parameters of a byte. */
+struct tuning_position {
+ u8 phase; /* DQS phase */
+ u8 unit; /* DQS unit delay */
+ u32 bits_delay; /* Bits deskew in this byte */
+};
+
+/* 36deg, 54deg, 72deg, 90deg, 108deg, 126deg, 144deg */
+const u8 dx_dll_phase[7] = {3, 2, 1, 0, 14, 13, 12};
+
+static u8 BIST_error_max = 1;
+static u32 BIST_seed = 0x1234ABCD;
+
+static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl)
+{
+ u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
+ u8 nb_bytes = NUM_BYTES;
+
+ switch (data_bus) {
+ case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
+ nb_bytes /= 2;
+ break;
+ case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
+ nb_bytes /= 4;
+ break;
+ default:
+ break;
+ }
+
+ return nb_bytes;
+}
+
+static void itm_soft_reset(struct stm32mp1_ddrphy *phy)
+{
+ stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
+}
+
+/* Read DQ unit delay register and provides the retrieved value for DQS
+ * We are assuming that we have the same delay when clocking
+ * by DQS and when clocking by DQSN
+ */
+static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
+{
+ u32 index;
+ u32 addr = DXNDQTR(phy, byte);
+
+ /* We are assuming that we have the same delay when clocking by DQS
+ * and when clocking by DQSN : use only the low bits
+ */
+ index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
+ & DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
+
+ pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
+ __func__, addr, readl(addr), index);
+
+ return index;
+}
+
+/* Sets the DQS phase delay for a byte lane.
+ *phase delay is specified by giving the index of the desired delay
+ * in the dx_dll_phase array.
+ */
+static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx)
+{
+ u8 sdphase_val = 0;
+
+ /* Write DXNDLLCR.SDPHASE = dx_dll_phase(phase_index); */
+ sdphase_val = dx_dll_phase[phase_idx];
+ clrsetbits_le32(DXNDLLCR(phy, byte),
+ DDRPHYC_DXNDLLCR_SDPHASE_MASK,
+ sdphase_val << DDRPHYC_DXNDLLCR_SDPHASE_SHIFT);
+}
+
+/* Sets the DQS unit delay for a byte lane.
+ * unit delay is specified by giving the index of the desired delay
+ * for dgsdly and dqsndly (same value).
+ */
+static void DQS_unit_delay(struct stm32mp1_ddrphy *phy,
+ u8 byte, u8 unit_dly_idx)
+{
+ /* Write the same value in DXNDQSTR.DQSDLY and DXNDQSTR.DQSNDLY */
+ clrsetbits_le32(DXNDQSTR(phy, byte),
+ DDRPHYC_DXNDQSTR_DQSDLY_MASK |
+ DDRPHYC_DXNDQSTR_DQSNDLY_MASK,
+ (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSDLY_SHIFT) |
+ (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT));
+
+ /* After changing this value, an ITM soft reset (PIR.ITMSRST=1,
+ * plus PIR.INIT=1) must be issued.
+ */
+ stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
+}
+
+/* Sets the DQ unit delay for a bit line in particular byte lane.
+ * unit delay is specified by giving the desired delay
+ */
+static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy,
+ u8 byte, u8 bit,
+ u8 dq_delay_index)
+{
+ u8 dq_bit_delay_val = dq_delay_index | (dq_delay_index << 2);
+
+ /* same value on delay for clock DQ an DQS_b */
+ clrsetbits_le32(DXNDQTR(phy, byte),
+ DDRPHYC_DXNDQTR_DQDLY_MASK
+ << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit),
+ dq_bit_delay_val << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit));
+}
+
+static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy,
+ u8 byte, u8 r0dgsl_idx)
+{
+ clrsetbits_le32(DXNDQSTR(phy, byte),
+ DDRPHYC_DXNDQSTR_R0DGSL_MASK,
+ r0dgsl_idx << DDRPHYC_DXNDQSTR_R0DGSL_SHIFT);
+}
+
+static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy,
+ u8 byte, u8 r0dgps_idx)
+{
+ clrsetbits_le32(DXNDQSTR(phy, byte),
+ DDRPHYC_DXNDQSTR_R0DGPS_MASK,
+ r0dgps_idx << DDRPHYC_DXNDQSTR_R0DGPS_SHIFT);
+}
+
+/* Basic BIST configuration for data lane tests. */
+static void config_BIST(struct stm32mp1_ddrphy *phy)
+{
+ /* Selects the SDRAM bank address to be used during BIST. */
+ u32 bbank = 0;
+ /* Selects the SDRAM row address to be used during BIST. */
+ u32 brow = 0;
+ /* Selects the SDRAM column address to be used during BIST. */
+ u32 bcol = 0;
+ /* Selects the value by which the SDRAM address is incremented
+ * for each write/read access.
+ */
+ u32 bainc = 0x00000008;
+ /* Specifies the maximum SDRAM rank to be used during BIST.
+ * The default value is set to maximum ranks minus 1.
+ * must be 0 with single rank
+ */
+ u32 bmrank = 0;
+ /* Selects the SDRAM rank to be used during BIST.
+ * must be 0 with single rank
+ */
+ u32 brank = 0;
+ /* Specifies the maximum SDRAM bank address to be used during
+ * BIST before the address & increments to the next rank.
+ */
+ u32 bmbank = 1;
+ /* Specifies the maximum SDRAM row address to be used during
+ * BIST before the address & increments to the next bank.
+ */
+ u32 bmrow = 0x7FFF; /* To check */
+ /* Specifies the maximum SDRAM column address to be used during
+ * BIST before the address & increments to the next row.
+ */
+ u32 bmcol = 0x3FF; /* To check */
+ u32 bmode_conf = 0x00000001; /* DRam mode */
+ u32 bdxen_conf = 0x00000001; /* BIST on Data byte */
+ u32 bdpat_conf = 0x00000002; /* Select LFSR pattern */
+
+ /*Setup BIST for DRAM mode, and LFSR-random data pattern.*/
+ /*Write BISTRR.BMODE = 1?b1;*/
+ /*Write BISTRR.BDXEN = 1?b1;*/
+ /*Write BISTRR.BDPAT = 2?b10;*/
+
+ /* reset BIST */
+ writel(0x3, &phy->bistrr);
+
+ writel((bmode_conf << 3) | (bdxen_conf << 14) | (bdpat_conf << 17),
+ &phy->bistrr);
+
+ /*Setup BIST Word Count*/
+ /*Write BISTWCR.BWCNT = 16?b0008;*/
+ writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */
+
+ writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0);
+ writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1);
+
+ /* To check this line : */
+ writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2);
+}
+
+/* Select the Byte lane to be tested by BIST. */
+static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8)
+{
+ clrsetbits_le32(&phy->bistrr,
+ DDRPHYC_BISTRR_BDXSEL_MASK,
+ datx8 << DDRPHYC_BISTRR_BDXSEL_SHIFT);
+
+ /*(For example, selecting Byte Lane 3, BISTRR.BDXSEL = 4?b0011)*/
+ /* Write BISTRR.BDXSEL = datx8; */
+}
+
+/* Perform BIST Write_Read test on a byte lane and return test result. */
+static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte,
+ struct BIST_result *bist)
+{
+ bool result = true; /* BIST_SUCCESS */
+ u32 cnt = 0;
+ u32 error = 0;
+
+ bist->test_result = true;
+
+run:
+ itm_soft_reset(phy);
+
+ /*Perform BIST Reset*/
+ /* Write BISTRR.BINST = 3?b011; */
+ clrsetbits_le32(&phy->bistrr,
+ 0x00000007,
+ 0x00000003);
+
+ /*Re-seed LFSR*/
+ /* Write BISTLSR.SEED = 32'h1234ABCD; */
+ if (BIST_seed)
+ writel(BIST_seed, &phy->bistlsr);
+ else
+ writel(rand(), &phy->bistlsr);
+
+ /* some delay to reset BIST */
+ mdelay(1);
+
+ /*Perform BIST Run*/
+ clrsetbits_le32(&phy->bistrr,
+ 0x00000007,
+ 0x00000001);
+ /* Write BISTRR.BINST = 3?b001; */
+
+ /* Wait for a number of CTL clocks before reading BIST register*/
+ /* Wait 300 ctl_clk cycles; ... IS it really needed?? */
+ /* Perform BIST Instruction Stop*/
+ /* Write BISTRR.BINST = 3?b010;*/
+
+ /* poll on BISTGSR.BDONE. If 0, wait. ++TODO Add timeout */
+ while (!(readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDDONE))
+ ;
+
+ /*Check if received correct number of words*/
+ /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */
+ if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT) ==
+ readl(&phy->bistwcr)) {
+ /*Determine if there is a data comparison error*/
+ /* if (Read BISTGSR.BDXERR = 1?b0) */
+ if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR)
+ result = false; /* BIST_FAIL; */
+ else
+ result = true; /* BIST_SUCCESS; */
+ } else {
+ result = false; /* BIST_FAIL; */
+ }
+
+ /* loop while success */
+ cnt++;
+ if (result && cnt != 1000)
+ goto run;
+
+ if (!result)
+ error++;
+
+ if (error < BIST_error_max) {
+ if (cnt != 1000)
+ goto run;
+ bist->test_result = true;
+ } else {
+ bist->test_result = false;
+ }
+}
+
+/* After running the deskew algo, this function applies the new DQ delays
+ * by reading them from the array "deskew_delay"and writing in PHY registers.
+ * The bits that are not deskewed parfectly (too much skew on them,
+ * or data eye very wide) are marked in the array deskew_non_converge.
+ */
+static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
+ u8 deskew_delay[NUM_BYTES][8],
+ u8 deskew_non_converge[NUM_BYTES][8])
+{
+ u8 bit_i;
+ u8 index;
+
+ for (bit_i = 0; bit_i < 8; bit_i++) {
+ set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
+ index = DQ_unit_index(phy, byte, bit_i);
+ pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
+ byte, bit_i, deskew_delay[byte][bit_i],
+ index, index - 3);
+ printf("Byte %d, bit %d, DQ delay = %d",
+ byte, bit_i, deskew_delay[byte][bit_i]);
+ if (deskew_non_converge[byte][bit_i] == 1)
+ pr_debug(" - not converged : still more skew");
+ printf("\n");
+ }
+}
+
+/* DQ Bit de-skew algorithm.
+ * Deskews data lines as much as possible.
+ * 1. Add delay to DQS line until finding the failure
+ * (normally a hold time violation)
+ * 2. Reduce DQS line by small steps until finding the very first time
+ * we go back to "Pass" condition.
+ * 3. For each DQ line, Reduce DQ delay until finding the very first failure
+ * (normally a hold time fail)
+ * 4. When all bits are at their first failure delay, we can consider them
+ * aligned.
+ * Handle conrer situation (Can't find Pass-fail, or fail-pass transitions
+ * at any step)
+ * TODO Provide a return Status. Improve doc
+ */
+static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy, char *string)
+{
+ /* New DQ delay value (index), set during Deskew algo */
+ u8 deskew_delay[NUM_BYTES][8];
+ /*If there is still skew on a bit, mark this bit. */
+ u8 deskew_non_converge[NUM_BYTES][8];
+ struct BIST_result result;
+ s8 dqs_unit_delay_index = 0;
+ u8 datx8 = 0;
+ u8 bit_i = 0;
+ s8 phase_idx = 0;
+ s8 bit_i_delay_index = 0;
+ u8 success = 0;
+ struct tuning_position last_right_ok;
+ u8 force_stop = 0;
+ u8 fail_found;
+ u8 error = 0;
+ u8 nb_bytes = get_nb_bytes(ctl);
+ /* u8 last_pass_dqs_unit = 0; */
+
+ memset(deskew_delay, 0, sizeof(deskew_delay));
+ memset(deskew_non_converge, 0, sizeof(deskew_non_converge));
+
+ /*Disable DQS Drift Compensation*/
+ clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
+ /*Disable all bytes*/
+ /* Disable automatic power down of DLL and IOs when disabling
+ * a byte (To avoid having to add programming and delay
+ * for a DLL re-lock when later re-enabling a disabled Byte Lane)
+ */
+ clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
+
+ /* Disable all data bytes */
+ clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
+ clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
+ clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
+ clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
+
+ /* Config the BIST block */
+ config_BIST(phy);
+ pr_debug("BIST Config done.\n");
+
+ /* Train each byte */
+ for (datx8 = 0; datx8 < nb_bytes; datx8++) {
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d, error=%d",
+ datx8 + 1, nb_bytes, error);
+ return TEST_FAILED;
+ }
+ pr_debug("\n======================\n");
+ pr_debug("Start deskew byte %d .\n", datx8);
+ pr_debug("======================\n");
+ /* Enable Byte (DXNGCR, bit DXEN) */
+ setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
+
+ /* Select the byte lane for comparison of read data */
+ BIST_datx8_sel(phy, datx8);
+
+ /* Set all DQDLYn to maximum value. All bits within the byte
+ * will be delayed with DQSTR = 2 instead of max = 3
+ * to avoid inter bits fail influence
+ */
+ writel(0xAAAAAAAA, DXNDQTR(phy, datx8));
+
+ /* Set the DQS phase delay to 90 DEG (default).
+ * What is defined here is the index of the desired config
+ * in the PHASE array.
+ */
+ phase_idx = _90deg;
+
+ /* Set DQS unit delay to the max value. */
+ dqs_unit_delay_index = MAX_DQS_UNIT_IDX;
+ DQS_unit_delay(phy, datx8, dqs_unit_delay_index);
+ DQS_phase_delay(phy, datx8, phase_idx);
+
+ /* Issue a DLL soft reset */
+ clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
+ setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
+
+ /* Test this typical init condition */
+ BIST_test(phy, datx8, &result);
+ success = result.test_result;
+
+ /* If the test pass in this typical condition,
+ * start the algo with it.
+ * Else, look for Pass init condition
+ */
+ if (!success) {
+ pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
+ success = 0; /* init */
+ /* Make sure we start with a PASS condition before
+ * looking for a fail condition.
+ * Find the first PASS PHASE condition
+ */
+
+ /* escape if we find a PASS */
+ pr_debug("increase Phase idx\n");
+ while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
+ DQS_phase_delay(phy, datx8, phase_idx);
+ BIST_test(phy, datx8, &result);
+ success = result.test_result;
+ phase_idx++;
+ }
+ /* if ended with success
+ * ==>> Restore the fist success condition
+ */
+ if (success)
+ phase_idx--; /* because it ended with ++ */
+ }
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d, error=%d",
+ datx8 + 1, nb_bytes, error);
+ return TEST_FAILED;
+ }
+ /* We couldn't find a successful condition, its seems
+ * we have hold violation, lets try reduce DQS_unit Delay
+ */
+ if (!success) {
+ /* We couldn't find a successful condition, its seems
+ * we have hold violation, lets try reduce DQS_unit
+ * Delay
+ */
+ pr_debug("Still fail. Try decrease DQS Unit delay\n");
+
+ phase_idx = 0;
+ dqs_unit_delay_index = 0;
+ DQS_phase_delay(phy, datx8, phase_idx);
+
+ /* escape if we find a PASS */
+ while (!success &&
+ (dqs_unit_delay_index <=
+ MAX_DQS_UNIT_IDX)) {
+ DQS_unit_delay(phy, datx8,
+ dqs_unit_delay_index);
+ BIST_test(phy, datx8, &result);
+ success = result.test_result;
+ dqs_unit_delay_index++;
+ }
+ if (success) {
+ /* Restore the first success condition*/
+ dqs_unit_delay_index--;
+ /* last_pass_dqs_unit = dqs_unit_delay_index;*/
+ DQS_unit_delay(phy, datx8,
+ dqs_unit_delay_index);
+ } else {
+ /* No need to continue,
+ * there is no pass region.
+ */
+ force_stop = 1;
+ }
+ }
+
+ /* There is an initial PASS condition
+ * Look for the first failing condition by PHASE stepping.
+ * This part of the algo can finish without converging.
+ */
+ if (force_stop) {
+ printf("Result: Failed ");
+ printf("[Cannot Deskew lines, ");
+ printf("there is no PASS region]\n");
+ error++;
+ continue;
+ }
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d, error=%d",
+ datx8 + 1, nb_bytes, error);
+ return TEST_FAILED;
+ }
+
+ pr_debug("there is a pass region for phase idx %d\n",
+ phase_idx);
+ pr_debug("Step1: Find the first failing condition\n");
+ /* Look for the first failing condition by PHASE stepping.
+ * This part of the algo can finish without converging.
+ */
+
+ /* escape if we find a fail (hold time violation)
+ * condition at any bit or if out of delay range.
+ */
+ while (success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
+ DQS_phase_delay(phy, datx8, phase_idx);
+ BIST_test(phy, datx8, &result);
+ success = result.test_result;
+ phase_idx++;
+ }
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d, error=%d",
+ datx8 + 1, nb_bytes, error);
+ return TEST_FAILED;
+ }
+
+ /* if the loop ended with a failing condition at any bit,
+ * lets look for the first previous success condition by unit
+ * stepping (minimal delay)
+ */
+ if (!success) {
+ pr_debug("Fail region (PHASE) found phase idx %d\n",
+ phase_idx);
+ pr_debug("Let's look for first success by DQS Unit steps\n");
+ /* This part, the algo always converge */
+ phase_idx--;
+
+ /* escape if we find a success condition
+ * or if out of delay range.
+ */
+ while (!success && dqs_unit_delay_index >= 0) {
+ DQS_unit_delay(phy, datx8,
+ dqs_unit_delay_index);
+ BIST_test(phy, datx8, &result);
+ success = result.test_result;
+ dqs_unit_delay_index--;
+ }
+ /* if the loop ended with a success condition,
+ * the last delay Right OK (before hold violation)
+ * condition is then defined as following:
+ */
+ if (success) {
+ /* Hold the dely parameters of the the last
+ * delay Right OK condition.
+ * -1 to get back to current condition
+ */
+ last_right_ok.phase = phase_idx;
+ /*+1 to get back to current condition */
+ last_right_ok.unit = dqs_unit_delay_index + 1;
+ last_right_ok.bits_delay = 0xFFFFFFFF;
+ pr_debug("Found %d\n", dqs_unit_delay_index);
+ } else {
+ /* the last OK condition is then with the
+ * previous phase_idx.
+ * -2 instead of -1 because at the last
+ * iteration of the while(),
+ * we incremented phase_idx
+ */
+ last_right_ok.phase = phase_idx - 1;
+ /* Nominal+1. Because we want the previous
+ * delay after reducing the phase delay.
+ */
+ last_right_ok.unit = 1;
+ last_right_ok.bits_delay = 0xFFFFFFFF;
+ pr_debug("Not Found : try previous phase %d\n",
+ phase_idx - 1);
+
+ DQS_phase_delay(phy, datx8, phase_idx - 1);
+ dqs_unit_delay_index = 0;
+ success = true;
+ while (success &&
+ (dqs_unit_delay_index <
+ MAX_DQS_UNIT_IDX)) {
+ DQS_unit_delay(phy, datx8,
+ dqs_unit_delay_index);
+ BIST_test(phy, datx8, &result);
+ success = result.test_result;
+ dqs_unit_delay_index++;
+ pr_debug("dqs_unit_delay_index = %d, result = %d\n",
+ dqs_unit_delay_index, success);
+ }
+
+ if (!success) {
+ last_right_ok.unit =
+ dqs_unit_delay_index - 1;
+ } else {
+ last_right_ok.unit = 0;
+ pr_debug("ERROR: failed region not FOUND");
+ }
+ }
+ } else {
+ /* we can't find a failing condition at all bits
+ * ==> Just hold the last test condition
+ * (the max DQS delay)
+ * which is the most likely,
+ * the closest to a hold violation
+ * If we can't find a Fail condition after
+ * the Pass region, stick at this position
+ * In order to have max chances to find a fail
+ * when reducing DQ delays.
+ */
+ last_right_ok.phase = MAX_DQS_PHASE_IDX;
+ last_right_ok.unit = MAX_DQS_UNIT_IDX;
+ last_right_ok.bits_delay = 0xFFFFFFFF;
+ pr_debug("Can't find the a fail condition\n");
+ }
+
+ /* step 2:
+ * if we arrive at this stage, it means that we found the last
+ * Right OK condition (by tweeking the DQS delay). Or we simply
+ * pushed DQS delay to the max
+ * This means that by reducing the delay on some DQ bits,
+ * we should find a failing condition.
+ */
+ printf("Byte %d, DQS unit = %d, phase = %d\n",
+ datx8, last_right_ok.unit, last_right_ok.phase);
+ pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
+ last_right_ok.unit, last_right_ok.phase,
+ last_right_ok.bits_delay);
+
+ /* Restore the last_right_ok condtion. */
+ DQS_unit_delay(phy, datx8, last_right_ok.unit);
+ DQS_phase_delay(phy, datx8, last_right_ok.phase);
+ writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8));
+
+ /* train each bit
+ * reduce delay on each bit, and perform a write/read test
+ * and stop at the very first time it fails.
+ * the goal is the find the first failing condition
+ * for each bit.
+ * When we achieve this condition< for all the bits,
+ * we are sure they are aligned (+/- step resolution)
+ */
+ fail_found = 0;
+ for (bit_i = 0; bit_i < 8; bit_i++) {
+ if (ctrlc()) {
+ sprintf(string,
+ "interrupted at byte %d/%d, error=%d",
+ datx8 + 1, nb_bytes, error);
+ return error;
+ }
+ pr_debug("deskewing bit %d:\n", bit_i);
+ success = 1; /* init */
+ /* Set all DQDLYn to maximum value.
+ * Only bit_i will be down-delayed
+ * ==> if we have a fail, it will be definitely
+ * from bit_i
+ */
+ writel(0xFFFFFFFF, DXNDQTR(phy, datx8));
+ /* Arriving at this stage,
+ * we have a success condition with delay = 3;
+ */
+ bit_i_delay_index = 3;
+
+ /* escape if bit delay is out of range or
+ * if a fatil occurs
+ */
+ while ((bit_i_delay_index >= 0) && success) {
+ set_DQ_unit_delay(phy, datx8,
+ bit_i,
+ bit_i_delay_index);
+ BIST_test(phy, datx8, &result);
+ success = result.test_result;
+ bit_i_delay_index--;
+ }
+
+ /* if escape with a fail condition
+ * ==> save this position for bit_i
+ */
+ if (!success) {
+ /* save the delay position.
+ * Add 1 because the while loop ended with a --,
+ * and that we need to hold the last success
+ * delay
+ */
+ deskew_delay[datx8][bit_i] =
+ bit_i_delay_index + 2;
+ if (deskew_delay[datx8][bit_i] > 3)
+ deskew_delay[datx8][bit_i] = 3;
+
+ /* A flag that states we found at least a fail
+ * at one bit.
+ */
+ fail_found = 1;
+ pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
+ bit_i, bit_i_delay_index + 1,
+ datx8, bit_i,
+ deskew_delay[datx8][bit_i]);
+ } else {
+ /* if we can find a success condition by
+ * back-delaying this bit, just set the delay
+ * to 0 (the best deskew
+ * possible) and mark the bit.
+ */
+ deskew_delay[datx8][bit_i] = 0;
+ /* set a flag that will be used later
+ * in the report.
+ */
+ deskew_non_converge[datx8][bit_i] = 1;
+ pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
+ bit_i, datx8, bit_i,
+ deskew_delay[datx8][bit_i]);
+ }
+ }
+ pr_debug("**********byte %d tuning complete************\n",
+ datx8);
+ /* If we can't find any failure by back delaying DQ lines,
+ * hold the default values
+ */
+ if (!fail_found) {
+ for (bit_i = 0; bit_i < 8; bit_i++)
+ deskew_delay[datx8][bit_i] = 0;
+ pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
+ }
+
+ apply_deskew_results(phy, datx8, deskew_delay,
+ deskew_non_converge);
+ /* Restore nominal value for DQS delay */
+ DQS_phase_delay(phy, datx8, 3);
+ DQS_unit_delay(phy, datx8, 3);
+ /* disable byte after byte bits deskew */
+ clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
+ } /* end of byte deskew */
+
+ /* re-enable all data bytes */
+ setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
+ setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
+ setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
+ setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
+
+ if (error) {
+ sprintf(string, "error = %d", error);
+ return TEST_FAILED;
+ }
+
+ return TEST_PASSED;
+} /* end function */
+
+/* Trim DQS timings and set it in the centre of data eye.
+ * Look for a PPPPF region, then look for a FPPP region and finally select
+ * the mid of the FPPPPPF region
+ */
+static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy, char *string)
+{
+ /*Stores the DQS trim values (PHASE index, unit index) */
+ u8 eye_training_val[NUM_BYTES][2];
+ u8 byte = 0;
+ struct BIST_result result;
+ s8 dqs_unit_delay_index = 0;
+ s8 phase_idx = 0;
+ s8 dqs_unit_delay_index_pass = 0;
+ s8 phase_idx_pass = 0;
+ u8 success = 0;
+ u8 left_phase_bound_found, right_phase_bound_found;
+ u8 left_unit_bound_found, right_unit_bound_found;
+ u8 left_bound_found, right_bound_found;
+ struct tuning_position left_bound, right_bound;
+ u8 error = 0;
+ u8 nb_bytes = get_nb_bytes(ctl);
+
+ /*Disable DQS Drift Compensation*/
+ clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
+ /*Disable all bytes*/
+ /* Disable automatic power down of DLL and IOs when disabling a byte
+ * (To avoid having to add programming and delay
+ * for a DLL re-lock when later re-enabling a disabled Byte Lane)
+ */
+ clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
+
+ /*Disable all data bytes */
+ clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
+ clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
+ clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
+ clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
+
+ /* Config the BIST block */
+ config_BIST(phy);
+
+ for (byte = 0; byte < nb_bytes; byte++) {
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d, error=%d",
+ byte + 1, nb_bytes, error);
+ return TEST_FAILED;
+ }
+ right_bound.phase = 0;
+ right_bound.unit = 0;
+
+ left_bound.phase = 0;
+ left_bound.unit = 0;
+
+ left_phase_bound_found = 0;
+ right_phase_bound_found = 0;
+
+ left_unit_bound_found = 0;
+ right_unit_bound_found = 0;
+
+ left_bound_found = 0;
+ right_bound_found = 0;
+
+ /* Enable Byte (DXNGCR, bit DXEN) */
+ setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
+
+ /* Select the byte lane for comparison of read data */
+ BIST_datx8_sel(phy, byte);
+
+ /* Set DQS phase delay to the nominal value. */
+ phase_idx = _90deg;
+ phase_idx_pass = phase_idx;
+
+ /* Set DQS unit delay to the nominal value. */
+ dqs_unit_delay_index = 3;
+ dqs_unit_delay_index_pass = dqs_unit_delay_index;
+ success = 0;
+
+ pr_debug("STEP0: Find Init delay\n");
+ /* STEP0: Find Init delay: a delay that put the system
+ * in a "Pass" condition then (TODO) update
+ * dqs_unit_delay_index_pass & phase_idx_pass
+ */
+ DQS_unit_delay(phy, byte, dqs_unit_delay_index);
+ DQS_phase_delay(phy, byte, phase_idx);
+ BIST_test(phy, byte, &result);
+ success = result.test_result;
+ /* If we have a fail in the nominal condition */
+ if (!success) {
+ /* Look at the left */
+ while (phase_idx >= 0 && !success) {
+ phase_idx--;
+ DQS_phase_delay(phy, byte, phase_idx);
+ BIST_test(phy, byte, &result);
+ success = result.test_result;
+ }
+ }
+ if (!success) {
+ /* if we can't find pass condition,
+ * then look at the right
+ */
+ phase_idx = _90deg;
+ while (phase_idx <= MAX_DQS_PHASE_IDX &&
+ !success) {
+ phase_idx++;
+ DQS_phase_delay(phy, byte,
+ phase_idx);
+ BIST_test(phy, byte, &result);
+ success = result.test_result;
+ }
+ }
+ /* save the pass condition */
+ if (success) {
+ phase_idx_pass = phase_idx;
+ } else {
+ printf("Result: Failed ");
+ printf("[Cannot DQS timings, ");
+ printf("there is no PASS region]\n");
+ error++;
+ continue;
+ }
+
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d, error=%d",
+ byte + 1, nb_bytes, error);
+ return TEST_FAILED;
+ }
+ pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
+ /* STEP1: Find LEFT PHASE DQS Bound */
+ while ((phase_idx >= 0) &&
+ (phase_idx <= MAX_DQS_PHASE_IDX) &&
+ !left_phase_bound_found) {
+ DQS_unit_delay(phy, byte,
+ dqs_unit_delay_index);
+ DQS_phase_delay(phy, byte,
+ phase_idx);
+ BIST_test(phy, byte, &result);
+ success = result.test_result;
+
+ /*TODO: Manage the case were at the beginning
+ * there is already a fail
+ */
+ if (!success) {
+ /* the last pass condition */
+ left_bound.phase = ++phase_idx;
+ left_phase_bound_found = 1;
+ } else if (success) {
+ phase_idx--;
+ }
+ }
+ if (!left_phase_bound_found) {
+ left_bound.phase = 0;
+ phase_idx = 0;
+ }
+ /* If not found, lets take 0 */
+
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d, error=%d",
+ byte + 1, nb_bytes, error);
+ return TEST_FAILED;
+ }
+ pr_debug("STEP2: Find UNIT left bound\n");
+ /* STEP2: Find UNIT left bound */
+ while ((dqs_unit_delay_index >= 0) &&
+ !left_unit_bound_found) {
+ DQS_unit_delay(phy, byte,
+ dqs_unit_delay_index);
+ DQS_phase_delay(phy, byte, phase_idx);
+ BIST_test(phy, byte, &result);
+ success = result.test_result;
+ if (!success) {
+ left_bound.unit =
+ ++dqs_unit_delay_index;
+ left_unit_bound_found = 1;
+ left_bound_found = 1;
+ } else if (success) {
+ dqs_unit_delay_index--;
+ }
+ }
+
+ /* If not found, lets take 0 */
+ if (!left_unit_bound_found)
+ left_bound.unit = 0;
+
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d, error=%d",
+ byte + 1, nb_bytes, error);
+ return TEST_FAILED;
+ }
+ pr_debug("STEP3: Find PHase right bound\n");
+ /* STEP3: Find PHase right bound, start with "pass"
+ * condition
+ */
+
+ /* Set DQS phase delay to the pass value. */
+ phase_idx = phase_idx_pass;
+
+ /* Set DQS unit delay to the pass value. */
+ dqs_unit_delay_index = dqs_unit_delay_index_pass;
+
+ while ((phase_idx <= MAX_DQS_PHASE_IDX) &&
+ !right_phase_bound_found) {
+ DQS_unit_delay(phy, byte,
+ dqs_unit_delay_index);
+ DQS_phase_delay(phy, byte, phase_idx);
+ BIST_test(phy, byte, &result);
+ success = result.test_result;
+ if (!success) {
+ /* the last pass condition */
+ right_bound.phase = --phase_idx;
+ right_phase_bound_found = 1;
+ } else if (success) {
+ phase_idx++;
+ }
+ }
+
+ /* If not found, lets take the max value */
+ if (!right_phase_bound_found) {
+ right_bound.phase = MAX_DQS_PHASE_IDX;
+ phase_idx = MAX_DQS_PHASE_IDX;
+ }
+
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d, error=%d",
+ byte + 1, nb_bytes, error);
+ return TEST_FAILED;
+ }
+ pr_debug("STEP4: Find UNIT right bound\n");
+ /* STEP4: Find UNIT right bound */
+ while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
+ !right_unit_bound_found) {
+ DQS_unit_delay(phy, byte,
+ dqs_unit_delay_index);
+ DQS_phase_delay(phy, byte, phase_idx);
+ BIST_test(phy, byte, &result);
+ success = result.test_result;
+ if (!success) {
+ right_bound.unit =
+ --dqs_unit_delay_index;
+ right_unit_bound_found = 1;
+ right_bound_found = 1;
+ } else if (success) {
+ dqs_unit_delay_index++;
+ }
+ }
+ /* If not found, lets take the max value */
+ if (!right_unit_bound_found)
+ right_bound.unit = MAX_DQS_UNIT_IDX;
+
+ /* If we found a regular FAil Pass FAil pattern
+ * FFPPPPPPFF
+ * OR PPPPPFF Or FFPPPPP
+ */
+
+ if (left_bound_found || right_bound_found) {
+ eye_training_val[byte][0] = (right_bound.phase +
+ left_bound.phase) / 2;
+ eye_training_val[byte][1] = (right_bound.unit +
+ left_bound.unit) / 2;
+
+ /* If we already lost 1/2PHASE Tuning,
+ * let's try to recover by ++ on unit
+ */
+ if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
+ eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
+ eye_training_val[byte][1]++;
+ pr_debug("** found phase : %d - %d & unit %d - %d\n",
+ right_bound.phase, left_bound.phase,
+ right_bound.unit, left_bound.unit);
+ pr_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
+ eye_training_val[byte][0],
+ eye_training_val[byte][1]);
+ } else {
+ /* PPPPPPPPPP, we're already good.
+ * Set nominal values.
+ */
+ eye_training_val[byte][0] = 3;
+ eye_training_val[byte][1] = 3;
+ }
+ DQS_phase_delay(phy, byte, eye_training_val[byte][0]);
+ DQS_unit_delay(phy, byte, eye_training_val[byte][1]);
+
+ printf("Byte %d, DQS unit = %d, phase = %d\n",
+ byte,
+ eye_training_val[byte][1],
+ eye_training_val[byte][0]);
+ }
+
+ if (error) {
+ sprintf(string, "error = %d", error);
+ return TEST_FAILED;
+ }
+
+ return TEST_PASSED;
+}
+
+static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte)
+{
+ u8 i = 0;
+
+ printf("Byte %d Dekew result, bit0 delay, bit1 delay...bit8 delay\n ",
+ byte);
+
+ for (i = 0; i < 8; i++)
+ printf("%d ", DQ_unit_index(phy, byte, i));
+ printf("\n");
+
+ printf("dxndllcr: [%08x] val:%08x\n",
+ DXNDLLCR(phy, byte),
+ readl(DXNDLLCR(phy, byte)));
+ printf("dxnqdstr: [%08x] val:%08x\n",
+ DXNDQSTR(phy, byte),
+ readl(DXNDQSTR(phy, byte)));
+ printf("dxndqtr: [%08x] val:%08x\n",
+ DXNDQTR(phy, byte),
+ readl(DXNDQTR(phy, byte)));
+}
+
+/* analyse the dgs gating log table, and determine the midpoint.*/
+static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
+ u8 dqs_gating[NUM_BYTES]
+ [MAX_GSL_IDX + 1]
+ [MAX_GPS_IDX + 1])
+{
+ /* stores the dqs gate values (gsl index, gps index) */
+ u8 dqs_gate_values[NUM_BYTES][2];
+ u8 gsl_idx, gps_idx = 0;
+ u8 left_bound_idx[2] = {0, 0};
+ u8 right_bound_idx[2] = {0, 0};
+ u8 left_bound_found = 0;
+ u8 right_bound_found = 0;
+ u8 intermittent = 0;
+ u8 value;
+
+ for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
+ for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
+ value = dqs_gating[byte][gsl_idx][gps_idx];
+ if (value == 1 && left_bound_found == 0) {
+ left_bound_idx[0] = gsl_idx;
+ left_bound_idx[1] = gps_idx;
+ left_bound_found = 1;
+ } else if (value == 0 &&
+ left_bound_found == 1 &&
+ !right_bound_found) {
+ if (gps_idx == 0) {
+ right_bound_idx[0] = gsl_idx - 1;
+ right_bound_idx[1] = MAX_GPS_IDX;
+ } else {
+ right_bound_idx[0] = gsl_idx;
+ right_bound_idx[1] = gps_idx - 1;
+ }
+ right_bound_found = 1;
+ } else if (value == 1 &&
+ right_bound_found == 1) {
+ intermittent = 1;
+ }
+ }
+ }
+
+ /* if only ppppppp is found, there is no mid region. */
+ if (left_bound_idx[0] == 0 && left_bound_idx[1] == 0 &&
+ right_bound_idx[0] == 0 && right_bound_idx[1] == 0)
+ intermittent = 1;
+
+ /*if we found a regular fail pass fail pattern ffppppppff
+ * or pppppff or ffppppp
+ */
+ if (!intermittent) {
+ /*if we found a regular fail pass fail pattern ffppppppff
+ * or pppppff or ffppppp
+ */
+ if (left_bound_found || right_bound_found) {
+ pr_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
+ left_bound_found,
+ right_bound_idx[0], left_bound_idx[0],
+ right_bound_found,
+ right_bound_idx[1], left_bound_idx[1]);
+ dqs_gate_values[byte][0] =
+ (right_bound_idx[0] + left_bound_idx[0]) / 2;
+ dqs_gate_values[byte][1] =
+ (right_bound_idx[1] + left_bound_idx[1]) / 2;
+ /* if we already lost 1/2gsl tuning,
+ * let's try to recover by ++ on gps
+ */
+ if (((right_bound_idx[0] +
+ left_bound_idx[0]) % 2 == 1) &&
+ dqs_gate_values[byte][1] != MAX_GPS_IDX)
+ dqs_gate_values[byte][1]++;
+ /* if we already lost 1/2gsl tuning and gps is on max*/
+ else if (((right_bound_idx[0] +
+ left_bound_idx[0]) % 2 == 1) &&
+ dqs_gate_values[byte][1] == MAX_GPS_IDX) {
+ dqs_gate_values[byte][1] = 0;
+ dqs_gate_values[byte][0]++;
+ }
+ /* if we have gsl left and write limit too close
+ * (difference=1)
+ */
+ if (((right_bound_idx[0] - left_bound_idx[0]) == 1)) {
+ dqs_gate_values[byte][1] = (left_bound_idx[1] +
+ right_bound_idx[1] +
+ 4) / 2;
+ if (dqs_gate_values[byte][1] >= 4) {
+ dqs_gate_values[byte][0] =
+ right_bound_idx[0];
+ dqs_gate_values[byte][1] -= 4;
+ } else {
+ dqs_gate_values[byte][0] =
+ left_bound_idx[0];
+ }
+ }
+ pr_debug("*******calculating mid region: system latency: %d phase: %d********\n",
+ dqs_gate_values[byte][0],
+ dqs_gate_values[byte][1]);
+ pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
+ set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
+ set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
+ }
+ } else {
+ /* if intermitant, restore defaut values */
+ pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
+ set_r0dgsl_delay(phy, byte, 0);
+ set_r0dgps_delay(phy, byte, 2);
+ }
+
+ /* return 0 if intermittent or if both left_bound
+ * and right_bound are not found
+ */
+ return !(intermittent || (left_bound_found && right_bound_found));
+}
+
+static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string)
+{
+ /* stores the log of pass/fail */
+ u8 dqs_gating[NUM_BYTES][MAX_GSL_IDX + 1][MAX_GPS_IDX + 1];
+ u8 byte, gsl_idx, gps_idx = 0;
+ struct BIST_result result;
+ u8 success = 0;
+ u8 nb_bytes = get_nb_bytes(ctl);
+
+ memset(dqs_gating, 0x0, sizeof(dqs_gating));
+
+ /*disable dqs drift compensation*/
+ clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
+ /*disable all bytes*/
+ /* disable automatic power down of dll and ios when disabling a byte
+ * (to avoid having to add programming and delay
+ * for a dll re-lock when later re-enabling a disabled byte lane)
+ */
+ clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
+
+ /* disable all data bytes */
+ clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
+ clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
+ clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
+ clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
+
+ /* config the bist block */
+ config_BIST(phy);
+
+ for (byte = 0; byte < nb_bytes; byte++) {
+ if (ctrlc()) {
+ sprintf(string, "interrupted at byte %d/%d",
+ byte + 1, nb_bytes);
+ return TEST_FAILED;
+ }
+ /* enable byte x (dxngcr, bit dxen) */
+ setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
+
+ /* select the byte lane for comparison of read data */
+ BIST_datx8_sel(phy, byte);
+ for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
+ for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
+ if (ctrlc()) {
+ sprintf(string,
+ "interrupted at byte %d/%d",
+ byte + 1, nb_bytes);
+ return TEST_FAILED;
+ }
+ /* write cfg to dxndqstr */
+ set_r0dgsl_delay(phy, byte, gsl_idx);
+ set_r0dgps_delay(phy, byte, gps_idx);
+
+ BIST_test(phy, byte, &result);
+ success = result.test_result;
+ if (success)
+ dqs_gating[byte][gsl_idx][gps_idx] = 1;
+ itm_soft_reset(phy);
+ }
+ }
+ set_midpoint_read_dqs_gating(phy, byte, dqs_gating);
+ /* dummy reads */
+ readl(0xc0000000);
+ readl(0xc0000000);
+ }
+
+ /* re-enable drift compensation */
+ /* setbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); */
+ return TEST_PASSED;
+}
+
+/****************************************************************
+ * TEST
+ ****************************************************************
+ */
+static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc,
+ char *argv[])
+{
+ u32 rfshctl3 = readl(&ctl->rfshctl3);
+ u32 pwrctl = readl(&ctl->pwrctl);
+ enum test_result res;
+
+ stm32mp1_refresh_disable(ctl);
+ res = read_dqs_gating(ctl, phy, string);
+ stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
+
+ return res;
+}
+
+static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 rfshctl3 = readl(&ctl->rfshctl3);
+ u32 pwrctl = readl(&ctl->pwrctl);
+ enum test_result res;
+
+ stm32mp1_refresh_disable(ctl);
+ res = bit_deskew(ctl, phy, string);
+ stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
+
+ return res;
+}
+
+static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ u32 rfshctl3 = readl(&ctl->rfshctl3);
+ u32 pwrctl = readl(&ctl->pwrctl);
+ enum test_result res;
+
+ stm32mp1_refresh_disable(ctl);
+ res = eye_training(ctl, phy, string);
+ stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
+
+ return res;
+}
+
+static enum test_result do_display(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ int byte;
+ u8 nb_bytes = get_nb_bytes(ctl);
+
+ for (byte = 0; byte < nb_bytes; byte++)
+ display_reg_results(phy, byte);
+
+ return TEST_PASSED;
+}
+
+static enum test_result do_bist_config(struct stm32mp1_ddrctl *ctl,
+ struct stm32mp1_ddrphy *phy,
+ char *string, int argc, char *argv[])
+{
+ unsigned long value;
+
+ if (argc > 0) {
+ if (strict_strtoul(argv[0], 0, &value) < 0) {
+ sprintf(string, "invalid nbErr %s", argv[0]);
+ return TEST_FAILED;
+ }
+ BIST_error_max = value;
+ }
+ if (argc > 1) {
+ if (strict_strtoul(argv[1], 0, &value) < 0) {
+ sprintf(string, "invalid Seed %s", argv[1]);
+ return TEST_FAILED;
+ }
+ BIST_seed = value;
+ }
+ printf("Bist.nbErr = %d\n", BIST_error_max);
+ if (BIST_seed)
+ printf("Bist.Seed = 0x%x\n", BIST_seed);
+ else
+ printf("Bist.Seed = random\n");
+
+ return TEST_PASSED;
+}
+
+/****************************************************************
+ * TEST Description
+ ****************************************************************
+ */
+
+const struct test_desc tuning[] = {
+ {do_read_dqs_gating, "Read DQS gating",
+ "software read DQS Gating", "", 0 },
+ {do_bit_deskew, "Bit de-skew", "", "", 0 },
+ {do_eye_training, "Eye Training", "or DQS training", "", 0 },
+ {do_display, "Display registers", "", "", 0 },
+ {do_bist_config, "Bist config", "[nbErr] [seed]",
+ "configure Bist test", 2},
+};
+
+const int tuning_nb = ARRAY_SIZE(tuning);
static const struct k3_sysctrler_desc k3_sysctrler_am654_desc = {
.host_id = 4, /* HOST_ID_R5_1 */
- .max_rx_timeout_us = 400000,
+ .max_rx_timeout_us = 800000,
.max_msg_size = 60,
};
#include <dm.h>
#include <reset-uclass.h>
#include <linux/io.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
#include <dm/lists.h>
/*
* Each reg has 16 bits reset signal for devices
static int socfpga_reset_probe(struct udevice *dev)
{
struct socfpga_reset_data *data = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
u32 modrst_offset;
void __iomem *membase;
membase = devfdt_get_addr_ptr(dev);
- modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10);
+ modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
data->modrst_base = membase + modrst_offset;
return 0;
return 0;
}
-int reset_get_by_index(struct udevice *dev, int index,
- struct reset_ctl *reset_ctl)
+static int reset_get_by_index_tail(int ret, ofnode node,
+ struct ofnode_phandle_args *args,
+ const char *list_name, int index,
+ struct reset_ctl *reset_ctl)
{
- struct ofnode_phandle_args args;
- int ret;
struct udevice *dev_reset;
struct reset_ops *ops;
- debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index,
- reset_ctl);
+ assert(reset_ctl);
reset_ctl->dev = NULL;
-
- ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
- index, &args);
- if (ret) {
- debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n",
- __func__, ret);
+ if (ret)
return ret;
- }
- ret = uclass_get_device_by_ofnode(UCLASS_RESET, args.node,
+ ret = uclass_get_device_by_ofnode(UCLASS_RESET, args->node,
&dev_reset);
if (ret) {
debug("%s: uclass_get_device_by_ofnode() failed: %d\n",
__func__, ret);
- debug("%s %d\n", ofnode_get_name(args.node), args.args[0]);
+ debug("%s %d\n", ofnode_get_name(args->node), args->args[0]);
return ret;
}
ops = reset_dev_ops(dev_reset);
reset_ctl->dev = dev_reset;
if (ops->of_xlate)
- ret = ops->of_xlate(reset_ctl, &args);
+ ret = ops->of_xlate(reset_ctl, args);
else
- ret = reset_of_xlate_default(reset_ctl, &args);
+ ret = reset_of_xlate_default(reset_ctl, args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
return ret;
return 0;
}
+int reset_get_by_index(struct udevice *dev, int index,
+ struct reset_ctl *reset_ctl)
+{
+ struct ofnode_phandle_args args;
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
+ index, &args);
+
+ return reset_get_by_index_tail(ret, dev_ofnode(dev), &args, "resets",
+ index > 0, reset_ctl);
+}
+
+int reset_get_by_index_nodev(ofnode node, int index,
+ struct reset_ctl *reset_ctl)
+{
+ struct ofnode_phandle_args args;
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0,
+ index > 0, &args);
+
+ return reset_get_by_index_tail(ret, node, &args, "resets",
+ index > 0, reset_ctl);
+}
+
int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
{
int i, ret, err, count;
/*
* The number of days in the month.
*/
-static int rtc_month_days(unsigned int month, unsigned int year)
+int rtc_month_days(unsigned int month, unsigned int year)
{
return rtc_days_in_month[month] + (is_leap_year(year) && month == 1);
}
Choose this option to add support for UART driver on the Marvell
Armada 3700 SoC. The base address is configured via DT.
+config MCFUART
+ bool "Freescale ColdFire UART support"
+ help
+ Choose this option to add support for UART driver on the ColdFire
+ SoC's family. The serial communication channel provides a full-duplex
+ asynchronous/synchronous receiver and transmitter deriving an
+ operating frequency from the internal bus clock or an external clock.
+
config MXC_UART
bool "IMX serial port support"
depends on MX5 || MX6
#include <serial.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* status register */
#define ALTERA_UART_TMT BIT(5) /* tx empty */
#define ALTERA_UART_TRDY BIT(6) /* tx ready */
plat->regs = map_physmem(devfdt_get_addr(dev),
sizeof(struct altera_uart_regs),
MAP_NOCACHE);
- plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "clock-frequency", 0);
+ plat->uartclk = dev_read_u32_default(dev, "clock-frequency", 0);
return 0;
}
*
* Modified to add device model (DM) support
* (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * Modified to add DM and fdt support, removed non DM code
+ * (C) Copyright 2018 Angelo Dureghello <angelo@sysam.it>
*/
/*
writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
}
-#ifndef CONFIG_DM_SERIAL
-
-static int mcf_serial_init(void)
-{
- uart_t *uart_base;
- int port_idx;
-
- uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
- port_idx = CONFIG_SYS_UART_PORT;
-
- return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
-}
-
-static void mcf_serial_putc(const char c)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- if (c == '\n')
- serial_putc('\r');
-
- /* Wait for last character to go. */
- while (!(readb(&uart->usr) & UART_USR_TXRDY))
- ;
-
- writeb(c, &uart->utb);
-}
-
-static int mcf_serial_getc(void)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- /* Wait for a character to arrive. */
- while (!(readb(&uart->usr) & UART_USR_RXRDY))
- ;
-
- return readb(&uart->urb);
-}
-
-static void mcf_serial_setbrg(void)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- mcf_serial_setbrg_common(uart, gd->baudrate);
-}
-
-static int mcf_serial_tstc(void)
-{
- uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
-
- return readb(&uart->usr) & UART_USR_RXRDY;
-}
-
-static struct serial_device mcf_serial_drv = {
- .name = "mcf_serial",
- .start = mcf_serial_init,
- .stop = NULL,
- .setbrg = mcf_serial_setbrg,
- .putc = mcf_serial_putc,
- .puts = default_serial_puts,
- .getc = mcf_serial_getc,
- .tstc = mcf_serial_tstc,
-};
-
-void mcf_serial_initialize(void)
-{
- serial_register(&mcf_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &mcf_serial_drv;
-}
-
-#endif
-
-#ifdef CONFIG_DM_SERIAL
-
static int coldfire_serial_probe(struct udevice *dev)
{
struct coldfire_serial_platdata *plat = dev->platdata;
return 0;
}
+static int coldfire_ofdata_to_platdata(struct udevice *dev)
+{
+ struct coldfire_serial_platdata *plat = dev_get_platdata(dev);
+ fdt_addr_t addr_base;
+
+ addr_base = devfdt_get_addr(dev);
+ if (addr_base == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ plat->base = (uint32_t)addr_base;
+
+ plat->port = dev->seq;
+ plat->baudrate = gd->baudrate;
+
+ return 0;
+}
+
static const struct dm_serial_ops coldfire_serial_ops = {
.putc = coldfire_serial_putc,
.pending = coldfire_serial_pending,
.setbrg = coldfire_serial_setbrg,
};
+static const struct udevice_id coldfire_serial_ids[] = {
+ { .compatible = "fsl,mcf-uart" },
+ { }
+};
+
U_BOOT_DRIVER(serial_coldfire) = {
.name = "serial_coldfire",
.id = UCLASS_SERIAL,
+ .of_match = coldfire_serial_ids,
+ .ofdata_to_platdata = coldfire_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct coldfire_serial_platdata),
.probe = coldfire_serial_probe,
.ops = &coldfire_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
-#endif
#include <dt-structs.h>
#include <ns16550.h>
#include <serial.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
#if defined(CONFIG_ROCKCHIP_RK3188)
struct rockchip_uart_platdata {
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_CPU_SH7760) || \
- defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786)
+#if defined(CONFIG_CPU_SH7780)
static int scif_rxfill(struct uart_port *port)
{
return sci_in(port, SCRFDR) & 0xff;
return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
}
}
-#elif defined(CONFIG_ARCH_SH7372)
-static int scif_rxfill(struct uart_port *port)
-{
- if (port->type == PORT_SCIFA)
- return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
- else
- return sci_in(port, SCRFDR);
-}
#else
static int scif_rxfill(struct uart_port *port)
{
sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
sci_in(port, SCFCR);
sci_out(port, SCFCR, 0);
+#if defined(CONFIG_RZA1)
+ sci_out(port, SCSPTR, 0x0003);
+#endif
}
static void
enum sh_clk_mode clk_mode; /* clock mode */
};
-#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
-#include <asm/regs306x.h>
-#endif
-#if defined(CONFIG_H8S2678)
-#include <asm/regs267x.h>
-#endif
-
-#if defined(CONFIG_CPU_SH7706) || \
- defined(CONFIG_CPU_SH7707) || \
- defined(CONFIG_CPU_SH7708) || \
- defined(CONFIG_CPU_SH7709)
-# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
-# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
-# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-#elif defined(CONFIG_CPU_SH7705)
-# define SCIF0 0xA4400000
-# define SCIF2 0xA4410000
-# define SCSMR_Ir 0xA44A0000
-# define IRDA_SCIF SCIF0
-# define SCPCR 0xA4000116
-# define SCPDR 0xA4000136
-
-/* Set the clock source,
- * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
- * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
- */
-# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
-#elif defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
# define PORT_PTCR 0xA405011EUL
# define PORT_PVCR 0xA4050122UL
# define SCIF_ORER 0x0200 /* overrun error bit */
-#elif defined(CONFIG_SH_RTS7751R2D)
-# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
-# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7750S) || \
- defined(CONFIG_CPU_SH7091) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R)
# define SCSPTR1 0xffe0001c /* 8 bit SCI */
# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
-#elif defined(CONFIG_CPU_SH7760)
-# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
-# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
-# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
-# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define PACR 0xa4050100
-# define PBCR 0xa4050102
-# define SCSCR_INIT(port) 0x3B
-#elif defined(CONFIG_CPU_SH7343)
-# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
-# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
-# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
-# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
-# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
#elif defined(CONFIG_CPU_SH7722)
# define PADR 0xA4050120
# undef PSDR
# define PSCR 0xA405011E
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7366)
-# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
-# define SCSPTR0 SCPDR0
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7723)
# define SCSPTR0 0xa4050160
# define SCSPTR1 0xa405013e
# define SCSPTR5 0xa4050128
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7724)
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
- 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
- 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
#elif defined(CONFIG_CPU_SH7734)
# define SCSPTR0 0xFFE40020
# define SCSPTR1 0xFFE41020
# define SCSPTR5 0xFFE45020
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH4_202)
-# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
-# define SCIF_BASE_ADDR 0x01030000
-# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
-# define SCIF_PTR2_OFFS 0x0000020
-# define SCIF_LSR2_OFFS 0x0000024
-# define SCSPTR\
- ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
-# define SCLSR2\
- ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
-# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
-#elif defined(CONFIG_H8S2678)
-# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
#elif defined(CONFIG_CPU_SH7757) || \
defined(CONFIG_CPU_SH7752) || \
defined(CONFIG_CPU_SH7753)
# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7770)
-# define SCSPTR0 0xff923020 /* 16 bit SCIF */
-# define SCSPTR1 0xff924020 /* 16 bit SCIF */
-# define SCSPTR2 0xff925020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
#elif defined(CONFIG_CPU_SH7780)
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
-#if defined(CONFIG_SH_SH2007)
-/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
-# define SCSCR_INIT(port) 0x38
-#else
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
# define SCSCR_INIT(port) 0x3a
-#endif
-#elif defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786)
-# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
-# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
-# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
-# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
-# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
-# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* Overrun error bit */
-# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7201) || \
- defined(CONFIG_CPU_SH7203) || \
- defined(CONFIG_CPU_SH7206) || \
- defined(CONFIG_CPU_SH7263) || \
- defined(CONFIG_CPU_SH7264)
-# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
-# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
-# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
-# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
-# if defined(CONFIG_CPU_SH7201)
-# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
-# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
-# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
-# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
-# endif
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7269)
+#elif defined(CONFIG_RZA1)
# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
# define SCSPTR6 0xe800a020 /* 16 bit SCIF */
# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7619)
-# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
-# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
-# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SHX3)
-# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
-# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
-# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
-# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* Overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
defined(CONFIG_R7S72100)
# if defined(CONFIG_SCIF_A)
#define SCI_CTRL_FLAGS_TE 0x20 /* all */
#define SCI_CTRL_FLAGS_RE 0x10 /* all */
#if defined(CONFIG_CPU_SH7750) || \
- defined(CONFIG_CPU_SH7091) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7722) || \
defined(CONFIG_CPU_SH7734) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7763) || \
- defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786) || \
- defined(CONFIG_CPU_SHX3)
+ defined(CONFIG_CPU_SH7780)
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
-#elif defined(CONFIG_CPU_SH7724)
-#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
#else
#define SCI_CTRL_FLAGS_REIE 0
#endif
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
-#if defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCIF_ORER 0x0200
#define SCxSR_ORER(port)\
(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
-#if defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
}\
}
-#ifdef CONFIG_H8300
-/* h8300 don't have SCIF */
-#define CPU_SCIF_FNS(name) \
- static inline unsigned int sci_##name##_in(struct uart_port *port) {\
- return 0;\
- }\
- static inline void sci_##name##_out(struct uart_port *port,\
- unsigned int value) {\
- }
-#else
#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
SCI_IN(scif_size, scif_offset);\
unsigned int value) {\
SCI_OUT(scif_size, scif_offset, value);\
}
-#endif
#define CPU_SCI_FNS(name, sci_offset, sci_size)\
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
SCI_OUT(sci_size, sci_offset, value);\
}
-#if defined(CONFIG_CPU_SH3) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
- defined(CONFIG_SH73A0) || \
+#if defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
-#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
-#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
- sh4_sci_offset, sh4_sci_size, \
- sh3_scif_offset, sh3_scif_size, \
- sh4_scif_offset, sh4_scif_size, \
- h8_sci_offset, h8_sci_size) \
- CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
- sh4_scif_offset, sh4_scif_size)
-#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
- sh4_scif_offset, sh4_scif_size) \
- CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
-#elif defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
-#elif defined(CONFIG_ARCH_SH7372) || \
- defined(CONFIG_R8A7740)
+#elif defined(CONFIG_R8A7740)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scifb_offset, sh4_scifb_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
#endif
-#elif defined(__H8300H__) || defined(__H8300S__)
-#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
- sh4_sci_offset, sh4_sci_size, \
- sh3_scif_offset, sh3_scif_size,\
- sh4_scif_offset, sh4_scif_size, \
- h8_sci_offset, h8_sci_size) \
- CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
-#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
- sh4_scif_offset, sh4_scif_size) \
- CPU_SCIF_FNS(name)
-#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7723)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#endif
-#if defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCxRDR, 0x24, 8)
SCIF_FNS(SCLSR, 0x00, 0)
SCIF_FNS(DL, 0x00, 0) /* dummy */
-#elif defined(CONFIG_ARCH_SH7372) || \
- defined(CONFIG_R8A7740)
+#elif defined(CONFIG_R8A7740)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
SCIF_FNS(SCSCR, 0x08, 16)
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
SCIF_FNS(SCLSR, 0x00, 0)
SCIF_FNS(DL, 0x00, 0) /* dummy */
-#elif defined(CONFIG_CPU_SH7723) ||\
- defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7723)
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
-#if defined(CONFIG_CPU_SH7760) || \
- defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786)
+#if defined(CONFIG_CPU_SH7780)
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
#define sci_in(port, reg) sci_##reg##_in(port)
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
-/* H8/300 series SCI pins assignment */
-#if defined(__H8300H__) || defined(__H8300S__)
-static const struct __attribute__((packed)) {
- int port; /* GPIO port no */
- unsigned short rx, tx; /* GPIO bit no */
-} h8300_sci_pins[] = {
-#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
- { /* SCI0 */
- .port = H8300_GPIO_P9,
- .rx = H8300_GPIO_B2,
- .tx = H8300_GPIO_B0,
- },
- { /* SCI1 */
- .port = H8300_GPIO_P9,
- .rx = H8300_GPIO_B3,
- .tx = H8300_GPIO_B1,
- },
- { /* SCI2 */
- .port = H8300_GPIO_PB,
- .rx = H8300_GPIO_B7,
- .tx = H8300_GPIO_B6,
- }
-#elif defined(CONFIG_H8S2678)
- { /* SCI0 */
- .port = H8300_GPIO_P3,
- .rx = H8300_GPIO_B2,
- .tx = H8300_GPIO_B0,
- },
- { /* SCI1 */
- .port = H8300_GPIO_P3,
- .rx = H8300_GPIO_B3,
- .tx = H8300_GPIO_B1,
- },
- { /* SCI2 */
- .port = H8300_GPIO_P5,
- .rx = H8300_GPIO_B1,
- .tx = H8300_GPIO_B0,
- }
-#endif
-};
-#endif
-
-#if defined(CONFIG_CPU_SH7706) || \
- defined(CONFIG_CPU_SH7707) || \
- defined(CONFIG_CPU_SH7708) || \
- defined(CONFIG_CPU_SH7709)
-static inline int sci_rxd_in(struct uart_port *port)
-{
- if (port->mapbase == 0xfffffe80)
- return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
- return 1;
-}
-#elif defined(CONFIG_CPU_SH7750) || \
+#if defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7750R) || \
- defined(CONFIG_CPU_SH7750S) || \
- defined(CONFIG_CPU_SH7091)
+ defined(CONFIG_CPU_SH7750S)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
return 1;
}
-#elif defined(__H8300H__) || defined(__H8300S__)
-static inline int sci_rxd_in(struct uart_port *port)
-{
- int ch = (port->mapbase - SMR0) >> 3;
- return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
-}
#else /* default case for non-SCI processors */
static inline int sci_rxd_in(struct uart_port *port)
{
* -- Mitch Davis - 15 Jul 2000
*/
-#if (defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7785) || \
- defined(CONFIG_CPU_SH7786)) && \
- !defined(CONFIG_SH_SH2007)
+#if defined(CONFIG_CPU_SH7780)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
-#elif defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
+#elif defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
-#elif defined(CONFIG_CPU_SH7723) ||\
- defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7723)
static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
{
if (port->type == PORT_SCIF)
return ((clk*2)+16*bps)/(16*bps)-1;
}
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
-#elif defined(__H8300H__) || defined(__H8300S__)
-#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
#elif defined(CONFIG_RCAR_GEN2)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
#if defined(CONFIG_SCIF_A)
* Copyright (C) 2018 Anup Patel <anup@brainfault.org>
*/
-#include <clk.h>
#include <common.h>
+#include <clk.h>
#include <debug_uart.h>
#include <dm.h>
#include <errno.h>
_stm32_serial_setbrg(base, uart_info,
CONFIG_DEBUG_UART_CLOCK,
CONFIG_BAUDRATE);
- printf("DEBUG done\n");
}
static inline void _debug_uart_putc(int c)
struct stm32_uart_info *uart_info = _debug_uart_info();
while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
- WATCHDOG_RESET();
+ ;
}
DEBUG_UART_FUNCS
sometimes called Azalia. The audio codec is detected using a
semi-automatic mechanism.
+config I2S_TEGRA
+ bool "Enable I2S support for Nvidia Tegra SoCs"
+ depends on I2S
+ select TEGRA124_DMA
+ help
+ Nvidia Tegra SoCs support several I2S interfaces for sending audio
+ data to an audio codec. This option enables support for this,
+ using one of the available audio codec drivers.
+
config SOUND_MAX98088
bool "Support Maxim max98088 audio codec"
depends on I2S
obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o
obj-$(CONFIG_I2S_ROCKCHIP) += rockchip_i2s.o rockchip_sound.o
obj-$(CONFIG_I2S_SAMSUNG) += samsung_sound.o
+obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o tegra_i2s.o tegra_sound.o
obj-$(CONFIG_SOUND_WM8994) += wm8994.o
obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o
obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o
#include <i2s.h>
#include <misc.h>
#include <sound.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/periph.h>
#include <dm/pinctrl.h>
static int rockchip_sound_setup(struct udevice *dev)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+159
+/*
+ * Take from dc tegra_ahub.c
+ *
+ * Copyright 2018 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_MISC
+
+#include <common.h>
+#include <dm.h>
+#include <i2s.h>
+#include <misc.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_ahub.h>
+#include <asm/arch-tegra/tegra_i2s.h>
+#include "tegra_i2s_priv.h"
+
+struct tegra_ahub_priv {
+ struct apbif_regs *apbif_regs;
+ struct xbar_regs *xbar_regs;
+ u32 full_mask;
+ int capacity_words; /* FIFO capacity in words */
+
+ /*
+ * This is unset intially, but is set by tegra_ahub_ioctl() called
+ * from the misc_ioctl() in tegra_sound_probe()
+ */
+ struct udevice *i2s;
+ struct udevice *dma;
+};
+
+static int tegra_ahub_xbar_enable_i2s(struct xbar_regs *regs, int i2s_id)
+{
+ /*
+ * Enables I2S as the receiver of APBIF by writing APBIF_TX0 (0x01) to
+ * the rx0 register
+ */
+ switch (i2s_id) {
+ case 0:
+ writel(1, ®s->i2s0_rx0);
+ break;
+ case 1:
+ writel(1, ®s->i2s1_rx0);
+ break;
+ case 2:
+ writel(1, ®s->i2s2_rx0);
+ break;
+ case 3:
+ writel(1, ®s->i2s3_rx0);
+ break;
+ case 4:
+ writel(1, ®s->i2s4_rx0);
+ break;
+ default:
+ log_err("Invalid I2S component id: %d\n", i2s_id);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int tegra_ahub_apbif_is_full(struct udevice *dev)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+
+ return readl(&priv->apbif_regs->apbdma_live_stat) & priv->full_mask;
+}
+
+/**
+ * tegra_ahub_wait_for_space() - Wait for space in the FIFO
+ *
+ * @return 0 if OK, -ETIMEDOUT if no space was available in time
+ */
+static int tegra_ahub_wait_for_space(struct udevice *dev)
+{
+ int i = 100000;
+ ulong start;
+
+ /* Busy-wait initially, since this should take almost no time */
+ while (i--) {
+ if (!tegra_ahub_apbif_is_full(dev))
+ return 0;
+ }
+
+ /* Failed, so do a slower loop for 100ms */
+ start = get_timer(0);
+ while (tegra_ahub_apbif_is_full(dev)) {
+ if (get_timer(start) > 100)
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int tegra_ahub_apbif_send(struct udevice *dev, int offset,
+ const void *buf, int len)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+ const u32 *data = (const u32 *)buf;
+ ssize_t written = 0;
+
+ if (len % sizeof(*data)) {
+ log_err("Data size (%zd) must be aligned to %zd.\n", len,
+ sizeof(*data));
+ return -EFAULT;
+ }
+ while (written < len) {
+ int ret = tegra_ahub_wait_for_space(dev);
+
+ if (ret)
+ return ret;
+
+ writel(*data++, &priv->apbif_regs->channel0_txfifo);
+ written += sizeof(*data);
+ }
+
+ return written;
+}
+
+static void tegra_ahub_apbif_set_cif(struct udevice *dev, u32 value)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+
+ writel(value, &priv->apbif_regs->channel0_cif_tx0_ctrl);
+}
+
+static void tegra_ahub_apbif_enable_channel0(struct udevice *dev,
+ int fifo_threshold)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+
+ u32 ctrl = TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN |
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 |
+ TEGRA_AHUB_CHANNEL_CTRL_TX_EN;
+
+ fifo_threshold--; /* fifo_threshold starts from 1 */
+ ctrl |= (fifo_threshold << TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT);
+ writel(ctrl, &priv->apbif_regs->channel0_ctrl);
+}
+
+static u32 tegra_ahub_get_cif(bool is_receive, uint channels,
+ uint bits_per_sample, uint fifo_threshold)
+{
+ uint audio_bits = (bits_per_sample >> 2) - 1;
+ u32 val;
+
+ channels--; /* Channels in CIF starts from 1 */
+ fifo_threshold--; /* FIFO threshold starts from 1 */
+ /* Assume input and output are always using same channel / bits */
+ val = channels << TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT |
+ channels << TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT |
+ audio_bits << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT |
+ audio_bits << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT |
+ fifo_threshold << TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT |
+ (is_receive ? TEGRA_AUDIOCIF_DIRECTION_RX <<
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT : 0);
+
+ return val;
+}
+
+static int tegra_ahub_enable(struct udevice *dev)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+ struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(priv->i2s);
+ u32 cif_ctrl = 0;
+ int ret;
+
+ /* We use APBIF channel0 as a sender */
+ priv->full_mask = TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL;
+ priv->capacity_words = 8;
+
+ /*
+ * FIFO is inactive until (fifo_threshold) of words are sent. For
+ * better performance, we want to set it to half of capacity.
+ */
+ u32 fifo_threshold = priv->capacity_words / 2;
+
+ /*
+ * Setup audio client interface (ACIF): APBIF (channel0) as sender and
+ * I2S as receiver
+ */
+ cif_ctrl = tegra_ahub_get_cif(true, uc_priv->channels,
+ uc_priv->bitspersample, fifo_threshold);
+ tegra_i2s_set_cif_tx_ctrl(priv->i2s, cif_ctrl);
+
+ cif_ctrl = tegra_ahub_get_cif(false, uc_priv->channels,
+ uc_priv->bitspersample, fifo_threshold);
+ tegra_ahub_apbif_set_cif(dev, cif_ctrl);
+ tegra_ahub_apbif_enable_channel0(dev, fifo_threshold);
+
+ ret = tegra_ahub_xbar_enable_i2s(priv->xbar_regs, uc_priv->id);
+ if (ret)
+ return ret;
+ log_debug("ahub: channels=%d, bitspersample=%d, cif_ctrl=%x, fifo_threshold=%d, id=%d\n",
+ uc_priv->channels, uc_priv->bitspersample, cif_ctrl,
+ fifo_threshold, uc_priv->id);
+
+ return 0;
+}
+
+static int tegra_ahub_ioctl(struct udevice *dev, unsigned long request,
+ void *buf)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+
+ if (request != AHUB_MISCOP_SET_I2S)
+ return -ENOSYS;
+
+ priv->i2s = *(struct udevice **)buf;
+ log_debug("i2s set to '%s'\n", priv->i2s->name);
+
+ return tegra_ahub_enable(dev);
+}
+
+static int tegra_ahub_probe(struct udevice *dev)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+ ulong addr;
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ log_debug("Invalid apbif address\n");
+ return -EINVAL;
+ }
+ priv->apbif_regs = (struct apbif_regs *)addr;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE) {
+ log_debug("Invalid xbar address\n");
+ return -EINVAL;
+ }
+ priv->xbar_regs = (struct xbar_regs *)addr;
+ log_debug("ahub apbif_regs=%p, xbar_regs=%p\n", priv->apbif_regs,
+ priv->xbar_regs);
+
+ return 0;
+}
+
+static struct misc_ops tegra_ahub_ops = {
+ .write = tegra_ahub_apbif_send,
+ .ioctl = tegra_ahub_ioctl,
+};
+
+static const struct udevice_id tegra_ahub_ids[] = {
+ { .compatible = "nvidia,tegra124-ahub" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra_ahub) = {
+ .name = "tegra_ahub",
+ .id = UCLASS_MISC,
+ .of_match = tegra_ahub_ids,
+ .ops = &tegra_ahub_ops,
+ .probe = tegra_ahub_probe,
+ .priv_auto_alloc_size = sizeof(struct tegra_ahub_priv),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+#define LOG_CATEGORY UCLASS_I2S
+#define LOG_DEBUG
+
+#include <common.h>
+#include <dm.h>
+#include <i2s.h>
+#include <misc.h>
+#include <sound.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2s.h>
+#include "tegra_i2s_priv.h"
+
+int tegra_i2s_set_cif_tx_ctrl(struct udevice *dev, u32 value)
+{
+ struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
+ struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address;
+
+ writel(value, ®s->cif_tx_ctrl);
+
+ return 0;
+}
+
+static void tegra_i2s_transmit_enable(struct i2s_ctlr *regs, int on)
+{
+ clrsetbits_le32(®s->ctrl, I2S_CTRL_XFER_EN_TX,
+ on ? I2S_CTRL_XFER_EN_TX : 0);
+}
+
+static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx)
+{
+ struct i2s_ctlr *regs = (struct i2s_ctlr *)pi2s_tx->base_address;
+ u32 audio_bits = (pi2s_tx->bitspersample >> 2) - 1;
+ u32 ctrl = readl(®s->ctrl);
+
+ /* Set format to LRCK / Left Low */
+ ctrl &= ~(I2S_CTRL_FRAME_FORMAT_MASK | I2S_CTRL_LRCK_MASK);
+ ctrl |= I2S_CTRL_FRAME_FORMAT_LRCK;
+ ctrl |= I2S_CTRL_LRCK_L_LOW;
+
+ /* Disable all transmission until we are ready to transfer */
+ ctrl &= ~(I2S_CTRL_XFER_EN_TX | I2S_CTRL_XFER_EN_RX);
+
+ /* Serve as master */
+ ctrl |= I2S_CTRL_MASTER_ENABLE;
+
+ /* Configure audio bits size */
+ ctrl &= ~I2S_CTRL_BIT_SIZE_MASK;
+ ctrl |= audio_bits << I2S_CTRL_BIT_SIZE_SHIFT;
+ writel(ctrl, ®s->ctrl);
+
+ /* Timing in LRCK mode: */
+ writel(pi2s_tx->bitspersample, ®s->timing);
+
+ /* I2S mode has [TX/RX]_DATA_OFFSET both set to 1 */
+ writel(((1 << I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
+ (1 << I2S_OFFSET_TX_DATA_OFFSET_SHIFT)), ®s->offset);
+
+ /* FSYNC_WIDTH = 2 clocks wide, TOTAL_SLOTS = 2 slots per fsync */
+ writel((2 - 1) << I2S_CH_CTRL_FSYNC_WIDTH_SHIFT, ®s->ch_ctrl);
+
+ return 0;
+}
+
+static int tegra_i2s_tx_data(struct udevice *dev, void *data, uint data_size)
+{
+ struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
+ struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address;
+ int ret;
+
+ tegra_i2s_transmit_enable(regs, 1);
+ ret = misc_write(dev_get_parent(dev), 0, data, data_size);
+ tegra_i2s_transmit_enable(regs, 0);
+ if (ret < 0)
+ return ret;
+ else if (ret < data_size)
+ return -EIO;
+
+ return 0;
+}
+
+static int tegra_i2s_probe(struct udevice *dev)
+{
+ struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
+ ulong base;
+
+ base = dev_read_addr(dev);
+ if (base == FDT_ADDR_T_NONE) {
+ debug("%s: Missing i2s base\n", __func__);
+ return -EINVAL;
+ }
+ priv->base_address = base;
+ priv->id = 1;
+ priv->audio_pll_clk = 4800000;
+ priv->samplingrate = 48000;
+ priv->bitspersample = 16;
+ priv->channels = 2;
+ priv->rfs = 256;
+ priv->bfs = 32;
+
+ return i2s_tx_init(priv);
+}
+
+static const struct i2s_ops tegra_i2s_ops = {
+ .tx_data = tegra_i2s_tx_data,
+};
+
+static const struct udevice_id tegra_i2s_ids[] = {
+ { .compatible = "nvidia,tegra124-i2s" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra_i2s) = {
+ .name = "tegra_i2s",
+ .id = UCLASS_I2S,
+ .of_match = tegra_i2s_ids,
+ .probe = tegra_i2s_probe,
+ .ops = &tegra_i2s_ops,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __TEGRA_I2S_PRIV_H
+#define __TEGRA_I2S_PRIV_H
+
+enum {
+ /* Set i2s device (in buf) */
+ AHUB_MISCOP_SET_I2S,
+};
+
+/*
+ * tegra_i2s_set_cif_tx_ctrl() - Set the I2C port to send to
+ *
+ * The CIF is not really part of I2S -- it's for Audio Hub to control
+ * the interface between I2S and Audio Hub. However since it's put in
+ * the I2S registers domain instead of the Audio Hub, we need to export
+ * this as a function.
+ *
+ * @dev: I2S device
+ * @value: Value to write to CIF_TX_CTRL register
+ * @return 0
+ */
+int tegra_i2s_set_cif_tx_ctrl(struct udevice *dev, u32 value);
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Google, LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_I2S
+
+#include <common.h>
+#include <audio_codec.h>
+#include <dm.h>
+#include <i2s.h>
+#include <misc.h>
+#include <sound.h>
+#include <asm/gpio.h>
+#include "tegra_i2s_priv.h"
+
+static int tegra_sound_setup(struct udevice *dev)
+{
+ struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct i2s_uc_priv *i2c_priv = dev_get_uclass_priv(uc_priv->i2s);
+ int ret;
+
+ if (uc_priv->setup_done)
+ return -EALREADY;
+ ret = audio_codec_set_params(uc_priv->codec, i2c_priv->id,
+ i2c_priv->samplingrate,
+ i2c_priv->samplingrate * i2c_priv->rfs,
+ i2c_priv->bitspersample,
+ i2c_priv->channels);
+ if (ret)
+ return ret;
+ uc_priv->setup_done = true;
+
+ return 0;
+}
+
+static int tegra_sound_play(struct udevice *dev, void *data, uint data_size)
+{
+ struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ return i2s_tx_data(uc_priv->i2s, data, data_size);
+}
+
+static int tegra_sound_probe(struct udevice *dev)
+{
+ struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct gpio_desc en_gpio;
+ struct udevice *ahub;
+ int ret;
+
+ ret = gpio_request_by_name(dev, "codec-enable-gpio", 0, &en_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+ ret = uclass_get_device_by_phandle(UCLASS_AUDIO_CODEC, dev,
+ "nvidia,audio-codec",
+ &uc_priv->codec);
+ if (ret) {
+ log_debug("Failed to probe audio codec\n");
+ return ret;
+ }
+ ret = uclass_get_device_by_phandle(UCLASS_I2S, dev,
+ "nvidia,i2s-controller",
+ &uc_priv->i2s);
+ if (ret) {
+ log_debug("Cannot find i2s: %d\n", ret);
+ return ret;
+ }
+
+ /* Set up the audio hub, telling it the currect i2s to use */
+ ahub = dev_get_parent(uc_priv->i2s);
+ ret = misc_ioctl(ahub, AHUB_MISCOP_SET_I2S, &uc_priv->i2s);
+ if (ret) {
+ log_debug("Cannot set i2c: %d\n", ret);
+ return ret;
+ }
+
+ log_debug("Probed sound '%s' with codec '%s' and i2s '%s'\n", dev->name,
+ uc_priv->codec->name, uc_priv->i2s->name);
+
+ return 0;
+}
+
+static const struct sound_ops tegra_sound_ops = {
+ .setup = tegra_sound_setup,
+ .play = tegra_sound_play,
+};
+
+static const struct udevice_id tegra_sound_ids[] = {
+ { .compatible = "nvidia,tegra-audio-max98090-nyan-big" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra_sound) = {
+ .name = "tegra_sound",
+ .id = UCLASS_SOUND,
+ .of_match = tegra_sound_ids,
+ .probe = tegra_sound_probe,
+ .ops = &tegra_sound_ops,
+};
used to access the SPI NOR flash on platforms embedding this
Cadence IP core.
+config CF_SPI
+ bool "ColdFire SPI driver"
+ help
+ Enable the ColdFire SPI driver. This driver can be used on
+ some m68k SoCs.
+
config DESIGNWARE_SPI
bool "Designware SPI driver"
help
config MT7621_SPI
bool "MediaTek MT7621 SPI driver"
- depends on ARCH_MT7620
+ depends on SOC_MT7628
help
Enable the MT7621 SPI driver. This driver can be used to access
the SPI NOR flash on platforms embedding this Ralink / MediaTek
config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver"
- depends on RCAR_GEN3
+ depends on RCAR_GEN3 || RZA1
imply SPI_FLASH_BAR
help
Enable the Renesas RPC SPI driver, used to access SPI NOR flash
config STM32_QSPI
bool "STM32F7 QSPI driver"
- depends on STM32F7 || ARCH_STM32MP
+ depends on STM32F4 || STM32F7 || ARCH_STM32MP
help
Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be
used to access the SPI NOR flash chips on platforms embedding
* Author: Rick Chen (rick@andestech.com)
*/
-#include <clk.h>
#include <common.h>
+#include <clk.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#define CQSPI_INDIRECT_READ 2
#define CQSPI_INDIRECT_WRITE 3
-DECLARE_GLOBAL_DATA_PTR;
-
static int cadence_spi_write_speed(struct udevice *bus, uint hz)
{
struct cadence_spi_platdata *plat = bus->platdata;
static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
{
struct cadence_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
- int subnode;
+ ofnode subnode;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
- plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs");
- plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128);
- plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4);
- plat->trigger_address = fdtdec_get_uint(blob, node,
- "cdns,trigger-address", 0);
+ plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
+ plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
+ plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
+ plat->trigger_address = dev_read_u32_default(bus,
+ "cdns,trigger-address",
+ 0);
/* All other paramters are embedded in the child node */
- subnode = fdt_first_subnode(blob, node);
- if (subnode < 0) {
+ subnode = dev_read_first_subnode(bus);
+ if (!ofnode_valid(subnode)) {
printf("Error: subnode with SPI flash config missing!\n");
return -ENODEV;
}
/* Use 500 KHz as a suitable default */
- plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency",
- 500000);
+ plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
+ 500000);
/* Read other parameters from DT */
- plat->page_size = fdtdec_get_uint(blob, subnode, "page-size", 256);
- plat->block_size = fdtdec_get_uint(blob, subnode, "block-size", 16);
- plat->tshsl_ns = fdtdec_get_uint(blob, subnode, "cdns,tshsl-ns", 200);
- plat->tsd2d_ns = fdtdec_get_uint(blob, subnode, "cdns,tsd2d-ns", 255);
- plat->tchsh_ns = fdtdec_get_uint(blob, subnode, "cdns,tchsh-ns", 20);
- plat->tslch_ns = fdtdec_get_uint(blob, subnode, "cdns,tslch-ns", 20);
+ plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
+ plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
+ plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
+ 200);
+ plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
+ 255);
+ plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
+ plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
*
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * Support for DM and DT, non-DM code removed.
+ * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
+ *
+ * TODO: fsl_dspi.c should work as a driver for the DSPI module.
*/
#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/spi_coldfire.h>
#include <spi.h>
#include <malloc.h>
-#include <asm/immap.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/io.h>
-struct cf_spi_slave {
- struct spi_slave slave;
+struct coldfire_spi_priv {
+ struct dspi *regs;
uint baudrate;
+ int mode;
int charbit;
};
-extern void cfspi_port_conf(void);
-extern int cfspi_claim_bus(uint bus, uint cs);
-extern void cfspi_release_bus(uint bus, uint cs);
-
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPI_IDLE_VAL
#endif
#endif
-#if defined(CONFIG_CF_DSPI)
-/* DSPI specific mode */
-#define SPI_MODE_MOD 0x00200000
-#define SPI_DBLRATE 0x00100000
-
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave)
+/*
+ * DSPI specific mode
+ *
+ * bit 31 - 28: Transfer size 3 to 16 bits
+ * 27 - 26: PCS to SCK delay prescaler
+ * 25 - 24: After SCK delay prescaler
+ * 23 - 22: Delay after transfer prescaler
+ * 21 : Allow overwrite for bit 31-22 and bit 20-8
+ * 20 : Double baud rate
+ * 19 - 16: PCS to SCK delay scaler
+ * 15 - 12: After SCK delay scaler
+ * 11 - 8: Delay after transfer scaler
+ * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
+ */
+#define SPI_MODE_MOD 0x00200000
+#define SPI_MODE_DBLRATE 0x00100000
+
+#define SPI_MODE_XFER_SZ_MASK 0xf0000000
+#define SPI_MODE_DLY_PRE_MASK 0x0fc00000
+#define SPI_MODE_DLY_SCA_MASK 0x000fff00
+
+#define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
+#define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
+#define MCF_DSPI_MAX_CTAR_REGS 8
+
+/* Default values */
+#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
+#define MCF_DSPI_DEFAULT_MAX_CS 4
+#define MCF_DSPI_DEFAULT_MODE 0
+
+#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
+ DSPI_CTAR_PCSSCK_1CLK | \
+ DSPI_CTAR_PASC(0) | \
+ DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | \
+ DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(1) | \
+ DSPI_CTAR_BR(6))
+
+#define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
+ DSPI_CTAR_PCSSCK(3) | \
+ DSPI_CTAR_PASC_7CLK | \
+ DSPI_CTAR_PDT(3) | \
+ DSPI_CTAR_CSSCK(0x0f) | \
+ DSPI_CTAR_ASC(0x0f) | \
+ DSPI_CTAR_DT(0x0f))
+
+#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
+
+static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
+ u32 ctrl, u16 data)
{
- return container_of(slave, struct cf_spi_slave, slave);
+ /*
+ * Need to check fifo level here
+ */
+ while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
+ ;
+
+ writel(ctrl | data, &cfspi->regs->tfr);
}
-static void cfspi_init(void)
+static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
- cfspi_port_conf(); /* port configuration */
-
- dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
- DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
- DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
- DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+ while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
+ ;
- /* Default setting in platform configuration */
-#ifdef CONFIG_SYS_DSPI_CTAR0
- dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR1
- dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR2
- dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR3
- dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR4
- dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR5
- dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR6
- dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;
-#endif
-#ifdef CONFIG_SYS_DSPI_CTAR7
- dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;
-#endif
+ return readw(&cfspi->regs->rfr);
}
-static void cfspi_tx(u32 ctrl, u16 data)
+static int coldfire_spi_claim_bus(struct udevice *dev)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ struct udevice *bus = dev->parent;
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ struct dm_spi_slave_platdata *slave_plat =
+ dev_get_parent_platdata(dev);
- while ((dspi->sr & 0x0000F000) >= 4) ;
+ if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+ return -1;
- dspi->tfr = (ctrl | data);
+ /* Clear FIFO and resume transfer */
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+ dspi_chip_select(slave_plat->cs);
+
+ return 0;
}
-static u16 cfspi_rx(void)
+static int coldfire_spi_release_bus(struct udevice *dev)
{
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ struct udevice *bus = dev->parent;
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ struct dm_spi_slave_platdata *slave_plat =
+ dev_get_parent_platdata(dev);
- while ((dspi->sr & 0x000000F0) == 0) ;
+ /* Clear FIFO */
+ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
- return (dspi->rfr & 0xFFFF);
+ dspi_chip_unselect(slave_plat->cs);
+
+ return 0;
}
-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
- void *din, ulong flags)
+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din,
+ unsigned long flags)
{
- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+ struct udevice *bus = dev_get_parent(dev);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
u8 *spi_rd = NULL, *spi_wr = NULL;
- static u32 ctrl = 0;
+ static u32 ctrl;
uint len = bitlen >> 3;
- if (cfslave->charbit == 16) {
+ if (cfspi->charbit == 16) {
bitlen >>= 1;
- spi_wr16 = (u16 *) dout;
- spi_rd16 = (u16 *) din;
+ spi_wr16 = (u16 *)dout;
+ spi_rd16 = (u16 *)din;
} else {
- spi_wr = (u8 *) dout;
- spi_rd = (u8 *) din;
+ spi_wr = (u8 *)dout;
+ spi_rd = (u8 *)din;
}
if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
ctrl |= DSPI_TFR_CONT;
- ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);
+ ctrl = setup_ctrl(ctrl, slave_plat->cs);
if (len > 1) {
int tmp_len = len - 1;
+
while (tmp_len--) {
- if (dout != NULL) {
- if (cfslave->charbit == 16)
- cfspi_tx(ctrl, *spi_wr16++);
+ if (dout) {
+ if (cfspi->charbit == 16)
+ cfspi_tx(cfspi, ctrl, *spi_wr16++);
else
- cfspi_tx(ctrl, *spi_wr++);
- cfspi_rx();
+ cfspi_tx(cfspi, ctrl, *spi_wr++);
+ cfspi_rx(cfspi);
}
- if (din != NULL) {
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- if (cfslave->charbit == 16)
- *spi_rd16++ = cfspi_rx();
+ if (din) {
+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ if (cfspi->charbit == 16)
+ *spi_rd16++ = cfspi_rx(cfspi);
else
- *spi_rd++ = cfspi_rx();
+ *spi_rd++ = cfspi_rx(cfspi);
}
}
len = 1; /* remaining byte */
}
- if ((flags & SPI_XFER_END) == SPI_XFER_END)
+ if (flags & SPI_XFER_END)
ctrl &= ~DSPI_TFR_CONT;
if (len) {
- if (dout != NULL) {
- if (cfslave->charbit == 16)
- cfspi_tx(ctrl, *spi_wr16);
+ if (dout) {
+ if (cfspi->charbit == 16)
+ cfspi_tx(cfspi, ctrl, *spi_wr16);
else
- cfspi_tx(ctrl, *spi_wr);
- cfspi_rx();
+ cfspi_tx(cfspi, ctrl, *spi_wr);
+ cfspi_rx(cfspi);
}
- if (din != NULL) {
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- if (cfslave->charbit == 16)
- *spi_rd16 = cfspi_rx();
+ if (din) {
+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ if (cfspi->charbit == 16)
+ *spi_rd16 = cfspi_rx(cfspi);
else
- *spi_rd = cfspi_rx();
+ *spi_rd = cfspi_rx(cfspi);
}
} else {
/* dummy read */
- cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);
- cfspi_rx();
+ cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
+ cfspi_rx(cfspi);
}
return 0;
}
-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
- uint mode)
+static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
{
- /*
- * bit definition for mode:
- * bit 31 - 28: Transfer size 3 to 16 bits
- * 27 - 26: PCS to SCK delay prescaler
- * 25 - 24: After SCK delay prescaler
- * 23 - 22: Delay after transfer prescaler
- * 21 : Allow overwrite for bit 31-22 and bit 20-8
- * 20 : Double baud rate
- * 19 - 16: PCS to SCK delay scaler
- * 15 - 12: After SCK delay scaler
- * 11 - 8: Delay after transfer scaler
- * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
- */
- volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
int prescaler[] = { 2, 3, 5, 7 };
int scaler[] = {
2, 4, 6, 8,
4096, 8192, 16384, 32768
};
int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
- int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
- u32 bus_setup = 0;
+ int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
+ u32 bus_setup;
+
+ cfspi->baudrate = max_hz;
+
+ /* Read current setup */
+ bus_setup = readl(&dspi->ctar[bus->seq]);
tmp = (prescaler[3] * scaler[15]);
/* Maximum and minimum baudrate it can handle */
- if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||
- (cfslave->baudrate < (gd->bus_clk / tmp))) {
+ if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
+ (cfspi->baudrate < (gd->bus_clk / tmp))) {
printf("Exceed baudrate limitation: Max %d - Min %d\n",
(int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
- return NULL;
+ return -1;
}
/* Activate Double Baud when it exceed 1/4 the bus clk */
- if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||
- (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
+ if ((bus_setup & DSPI_CTAR_DBR) ||
+ (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
bus_setup |= DSPI_CTAR_DBR;
dbr = 1;
}
- if (mode & SPI_CPOL)
- bus_setup |= DSPI_CTAR_CPOL;
- if (mode & SPI_CPHA)
- bus_setup |= DSPI_CTAR_CPHA;
- if (mode & SPI_LSB_FIRST)
- bus_setup |= DSPI_CTAR_LSBFE;
-
/* Overwrite default value set in platform configuration file */
- if (mode & SPI_MODE_MOD) {
-
- if ((mode & 0xF0000000) == 0)
- bus_setup |=
- dspi->ctar[cfslave->slave.bus] & 0x78000000;
- else
- bus_setup |= ((mode & 0xF0000000) >> 1);
-
+ if (cfspi->mode & SPI_MODE_MOD) {
/*
* Check to see if it is enabled by default in platform
* config, or manual setting passed by mode parameter
*/
- if (mode & SPI_DBLRATE) {
+ if (cfspi->mode & SPI_MODE_DBLRATE) {
bus_setup |= DSPI_CTAR_DBR;
dbr = 1;
}
- bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */
- bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */
- } else
- bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);
-
- cfslave->charbit =
- ((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==
- 0x78000000) ? 16 : 8;
+ }
pbrcnt = sizeof(prescaler) / sizeof(int);
brcnt = sizeof(scaler) / sizeof(int);
for (j = 0; j < brcnt; j++) {
tmp = (baud_speed / scaler[j]) * (1 + dbr);
- if (tmp > cfslave->baudrate)
- diff = tmp - cfslave->baudrate;
+ if (tmp > cfspi->baudrate)
+ diff = tmp - cfspi->baudrate;
else
- diff = cfslave->baudrate - tmp;
+ diff = cfspi->baudrate - tmp;
if (diff < bestmatch) {
bestmatch = diff;
}
}
}
+
+ bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
- dspi->ctar[cfslave->slave.bus] = bus_setup;
+ writel(bus_setup, &dspi->ctar[bus->seq]);
- return &cfslave->slave;
+ return 0;
}
-#endif /* CONFIG_CF_DSPI */
-#ifdef CONFIG_CMD_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
{
- if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
- return 1;
- else
- return 0;
-}
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ u32 bus_setup = 0;
-void spi_init(void)
-{
- cfspi_init();
-}
+ cfspi->mode = mode;
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct cf_spi_slave *cfslave;
+ if (cfspi->mode & SPI_CPOL)
+ bus_setup |= DSPI_CTAR_CPOL;
+ if (cfspi->mode & SPI_CPHA)
+ bus_setup |= DSPI_CTAR_CPHA;
+ if (cfspi->mode & SPI_LSB_FIRST)
+ bus_setup |= DSPI_CTAR_LSBFE;
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
+ /* Overwrite default value set in platform configuration file */
+ if (cfspi->mode & SPI_MODE_MOD) {
+ if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
+ bus_setup |=
+ readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT;
+ else
+ bus_setup |=
+ ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
- cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);
- if (!cfslave)
- return NULL;
+ /* PSCSCK, PASC, PDT */
+ bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
+ /* CSSCK, ASC, DT */
+ bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
+ } else {
+ bus_setup |=
+ (readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK);
+ }
+
+ cfspi->charbit =
+ ((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) ==
+ MCF_FRM_SZ_16BIT) ? 16 : 8;
- cfslave->baudrate = max_hz;
+ setbits_be32(&dspi->ctar[bus->seq], bus_setup);
- /* specific setup */
- return cfspi_setup_slave(cfslave, mode);
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int coldfire_spi_probe(struct udevice *bus)
{
- struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
+ struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+ struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
+ struct dspi *dspi = cfspi->regs;
+ int i;
- free(cfslave);
-}
+ cfspi->regs = (struct dspi *)plat->regs_addr;
-int spi_claim_bus(struct spi_slave *slave)
-{
- return cfspi_claim_bus(slave->bus, slave->cs);
+ cfspi->baudrate = plat->speed_hz;
+ cfspi->mode = plat->mode;
+
+ for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
+ unsigned int ctar = 0;
+
+ if (plat->ctar[i][0] == 0)
+ break;
+
+ ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
+ DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
+ DSPI_CTAR_PASC(plat->ctar[i][2]) |
+ DSPI_CTAR_PDT(plat->ctar[i][3]) |
+ DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
+ DSPI_CTAR_ASC(plat->ctar[i][5]) |
+ DSPI_CTAR_DT(plat->ctar[i][6]) |
+ DSPI_CTAR_BR(plat->ctar[i][7]);
+
+ writel(ctar, &cfspi->regs->ctar[i]);
+ }
+
+ /* Default CTARs */
+ for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
+ writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
+
+ dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
+ DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
+ DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
+ DSPI_MCR_CRXF | DSPI_MCR_CTXF;
+
+ return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+void spi_init(void)
{
- cfspi_release_bus(slave->bus, slave->cs);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
{
- return cfspi_xfer(slave, bitlen, dout, din, flags);
+ fdt_addr_t addr;
+ struct coldfire_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+ int *ctar, len;
+
+ addr = devfdt_get_addr(bus);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENOMEM;
+
+ plat->regs_addr = addr;
+
+ plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
+ MCF_DSPI_DEFAULT_MAX_CS);
+
+ plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+ MCF_DSPI_DEFAULT_SCK_FREQ);
+
+ plat->mode = fdtdec_get_int(blob, node, "spi-mode",
+ MCF_DSPI_DEFAULT_MODE);
+
+ memset(plat->ctar, 0, sizeof(plat->ctar));
+
+ ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
+
+ if (ctar && len) {
+ int i, q, ctar_regs;
+
+ ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
+
+ if (ctar_regs > MAX_CTAR_REGS)
+ ctar_regs = MAX_CTAR_REGS;
+
+ for (i = 0; i < ctar_regs; i++) {
+ for (q = 0; q < MAX_CTAR_FIELDS; q++)
+ plat->ctar[i][q] = *ctar++;
+ }
+ }
+
+ debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
+ (void *)plat->regs_addr,
+ plat->speed_hz, plat->num_cs, plat->mode);
+
+ return 0;
}
-#endif /* CONFIG_CMD_SPI */
+
+static const struct udevice_id coldfire_spi_ids[] = {
+ { .compatible = "fsl,mcf-dspi" },
+ { }
+};
+#endif
+
+static const struct dm_spi_ops coldfire_spi_ops = {
+ .claim_bus = coldfire_spi_claim_bus,
+ .release_bus = coldfire_spi_release_bus,
+ .xfer = coldfire_spi_xfer,
+ .set_speed = coldfire_spi_set_speed,
+ .set_mode = coldfire_spi_set_mode,
+};
+
+U_BOOT_DRIVER(coldfire_spi) = {
+ .name = "spi_coldfire",
+ .id = UCLASS_SPI,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .of_match = coldfire_spi_ids,
+ .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
+#endif
+ .probe = coldfire_spi_probe,
+ .ops = &coldfire_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
+};
#include <linux/iopoll.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Register offsets */
#define DW_SPI_CTRL0 0x00
#define DW_SPI_CTRL1 0x04
static int dw_spi_ofdata_to_platdata(struct udevice *bus)
{
struct dw_spi_platdata *plat = bus->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(bus);
plat->regs = (struct dw_spi *)devfdt_get_addr(bus);
/* Use 500KHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
- 500000);
+ plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+ 500000);
debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
plat->frequency);
priv->regs = plat->regs;
priv->extr = plat->extr;
-
+#if CONFIG_IS_ENABLED(CLK)
clk_enable(&priv->clk);
-
+#endif
return 0;
}
static int rpc_spi_ofdata_to_platdata(struct udevice *bus)
{
struct rpc_spi_platdata *plat = dev_get_platdata(bus);
- struct rpc_spi_priv *priv = dev_get_priv(bus);
- int ret;
plat->regs = dev_read_addr_index(bus, 0);
plat->extr = dev_read_addr_index(bus, 1);
+#if CONFIG_IS_ENABLED(CLK)
+ struct rpc_spi_priv *priv = dev_get_priv(bus);
+ int ret;
+
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {
printf("%s: Could not get clock for %s: %d\n",
__func__, bus->name, ret);
return ret;
}
+#endif
plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000);
{ .compatible = "renesas,rpc-r8a77965" },
{ .compatible = "renesas,rpc-r8a77970" },
{ .compatible = "renesas,rpc-r8a77995" },
+ { .compatible = "renesas,rpc-r7s72100" },
{ }
};
/*
* spi driver for rockchip
*
+ * (C) 2019 Theobroma Systems Design und Consulting GmbH
+ *
* (C) Copyright 2015 Google, Inc
*
* (C) Copyright 2008-2013 Rockchip Electronics
#include <spi.h>
#include <linux/errno.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/periph.h>
#include <dm/pinctrl.h>
#include "rk_spi.h"
/* Change to 1 to output registers at the start of each transaction */
#define DEBUG_RK_SPI 0
+struct rockchip_spi_params {
+ /* RXFIFO overruns and TXFIFO underruns stop the master clock */
+ bool master_manages_fifo;
+};
+
struct rockchip_spi_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_rk3288_spi of_plat;
unsigned int max_freq;
unsigned int mode;
ulong last_transaction_us; /* Time of last transaction end */
- u8 bits_per_word; /* max 16 bits per word */
- u8 n_bytes;
unsigned int speed_hz;
unsigned int last_speed_hz;
- unsigned int tmode;
uint input_rate;
};
if (plat->deactivate_delay_us && priv->last_transaction_us) {
ulong delay_us; /* The delay completed so far */
delay_us = timer_get_us() - priv->last_transaction_us;
- if (delay_us < plat->deactivate_delay_us)
- udelay(plat->deactivate_delay_us - delay_us);
+ if (delay_us < plat->deactivate_delay_us) {
+ ulong additional_delay_us =
+ plat->deactivate_delay_us - delay_us;
+ debug("%s: delaying by %ld us\n",
+ __func__, additional_delay_us);
+ udelay(additional_delay_us);
+ }
}
debug("activate cs%u\n", cs);
}
priv->input_rate = ret;
debug("%s: rate = %u\n", __func__, priv->input_rate);
- priv->bits_per_word = 8;
- priv->tmode = TMOD_TR; /* Tx & Rx */
return 0;
}
struct udevice *bus = dev->parent;
struct rockchip_spi_priv *priv = dev_get_priv(bus);
struct rockchip_spi *regs = priv->regs;
- u8 spi_dfs, spi_tf;
uint ctrlr0;
/* Disable the SPI hardware */
- rkspi_enable_chip(regs, 0);
-
- switch (priv->bits_per_word) {
- case 8:
- priv->n_bytes = 1;
- spi_dfs = DFS_8BIT;
- spi_tf = HALF_WORD_OFF;
- break;
- case 16:
- priv->n_bytes = 2;
- spi_dfs = DFS_16BIT;
- spi_tf = HALF_WORD_ON;
- break;
- default:
- debug("%s: unsupported bits: %dbits\n", __func__,
- priv->bits_per_word);
- return -EPROTONOSUPPORT;
- }
+ rkspi_enable_chip(regs, false);
if (priv->speed_hz != priv->last_speed_hz)
rkspi_set_clk(priv, priv->speed_hz);
ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
/* Data Frame Size */
- ctrlr0 |= spi_dfs << DFS_SHIFT;
+ ctrlr0 |= DFS_8BIT << DFS_SHIFT;
/* set SPI mode 0..3 */
if (priv->mode & SPI_CPOL)
ctrlr0 |= FBM_MSB << FBM_SHIFT;
/* Byte and Halfword Transform */
- ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
+ ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
/* Rxd Sample Delay */
ctrlr0 |= 0 << RXDSD_SHIFT;
ctrlr0 |= FRF_SPI << FRF_SHIFT;
/* Tx and Rx mode */
- ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
+ ctrlr0 |= TMOD_TR << TMOD_SHIFT;
writel(ctrlr0, ®s->ctrlr0);
return 0;
}
+static inline int rockchip_spi_16bit_reader(struct udevice *dev,
+ u8 **din, int *len)
+{
+ struct udevice *bus = dev->parent;
+ const struct rockchip_spi_params * const data =
+ (void *)dev_get_driver_data(bus);
+ struct rockchip_spi_priv *priv = dev_get_priv(bus);
+ struct rockchip_spi *regs = priv->regs;
+ const u32 saved_ctrlr0 = readl(®s->ctrlr0);
+#if defined(DEBUG)
+ u32 statistics_rxlevels[33] = { };
+#endif
+ u32 frames = *len / 2;
+ u8 *in = (u8 *)(*din);
+ u32 max_chunk_size = SPI_FIFO_DEPTH;
+
+ if (!frames)
+ return 0;
+
+ /*
+ * If we know that the hardware will manage RXFIFO overruns
+ * (i.e. stop the SPI clock until there's space in the FIFO),
+ * we the allow largest possible chunk size that can be
+ * represented in CTRLR1.
+ */
+ if (data && data->master_manages_fifo)
+ max_chunk_size = 0x10000;
+
+ // rockchip_spi_configure(dev, mode, size)
+ rkspi_enable_chip(regs, false);
+ clrsetbits_le32(®s->ctrlr0,
+ TMOD_MASK << TMOD_SHIFT,
+ TMOD_RO << TMOD_SHIFT);
+ /* 16bit data frame size */
+ clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT);
+
+ /* Update caller's context */
+ const u32 bytes_to_process = 2 * frames;
+ *din += bytes_to_process;
+ *len -= bytes_to_process;
+
+ /* Process our frames */
+ while (frames) {
+ u32 chunk_size = min(frames, max_chunk_size);
+
+ frames -= chunk_size;
+
+ writew(chunk_size - 1, ®s->ctrlr1);
+ rkspi_enable_chip(regs, true);
+
+ do {
+ u32 rx_level = readw(®s->rxflr);
+#if defined(DEBUG)
+ statistics_rxlevels[rx_level]++;
+#endif
+ chunk_size -= rx_level;
+ while (rx_level--) {
+ u16 val = readw(regs->rxdr);
+ *in++ = val & 0xff;
+ *in++ = val >> 8;
+ }
+ } while (chunk_size);
+
+ rkspi_enable_chip(regs, false);
+ }
+
+#if defined(DEBUG)
+ debug("%s: observed rx_level during processing:\n", __func__);
+ for (int i = 0; i <= 32; ++i)
+ if (statistics_rxlevels[i])
+ debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
+#endif
+ /* Restore the original transfer setup and return error-free. */
+ writel(saved_ctrlr0, ®s->ctrlr0);
+ return 0;
+}
+
static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
const u8 *out = dout;
u8 *in = din;
int toread, towrite;
- int ret;
+ int ret = 0;
debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
len, flags);
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev, slave_plat->cs);
+ /*
+ * To ensure fast loading of firmware images (e.g. full U-Boot
+ * stage, ATF, Linux kernel) from SPI flash, we optimise the
+ * case of read-only transfers by using the full 16bits of each
+ * FIFO element.
+ */
+ if (!out)
+ ret = rockchip_spi_16bit_reader(dev, &in, &len);
+
+ /* This is the original 8bit reader/writer code */
while (len > 0) {
- int todo = min(len, 0xffff);
+ int todo = min(len, 0x10000);
rkspi_enable_chip(regs, false);
writel(todo - 1, ®s->ctrlr1);
toread--;
}
}
- ret = rkspi_wait_till_not_busy(regs);
- if (ret)
- break;
+
+ /*
+ * In case that there's a transmit-component, we need to wait
+ * until the control goes idle before we can disable the SPI
+ * control logic (as this will implictly flush the FIFOs).
+ */
+ if (out) {
+ ret = rkspi_wait_till_not_busy(regs);
+ if (ret)
+ break;
+ }
+
len -= todo;
}
*/
};
+const struct rockchip_spi_params rk3399_spi_params = {
+ .master_manages_fifo = true,
+};
+
static const struct udevice_id rockchip_spi_ids[] = {
{ .compatible = "rockchip,rk3288-spi" },
- { .compatible = "rockchip,rk3368-spi" },
- { .compatible = "rockchip,rk3399-spi" },
+ { .compatible = "rockchip,rk3368-spi",
+ .data = (ulong)&rk3399_spi_params },
+ { .compatible = "rockchip,rk3399-spi",
+ .data = (ulong)&rk3399_spi_params },
{ }
};
to effect a reset. The uclass will try all available drivers when
reset_walk() is called.
+config SPL_SYSRESET
+ bool "Enable support for system reset drivers in SPL mode"
+ depends on SYSRESET && SPL_DM
+ help
+ Enable system reset drivers which can be used to reset the CPU or
+ board. Each driver can provide a reset method which will be called
+ to effect a reset. The uclass will try all available drivers when
+ reset_walk() is called.
+
+config TPL_SYSRESET
+ bool "Enable support for system reset drivers in TPL mode"
+ depends on SYSRESET && TPL_DM
+ help
+ Enable system reset drivers which can be used to reset the CPU or
+ board. Each driver can provide a reset method which will be called
+ to effect a reset. The uclass will try all available drivers when
+ reset_walk() is called.
+
if SYSRESET
config SYSRESET_GPIO
bool "Enable support for GPIO reset driver"
- select GPIO
+ select DM_GPIO
help
Reset support via GPIO pin connected reset logic. This is used for
example on Microblaze where reset logic can be controlled via GPIO
#
# (C) Copyright 2016 Cadence Design Systems Inc.
-obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o
obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
#include <errno.h>
#include <sysreset.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3328.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3328.h>
+#include <asm/arch-rockchip/hardware.h>
#include <linux/err.h>
int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
#include <common.h>
#include <dm.h>
+#include <efi_loader.h>
+#include <pch.h>
#include <sysreset.h>
+#include <asm/acpi_s3.h>
#include <asm/io.h>
#include <asm/processor.h>
-#include <efi_loader.h>
-static __efi_runtime int x86_sysreset_request(struct udevice *dev,
- enum sysreset_t type)
+struct x86_sysreset_platdata {
+ struct udevice *pch;
+};
+
+/*
+ * Power down the machine by using the power management sleep control
+ * of the chipset. This will currently only work on Intel chipsets.
+ * However, adapting it to new chipsets is fairly simple. You will
+ * have to find the IO address of the power management register block
+ * in your southbridge, and look up the appropriate SLP_TYP_S5 value
+ * from your southbridge's data sheet.
+ *
+ * This function never returns.
+ */
+int pch_sysreset_power_off(struct udevice *dev)
+{
+ struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
+ struct pch_pmbase_info pm;
+ u32 reg32;
+ int ret;
+
+ if (!plat->pch)
+ return -ENOENT;
+ ret = pch_ioctl(plat->pch, PCH_REQ_PMBASE_INFO, &pm, sizeof(pm));
+ if (ret)
+ return ret;
+
+ /*
+ * Mask interrupts or system might stay in a coma, not executing code
+ * anymore, but not powered off either.
+ */
+ asm("cli");
+
+ /*
+ * Avoid any GPI waking the system from S5* or the system might stay in
+ * a coma
+ */
+ outl(0x00000000, pm.base + pm.gpio0_en_ofs);
+
+ /* Clear Power Button Status */
+ outw(PWRBTN_STS, pm.base + pm.pm1_sts_ofs);
+
+ /* PMBASE + 4, Bit 10-12, Sleeping Type, * set to 111 -> S5, soft_off */
+ reg32 = inl(pm.base + pm.pm1_cnt_ofs);
+
+ /* Set Sleeping Type to S5 (poweroff) */
+ reg32 &= ~(SLP_EN | SLP_TYP);
+ reg32 |= SLP_TYP_S5;
+ outl(reg32, pm.base + pm.pm1_cnt_ofs);
+
+ /* Now set the Sleep Enable bit */
+ reg32 |= SLP_EN;
+ outl(reg32, pm.base + pm.pm1_cnt_ofs);
+
+ for (;;)
+ asm("hlt");
+}
+
+static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
int value;
+ int ret;
switch (type) {
case SYSRESET_WARM:
case SYSRESET_COLD:
value = SYS_RST | RST_CPU | FULL_RST;
break;
+ case SYSRESET_POWER_OFF:
+ ret = pch_sysreset_power_off(dev);
+ if (ret)
+ return ret;
+ return -EINPROGRESS;
default:
return -ENOSYS;
}
return -EINPROGRESS;
}
+static int x86_sysreset_get_last(struct udevice *dev)
+{
+ return SYSRESET_POWER;
+}
+
#ifdef CONFIG_EFI_LOADER
void __efi_runtime EFIAPI efi_reset_system(
enum efi_reset_type reset_type,
efi_status_t reset_status,
unsigned long data_size, void *reset_data)
{
+ int value;
+
+ /*
+ * inline this code since we are not caused in the context of a
+ * udevice and passing NULL to x86_sysreset_request() is too horrible.
+ */
if (reset_type == EFI_RESET_COLD ||
reset_type == EFI_RESET_PLATFORM_SPECIFIC)
- x86_sysreset_request(NULL, SYSRESET_COLD);
- else if (reset_type == EFI_RESET_WARM)
- x86_sysreset_request(NULL, SYSRESET_WARM);
+ value = SYS_RST | RST_CPU | FULL_RST;
+ else /* assume EFI_RESET_WARM since we cannot return an error */
+ value = SYS_RST | RST_CPU;
+ outb(value, IO_PORT_RESET);
/* TODO EFI_RESET_SHUTDOWN */
}
#endif
+static int x86_sysreset_probe(struct udevice *dev)
+{
+ struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
+
+ /* Locate the PCH if there is one. It isn't essential */
+ uclass_first_device(UCLASS_PCH, &plat->pch);
+
+ return 0;
+}
static const struct udevice_id x86_sysreset_ids[] = {
{ .compatible = "x86,reset" },
static struct sysreset_ops x86_sysreset_ops = {
.request = x86_sysreset_request,
+ .get_last = x86_sysreset_get_last,
};
U_BOOT_DRIVER(x86_sysreset) = {
.id = UCLASS_SYSRESET,
.of_match = x86_sysreset_ids,
.ops = &x86_sysreset_ops,
+ .probe = x86_sysreset_probe,
+ .platdata_auto_alloc_size = sizeof(struct x86_sysreset_platdata),
};
if (!ep)
return TEE_ERROR_ITEM_NOT_FOUND;
- value_sz = strlen(ep->data);
+ value_sz = strlen(ep->data) + 1;
memcpy(value, ep->data, value_sz);
return TEE_SUCCESS;
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
+config RENESAS_OSTM_TIMER
+ bool "Renesas RZ/A1 R7S72100 OSTM Timer"
+ depends on TIMER
+ help
+ Enables support for the Renesas OSTM Timer driver.
+ This timer is present on Renesas RZ/A1 R7S72100 SoCs.
+
config X86_TSC_TIMER_EARLY_FREQ
int "x86 TSC timer frequency in MHz when used as the early timer"
depends on X86_TSC_TIMER
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
+obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
#define DW_APB_CURR_VAL 0x4
#define DW_APB_CTRL 0x8
-DECLARE_GLOBAL_DATA_PTR;
-
struct dw_apb_timer_priv {
fdt_addr_t regs;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas RZ/A1 R7S72100 OSTM Timer driver
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <clk.h>
+#include <timer.h>
+
+#define OSTM_CMP 0x00
+#define OSTM_CNT 0x04
+#define OSTM_TE 0x10
+#define OSTM_TS 0x14
+#define OSTM_TT 0x18
+#define OSTM_CTL 0x20
+#define OSTM_CTL_D BIT(1)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ostm_priv {
+ fdt_addr_t regs;
+};
+
+static int ostm_get_count(struct udevice *dev, u64 *count)
+{
+ struct ostm_priv *priv = dev_get_priv(dev);
+
+ *count = timer_conv_64(readl(priv->regs + OSTM_CNT));
+
+ return 0;
+}
+
+static int ostm_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct ostm_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ uc_priv->clock_rate = clk_get_rate(&clk);
+
+ clk_free(&clk);
+#else
+ uc_priv->clock_rate = CONFIG_SYS_CLK_FREQ / 2;
+#endif
+
+ readb(priv->regs + OSTM_CTL);
+ writeb(OSTM_CTL_D, priv->regs + OSTM_CTL);
+
+ setbits_8(priv->regs + OSTM_TT, BIT(0));
+ writel(0xffffffff, priv->regs + OSTM_CMP);
+ setbits_8(priv->regs + OSTM_TS, BIT(0));
+
+ return 0;
+}
+
+static int ostm_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ostm_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_read_addr(dev);
+
+ return 0;
+}
+
+static const struct timer_ops ostm_ops = {
+ .get_count = ostm_get_count,
+};
+
+static const struct udevice_id ostm_ids[] = {
+ { .compatible = "renesas,ostm" },
+ {}
+};
+
+U_BOOT_DRIVER(ostm_timer) = {
+ .name = "ostm-timer",
+ .id = UCLASS_TIMER,
+ .ops = &ostm_ops,
+ .probe = ostm_probe,
+ .of_match = ostm_ids,
+ .ofdata_to_platdata = ostm_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct ostm_priv),
+};
#include <dm.h>
#include <dm/ofnode.h>
#include <mapmem.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-rockchip/timer.h>
#include <dt-structs.h>
#include <timer.h>
#include <asm/io.h>
Select this for Xilinx ZynqMP and similar Platforms.
This wrapper supports Host and Peripheral operation modes.
+config USB_DWC3_MESON_G12A
+ bool "Amlogic Meson G12A USB wrapper"
+ depends on DM_USB && USB_DWC3 && ARCH_MESON
+ imply PHY
+ help
+ Select this for Amlogic Meson G12A Platforms.
+ This wrapper supports Host and Peripheral operation modes.
+
config USB_DWC3_UNIPHIER
bool "DesignWare USB3 Host Support on UniPhier Platforms"
depends on ARCH_UNIPHIER && USB_XHCI_DWC3
obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
+obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o
obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o
obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Amlogic G12A DWC3 Glue layer
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <asm-generic/io.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dwc3-uboot.h>
+#include <generic-phy.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <malloc.h>
+#include <regmap.h>
+#include <usb.h>
+#include "core.h"
+#include "gadget.h"
+#include <reset.h>
+#include <clk.h>
+#include <power/regulator.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+
+/* USB2 Ports Control Registers */
+
+#define U2P_REG_SIZE 0x20
+
+#define U2P_R0 0x0
+ #define U2P_R0_HOST_DEVICE BIT(0)
+ #define U2P_R0_POWER_OK BIT(1)
+ #define U2P_R0_HAST_MODE BIT(2)
+ #define U2P_R0_POWER_ON_RESET BIT(3)
+ #define U2P_R0_ID_PULLUP BIT(4)
+ #define U2P_R0_DRV_VBUS BIT(5)
+
+#define U2P_R1 0x4
+ #define U2P_R1_PHY_READY BIT(0)
+ #define U2P_R1_ID_DIG BIT(1)
+ #define U2P_R1_OTG_SESSION_VALID BIT(2)
+ #define U2P_R1_VBUS_VALID BIT(3)
+
+/* USB Glue Control Registers */
+
+#define USB_R0 0x80
+ #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
+ #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
+ #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
+ #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
+ #define USB_R0_U2D_ACT BIT(31)
+
+#define USB_R1 0x84
+ #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
+ #define USB_R1_U3H_PME_ENABLE BIT(1)
+ #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2)
+ #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7)
+ #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12)
+ #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
+ #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
+ #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
+ #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
+ #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
+
+#define USB_R2 0x88
+ #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
+ #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
+
+#define USB_R3 0x8c
+ #define USB_R3_P30_SSC_ENABLE BIT(0)
+ #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
+ #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
+ #define USB_R3_P30_REF_SSP_EN BIT(13)
+
+#define USB_R4 0x90
+ #define USB_R4_P21_PORT_RESET_0 BIT(0)
+ #define USB_R4_P21_SLEEP_M0 BIT(1)
+ #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
+ #define USB_R4_P21_ONLY BIT(4)
+
+#define USB_R5 0x94
+ #define USB_R5_ID_DIG_SYNC BIT(0)
+ #define USB_R5_ID_DIG_REG BIT(1)
+ #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
+ #define USB_R5_ID_DIG_EN_0 BIT(4)
+ #define USB_R5_ID_DIG_EN_1 BIT(5)
+ #define USB_R5_ID_DIG_CURR BIT(6)
+ #define USB_R5_ID_DIG_IRQ BIT(7)
+ #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
+ #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
+
+enum {
+ USB2_HOST_PHY = 0,
+ USB2_OTG_PHY,
+ USB3_HOST_PHY,
+ PHY_COUNT,
+};
+
+static const char *phy_names[PHY_COUNT] = {
+ "usb2-phy0", "usb2-phy1", "usb3-phy0",
+};
+
+struct dwc3_meson_g12a {
+ struct udevice *dev;
+ struct regmap *regmap;
+ struct clk clk;
+ struct reset_ctl reset;
+ struct phy phys[PHY_COUNT];
+ enum usb_dr_mode otg_mode;
+ enum usb_dr_mode otg_phy_mode;
+ unsigned int usb2_ports;
+ unsigned int usb3_ports;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ struct udevice *vbus_supply;
+#endif
+};
+
+#define U2P_REG_SIZE 0x20
+#define USB_REG_OFFSET 0x80
+
+static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
+ int i, enum usb_dr_mode mode)
+{
+ switch (mode) {
+ case USB_DR_MODE_HOST:
+ case USB_DR_MODE_OTG:
+ case USB_DR_MODE_UNKNOWN:
+ regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
+ U2P_R0_HOST_DEVICE,
+ U2P_R0_HOST_DEVICE);
+ break;
+
+ case USB_DR_MODE_PERIPHERAL:
+ regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
+ U2P_R0_HOST_DEVICE, 0);
+ break;
+ }
+}
+
+static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
+{
+ int i;
+
+ if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
+ priv->otg_phy_mode = USB_DR_MODE_PERIPHERAL;
+ else
+ priv->otg_phy_mode = USB_DR_MODE_HOST;
+
+ for (i = 0 ; i < USB3_HOST_PHY ; ++i) {
+ if (!priv->phys[i].dev)
+ continue;
+
+ regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
+ U2P_R0_POWER_ON_RESET,
+ U2P_R0_POWER_ON_RESET);
+
+ if (i == USB2_OTG_PHY) {
+ regmap_update_bits(priv->regmap,
+ U2P_R0 + (U2P_REG_SIZE * i),
+ U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
+ U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS);
+
+ dwc3_meson_g12a_usb2_set_mode(priv, i,
+ priv->otg_phy_mode);
+ } else
+ dwc3_meson_g12a_usb2_set_mode(priv, i,
+ USB_DR_MODE_HOST);
+
+ regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
+ U2P_R0_POWER_ON_RESET, 0);
+ }
+
+ return 0;
+}
+
+static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
+{
+ regmap_update_bits(priv->regmap, USB_R3,
+ USB_R3_P30_SSC_RANGE_MASK |
+ USB_R3_P30_REF_SSP_EN,
+ USB_R3_P30_SSC_ENABLE |
+ FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) |
+ USB_R3_P30_REF_SSP_EN);
+ udelay(2);
+
+ regmap_update_bits(priv->regmap, USB_R2,
+ USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK,
+ FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15));
+
+ regmap_update_bits(priv->regmap, USB_R2,
+ USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK,
+ FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20));
+
+ udelay(2);
+
+ regmap_update_bits(priv->regmap, USB_R1,
+ USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT,
+ USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);
+
+ regmap_update_bits(priv->regmap, USB_R1,
+ USB_R1_P30_PCS_TX_SWING_FULL_MASK,
+ FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
+}
+
+static void dwc3_meson_g12a_usb_init_mode(struct dwc3_meson_g12a *priv)
+{
+ if (priv->otg_phy_mode == USB_DR_MODE_PERIPHERAL) {
+ regmap_update_bits(priv->regmap, USB_R0,
+ USB_R0_U2D_ACT, USB_R0_U2D_ACT);
+ regmap_update_bits(priv->regmap, USB_R0,
+ USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
+ regmap_update_bits(priv->regmap, USB_R4,
+ USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
+ } else {
+ regmap_update_bits(priv->regmap, USB_R0,
+ USB_R0_U2D_ACT, 0);
+ regmap_update_bits(priv->regmap, USB_R4,
+ USB_R4_P21_SLEEP_M0, 0);
+ }
+}
+
+static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
+{
+ int ret;
+
+ ret = dwc3_meson_g12a_usb2_init(priv);
+ if (ret)
+ return ret;
+
+ regmap_update_bits(priv->regmap, USB_R1,
+ USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
+ FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
+
+ regmap_update_bits(priv->regmap, USB_R5,
+ USB_R5_ID_DIG_EN_0,
+ USB_R5_ID_DIG_EN_0);
+ regmap_update_bits(priv->regmap, USB_R5,
+ USB_R5_ID_DIG_EN_1,
+ USB_R5_ID_DIG_EN_1);
+ regmap_update_bits(priv->regmap, USB_R5,
+ USB_R5_ID_DIG_TH_MASK,
+ FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
+
+ /* If we have an actual SuperSpeed port, initialize it */
+ if (priv->usb3_ports)
+ dwc3_meson_g12a_usb3_init(priv);
+
+ dwc3_meson_g12a_usb_init_mode(priv);
+
+ return 0;
+}
+
+int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode)
+{
+ struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
+
+ if (!priv)
+ return -EINVAL;
+
+ if (mode != USB_DR_MODE_HOST && mode != USB_DR_MODE_PERIPHERAL)
+ return -EINVAL;
+
+ if (!priv->phys[USB2_OTG_PHY].dev)
+ return -EINVAL;
+
+ if (mode == priv->otg_mode)
+ return 0;
+
+ if (mode == USB_DR_MODE_HOST)
+ debug("%s: switching to Host Mode\n", __func__);
+ else
+ debug("%s: switching to Device Mode\n", __func__);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->vbus_supply) {
+ int ret = regulator_set_enable(priv->vbus_supply,
+ (mode == USB_DR_MODE_PERIPHERAL));
+ if (ret)
+ return ret;
+ }
+#endif
+ priv->otg_phy_mode = mode;
+
+ dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode);
+
+ dwc3_meson_g12a_usb_init_mode(priv);
+
+ return 0;
+}
+
+static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
+{
+ int i, ret;
+
+ for (i = 0 ; i < PHY_COUNT ; ++i) {
+ ret = generic_phy_get_by_name(priv->dev, phy_names[i],
+ &priv->phys[i]);
+ if (ret == -ENOENT)
+ continue;
+
+ if (ret)
+ return ret;
+
+ if (i == USB3_HOST_PHY)
+ priv->usb3_ports++;
+ else
+ priv->usb2_ports++;
+ }
+
+ debug("%s: usb2 ports: %d\n", __func__, priv->usb2_ports);
+ debug("%s: usb3 ports: %d\n", __func__, priv->usb3_ports);
+
+ return 0;
+}
+
+static int dwc3_meson_g12a_reset_init(struct dwc3_meson_g12a *priv)
+{
+ int ret;
+
+ ret = reset_get_by_index(priv->dev, 0, &priv->reset);
+ if (ret)
+ return ret;
+
+ ret = reset_assert(&priv->reset);
+ udelay(1);
+ ret |= reset_deassert(&priv->reset);
+ if (ret) {
+ reset_free(&priv->reset);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int dwc3_meson_g12a_clk_init(struct dwc3_meson_g12a *priv)
+{
+ int ret;
+
+ ret = clk_get_by_index(priv->dev, 0, &priv->clk);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_enable(&priv->clk);
+ if (ret) {
+ clk_free(&priv->clk);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static int dwc3_meson_g12a_probe(struct udevice *dev)
+{
+ struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
+ int ret, i;
+
+ priv->dev = dev;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
+ if (ret)
+ return ret;
+
+ ret = dwc3_meson_g12a_clk_init(priv);
+ if (ret)
+ return ret;
+
+ ret = dwc3_meson_g12a_reset_init(priv);
+ if (ret)
+ return ret;
+
+ ret = dwc3_meson_g12a_get_phys(priv);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ ret = device_get_supply_regulator(dev, "vbus-supply",
+ &priv->vbus_supply);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get PHY regulator\n");
+ return ret;
+ }
+
+ if (priv->vbus_supply) {
+ ret = regulator_set_enable(priv->vbus_supply, true);
+ if (ret)
+ return ret;
+ }
+#endif
+
+ priv->otg_mode = usb_get_dr_mode(dev_of_offset(dev));
+
+ ret = dwc3_meson_g12a_usb_init(priv);
+ if (ret)
+ return ret;
+
+ for (i = 0 ; i < PHY_COUNT ; ++i) {
+ if (!priv->phys[i].dev)
+ continue;
+
+ ret = generic_phy_init(&priv->phys[i]);
+ if (ret)
+ goto err_phy_init;
+ }
+
+ return 0;
+
+err_phy_init:
+ for (i = 0 ; i < PHY_COUNT ; ++i) {
+ if (!priv->phys[i].dev)
+ continue;
+
+ generic_phy_exit(&priv->phys[i]);
+ }
+
+ return ret;
+}
+
+static int dwc3_meson_g12a_remove(struct udevice *dev)
+{
+ struct dwc3_meson_g12a *priv = dev_get_platdata(dev);
+ int i;
+
+ reset_release_all(&priv->reset, 1);
+
+ clk_release_all(&priv->clk, 1);
+
+ for (i = 0 ; i < PHY_COUNT ; ++i) {
+ if (!priv->phys[i].dev)
+ continue;
+
+ generic_phy_exit(&priv->phys[i]);
+ }
+
+ return dm_scan_fdt_dev(dev);
+}
+
+static const struct udevice_id dwc3_meson_g12a_ids[] = {
+ { .compatible = "amlogic,meson-g12a-usb-ctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(dwc3_generic_wrapper) = {
+ .name = "dwc3-meson-g12a",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = dwc3_meson_g12a_ids,
+ .probe = dwc3_meson_g12a_probe,
+ .remove = dwc3_meson_g12a_remove,
+ .platdata_auto_alloc_size = sizeof(struct dwc3_meson_g12a),
+
+};
#include <linux/compiler.h>
#include <version.h>
#include <g_dnl.h>
-#include <asm/arch/f_rockusb.h>
+#include <asm/arch-rockchip/f_rockusb.h>
static inline struct f_rockusb *func_to_rockusb(struct usb_function *f)
{
---help---
Enables support for the on-chip EHCI controller on MVEBU SoCs.
+config USB_EHCI_MX5
+ bool "Support for i.MX5 on-chip EHCI USB controller"
+ depends on ARCH_MX5
+ default n
+ help
+ Enables support for the on-chip EHCI controller on i.MX5 SoCs.
+
config USB_EHCI_MX6
bool "Support for i.MX6 on-chip EHCI USB controller"
depends on ARCH_MX6
---help---
Enables support for generic OHCI controller.
+config USB_OHCI_DA8XX
+ bool "Support for da850 OHCI USB controller"
+ help
+ Enable support for the da850 USB controller.
+
endif # USB_OHCI_HCD
config USB_UHCI_HCD
struct usb_ehci *ehci = NULL;
struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
ehci);
-
+#ifdef CONFIG_PPC
+ ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
+#else
ehci = (struct usb_ehci *)priv->hcd_base;
+#endif
+
if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
return -ENXIO;
debug("Can't get the EHCI register base address\n");
return -ENXIO;
}
+#ifdef CONFIG_PPC
+ ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
+#else
ehci = (struct usb_ehci *)priv->hcd_base;
+#endif
hccr = (struct ehci_hccr *)(&ehci->caplength);
hcor = (struct ehci_hcor *)
((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <dm.h>
+#include <power/regulator.h>
#include "ehci.h"
mdelay(50);
}
+#if !CONFIG_IS_ENABLED(DM_USB)
static const struct ehci_ops mx5_ehci_ops = {
.powerup_fixup = mx5_ehci_powerup_fixup,
};
{
return 0;
}
+#else /* CONFIG_IS_ENABLED(DM_USB) */
+struct ehci_mx5_priv_data {
+ struct ehci_ctrl ctrl;
+ struct usb_ehci *ehci;
+ struct udevice *vbus_supply;
+ enum usb_init_type init_type;
+ int portnr;
+};
+
+static const struct ehci_ops mx5_ehci_ops = {
+ .powerup_fixup = mx5_ehci_powerup_fixup,
+};
+
+static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ const char *mode;
+
+ mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
+ if (mode) {
+ if (strcmp(mode, "peripheral") == 0)
+ plat->init_type = USB_INIT_DEVICE;
+ else if (strcmp(mode, "host") == 0)
+ plat->init_type = USB_INIT_HOST;
+ else
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
+ struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
+ enum usb_init_type type = plat->init_type;
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ int ret;
+
+ set_usboh3_clk();
+ enable_usboh3_clk(true);
+ set_usb_phy_clk();
+ enable_usb_phy1_clk(true);
+ enable_usb_phy2_clk(true);
+ mdelay(1);
+
+ priv->ehci = ehci;
+ priv->portnr = dev->seq;
+ priv->init_type = type;
+
+ ret = device_get_supply_regulator(dev, "vbus-supply",
+ &priv->vbus_supply);
+ if (ret)
+ debug("%s: No vbus supply\n", dev->name);
+
+ if (!ret && priv->vbus_supply) {
+ ret = regulator_set_enable(priv->vbus_supply,
+ (type == USB_INIT_DEVICE) ?
+ false : true);
+ if (ret) {
+ puts("Error enabling VBUS supply\n");
+ return ret;
+ }
+ }
+
+ hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ hcor = (struct ehci_hcor *)((uint32_t)hccr +
+ HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
+ setbits_le32(&ehci->usbmode, CM_HOST);
+
+ __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+
+ mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
+ mdelay(10);
+
+ return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
+ priv->init_type);
+}
+
+static const struct udevice_id mx5_usb_ids[] = {
+ { .compatible = "fsl,imx53-usb" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_mx5) = {
+ .name = "ehci_mx5",
+ .id = UCLASS_USB,
+ .of_match = mx5_usb_ids,
+ .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
+ .probe = ehci_usb_probe,
+ .remove = ehci_deregister,
+ .ops = &ehci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct ehci_mx5_priv_data),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif /* !CONFIG_IS_ENABLED(DM_USB) */
*/
#include <common.h>
-
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include "ohci.h"
#include <asm/arch/da8xx-usb.h>
+struct da8xx_ohci {
+ ohci_t ohci;
+ struct clk *clocks; /* clock list */
+ struct phy phy;
+ int clock_count; /* number of clock in clock list */
+};
+
+static int usb_phy_on(void)
+{
+ unsigned long timeout;
+
+ clrsetbits_le32(&davinci_syscfg_regs->cfgchip2,
+ (CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN |
+ CFGCHIP2_OTGPWRDN | CFGCHIP2_OTGMODE |
+ CFGCHIP2_REFFREQ | CFGCHIP2_USB1PHYCLKMUX),
+ (CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN |
+ CFGCHIP2_PHY_PLLON | CFGCHIP2_REFFREQ_24MHZ |
+ CFGCHIP2_USB2PHYCLKMUX | CFGCHIP2_USB1SUSPENDM));
+
+ /* wait until the usb phy pll locks */
+ timeout = get_timer(0);
+ while (get_timer(timeout) < 10) {
+ if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
+ return 1;
+ }
+
+ /* USB phy was not turned on */
+ return 0;
+}
+
+static void usb_phy_off(void)
+{
+ /* Power down the on-chip PHY. */
+ clrsetbits_le32(&davinci_syscfg_regs->cfgchip2,
+ CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM,
+ CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
+ CFGCHIP2_RESET);
+}
+
int usb_cpu_init(void)
{
/* enable psc for usb2.0 */
{
return usb_cpu_stop();
}
+
+#if CONFIG_IS_ENABLED(DM_USB)
+static int ohci_da8xx_probe(struct udevice *dev)
+{
+ struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
+ struct da8xx_ohci *priv = dev_get_priv(dev);
+ int i, err, ret, clock_nb;
+
+ err = 0;
+ priv->clock_count = 0;
+ clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
+
+ if (clock_nb < 0)
+ return clock_nb;
+
+ if (clock_nb > 0) {
+ priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
+ GFP_KERNEL);
+ if (!priv->clocks)
+ return -ENOMEM;
+
+ for (i = 0; i < clock_nb; i++) {
+ err = clk_get_by_index(dev, i, &priv->clocks[i]);
+ if (err < 0)
+ break;
+
+ err = clk_enable(&priv->clocks[i]);
+ if (err) {
+ dev_err(dev, "failed to enable clock %d\n", i);
+ clk_free(&priv->clocks[i]);
+ goto clk_err;
+ }
+ priv->clock_count++;
+ }
+ }
+
+ err = usb_cpu_init();
+
+ if (err)
+ goto clk_err;
+
+ err = ohci_register(dev, regs);
+ if (err)
+ goto phy_err;
+
+ return 0;
+
+phy_err:
+ ret = usb_cpu_stop();
+ if (ret)
+ dev_err(dev, "failed to shutdown usb phy\n");
+
+clk_err:
+ ret = clk_release_all(priv->clocks, priv->clock_count);
+ if (ret)
+ dev_err(dev, "failed to disable all clocks\n");
+
+ return err;
+}
+
+static int ohci_da8xx_remove(struct udevice *dev)
+{
+ struct da8xx_ohci *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = ohci_deregister(dev);
+ if (ret)
+ return ret;
+
+ ret = usb_cpu_stop();
+ if (ret)
+ return ret;
+
+ return clk_release_all(priv->clocks, priv->clock_count);
+}
+
+static const struct udevice_id da8xx_ohci_ids[] = {
+ { .compatible = "ti,da830-ohci" },
+ { }
+};
+
+U_BOOT_DRIVER(ohci_generic) = {
+ .name = "ohci-da8xx",
+ .id = UCLASS_USB,
+ .of_match = da8xx_ohci_ids,
+ .probe = ohci_da8xx_probe,
+ .remove = ohci_da8xx_remove,
+ .ops = &ohci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct da8xx_ohci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
+};
+#endif
return -1;
}
-#if 0
mdelay(10);
/* ohci_dump_status(ohci); */
-#endif
timeout = USB_TIMEOUT_MS(pipe);
csr = readw(&musbr->txcsr);
csr |= MUSB_CSR0_TXPKTRDY;
-#if !defined(CONFIG_SOC_DM365)
csr |= MUSB_CSR0_H_DIS_PING;
-#endif
writew(csr, &musbr->txcsr);
result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
if (result < 0)
/* Set the StatusPkt bit */
csr = readw(&musbr->txcsr);
csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
-#if !defined(CONFIG_SOC_DM365)
csr |= MUSB_CSR0_H_DIS_PING;
-#endif
writew(csr, &musbr->txcsr);
/* Wait until TXPKTRDY bit is cleared */
/* Set the StatusPkt bit and ReqPkt bit */
csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
-#if !defined(CONFIG_SOC_DM365)
csr |= MUSB_CSR0_H_DIS_PING;
-#endif
writew(csr, &musbr->txcsr);
result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
- (1 << LCD_MAX_LOG2_BPP) / 8;
+ (1 << VIDEO_BPP32) / 8;
return 0;
}
static const struct udevice_id ipuv3_video_ids[] = {
{ .compatible = "fsl,imx6q-ipu" },
+ { .compatible = "fsl,imx53-ipu" },
{ }
};
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/grf_rk3288.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
#include <power/regulator.h>
#include "rk_hdmi.h"
#include "rk_mipi.h"
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/hardware.h>
#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/rockchip_mipi_dsi.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3288.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
#define MHz 1000000
#include <regmap.h>
#include <syscon.h>
#include <video.h>
-#include <asm/hardware.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3288.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/hardware.h>
#include "rk_vop.h"
DECLARE_GLOBAL_DATA_PTR;
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/grf_rk3399.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
#include <power/regulator.h>
#include "rk_hdmi.h"
#include "rk_mipi.h"
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/hardware.h>
#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3399.h>
-#include <asm/arch/grf_rk3399.h>
-#include <asm/arch/rockchip_mipi_dsi.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
/* Select mipi dsi source, big or little vop */
static int rk_mipi_dsi_source_select(struct udevice *dev)
#include <dm.h>
#include <regmap.h>
#include <video.h>
-#include <asm/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
#include "rk_vop.h"
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/edp_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/edp_rk3288.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
#include <dt-bindings/clock/rk3288-cru.h>
#define MAX_CR_LOOP 5
#include <regmap.h>
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/hardware.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
#include "rk_hdmi.h"
#include "rk_vop.h" /* for rk_vop_probe_regulators */
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/lvds_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/lvds_rk3288.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/video/rk3288.h>
#include "rk_mipi.h"
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/hardware.h>
#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3399.h>
-#include <asm/arch/grf_rk3399.h>
-#include <asm/arch/rockchip_mipi_dsi.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
DECLARE_GLOBAL_DATA_PTR;
#include <syscon.h>
#include <video.h>
#include <asm/gpio.h>
-#include <asm/hardware.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/edp_rk3288.h>
-#include <asm/arch/vop_rk3288.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/edp_rk3288.h>
+#include <asm/arch-rockchip/vop_rk3288.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <power/regulator.h>
#ifndef __RK_VOP_H__
#define __RK_VOP_H__
-#include <asm/arch/vop_rk3288.h>
+#include <asm/arch-rockchip/vop_rk3288.h>
struct rk_vop_priv {
void *grf;
return 0;
}
+int vidconsole_put_string(struct udevice *dev, const char *str)
+{
+ const char *s;
+ int ret;
+
+ for (s = str; *s; s++) {
+ ret = vidconsole_put_char(dev, *s);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static void vidconsole_putc(struct stdio_dev *sdev, const char ch)
{
struct udevice *dev = sdev->priv;
{
struct udevice *dev = sdev->priv;
- while (*s)
- vidconsole_put_char(dev, *s++);
+ vidconsole_put_string(dev, s);
video_sync(dev->parent, false);
}
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct video_priv *priv = dev_get_uclass_priv(vid);
if (priv->flush_dcache) {
help
Enable driver model for watchdog timer. At the moment the API
is very simple and only supports four operations:
- start, restart, stop and reset (expire immediately).
+ start, stop, reset and expire_now (expire immediately).
What exactly happens when the timer expires is up to a particular
device/driver.
Select this to enable Orion watchdog timer, which can be found on some
Marvell Armada chips.
+config WDT_SP805
+ bool "SP805 watchdog timer support"
+ depends on WDT
+ help
+ Select this to enable SP805 watchdog timer, which can be found on some
+ nxp layerscape chips.
+
config WDT_CDNS
bool "Cadence watchdog timer support"
depends on WDT
config WDT_MT7621
bool "MediaTek MT7621 watchdog timer support"
- depends on WDT && ARCH_MT7620
+ depends on WDT && SOC_MT7628
help
Select this to enable Ralink / Mediatek watchdog timer,
which can be found on some MediaTek chips.
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
#include <common.h>
#include <dm.h>
#include <wdt.h>
+#include <clk.h>
#include <asm/io.h>
/* WDT Value register */
struct bcm6345_wdt_priv {
void __iomem *regs;
+ unsigned long clk_rate;
};
static int bcm6345_wdt_reset(struct udevice *dev)
static int bcm6345_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
{
struct bcm6345_wdt_priv *priv = dev_get_priv(dev);
+ u32 val = priv->clk_rate / 1000 * timeout;
- if (timeout < WDT_VAL_MIN) {
+ if (val < WDT_VAL_MIN) {
debug("watchdog won't fire with less than 2 ticks\n");
- timeout = WDT_VAL_MIN;
- } else if (timeout > WDT_VAL_MAX) {
+ val = WDT_VAL_MIN;
+ } else if (val > WDT_VAL_MAX) {
debug("maximum watchdog timeout exceeded\n");
- timeout = WDT_VAL_MAX;
+ val = WDT_VAL_MAX;
}
- writel(timeout, priv->regs + WDT_VAL_REG);
+ writel(val, priv->regs + WDT_VAL_REG);
return bcm6345_wdt_reset(dev);
}
static int bcm6345_wdt_probe(struct udevice *dev)
{
struct bcm6345_wdt_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
priv->regs = dev_remap_addr(dev);
if (!priv->regs)
return -EINVAL;
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (!ret)
+ priv->clk_rate = clk_get_rate(&clk);
+ else
+ return -EINVAL;
+
bcm6345_wdt_stop(dev);
return 0;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Watchdog driver for SP805 on some Layerscape SoC
+ *
+ * Copyright 2019 NXP
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm/device.h>
+#include <dm/fdtaddr.h>
+#include <dm/read.h>
+#include <linux/bitops.h>
+#include <watchdog.h>
+#include <wdt.h>
+
+#define WDTLOAD 0x000
+#define WDTCONTROL 0x008
+#define WDTINTCLR 0x00C
+#define WDTLOCK 0xC00
+
+#define TIME_OUT_MIN_MSECS 1
+#define TIME_OUT_MAX_MSECS 120000
+#define SYS_FSL_WDT_CLK_DIV 16
+#define INT_ENABLE BIT(0)
+#define RESET_ENABLE BIT(1)
+#define DISABLE 0
+#define UNLOCK 0x1ACCE551
+#define LOCK 0x00000001
+#define INT_MASK BIT(0)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sp805_wdt_priv {
+ void __iomem *reg;
+};
+
+static int sp805_wdt_reset(struct udevice *dev)
+{
+ struct sp805_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(UNLOCK, priv->reg + WDTLOCK);
+ writel(INT_MASK, priv->reg + WDTINTCLR);
+ writel(LOCK, priv->reg + WDTLOCK);
+ readl(priv->reg + WDTLOCK);
+
+ return 0;
+}
+
+static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ u32 load_value;
+ u32 load_time;
+ struct sp805_wdt_priv *priv = dev_get_priv(dev);
+
+ load_time = (u32)timeout;
+ if (timeout < TIME_OUT_MIN_MSECS)
+ load_time = TIME_OUT_MIN_MSECS;
+ else if (timeout > TIME_OUT_MAX_MSECS)
+ load_time = TIME_OUT_MAX_MSECS;
+ /* sp805 runs counter with given value twice, so when the max timeout is
+ * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
+ * not overflow.
+ */
+ load_value = (gd->bus_clk) /
+ (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
+
+ writel(UNLOCK, priv->reg + WDTLOCK);
+ writel(load_value, priv->reg + WDTLOAD);
+ writel(INT_MASK, priv->reg + WDTINTCLR);
+ writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL);
+ writel(LOCK, priv->reg + WDTLOCK);
+ readl(priv->reg + WDTLOCK);
+
+ return 0;
+}
+
+static int sp805_wdt_stop(struct udevice *dev)
+{
+ struct sp805_wdt_priv *priv = dev_get_priv(dev);
+
+ writel(UNLOCK, priv->reg + WDTLOCK);
+ writel(DISABLE, priv->reg + WDTCONTROL);
+ writel(LOCK, priv->reg + WDTLOCK);
+ readl(priv->reg + WDTLOCK);
+
+ return 0;
+}
+
+static int sp805_wdt_probe(struct udevice *dev)
+{
+ debug("%s: Probing wdt%u\n", __func__, dev->seq);
+
+ return 0;
+}
+
+static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sp805_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->reg = (void __iomem *)dev_read_addr(dev);
+ if (IS_ERR(priv->reg))
+ return PTR_ERR(priv->reg);
+
+ return 0;
+}
+
+static const struct wdt_ops sp805_wdt_ops = {
+ .start = sp805_wdt_start,
+ .reset = sp805_wdt_reset,
+ .stop = sp805_wdt_stop,
+};
+
+static const struct udevice_id sp805_wdt_ids[] = {
+ { .compatible = "arm,sp805-wdt" },
+ {}
+};
+
+U_BOOT_DRIVER(sp805_wdt) = {
+ .name = "sp805_wdt",
+ .id = UCLASS_WDT,
+ .of_match = sp805_wdt_ids,
+ .probe = sp805_wdt_probe,
+ .priv_auto_alloc_size = sizeof(struct sp805_wdt_priv),
+ .ofdata_to_platdata = sp805_wdt_ofdata_to_platdata,
+ .ops = &sp805_wdt_ops,
+};
Value of the SPI chip select for environment.
config USE_ENV_SPI_MAX_HZ
- bool "SPI flash bus for environment"
+ bool "SPI flash max frequency for environment"
depends on ENV_IS_IN_SPI_FLASH
help
Force the SPI max work clock for environment.
If not defined, use CONFIG_SF_DEFAULT_SPEED.
config ENV_SPI_MAX_HZ
- int "Value of SPI flash max work for environment"
+ int "Value of SPI flash max frequency for environment"
depends on USE_ENV_SPI_MAX_HZ
help
Value of the SPI max work clock for environment.
It's a string of the EXT4 file name. This file use to store the
environment (explicit path to the file)
-if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARC
+if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARC || ARCH_STM32MP
config ENV_OFFSET
hex "Environment Offset"
#include <env_default.h>
struct hsearch_data env_htab = {
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
+ /* defined in flags.c, only compile with ENV_SUPPORT */
.change_ok = env_flags_validate,
+#endif
};
/*
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
env_reloc();
env_fix_drivers();
- env_htab.change_ok += gd->reloc_off;
+
+ if (env_htab.change_ok)
+ env_htab.change_ok += gd->reloc_off;
#endif
if (gd->env_valid == ENV_INVALID) {
#if defined(CONFIG_ENV_IS_NOWHERE) || defined(CONFIG_SPL_BUILD)
bool "Enable BTRFS filesystem support"
select CRC32C
select LZO
+ select ZSTD
select RBTREE
help
This provides a single-device read-only BTRFS support. BTRFS is a
if (inr == -1ULL) {
printf("Cannot lookup path %s\n", path);
- return 1;
+ return -1;
}
if (type != BTRFS_FT_DIR) {
printf("Not a directory: %s\n", path);
- return 1;
+ return -1;
}
if (btrfs_readdir(&root, inr, readdir_callback)) {
printf("An error occured while listing directory %s\n", path);
- return 1;
+ return -1;
}
return 0;
if (inr == -1ULL) {
printf("Cannot lookup file %s\n", file);
- return 1;
+ return -1;
}
if (type != BTRFS_FT_REG_FILE) {
printf("Not a regular file: %s\n", file);
- return 1;
+ return -1;
}
*size = inode.size;
if (inr == -1ULL) {
printf("Cannot lookup file %s\n", file);
- return 1;
+ return -1;
}
if (type != BTRFS_FT_REG_FILE) {
printf("Not a regular file: %s\n", file);
- return 1;
+ return -1;
}
if (!len)
rd = btrfs_file_read(&root, inr, offset, len, buf);
if (rd == -1ULL) {
printf("An error occured while reading file %s\n", file);
- return 1;
+ return -1;
}
*actread = rd;
BTRFS_COMPRESS_NONE = 0,
BTRFS_COMPRESS_ZLIB = 1,
BTRFS_COMPRESS_LZO = 2,
- BTRFS_COMPRESS_TYPES = 2,
- BTRFS_COMPRESS_LAST = 3,
+ BTRFS_COMPRESS_ZSTD = 3,
+ BTRFS_COMPRESS_TYPES = 3,
+ BTRFS_COMPRESS_LAST = 4,
};
struct btrfs_file_extent_item {
*/
#include "btrfs.h"
+#include <malloc.h>
#include <linux/lzo.h>
+#include <linux/zstd.h>
#include <u-boot/zlib.h>
#include <asm/unaligned.h>
return res;
}
+#define ZSTD_BTRFS_MAX_WINDOWLOG 17
+#define ZSTD_BTRFS_MAX_INPUT (1 << ZSTD_BTRFS_MAX_WINDOWLOG)
+
+static u32 decompress_zstd(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen)
+{
+ ZSTD_DStream *dstream;
+ ZSTD_inBuffer in_buf;
+ ZSTD_outBuffer out_buf;
+ void *workspace;
+ size_t wsize;
+ u32 res = -1;
+
+ wsize = ZSTD_DStreamWorkspaceBound(ZSTD_BTRFS_MAX_INPUT);
+ workspace = malloc(wsize);
+ if (!workspace) {
+ debug("%s: cannot allocate workspace of size %zu\n", __func__,
+ wsize);
+ return -1;
+ }
+
+ dstream = ZSTD_initDStream(ZSTD_BTRFS_MAX_INPUT, workspace, wsize);
+ if (!dstream) {
+ printf("%s: ZSTD_initDStream failed\n", __func__);
+ goto err_free;
+ }
+
+ in_buf.src = cbuf;
+ in_buf.pos = 0;
+ in_buf.size = clen;
+
+ out_buf.dst = dbuf;
+ out_buf.pos = 0;
+ out_buf.size = dlen;
+
+ while (1) {
+ size_t ret;
+
+ ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf);
+ if (ZSTD_isError(ret)) {
+ printf("%s: ZSTD_decompressStream error %d\n", __func__,
+ ZSTD_getErrorCode(ret));
+ goto err_free;
+ }
+
+ if (in_buf.pos >= clen || !ret)
+ break;
+ }
+
+ res = out_buf.pos;
+
+err_free:
+ free(workspace);
+ return res;
+}
+
u32 btrfs_decompress(u8 type, const char *c, u32 clen, char *d, u32 dlen)
{
u32 res;
return decompress_zlib(cbuf, clen, dbuf, dlen);
case BTRFS_COMPRESS_LZO:
return decompress_lzo(cbuf, clen, dbuf, dlen);
+ case BTRFS_COMPRESS_ZSTD:
+ return decompress_zstd(cbuf, clen, dbuf, dlen);
default:
printf("%s: Unsupported compression in extent: %i\n", __func__,
type);
break;
if (btrfs_check_super_csum(raw_sb)) {
- printf("%s: invalid checksum at superblock mirror %i\n",
- __func__, i);
+ debug("%s: invalid checksum at superblock mirror %i\n",
+ __func__, i);
continue;
}
btrfs_super_block_to_cpu(sb);
if (sb->magic != BTRFS_MAGIC) {
- printf("%s: invalid BTRFS magic 0x%016llX at "
- "superblock mirror %i\n", __func__, sb->magic,
- i);
+ debug("%s: invalid BTRFS magic 0x%016llX at "
+ "superblock mirror %i\n", __func__, sb->magic, i);
} else if (sb->bytenr != superblock_offsets[i]) {
printf("%s: invalid bytenr 0x%016llX (expected "
"0x%016llX) at superblock mirror %i\n",
}
if (!btrfs_info.sb.generation) {
- printf("%s: No valid BTRFS superblock found!\n", __func__);
+ debug("%s: No valid BTRFS superblock found!\n", __func__);
return -1;
}
* expected to fail if passed a directory path:
*/
free(fsdata.fatbuf);
- fat_itr_root(itr, &fsdata);
- if (!fat_itr_resolve(itr, filename, TYPE_DIR)) {
+ ret = fat_itr_root(itr, &fsdata);
+ if (ret)
+ goto out_free_itr;
+ ret = fat_itr_resolve(itr, filename, TYPE_DIR);
+ if (!ret)
*size = 0;
- ret = 0;
- }
goto out_free_both;
}
return 1;
}
-static int flush_dir_table(fat_itr *itr);
+static int new_dir_table(fat_itr *itr);
+static int flush_dir(fat_itr *itr);
/*
* Fill dir_slot entries with appropriate name, id, and attr
memcpy(itr->dent, slotptr, sizeof(dir_slot));
slotptr--;
counter--;
+
+ if (itr->remaining == 0)
+ flush_dir(itr);
+
+ /* allocate a cluster for more entries */
if (!fat_itr_next(itr))
- if (!itr->dent && !itr->is_root && flush_dir_table(itr))
+ if (!itr->dent &&
+ (!itr->is_root || itr->fsdata->fatsize == 32) &&
+ new_dir_table(itr))
return -1;
}
- if (!itr->dent && !itr->is_root)
- /*
- * don't care return value here because we have already
- * finished completing an entry with name, only ending up
- * no more entry left
- */
- flush_dir_table(itr);
-
return 0;
}
}
/**
- * set_cluster() - write data to cluster
+ * set_sectors() - write data to sectors
*
- * Write 'size' bytes from 'buffer' into the specified cluster.
+ * Write 'size' bytes from 'buffer' into the specified sector.
*
* @mydata: data to be written
- * @clustnum: cluster to be written to
+ * @startsect: sector to be written to
* @buffer: data to be written
* @size: bytes to be written (but not more than the size of a cluster)
* Return: 0 on success, -1 otherwise
*/
static int
-set_cluster(fsdata *mydata, u32 clustnum, u8 *buffer, u32 size)
+set_sectors(fsdata *mydata, u32 startsect, u8 *buffer, u32 size)
{
- u32 idx = 0;
- u32 startsect;
+ u32 nsects = 0;
int ret;
- if (clustnum > 0)
- startsect = clust_to_sect(mydata, clustnum);
- else
- startsect = mydata->rootdir_sect;
-
- debug("clustnum: %d, startsect: %d\n", clustnum, startsect);
+ debug("startsect: %d\n", startsect);
if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {
ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
size -= mydata->sect_size;
}
} else if (size >= mydata->sect_size) {
- idx = size / mydata->sect_size;
- ret = disk_write(startsect, idx, buffer);
- if (ret != idx) {
+ nsects = size / mydata->sect_size;
+ ret = disk_write(startsect, nsects, buffer);
+ if (ret != nsects) {
debug("Error writing data (got %d)\n", ret);
return -1;
}
- startsect += idx;
- idx *= mydata->sect_size;
- buffer += idx;
- size -= idx;
+ startsect += nsects;
+ buffer += nsects * mydata->sect_size;
+ size -= nsects * mydata->sect_size;
}
if (size) {
return 0;
}
+/**
+ * set_cluster() - write data to cluster
+ *
+ * Write 'size' bytes from 'buffer' into the specified cluster.
+ *
+ * @mydata: data to be written
+ * @clustnum: cluster to be written to
+ * @buffer: data to be written
+ * @size: bytes to be written (but not more than the size of a cluster)
+ * Return: 0 on success, -1 otherwise
+ */
+static int
+set_cluster(fsdata *mydata, u32 clustnum, u8 *buffer, u32 size)
+{
+ return set_sectors(mydata, clust_to_sect(mydata, clustnum),
+ buffer, size);
+}
+
+static int
+flush_dir(fat_itr *itr)
+{
+ fsdata *mydata = itr->fsdata;
+ u32 startsect, sect_offset, nsects;
+
+ if (!itr->is_root || mydata->fatsize == 32)
+ return set_cluster(mydata, itr->clust, itr->block,
+ mydata->clust_size * mydata->sect_size);
+
+ sect_offset = itr->clust * mydata->clust_size;
+ startsect = mydata->rootdir_sect + sect_offset;
+ /* do not write past the end of rootdir */
+ nsects = min_t(u32, mydata->clust_size,
+ mydata->rootdir_size - sect_offset);
+
+ return set_sectors(mydata, startsect, itr->block,
+ nsects * mydata->sect_size);
+}
+
static __u8 tmpbuf_cluster[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN);
/*
}
/*
- * Write directory entries in itr's buffer to block device
+ * Allocate a cluster for additional directory entries
*/
-static int flush_dir_table(fat_itr *itr)
+static int new_dir_table(fat_itr *itr)
{
fsdata *mydata = itr->fsdata;
int dir_newclust = 0;
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
- if (set_cluster(mydata, itr->clust, itr->block, bytesperclust) != 0) {
- printf("error: writing directory entry\n");
- return -1;
- }
dir_newclust = find_empty_cluster(mydata);
set_fatent_value(mydata, itr->clust, dir_newclust);
if (mydata->fatsize == 32)
return itr->dent;
}
- if (!itr->dent && !itr->is_root && flush_dir_table(itr))
+ /* allocate a cluster for more entries */
+ if (!itr->dent &&
+ (!itr->is_root || itr->fsdata->fatsize == 32) &&
+ new_dir_table(itr))
/* indicate that allocating dent failed */
itr->dent = NULL;
return 0;
}
+/**
+ * normalize_longname() - check long file name and convert to lower case
+ *
+ * We assume here that the FAT file system is using an 8bit code page.
+ * Linux typically uses CP437, EDK2 assumes CP1250.
+ *
+ * @l_filename: preallocated buffer receiving the normalized name
+ * @filename: filename to normalize
+ * Return: 0 on success, -1 on failure
+ */
static int normalize_longname(char *l_filename, const char *filename)
{
- const char *p, legal[] = "!#$%&\'()-.@^`_{}~";
- unsigned char c;
- int name_len;
-
- /* Check that the filename is valid */
- for (p = filename; p < filename + strlen(filename); p++) {
- c = *p;
-
- if (('0' <= c) && (c <= '9'))
- continue;
- if (('A' <= c) && (c <= 'Z'))
- continue;
- if (('a' <= c) && (c <= 'z'))
- continue;
- if (strchr(legal, c))
- continue;
- /* extended code */
- if ((0x80 <= c) && (c <= 0xff))
- continue;
+ const char *p, illegal[] = "<>:\"/\\|?*";
+ if (strlen(filename) >= VFAT_MAXLEN_BYTES)
return -1;
- }
- /* Normalize it */
- name_len = strlen(filename);
- if (name_len >= VFAT_MAXLEN_BYTES)
- /* should return an error? */
- name_len = VFAT_MAXLEN_BYTES - 1;
+ for (p = filename; *p; ++p) {
+ if ((unsigned char)*p < 0x20)
+ return -1;
+ if (strchr(illegal, *p))
+ return -1;
+ }
- memcpy(l_filename, filename, name_len);
- l_filename[name_len] = 0; /* terminate the string */
- downcase(l_filename, INT_MAX);
+ strcpy(l_filename, filename);
+ downcase(l_filename, VFAT_MAXLEN_BYTES);
return 0;
}
memset(itr->dent, 0, sizeof(*itr->dent));
- /* Set short name to set alias checksum field in dir_slot */
+ /* Calculate checksum for short name */
set_name(itr->dent, filename);
+
+ /* Set long name entries */
if (fill_dir_slot(itr, filename)) {
ret = -EIO;
goto exit;
}
- /* Set attribute as archive for regular file */
+ /* Set short name entry */
fill_dentry(itr->fsdata, itr->dent, filename, 0, size, 0x20);
retdent = itr->dent;
}
/* Write directory table to device */
- ret = set_cluster(mydata, itr->clust, itr->block,
- mydata->clust_size * mydata->sect_size);
+ ret = flush_dir(itr);
if (ret) {
printf("Error: writing directory entry\n");
ret = -EIO;
memset(dentptr, 0, sizeof(*dentptr));
dentptr->name[0] = 0xe5;
- if (set_cluster(mydata, itr->clust, itr->block,
- mydata->clust_size * mydata->sect_size) != 0) {
+ if (flush_dir(itr)) {
printf("error: writing directory entry\n");
return -EIO;
}
}
/* Write directory table to device */
- ret = set_cluster(mydata, itr->clust, itr->block,
- mydata->clust_size * mydata->sect_size);
+ ret = flush_dir(itr);
if (ret)
printf("Error: writing directory entry\n");
};
struct ahci_ioports {
- void __iomem *cmd_addr;
- void __iomem *scr_addr;
void __iomem *port_mmio;
struct ahci_cmd_hdr *cmd_slot;
struct ahci_sg *cmd_tbl_sg;
--- /dev/null
+/*
+ * This is from the Android Project,
+ * Repository: https://android.googlesource.com/platform/bootable/recovery
+ * File: bootloader_message/include/bootloader_message/bootloader_message.h
+ * Commit: c784ce50e8c10eaf70e1f97e24e8324aef45faf5
+ *
+ * Copyright (C) 2008 The Android Open Source Project
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ANDROID_BOOTLOADER_MESSAGE_H
+#define __ANDROID_BOOTLOADER_MESSAGE_H
+
+/* compiler.h defines the types that otherwise are included from stdint.h and
+ * stddef.h
+ */
+#include <compiler.h>
+
+/* Spaces used by misc partition are as below:
+ * 0 - 2K For bootloader_message
+ * 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used
+ * as bootloader_message_ab struct)
+ * 16K - 64K Used by uncrypt and recovery to store wipe_package for A/B devices
+ * Note that these offsets are admitted by bootloader,recovery and uncrypt, so they
+ * are not configurable without changing all of them. */
+static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0;
+static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024;
+
+/* Bootloader Message (2-KiB)
+ *
+ * This structure describes the content of a block in flash
+ * that is used for recovery and the bootloader to talk to
+ * each other.
+ *
+ * The command field is updated by linux when it wants to
+ * reboot into recovery or to update radio or bootloader firmware.
+ * It is also updated by the bootloader when firmware update
+ * is complete (to boot into recovery for any final cleanup)
+ *
+ * The status field was used by the bootloader after the completion
+ * of an "update-radio" or "update-hboot" command, which has been
+ * deprecated since Froyo.
+ *
+ * The recovery field is only written by linux and used
+ * for the system to send a message to recovery or the
+ * other way around.
+ *
+ * The stage field is written by packages which restart themselves
+ * multiple times, so that the UI can reflect which invocation of the
+ * package it is. If the value is of the format "#/#" (eg, "1/3"),
+ * the UI will add a simple indicator of that status.
+ *
+ * We used to have slot_suffix field for A/B boot control metadata in
+ * this struct, which gets unintentionally cleared by recovery or
+ * uncrypt. Move it into struct bootloader_message_ab to avoid the
+ * issue.
+ */
+struct bootloader_message {
+ char command[32];
+ char status[32];
+ char recovery[768];
+
+ /* The 'recovery' field used to be 1024 bytes. It has only ever
+ * been used to store the recovery command line, so 768 bytes
+ * should be plenty. We carve off the last 256 bytes to store the
+ * stage string (for multistage packages) and possible future
+ * expansion. */
+ char stage[32];
+
+ /* The 'reserved' field used to be 224 bytes when it was initially
+ * carved off from the 1024-byte recovery field. Bump it up to
+ * 1184-byte so that the entire bootloader_message struct rounds up
+ * to 2048-byte. */
+ char reserved[1184];
+};
+
+/**
+ * We must be cautious when changing the bootloader_message struct size,
+ * because A/B-specific fields may end up with different offsets.
+ */
+#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
+static_assert(sizeof(struct bootloader_message) == 2048,
+ "struct bootloader_message size changes, which may break A/B devices");
+#endif
+
+/**
+ * The A/B-specific bootloader message structure (4-KiB).
+ *
+ * We separate A/B boot control metadata from the regular bootloader
+ * message struct and keep it here. Everything that's A/B-specific
+ * stays after struct bootloader_message, which should be managed by
+ * the A/B-bootloader or boot control HAL.
+ *
+ * The slot_suffix field is used for A/B implementations where the
+ * bootloader does not set the androidboot.ro.boot.slot_suffix kernel
+ * commandline parameter. This is used by fs_mgr to mount /system and
+ * other partitions with the slotselect flag set in fstab. A/B
+ * implementations are free to use all 32 bytes and may store private
+ * data past the first NUL-byte in this field. It is encouraged, but
+ * not mandatory, to use 'struct bootloader_control' described below.
+ *
+ * The update_channel field is used to store the Omaha update channel
+ * if update_engine is compiled with Omaha support.
+ */
+struct bootloader_message_ab {
+ struct bootloader_message message;
+ char slot_suffix[32];
+ char update_channel[128];
+
+ /* Round up the entire struct to 4096-byte. */
+ char reserved[1888];
+};
+
+/**
+ * Be cautious about the struct size change, in case we put anything post
+ * bootloader_message_ab struct (b/29159185).
+ */
+#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
+static_assert(sizeof(struct bootloader_message_ab) == 4096,
+ "struct bootloader_message_ab size changes");
+#endif
+
+#define BOOT_CTRL_MAGIC 0x42414342 /* Bootloader Control AB */
+#define BOOT_CTRL_VERSION 1
+
+struct slot_metadata {
+ /* Slot priority with 15 meaning highest priority, 1 lowest
+ * priority and 0 the slot is unbootable. */
+ uint8_t priority : 4;
+ /* Number of times left attempting to boot this slot. */
+ uint8_t tries_remaining : 3;
+ /* 1 if this slot has booted successfully, 0 otherwise. */
+ uint8_t successful_boot : 1;
+ /* 1 if this slot is corrupted from a dm-verity corruption, 0
+ * otherwise. */
+ uint8_t verity_corrupted : 1;
+ /* Reserved for further use. */
+ uint8_t reserved : 7;
+} __attribute__((packed));
+
+/* Bootloader Control AB
+ *
+ * This struct can be used to manage A/B metadata. It is designed to
+ * be put in the 'slot_suffix' field of the 'bootloader_message'
+ * structure described above. It is encouraged to use the
+ * 'bootloader_control' structure to store the A/B metadata, but not
+ * mandatory.
+ */
+struct bootloader_control {
+ /* NUL terminated active slot suffix. */
+ char slot_suffix[4];
+ /* Bootloader Control AB magic number (see BOOT_CTRL_MAGIC). */
+ uint32_t magic;
+ /* Version of struct being used (see BOOT_CTRL_VERSION). */
+ uint8_t version;
+ /* Number of slots being managed. */
+ uint8_t nb_slot : 3;
+ /* Number of times left attempting to boot recovery. */
+ uint8_t recovery_tries_remaining : 3;
+ /* Ensure 4-bytes alignment for slot_info field. */
+ uint8_t reserved0[2];
+ /* Per-slot information. Up to 4 slots. */
+ struct slot_metadata slot_info[4];
+ /* Reserved for further use. */
+ uint8_t reserved1[8];
+ /* CRC32 of all 28 bytes preceding this field (little endian
+ * format). */
+ uint32_t crc32_le;
+} __attribute__((packed));
+
+#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus)
+static_assert(sizeof(struct bootloader_control) ==
+ sizeof(((struct bootloader_message_ab *)0)->slot_suffix),
+ "struct bootloader_control has wrong size");
+#endif
+
+#ifndef __UBOOT__
+
+#ifdef __cplusplus
+
+#include <string>
+#include <vector>
+
+/* Return the block device name for the bootloader message partition and waits
+ * for the device for up to 10 seconds. In case of error returns the empty
+ * string. */
+std::string get_bootloader_message_blk_device(std::string* err);
+
+/* Read bootloader message into boot. Error message will be set in err. */
+bool read_bootloader_message(bootloader_message* boot, std::string* err);
+
+/* Read bootloader message from the specified misc device into boot. */
+bool read_bootloader_message_from(bootloader_message* boot, const std::string& misc_blk_device,
+ std::string* err);
+
+/* Write bootloader message to BCB. */
+bool write_bootloader_message(const bootloader_message& boot, std::string* err);
+
+/* Write bootloader message to the specified BCB device. */
+bool write_bootloader_message_to(const bootloader_message& boot,
+ const std::string& misc_blk_device, std::string* err);
+
+/* Write bootloader message (boots into recovery with the options) to BCB. Will
+ * set the command and recovery fields, and reset the rest. */
+bool write_bootloader_message(const std::vector<std::string>& options, std::string* err);
+
+/* Write bootloader message (boots into recovery with the options) to the specific BCB device. Will
+ * set the command and recovery fields, and reset the rest. */
+bool write_bootloader_message_to(const std::vector<std::string>& options,
+ const std::string& misc_blk_device, std::string* err);
+
+/* Update bootloader message (boots into recovery with the options) to BCB. Will
+ * only update the command and recovery fields. */
+bool update_bootloader_message(const std::vector<std::string>& options, std::string* err);
+
+/* Update bootloader message (boots into recovery with the |options|) in |boot|. Will only update
+ * the command and recovery fields. */
+bool update_bootloader_message_in_struct(bootloader_message* boot,
+ const std::vector<std::string>& options);
+
+/* Clear BCB. */
+bool clear_bootloader_message(std::string* err);
+
+/* Writes the reboot-bootloader reboot reason to the bootloader_message. */
+bool write_reboot_bootloader(std::string* err);
+
+/* Read the wipe package from BCB (from offset WIPE_PACKAGE_OFFSET_IN_MISC). */
+bool read_wipe_package(std::string* package_data, size_t size, std::string* err);
+
+/* Write the wipe package into BCB (to offset WIPE_PACKAGE_OFFSET_IN_MISC). */
+bool write_wipe_package(const std::string& package_data, std::string* err);
+
+#else
+
+#include <stdbool.h>
+
+/* C Interface. */
+bool write_bootloader_message(const char* options);
+bool write_reboot_bootloader(void);
+
+#endif /* ifdef __cplusplus */
+
+#endif /* __UBOOT__ */
+
+#endif /* __ANDROID_BOOTLOADER_MESSAGE_H */
boot_os_fn *bootm_os_get_boot_func(int os);
+#if defined(CONFIG_FIT_SIGNATURE)
int bootm_host_load_images(const void *fit, int cfg_noffset);
+#endif
int boot_selected_os(int argc, char * const argv[], int state,
bootm_headers_t *images, boot_os_fn *boot_fn);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+/*
+ * Structure for the cache controller
+ */
+struct cache_info {
+ phys_addr_t base; /* Base physical address of cache device. */
+};
+
+struct cache_ops {
+ /**
+ * get_info() - Get basic cache info
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @info: Place to put info
+ * @return 0 if OK, -ve on error
+ */
+ int (*get_info)(struct udevice *dev, struct cache_info *info);
+};
+
+#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
+
+/**
+ * cache_get_info() - Get information about a cache controller
+ *
+ * @dev: Device to check (UCLASS_CACHE)
+ * @info: Returns cache info
+ * @return 0 if OK, -ve on error
+ */
+int cache_get_info(struct udevice *dev, struct cache_info *info);
+
+#endif
*
* @src: utf-8 string
* @count: maximum number of code points to convert
- * Return: length in bytes after conversion to utf-16 without the
+ * Return: length in u16 after conversion to utf-16 without the
* trailing \0. If an invalid UTF-8 sequence is hit one
- * word will be reserved for a replacement character.
+ * u16 will be reserved for a replacement character.
*/
size_t utf8_utf16_strnlen(const char *src, size_t count);
* utf8_utf16_strlen() - length of a utf-8 string after conversion to utf-16
*
* @src: utf-8 string
- * Return: length in bytes after conversion to utf-16 without the
- * trailing \0. -1 if the utf-8 string is not valid.
+ * Return: length in u16 after conversion to utf-16 without the
+ * trailing \0. If an invalid UTF-8 sequence is hit one
+ * u16 will be reserved for a replacement character.
*/
#define utf8_utf16_strlen(a) utf8_utf16_strnlen((a), SIZE_MAX)
*
* @src: utf-16 string
* Return: length in bytes after conversion to utf-8 without the
- * trailing \0. -1 if the utf-16 string is not valid.
+ * trailing \0. If an invalid UTF-16 sequence is hit one
+ * byte will be reserved for a replacement character.
*/
#define utf16_utf8_strlen(a) utf16_utf8_strnlen((a), SIZE_MAX)
#ifndef _CLK_H_
#define _CLK_H_
+#include <dm/ofnode.h>
#include <linux/errno.h>
#include <linux/types.h>
*/
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
+/**
+ * clock_get_by_index_nodev - Get/request a clock by integer index
+ * without a device.
+ *
+ * This is a version of clk_get_by_index() that does not use a device.
+ *
+ * @node: The client ofnode.
+ * @index: The index of the clock to request, within the client's list of
+ * clocks.
+ * @clock A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk);
+
/**
* clock_get_bulk - Get/request all clocks of a device.
*
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* about 545KB (1089 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_TERANETICS
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#ifdef CONFIG_CMD_SPI
-# define CONFIG_SYS_DSPI_CS2
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#ifdef CONFIG_CMD_SPI
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
-# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
-#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#ifdef CONFIG_CMD_SPI
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
-# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
-#endif
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SYS_SBFHDR_SIZE 0x13
-#ifdef CONFIG_CMD_SPI
-
-# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1))
-#endif
/* PCI */
#ifdef CONFIG_CMD_PCI
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_TSEC1
#define CONFIG_VSC7385_ENET
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
- SICRH_ESDHC_A_SD |\
- SICRH_ESDHC_B_SD |\
- SICRH_ESDHC_C_SD |\
- SICRH_GPIO_A_TSEC2 |\
- SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
- SICRH_IEEE1588_A_GPIO |\
- SICRH_USB |\
- SICRH_GTM_GPIO |\
- SICRH_IEEE1588_B_GPIO |\
- SICRH_ETSEC2_CRS |\
- SICRH_GPIOSEL_1 |\
- SICRH_TMROBI_V3P3 |\
- SICRH_TSOBI1_V2P5 |\
- SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
-#define CONFIG_SYS_SICRL (\
- SICRL_SPI_PF0 |\
- SICRL_UART_PF0 |\
- SICRL_IRQ_PF0 |\
- SICRL_I2C2_PF0 |\
- SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
/*
* SERDES
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
*/
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit Port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
/* 0xFFFF8396 */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
/* VSC7385 Base address on CS2 */
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 /* 8-bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
- /* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
/* 0xFFFE09FF */
-/* Access window base at VSC7385 base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
-/* Access window size 128K */
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
/*
* Environment Configuration
*/
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
- */
-/*
- * mpc8313epb board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1
-#define CONFIG_MPC831x 1
-#define CONFIG_MPC8313 1
-#define CONFIG_MPC8313ERDB 1
-
-#ifdef CONFIG_NAND
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SPL_MAX_SIZE (4 * 1024)
-#define CONFIG_SPL_PAD_TO 0x4000
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#endif
-
-#endif /* CONFIG_NAND */
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_ELBC 1
-
-/*
- * On-board devices
- *
- * TSEC1 is VSC switch
- * TSEC2 is SoC TSEC
- */
-#define CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
-
-#ifdef CONFIG_SYS_66MHZ
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#elif defined(CONFIG_SYS_33MHZ)
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#else
-#error Unknown oscillator frequency.
-#endif
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
-#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00001000
-#define CONFIG_SYS_MEMTEST_END 0x07f00000
-
-/* Early revs of this board will lock up hard when attempting
- * to access the PMC registers, unless a JTAG debugger is
- * connected, or some resistor modifications are made.
- */
-#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
-/*
- * Device configurations
- */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC1
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE 0xFE7FE000
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-
-/*
- * Manually set up DDR parameters, as this board does not
- * seem to have the SPD connected to I2C.
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (10 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3835a322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (5 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x129048c6 */ /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x05100500 */
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32 \
- | SDRAM_CFG_2T_EN)
- /* 0x43088000 */
-#else
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-#endif
-#define CONFIG_SYS_SDRAM_CFG2 0x00401000
-/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0632 << SDRAM_MODE_SD_SHIFT))
- /* 0x44480632 */
-#define CONFIG_SYS_DDR_MODE_2 0x8000C000
-
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_NOMZ \
- | DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_9 \
- | OR_GPCM_EHTR \
- | OR_GPCM_EAD)
- /* 0xFF006FF7 TODO SLOW 16 MB flash size */
- /* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
- /* 16 MB window size */
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
- !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
- | (0xFF << LBCR_BMT_SHIFT) \
- | 0xF) /* 0x0004ff0f */
-
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
-
-/* drivers/mtd/nand/raw/nand.c */
-#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE 0xE2800000
-#endif
-
-#define CONFIG_MTD_PARTITION
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM \
- (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF8396 */
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#endif
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
-/* local bus write LED / read status buffer (BCSR) mapping */
-#define CONFIG_SYS_BCSR_ADDR 0xFA000000
-#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
- /* map at 0xFA000000 on LCS3 */
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
- /* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFF8FF7 */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
- /* VSC7385 Base address on LCS2 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
-#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFE09FF */
-
- /* Access window base at VSC7385 base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
-
-#endif
-
-#define CONFIG_MPC83XX_GPIO 1
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-/*
- * TSEC
- */
-
-#define CONFIG_GMII /* MII PHY management */
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x1c
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC1_PHYIDX 0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define TSEC2_PHY_ADDR 4
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC2_PHYIDX 0
-#endif
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC1"
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Environment
- */
-#if defined(CONFIG_NAND)
- #define CONFIG_ENV_OFFSET (512 * 1024)
- #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
- #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND \
- (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#elif !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
-
-/* Address and size of Redundant Environment Sector */
-#else
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Command line configuration.
- */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-#ifdef CONFIG_SYS_66MHZ
-
-/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
-/* 0x62040000 */
-#define CONFIG_SYS_HRCW_LOW (\
- 0x20000000 /* reserved, must be set */ |\
- HRCWL_DDRCM |\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
-
-#elif defined(CONFIG_SYS_33MHZ)
-
-/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
-/* 0x65040000 */
-#define CONFIG_SYS_HRCW_LOW (\
- 0x20000000 /* reserved, must be set */ |\
- HRCWL_DDRCM |\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_CSB_TO_CLKIN_5X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
-
-#endif
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_ROM_LOC_NAND_SP_8BIT |\
- HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY)
-#endif
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
- /* Enable Internal USB Phy and GPIO on LCD Connector */
-#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
-
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI2 not supported on 8313 */
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME "mpc8313erdb"
-#define CONFIG_ROOTPATH "/nfs/root/path"
-#define CONFIG_BOOTFILE "uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot.bin"
-#define CONFIG_FDTFILE "mpc8313erdb.dtb"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "ethprime=TSEC1\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
- "$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1
+
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SPL_MAX_SIZE (4 * 1024)
+#define CONFIG_SPL_PAD_TO 0x4000
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_ELBC 1
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is VSC switch
+ * TSEC2 is SoC TSEC
+ */
+#define CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00001000
+#define CONFIG_SYS_MEMTEST_END 0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
+
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC1
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE 0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE 8192
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
+ /* 0x80010102 */
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+ /* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (10 << TIMING_CFG1_REFREC_SHIFT) \
+ | (3 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
+ /* 0x3835a322 */
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (5 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x129048c6 */ /* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+ /* 0x05100500 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_32 \
+ | SDRAM_CFG_2T_EN)
+ /* 0x43088000 */
+#else
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_32)
+ /* 0x43080000 */
+#endif
+#define CONFIG_SYS_SDRAM_CFG2 0x00401000
+/* set burst length to 8 for 32-bit data path */
+#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0632 << SDRAM_MODE_SD_SHIFT))
+ /* 0x44480632 */
+#define CONFIG_SYS_DDR_MODE_2 0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+ /*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
+ | DDRCDR_PZ_NOMZ \
+ | DDRCDR_NZ_NOMZ \
+ | DDRCDR_M_ODR)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
+ !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/* drivers/mtd/nand/raw/nand.c */
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_NAND_BASE 0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE 0xE2800000
+#endif
+
+#define CONFIG_MTD_PARTITION
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+
+/* local bus write LED / read status buffer (BCSR) mapping */
+#define CONFIG_SYS_BCSR_ADDR 0xFA000000
+#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
+ /* map at 0xFA000000 on LCS3 */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+ /* VSC7385 Base address on LCS2 */
+#define CONFIG_SYS_VSC7385_BASE 0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
+
+
+#endif
+
+#define CONFIG_MPC83XX_GPIO 1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/*
+ * TSEC
+ */
+
+#define CONFIG_GMII /* MII PHY management */
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define TSEC1_PHY_ADDR 0x1c
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC1_PHYIDX 0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define TSEC2_PHY_ADDR 4
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC2_PHYIDX 0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OFFSET (512 * 1024)
+#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+ /* Enable Internal USB Phy and GPIO on LCD Connector */
+#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV "eth1"
+
+#define CONFIG_HOSTNAME "mpc8313erdb"
+#define CONFIG_ROOTPATH "/nfs/root/path"
+#define CONFIG_BOOTFILE "uImage"
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot.bin"
+#define CONFIG_FDTFILE "mpc8313erdb.dtb"
+
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" CONFIG_NETDEV "\0" \
+ "ethprime=TSEC1\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
+ "console=ttyS0\0" \
+ "setbootargs=setenv bootargs " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+ "$netdev:off " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv rootdev /dev/nfs;" \
+ "run setbootargs;" \
+ "run setipargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv rootdev /dev/ram;" \
+ "run setbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_ELBC 1
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is VSC switch
+ * TSEC2 is SoC TSEC
+ */
+#define CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+
+#define CONFIG_SYS_MEMTEST_START 0x00001000
+#define CONFIG_SYS_MEMTEST_END 0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
+
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC1
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE 0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE 8192
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
+ /* 0x80010102 */
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+ /* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (10 << TIMING_CFG1_REFREC_SHIFT) \
+ | (3 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
+ /* 0x3835a322 */
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (5 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x129048c6 */ /* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+ /* 0x05100500 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_32 \
+ | SDRAM_CFG_2T_EN)
+ /* 0x43088000 */
+#else
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_32)
+ /* 0x43080000 */
+#endif
+#define CONFIG_SYS_SDRAM_CFG2 0x00401000
+/* set burst length to 8 for 32-bit data path */
+#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0632 << SDRAM_MODE_SD_SHIFT))
+ /* 0x44480632 */
+#define CONFIG_SYS_DDR_MODE_2 0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+ /*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
+ | DDRCDR_PZ_NOMZ \
+ | DDRCDR_NZ_NOMZ \
+ | DDRCDR_M_ODR)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
+ !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/* drivers/mtd/nand/nand.c */
+#define CONFIG_SYS_NAND_BASE 0xE2800000
+
+#define CONFIG_MTD_PARTITION
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+
+/* local bus write LED / read status buffer (BCSR) mapping */
+#define CONFIG_SYS_BCSR_ADDR 0xFA000000
+#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
+ /* map at 0xFA000000 on LCS3 */
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+ /* VSC7385 Base address on LCS2 */
+#define CONFIG_SYS_VSC7385_BASE 0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
+
+
+#endif
+
+#define CONFIG_MPC83XX_GPIO 1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/*
+ * TSEC
+ */
+
+#define CONFIG_GMII /* MII PHY management */
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define TSEC1_PHY_ADDR 0x1c
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC1_PHYIDX 0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define TSEC2_PHY_ADDR 4
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC2_PHYIDX 0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * Environment
+ */
+#if !defined(CONFIG_SYS_RAMBOOT)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+ #define CONFIG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+ /* Enable Internal USB Phy and GPIO on LCD Connector */
+#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV "eth1"
+
+#define CONFIG_HOSTNAME "mpc8313erdb"
+#define CONFIG_ROOTPATH "/nfs/root/path"
+#define CONFIG_BOOTFILE "uImage"
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot.bin"
+#define CONFIG_FDTFILE "mpc8313erdb.dtb"
+
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" CONFIG_NETDEV "\0" \
+ "ethprime=TSEC1\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
+ "console=ttyS0\0" \
+ "setbootargs=setenv bootargs " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+ "$netdev:off " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv rootdev /dev/nfs;" \
+ "run setbootargs;" \
+ "run setipargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv rootdev /dev/ram;" \
+ "run setbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif /* __CONFIG_H */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC831x 1 /* MPC831x CPU family */
-#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
-#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_ROM_LOC_NAND_SP_8BIT |\
- HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY)
-#endif
/*
* System IO Config
#define CONFIG_HWCONFIG
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-#define CONFIG_FSL_ELBC 1
+#define CONFIG_FSL_ELBC
/*
* FLASH on the Local Bus
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM \
- (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF8396 */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
!defined(CONFIG_NAND_SPL)
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
/*
* MMU Setup
*/
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_128M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_8M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#define CONFIG_SYS_IBAT6L 0
-#define CONFIG_SYS_IBAT6U 0
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L 0
-#define CONFIG_SYS_IBAT7U 0
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2_5X1 |\
- HRCWL_CE_PLL_VCO_DIV_2 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
/*
* System IO Config
*/
#define CONFIG_SYS_SICRL 0x00000000
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
-#define CONFIG_SYS_SPCR_OPT 1
-
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFE006FF7 */
+
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#else
-#define CONFIG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#endif
-
-/* Nothing in BAT7 */
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if (CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
-#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2X1 |\
- HRCWL_CE_PLL_VCO_DIV_2 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X3)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-#endif
/*
* System IO Config
*/
#define CONFIG_SYS_SICRL 0x00000000
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfe006ff7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
*/
#define CONFIG_SYS_BCSR 0xF8000000
/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFFE9F7 */
+
/*
* Windows to access PIB via local bus
/* PIB window base 0xF8008000 */
#define CONFIG_SYS_PIB_BASE 0xF8008000
#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
/*
* CS2 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8008801 */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
+
/*
* CS3 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
- CONFIG_SYS_PIB_WINDOW_SIZE) \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8010801 */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
+
/*
* Serial Port
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x family */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
-
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
-#endif /* CONFIG_PCISLAVE */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define CONFIG_SYS_CLK_FREQ 33000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
-#endif
-#endif
-
-#define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
*/
#undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#undef CONFIG_DDR_2T_TIMING
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
- /* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
*/
#define CONFIG_SYS_BCSR 0xE2400000
/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0x00000801 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_CLEAR \
- | OR_GPCM_EHTR_CLEAR)
- /* 0xFFFFE8F0 */
+
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
- * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
- */
-#undef CONFIG_SYS_LB_SDRAM
-
-#ifdef CONFIG_SYS_LB_SDRAM
-/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
- | BR_PS_32 /* 32-bit port */ \
- | BR_MS_SDRAM /* MSEL = SDRAM */ \
- | BR_V) /* Valid */
- /* 0xF0001861 */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
- | OR_SDRAM_XAM \
- | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
- | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
- | OR_SDRAM_EAD)
- /* 0xFC006901 */
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
- | LSDMR_BSMA1516 \
- | LSDMR_RFCR8 \
- | LSDMR_PRETOACT6 \
- | LSDMR_ACTTORW3 \
- | LSDMR_BL8 \
- | LSDMR_WRC3 \
- | LSDMR_CL3)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-#endif
-
/*
* Serial Port
*/
#if defined(CONFIG_PCI)
-#define PCI_ONE_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
-
#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif /* PCI_64BIT */
-#endif /* CONFIG_PCISLAVE */
-
/*
* System performance
*/
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_INSTRUCTION_CACHE)
-
-/* #define CONFIG_SYS_HID0_FINAL (\
- HID0_ENABLE_INSTRUCTION_CACHE |\
- HID0_ENABLE_M_BIT |\
- HID0_ENABLE_ADDRESS_BROADCAST) */
-
-#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
-#endif
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
#endif
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * mpc8349emds board configuration file
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC /* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
+
+/*
+ * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
+ * unselect it to use old spd_sdram.c
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x52
+#define SPD_EEPROM_ADDRESS2 0x51
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
+ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#undef CONFIG_DDR_2T_TIMING
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+#else
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE 256 /* MB */
+#if defined(CONFIG_DDR_II)
+#define CONFIG_SYS_DDRCDR 0x80080001
+#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
+#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
+#define CONFIG_SYS_DDR_TIMING_0 0x00220802
+#define CONFIG_SYS_DDR_TIMING_1 0x38357322
+#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
+#define CONFIG_SYS_DDR_MODE 0x47d00432
+#define CONFIG_SYS_DDR_MODE2 0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
+#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#else
+#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1 0x36332321
+#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+ /* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE 0x00000023
+#else
+/* the default burst length is 4 - for 64-bit data path */
+ /* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE 0x00000022
+#endif
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
+ */
+#define CONFIG_SYS_BCSR 0xE2400000
+ /* Access window base at BCSR base */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
+
+/*
+ * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
+ */
+
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port-size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ */
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ * 64MB mask for AM, OR2[0:7] = 1111 1100
+ * XAM, OR2[17:18] = 11
+ * 9 columns OR2[19-21] = 010
+ * 13 rows OR2[23-25] = 100
+ * EAD set for extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+
+ /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT 0x32000000
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
+ | LSDMR_BSMA1516 \
+ | LSDMR_RFCR8 \
+ | LSDMR_PRETOACT6 \
+ | LSDMR_ACTTORW3 \
+ | LSDMR_BL8 \
+ | LSDMR_WRC3 \
+ | LSDMR_CL3)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+
+/* SPI */
+#undef CONFIG_SOFT_SPI /* SPI bit-banged */
+
+/* GPIOs. Used as SPI chip selects */
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
+#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/* USB */
+#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_83XX_PCI_STREAMING
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CONFIG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+/*
+ * System performance
+ */
+#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
+#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_HOSTNAME "mpc8349emds"
+#define CONFIG_ROOTPATH "/nfsroot/rootfs"
+#define CONFIG_BOOTFILE "uImage"
+
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=mpc8349emds\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
+ "update=protect off fe000000 fe03ffff; " \
+ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
+ "upd=run load update\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=mpc834x_mds.dtb\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
-#define CONFIG_SYS_LOWBOOT
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
-#define CONFIG_MPC8349 /* MPC8349 specific */
-
-#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
-
#define CONFIG_MISC_INIT_F
/*
* On-board devices
*/
-#ifdef CONFIG_MPC8349ITX
+#ifdef CONFIG_TARGET_MPC8349ITX
/* The CF card interface on the back of the board */
#define CONFIG_COMPACT_FLASH
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x2000
* BRx, ORx, LBLAWBARx, and LBLAWARx
*/
-/* Flash */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
#endif
-/* LED */
#define CONFIG_SYS_LED_BASE 0xF9000000
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_9 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
+
/* Compact Flash */
#define CONFIG_SYS_CF_BASE 0xF0000000
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
- | BR_PS_16 \
- | BR_MS_UPMA \
- | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
#endif
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
/*
* Serial Port
*/
#endif
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#endif
-
/* TSEC */
#ifdef CONFIG_TSEC_ENET
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
/*
* System performance
*/
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
/* USB DR as device + USB MPH as host */
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
-#define CONFIG_SYS_HID0_INIT 0x00000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
-
-#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI */
-#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L 0
-#define CONFIG_SYS_IBAT1U 0
-#define CONFIG_SYS_IBAT2L 0
-#define CONFIG_SYS_IBAT2U 0
-#endif
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L 0
-#define CONFIG_SYS_IBAT3U 0
-#define CONFIG_SYS_IBAT4L 0
-#define CONFIG_SYS_IBAT4U 0
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L 0
-#define CONFIG_SYS_IBAT7U 0
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH "u-boot.bin"
-#ifdef CONFIG_MPC8349ITX
+#ifdef CONFIG_TARGET_MPC8349ITX
#define CONFIG_FDTFILE "mpc8349emitx.dtb"
#else
#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
-#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66MHz, then
- * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_6X1 |\
- HRCWL_CORE_TO_CSB_1_5X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#endif
-
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-
-/* System Priority Control Register */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
/*
* IP blocks clock configuration
#define CONFIG_HWCONFIG
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_FSL_ELBC 1
/*
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFE000FF7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
*/
#define CONFIG_SYS_BCSR 0xF8000000
/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8000801 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFFE9F7 */
/*
* NAND Flash on the Local Bus
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
- | OR_FCM_BCTLD \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_RST \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF919E */
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+
/*
* Serial Port
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
- | BATU_BL_8M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
-#define CONFIG_MPC837XERDB 1
#define CONFIG_HWCONFIG
*/
#define CONFIG_VSC7385_ENET
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_PCIE
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_5X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#endif
-
/* System performance - define the value i.e. CONFIG_SYS_XXX
*/
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
-/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
-
/* System Clock Configuration Register */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
*/
#define CONFIG_SYS_OBIR 0x30100000
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
/*
* Device configurations
*/
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_FSL_ELBC 1
/*
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_9 \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFF800191 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
* NAND Flash on the Local Bus
*/
#define CONFIG_SYS_NAND_BASE 0xE0600000
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfffe09ff */
-
- /* Access Base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
#endif
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
- | BATU_BL_8M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* L2 Switch: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#ifndef __ASSEMBLY__
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#ifndef __ASSEMBLY__
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
/*
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
#define CONFIG_ALTIVEC 1
/*
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
#define CONFIG_ALTIVEC 1
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHY_ATHEROS
#endif
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* about 825KB (1650 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_TERANETICS
#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_QE
/* Default address of microcode for the Linux FMan driver */
#if defined(CONFIG_SPIFLASH)
/*
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#define CONFIG_SYS_QE_FW_ADDR 0x130000
#elif defined(CONFIG_SDCARD)
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
#endif
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_SYS_DPAA_FMAN
-#ifdef CONFIG_TARGET_T1024RDB
-#define CONFIG_QE
-#endif
/* Default address of microcode for the Linux FMan driver */
#if defined(CONFIG_SPIFLASH)
/*
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#define CONFIG_SYS_QE_FW_ADDR 0x130000
#elif defined(CONFIG_SDCARD)
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
#endif
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHY_REALTEK
#if defined(CONFIG_TARGET_T1024RDB)
#define RGMII_PHY1_ADDR 0x2
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#define CONFIG_QE
/* Default address of microcode for the Linux Fman driver */
#if defined(CONFIG_SPIFLASH)
/*
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* about 825KB (1650 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
#endif
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#define CONFIG_QE
#define CONFIG_U_QE
/* Default address of microcode for the Linux Fman driver */
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#endif
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#define CONFIG_CORTINA_FW_ADDR 0x120000
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_CORTINA_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_CORTINA_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_CORTINA_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHY_CORTINA
#define CONFIG_PHY_REALTEK
#define CONFIG_CORTINA_FW_LENGTH 0x40000
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_TERANETICS
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_CORTINA
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x specific */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
-
-/* IMMR Base Address Register, use Freescale default: 0xff400000 */
-#define CONFIG_SYS_IMMR 0xff400000
-
-/* System clock. Primary input clock when in PCI host mode */
-#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
-
-/*
- * Local Bus LCRR
- * LCRR: DLL bypass, Clock divider is 8
- *
- * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
- *
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
/* board pre init: do not call, nothing to do */
* DDR Setup
*/
/* DDR is system memory*/
-#define CONFIG_SYS_DDR_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
-/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
- | BR_MS_GPCM \
- | BR_PS_32 \
- | BR_V)
-
-/* FLASH timing (0x0000_0c54) */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV4 \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_TRLX)
-
-#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
- | CONFIG_SYS_OR_TIMING_FLASH)
-
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
-
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
/* disable remaining mappings */
#define CONFIG_SYS_BR1_PRELIM 0x00000000
#define CONFIG_SYS_OR1_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
#define CONFIG_SYS_BR2_PRELIM 0x00000000
#define CONFIG_SYS_OR2_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
#define CONFIG_SYS_BR3_PRELIM 0x00000000
#define CONFIG_SYS_OR3_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
/*
* Monitor config
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-/* i-cache and d-cache disabled */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR 0 - 512M */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* stack in DCACHE @ 512M (no backing mem) */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-
/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
- | BATU_BL_16M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#define CONFIG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
#endif
-/* IMMRBAR */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
- | BATU_BL_1M \
- | BATU_VS \
- | BATU_VP)
-
-/* FLASH */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
#define CONFIG_LOADCMD "fatload"
#define CONFIG_RFSPART "2"
-#define CONFIG_SUPPORT_EMMC_BOOT
-
#include "mx6_common.h"
#include <linux/sizes.h>
#define CONFIG_NET_RETRY_COUNT 10
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
-#define CONFIG_SUPPORT_EMMC_BOOT
-
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* SD/MMC support */
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
/*
* SATA Configs
*/
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x20000000\0" \
- "fdt_addr_r=0x12000000\0" \
+ "fdt_addr_r=0x12100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x11000000\0" \
"pxefile_addr_r=0x17100000\0" \
- "ramdisk_addr_r=0x12100000\0" \
+ "ramdisk_addr_r=0x12200000\0" \
"scriptaddr=0x17000000\0"
#define NFS_BOOTCMD \
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
-#define CONFIG_SYS_DCACHE_OFF
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
#include "exynos5250-common.h"
#include <configs/exynos5-common.h>
-/* SD/MMC configuration */
-#define CONFIG_SUPPORT_EMMC_BOOT
-
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-
#define CONFIG_PREBOOT
#define CONFIG_S5P_PA_SYSRAM 0x02020000
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
-/* Power */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-
#endif /* __CONFIG_H */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-/* Enable cache controller */
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#ifdef CONFIG_PRE_CON_BUF_SZ
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
/* DT blob (fdt) address */
-#define CONFIG_SYS_FDT_BASE 0x000f0000
+#define CONFIG_SYS_FDT_BASE 0x800f0000
/*
* Physical Memory Map
#define CONFIG_USBID_ADDR 0x34052c46
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_L2CACHE_OFF
#endif /* __BCM23550_W1D_H */
#include "bcmstb.h"
-#define BCMSTB_SDHCI_BASE 0xf0200300
#define BCMSTB_TIMER_LOW 0xf0412008
#define BCMSTB_TIMER_HIGH 0xf041200c
#define BCMSTB_TIMER_FREQUENCY 0xf0412020
#include "bcmstb.h"
-#define BCMSTB_SDHCI_BASE 0xf03e0200
#define BCMSTB_TIMER_LOW 0xf0412008
#define BCMSTB_TIMER_HIGH 0xf041200c
#define BCMSTB_TIMER_FREQUENCY 0xf0412020
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif /* CONFIG_NAND */
/*
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif /* CONFIG_NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
#endif /* CONFIG_NAND */
/*
/*#define CONFIG_MACH_TYPE 3589*/
#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/
-/* MMC/SD IP block */
-#if defined(CONFIG_EMMC_BOOT)
- #define CONFIG_SUPPORT_EMMC_BOOT
-#endif /* CONFIG_EMMC_BOOT */
-
/*
* When we have NAND flash we expect to be making use of mtdparts,
* both for ease of use in U-Boot and for passing information on to
#define NANDTGTS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
-"cfgscr=nand read ${cfgaddr} cfgscr && source ${cfgaddr}\0" \
+"cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \
+" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
"nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \
"root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \
"b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \
#ifdef CONFIG_ENV_IS_IN_MMC
#define MMCTGTS \
MMCSPI_TGTS \
-"cfgscr=mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr}\0"
+"cfgscr=mw ${dtbaddr} 0;" \
+" mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
+" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
#else
#define MMCTGTS ""
#endif /* CONFIG_MMC */
#ifdef CONFIG_SPI
#define SPITGTS \
MMCSPI_TGTS \
-"cfgscr=sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr}\0"
+"cfgscr=mw ${dtbaddr} 0;" \
+" sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \
+" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
#else
#define SPITGTS ""
#endif /* CONFIG_SPI */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * esd vme8349 U-Boot configuration file
+ * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
+ *
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * reinhard.arlt@esd-electronics.de
+ * Based on the MPC8349EMDS config.
+ */
+
+/*
+ * vme8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+
+/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
+
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_SYS_READ_SPD vme8349_read_spd
+#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
+ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
+ | DDRCDR_ODT \
+ | DDRCDR_Q_DRN)
+ /* 0x80080001 */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
+
+
+#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
+
+#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
+
+#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+
+#if defined(CONFIG_PCI)
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0xFIXME
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII /* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_PHY_M88E1111
+#define TSEC1_PHY_ADDR 0x08
+#define TSEC2_PHY_ADDR 0x10
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CONFIG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_RTC_BUS_NUM 0x01
+#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#define CONFIG_RTC_RX8025
+
+/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR 0x00100000
+#define CONFIG_SYS_GPIO1_DAT 0x00100000
+
+#define CONFIG_SYS_GPIO2_PRELIM
+#define CONFIG_SYS_GPIO2_DIR 0x78900000
+#define CONFIG_SYS_GPIO2_DAT 0x70100000
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME "VME8349"
+#define CONFIG_ROOTPATH "/tftpboot/rootfs"
+#define CONFIG_BOOTFILE "uImage"
+
+#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=vme8349\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
+ "update=protect off fff00000 fff3ffff; " \
+ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+ "upd=run load update\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=vme8349.dtb\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#ifndef __ASSEMBLY__
+int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len);
+#endif
+
+#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011-2014 OMICRON electronics GmbH
- *
- * Based on da850evm.h. Original Copyrights follow:
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
-
-/*
- * SoC Configuration
- */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
-#define CONFIG_SYS_WDT_PERIOD_LOW \
- (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
-#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
-#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
-
-/*
- * PLL configuration
- */
-
-#define CONFIG_SYS_DA850_PLL0_PLLM \
- ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
-#define CONFIG_SYS_DA850_PLL1_PLLM \
- ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
-
-/*
- * DDR2 memory configuration
- */
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
- DV_DDR_PHY_EXT_STRBEN | \
- (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
- (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
- (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
- (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
- (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
- (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
- (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
- (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \
- (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
-
-/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
-
-#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
- (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
- (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
- (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
- (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
- (1 << DV_DDR_SDTMR1_WTR_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
- (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
- (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
- (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
- (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
- (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
- (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
- (2 << DV_DDR_SDTMR2_CKE_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF
-#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
-
-/*
- * Flash memory timing
- */
-
-#define CONFIG_SYS_DA850_CS2CFG ( \
- DAVINCI_ABCR_WSETUP(2) | \
- DAVINCI_ABCR_WSTROBE(5) | \
- DAVINCI_ABCR_WHOLD(3) | \
- DAVINCI_ABCR_RSETUP(1) | \
- DAVINCI_ABCR_RSTROBE(14) | \
- DAVINCI_ABCR_RHOLD(0) | \
- DAVINCI_ABCR_TA(3) | \
- DAVINCI_ABCR_ASIZE_16BIT)
-
-/* single 64 MB NOR flash device connected to CS2 and CS3 */
-#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
-
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
- DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
- DAVINCI_SYSCFG_SUSPSRC_UART2 | \
- DAVINCI_SYSCFG_SUSPSRC_EMAC | \
- DAVINCI_SYSCFG_SUSPSRC_I2C)
-
-/* memtest start addr */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
-
-/* memtest will be run on 16MB */
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
-#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
-#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */
-#define CONFIG_SYS_MAX_FLASH_SECT \
- ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
-
-/*
- * Network & Ethernet Configuration
- */
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-/*
- * U-Boot general configuration
- */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_LOADADDR 0xc0700000
-#define CONFIG_MX_CYCLIC
-
-/*
- * Linux Information
- */
-#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
-#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
-#define CONFIG_RESET_TO_RETRY
-
-/*
- * Default environment settings
- * gpio0 = button, gpio1 = led green, gpio2 = led red
- * verify = n ... disable kernel checksum verification for faster booting
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "tftpdir=calimero\0" \
- "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \
- "erase 0x60800000 +0x400000; " \
- "cp.b $loadaddr 0x60800000 $filesize\0" \
- "flashrootfs=" \
- "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \
- "erase 0x60c00000 +0x2e00000; " \
- "cp.b $loadaddr 0x60c00000 $filesize\0" \
- "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \
- "protect off all; " \
- "erase 0x60000000 +0x80000; " \
- "cp.b $loadaddr 0x60000000 $filesize\0" \
- "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \
- "erase 0x60080000 +0x780000; " \
- "cp.b $loadaddr 0x60080000 $filesize\0" \
- "erase_persistent=erase 0x63a00000 +0x600000;\0" \
- "bootnor=setenv bootargs console=ttyS2,115200n8 " \
- "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
- "rootwait ethaddr=$ethaddr; " \
- "gpio c 1; gpio s 2; bootm 0x60800000\0" \
- "bootrlk=gpio s 1; gpio s 2;" \
- "setenv bootargs console=ttyS2,115200n8 " \
- "ethaddr=$ethaddr; bootm 0x60080000\0" \
- "boottftp=setenv bootargs console=ttyS2,115200n8 " \
- "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
- "rootwait ethaddr=$ethaddr; " \
- "tftpboot $loadaddr $tftpdir/uImage;" \
- "gpio c 1; gpio s 2; bootm $loadaddr\0" \
- "checkupdate=if test -n $update_flag; then " \
- "echo Previous update failed - starting RLK; " \
- "run bootrlk; fi; " \
- "if test -n $initial_setup; then " \
- "echo Running initial setup procedure; " \
- "sleep 1; run flashall; fi\0" \
- "product=accessory\0" \
- "serial=XX12345\0" \
- "checknor=" \
- "if gpio i 0; then run bootnor; fi;\0" \
- "checkrlk=" \
- "if gpio i 0; then run bootrlk; fi;\0" \
- "checkbutton=" \
- "run checknor; sleep 1;" \
- "run checknor; sleep 1;" \
- "run checknor; sleep 1;" \
- "run checknor; sleep 1;" \
- "run checknor;" \
- "gpio s 1; gpio s 2;" \
- "echo ---- Release button to boot RLK ----;" \
- "run checkrlk; sleep 1;" \
- "run checkrlk; sleep 1;" \
- "run checkrlk; sleep 1;" \
- "run checkrlk; sleep 1;" \
- "run checkrlk; sleep 1;" \
- "run checkrlk;" \
- "echo ---- Factory reset requested ----;" \
- "gpio c 1;" \
- "setenv factory_reset true;" \
- "saveenv;" \
- "run bootnor;\0" \
- "flashall=run flashrlk;" \
- "run flashkernel;" \
- "run flashrootfs;" \
- "setenv erase_datafs true;" \
- "setenv initial_setup;" \
- "saveenv;" \
- "run bootnor;\0" \
- "verify=n\0" \
- "clearenv=protect off all;" \
- "erase 0x60040000 +0x40000;\0" \
- "altbootcmd=run bootrlk\0"
-
-#define CONFIG_PREBOOT \
- "echo Version: $ver; " \
- "echo Serial: $serial; " \
- "echo MAC: $ethaddr; " \
- "echo Product: $product; " \
- "gpio c 1; gpio c 2;"
-
-/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
-/* initial stack pointer in internal SRAM */
-#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
-
-#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
-
-#ifndef __ASSEMBLY__
-int calimain_get_osc_freq(void);
-#endif
-
-#include <asm/arch/hardware.h>
-
-#endif /* __CONFIG_H */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x003f8000
-#define BOOT_DEVICE_SPI 10
-
#define CONFIG_SPL_BOARD_LOAD_IMAGE
-#define BOOT_DEVICE_BOARD 11
#endif /* __CONFIG_H */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x003f8000
+#define CONFIG_TPL_TEXT_BASE 0xfffd8000
+
#endif /* __CONFIG_H */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#endif
/* USB Configs */
*/
#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_SUPPORT_EMMC_BOOT
-#endif
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 CompuLab, Ltd.
- * Author: Igor Grinberg <grinberg@compulab.co.il>
- *
- * Configuration settings for the CompuLab CM-T3517 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_CM_T3517 /* working with CM-T3517 */
-
-/*
- * This is needed for the DMA stuff.
- * Although the default iss 64, we still define it
- * to be on the safe side once the default is changed.
- */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-/*
- * The early kernel mapping on ARM currently only maps from the base of DRAM
- * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
- * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
- * so that leaves DRAM base to DRAM base + 0x4000 available.
- */
-#define CONFIG_SYS_BOOTMAPSZ 0x4000
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SERIAL_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/* USB */
-
-#ifndef CONFIG_USB_MUSB_AM35X
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
-#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
-#endif /* CONFIG_USB_MUSB_AM35X */
-
-/* commands to include */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS 0
-#define CONFIG_I2C_MULTI_BUS
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access nand at */
- /* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
- /* devices */
-
-/* Environment information */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "baudrate=115200\0" \
- "console=ttyO2,115200n8\0" \
- "netretry=yes\0" \
- "mpurate=auto\0" \
- "vram=12M\0" \
- "dvimode=1024x768MR-16@60\0" \
- "defaultdisplay=dvi\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
- "mmcrootfstype=ext4\0" \
- "nandroot=/dev/mtdblock4 rw\0" \
- "nandrootfstype=ubifs\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "nandargs=setenv bootargs console=${console} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 2a0000 400000; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_TIMESTAMP
-#define CONFIG_SYS_AUTOLOAD "no"
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
-
-/*
- * AM3517 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define CONFIG_SYS_CS0_SIZE (256 << 20)
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_ADDR 0x260000
-
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define CONFIG_ARP_TIMEOUT 200UL
-#define CONFIG_NET_RETRY_COUNT 5
-#endif /* CONFIG_CMD_NET */
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/* Status LED */
-#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
-
-/* Display Configuration */
-#define LCD_BPP LCD_COLOR16
-
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASHIMAGE_GUARD
-#define CONFIG_BMP_16BPP
-#define CONFIG_SCF0403_LCD
-
-/* EEPROM */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256
-
-#endif /* __CONFIG_H */
/* Enhance our eMMC support / experience. */
#define CONFIG_HSMMC2_8BIT
-#define CONFIG_SUPPORT_EMMC_BOOT
/* SATA Boot related defines */
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2019 Toradex AG
*
* Configuration settings for the Colibri iMX6ULL module.
*
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
/* Network */
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-
#define CONFIG_IP_DEFRAG
#define CONFIG_TFTP_BLOCKSIZE 16352
#define CONFIG_TFTP_TSIZE
/* ENET1 */
#define IMX_FEC_BASE ENET2_BASE_ADDR
-/* MMC Config*/
+/* MMC Config */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
- "fdt_addr_r=0x82000000\0" \
+ "fdt_addr_r=0x82100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"pxefile_addr_r=0x87100000\0" \
- "ramdisk_addr_r=0x82100000\0" \
+ "ramdisk_addr_r=0x82200000\0" \
"scriptaddr=0x87000000\0"
#define NFS_BOOTCMD \
#define CONFIG_VIDEO_BMP_LOGO
#endif
-#endif
+#endif /* __COLIBRI_IMX6ULL_CONFIG_H */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
/* Network */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
#define EMMC_BOOTCMD \
- "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
+ "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\
+ "rw,noatime rootfstype=ext4 " \
"rootwait\0" \
- "emmcboot=run setup; " \
+ "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
"${vidargs}; echo Booting from internal eMMC chip...; " \
- "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
+ "run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \
+ "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
- "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+ "emmcbootpart=1\0" \
+ "emmcdev=0\0" \
+ "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
+ "${fdt_addr_r} ${fdt_file} && " \
+ "setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \
+ "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
+ "emmcrootpart=2\0"
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
- "fdt_addr_r=0x12000000\0" \
+ "fdt_addr_r=0x12100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x11000000\0" \
"pxefile_addr_r=0x17100000\0" \
- "ramdisk_addr_r=0x12100000\0" \
+ "ramdisk_addr_r=0x12200000\0" \
"scriptaddr=0x17000000\0"
#define NFS_BOOTCMD \
"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
#define SD_BOOTCMD \
- "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
- "rootwait\0" \
- "sdboot=run setup; " \
+ "set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} rw,noatime " \
+ "rootfstype=ext4 rootwait\0" \
+ "sdboot=run setup; run sdfinduuid; run set_sdargs; " \
"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
"${vidargs}; echo Booting from SD card; " \
- "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
- "${boot_file} && run fdt_fixup && " \
+ "run sddtbload; load mmc ${sddev}:${sdbootpart} "\
+ "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
- "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+ "sdbootpart=1\0" \
+ "sddev=1\0" \
+ "sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
+ "${fdt_addr_r} ${fdt_file} && setenv dtbparam \" - " \
+ "${fdt_addr_r}\" && true\0" \
+ "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
+ "sdrootpart=2\0"
#define USB_BOOTCMD \
- "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \
- "rootwait\0" \
- "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
+ "set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} rw,noatime " \
+ "rootfstype=ext4 rootwait\0" \
+ "usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \
+ "setenv bootargs ${defargs} ${setupargs} " \
"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
- "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
+ "run usbdtbload; " \
+ "load usb ${usbdev}:${usbbootpart} ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
- "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
- "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+ "usbbootpart=1\0" \
+ "usbdev=0\0" \
+ "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \
+ "${fdt_addr_r} " \
+ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && " \
+ "true\0" \
+ "usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \
+ "usbrootpart=2\0"
#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
+ USB_BOOTCMD \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \
#define CONFIG_SYS_FSL_USDHC_NUM 1
#elif CONFIG_TARGET_COLIBRI_IMX7_EMMC
#define CONFIG_SYS_FSL_USDHC_NUM 2
-
-#define CONFIG_SUPPORT_EMMC_BOOT
#endif
#undef CONFIG_BOOTM_PLAN9
/* Avoid overwriting factory configuration block */
#define CONFIG_BOARD_SIZE_LIMIT 0x40000
-/* We will never enable dcache because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
/*
* Environment settings
*/
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
* env, so we got 0x110000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#elif defined(CONFIG_SDCARD)
/*
* about 825KB (1650 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#elif defined(CONFIG_NAND)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_TERANETICS
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_CRS305_1G_4S_H
+#define _CONFIG_CRS305_1G_4S_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 96
+
+#endif /* _CONFIG_CRS305_1G_4S_H */
* about 825KB (1650 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#endif
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_ENV_SIZE (16 << 10)
#endif
+/* USB Configs */
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "da850evm"
+
#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board configuration file for Variscite DART-6UL Evaluation Kit
+ * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ */
+#ifndef __DART_6UL_H
+#define __DART_6UL_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/* NAND pin conflicts with usdhc2 */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_ENET_DEV 0
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x3
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "eth1"
+#endif
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+/* Environment settings */
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_OFFSET (14 * SZ_64K)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+
+/* Environment in SD */
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 0
+#define MMC_ROOTFS_DEV 0
+#define MMC_ROOTFS_PART 2
+
+/* Console configs */
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* I2C configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE SZ_512M
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#define CONFIG_IMX_THERMAL
+
+#define ENV_MMC \
+ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
+ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
+ "fitpart=1\0" \
+ "bootdelay=3\0" \
+ "silent=1\0" \
+ "optargs=rw rootwait\0" \
+ "mmcautodetect=yes\0" \
+ "mmcrootfstype=ext4\0" \
+ "mmcfit_name=fitImage\0" \
+ "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
+ "${mmcfit_name}\0" \
+ "mmcargs=setenv bootargs " \
+ "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
+ "console=${console} rootfstype=${mmcrootfstype}\0" \
+ "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "console=ttymxc0,115200n8\0" \
+ "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
+ "fit_addr=0x82000000\0" \
+ ENV_MMC
+
+#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#endif /* __DART_6UL_H */
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_SYS_DCACHE_OFF
-
#endif /* _CONFIG_DB_88F6281_BP_H */
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SUPPORT_EMMC_BOOT
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* SPI SPL */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
-#define CONFIG_SUPPORT_EMMC_BOOT
-
/* USB xHCI HOST */
#define CONFIG_USB_XHCI_OMAP
* it has to be done after each HCD reset */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-/* Support all possible USB ethernet dongles */
-
-/* Extra Commands */
-/* Enable that for switching of boot partitions */
-/* Disabled by default as some sub-commands can brick eMMC */
-/*#define CONFIG_SUPPORT_EMMC_BOOT */
-
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-#define CONFIG_USE_SPIFLASH
-#define CONFIG_SYS_USE_NAND
-#define CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
-#define CONFIG_PREBOOT
-
-/*
- * SoC Configuration
- */
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 4*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
-#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
-
-/* memtest start addr */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
-
-/* memtest will be run on 16MB */
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
-
-/*
- * I2C Configuration
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-
-/*
- * Network & Ethernet Configuration
- */
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_ENV_OFFSET 0x80000
-#define CONFIG_ENV_SECT_SIZE (64 << 10)
-#endif
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_VIDEO_DA8XX
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-/*
- * U-Boot general configuration
- */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_MX_CYCLIC
-
-/*
- * Linux Information
- */
-#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-/* NAND Setup */
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_NO_SUBPAGE
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
-#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#endif
-
-#if !defined(CONFIG_SYS_USE_NAND) && \
- !defined(CONFIG_USE_NOR) && \
- !defined(CONFIG_USE_SPIFLASH)
-#define CONFIG_ENV_SIZE (16 << 10)
-#endif
-
-/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define CONFIG_HOSTNAME "ea20"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "as=3\0" \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "rfsbargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rfsbpath}\0" \
- "testrfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${testrfspath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw initrd=" \
- "0x${ramdisk_addr_r},4M\0" \
- "mtdids=nand0=davinci_nand.0\0" \
- "serverip=192.168.5.249\0" \
- "ipaddr=192.168.5.248\0" \
- "rootpath=/opt/eldk/arm\0" \
- "splashpos=230,180\0" \
- "testrfspath=/opt/eldk/test_arm\0" \
- "nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc " \
- "ubi.mtd=${as} root=ubi0:rootfs\0" \
- "nandrwargs=setenv bootargs rootfstype=ubifs rw chk_data_crc " \
- "ubi.mtd=${as} root=ubi0:rootfs\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=${consoledev},${baudrate}n8\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "addmem=setenv bootargs ${bootargs} mem=${memory}\0" \
- "consoledev=ttyS0\0" \
- "loadaddr=c0000014\0" \
- "memory=32M\0" \
- "kernel_addr_r=c0700000\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
- "ramdisk_file=" CONFIG_HOSTNAME "/image.ext2\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
- "bootm ${kernel_addr_r}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc addmem;" \
- "bootm ${kernel_addr_r}\0" \
- "net_rfsb=tftp ${kernel_addr_r} ${bootfile}; " \
- "run rfsbargs addip addtty addmtd addmisc addmem; " \
- "bootm ${kernel_addr_r}\0" \
- "net_testrfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run testrfsargs addip addtty addmtd addmisc addmem; " \
- "bootm ${kernel_addr_r}\0" \
- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "nand_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
- "ubifsload ${kernel_addr_r} /boot/uImage;" \
- "ubifsumount; run nandargs addip addtty " \
- "addmtd addmisc addmem;clrlogo;" \
- "bootm ${kernel_addr_r}\0" \
- "nand_nandrw=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
- "ubifsload ${kernel_addr_r} /boot/uImage;" \
- "ubifsumount; run nandrwargs addip addtty " \
- "addmtd addmisc addmem;clrlogo;" \
- "bootm ${kernel_addr_r}\0" \
- "net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs" \
- " addip addtty addmtd addmisc addmem;" \
- "clrlogo;bootm ${kernel_addr_r}\0" \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
- "load_magic=if sf probe 0;then sf " \
- "read c0000000 0x10000 0x60000;fi\0" \
- "load_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
- "if ubifsload c0000014 /boot/u-boot.bin;" \
- "then mw c0000008 ${filesize};else echo Error reading" \
- " u-boot from nand!;fi\0" \
- "load_net=if sf probe 0;then sf read c0000000 0x10000 " \
- "0x60000;tftp c0000014 ${u-boot};" \
- "mw c0000008 ${filesize};fi\0" \
- "upd=if sf probe 0;then sf erase 10000 60000;" \
- "sf write c0000000 10000 60000;fi\0" \
- "ublupdate=if tftp C0700000 ${ublname};then sf probe 0; " \
- "sf erase 0 10000;" \
- "sf write 0xc0700000 0 ${filesize};fi\0" \
- "ubootupd_net=if run load_net;then echo Updating u-boot;" \
- "if run upd; then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \
- "bootcmd=run net_testrfs\0"
-
-#include <asm/arch/hardware.h>
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 8D Technologies inc.
- * Based on mt_ventoux.h, original banner below:
- *
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2009 TechNexion Ltd.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tam3517-common.h"
-
-/* Our console port is port3 */
-#undef CONFIG_SYS_NS16550_COM1
-
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-
-#define CONFIG_MACH_TYPE MACH_TYPE_ECO5_PK
-
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_HOSTNAME "eco5pk"
-
-/*
- * Set its own mtdparts, different from common
- */
-
-/*
- * The arithmetic in tam3517.h is wrong for us and the kernel gets overwritten.
- */
-#undef CONFIG_ENV_OFFSET_REDUND
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_SYS_ENV_SECT_SIZE)
-
-#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
- "install_kernel=if dhcp $bootfile; then nand erase kernel;" \
- "nand write $fileaddr kernel; fi\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
- "serverip=192.168.142.60\0"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas Solutions ECOVEC board
- *
- * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
- * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
- * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- */
-
-#ifndef __ECOVEC_H
-#define __ECOVEC_H
-
-/*
- * Address Interface BusWidth
- *-----------------------------------------
- * 0x0000_0000 U-Boot 16bit
- * 0x0004_0000 Linux romImage 16bit
- * 0x0014_0000 MTD for Linux 16bit
- * 0x0400_0000 Internal I/O 16/32bit
- * 0x0800_0000 DRAM 32bit
- * 0x1800_0000 MFI 16bit
- */
-
-#define CONFIG_CPU_SH7724 1
-
-#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
-
-#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
-#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
-#define CONFIG_SYS_I2C_SH_SPEED0 100000
-#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
-#define CONFIG_SYS_I2C_SH_SPEED1 100000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 41666666
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT (0)
-#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
-#define CONFIG_PHY_SMSC 1
-#define CONFIG_BITBANGMII
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-/* USB / R8A66597 */
-#define CONFIG_USB_R8A66597_HCD
-#define CONFIG_R8A66597_BASE_ADDR 0xA4D80000
-#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
-#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
-#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
-#define CONFIG_SUPERH_ON_CHIP_R8A66597
-
-/* undef to save memory */
-/* Monitor Command Prompt */
-/* Buffer size for Console output */
-#define CONFIG_SYS_PBSIZE 256
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_SCIF 1
-#define CONFIG_CONS_SCIF0 1
-
-/* Suppress display of console information at boot */
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE (0x88000000)
-#define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
-/* Enable alternate, more extensive, memory test */
-/* Scratch address used by the alternate memory test */
-#undef CONFIG_SYS_MEMTEST_SCRATCH
-
-/* Enable temporary baudrate change while serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BASE (0xA0000000)
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-/* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
-/* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
-/* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
-/* Timeout for Flash clear lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
-
-/*
- * Use hardware flash sectors protection instead
- * of U-Boot software protection
- */
-#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
-/* Monitor size */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* ENV setting */
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 41666666
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-#endif /* __ECOVEC_H */
#define CONFIG_ENV_SIZE (64 * 1024)
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024)
-#define CONFIG_SUPPORT_EMMC_BOOT
/* RTC */
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
/* MarSBoard */
#define CONFIG_FDTFILE "imx6q-marsboard.dtb"
#include <configs/rk3368_common.h>
#define CONFIG_CONSOLE_SCROLL_LINES 10
+#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#include <configs/rk322x_common.h>
-
-/* Store env in emmc */
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 0
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#ifndef CONFIG_SPL_BUILD
-/* Enable gpt partition table */
-#undef PARTS_DEFAULT
-#define PARTS_DEFAULT \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=loader_a,start=4M,size=4M,uuid=${uuid_gpt_loader};" \
- "name=loader_b,size=4M,uuid=${uuid_gpt_reserved};" \
- "name=trust_a,size=4M,uuid=${uuid_gpt_reserved};" \
- "name=trust_b,size=4M,uuid=${uuid_gpt_reserved};" \
- "name=misc,size=4M,uuid=${uuid_gpt_misc};" \
- "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \
- "name=boot_a,size=32M,uuid=${uuid_gpt_boot_a};" \
- "name=boot_b,size=32M,uuid=${uuid_gpt_boot_b};" \
- "name=system_a,size=818M,uuid=${uuid_gpt_system_a};" \
- "name=system_b,size=818M,uuid=${uuid_gpt_system_b};" \
- "name=vendor_a,size=50M,uuid=${uuid_gpt_vendor_a};" \
- "name=vendor_b,size=50M,uuid=${uuid_gpt_vendor_b};" \
- "name=cache,size=100M,uuid=${uuid_gpt_cache};" \
- "name=persist,size=4M,uuid=${uuid_gpt_persist};" \
- "name=userdata,size=-,uuid=${uuid_gpt_userdata};\0" \
-
-#define CONFIG_PREBOOT
-
-#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-
-#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND \
- "mmc read 0x61000000 0x8000 0x5000;" \
- "bootm 0x61000000" \
-
-/* Enable atags */
-#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
-#define CONFIG_INITRD_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-
-#endif
+#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030
-#define CONFIG_SUPPORT_EMMC_BOOT
/* specific .lds file */
/* High Level Configuration Options */
#define CONFIG_MX35
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
/* Set TEXT at the beginning of the NOR flash */
--- /dev/null
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
+
+/*
+ * Memory test
+ * TODO: Migrate!
+ */
+#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x07e00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+
+/* TODO: Turn into string option and migrate to Kconfig */
+#define CONFIG_HOSTNAME "gazerbeam"
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS1\0" \
+ "u-boot=u-boot.bin\0" \
+ "kernel_addr=1000000\0" \
+ "fdt_addr=C00000\0" \
+ "fdtfile=hrcon.dtb\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+ " +${filesize};cp.b ${fileaddr} " \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "upd=run load update\0" \
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp ${kernel_addr} $bootfile;" \
+ "tftp ${fdt_addr} $fdtfile;" \
+ "bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_MMCBOOTCOMMAND \
+ "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
+ "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
+ "bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+
+#endif /* __CONFIG_H */
#define CONFIG_MXC_UART_BASE UART3_BASE
#define CONSOLE_DEV "ttymxc2"
-#define CONFIG_SUPPORT_EMMC_BOOT
-
-
#include "mx6_common.h"
#include <linux/sizes.h>
* Commands configuration
*/
-/* Disable DCACHE */
-#define CONFIG_SYS_DCACHE_OFF
-
/* Network configuration */
#ifdef CONFIG_CMD_NET
#define CONFIG_ARMADA100_FEC
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Renesas GRPEACH board
+ *
+ * Copyright (C) 2017-2019 Renesas Electronics
+ */
+
+#ifndef __GRPEACH_H
+#define __GRPEACH_H
+
+/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+/* Serial Console */
+#define CONFIG_BAUDRATE 115200
+
+/* Miscellaneous */
+#define CONFIG_SYS_PBSIZE 256
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_ARCH_CPU_INIT
+
+/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET 0x80000
+
+/* Malloc */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+/* Kernel Boot */
+#define CONFIG_BOOTARGS "ignore_loglevel"
+
+/* Network interface */
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 0
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+#endif /* __GRPEACH_H */
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-/* eMMC Configs */
-#define CONFIG_SUPPORT_EMMC_BOOT
-
/*
* SATA Configs
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
#define CONFIG_SYS_TIMER_RATE (150000000/256)
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_HRCON 1 /* HRCON board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
- SICRH_ESDHC_A_SD |\
- SICRH_ESDHC_B_SD |\
- SICRH_ESDHC_C_SD |\
- SICRH_GPIO_A_GPIO |\
- SICRH_GPIO_B_GPIO |\
- SICRH_IEEE1588_A_GPIO |\
- SICRH_USB |\
- SICRH_GTM_GPIO |\
- SICRH_IEEE1588_B_GPIO |\
- SICRH_ETSEC2_GPIO |\
- SICRH_GPIOSEL_1 |\
- SICRH_TMROBI_V3P3 |\
- SICRH_TSOBI1_V2P5 |\
- SICRH_TSOBI2_V2P5) /* 0x0037f103 */
-#define CONFIG_SYS_SICRL (\
- SICRL_SPI_PF0 |\
- SICRL_UART_PF0 |\
- SICRL_IRQ_PF0 |\
- SICRL_I2C2_PF0 |\
- SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
/*
* SERDES
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-/*
- * FPGA
- */
-#define CONFIG_SYS_FPGA0_BASE 0xE0600000
-#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
-
-/* Window base at FPGA base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
-
-#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k) 0x0010
#define CONFIG_SYS_FPGA_COUNT 1
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
/*
* Environment Configuration
*/
/*
* High Level Configuration Options
*/
-#define CONFIG_MPC831x
-#define CONFIG_MPC8313
-
#define CONFIG_FSL_ELBC
#define CONFIG_BOOT_RETRY_TIME 900
#define CONFIG_BOOT_RETRY_MIN 30
#define CONFIG_RESET_TO_RETRY
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-#define CONFIG_SYS_IMMR 0xF0000000
-
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.000MHz, then
- * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
- */
-#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_8BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_MII |\
- HRCWH_TSEC2M_IN_MII |\
- HRCWH_BIG_ENDIAN)
-
#define CONFIG_SYS_SICRH 0x00000000
#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
#define CONFIG_HWCONFIG
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
- HID0_ENABLE_INSTRUCTION_CACHE |\
- HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
-
/*
* Definitions for initial stack pointer and data area (in DCACHE )
*/
- CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
- (0xFF << LBCR_BMT_SHIFT) |\
- 0xF)
-
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
/*
* Internal Definitions
*/
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
/*
* Manually set up DDR parameters,
#define CONFIG_SYS_FLASH_BASE 0xFF800000
#define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
- BR_PS_8 |\
- BR_MS_GPCM |\
- BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- OR_GPCM_SCY_10 |\
- OR_GPCM_EHTR |\
- OR_GPCM_TRLX |\
- OR_GPCM_CSNT |\
- OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define NAND_CACHE_PAGES 64
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
- (2<<BR_DECC_SHIFT) |\
- BR_PS_8 |\
- BR_MS_FCM |\
- BR_V)
-
-#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
- OR_FCM_PGS |\
- OR_FCM_CSCT |\
- OR_FCM_CST |\
- OR_FCM_CHT |\
- OR_FCM_SCY_4 |\
- OR_FCM_TRLX |\
- OR_FCM_EHTR |\
- OR_FCM_RST)
/*
* MRAM setup
*/
#define CONFIG_SYS_MRAM_BASE 0xE2000000
#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
#define CONFIG_SYS_OR_TIMING_MRAM
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
- BR_PS_8 |\
- BR_MS_GPCM |\
- BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
/*
* CPLD setup
*/
#define CONFIG_SYS_CPLD_BASE 0xE3000000
#define CONFIG_SYS_CPLD_SIZE 0x8000
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
#define CONFIG_SYS_OR_TIMING_MRAM
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
- BR_PS_8 |\
- BR_MS_GPCM |\
- BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
/*
* HW-Watchdog
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SYS_SCCR_USBDRCM 3
-/*
- * BAT's
- */
-#define CONFIG_HIGH_BATS
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
- BATL_PP_10)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
- BATU_BL_256M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* Initial RAM @ 0xFD000000 */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
- BATL_PP_10 |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
- BATU_BL_256K |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH @ 0xFF800000 */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
- BATL_PP_10 |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
- BATU_BL_8M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
- BATL_PP_10 |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* IMMRBAR @ 0xF0000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
- BATL_PP_10 |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
- BATU_BL_128M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
-#define CONFIG_SYS_IBAT6L (0xE0000000 |\
- BATL_PP_10 |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xE0000000 |\
- BATU_BL_256M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
/*
* U-Boot environment setup
*/
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console},${baudrate}" \
- " root=PARTUUID=${uuid} rootwait rw\0 ${mtdparts}\0" \
+ " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
"nandargs=setenv bootargs console=${console},${baudrate}" \
- " ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
+ " ubi.mtd=fs root=${nandroot} ${mtdparts} ${optargs}\0" \
"ramargs=setenv bootargs console=${console},${baudrate}" \
- " root=/dev/ram rw ${mtdparts}\0" \
+ " root=/dev/ram rw ${mtdparts} ${optargs}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...;" \
/* MMC */
#define CONFIG_SYS_MMC_ENV_DEV 2
-#define CONFIG_SUPPORT_EMMC_BOOT
/* Ethernet */
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_MXC_GPIO
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8QM_MEK_H
+#define __IMX8QM_MEK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_TEXT_BASE 0x0
+#define CONFIG_SPL_MAX_SIZE (124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
+
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x013E000
+#define CONFIG_SPL_BSS_START_ADDR 0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
+#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
+#define CONFIG_MALLOC_F_ADDR 0x00120000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_OF_EMBED
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define USDHC1_BASE_ADDR 0x5B010000
+#define USDHC2_BASE_ADDR 0x5B020000
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "panel=NULL\0" \
+ "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
+ "fdt_addr=0x83000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "boot_fdt=try\0" \
+ "fdt_file=fsl-imx8qxp-mek.dtb\0" \
+ "initrd_addr=0x83800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "echo wait for boot; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "booti; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
+
+/* Default environment is in SD */
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_OFFSET (64 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_2 0x880000000
+#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
+#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE 115200
+
+/* Monitor Command Prompt */
+#define CONFIG_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 8000000 /* 8MHz */
+
+/* Networking */
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define FEC_QUIRK_ENET_MAC
+
+#endif /* __IMX8QM_MEK_H */
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_MALLOC_F_ADDR 0x00120000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_ENV_OVERWRITE
"script=boot.scr\0" \
"image=Image\0" \
"panel=NULL\0" \
- "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
+ "console=ttyLP0,${baudrate} earlycon\0" \
"fdt_addr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
- "fdt_file=fsl-imx8qxp-mek.dtb\0" \
+ "fdt_file=imx8qxp-mek.dtb\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
#define CONFIG_BAUDRATE 115200
/* Monitor Command Prompt */
-#define CONFIG_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- * Based on:
- * U-Boot:include/configs/da850evm.h
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-
-/*
- * SoC Configuration
- */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
-
-/* memtest start addr */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
-
-/* memtest will be run on 16MB */
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
-
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
- DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
- DAVINCI_SYSCFG_SUSPSRC_UART2 | \
- DAVINCI_SYSCFG_SUSPSRC_UART0 | \
- DAVINCI_SYSCFG_SUSPSRC_EMAC)
-
-/*
- * PLL configuration
- */
-
-#define CONFIG_SYS_DA850_PLL0_PLLM 24
-#define CONFIG_SYS_DA850_PLL1_PLLM 24
-
-/*
- * DDR2 memory configuration
- */
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
- DV_DDR_PHY_EXT_STRBEN | \
- (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498
-
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
-#define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
-
-#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
- (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
- (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
- (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
- (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
- (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
- (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
- (1 << DV_DDR_SDTMR1_WTR_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
- (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
- (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
- (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
- (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
- (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
- (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
- (2 << DV_DDR_SDTMR2_CKE_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
- (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
- (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
- (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
- (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
- (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
- (2 << DV_DDR_SDCR_CL_SHIFT) | \
- (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
- (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
-
-#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
- DAVINCI_ABCR_WSTROBE(2) | \
- DAVINCI_ABCR_WHOLD(0) | \
- DAVINCI_ABCR_RSETUP(1) | \
- DAVINCI_ABCR_RSTROBE(2) | \
- DAVINCI_ABCR_RHOLD(1) | \
- DAVINCI_ABCR_TA(0) | \
- DAVINCI_ABCR_ASIZE_8BIT)
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-
-/*
- * Flash & Environment
- */
-#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
- CONFIG_SYS_NAND_U_BOOT_SIZE - \
- CONFIG_SYS_MALLOC_LEN - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS { \
- 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
- 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
- 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
- 54, 55, 56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 10
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_LOAD
-
-/*
- * Network & Ethernet Configuration
- */
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-/*
- * U-Boot general configuration
- */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_MX_CYCLIC
-
-/*
- * Linux Information
- */
-#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
- "root=/dev/mtdblock5 rw noinitrd " \
- "rootfstype=jffs2 noinitrd\0" \
- "hwconfig=dsp:wake=yes\0" \
- "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
- "bootfile=uImage\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "mtddevname=uboot-env\0" \
- "mtddevnum=0\0" \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "u-boot=/tftpboot/ipam390/u-boot.ais\0" \
- "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
- "nand write c0000000 20000 ${filesize}\0" \
- "setbootparms=nand read c0100000 200000 400000;" \
- "run defbootargs addmtd;" \
- "spl export atags c0100000;" \
- "nand erase.part bootparms;" \
- "nand write c0000100 180000 20000\0" \
- "\0"
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-/* defines for SPL */
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
- CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_STACK 0x8001ff00
-#define CONFIG_SPL_MAX_SIZE 0x20000
-#define CONFIG_SPL_MAX_FOOTPRINT 32768
-
-/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-
-/* add FALCON boot mode */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
-#define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
-
-/* GPIO support */
-#define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
-
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11)
-#define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12)
-
-#include <asm/arch/hardware.h>
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66000000
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define CONFIG_83XX_PCICLK 66000000
+
+/* QE microcode/firmware address */
+/* between the u-boot partition and env */
+#ifndef CONFIG_SYS_QE_FW_ADDR
+#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
+#endif
+
+/*
+ * System IO Config
+ */
+/* 0x14000180 SICR_1 */
+#define CONFIG_SYS_SICRL (0 \
+ | SICR_1_UART1_UART1RTS \
+ | SICR_1_I2C_CKSTOP \
+ | SICR_1_IRQ_A_IRQ \
+ | SICR_1_IRQ_B_IRQ \
+ | SICR_1_GPIO_A_GPIO \
+ | SICR_1_GPIO_B_GPIO \
+ | SICR_1_GPIO_C_GPIO \
+ | SICR_1_GPIO_D_GPIO \
+ | SICR_1_GPIO_E_GPIO \
+ | SICR_1_GPIO_F_GPIO \
+ | SICR_1_USB_A_UART2S \
+ | SICR_1_USB_B_UART2RTS \
+ | SICR_1_FEC1_FEC1 \
+ | SICR_1_FEC2_FEC2 \
+ )
+
+/* 0x00080400 SICR_2 */
+#define CONFIG_SYS_SICRH (0 \
+ | SICR_2_FEC3_FEC3 \
+ | SICR_2_HDLC1_A_HDLC1 \
+ | SICR_2_ELBC_A_LA \
+ | SICR_2_ELBC_B_LCLK \
+ | SICR_2_HDLC2_A_HDLC2 \
+ | SICR_2_USB_D_GPIO \
+ | SICR_2_PCI_PCI \
+ | SICR_2_HDLC1_B_HDLC1 \
+ | SICR_2_HDLC1_C_HDLC1 \
+ | SICR_2_HDLC2_B_GPIO \
+ | SICR_2_HDLC2_C_HDLC2 \
+ | SICR_2_QUIESCE_B \
+ )
+
+/* GPR_1 */
+#define CONFIG_SYS_GPR1 0x50008060
+
+#define CONFIG_SYS_GP1DIR 0x00000000
+#define CONFIG_SYS_GP1ODR 0x00000000
+#define CONFIG_SYS_GP2DIR 0xFF000000
+#define CONFIG_SYS_GP2ODR 0x00000000
+
+#define CONFIG_SYS_DDRCDR (\
+ DDRCDR_EN | \
+ DDRCDR_PZ_MAXZ | \
+ DDRCDR_NZ_MAXZ | \
+ DDRCDR_M_ODR)
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+ SDRAM_CFG_32_BE | \
+ SDRAM_CFG_SREN | \
+ SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ODT_RD_NEVER | \
+ CSCONFIG_ODT_WR_ONLY_CURRENT | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE 0x47860242
+#define CONFIG_SYS_DDR_MODE2 0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
+ (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ (3 << TIMING_CFG1_WRREC_SHIFT) | \
+ (7 << TIMING_CFG1_REFREC_SHIFT) | \
+ (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+ (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/* ethernet port connected to piggy (UEC2) */
+#define CONFIG_HAS_ETH1
+#define CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
+#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
+#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR 0
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
--- /dev/null
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66000000
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define CONFIG_83XX_PCICLK 66000000
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH1 /* GETH1 */
+#define UEC_VERBOSE_DEBUG 1
+
+#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
+
+#define CONFIG_SYS_DDRCDR (\
+ DDRCDR_EN | \
+ DDRCDR_PZ_MAXZ | \
+ DDRCDR_NZ_MAXZ | \
+ DDRCDR_M_ODR)
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+ SDRAM_CFG_32_BE | \
+ SDRAM_CFG_SREN | \
+ SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ODT_WR_CFG | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE 0x47860242
+#define CONFIG_SYS_DDR_MODE2 0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
+ (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ (3 << TIMING_CFG1_WRREC_SHIFT) | \
+ (7 << TIMING_CFG1_REFREC_SHIFT) | \
+ (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+ (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
--- /dev/null
+/* KMBEC FPGA (PRIO) */
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
+
+/*
+ * High Level Configuration Options
+ */
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH1 /* GETH1 */
+#define UEC_VERBOSE_DEBUG 1
+
+#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+
+/*
+ * System IO Setup
+ */
+#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
+
+/**
+ * DDR RAM settings
+ */
+#define CONFIG_SYS_DDR_SDRAM_CFG (\
+ SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+ SDRAM_CFG_SREN | \
+ SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+
+#define CONFIG_SYS_DDR_CLK_CNTL (\
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CONFIG_SYS_DDR_INTERVAL (\
+ (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+
+#define CONFIG_SYS_DDRCDR (\
+ DDRCDR_EN | \
+ DDRCDR_Q_DRN)
+#define CONFIG_SYS_DDR_MODE 0x47860452
+#define CONFIG_SYS_DDR_MODE2 0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 (\
+ (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
+ (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ (3 << TIMING_CFG1_WRREC_SHIFT) | \
+ (7 << TIMING_CFG1_REFREC_SHIFT) | \
+ (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 (\
+ (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (5 << TIMING_CFG2_CPO_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * PAXE on the local bus CS3
+ */
+#define CONFIG_SYS_PAXE_BASE 0xA0000000
+#define CONFIG_SYS_PAXE_SIZE 256
--- /dev/null
+/*
+ * Internal Definitions
+ */
+#define BOOTFLASH_START 0xF0000000
+
+#define CONFIG_KM_CONSOLE_TTY "ttyS0"
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CFG_83XX_DDR_USES_CS0
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_DDR_II
+#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE 0xF0000000
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* Reserve 768 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus Machine PortSz Size Device
+ * ---- --- ------- ------ ----- ------
+ * 0 Local GPCM 16 bit 256MB FLASH
+ * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
+ *
+ */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_NUM_I2C_BUSES 4
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 200000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 200000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+ {1, {I2C_NULL_HOP} } }
+
+#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#ifndef CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#endif
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#ifndef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
+#endif
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else /* CFG_SYS_RAMBOOT */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#endif /* CFG_SYS_RAMBOOT */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ CONFIG_KM_DEF_ARCH \
+ "newenv=" \
+ "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \
+ "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \
+ "unlock=yes\0" \
+ ""
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME "UEC0"
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Keymile AG
- * Gerlando Falauto <gerlando.falauto@keymile.com>
- *
- * Based on km8321-common.h, see respective copyright notice for credits
- */
-
-#ifndef __CONFIG_KM8309_COMMON_H
-#define __CONFIG_KM8309_COMMON_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */
-
-#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
-
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-/* between the u-boot partition and env */
-#ifndef CONFIG_SYS_QE_FW_ADDR
-#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
-#endif
-
-/*
- * System IO Config
- */
-/* 0x14000180 SICR_1 */
-#define CONFIG_SYS_SICRL (0 \
- | SICR_1_UART1_UART1RTS \
- | SICR_1_I2C_CKSTOP \
- | SICR_1_IRQ_A_IRQ \
- | SICR_1_IRQ_B_IRQ \
- | SICR_1_GPIO_A_GPIO \
- | SICR_1_GPIO_B_GPIO \
- | SICR_1_GPIO_C_GPIO \
- | SICR_1_GPIO_D_GPIO \
- | SICR_1_GPIO_E_GPIO \
- | SICR_1_GPIO_F_GPIO \
- | SICR_1_USB_A_UART2S \
- | SICR_1_USB_B_UART2RTS \
- | SICR_1_FEC1_FEC1 \
- | SICR_1_FEC2_FEC2 \
- )
-
-/* 0x00080400 SICR_2 */
-#define CONFIG_SYS_SICRH (0 \
- | SICR_2_FEC3_FEC3 \
- | SICR_2_HDLC1_A_HDLC1 \
- | SICR_2_ELBC_A_LA \
- | SICR_2_ELBC_B_LCLK \
- | SICR_2_HDLC2_A_HDLC2 \
- | SICR_2_USB_D_GPIO \
- | SICR_2_PCI_PCI \
- | SICR_2_HDLC1_B_HDLC1 \
- | SICR_2_HDLC1_C_HDLC1 \
- | SICR_2_HDLC2_B_GPIO \
- | SICR_2_HDLC2_C_HDLC2 \
- | SICR_2_QUIESCE_B \
- )
-
-/* GPR_1 */
-#define CONFIG_SYS_GPR1 0x50008060
-
-#define CONFIG_SYS_GP1DIR 0x00000000
-#define CONFIG_SYS_GP1ODR 0x00000000
-#define CONFIG_SYS_GP2DIR 0xFF000000
-#define CONFIG_SYS_GP2ODR 0x00000000
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
- HRCWL_DDR_TO_SCB_CLK_2X1 | \
- HRCWL_CSB_TO_CLKIN_2X1 | \
- HRCWL_CORE_TO_CSB_2X1 | \
- HRCWL_CE_PLL_VCO_DIV_2 | \
- HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT | \
- HRCWH_PCI_ARBITER_DISABLE | \
- HRCWH_CORE_ENABLE | \
- HRCWH_FROM_0X00000100 | \
- HRCWH_BOOTSEQ_DISABLE | \
- HRCWH_SW_WATCHDOG_DISABLE | \
- HRCWH_ROM_LOC_LOCAL_16BIT | \
- HRCWH_BIG_ENDIAN | \
- HRCWH_LALE_NORMAL)
-
-#define CONFIG_SYS_DDRCDR (\
- DDRCDR_EN | \
- DDRCDR_PZ_MAXZ | \
- DDRCDR_NZ_MAXZ | \
- DDRCDR_M_ODR)
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
- SDRAM_CFG_32_BE | \
- SDRAM_CFG_SREN | \
- SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
- (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
- CSCONFIG_ODT_RD_NEVER | \
- CSCONFIG_ODT_WR_ONLY_CURRENT | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE 0x47860242
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
- (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
- (0 << TIMING_CFG0_WWT_SHIFT) | \
- (0 << TIMING_CFG0_RRT_SHIFT) | \
- (0 << TIMING_CFG0_WRT_SHIFT) | \
- (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
- (2 << TIMING_CFG1_WRTORD_SHIFT) | \
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- (3 << TIMING_CFG1_WRREC_SHIFT) | \
- (7 << TIMING_CFG1_REFREC_SHIFT) | \
- (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
- (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
- (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
- (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP 0x80000000
-#define CONFIG_SYS_LCRR_EADC 0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
-
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * MMU Setup
- */
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#endif /* __CONFIG_KM8309_COMMON_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2010
- * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
- *
- * (C) Copyright 2010-2011
- * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
- */
-
-#ifndef __CONFIG_KM8321_COMMON_H
-#define __CONFIG_KM8321_COMMON_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_QE /* Has QE */
-#define CONFIG_MPC832x /* MPC832x CPU specific */
-#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
-
-#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
-
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
- HRCWL_DDR_TO_SCB_CLK_2X1 | \
- HRCWL_CSB_TO_CLKIN_2X1 | \
- HRCWL_CORE_TO_CSB_2_5X1 | \
- HRCWL_CE_PLL_VCO_DIV_2 | \
- HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT | \
- HRCWH_PCI_ARBITER_DISABLE | \
- HRCWH_CORE_ENABLE | \
- HRCWH_FROM_0X00000100 | \
- HRCWH_BOOTSEQ_DISABLE | \
- HRCWH_SW_WATCHDOG_DISABLE | \
- HRCWH_ROM_LOC_LOCAL_16BIT | \
- HRCWH_BIG_ENDIAN | \
- HRCWH_LALE_NORMAL)
-
-#define CONFIG_SYS_DDRCDR (\
- DDRCDR_EN | \
- DDRCDR_PZ_MAXZ | \
- DDRCDR_NZ_MAXZ | \
- DDRCDR_M_ODR)
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
- SDRAM_CFG_32_BE | \
- SDRAM_CFG_SREN | \
- SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
- (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
- CSCONFIG_ODT_WR_CFG | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE 0x47860242
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
- (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
- (0 << TIMING_CFG0_WWT_SHIFT) | \
- (0 << TIMING_CFG0_RRT_SHIFT) | \
- (0 << TIMING_CFG0_WRT_SHIFT) | \
- (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
- (2 << TIMING_CFG1_WRTORD_SHIFT) | \
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- (3 << TIMING_CFG1_WRREC_SHIFT) | \
- (7 << TIMING_CFG1_REFREC_SHIFT) | \
- (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
- (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
- (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
- (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP 0x80000000
-#define CONFIG_SYS_LCRR_EADC 0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
-
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * MMU Setup
- */
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#endif /* __CONFIG_KM8321_COMMON_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#ifndef __CONFIG_KM83XX_H
-#define __CONFIG_KM83XX_H
-
-/* include common defines/options for all Keymile boards */
-#include "keymile-common.h"
-#include "km-powerpc.h"
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66000000
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_83XX_PCICLK 66000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CFG_83XX_DDR_USES_CS0
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_DDR_II
-#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_FLASH_BASE 0xF0000000
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/* Reserve 768 kB for Mon */
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus Machine PortSz Size Device
- * ---- --- ------- ------ ----- ------
- * 0 Local GPCM 16 bit 256MB FLASH
- * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
- *
- */
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- BR_PS_16 | /* 16 bit port size */ \
- BR_MS_GPCM | /* MSEL = GPCM */ \
- BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_5 | \
- OR_GPCM_TRLX_SET | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-/*
- * PRIO1/PIGGY on the local bus CS1
- */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
- BR_PS_8 | /* 8 bit port size */ \
- BR_MS_GPCM | /* MSEL = GPCM */ \
- BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX_SET | OR_GPCM_EAD)
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#if !defined(CONFIG_MPC8309)
-#define CONFIG_UEC_ETH1 /* GETH1 */
-#define UEC_VERBOSE_DEBUG 1
-#endif
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 0
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif
-
-/*
- * Environment
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
-#ifndef CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#endif
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
-#ifndef CONFIG_ENV_OFFSET
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
-#endif
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#else /* CFG_SYS_RAMBOOT */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#endif /* CFG_SYS_RAMBOOT */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_NUM_I2C_BUSES 4
-#define CONFIG_SYS_I2C_MAX_HOPS 1
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 200000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 200000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
- {1, {I2C_NULL_HOP} } }
-
-#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/*
- * Internal Definitions
- */
-#define BOOTFLASH_START 0xF0000000
-
-#define CONFIG_KM_CONSOLE_TTY "ttyS0"
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-
-#ifndef CONFIG_KM_DEF_ARCH
-#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_KM_DEF_ENV \
- CONFIG_KM_DEF_ARCH \
- "newenv=" \
- "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
- "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
- "unlock=yes\0" \
- ""
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#endif
-
-#endif /* __CONFIG_KM83XX_H */
* env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
* ucode is stored after env, so we got 0x120000.
*/
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PCI_INDIRECT_BRIDGE
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012
- * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
- * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* KMBEC FPGA (PRIO) */
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
-
-#if defined CONFIG_KMETER1
-#define CONFIG_HOSTNAME "kmeter1"
-#define CONFIG_KM_BOARD_NAME "kmeter1"
-#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
-#elif defined CONFIG_KMCOGE5NE
-#define CONFIG_HOSTNAME "kmcoge5ne"
-#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
-#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
-#define CONFIG_NAND_ECC_BCH
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
-
-#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
-#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
-#else
-#error ("Board not supported")
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_QE /* Has QE */
-#define CONFIG_MPC8360 /* MPC8360 CPU specific */
-
-/* include common defines/options for all 83xx Keymile boards */
-#include "km/km83xx-common.h"
-
-/*
- * System IO Setup
- */
-#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_CSB_TO_CLKIN_4X1 | \
- HRCWL_CORE_TO_CSB_2X1 | \
- HRCWL_CE_PLL_VCO_DIV_2 | \
- HRCWL_CE_TO_PLL_1X6)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_CORE_ENABLE | \
- HRCWH_FROM_0X00000100 | \
- HRCWH_BOOTSEQ_DISABLE | \
- HRCWH_SW_WATCHDOG_DISABLE | \
- HRCWH_ROM_LOC_LOCAL_16BIT | \
- HRCWH_BIG_ENDIAN | \
- HRCWH_LALE_EARLY | \
- HRCWH_LDP_CLEAR)
-
-/**
- * DDR RAM settings
- */
-#define CONFIG_SYS_DDR_SDRAM_CFG (\
- SDRAM_CFG_SDRAM_TYPE_DDR2 | \
- SDRAM_CFG_SREN | \
- SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-
-#ifdef CONFIG_KMCOGE5NE
-/**
- * KMCOGE5NE has 512 MB RAM
- */
-#define CONFIG_SYS_DDR_CS0_CONFIG (\
- CSCONFIG_EN | \
- CSCONFIG_AP | \
- CSCONFIG_ODT_WR_ONLY_CURRENT | \
- CSCONFIG_BANK_BIT_3 | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10)
-#else
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10 | \
- CSCONFIG_ODT_WR_ONLY_CURRENT)
-#endif
-
-#define CONFIG_SYS_DDR_CLK_CNTL (\
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CONFIG_SYS_DDR_INTERVAL (\
- (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
- (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-
-#define CONFIG_SYS_DDRCDR (\
- DDRCDR_EN | \
- DDRCDR_Q_DRN)
-#define CONFIG_SYS_DDR_MODE 0x47860452
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0 (\
- (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
- (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
- (0 << TIMING_CFG0_WWT_SHIFT) | \
- (0 << TIMING_CFG0_RRT_SHIFT) | \
- (0 << TIMING_CFG0_WRT_SHIFT) | \
- (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
- (2 << TIMING_CFG1_WRTORD_SHIFT) | \
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- (3 << TIMING_CFG1_WRREC_SHIFT) | \
- (7 << TIMING_CFG1_REFREC_SHIFT) | \
- (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 (\
- (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
- (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
- (5 << TIMING_CFG2_CPO_SHIFT) | \
- (0 << TIMING_CFG2_ADD_LAT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-
-/*
- * PAXE on the local bus CS3
- */
-#define CONFIG_SYS_PAXE_BASE 0xA0000000
-#define CONFIG_SYS_PAXE_SIZE 256
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
-
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
-
-#define CONFIG_SYS_BR3_PRELIM (\
- CONFIG_SYS_PAXE_BASE | \
- (1 << BR_PS_SHIFT) | \
- BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (\
- MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX | \
- OR_GPCM_EAD)
-
-#ifdef CONFIG_KMCOGE5NE
-/*
- * BFTIC3 on the local bus CS4
- */
-#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
-#define CONFIG_SYS_BFTIC3_SIZE 256
-
-#define CONFIG_SYS_BR4_PRELIM (\
- CONFIG_SYS_BFTIC3_BASE |\
- (1 << BR_PS_SHIFT) | \
- BR_V)
-
-#define CONFIG_SYS_OR4_PRELIM (\
- MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV2 |\
- OR_GPCM_SCY_2 |\
- OR_GPCM_TRLX |\
- OR_GPCM_EAD)
-#endif
-
-/*
- * MMU Setup
- */
-
-/* PAXE: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (\
- CONFIG_SYS_PAXE_BASE | \
- BATL_PP_10 | \
- BATL_MEMCOHERENCE)
-
-#define CONFIG_SYS_IBAT5U (\
- CONFIG_SYS_PAXE_BASE | \
- BATU_BL_256M | \
- BATU_VS | \
- BATU_VP)
-
-#define CONFIG_SYS_DBAT5L (\
- CONFIG_SYS_PAXE_BASE | \
- BATL_PP_10 | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_KMCOGE5NE
-/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L (\
- CONFIG_SYS_BFTIC3_BASE | \
- BATL_PP_10 | \
- BATL_MEMCOHERENCE)
-
-#define CONFIG_SYS_IBAT6U (\
- CONFIG_SYS_BFTIC3_BASE | \
- BATU_BL_256M | \
- BATU_VS | \
- BATU_VP)
-
-#define CONFIG_SYS_DBAT6L (\
- CONFIG_SYS_BFTIC3_BASE | \
- BATL_PP_10 | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/* DDR/LBC SDRAM next 256M: cacheable */
-#define CONFIG_SYS_IBAT7L (\
- CONFIG_SYS_SDRAM_BASE2 |\
- BATL_PP_10 |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-
-#define CONFIG_SYS_IBAT7U (\
- CONFIG_SYS_SDRAM_BASE2 |\
- BATU_BL_256M |\
- BATU_VS |\
- BATU_VP)
-/* enable POST tests */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
-#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
-#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
-#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
-#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
-
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#endif
-
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#endif /* CONFIG */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
+ * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_HOSTNAME "kmcoge5ne"
+#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
+#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8360.h"
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66000000
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define CONFIG_83XX_PCICLK 66000000
+
+/**
+ * KMCOGE5NE has 512 MB RAM
+ */
+#define CONFIG_SYS_DDR_CS0_CONFIG (\
+ CSCONFIG_EN | \
+ CSCONFIG_AP | \
+ CSCONFIG_ODT_WR_ONLY_CURRENT | \
+ CSCONFIG_BANK_BIT_3 | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10)
+
+/*
+ * BFTIC3 on the local bus CS4
+ */
+#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
+#define CONFIG_SYS_BFTIC3_SIZE 256
+
+/* enable POST tests */
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
+#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
+#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
+#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
+
+#endif /* CONFIG */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
+ * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_HOSTNAME "kmeter1"
+#define CONFIG_KM_BOARD_NAME "kmeter1"
+#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8360.h"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10 | \
+ CSCONFIG_ODT_WR_ONLY_CURRENT)
+#endif /* CONFIG */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME "kmopti2"
+#define CONFIG_HOSTNAME "kmopti2"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME "kmsupx5"
+#define CONFIG_HOSTNAME "kmsupx5"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_HOSTNAME "kmtegr1"
+#define CONFIG_KM_BOARD_NAME "kmtegr1"
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
+
+#define CONFIG_ENV_ADDR 0xF0100000
+#define CONFIG_ENV_OFFSET 0x100000
+
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8309.h"
+
+/* must be after the include because KMBEC_FPGA is otherwise undefined */
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+
+#endif /* __CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME "kmtepr2"
+#define CONFIG_HOSTNAME "kmtepr2"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_HOSTNAME "kmvect1"
+#define CONFIG_KM_BOARD_NAME "kmvect1"
+/* at end of uboot partition, before env */
+#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8309.h"
+
+#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
+ 0x0000c000 | \
+ MxMR_WLFx_2X)
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MV88E6352_SWITCH
+#define CONFIG_KM_MVEXTSW_ADDR 0x10
+
+/* ethernet port connected to simple switch 88e6122 (UEC0) */
+#define CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
+
+#define CONFIG_FIXED_PHY 0xFFFFFFFF
+#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
+#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
+ {devnum, speed, duplex}
+#define CONFIG_SYS_FIXED_PHY_PORTS \
+ CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
+
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+
+#endif /* __CONFIG_H */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
/* USB Configs */
-#define CONFIG_USB_EHCI_MX5
-#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
"setexpr blkc ${blkc} + 1; " \
"mmc write ${loadaddr} 0x2 ${blkc}" \
"; fi\0" \
- "upwic=setenv wic_file kp-image-kp${boardsoc}${boardtype}.wic; "\
+ "upwic=setenv wic_file kp-image-kp${boardsoc}.wic; "\
"if tftp ${loadaddr} ${wic_file}; then " \
"setexpr blkc ${filesize} / 0x200; " \
"setexpr blkc ${blkc} + 1; " \
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SKIP_LOWLEVEL_INIT
/*
* Memory Info
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
#endif
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/*SPI device */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT)
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_FSL_SPI_INTERFACE
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+ "env exists secureboot " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"installer=load mmc 0:2 $load_addr " \
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+ "env exists secureboot " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"installer=load mmc 0:2 $load_addr " \
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
- !defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#endif
-
/*
* IFC Definitions
*/
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
- !defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#endif
-
/*
* IFC Definitions
*/
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+ "env exists secureboot " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"installer=load mmc 0:2 $load_addr " \
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __L1028A_COMMON_H
+#define __L1028A_COMMON_H
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_MP
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0)
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "board=ls1028ardb\0" \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x00f00000\0" \
+ "kernel_addr=0x01000000\0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "ramdisk_addr_r=0xa0000000\0" \
+ "kernel_start=0x1000000\0" \
+ "kernelheader_start=0x800000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernelheader_size=0x40000\0" \
+ "kernel_addr_sd=0x8000\0" \
+ "kernel_size_sd=0x14000\0" \
+ "kernelhdr_addr_sd=0x4000\0" \
+ "kernelhdr_size_sd=0x10\0" \
+ "console=ttyS0,115200\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ BOOTENV \
+ "boot_scripts=ls1028ardb_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;" \
+ "\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0" \
+ "sd_bootcmd=echo Trying load from SD ..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
+ "env exists secureboot && mmc read $kernelheader_addr_r " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$board\0" \
+ "emmc_bootcmd=echo Trying load from EMMC ..;" \
+ "mmcinfo; mmc dev 1; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
+ "env exists secureboot && mmc read $kernelheader_addr_r " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+
+#define SD_BOOTCOMMAND \
+ "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+
+#ifndef CONFIG_CMDLINE_EDITING
+#define CONFIG_CMDLINE_EDITING 1
+#endif
+
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define OCRAM_NONSECURE_SIZE 0x00010000
+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
+#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
+#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_SECT_SIZE 0x40000
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT 0x8
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#endif /* __L1028A_COMMON_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1028A_QDS_H
+#define __LS1028A_QDS_H
+
+#include "ls1028a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE 0x7fb00000
+#define QIXIS_BASE_PHYS QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_SWITCH 1
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 5
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x00
+#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_EMMC 0x00
+#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_RCW_SRC_SD 0x8
+#define QIXIS_RCW_SRC_EMMC 0x9
+#define QIXIS_RCW_SRC_QSPI 0xf
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RST_FORCE_MEM 0x01
+
+#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
+#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_MSEL_GPCM | \
+ CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_NOR_MODE_AVD_NOR | \
+ CSOR_NOR_TRHZ_80)
+#endif
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM 1
+#define I2C_MUX_CH_RTC 0xB
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_SIZE 0x2000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+/* DSPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifndef SPL_NO_ENV
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "board=ls1028aqds\0" \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x00f00000\0" \
+ "kernel_addr=0x01000000\0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "ramdisk_addr_r=0xa0000000\0" \
+ "kernel_start=0x1000000\0" \
+ "kernelheader_start=0x800000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernelheader_size=0x40000\0" \
+ "kernel_addr_sd=0x8000\0" \
+ "kernel_size_sd=0x14000\0" \
+ "kernelhdr_addr_sd=0x4000\0" \
+ "kernelhdr_size_sd=0x10\0" \
+ "console=ttyS0,115200\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ BOOTENV \
+ "boot_scripts=ls1028aqds_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1028aqds_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;" \
+ "\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0" \
+ "sd_bootcmd=echo Trying load from SD ..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
+ "env exists secureboot && mmc read $kernelheader_addr_r " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$board\0" \
+ "emmc_bootcmd=echo Trying load from EMMC ..;" \
+ "mmcinfo; mmc dev 1; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
+ "env exists secureboot && mmc read $kernelheader_addr_r " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$board\0"
+#endif
+#endif /* __LS1028A_QDS_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1028A_RDB_H
+#define __LS1028A_RDB_H
+
+#include "ls1028a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+
+#define CONFIG_SYS_RTC_BUS_NUM 0
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_SIZE 0x2000
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE 0x7fb00000
+#define QIXIS_BASE_PHYS QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_SWITCH 2
+#define QIXIS_LBMAP_MASK 0xe0
+#define QIXIS_LBMAP_SHIFT 0x5
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x00
+#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_EMMC 0x00
+#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_RCW_SRC_SD 0xf8
+#define QIXIS_RCW_SRC_EMMC 0xf9
+#define QIXIS_RCW_SRC_QSPI 0xff
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x11
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RST_FORCE_MEM 0x01
+
+#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
+#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_MSEL_GPCM | \
+ CSPR_V)
+#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_NOR_MODE_AVD_NOR | \
+ CSOR_NOR_TRHZ_80)
+#endif
+
+/* SATA */
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define SCSI_VEND_ID 0x1b4b
+#define SCSI_DEV_ID 0x9170
+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
+
+#endif /* __LS1028A_RDB_H */
#else
#ifdef CONFIG_NAND_BOOT
/* Store Fman ucode at offeset 0x900000(72 blocks). */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
/*
* about 1MB (2040 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
#define CONFIG_SYS_QE_FW_ADDR 0x60940000
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+ "env exists secureboot " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHYLIB_10G
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
*/
-#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
#endif
#endif
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
- "&& esbc_validate ${scripthdraddr};" \
+ "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+ "env exists secureboot " \
+ "&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHYLIB_10G
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
+ "env exists secureboot " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"installer=load mmc 0:2 $load_addr " \
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+ "env exists secureboot " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
-#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_SYS_MAXARGS 64 /* max command args */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define AQR107_PHY_ADDR1 0x04
#define AQR107_PHY_ADDR2 0x05
+#define AQR107_IRQ_MASK 0x0C
#define CORTINA_NO_FW_UPLOAD
#define CORTINA_PHY_ADDR1 0x0
* USB
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_MX5
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- *
- * Based on omap3_evm_config.h
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MCX
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
- * and older u-boot.bin with the new U-Boot SPL.
- */
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
-/*
- * DDR related
- */
-#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/* EHCI */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
-
-/* commands to include */
-
-#define CONFIG_SYS_I2C
-
-/* RTC */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access */
- /* nand at CS0 */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
- /* NAND devices */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
-
-/* Environment information */
-
-#define CONFIG_BOOTFILE "uImage"
-
-/* Setup MTD for NAND on the SOM */
-
-#define CONFIG_HOSTNAME "mcx"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
- "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
- "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
- "addfb=setenv bootargs ${bootargs} vram=6M " \
- "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:eth0:off\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "addtty=setenv bootargs ${bootargs} " \
- "console=${consoledev},${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "baudrate=115200\0" \
- "consoledev=ttyO2\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "loadaddr=0x82000000\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "load_k=tftp ${loadaddr} ${bootfile}\0" \
- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
- "loadmlo=tftp ${loadaddr} ${mlo}\0" \
- "mlo=" CONFIG_HOSTNAME "/MLO\0" \
- "mmcargs=root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext3 rootwait\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "run addip addtty addmtd addfb addeth addmisc;" \
- "run loaduimage; " \
- "bootm ${loadaddr}\0" \
- "net_nfs=run load_k; " \
- "run nfsargs; " \
- "run addip addtty addmtd addfb addeth addmisc;" \
- "bootm ${loadaddr}\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
- "uboot_addr=0x80000\0" \
- "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
- "nand write ${loadaddr} ${uboot_addr} 80000\0" \
- "updatemlo=nandecc hw;nand erase 0 20000;" \
- "nand write ${loadaddr} 0 20000\0" \
- "upd=if run load;then echo Updating u-boot;if run update;" \
- "then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "nandargs=setenv bootargs ubi.mtd=7 " \
- "root=ubi0:rootfs rootfstype=ubifs\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "ubi part nand0,4;" \
- "ubi readvol ${loadaddr} kernel;" \
- "run addtty addmtd addfb addeth addmisc;" \
- "bootm ${loadaddr}\0" \
- "preboot=ubi part nand0,7;" \
- "ubi readvol ${loadaddr} splash;" \
- "bmp display ${loadaddr};" \
- "gpio set 55\0" \
- "swupdate_args=setenv bootargs root=/dev/ram " \
- "quiet loglevel=1 " \
- "consoleblank=0 ${swupdate_misc}\0" \
- "swupdate=echo Running Sw-Update...;" \
- "if printenv mtdparts;then echo Starting SwUpdate...; " \
- "else mtdparts default;fi; " \
- "ubi part nand0,5;" \
- "ubi readvol 0x82000000 kernel_recovery;" \
- "ubi part nand0,6;" \
- "ubi readvol 0x84000000 fs_recovery;" \
- "run swupdate_args; " \
- "setenv bootargs ${bootargs} " \
- "${mtdparts} " \
- "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
- "omapdss.def_disp=lcd;" \
- "bootm 0x82000000 0x84000000\0" \
- "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
- "then source 82000000;else run nandboot;fi\0"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
- /* address */
-#define CONFIG_PREBOOT
-
-/*
- * AM3517 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/*
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-
-/* Redundant Environment */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x180000
-#define CONFIG_ENV_ADDR 0x180000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- 2 * CONFIG_SYS_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/* Defines for SPL */
-
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-
-#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-/* move malloc and bss high to prevent clashing with the main image */
-#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
- 48, 49, 50, 51, 52, 53, 54, 55,\
- 56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
-#define CONFIG_SPL_NAND_SOFTECC
-
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-
-/*
- * ethernet support
- *
- */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_RLE8
-
-#endif /* __CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+/*
+ * Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * max number of command args
+ */
+#define CONFIG_SYS_MAXARGS 16
+
+/*
+ * Boot Argument Buffer Size
+ */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
+ */
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+
+/* Init Stack Pointer */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000)
+
+#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* SDRAM */
+
+/*
+ * memtest works on DRAM
+ */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
+
+/* When we use RAM as ENV */
+#define CONFIG_ENV_SIZE 0x2000
+
+#endif /* __CONFIG_H */
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
/*
* On-board devices
#define CONFIG_TSEC1
#define CONFIG_TSEC2
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_MII |\
- HRCWH_TSEC2M_IN_MII |\
- HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
- SICRH_ESDHC_A_GPIO |\
- SICRH_ESDHC_B_GPIO |\
- SICRH_ESDHC_C_GTM |\
- SICRH_GPIO_A_TSEC2 |\
- SICRH_GPIO_B_TSEC2_TX_CLK |\
- SICRH_IEEE1588_A_GPIO |\
- SICRH_USB |\
- SICRH_GTM_GPIO |\
- SICRH_IEEE1588_B_GPIO |\
- SICRH_ETSEC2_CRS |\
- SICRH_GPIOSEL_1 |\
- SICRH_TMROBI_V3P3 |\
- SICRH_TSOBI1_V3P3 |\
- SICRH_TSOBI2_V3P3) /* 0xf577d100 */
-#define CONFIG_SYS_SICRL (\
- SICRL_SPI_PF0 |\
- SICRL_UART_PF0 |\
- SICRL_IRQ_PF0 |\
- SICRL_I2C2_PF0 |\
- SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
-
#define CONFIG_SYS_GPIO1_PRELIM
/* GPIO Default input/output settings */
#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
*/
#define CONFIG_SYS_GPIO1_DAT 0x08008C00
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
/*
* SERDES
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_4 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512
* SJA1000 CAN controller on Local Bus
*/
#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \
- | BR_PS_8 /* 8 bit port size */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_EHTR_SET)
- /* 0xFFFF8052 */
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+
/*
* CPLD on Local Bus
*/
#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \
- | OR_GPCM_SCY_4 \
- | OR_GPCM_EHTR_SET)
- /* 0xFFFF8042 */
-
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+
/*
* Serial Port
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
/*
* Environment Configuration
*/
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for MPR2
- *
- * Copyright (C) 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- */
-
-#ifndef __MPR2_H
-#define __MPR2_H
-
-/* Supported commands */
-
-/* Default environment variables */
-#define CONFIG_BOOTFILE "/boot/zImage"
-#define CONFIG_LOADADDR 0x8E000000
-
-/* CPU and platform */
-#define CONFIG_CPU_SH7720 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* U-Boot internals */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-
-/* Memory */
-#define CONFIG_SYS_SDRAM_BASE 0x8C000000
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
-
-/* Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BASE 0xA0000000
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Clocks */
-#define CONFIG_SYS_CLK_FREQ 24000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* UART */
-#define CONFIG_CONS_SCIF0 1
-
-#endif /* __MPR2_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Hitachi Solution Engine 7720
- *
- * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#ifndef __MS7720SE_H
-#define __MS7720SE_H
-
-#define CONFIG_CPU_SH7720 1
-
-#define CONFIG_BOOTFILE "/boot/zImage"
-#define CONFIG_LOADADDR 0x8E000000
-
-#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* MEMORY */
-#define MS7720SE_SDRAM_BASE 0x8C000000
-#define MS7720SE_FLASH_BASE_1 0xA0000000
-#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
-
-#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
-
-#define CONFIG_SYS_MAX_FLASH_SECT 150
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* PCMCIA */
-#define CONFIG_IDE_PCMCIA 1
-#define CONFIG_MARUBUN_PCCARD 1
-#define CONFIG_PCMCIA_SLOT_A 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
-#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
-#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
-#define CONFIG_SYS_MARUBUN_IO 0xb8600000
-
-#define CONFIG_SYS_PIO_MODE 1
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#define CONFIG_IDE_SWAP_IO
-
-#endif /* __MS7720SE_H */
/* MMC */
#define MMC_SUPPORTS_TUNING
-#define CONFIG_SUPPORT_EMMC_BOOT
/* DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- *
- * Configuration settings for the Teejet mt_ventoux board.
- *
- * Copyright (C) 2009 TechNexion Ltd.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tam3517-common.h"
-
-#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
- 6 * 1024 * 1024)
-
-#define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX
-
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_HOSTNAME "mt_ventoux"
-
-/*
- * Set its own mtdparts, different from common
- */
-
-/*
- * FPGA
- */
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_WAIT 10000
-#define CONFIG_MAX_FPGA_DEVICES 1
-#define CONFIG_FPGA_DELAY() udelay(1)
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_RLE8
-
-#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
- "bootcmd=run net_nfs\0"
-
-#endif /* __CONFIG_H */
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
-#define CONFIG_USB_EHCI_MX5
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
-#define CONFIG_USB_EHCI_MX5
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_SYS_MMC_ENV_DEV 0
/* Framebuffer and LCD */
+#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_PREBOOT
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
#endif /* __CONFIG_H */
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
-#define CONFIG_USB_EHCI_MX5
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
-#define CONFIG_USB_EHCI_MX5
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONSOLE_DEV "ttymxc0"
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
#include "mx6sabre_common.h"
/* Falcon Mode */
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#ifdef CONFIG_IMX_BOOTAUX
#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
#define CONFIG_FSL_USDHC
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define CONFIG_CMD_CACHE
#endif
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"mmcrootfstype=ext4 rootwait\0" \
"nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \
"nandrootfstype=ubifs rootwait\0" \
"ramargs=setenv bootargs "\
"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
"mmcargs=setenv bootargs "\
- "root=${mmcroot} rootfstype=${mmcrootfstype}\0" \
+ "root=PARTUUID=${uuid} " \
+ "rootfstype=${mmcrootfstype} rw\0" \
"nandargs=setenv bootargs "\
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"loadfdt=mmc rescan; " \
"load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
"mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \
+ "run finduuid; "\
"run mmcargs; " \
"run common_bootargs; " \
"run dump_bootargs; " \
/* Enhance our eMMC support / experience. */
#define CONFIG_HSMMC2_8BIT
-#define CONFIG_SUPPORT_EMMC_BOOT
/* Required support for the TCA642X GPIO we have on the uEVM */
#define CONFIG_TCA642X
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* MMC */
-#define CONFIG_SUPPORT_EMMC_BOOT
-
/* USB */
#ifdef CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
-#define CONFIG_SYS_DCACHE_OFF 1
-
/* ORIGEN has 4 bank of DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#if defined(CONFIG_TARGET_P1021RDB)
#define CONFIG_BOARDNAME "P1021RDB-PC"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_QE
#define CONFIG_VSC7385_ENET
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
addresses in the LBC */
#if defined(CONFIG_TARGET_P1025RDB)
#define CONFIG_BOARDNAME "P1025RDB"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_QE
#define CONFIG_SLIC
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
#ifdef CONFIG_QE
/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_QE */
#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_PHY_ATHEROS
-#define CONFIG_QE
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
#endif
#ifdef CONFIG_QE
/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_QE */
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=" \
"spl raw 0x2 0x400;" \
- "u-boot raw 0x8a 0x400;" \
+ "u-boot raw 0x8a 0x1000;" \
"/boot/zImage ext4 0 1;" \
"/boot/imx7d-pico-hobbit.dtb ext4 0 1;" \
"/boot/imx7d-pico-pi.dtb ext4 0 1;" \
"bootmenu_1=Boot using PICO-Pi baseboard=" \
"setenv fdtfile imx7d-pico-pi.dtb\0" \
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_SYS_MALLOC_LEN SZ_8M
-#define CONFIG_SYS_BOOTM_LEN SZ_16M
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
/* Environment options */
-#define CONFIG_ENV_SIZE SZ_4K
+#define CONFIG_ENV_SIZE SZ_128K
#define BOOT_TARGET_DEVICES(func) \
func(QEMU, qemu, na) \
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
- "kernel_addr_r=0x81000000\0" \
- "fdt_addr_r=0x82000000\0" \
- "scriptaddr=0x82100000\0" \
- "pxefile_addr_r=0x82200000\0" \
- "ramdisk_addr_r=0x82300000\0" \
+ "kernel_addr_r=0x84000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "scriptaddr=0x88100000\0" \
+ "pxefile_addr_r=0x88200000\0" \
+ "ramdisk_addr_r=0x88300000\0" \
BOOTENV
+#define CONFIG_PREBOOT \
+ "setenv fdt_addr ${fdtcontroladdr};" \
+ "fdt addr ${fdtcontroladdr};"
+
#endif /* __CONFIG_H */
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
#define CONFIG_ATAPI
-/* SPI is not supported */
-
-#define BOOT_DEVICE_SPI 10
-
#define CONFIG_SPL_BOARD_LOAD_IMAGE
-#define BOOT_DEVICE_BOARD 11
#endif /* __CONFIG_H */
#define CONFIG_REMAKE_ELF
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_TARGET "spl/u-boot-spl.scif"
+#endif
+
/* boot option */
#define CONFIG_CMDLINE_TAG
"tftp 0x48000000 Image-"CONFIG_DEFAULT_FDT_FILE"; " \
"booti 0x48080000 - 0x48000000"
+/* SPL support */
+#if defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965)
+#define CONFIG_SPL_BSS_START_ADDR 0xe633f000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x1000
+#else
+#define CONFIG_SPL_BSS_START_ADDR 0xe631f000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x1000
+#endif
+#define CONFIG_SPL_STACK 0xe6304000
+#define CONFIG_SPL_MAX_SIZE 0x7000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF2
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
+
#endif /* __RCAR_GEN3_COMMON_H */
#ifndef __CONFIG_RK3036_COMMON_H
#define __CONFIG_RK3036_COMMON_H
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CACHELINE_SIZE 64
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#ifndef __CONFIG_RK322X_COMMON_H
#define __CONFIG_RK322X_COMMON_H
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
-#define CONFIG_SYS_LOAD_ADDR 0x60800800
-#define CONFIG_SPL_STACK 0x10088000
+#define CONFIG_SYS_INIT_SP_ADDR 0x61100000
+#define CONFIG_SYS_LOAD_ADDR 0x61800800
+#define CONFIG_SPL_MAX_SIZE 0x100000
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
#ifndef __CONFIG_RK3288_COMMON_H
#define __CONFIG_RK3288_COMMON_H
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_SYS_CACHELINE_SIZE 64
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
#include <linux/sizes.h>
#define CONFIG_SYS_SDRAM_BASE 0
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00280000
-#define CONFIG_SPL_MAX_SIZE 0x40000
+#define CONFIG_SPL_MAX_SIZE 0x60000
#define CONFIG_SPL_BSS_START_ADDR 0x400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
+#define CONFIG_SPL_STACK 0x00188000
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00800800
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT)
+#define CONFIG_SPL_STACK 0x00400000
+#define CONFIG_SPL_MAX_SIZE 0x100000
+#define CONFIG_SPL_BSS_START_ADDR 0x00400000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
+#else
#define CONFIG_SPL_STACK 0xff8effff
#define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000
/* BSS setup */
#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000
#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
+#endif
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas Technology RSK 7203
- *
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#ifndef __RSK7203_H
-#define __RSK7203_H
-
-#define CONFIG_CPU_SH7203 1
-
-#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
-
-#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* MEMORY */
-#define RSK7203_SDRAM_BASE 0x0C000000
-#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
-#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
-
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-#define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
-
-#define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT 64
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
-#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
-
-#endif /* __RSK7203_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas RSK2+SH7264 board
- *
- * Copyright (C) 2011 Renesas Electronics Europe Ltd.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#ifndef __RSK7264_H
-#define __RSK7264_H
-
-#define CONFIG_CPU_SH7264 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-
-/* Serial */
-#define CONFIG_CONS_SCIF3 1
-
-/* Memory */
-/* u-boot relocated to top 256KB of ram */
-#define CONFIG_SYS_SDRAM_BASE 0x0C000000
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
-
-/* Flash */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_ENV_OFFSET (128 * 1024)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 36000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
-#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
-
-#endif /* __RSK7264_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas RSK2+SH7269 board
- *
- * Copyright (C) 2012 Renesas Electronics Europe Ltd.
- * Copyright (C) 2012 Phil Edworthy
- */
-
-#ifndef __RSK7269_H
-#define __RSK7269_H
-
-#define CONFIG_CPU_SH7269 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
-
-#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
-
-/* Serial */
-#define CONFIG_CONS_SCIF7
-
-/* Memory */
-/* u-boot relocated to top 256KB of ram */
-#define CONFIG_SYS_SDRAM_BASE 0x0C000000
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
-
-/* NOR Flash */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_ENV_OFFSET (128 * 1024)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 66125000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
-#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
-
-#endif /* __RSK7269_H */
#ifndef __CONFIG_RV1108_COMMON_H
#define __CONFIG_RV1108_COMMON_H
-#include <asm/arch/hardware.h>
+#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x family */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-/*
- * The default if PCI isn't enabled, or if no PCI clk setting is given
- * is 66MHz; this is what the board defaults to when the PCI slot is
- * physically empty. The board will automatically (i.e w/o jumpers)
- * clock down to 33MHz if you insert a 33MHz PCI card.
- */
-#ifdef CONFIG_PCI_33M
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#else /* 66M */
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_33M
-#define CONFIG_SYS_CLK_FREQ 33000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
-#else /* 66M */
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#endif
-#endif
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
*/
#undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFF806FF7 */
-
- /* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
-#ifdef CONFIG_SYS_LB_SDRAM
-/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
- | BR_PS_32 \
- | BR_MS_SDRAM \
- | BR_V)
- /* 0xF0001861 */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
- | OR_SDRAM_XAM \
- | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
- | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
- | OR_SDRAM_EAD)
- /* 0xFC006901 */
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
- | LSDMR_BSMA1516 \
- | LSDMR_RFCR8 \
- | LSDMR_PRETOACT6 \
- | LSDMR_ACTTORW3 \
- | LSDMR_BL8 \
- | LSDMR_WRC3 \
- | LSDMR_CL3)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-#endif
-
/*
* Serial Port
*/
#if defined(CONFIG_PCI)
-#define PCI_64BIT
-#define PCI_ONE_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_INSTRUCTION_CACHE)
-
-/* #define CONFIG_SYS_HID0_FINAL (\
- HID0_ENABLE_INSTRUCTION_CACHE |\
- HID0_ENABLE_M_BIT |\
- HID0_ENABLE_ADDRESS_BROADCAST) */
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
#endif
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas Technology R0P7785LC0011RL board
- *
- * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#ifndef __SH7785LCR_H
-#define __SH7785LCR_H
-
-#define CONFIG_CPU_SH7785 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootdevice=0:1\0" \
- "usbload=usb reset;usbboot;usb stop;bootm\0"
-
-#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* MEMORY */
-#if defined(CONFIG_SH_32BIT)
-/* 0x40000000 - 0x47FFFFFF does not use */
-#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
-#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
-#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
-#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
-#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
-#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
-#define SH7785LCR_USB_BASE (0xa6000000)
-#else
-#define SH7785LCR_SDRAM_BASE (0x08000000)
-#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
-#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
-#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
-#define SH7785LCR_USB_BASE (0xb4000000)
-#endif
-
-#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF1 1
-#define CONFIG_SCIF_EXT_CLOCK 1
-
-#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- (SH7785LCR_SDRAM_SIZE) - \
- 4 * 1024 * 1024)
-#undef CONFIG_SYS_MEMTEST_SCRATCH
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
- (0 * SH7785LCR_FLASH_BANK_SIZE) }
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
-#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
-
-#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/* R8A66597 */
-#define CONFIG_USB_R8A66597_HCD
-#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
-#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
-#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
-#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
-
-/* PCI Controller */
-#define CONFIG_SH4_PCI
-#define CONFIG_SH7780_PCI
-#if defined(CONFIG_SH_32BIT)
-#define CONFIG_SH7780_PCI_LSR 0x1ff00001
-#define CONFIG_SH7780_PCI_LAR 0x5f000000
-#define CONFIG_SH7780_PCI_BAR 0x5f000000
-#else
-#define CONFIG_SH7780_PCI_LSR 0x07f00001
-#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
-#endif
-#define CONFIG_PCI_SCAN_SHOW 1
-
-#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
-
-#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
-
-#if defined(CONFIG_SH_32BIT)
-#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
-#else
-#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
-#endif
-#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
-
-/* ENV setting */
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_ENV_SECT_SIZE (256 * 1024)
-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
-
-/* Board Clock */
-/* The SCIF used external clock. system clock only used timer. */
-#define CONFIG_SYS_CLK_FREQ 50000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-#endif /* __SH7785LCR_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for shmin (T-SH7706LAN, T-SH7706LSR)
- *
- * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#ifndef __SHMIN_H
-#define __SHMIN_H
-
-#define CONFIG_CPU_SH7706 1
-/* T-SH7706LAN */
-#define CONFIG_SHMIN 1
-/* T-SH7706LSR*/
-/* #define CONFIG_T_SH7706LSR 1 */
-
-/*
- * This board has original boot loader. If you write u-boot to 0x0,
- * you should set undef.
- */
-#undef CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* system */
-#define SHMIN_SDRAM_BASE (0x8C000000)
-#define SHMIN_FLASH_BASE_1 (0xA0000000)
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600,14400,19200,38400,57600,115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-/* memory */
-#define CONFIG_SYS_SDRAM_BASE SHMIN_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START SHMIN_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - (256 * 1024))
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_BASE SHMIN_FLASH_BASE_1
-#define CONFIG_SYS_MAX_FLASH_SECT 11
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ATMEL_TOTALSECT CONFIG_SYS_MAX_FLASH_SECT
-#define CONFIG_SYS_ATMEL_REGION 4
-#define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
-#define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
-
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-
-#ifdef CONFIG_T_SH7706LSR
-#define CONFIG_ENV_ADDR (SHMIN_FLASH_BASE_1 + 70000)
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#endif
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#ifdef CONFIG_T_SH7706LSR
-#define CONFIG_SYS_CLK_FREQ 40000000
-#else
-#define CONFIG_SYS_CLK_FREQ 33333333
-#endif /* CONFIG_T_SH7706LSR */
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* Network device */
-#define CONFIG_DRIVER_NE2000
-#define CONFIG_DRIVER_NE2000_BASE (0xb0000300)
-
-#endif /* __SHMIN_H */
#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
#define CONFIG_SYS_AT91_PLLB 0x10483f0e
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
+ * Copyright (C) 2015-2019 Altera Corporation <www.altera.com>
*/
#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* SPL memory allocation configuration, this is for FAT implementation */
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
+
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_ARIES_MCVEVK_H__
+#define __CONFIG_ARIES_MCVEVK_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE "fitImage"
+#define CONFIG_PREBOOT "run try_bootscript"
+#define CONFIG_BOOTCOMMAND "run mmc_mmc"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Environment is in MMC */
+#define CONFIG_ENV_OVERWRITE
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "consdev=ttyS0\0" \
+ "baudrate=115200\0" \
+ "bootscript=boot.scr\0" \
+ "setuuid=part uuid mmc 0:3 uuid\0" \
+ "netdev=eth0\0" \
+ "hostname=mcvevk\0" \
+ "kernel_addr_r=0x10000000\0" \
+ "socfpga_legacy_reset_compat=1\0" \
+ "bootm_size=0xa000000\0" \
+ "dfu_alt_info=mmc raw 0 3867148288\0" \
+ "update_filename=u-boot-with-spl.sfp\0" \
+ "update_sd_offset=0x800\0" \
+ "update_sd=" /* Update the SD firmware partition */ \
+ "if mmc rescan ; then " \
+ "if tftp ${update_filename} ; then " \
+ "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
+ "setexpr fw_sz ${fw_sz} + 1 ; " \
+ "mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \
+ "fi ; " \
+ "fi\0" \
+ "update_qspi_offset=0x0\0" \
+ "update_qspi=" /* Update the QSPI firmware */ \
+ "if sf probe ; then " \
+ "if tftp ${update_filename} ; then " \
+ "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
+ "fi ; " \
+ "fi\0" \
+ "fpga_filename=output_file.rbf\0" \
+ "load_fpga=" /* Load FPGA bitstream */ \
+ "if tftp ${fpga_filename} ; then " \
+ "fpga load 0 $loadaddr $filesize ; " \
+ "bridge enable ; " \
+ "fi\0" \
+ "addcons=" \
+ "setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "addip=" \
+ "setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off\0" \
+ "addmisc=" \
+ "setenv bootargs ${bootargs} ${miscargs}\0" \
+ "addargs=run addcons addmisc\0" \
+ "mmcload=" \
+ "mmc rescan ; " \
+ "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \
+ "netload=" \
+ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
+ "miscargs=nohlt panic=1\0" \
+ "mmcargs=setenv bootargs root=PARTUUID=${uuid} rw rootwait\0" \
+ "nfsargs=" \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
+ "mmc_mmc=" \
+ "run mmcload setuuid mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "mmc_nfs=" \
+ "run mmcload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_mmc=" \
+ "run netload setuuid mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_nfs=" \
+ "run netload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "try_bootscript=" \
+ "mmc rescan;" \
+ "if test -e mmc 0:2 ${bootscript} ; then " \
+ "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \
+ "then ; " \
+ "echo Running bootscript... ; " \
+ "source ${kernel_addr_r} ; " \
+ "fi ; " \
+ "fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_ARIES_MCVEVK_H__ */
#define CONFIG_SYS_MEMTEST_START 0
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000
-/*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
/*
* Serial / UART configurations
*/
#define CONFIG_ARMV7_SECURE_MAX_SIZE STM32_SYSRAM_SIZE
#endif
-/*
- * malloc() pool size
- */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
-
/*
* Configuration of the external SRAM memory used by U-Boot
*/
*/
#define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE
-/*
- * Env parameters
- */
-#define CONFIG_ENV_SIZE SZ_4K
-
/* ATAGs */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
/*MMC SD*/
#define CONFIG_SYS_MMC_MAX_DEVICE 3
-#define CONFIG_SUPPORT_EMMC_BOOT
/*****************************************************************************/
#ifdef CONFIG_DISTRO_DEFAULTS
* for nand boot, boot with on ubifs partition on nand
* for nor boot, use the default order
*/
-#define CONFIG_PREBOOT
-
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
"if test ${boot_device} = serial || test ${boot_device} = usb;" \
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
- DSPI_CTAR_PCSSCK_1CLK | \
- DSPI_CTAR_PASC(0) | \
- DSPI_CTAR_PDT(0) | \
- DSPI_CTAR_CSSCK(0) | \
- DSPI_CTAR_ASC(0) | \
- DSPI_CTAR_DT(1) | \
- DSPI_CTAR_BR(6))
-#define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
-#define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
-
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_STRIDER 1 /* STRIDER board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_MII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
- SICRH_ESDHC_A_SD |\
- SICRH_ESDHC_B_SD |\
- SICRH_ESDHC_C_SD |\
- SICRH_GPIO_A_GPIO |\
- SICRH_GPIO_B_GPIO |\
- SICRH_IEEE1588_A_GPIO |\
- SICRH_USB |\
- SICRH_GTM_GPIO |\
- SICRH_IEEE1588_B_GPIO |\
- SICRH_ETSEC2_GPIO |\
- SICRH_GPIOSEL_1 |\
- SICRH_TMROBI_V3P3 |\
- SICRH_TSOBI1_V2P5 |\
- SICRH_TSOBI2_V2P5) /* 0x0037f103 */
-#define CONFIG_SYS_SICRL (\
- SICRL_SPI_PF0 |\
- SICRL_UART_PF0 |\
- SICRL_IRQ_PF0 |\
- SICRL_I2C2_PF0 |\
- SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
/*
* SERDES
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-/*
- * FPGA
- */
-#define CONFIG_SYS_FPGA0_BASE 0xE0600000
-#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
-
-/* Window base at FPGA base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_TRLX_CLEAR \
- | OR_GPCM_EHTR_CLEAR)
-
-#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k) 0x0010
#define CONFIG_SYS_FPGA_COUNT 1
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
/*
* Environment Configuration
*/
#ifndef __CONFIG_STV0991_H
#define __CONFIG_STV0991_H
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
/* ram memory-related information */
#define BOOT_TARGET_DEVICES_USB(func)
#endif
+#ifdef CONFIG_CMD_PXE
+#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
/* FEL boot support, auto-execute boot.scr if a script address was provided */
#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \
"bootcmd_fel=" \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
BOOT_TARGET_DEVICES_USB(func) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
+ BOOT_TARGET_DEVICES_PXE(func) \
+ BOOT_TARGET_DEVICES_DHCP(func)
#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
#define BOOTCMD_SUNXI_COMPAT \
* High Level Configuration Options
*/
-/* This needs to be set prior to including km/km83xx-common.h */
-
-#if defined(CONFIG_SUVD3) /* SUVD3 board specific */
#define CONFIG_HOSTNAME "suvd3"
-#define CONFIG_KM_BOARD_NAME "suvd3"
-/* include common defines/options for all 8321 Keymile boards */
-#include "km/km8321-common.h"
-
-#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */
-#define CONFIG_HOSTNAME "kmvect1"
-#define CONFIG_KM_BOARD_NAME "kmvect1"
-/* at end of uboot partition, before env */
-#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
-/* include common defines/options for all 8309 Keymile boards */
-#include "km/km8309-common.h"
-
-#elif defined(CONFIG_KMTEGR1) /* TEGR1 board specific */
-#define CONFIG_HOSTNAME "kmtegr1"
-#define CONFIG_KM_BOARD_NAME "kmtegr1"
-#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
-#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
-
-#define CONFIG_ENV_ADDR 0xF0100000
-#define CONFIG_ENV_OFFSET 0x100000
-
-#define CONFIG_NAND_ECC_BCH
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-
-/* include common defines/options for all 8309 Keymile boards */
-#include "km/km8309-common.h"
-/* must be after the include because KMBEC_FPGA is otherwise undefined */
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
-
-#else
-#error Supported boards are: SUVD3, KMVECT1, KMTEGR1
-#endif
-
-#define CONFIG_SYS_APP1_BASE 0xA0000000
-#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
-#define CONFIG_SYS_APP2_BASE 0xB0000000
-#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus Machine PortSz Size Device
- * ---- --- ------- ------ ----- ------
- * 2 Local UPMA 16 bit 256MB APP1
- * 3 Local GPCM 16 bit 256MB APP2
- *
- */
-
-#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
-/*
- * APP1 on the local bus CS2
- */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
- BR_PS_16 | \
- BR_MS_UPMA | \
- BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
+#define CONFIG_KM_BOARD_NAME "suvd3"
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
- BR_PS_16 | \
- BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV4 | \
- OR_GPCM_SCY_3 | \
- OR_GPCM_TRLX_SET)
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
MxMR_WLFx_2X)
-
-#elif defined(CONFIG_KMTEGR1)
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
- BR_PS_16 | \
- BR_MS_GPCM | \
- BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
- OR_GPCM_SCY_5 | \
- OR_GPCM_TRLX_CLEAR | \
- OR_GPCM_EHTR_CLEAR)
-
-#endif /* CONFIG_KMTEGR1 */
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-/*
- * MMU Setup
- */
-#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
-/* APP1: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#elif defined(CONFIG_KMTEGR1)
-#define CONFIG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#endif /* CONFIG_KMTEGR1 */
-
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/*
- * QE UEC ethernet configuration
- */
-#if defined(CONFIG_KMVECT1)
-#define CONFIG_MV88E6352_SWITCH
-#define CONFIG_KM_MVEXTSW_ADDR 0x10
-
-/* ethernet port connected to simple switch 88e6122 (UEC0) */
-#define CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
-
-#define CONFIG_FIXED_PHY 0xFFFFFFFF
-#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
-#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
- {devnum, speed, duplex}
-#define CONFIG_SYS_FIXED_PHY_PORTS \
- CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
-
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif /* CONFIG_KMVECT1 */
-
-#if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1)
-/* ethernet port connected to piggy (UEC2) */
-#define CONFIG_HAS_ETH1
-#define CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 0
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */
-
#endif /* __CONFIG_H */
#include <asm/hardware.h>
#include <linux/sizes.h>
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
* adapting the initial boot program.
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
/* general purpose I/O */
#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
-/* serial console */
-#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
-
/*
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
/* SPI EEPROM */
#define TAURUS_SPI_MASK (1 << 4)
-#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
#if defined(CONFIG_SPL_BUILD)
/* SPL related */
#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_OFFSET_REDUND 0x180000
#define CONFIG_ENV_SIZE (SZ_128K) /* 1 sector = 128 kB */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
+#ifndef CONFIG_SPL_BUILD
+#if defined(CONFIG_BOARD_AXM)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+ "${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \
+ "addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \
+ "boot_file=setenv bootfile /${project_dir}/kernel/uImage\0" \
+ "boot_retries=0\0" \
+ "ethact=macb0\0" \
+ "flash_nfs=run nand_kernel;run nfsargs;run addip;" \
+ "upgrade_available;bootm ${kernel_ram};reset\0" \
+ "flash_self=run nand_kernel;run setbootargs;upgrade_available;" \
+ "bootm ${kernel_ram};reset\0" \
+ "flash_self_test=run nand_kernel;run setbootargs addtest;" \
+ "upgrade_available;bootm ${kernel_ram};reset\0" \
+ "hostname=systemone\0" \
+ "kernel_Off=0x00200000\0" \
+ "kernel_Off_fallback=0x03800000\0" \
+ "kernel_ram=0x21500000\0" \
+ "kernel_size=0x00400000\0" \
+ "kernel_size_fallback=0x00400000\0" \
+ "loads_echo=1\0" \
+ "nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} " \
+ "${kernel_size}\0" \
+ "net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};" \
+ "run nfsargs;run addip;upgrade_available;" \
+ "bootm ${kernel_ram};reset\0" \
+ "netdev=eth0\0" \
+ "nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs " \
+ "rw nfsroot=${serverip}:${rootpath} " \
+ "at91sam9_wdt.wdt_timeout=16\0" \
+ "partitionset_active=A\0" \
+ "preboot=echo;echo Type 'run flash_self' to use kernel and root " \
+ "filesystem on memory;echo Type 'run flash_nfs' to use " \
+ "kernel from memory and root filesystem over NFS;echo Type " \
+ "'run net_nfs' to get Kernel over TFTP and mount root " \
+ "filesystem over NFS;echo\0" \
+ "project_dir=systemone\0" \
+ "root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0" \
+ "rootfs=/dev/mtdblock5\0" \
+ "rootfs_fallback=/dev/mtdblock7\0" \
+ "setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops " \
+ "root=${rootfs} rootfstype=jffs2 panic=7 " \
+ "at91sam9_wdt.wdt_timeout=16\0" \
+ "stderr=serial\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "upgrade_available=0\0"
+#endif
+#endif /* #ifndef CONFIG_SPL_BUILD */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
#ifndef CONFIG_SPL_BUILD
+#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
+#endif
#include <config_distro_bootcmd.h>
#else
#define BOOTENV
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
-#define CONFIG_SYS_DCACHE_OFF
/* Memory Configuration */
#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME "tuge1"
+#define CONFIG_HOSTNAME "tuge1"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-/*
- * Commands configuration
- */
-
-/* I2C support */
-#define CONFIG_DM_I2C
-#define CONFIG_I2C_MUX
-#define CONFIG_I2C_MUX_PCA954x
-#define CONFIG_SPL_I2C_MUX
-#define CONFIG_SYS_I2C_MVTWSI
-
-/*
- * SDIO/MMC Card Configuration
- */
-#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
-
-/*
- * SATA/SCSI/AHCI configuration
- */
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define BOOT_TARGET_DEVICES_USB(func)
#endif
+#ifdef CONFIG_SCSI
+#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
+#else
+#define BOOT_TARGET_DEVICES_SCSI(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_USB(func) \
+ BOOT_TARGET_DEVICES_SCSI(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
/*
* High Level Configuration Options
*/
-#if defined(CONFIG_KMSUPX5)
-#define CONFIG_KM_BOARD_NAME "kmsupx5"
-#define CONFIG_HOSTNAME "kmsupx5"
-#elif defined(CONFIG_TUGE1)
-#define CONFIG_KM_BOARD_NAME "tuge1"
-#define CONFIG_HOSTNAME "tuge1"
-#elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */
#define CONFIG_KM_BOARD_NAME "tuxx1"
#define CONFIG_HOSTNAME "tuxx1"
-#elif defined(CONFIG_KMOPTI2)
-#define CONFIG_KM_BOARD_NAME "kmopti2"
-#define CONFIG_HOSTNAME "kmopti2"
-#elif defined(CONFIG_KMTEPR2)
-#define CONFIG_KM_BOARD_NAME "kmtepr2"
-#define CONFIG_HOSTNAME "kmtepr2"
-#else
-#error ("Board not supported")
-#endif
-/* include common defines/options for all 8321 Keymile boards */
-#include "km/km8321-common.h"
-
-#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
-#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
-#if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
-#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
-#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
-#endif
-
-/*
- * Init Local Bus Memory Controller:
- * Device on board
- * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2
- * -----------------------------------------------------------------------------
- * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
- * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
- *
- * Device on board (continued)
- * Bank Bus Machine PortSz Size KMTEPR2
- * -----------------------------------------------------------------------------
- * 2 Local GPCM 8 bit 256MB NVRAM
- * 3 Local GPCM 8 bit 256MB TEP2 (16 bit)
- */
-
-#if defined(CONFIG_KMTEPRO2)
-/*
- * Configuration for C2 (NVRAM) on the local bus
- */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
- BR_PS_8 | \
- BR_MS_GPCM | \
- BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV2 | \
- OR_GPCM_XACS | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX_SET | \
- OR_GPCM_EHTR_SET | \
- OR_GPCM_EAD)
-#else
-/*
- * Configuration for C2 on the local bus
- */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
-/* Window size: 256 MB */
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
- BR_PS_8 | \
- BR_MS_GPCM | \
- BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV4 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX_SET | \
- OR_GPCM_EHTR_CLEAR | \
- OR_GPCM_EAD)
-#endif
-
-#if defined(CONFIG_TUXX1)
-/*
- * Configuration for C3 on the local bus
- */
-/* Access window base at PINC3 base */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
-/* Window size: 256 MB */
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
- BR_PS_8 | \
- BR_MS_GPCM | \
- BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX_SET | \
- OR_GPCM_EHTR_CLEAR)
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
MxMR_WLFx_2X)
-#endif
-
-#if defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
-/*
- * Configuration for C3 on the local bus
- */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
- BR_PS_16 | \
- BR_MS_GPCM | \
- BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
- OR_GPCM_SCY_4 | \
- OR_GPCM_TRLX_CLEAR | \
- OR_GPCM_EHTR_CLEAR)
-#endif
-
-/*
- * MMU Setup
- */
-/* APP1: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
- BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-/* 512M should also include APP2... */
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \
- BATU_BL_256M | \
- BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \
- BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5)
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#else
-/* APP2: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \
- BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \
- BATU_BL_256M | \
- BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \
- BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#endif
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2009 TechNexion Ltd.
- *
- * Configuration for the Technexion twister board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "tam3517-common.h"
-
-#define CONFIG_MACH_TYPE MACH_TYPE_TAM3517
-
-#define CONFIG_TAM3517_SW3_SETTINGS
-#define CONFIG_XR16L2751
-
-
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_HOSTNAME "twister"
-
-#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
- "bootcmd=run nandboot\0"
-
-/* SPL OS boot options */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
-
-#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
-
-#endif /* __CONFIG_H */
* MMU and Cache Setting
*----------------------------------------------------------------------*/
-/* Comment out the following to enable L1 cache */
-/* #define CONFIG_SYS_ICACHE_OFF */
-/* #define CONFIG_SYS_DCACHE_OFF */
-
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-/* SD/MMC */
-#define CONFIG_SUPPORT_EMMC_BOOT
-
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* USB */
-#define CONFIG_USB_EHCI_MX5
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
* High Level Configuration Options
*/
#define CONFIG_E300 1
-#define CONFIG_MPC831x 1
-#define CONFIG_MPC8313 1
#define CONFIG_PCI_INDIRECT_BRIDGE 1
#define CONFIG_FSL_ELBC 1
* On-board devices
*
*/
-#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07000000
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
-
/*
* Device configurations
*/
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
/*
* Manually set up DDR parameters, as this board does not
#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV4 \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EAD)
- /* 0xfe000c55 */
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
/*
* NAND settings
*/
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_PS_8 \
- | BR_DECC_CHK_GEN \
- | BR_MS_FCM \
- | BR_V) /* valid */
- /* 0x61000c21 */
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
- | OR_FCM_BCTLD \
- | OR_FCM_CHT \
- | OR_FCM_SCY_2 \
- | OR_FCM_RST \
- | OR_FCM_TRLX)
- /* 0xffff90ac */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
-/* CS2 NvRAM */
-#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
- | BR_PS_8 \
- | BR_V)
- /* 0x60000801 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_3 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfffe0937 */
-/* local bus read write buffer mapping SRAM@0x64000000 */
-#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
- | BR_PS_16 \
- | BR_V)
- /* 0x62001001 */
-
-#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfe0009f7 */
+
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+
+
/*
* Serial Port
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-/* 0x64050000 */
-#define CONFIG_SYS_HRCW_LOW (\
- 0x20000000 /* reserved, must be set */ |\
- HRCWL_DDRCM |\
- HRCWL_CSB_TO_CLKIN_4X1 | \
- HRCWL_CORE_TO_CSB_2_5X1)
-
-/* 0xa0600004 */
-#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
- HRCWH_PCI_ARBITER_ENABLE | \
- HRCWH_CORE_ENABLE | \
- HRCWH_FROM_0X00000100 | \
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT | \
- HRCWH_TSEC1M_IN_MII | \
- HRCWH_BIG_ENDIAN | \
- HRCWH_LALE_EARLY)
-
/* System IO Config */
#define CONFIG_SYS_SICRH (0x01000000 | \
SICRH_ETSEC2_B | \
SICRL_ETSEC2_A)
/* 0x33fc0003) */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#if defined(CONFIG_PCI)
-/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
-#endif
-
-/* PCI2 not supported on 8313 */
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* FPGA, SRAM, NAND @ 0x60000000 */
-#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#define CONFIG_NETDEV eth0
#define CONFIG_HOSTNAME "ve8313"
/* MMC */
#ifdef CONFIG_CMD_MMC
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI 0xfc000000
#define CONFIG_SYS_MMC_CLK_OD 500000
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#ifdef CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */
/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */
#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * Top level Makefile configuration choices
- */
-#ifdef CONFIG_CADDY2
-#define VME_CADDY2
-#endif
-
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x family */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define CONFIG_SYS_CLK_FREQ 33000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
-#endif
-#endif
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
*/
#undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
/*
* FLASH on the Local Bus
*/
-#ifdef VME_CADDY2
-#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- BR_PS_16 | /* 16bit */ \
- BR_MS_GPCM | /* MSEL = GPCM */ \
- BR_V) /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffc06ff7 */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
-#else
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- BR_PS_16 | /* 16bit */ \
- BR_MS_GPCM | /* MSEL = GPCM */ \
- BR_V) /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xf8006ff7 */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
-#endif
+
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
- | BR_PS_32 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF0001801 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
- | OR_GPCM_SETA)
- /* 0xfffc0208 */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
+
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
/*
#if defined(CONFIG_PCI)
-#define PCI_64BIT
-#define PCI_ONE_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
#define CONFIG_SYS_GPIO1_PRELIM
#define CONFIG_SYS_GPIO1_DIR 0x00100000
#define CONFIG_SYS_GPIO1_DAT 0x00100000
#define CONFIG_SYS_GPIO2_DIR 0x78900000
#define CONFIG_SYS_GPIO2_DAT 0x70100000
-#define CONFIG_HIGH_BATS /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-
-/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
#endif
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#if (CONFIG_SYS_DDR_SIZE == 512)
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
- BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
- BATU_BL_256M | BATU_VS | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#endif
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
-#define CONFIG_SUPPORT_EMMC_BOOT
/* Watchdog */
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */
#endif
#endif
-#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_SERIAL_TAG
#define CONFIG_DFU_ENV_SETTINGS \
- "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
+ "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_DFU_ENV_SETTINGS \
#define CONFIG_MX35_HCLK_FREQ 24000000
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
/* This is required to setup the ESDC controller */
*/
#define CONFIG_MACH_TYPE 736
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/*-----------------------------------------------------------------------
* Real Time Clock Configuration
*/
-#define CONFIG_RTC_MC146818
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
#ifndef __CONFIG_VERSAL_MINI_H
#define __CONFIG_VERSAL_MINI_H
-/* #define CONFIG_SYS_DCACHE_OFF */
-#define CONFIG_SYS_ICACHE_OFF
-
#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000
#define CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_MAY_FAIL
-#if defined(CONFIG_MMC_SDHCI_ZYNQ)
-# define CONFIG_SUPPORT_EMMC_BOOT
-#endif
-
#ifdef CONFIG_NAND_ARASAN
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_ONFI_DETECTION
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x800000
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000)
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000)
#define CONFIG_SYS_MALLOC_LEN 0x2000
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_ALTIVEC 1
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
/* I2C configs */
#define CONFIG_SYS_I2C
#define CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
#include "el6x_common.h"
/* Ethernet */
#define CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk0p1"
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
#include "el6x_common.h"
/* Ethernet */
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-/* Disable dcache for SPL just for sure */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
/* Address in RAM where the parameters must be copied by SPL. */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000
#define __CONFIG_ZYNQ_CSE_H
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_ICACHE_OFF
#include <configs/zynq-common.h>
* @def: default value to return if the property has no value
* @return property value, or @def if not found
*/
-int ofnode_read_u32_default(ofnode ref, const char *propname, u32 def);
+u32 ofnode_read_u32_default(ofnode ref, const char *propname, u32 def);
/**
* ofnode_read_s32_default() - Read a 32-bit integer from a property
*/
int ofnode_read_size(ofnode node, const char *propname);
+/**
+ * ofnode_get_addr_size_index() - get an address/size from a node
+ * based on index
+ *
+ * This reads the register address/size from a node based on index
+ *
+ * @node: node to read from
+ * @index: Index of address to read (0 for first)
+ * @size: Pointer to size of the address
+ * @return address, or FDT_ADDR_T_NONE if not present or invalid
+ */
+phys_addr_t ofnode_get_addr_size_index(ofnode node, int index,
+ fdt_size_t *size);
+
/**
* ofnode_get_addr_index() - get an address from a node
*
* @set_state_simple: do needed pinctrl operations for a peripherl @periph.
* (necessary for pinctrl_simple)
* @get_pin_muxing: display the muxing of a given pin.
+ * @gpio_request_enable: requests and enables GPIO on a certain pin.
+ * Implement this only if you can mux every pin individually as GPIO. The
+ * affected GPIO range is passed along with an offset(pin number) into that
+ * specific GPIO range - function selectors and pin groups are orthogonal
+ * to this, the core will however make sure the pins do not collide.
+ * @gpio_disable_free: free up GPIO muxing on a certain pin, the reverse of
+ * @gpio_request_enable
*/
struct pinctrl_ops {
int (*get_pins_count)(struct udevice *dev);
*/
int (*get_pin_muxing)(struct udevice *dev, unsigned int selector,
char *buf, int size);
+
+ /**
+ * gpio_request_enable: requests and enables GPIO on a certain pin.
+ *
+ * @dev: Pinctrl device to use
+ * @selector: Pin selector
+ * return 0 if OK, -ve on error
+ */
+ int (*gpio_request_enable)(struct udevice *dev, unsigned int selector);
+
+ /**
+ * gpio_disable_free: free up GPIO muxing on a certain pin.
+ *
+ * @dev: Pinctrl device to use
+ * @selector: Pin selector
+ * return 0 if OK, -ve on error
+ */
+ int (*gpio_disable_free)(struct udevice *dev, unsigned int selector);
};
#define pinctrl_get_ops(dev) ((struct pinctrl_ops *)(dev)->driver->ops)
*/
int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf,
int size);
+
+/**
+ * pinctrl_gpio_request() - request a single pin to be used as GPIO
+ *
+ * @dev: GPIO peripheral device
+ * @offset: the GPIO pin offset from the GPIO controller
+ * @return: 0 on success, or negative error code on failure
+ */
+int pinctrl_gpio_request(struct udevice *dev, unsigned offset);
+
+/**
+ * pinctrl_gpio_free() - free a single pin used as GPIO
+ *
+ * @dev: GPIO peripheral device
+ * @offset: the GPIO pin offset from the GPIO controller
+ * @return: 0 on success, or negative error code on failure
+ */
+int pinctrl_gpio_free(struct udevice *dev, unsigned offset);
+
#endif /* __PINCTRL_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __spi_coldfire_h
+#define __spi_coldfire_h
+
+#define MAX_CTAR_REGS 8
+#define MAX_CTAR_FIELDS 8
+
+/*
+ * struct coldfire_spi_platdata - information about a coldfire spi module
+ *
+ * @regs_addr: base address for module registers
+ * @speed_hz: default SCK frequency
+ * @mode: default SPI mode
+ * @num_cs: number of DSPI chipselect signals
+ */
+struct coldfire_spi_platdata {
+ fdt_addr_t regs_addr;
+ uint speed_hz;
+ uint mode;
+ uint num_cs;
+ uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS];
+};
+
+#endif /* __spi_coldfire_h */
+
UCLASS_BLK, /* Block device */
UCLASS_BOARD, /* Device information from hardware */
UCLASS_BOOTCOUNT, /* Bootcount backing store */
+ UCLASS_CACHE, /* Cache controller */
UCLASS_CLK, /* Clock source, e.g. used by peripherals */
UCLASS_CPU, /* CPU, typically part of an SoC */
UCLASS_CROS_EC, /* Chrome OS EC */
#define CLKID_AO_M4_FCLK 13
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
+#define CLKID_AO_SAR_ADC_SEL 16
#define CLKID_AO_SAR_ADC_CLK 18
+#define CLKID_AO_CTS_OSCIN 19
#define CLKID_AO_32K 23
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_5OM 177
+#define CLKID_CPU_CLK 187
+#define CLKID_PCIE_PLL 201
+#define CLKID_VDEC_1 204
+#define CLKID_VDEC_HEVC 207
+#define CLKID_VDEC_HEVCF 210
#endif /* __G12A_CLKC_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H
+#define __DT_BINDINGS_CLOCK_IMX8QM_H
+
+#define IMX8QM_CLK_DUMMY 0
+
+#define IMX8QM_A53_DIV 1
+#define IMX8QM_A53_CLK 2
+#define IMX8QM_A72_DIV 3
+#define IMX8QM_A72_CLK 4
+
+/* SC Clocks. */
+#define IMX8QM_SC_I2C_DIV 5
+#define IMX8QM_SC_I2C_CLK 6
+#define IMX8QM_SC_PID0_DIV 7
+#define IMX8QM_SC_PID0_CLK 8
+#define IMX8QM_SC_PIT_DIV 9
+#define IMX8QM_SC_PIT_CLK 10
+#define IMX8QM_SC_TPM_DIV 11
+#define IMX8QM_SC_TPM_CLK 12
+#define IMX8QM_SC_UART_DIV 13
+#define IMX8QM_SC_UART_CLK 14
+
+/* LSIO */
+#define IMX8QM_PWM0_DIV 15
+#define IMX8QM_PWM0_CLK 16
+#define IMX8QM_PWM1_DIV 17
+#define IMX8QM_PWM1_CLK 18
+#define IMX8QM_PWM2_DIV 19
+#define IMX8QM_PWM2_CLK 20
+#define IMX8QM_PWM3_DIV 21
+#define IMX8QM_PWM3_CLK 22
+#define IMX8QM_PWM4_DIV 23
+#define IMX8QM_PWM4_CLK 24
+#define IMX8QM_PWM5_DIV 26
+#define IMX8QM_PWM5_CLK 27
+#define IMX8QM_PWM6_DIV 28
+#define IMX8QM_PWM6_CLK 29
+#define IMX8QM_PWM7_DIV 30
+#define IMX8QM_PWM7_CLK 31
+#define IMX8QM_FSPI0_DIV 32
+#define IMX8QM_FSPI0_CLK 33
+#define IMX8QM_FSPI1_DIV 34
+#define IMX8QM_FSPI1_CLK 35
+#define IMX8QM_GPT0_DIV 36
+#define IMX8QM_GPT0_CLK 37
+#define IMX8QM_GPT1_DIV 38
+#define IMX8QM_GPT1_CLK 39
+#define IMX8QM_GPT2_DIV 40
+#define IMX8QM_GPT2_CLK 41
+#define IMX8QM_GPT3_DIV 42
+#define IMX8QM_GPT3_CLK 43
+#define IMX8QM_GPT4_DIV 44
+#define IMX8QM_GPT4_CLK 45
+
+/* Connectivity */
+#define IMX8QM_APBHDMA_CLK 46
+#define IMX8QM_GPMI_APB_CLK 47
+#define IMX8QM_GPMI_APB_BCH_CLK 48
+#define IMX8QM_GPMI_BCH_IO_DIV 49
+#define IMX8QM_GPMI_BCH_IO_CLK 50
+#define IMX8QM_GPMI_BCH_DIV 51
+#define IMX8QM_GPMI_BCH_CLK 52
+#define IMX8QM_SDHC0_IPG_CLK 53
+#define IMX8QM_SDHC0_DIV 54
+#define IMX8QM_SDHC0_CLK 55
+#define IMX8QM_SDHC1_IPG_CLK 56
+#define IMX8QM_SDHC1_DIV 57
+#define IMX8QM_SDHC1_CLK 58
+#define IMX8QM_SDHC2_IPG_CLK 59
+#define IMX8QM_SDHC2_DIV 60
+#define IMX8QM_SDHC2_CLK 61
+#define IMX8QM_USB2_OH_AHB_CLK 62
+#define IMX8QM_USB2_OH_IPG_S_CLK 63
+#define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64
+#define IMX8QM_USB2_PHY_IPG_CLK 65
+#define IMX8QM_USB3_IPG_CLK 66
+#define IMX8QM_USB3_CORE_PCLK 67
+#define IMX8QM_USB3_PHY_CLK 68
+#define IMX8QM_USB3_ACLK_DIV 69
+#define IMX8QM_USB3_ACLK 70
+#define IMX8QM_USB3_BUS_DIV 71
+#define IMX8QM_USB3_BUS_CLK 72
+#define IMX8QM_USB3_LPM_DIV 73
+#define IMX8QM_USB3_LPM_CLK 74
+#define IMX8QM_ENET0_AHB_CLK 75
+#define IMX8QM_ENET0_IPG_S_CLK 76
+#define IMX8QM_ENET0_IPG_CLK 77
+#define IMX8QM_ENET0_RGMII_DIV 78
+#define IMX8QM_ENET0_RGMII_TX_CLK 79
+#define IMX8QM_ENET0_ROOT_DIV 80
+#define IMX8QM_ENET0_TX_CLK 81
+#define IMX8QM_ENET0_ROOT_CLK 82
+#define IMX8QM_ENET0_PTP_CLK 83
+#define IMX8QM_ENET0_BYPASS_DIV 84
+#define IMX8QM_ENET1_AHB_CLK 85
+#define IMX8QM_ENET1_IPG_S_CLK 86
+#define IMX8QM_ENET1_IPG_CLK 87
+#define IMX8QM_ENET1_RGMII_DIV 88
+#define IMX8QM_ENET1_RGMII_TX_CLK 89
+#define IMX8QM_ENET1_ROOT_DIV 90
+#define IMX8QM_ENET1_TX_CLK 91
+#define IMX8QM_ENET1_ROOT_CLK 92
+#define IMX8QM_ENET1_PTP_CLK 93
+#define IMX8QM_ENET1_BYPASS_DIV 94
+#define IMX8QM_MLB_CLK 95
+#define IMX8QM_MLB_HCLK 96
+#define IMX8QM_MLB_IPG_CLK 97
+#define IMX8QM_EDMA_CLK 98
+#define IMX8QM_EDMA_IPG_CLK 99
+
+/* DMA */
+#define IMX8QM_SPI0_IPG_CLK 100
+#define IMX8QM_SPI0_DIV 101
+#define IMX8QM_SPI0_CLK 102
+#define IMX8QM_SPI1_IPG_CLK 103
+#define IMX8QM_SPI1_DIV 104
+#define IMX8QM_SPI1_CLK 105
+#define IMX8QM_SPI2_IPG_CLK 106
+#define IMX8QM_SPI2_DIV 107
+#define IMX8QM_SPI2_CLK 108
+#define IMX8QM_SPI3_IPG_CLK 109
+#define IMX8QM_SPI3_DIV 110
+#define IMX8QM_SPI3_CLK 111
+#define IMX8QM_UART0_IPG_CLK 112
+#define IMX8QM_UART0_DIV 113
+#define IMX8QM_UART0_CLK 114
+#define IMX8QM_UART1_IPG_CLK 115
+#define IMX8QM_UART1_DIV 116
+#define IMX8QM_UART1_CLK 117
+#define IMX8QM_UART2_IPG_CLK 118
+#define IMX8QM_UART2_DIV 119
+#define IMX8QM_UART2_CLK 120
+#define IMX8QM_UART3_IPG_CLK 121
+#define IMX8QM_UART3_DIV 122
+#define IMX8QM_UART3_CLK 123
+#define IMX8QM_UART4_IPG_CLK 124
+#define IMX8QM_UART4_DIV 125
+#define IMX8QM_EMVSIM0_IPG_CLK 126
+#define IMX8QM_UART4_CLK 127
+#define IMX8QM_EMVSIM0_DIV 128
+#define IMX8QM_EMVSIM0_CLK 129
+#define IMX8QM_EMVSIM1_IPG_CLK 130
+#define IMX8QM_EMVSIM1_DIV 131
+#define IMX8QM_EMVSIM1_CLK 132
+#define IMX8QM_CAN0_IPG_CHI_CLK 133
+#define IMX8QM_CAN0_IPG_CLK 134
+#define IMX8QM_CAN0_DIV 135
+#define IMX8QM_CAN0_CLK 136
+#define IMX8QM_CAN1_IPG_CHI_CLK 137
+#define IMX8QM_CAN1_IPG_CLK 138
+#define IMX8QM_CAN1_DIV 139
+#define IMX8QM_CAN1_CLK 140
+#define IMX8QM_CAN2_IPG_CHI_CLK 141
+#define IMX8QM_CAN2_IPG_CLK 142
+#define IMX8QM_CAN2_DIV 143
+#define IMX8QM_CAN2_CLK 144
+#define IMX8QM_I2C0_IPG_CLK 145
+#define IMX8QM_I2C0_DIV 146
+#define IMX8QM_I2C0_CLK 147
+#define IMX8QM_I2C1_IPG_CLK 148
+#define IMX8QM_I2C1_DIV 149
+#define IMX8QM_I2C1_CLK 150
+#define IMX8QM_I2C2_IPG_CLK 151
+#define IMX8QM_I2C2_DIV 152
+#define IMX8QM_I2C2_CLK 153
+#define IMX8QM_I2C3_IPG_CLK 154
+#define IMX8QM_I2C3_DIV 155
+#define IMX8QM_I2C3_CLK 156
+#define IMX8QM_I2C4_IPG_CLK 157
+#define IMX8QM_I2C4_DIV 158
+#define IMX8QM_I2C4_CLK 159
+#define IMX8QM_FTM0_IPG_CLK 160
+#define IMX8QM_FTM0_DIV 161
+#define IMX8QM_FTM0_CLK 162
+#define IMX8QM_FTM1_IPG_CLK 163
+#define IMX8QM_FTM1_DIV 164
+#define IMX8QM_FTM1_CLK 165
+#define IMX8QM_ADC0_IPG_CLK 166
+#define IMX8QM_ADC0_DIV 167
+#define IMX8QM_ADC0_CLK 168
+#define IMX8QM_ADC1_IPG_CLK 169
+#define IMX8QM_ADC1_DIV 170
+#define IMX8QM_ADC1_CLK 171
+
+/* Audio */
+#define IMX8QM_AUD_PLL0_DIV 172
+#define IMX8QM_AUD_PLL0 173
+#define IMX8QM_AUD_PLL1_DIV 174
+#define IMX8QM_AUD_PLL1 175
+#define IMX8QM_AUD_AMIX_IPG 182
+#define IMX8QM_AUD_ESAI_0_IPG 183
+#define IMX8QM_AUD_ESAI_1_IPG 184
+#define IMX8QM_AUD_ESAI_0_EXTAL_IPG 185
+#define IMX8QM_AUD_ESAI_1_EXTAL_IPG 186
+#define IMX8QM_AUD_SAI_0_IPG 187
+#define IMX8QM_AUD_SAI_0_IPG_S 188
+#define IMX8QM_AUD_SAI_0_MCLK 189
+#define IMX8QM_AUD_SAI_1_IPG 190
+#define IMX8QM_AUD_SAI_1_IPG_S 191
+#define IMX8QM_AUD_SAI_1_MCLK 192
+#define IMX8QM_AUD_SAI_2_IPG 193
+#define IMX8QM_AUD_SAI_2_IPG_S 194
+#define IMX8QM_AUD_SAI_2_MCLK 195
+#define IMX8QM_AUD_SAI_3_IPG 196
+#define IMX8QM_AUD_SAI_3_IPG_S 197
+#define IMX8QM_AUD_SAI_3_MCLK 198
+#define IMX8QM_AUD_SAI_6_IPG 199
+#define IMX8QM_AUD_SAI_6_IPG_S 200
+#define IMX8QM_AUD_SAI_6_MCLK 201
+#define IMX8QM_AUD_SAI_7_IPG 202
+#define IMX8QM_AUD_SAI_7_IPG_S 203
+#define IMX8QM_AUD_SAI_7_MCLK 204
+#define IMX8QM_AUD_SAI_HDMIRX0_IPG 205
+#define IMX8QM_AUD_SAI_HDMIRX0_IPG_S 206
+#define IMX8QM_AUD_SAI_HDMIRX0_MCLK 207
+#define IMX8QM_AUD_SAI_HDMITX0_IPG 208
+#define IMX8QM_AUD_SAI_HDMITX0_IPG_S 209
+#define IMX8QM_AUD_SAI_HDMITX0_MCLK 210
+#define IMX8QM_AUD_MQS_IPG 211
+#define IMX8QM_AUD_MQS_HMCLK 212
+#define IMX8QM_AUD_GPT5_IPG_S 213
+#define IMX8QM_AUD_GPT5_CLKIN 214
+#define IMX8QM_AUD_GPT5_24M_CLK 215
+#define IMX8QM_AUD_GPT6_IPG_S 216
+#define IMX8QM_AUD_GPT6_CLKIN 217
+#define IMX8QM_AUD_GPT6_24M_CLK 218
+#define IMX8QM_AUD_GPT7_IPG_S 219
+#define IMX8QM_AUD_GPT7_CLKIN 220
+#define IMX8QM_AUD_GPT7_24M_CLK 221
+#define IMX8QM_AUD_GPT8_IPG_S 222
+#define IMX8QM_AUD_GPT8_CLKIN 223
+#define IMX8QM_AUD_GPT8_24M_CLK 224
+#define IMX8QM_AUD_GPT9_IPG_S 225
+#define IMX8QM_AUD_GPT9_CLKIN 226
+#define IMX8QM_AUD_GPT9_24M_CLK 227
+#define IMX8QM_AUD_GPT10_IPG_S 228
+#define IMX8QM_AUD_GPT10_CLKIN 229
+#define IMX8QM_AUD_GPT10_24M_CLK 230
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV 232
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK 233
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV 234
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK 235
+#define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV 236
+#define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK 237
+#define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV 238
+#define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK 239
+#define IMX8QM_AUD_MCLKOUT0 240
+#define IMX8QM_AUD_MCLKOUT1 241
+#define IMX8QM_AUD_SPDIF_0_TX_CLK 242
+#define IMX8QM_AUD_SPDIF_0_GCLKW 243
+#define IMX8QM_AUD_SPDIF_0_IPG_S 244
+#define IMX8QM_AUD_SPDIF_1_TX_CLK 245
+#define IMX8QM_AUD_SPDIF_1_GCLKW 246
+#define IMX8QM_AUD_SPDIF_1_IPG_S 247
+#define IMX8QM_AUD_ASRC_0_IPG 248
+#define IMX8QM_AUD_ASRC_0_MEM 249
+#define IMX8QM_AUD_ASRC_1_IPG 250
+#define IMX8QM_AUD_ASRC_1_MEM 251
+
+/* VPU */
+#define IMX8QM_VPU_CORE_DIV 252
+#define IMX8QM_VPU_CORE_CLK 253
+#define IMX8QM_VPU_UART_DIV 254
+#define IMX8QM_VPU_UART_CLK 255
+#define IMX8QM_VPU_DDR_DIV 256
+#define IMX8QM_VPU_DDR_CLK 257
+#define IMX8QM_VPU_SYS_DIV 258
+#define IMX8QM_VPU_SYS_CLK 259
+#define IMX8QM_VPU_XUVI_DIV 260
+#define IMX8QM_VPU_XUVI_CLK 261
+
+/* GPU Clocks. */
+#define IMX8QM_GPU0_CORE_DIV 262
+#define IMX8QM_GPU0_CORE_CLK 263
+#define IMX8QM_GPU0_SHADER_DIV 264
+#define IMX8QM_GPU0_SHADER_CLK 265
+#define IMX8QM_GPU1_CORE_DIV 266
+#define IMX8QM_GPU1_CORE_CLK 267
+#define IMX8QM_GPU1_SHADER_DIV 268
+#define IMX8QM_GPU1_SHADER_CLK 269
+
+/* MIPI CSI */
+#define IMX8QM_CSI0_IPG_CLK_S 270
+#define IMX8QM_CSI0_LIS_IPG_CLK 271
+#define IMX8QM_CSI0_APB_CLK 272
+#define IMX8QM_CSI0_I2C0_DIV 273
+#define IMX8QM_CSI0_I2C0_CLK 274
+#define IMX8QM_CSI0_PWM0_DIV 275
+#define IMX8QM_CSI0_PWM0_CLK 276
+#define IMX8QM_CSI0_CORE_DIV 277
+#define IMX8QM_CSI0_CORE_CLK 278
+#define IMX8QM_CSI0_ESC_DIV 279
+#define IMX8QM_CSI0_ESC_CLK 280
+#define IMX8QM_CSI1_IPG_CLK_S 281
+#define IMX8QM_CSI1_LIS_IPG_CLK 282
+#define IMX8QM_CSI1_APB_CLK 283
+#define IMX8QM_CSI1_I2C0_DIV 284
+#define IMX8QM_CSI1_I2C0_CLK 285
+#define IMX8QM_CSI1_PWM0_DIV 286
+#define IMX8QM_CSI1_PWM0_CLK 287
+#define IMX8QM_CSI1_CORE_DIV 288
+#define IMX8QM_CSI1_CORE_CLK 289
+#define IMX8QM_CSI1_ESC_DIV 290
+#define IMX8QM_CSI1_ESC_CLK 291
+
+/* Display */
+#define IMX8QM_DC0_PLL0_DIV 292
+#define IMX8QM_DC0_PLL0_CLK 293
+#define IMX8QM_DC0_PLL1_DIV 294
+#define IMX8QM_DC0_PLL1_CLK 295
+#define IMX8QM_DC0_DISP0_DIV 296
+#define IMX8QM_DC0_DISP0_CLK 297
+#define IMX8QM_DC0_DISP1_DIV 298
+#define IMX8QM_DC0_DISP1_CLK 299
+#define IMX8QM_DC0_BYPASS_0_DIV 300
+#define IMX8QM_DC0_BYPASS_1_DIV 301
+#define IMX8QM_DC0_IRIS_AXI_CLK 302
+#define IMX8AM_DC0_IRIS_MVPL_CLK 303
+#define IMX8QM_DC0_DISP0_MSI_CLK 304
+#define IMX8QM_DC0_LIS_IPG_CLK 305
+#define IMX8QM_DC0_PXL_CMB_APB_CLK 306
+#define IMX8QM_DC0_PRG0_RTRAM_CLK 307
+#define IMX8QM_DC0_PRG1_RTRAM_CLK 308
+#define IMX8QM_DC0_PRG2_RTRAM_CLK 309
+#define IMX8QM_DC0_PRG3_RTRAM_CLK 310
+#define IMX8QM_DC0_PRG4_RTRAM_CLK 311
+#define IMX8QM_DC0_PRG5_RTRAM_CLK 312
+#define IMX8QM_DC0_PRG6_RTRAM_CLK 313
+#define IMX8QM_DC0_PRG7_RTRAM_CLK 314
+#define IMX8QM_DC0_PRG8_RTRAM_CLK 315
+#define IMX8QM_DC0_PRG0_APB_CLK 316
+#define IMX8QM_DC0_PRG1_APB_CLK 317
+#define IMX8QM_DC0_PRG2_APB_CLK 318
+#define IMX8QM_DC0_PRG3_APB_CLK 319
+#define IMX8QM_DC0_PRG4_APB_CLK 320
+#define IMX8QM_DC0_PRG5_APB_CLK 321
+#define IMX8QM_DC0_PRG6_APB_CLK 322
+#define IMX8QM_DC0_PRG7_APB_CLK 323
+#define IMX8QM_DC0_PRG8_APB_CLK 324
+#define IMX8QM_DC0_DPR0_APB_CLK 325
+#define IMX8QM_DC0_DPR1_APB_CLK 326
+#define IMX8QM_DC0_RTRAM0_CLK 327
+#define IMX8QM_DC0_RTRAM1_CLK 328
+#define IMX8QM_DC1_PLL0_DIV 329
+#define IMX8QM_DC1_PLL0_CLK 330
+#define IMX8QM_DC1_PLL1_DIV 331
+#define IMX8QM_DC1_PLL1_CLK 332
+#define IMX8QM_DC1_DISP0_DIV 333
+#define IMX8QM_DC1_DISP0_CLK 334
+#define IMX8QM_DC1_BYPASS_0_DIV 335
+#define IMX8QM_DC1_BYPASS_1_DIV 336
+#define IMX8QM_DC1_DISP1_DIV 337
+#define IMX8QM_DC1_DISP1_CLK 338
+#define IMX8QM_DC1_IRIS_AXI_CLK 339
+#define IMX8AM_DC1_IRIS_MVPL_CLK 340
+#define IMX8QM_DC1_DISP0_MSI_CLK 341
+#define IMX8QM_DC1_LIS_IPG_CLK 342
+#define IMX8QM_DC1_PXL_CMB_APB_CLK 343
+#define IMX8QM_DC1_PRG0_RTRAM_CLK 344
+#define IMX8QM_DC1_PRG1_RTRAM_CLK 345
+#define IMX8QM_DC1_PRG2_RTRAM_CLK 346
+#define IMX8QM_DC1_PRG3_RTRAM_CLK 347
+#define IMX8QM_DC1_PRG4_RTRAM_CLK 348
+#define IMX8QM_DC1_PRG5_RTRAM_CLK 349
+#define IMX8QM_DC1_PRG6_RTRAM_CLK 350
+#define IMX8QM_DC1_PRG7_RTRAM_CLK 351
+#define IMX8QM_DC1_PRG8_RTRAM_CLK 352
+#define IMX8QM_DC1_PRG0_APB_CLK 353
+#define IMX8QM_DC1_PRG1_APB_CLK 354
+#define IMX8QM_DC1_PRG2_APB_CLK 355
+#define IMX8QM_DC1_PRG3_APB_CLK 356
+#define IMX8QM_DC1_PRG4_APB_CLK 357
+#define IMX8QM_DC1_PRG5_APB_CLK 358
+#define IMX8QM_DC1_PRG6_APB_CLK 359
+#define IMX8QM_DC1_PRG7_APB_CLK 360
+#define IMX8QM_DC1_PRG8_APB_CLK 361
+#define IMX8QM_DC1_DPR0_APB_CLK 362
+#define IMX8QM_DC1_DPR1_APB_CLK 363
+#define IMX8QM_DC1_RTRAM0_CLK 364
+#define IMX8QM_DC1_RTRAM1_CLK 365
+
+/* DRC */
+#define IMX8QM_DRC0_PLL0_DIV 366
+#define IMX8QM_DRC0_PLL0_CLK 367
+#define IMX8QM_DRC0_DIV 368
+#define IMX8QM_DRC0_CLK 369
+#define IMX8QM_DRC1_PLL0_DIV 370
+#define IMX8QM_DRC1_PLL0_CLK 371
+#define IMX8QM_DRC1_DIV 372
+#define IMX8QM_DRC1_CLK 373
+
+/* HDMI */
+#define IMX8QM_HDMI_AV_PLL_DIV 374
+#define IMX8QM_HDMI_AV_PLL_CLK 375
+#define IMX8QM_HDMI_I2S_BYPASS_CLK 376
+#define IMX8QM_HDMI_I2C0_DIV 377
+#define IMX8QM_HDMI_I2C0_CLK 378
+#define IMX8QM_HDMI_PXL_DIV 379
+#define IMX8QM_HDMI_PXL_CLK 380
+#define IMX8QM_HDMI_PXL_LINK_DIV 381
+#define IMX8QM_HDMI_PXL_LINK_CLK 382
+#define IMX8QM_HDMI_PXL_MUX_DIV 383
+#define IMX8QM_HDMI_PXL_MUX_CLK 384
+#define IMX8QM_HDMI_I2S_DIV 385
+#define IMX8QM_HDMI_I2S_CLK 386
+#define IMX8QM_HDMI_HDP_CORE_DIV 387
+#define IMX8QM_HDMI_HDP_CORE_CLK 388
+#define IMX8QM_HDMI_I2C_IPG_S_CLK 389
+#define IMX8QM_HDMI_I2C_IPG_CLK 390
+#define IMX8QM_HDMI_PWM_IPG_S_CLK 391
+#define IMX8QM_HDMI_PWM_IPG_CLK 392
+#define IMX8QM_HDMI_PWM_32K_CLK 393
+#define IMX8QM_HDMI_GPIO_IPG_CLK 394
+#define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK 395
+#define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK 396
+#define IMX8QM_HDMI_LIS_IPG_CLK 397
+#define IMX8QM_HDMI_MSI_HCLK 398
+#define IMX8QM_HDMI_PXL_EVEN_CLK 399
+#define IMX8QM_HDMI_HDP_CLK 400
+#define IMX8QM_HDMI_PXL_DBL_CLK 401
+#define IMX8QM_HDMI_APB_CLK 402
+#define IMX8QM_HDMI_PXL_LPCG_CLK 403
+#define IMX8QM_HDMI_HDP_PHY_CLK 404
+#define IMX8QM_HDMI_IPG_DIV 405
+#define IMX8QM_HDMI_VIF_CLK 406
+#define IMX8QM_HDMI_DIG_PLL_DIV 407
+#define IMX8QM_HDMI_DIG_PLL_CLK 408
+#define IMX8QM_HDMI_APB_MUX_CSR_CLK 409
+#define IMX8QM_HDMI_APB_MUX_CTRL_CLK 410
+
+/* RX-HDMI */
+#define IMX8QM_HDMI_RX_I2S_BYPASS_CLK 411
+#define IMX8QM_HDMI_RX_BYPASS_CLK 412
+#define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK 413
+#define IMX8QM_HDMI_RX_I2C0_DIV 414
+#define IMX8QM_HDMI_RX_I2C0_CLK 415
+#define IMX8QM_HDMI_RX_SPDIF_DIV 416
+#define IMX8QM_HDMI_RX_SPDIF_CLK 417
+#define IMX8QM_HDMI_RX_HD_REF_DIV 418
+#define IMX8QM_HDMI_RX_HD_REF_CLK 419
+#define IMX8QM_HDMI_RX_HD_CORE_DIV 420
+#define IMX8QM_HDMI_RX_HD_CORE_CLK 421
+#define IMX8QM_HDMI_RX_PXL_DIV 422
+#define IMX8QM_HDMI_RX_PXL_CLK 423
+#define IMX8QM_HDMI_RX_I2S_DIV 424
+#define IMX8QM_HDMI_RX_I2S_CLK 425
+#define IMX8QM_HDMI_RX_PWM_DIV 426
+#define IMX8QM_HDMI_RX_PWM_CLK 427
+
+/* LVDS */
+#define IMX8QM_LVDS0_BYPASS_CLK 428
+#define IMX8QM_LVDS0_PIXEL_DIV 429
+#define IMX8QM_LVDS0_PIXEL_CLK 430
+#define IMX8QM_LVDS0_PHY_DIV 431
+#define IMX8QM_LVDS0_PHY_CLK 432
+#define IMX8QM_LVDS0_I2C0_IPG_CLK 433
+#define IMX8QM_LVDS0_I2C0_DIV 434
+#define IMX8QM_LVDS0_I2C0_CLK 435
+#define IMX8QM_LVDS0_I2C1_IPG_CLK 436
+#define IMX8QM_LVDS0_I2C1_DIV 437
+#define IMX8QM_LVDS0_I2C1_CLK 438
+#define IMX8QM_LVDS0_PWM0_IPG_CLK 439
+#define IMX8QM_LVDS0_PWM0_DIV 440
+#define IMX8QM_LVDS0_PWM0_CLK 441
+#define IMX8QM_LVDS0_GPIO_IPG_CLK 444
+#define IMX8QM_LVDS1_BYPASS_DIV 445
+#define IMX8QM_LVDS1_BYPASS_CLK 446
+#define IMX8QM_LVDS1_PIXEL_DIV 447
+#define IMX8QM_LVDS1_PIXEL_CLK 448
+#define IMX8QM_LVDS1_PHY_DIV 449
+#define IMX8QM_LVDS1_PHY_CLK 450
+#define IMX8QM_LVDS1_I2C0_IPG_CLK 451
+#define IMX8QM_LVDS1_I2C0_DIV 452
+#define IMX8QM_LVDS1_I2C0_CLK 453
+#define IMX8QM_LVDS1_I2C1_IPG_CLK 454
+#define IMX8QM_LVDS1_I2C1_DIV 455
+#define IMX8QM_LVDS1_I2C1_CLK 456
+#define IMX8QM_LVDS1_PWM0_IPG_CLK 457
+#define IMX8QM_LVDS1_PWM0_DIV 458
+#define IMX8QM_LVDS1_PWM0_CLK 459
+#define IMX8QM_LVDS1_GPIO_IPG_CLK 462
+
+/* MIPI */
+#define IMX8QM_MIPI0_BYPASS_CLK 465
+#define IMX8QM_MIPI0_I2C0_DIV 466
+#define IMX8QM_MIPI0_I2C0_CLK 467
+#define IMX8QM_MIPI0_I2C1_DIV 468
+#define IMX8QM_MIPI0_I2C1_CLK 469
+#define IMX8QM_MIPI0_PWM0_DIV 470
+#define IMX8QM_MIPI0_PWM0_CLK 471
+#define IMX8QM_MIPI0_DSI_TX_ESC_DIV 472
+#define IMX8QM_MIPI0_DSI_TX_ESC_CLK 473
+#define IMX8QM_MIPI0_DSI_RX_ESC_DIV 474
+#define IMX8QM_MIPI0_DSI_RX_ESC_CLK 475
+#define IMX8QM_MIPI0_PXL_DIV 476
+#define IMX8QM_MIPI0_PXL_CLK 477
+#define IMX8QM_MIPI1_BYPASS_CLK 479
+#define IMX8QM_MIPI1_I2C0_DIV 480
+#define IMX8QM_MIPI1_I2C0_CLK 481
+#define IMX8QM_MIPI1_I2C1_DIV 482
+#define IMX8QM_MIPI1_I2C1_CLK 483
+#define IMX8QM_MIPI1_PWM0_DIV 484
+#define IMX8QM_MIPI1_PWM0_CLK 485
+#define IMX8QM_MIPI1_DSI_TX_ESC_DIV 486
+#define IMX8QM_MIPI1_DSI_TX_ESC_CLK 487
+#define IMX8QM_MIPI1_DSI_RX_ESC_DIV 488
+#define IMX8QM_MIPI1_DSI_RX_ESC_CLK 489
+#define IMX8QM_MIPI1_PXL_DIV 490
+#define IMX8QM_MIPI1_PXL_CLK 491
+
+/* Imaging */
+#define IMX8QM_IMG_JPEG_ENC_IPG_CLK 492
+#define IMX8QM_IMG_JPEG_ENC_CLK 493
+#define IMX8QM_IMG_JPEG_DEC_IPG_CLK 494
+#define IMX8QM_IMG_JPEG_DEC_CLK 495
+#define IMX8QM_IMG_PXL_LINK_DC0_CLK 496
+#define IMX8QM_IMG_PXL_LINK_DC1_CLK 497
+#define IMX8QM_IMG_PXL_LINK_CSI0_CLK 498
+#define IMX8QM_IMG_PXL_LINK_CSI1_CLK 499
+#define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK 500
+#define IMX8QM_IMG_PDMA_0_CLK 501
+#define IMX8QM_IMG_PDMA_1_CLK 502
+#define IMX8QM_IMG_PDMA_2_CLK 503
+#define IMX8QM_IMG_PDMA_3_CLK 504
+#define IMX8QM_IMG_PDMA_4_CLK 505
+#define IMX8QM_IMG_PDMA_5_CLK 506
+#define IMX8QM_IMG_PDMA_6_CLK 507
+#define IMX8QM_IMG_PDMA_7_CLK 508
+
+/* HSIO */
+#define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK 509
+#define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK 510
+#define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK 511
+#define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK 512
+#define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK 513
+#define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK 514
+#define IMX8QM_HSIO_PCIE_X1_PER_CLK 515
+#define IMX8QM_HSIO_PCIE_X2_PER_CLK 516
+#define IMX8QM_HSIO_SATA_PER_CLK 517
+#define IMX8QM_HSIO_PHY_X1_PER_CLK 518
+#define IMX8QM_HSIO_PHY_X2_PER_CLK 519
+#define IMX8QM_HSIO_MISC_PER_CLK 520
+#define IMX8QM_HSIO_PHY_X1_APB_CLK 521
+#define IMX8QM_HSIO_PHY_X2_APB_0_CLK 522
+#define IMX8QM_HSIO_PHY_X2_APB_1_CLK 523
+#define IMX8QM_HSIO_SATA_CLK 524
+#define IMX8QM_HSIO_GPIO_CLK 525
+#define IMX8QM_HSIO_PHY_X1_PCLK 526
+#define IMX8QM_HSIO_PHY_X2_PCLK_0 527
+#define IMX8QM_HSIO_PHY_X2_PCLK_1 528
+#define IMX8QM_HSIO_SATA_EPCS_RX_CLK 529
+#define IMX8QM_HSIO_SATA_EPCS_TX_CLK 530
+
+/* M4 */
+#define IMX8QM_M4_0_CORE_DIV 531
+#define IMX8QM_M4_0_CORE_CLK 532
+#define IMX8QM_M4_0_I2C_DIV 533
+#define IMX8QM_M4_0_I2C_CLK 534
+#define IMX8QM_M4_0_PIT_DIV 535
+#define IMX8QM_M4_0_PIT_CLK 536
+#define IMX8QM_M4_0_TPM_DIV 537
+#define IMX8QM_M4_0_TPM_CLK 538
+#define IMX8QM_M4_0_UART_DIV 539
+#define IMX8QM_M4_0_UART_CLK 540
+#define IMX8QM_M4_0_WDOG_DIV 541
+#define IMX8QM_M4_0_WDOG_CLK 542
+#define IMX8QM_M4_1_CORE_DIV 543
+#define IMX8QM_M4_1_CORE_CLK 544
+#define IMX8QM_M4_1_I2C_DIV 545
+#define IMX8QM_M4_1_I2C_CLK 546
+#define IMX8QM_M4_1_PIT_DIV 547
+#define IMX8QM_M4_1_PIT_CLK 548
+#define IMX8QM_M4_1_TPM_DIV 549
+#define IMX8QM_M4_1_TPM_CLK 550
+#define IMX8QM_M4_1_UART_DIV 551
+#define IMX8QM_M4_1_UART_CLK 552
+#define IMX8QM_M4_1_WDOG_DIV 553
+#define IMX8QM_M4_1_WDOG_CLK 554
+
+/* IPG clocks */
+#define IMX8QM_24MHZ 555
+#define IMX8QM_GPT_3M 556
+#define IMX8QM_IPG_DMA_CLK_ROOT 557
+#define IMX8QM_IPG_AUD_CLK_ROOT 558
+#define IMX8QM_IPG_CONN_CLK_ROOT 559
+#define IMX8QM_AHB_CONN_CLK_ROOT 560
+#define IMX8QM_AXI_CONN_CLK_ROOT 561
+#define IMX8QM_IPG_MIPI_CSI_CLK_ROOT 562
+#define IMX8QM_DC_AXI_EXT_CLK 563
+#define IMX8QM_DC_AXI_INT_CLK 564
+#define IMX8QM_DC_CFG_CLK 565
+#define IMX8QM_HDMI_IPG_CLK 566
+#define IMX8QM_LVDS_IPG_CLK 567
+#define IMX8QM_IMG_AXI_CLK 568
+#define IMX8QM_IMG_IPG_CLK 569
+#define IMX8QM_IMG_PXL_CLK 570
+#define IMX8QM_CSI0_I2C0_IPG_CLK 571
+#define IMX8QM_CSI0_PWM0_IPG_CLK 572
+#define IMX8QM_CSI1_I2C0_IPG_CLK 573
+#define IMX8QM_CSI1_PWM0_IPG_CLK 574
+#define IMX8QM_DC0_DPR0_B_CLK 575
+#define IMX8QM_DC0_DPR1_B_CLK 576
+#define IMX8QM_DC1_DPR0_B_CLK 577
+#define IMX8QM_DC1_DPR1_B_CLK 578
+#define IMX8QM_32KHZ 579
+#define IMX8QM_HSIO_AXI_CLK 580
+#define IMX8QM_HSIO_PER_CLK 581
+#define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK 582
+#define IMX8QM_HDMI_RX_PWM_IPG_S_CLK 583
+#define IMX8QM_HDMI_RX_PWM_IPG_CLK 584
+#define IMX8QM_HDMI_RX_I2C_DIV_CLK 585
+#define IMX8QM_HDMI_RX_I2C_IPG_S_CLK 586
+#define IMX8QM_HDMI_RX_I2C_IPG_CLK 587
+#define IMX8QM_HDMI_RX_SINK_PCLK 588
+#define IMX8QM_HDMI_RX_SINK_SCLK 589
+#define IMX8QM_HDMI_RX_PXL_ENC_CLK 590
+#define IMX8QM_HDMI_RX_IPG_CLK 591
+
+/* ACM */
+#define IMX8QM_HDMI_RX_MCLK 592
+#define IMX8QM_EXT_AUD_MCLK0 593
+#define IMX8QM_EXT_AUD_MCLK1 594
+#define IMX8QM_ESAI0_RX_CLK 595
+#define IMX8QM_ESAI0_RX_HF_CLK 596
+#define IMX8QM_ESAI0_TX_CLK 597
+#define IMX8QM_ESAI0_TX_HF_CLK 598
+#define IMX8QM_ESAI1_RX_CLK 599
+#define IMX8QM_ESAI1_RX_HF_CLK 600
+#define IMX8QM_ESAI1_TX_CLK 601
+#define IMX8QM_ESAI1_TX_HF_CLK 602
+#define IMX8QM_SPDIF0_RX 603
+#define IMX8QM_SPDIF1_RX 604
+#define IMX8QM_SAI0_RX_BCLK 605
+#define IMX8QM_SAI0_TX_BCLK 606
+#define IMX8QM_SAI1_RX_BCLK 607
+#define IMX8QM_SAI1_TX_BCLK 608
+#define IMX8QM_SAI2_RX_BCLK 609
+#define IMX8QM_SAI3_RX_BCLK 610
+#define IMX8QM_HDMI_RX_SAI0_RX_BCLK 611
+#define IMX8QM_SAI6_RX_BCLK 612
+#define IMX8QM_HDMI_TX_SAI0_TX_BCLK 613
+
+#define IMX8QM_ACM_AUD_CLK0_SEL 614
+#define IMX8QM_ACM_AUD_CLK0_CLK 615
+#define IMX8QM_ACM_AUD_CLK1_SEL 616
+#define IMX8QM_ACM_AUD_CLK1_CLK 617
+#define IMX8QM_ACM_MCLKOUT0_SEL 618
+#define IMX8QM_ACM_MCLKOUT0_CLK 619
+#define IMX8QM_ACM_MCLKOUT1_SEL 620
+#define IMX8QM_ACM_MCLKOUT1_CLK 621
+#define IMX8QM_ACM_ASRC0_MUX_CLK_SEL 622
+#define IMX8QM_ACM_ASRC0_MUX_CLK_CLK 623
+#define IMX8QM_ACM_ASRC1_MUX_CLK_SEL 624
+#define IMX8QM_ACM_ASRC1_MUX_CLK_CLK 625
+#define IMX8QM_ACM_ESAI0_MCLK_SEL 626
+#define IMX8QM_ACM_ESAI0_MCLK_CLK 627
+#define IMX8QM_ACM_ESAI1_MCLK_SEL 628
+#define IMX8QM_ACM_ESAI1_MCLK_CLK 629
+#define IMX8QM_ACM_GPT0_MUX_CLK_SEL 630
+#define IMX8QM_ACM_GPT0_MUX_CLK_CLK 631
+#define IMX8QM_ACM_GPT1_MUX_CLK_SEL 632
+#define IMX8QM_ACM_GPT1_MUX_CLK_CLK 633
+#define IMX8QM_ACM_GPT2_MUX_CLK_SEL 634
+#define IMX8QM_ACM_GPT2_MUX_CLK_CLK 635
+#define IMX8QM_ACM_GPT3_MUX_CLK_SEL 636
+#define IMX8QM_ACM_GPT3_MUX_CLK_CLK 637
+#define IMX8QM_ACM_GPT4_MUX_CLK_SEL 638
+#define IMX8QM_ACM_GPT4_MUX_CLK_CLK 639
+#define IMX8QM_ACM_GPT5_MUX_CLK_SEL 640
+#define IMX8QM_ACM_GPT5_MUX_CLK_CLK 641
+#define IMX8QM_ACM_SAI0_MCLK_SEL 642
+#define IMX8QM_ACM_SAI0_MCLK_CLK 643
+#define IMX8QM_ACM_SAI1_MCLK_SEL 644
+#define IMX8QM_ACM_SAI1_MCLK_CLK 645
+#define IMX8QM_ACM_SAI2_MCLK_SEL 646
+#define IMX8QM_ACM_SAI2_MCLK_CLK 647
+#define IMX8QM_ACM_SAI3_MCLK_SEL 648
+#define IMX8QM_ACM_SAI3_MCLK_CLK 649
+#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL 650
+#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK 651
+#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL 652
+#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK 653
+#define IMX8QM_ACM_SAI6_MCLK_SEL 654
+#define IMX8QM_ACM_SAI6_MCLK_CLK 655
+#define IMX8QM_ACM_SAI7_MCLK_SEL 656
+#define IMX8QM_ACM_SAI7_MCLK_CLK 657
+#define IMX8QM_ACM_SPDIF0_TX_CLK_SEL 658
+#define IMX8QM_ACM_SPDIF0_TX_CLK_CLK 659
+#define IMX8QM_ACM_SPDIF1_TX_CLK_SEL 660
+#define IMX8QM_ACM_SPDIF1_TX_CLK_CLK 661
+#define IMX8QM_ACM_MQS_TX_CLK_SEL 662
+#define IMX8QM_ACM_MQS_TX_CLK_CLK 663
+
+#define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL 664
+#define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK 665
+#define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL 666
+#define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK 667
+#define IMX8QM_ENET0_REF_50MHZ_CLK 668
+#define IMX8QM_ENET1_REF_50MHZ_CLK 669
+#define IMX8QM_ENET_25MHZ_CLK 670
+#define IMX8QM_ENET_125MHZ_CLK 671
+#define IMX8QM_ENET0_REF_DIV 672
+#define IMX8QM_ENET0_REF_CLK 673
+#define IMX8QM_ENET1_REF_DIV 674
+#define IMX8QM_ENET1_REF_CLK 675
+#define IMX8QM_ENET0_RMII_TX_CLK 676
+#define IMX8QM_ENET1_RMII_TX_CLK 677
+#define IMX8QM_ENET0_RMII_TX_SEL 678
+#define IMX8QM_ENET1_RMII_TX_SEL 679
+#define IMX8QM_ENET0_RMII_RX_CLK 680
+#define IMX8QM_ENET1_RMII_RX_CLK 681
+
+#define IMX8QM_KPP_CLK 683
+#define IMX8QM_GPT0_HF_CLK 684
+#define IMX8QM_GPT0_IPG_S_CLK 685
+#define IMX8QM_GPT0_IPG_SLV_CLK 686
+#define IMX8QM_GPT0_IPG_MSTR_CLK 687
+#define IMX8QM_GPT1_HF_CLK 688
+#define IMX8QM_GPT1_IPG_S_CLK 689
+#define IMX8QM_GPT1_IPG_SLV_CLK 690
+#define IMX8QM_GPT1_IPG_MSTR_CLK 691
+#define IMX8QM_GPT2_HF_CLK 692
+#define IMX8QM_GPT2_IPG_S_CLK 693
+#define IMX8QM_GPT2_IPG_SLV_CLK 694
+#define IMX8QM_GPT2_IPG_MSTR_CLK 695
+#define IMX8QM_GPT3_HF_CLK 696
+#define IMX8QM_GPT3_IPG_S_CLK 697
+#define IMX8QM_GPT3_IPG_SLV_CLK 698
+#define IMX8QM_GPT3_IPG_MSTR_CLK 699
+#define IMX8QM_GPT4_HF_CLK 700
+#define IMX8QM_GPT4_IPG_S_CLK 701
+#define IMX8QM_GPT4_IPG_SLV_CLK 702
+#define IMX8QM_GPT4_IPG_MSTR_CLK 703
+#define IMX8QM_PWM0_HF_CLK 704
+#define IMX8QM_PWM0_IPG_S_CLK 705
+#define IMX8QM_PWM0_IPG_SLV_CLK 706
+#define IMX8QM_PWM0_IPG_MSTR_CLK 707
+#define IMX8QM_PWM1_HF_CLK 708
+#define IMX8QM_PWM1_IPG_S_CLK 709
+#define IMX8QM_PWM1_IPG_SLV_CLK 710
+#define IMX8QM_PWM1_IPG_MSTR_CLK 711
+#define IMX8QM_PWM2_HF_CLK 712
+#define IMX8QM_PWM2_IPG_S_CLK 713
+#define IMX8QM_PWM2_IPG_SLV_CLK 714
+#define IMX8QM_PWM2_IPG_MSTR_CLK 715
+#define IMX8QM_PWM3_HF_CLK 716
+#define IMX8QM_PWM3_IPG_S_CLK 717
+#define IMX8QM_PWM3_IPG_SLV_CLK 718
+#define IMX8QM_PWM3_IPG_MSTR_CLK 719
+#define IMX8QM_PWM4_HF_CLK 720
+#define IMX8QM_PWM4_IPG_S_CLK 721
+#define IMX8QM_PWM4_IPG_SLV_CLK 722
+#define IMX8QM_PWM4_IPG_MSTR_CLK 723
+#define IMX8QM_PWM5_HF_CLK 724
+#define IMX8QM_PWM5_IPG_S_CLK 725
+#define IMX8QM_PWM5_IPG_SLV_CLK 726
+#define IMX8QM_PWM5_IPG_MSTR_CLK 727
+#define IMX8QM_PWM6_HF_CLK 728
+#define IMX8QM_PWM6_IPG_S_CLK 729
+#define IMX8QM_PWM6_IPG_SLV_CLK 730
+#define IMX8QM_PWM6_IPG_MSTR_CLK 731
+#define IMX8QM_PWM7_HF_CLK 732
+#define IMX8QM_PWM7_IPG_S_CLK 733
+#define IMX8QM_PWM7_IPG_SLV_CLK 734
+#define IMX8QM_PWM7_IPG_MSTR_CLK 735
+#define IMX8QM_FSPI0_HCLK 736
+#define IMX8QM_FSPI0_IPG_CLK 737
+#define IMX8QM_FSPI0_IPG_S_CLK 738
+#define IMX8QM_FSPI1_HCLK 736
+#define IMX8QM_FSPI1_IPG_CLK 737
+#define IMX8QM_FSPI1_IPG_S_CLK 738
+#define IMX8QM_GPIO0_IPG_S_CLK 739
+#define IMX8QM_GPIO1_IPG_S_CLK 740
+#define IMX8QM_GPIO2_IPG_S_CLK 741
+#define IMX8QM_GPIO3_IPG_S_CLK 742
+#define IMX8QM_GPIO4_IPG_S_CLK 743
+#define IMX8QM_GPIO5_IPG_S_CLK 744
+#define IMX8QM_GPIO6_IPG_S_CLK 745
+#define IMX8QM_GPIO7_IPG_S_CLK 746
+#define IMX8QM_ROMCP_CLK 747
+#define IMX8QM_ROMCP_REG_CLK 748
+#define IMX8QM_96KROM_CLK 749
+#define IMX8QM_OCRAM_MEM_CLK 750
+#define IMX8QM_OCRAM_CTRL_CLK 751
+#define IMX8QM_LSIO_BUS_CLK 752
+#define IMX8QM_LSIO_MEM_CLK 753
+#define IMX8QM_LVDS0_LIS_IPG_CLK 754
+#define IMX8QM_LVDS1_LIS_IPG_CLK 755
+#define IMX8QM_MIPI0_LIS_IPG_CLK 756
+#define IMX8QM_MIPI0_I2C0_IPG_S_CLK 757
+#define IMX8QM_MIPI0_I2C0_IPG_CLK 758
+#define IMX8QM_MIPI0_I2C1_IPG_S_CLK 759
+#define IMX8QM_MIPI0_I2C1_IPG_CLK 760
+#define IMX8QM_MIPI0_CLK_ROOT 761
+#define IMX8QM_MIPI1_LIS_IPG_CLK 762
+#define IMX8QM_MIPI1_I2C0_IPG_S_CLK 763
+#define IMX8QM_MIPI1_I2C0_IPG_CLK 764
+#define IMX8QM_MIPI1_I2C1_IPG_S_CLK 765
+#define IMX8QM_MIPI1_I2C1_IPG_CLK 766
+#define IMX8QM_MIPI1_CLK_ROOT 767
+#define IMX8QM_DC0_DISP0_SEL 768
+#define IMX8QM_DC0_DISP1_SEL 769
+#define IMX8QM_DC1_DISP0_SEL 770
+#define IMX8QM_DC1_DISP1_SEL 771
+
+/* CM40 */
+#define IMX8QM_CM40_IPG_CLK 772
+#define IMX8QM_CM40_I2C_DIV 773
+#define IMX8QM_CM40_I2C_CLK 774
+#define IMX8QM_CM40_I2C_IPG_CLK 775
+
+/* CM41 */
+#define IMX8QM_CM41_IPG_CLK 776
+#define IMX8QM_CM41_I2C_DIV 777
+#define IMX8QM_CM41_I2C_CLK 778
+#define IMX8QM_CM41_I2C_IPG_CLK 779
+
+#define IMX8QM_HDMI_PXL_SEL 780
+#define IMX8QM_HDMI_PXL_LINK_SEL 781
+#define IMX8QM_HDMI_PXL_MUX_SEL 782
+#define IMX8QM_HDMI_AV_PLL_BYPASS_CLK 783
+
+#define IMX8QM_HDMI_RX_PXL_SEL 784
+#define IMX8QM_HDMI_RX_HD_REF_SEL 785
+#define IMX8QM_HDMI_RX_HD_CORE_SEL 786
+#define IMX8QM_HDMI_RX_DIG_PLL_CLK 787
+
+#define IMX8QM_LSIO_MU5A_IPG_S_CLK 788
+#define IMX8QM_LSIO_MU5A_IPG_CLK 789
+#define IMX8QM_LSIO_MU6A_IPG_S_CLK 790
+#define IMX8QM_LSIO_MU6A_IPG_CLK 791
+
+/* DSP */
+#define IMX8QM_AUD_DSP_ADB_ACLK 792
+#define IMX8QM_AUD_DSP_IPG 793
+#define IMX8QM_AUD_DSP_CORE_CLK 794
+#define IMX8QM_AUD_OCRAM_IPG 795
+
+#define IMX8QM_CLK_END 796
+
+#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
+#define __DT_BINDINGS_CLOCK_R7S72100_H__
+
+#define R7S72100_CLK_PLL 0
+#define R7S72100_CLK_I 1
+#define R7S72100_CLK_G 2
+
+/* MSTP2 */
+#define R7S72100_CLK_CORESIGHT 0
+
+/* MSTP3 */
+#define R7S72100_CLK_IEBUS 7
+#define R7S72100_CLK_IRDA 6
+#define R7S72100_CLK_LIN0 5
+#define R7S72100_CLK_LIN1 4
+#define R7S72100_CLK_MTU2 3
+#define R7S72100_CLK_CAN 2
+#define R7S72100_CLK_ADCPWR 1
+#define R7S72100_CLK_PWM 0
+
+/* MSTP4 */
+#define R7S72100_CLK_SCIF0 7
+#define R7S72100_CLK_SCIF1 6
+#define R7S72100_CLK_SCIF2 5
+#define R7S72100_CLK_SCIF3 4
+#define R7S72100_CLK_SCIF4 3
+#define R7S72100_CLK_SCIF5 2
+#define R7S72100_CLK_SCIF6 1
+#define R7S72100_CLK_SCIF7 0
+
+/* MSTP5 */
+#define R7S72100_CLK_SCI0 7
+#define R7S72100_CLK_SCI1 6
+#define R7S72100_CLK_SG0 5
+#define R7S72100_CLK_SG1 4
+#define R7S72100_CLK_SG2 3
+#define R7S72100_CLK_SG3 2
+#define R7S72100_CLK_OSTM0 1
+#define R7S72100_CLK_OSTM1 0
+
+/* MSTP6 */
+#define R7S72100_CLK_ADC 7
+#define R7S72100_CLK_CEU 6
+#define R7S72100_CLK_DOC0 5
+#define R7S72100_CLK_DOC1 4
+#define R7S72100_CLK_DRC0 3
+#define R7S72100_CLK_DRC1 2
+#define R7S72100_CLK_JCU 1
+#define R7S72100_CLK_RTC 0
+
+/* MSTP7 */
+#define R7S72100_CLK_VDEC0 7
+#define R7S72100_CLK_VDEC1 6
+#define R7S72100_CLK_ETHER 4
+#define R7S72100_CLK_NAND 3
+#define R7S72100_CLK_USB0 1
+#define R7S72100_CLK_USB1 0
+
+/* MSTP8 */
+#define R7S72100_CLK_IMR0 7
+#define R7S72100_CLK_IMR1 6
+#define R7S72100_CLK_IMRDISP 5
+#define R7S72100_CLK_MMCIF 4
+#define R7S72100_CLK_MLB 3
+#define R7S72100_CLK_ETHAVB 2
+#define R7S72100_CLK_SCUX 1
+
+/* MSTP9 */
+#define R7S72100_CLK_I2C0 7
+#define R7S72100_CLK_I2C1 6
+#define R7S72100_CLK_I2C2 5
+#define R7S72100_CLK_I2C3 4
+#define R7S72100_CLK_SPIBSC0 3
+#define R7S72100_CLK_SPIBSC1 2
+#define R7S72100_CLK_VDC50 1 /* and LVDS */
+#define R7S72100_CLK_VDC51 0
+
+/* MSTP10 */
+#define R7S72100_CLK_SPI0 7
+#define R7S72100_CLK_SPI1 6
+#define R7S72100_CLK_SPI2 5
+#define R7S72100_CLK_SPI3 4
+#define R7S72100_CLK_SPI4 3
+#define R7S72100_CLK_CDROM 2
+#define R7S72100_CLK_SPDIF 1
+#define R7S72100_CLK_RGPVG2 0
+
+/* MSTP11 */
+#define R7S72100_CLK_SSI0 5
+#define R7S72100_CLK_SSI1 4
+#define R7S72100_CLK_SSI2 3
+#define R7S72100_CLK_SSI3 2
+#define R7S72100_CLK_SSI4 1
+#define R7S72100_CLK_SSI5 0
+
+/* MSTP12 */
+#define R7S72100_CLK_SDHI00 3
+#define R7S72100_CLK_SDHI01 2
+#define R7S72100_CLK_SDHI10 1
+#define R7S72100_CLK_SDHI11 0
+
+/* MSTP13 */
+#define R7S72100_CLK_PIX1 2
+#define R7S72100_CLK_PIX0 1
+
+#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#ifndef _LUTON_DATA_H_
+#define _LUTON_DATA_H_
+
+#define SERDES6G(x) (x)
+#define SERDES6G_MAX SERDES6G(5)
+#define SERDES_MAX (SERDES6G_MAX)
+
+/* similar with phy_interface_t */
+#define PHY_MODE_SGMII 2
+#define PHY_MODE_QSGMII 4
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#ifndef _OCELOT_DATA_H_
+#define _OCELOT_DATA_H_
+
+#define SERDES1G(x) (x)
+#define SERDES1G_MAX SERDES1G(7)
+#define SERDES6G(x) (SERDES1G_MAX + 1 + (x))
+#define SERDES6G_MAX SERDES6G(11)
+#define SERDES_MAX (SERDES6G_MAX + 1)
+
+/* similar with phy_interface_t */
+#define PHY_MODE_SGMII 2
+#define PHY_MODE_QSGMII 4
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _SERVAL_DATA_H_
+#define _SERVAL_DATA_H_
+
+#define SERDES1G(x) (x)
+#define SERDES1G_MAX SERDES1G(9)
+#define SERDES6G(x) (SERDES1G_MAX + 1 + (x))
+#define SERDES6G_MAX SERDES6G(11)
+#define SERDES_MAX (SERDES6G_MAX + 1)
+
+/* similar with phy_interface_t */
+#define PHY_MODE_SGMII 2
+#define PHY_MODE_QSGMII 4
+
+#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for TI K3-AM65 pinctrl bindings.
- *
- * Copyright (C) 2018 Texas Instruments
- */
-#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
-#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
-
-/* K3 mux mode options for each pin. See TRM for options */
-#define MUX_MODE0 0
-#define MUX_MODE1 1
-#define MUX_MODE2 2
-#define MUX_MODE3 3
-#define MUX_MODE4 4
-#define MUX_MODE5 5
-#define MUX_MODE6 6
-#define MUX_MODE7 7
-#define MUX_MODE15 15
-
-#define PULL_DISABLE (1 << 16)
-#define PULL_UP (1 << 17)
-#define INPUT_EN (1 << 18)
-#define SLEWCTRL_200MHZ 0
-#define SLEWCTRL_150MHZ (1 << 19)
-#define SLEWCTRL_100MHZ (2 << 19)
-#define SLEWCTRL_50MHZ (3 << 19)
-#define TX_DIS (1 << 21)
-#define ISO_OVR (1 << 22)
-#define ISO_BYPASS (1 << 23)
-#define DS_EN (1 << 24)
-#define DS_INPUT (1 << 25)
-#define DS_FORCE_OUT_HIGH (1 << 26)
-#define DS_PULL_UP_DOWN_EN 0
-#define DS_PULL_UP_DOWN_DIS (1 << 27)
-#define DS_PULL_UP_SEL (1 << 28)
-#define WAKEUP_ENABLE (1 << 29)
-
-#define PIN_OUTPUT (PULL_DISABLE)
-#define PIN_OUTPUT_PULLUP (PULL_UP)
-#define PIN_OUTPUT_PULLDOWN 0
-#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
-#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (INPUT_EN)
-
-#define AM65X_IOPAD(pa, val) (((pa) & 0x1fff)) (val)
-#define AM65X_WKUP_IOPAD(pa, val) (((pa) & 0x1fff)) (val)
-
-#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for TI K3-AM65 pinctrl bindings.
+ *
+ * Copyright (C) 2018 Texas Instruments
+ */
+#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
+#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
+
+#define PULL_DISABLE (1 << 16)
+#define PULL_UP (1 << 17)
+#define INPUT_EN (1 << 18)
+#define SLEWCTRL_200MHZ 0
+#define SLEWCTRL_150MHZ (1 << 19)
+#define SLEWCTRL_100MHZ (2 << 19)
+#define SLEWCTRL_50MHZ (3 << 19)
+#define TX_DIS (1 << 21)
+#define ISO_OVR (1 << 22)
+#define ISO_BYPASS (1 << 23)
+#define DS_EN (1 << 24)
+#define DS_INPUT (1 << 25)
+#define DS_FORCE_OUT_HIGH (1 << 26)
+#define DS_PULL_UP_DOWN_EN 0
+#define DS_PULL_UP_DOWN_DIS (1 << 27)
+#define DS_PULL_UP_SEL (1 << 28)
+#define WAKEUP_ENABLE (1 << 29)
+
+#define PIN_OUTPUT (PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP (PULL_UP)
+#define PIN_OUTPUT_PULLDOWN 0
+#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN (INPUT_EN)
+
+#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef SC_PADS_H
+#define SC_PADS_H
+
+#define SC_P_SIM0_CLK 0 /* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
+#define SC_P_SIM0_RST 1 /* DMA.SIM0.RST, LSIO.GPIO0.IO01 */
+#define SC_P_SIM0_IO 2 /* DMA.SIM0.IO, LSIO.GPIO0.IO02 */
+#define SC_P_SIM0_PD 3 /* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
+#define SC_P_SIM0_POWER_EN 4 /* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
+#define SC_P_SIM0_GPIO0_00 5 /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /* */
+#define SC_P_M40_I2C0_SCL 7 /* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
+#define SC_P_M40_I2C0_SDA 8 /* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
+#define SC_P_M40_GPIO0_00 9 /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
+#define SC_P_M40_GPIO0_01 10 /* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
+#define SC_P_M41_I2C0_SCL 11 /* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
+#define SC_P_M41_I2C0_SDA 12 /* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
+#define SC_P_M41_GPIO0_00 13 /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
+#define SC_P_M41_GPIO0_01 14 /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
+#define SC_P_GPT0_CLK 15 /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
+#define SC_P_GPT0_CAPTURE 16 /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
+#define SC_P_GPT0_COMPARE 17 /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
+#define SC_P_GPT1_CLK 18 /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
+#define SC_P_GPT1_CAPTURE 19 /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
+#define SC_P_GPT1_COMPARE 20 /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
+#define SC_P_UART0_RX 21 /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
+#define SC_P_UART0_TX 22 /* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
+#define SC_P_UART0_RTS_B 23 /* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
+#define SC_P_UART0_CTS_B 24 /* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
+#define SC_P_UART1_TX 25 /* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
+#define SC_P_UART1_RX 26 /* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
+#define SC_P_UART1_RTS_B 27 /* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
+#define SC_P_UART1_CTS_B 28 /* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /* */
+#define SC_P_SCU_PMIC_MEMC_ON 30 /* SCU.GPIO0.IOXX_PMIC_MEMC_ON */
+#define SC_P_SCU_WDOG_OUT 31 /* SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SDA 32 /* SCU.PMIC_I2C.SDA */
+#define SC_P_PMIC_I2C_SCL 33 /* SCU.PMIC_I2C.SCL */
+#define SC_P_PMIC_EARLY_WARNING 34 /* SCU.PMIC_EARLY_WARNING */
+#define SC_P_PMIC_INT_B 35 /* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00 36 /* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
+#define SC_P_SCU_GPIO0_01 37 /* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
+#define SC_P_SCU_GPIO0_02 38 /* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
+#define SC_P_SCU_GPIO0_03 39 /* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
+#define SC_P_SCU_GPIO0_04 40 /* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
+#define SC_P_SCU_GPIO0_05 41 /* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
+#define SC_P_SCU_GPIO0_06 42 /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
+#define SC_P_SCU_GPIO0_07 43 /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
+#define SC_P_SCU_BOOT_MODE0 44 /* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1 45 /* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2 46 /* SCU.DSC.BOOT_MODE2 */
+#define SC_P_SCU_BOOT_MODE3 47 /* SCU.DSC.BOOT_MODE3 */
+#define SC_P_SCU_BOOT_MODE4 48 /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
+#define SC_P_SCU_BOOT_MODE5 49 /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
+#define SC_P_LVDS0_GPIO00 50 /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
+#define SC_P_LVDS0_GPIO01 51 /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
+#define SC_P_LVDS0_I2C0_SCL 52 /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
+#define SC_P_LVDS0_I2C0_SDA 53 /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
+#define SC_P_LVDS0_I2C1_SCL 54 /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
+#define SC_P_LVDS0_I2C1_SDA 55 /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
+#define SC_P_LVDS1_GPIO00 56 /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
+#define SC_P_LVDS1_GPIO01 57 /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
+#define SC_P_LVDS1_I2C0_SCL 58 /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
+#define SC_P_LVDS1_I2C0_SDA 59 /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
+#define SC_P_LVDS1_I2C1_SCL 60 /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
+#define SC_P_LVDS1_I2C1_SDA 61 /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /* */
+#define SC_P_MIPI_DSI0_I2C0_SCL 63 /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
+#define SC_P_MIPI_DSI0_I2C0_SDA 64 /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
+#define SC_P_MIPI_DSI0_GPIO0_00 65 /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
+#define SC_P_MIPI_DSI0_GPIO0_01 66 /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
+#define SC_P_MIPI_DSI1_I2C0_SCL 67 /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
+#define SC_P_MIPI_DSI1_I2C0_SDA 68 /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
+#define SC_P_MIPI_DSI1_GPIO0_00 69 /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
+#define SC_P_MIPI_DSI1_GPIO0_01 70 /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /* */
+#define SC_P_MIPI_CSI0_MCLK_OUT 72 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
+#define SC_P_MIPI_CSI0_I2C0_SCL 73 /* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_CSI0_I2C0_SDA 74 /* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_CSI0_GPIO0_00 75 /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_CSI0_GPIO0_01 76 /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_CSI1_MCLK_OUT 77 /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_CSI1_GPIO0_00 78 /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_CSI1_GPIO0_01 79 /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_CSI1_I2C0_SCL 80 /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
+#define SC_P_MIPI_CSI1_I2C0_SDA 81 /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
+#define SC_P_HDMI_TX0_TS_SCL 82 /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
+#define SC_P_HDMI_TX0_TS_SDA 83 /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
+#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /* */
+#define SC_P_ESAI1_FSR 85 /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
+#define SC_P_ESAI1_FST 86 /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
+#define SC_P_ESAI1_SCKR 87 /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
+#define SC_P_ESAI1_SCKT 88 /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
+#define SC_P_ESAI1_TX0 89 /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
+#define SC_P_ESAI1_TX1 90 /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
+#define SC_P_ESAI1_TX2_RX3 91 /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
+#define SC_P_ESAI1_TX3_RX2 92 /* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
+#define SC_P_ESAI1_TX4_RX1 93 /* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
+#define SC_P_ESAI1_TX5_RX0 94 /* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
+#define SC_P_SPDIF0_RX 95 /* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
+#define SC_P_SPDIF0_TX 96 /* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
+#define SC_P_SPDIF0_EXT_CLK 97 /* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
+#define SC_P_SPI3_SCK 98 /* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
+#define SC_P_SPI3_SDO 99 /* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
+#define SC_P_SPI3_SDI 100 /* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
+#define SC_P_SPI3_CS0 101 /* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
+#define SC_P_SPI3_CS1 102 /* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /* */
+#define SC_P_ESAI0_FSR 104 /* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
+#define SC_P_ESAI0_FST 105 /* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
+#define SC_P_ESAI0_SCKR 106 /* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
+#define SC_P_ESAI0_SCKT 107 /* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
+#define SC_P_ESAI0_TX0 108 /* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
+#define SC_P_ESAI0_TX1 109 /* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
+#define SC_P_ESAI0_TX2_RX3 110 /* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
+#define SC_P_ESAI0_TX3_RX2 111 /* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
+#define SC_P_ESAI0_TX4_RX1 112 /* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
+#define SC_P_ESAI0_TX5_RX0 113 /* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
+#define SC_P_MCLK_IN0 114 /* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
+#define SC_P_MCLK_OUT0 115 /* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /* */
+#define SC_P_SPI0_SCK 117 /* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
+#define SC_P_SPI0_SDO 118 /* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
+#define SC_P_SPI0_SDI 119 /* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
+#define SC_P_SPI0_CS0 120 /* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
+#define SC_P_SPI0_CS1 121 /* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
+#define SC_P_SPI2_SCK 122 /* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
+#define SC_P_SPI2_SDO 123 /* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
+#define SC_P_SPI2_SDI 124 /* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
+#define SC_P_SPI2_CS0 125 /* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
+#define SC_P_SPI2_CS1 126 /* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
+#define SC_P_SAI1_RXC 127 /* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
+#define SC_P_SAI1_RXD 128 /* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
+#define SC_P_SAI1_RXFS 129 /* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
+#define SC_P_SAI1_TXC 130 /* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
+#define SC_P_SAI1_TXD 131 /* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
+#define SC_P_SAI1_TXFS 132 /* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /* */
+#define SC_P_ADC_IN7 134 /* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
+#define SC_P_ADC_IN6 135 /* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
+#define SC_P_ADC_IN5 136 /* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
+#define SC_P_ADC_IN4 137 /* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
+#define SC_P_ADC_IN3 138 /* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
+#define SC_P_ADC_IN2 139 /* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
+#define SC_P_ADC_IN1 140 /* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
+#define SC_P_ADC_IN0 141 /* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
+#define SC_P_MLB_SIG 142 /* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
+#define SC_P_MLB_CLK 143 /* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
+#define SC_P_MLB_DATA 144 /* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /* */
+#define SC_P_FLEXCAN0_RX 146 /* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
+#define SC_P_FLEXCAN0_TX 147 /* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
+#define SC_P_FLEXCAN1_RX 148 /* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
+#define SC_P_FLEXCAN1_TX 149 /* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
+#define SC_P_FLEXCAN2_RX 150 /* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
+#define SC_P_FLEXCAN2_TX 151 /* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /* */
+#define SC_P_USB_SS3_TC0 153 /* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1 154 /* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2 155 /* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3 156 /* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /* */
+#define SC_P_USDHC1_RESET_B 158 /* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
+#define SC_P_USDHC1_VSELECT 159 /* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
+#define SC_P_USDHC2_RESET_B 160 /* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
+#define SC_P_USDHC2_VSELECT 161 /* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
+#define SC_P_USDHC2_WP 162 /* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
+#define SC_P_USDHC2_CD_B 163 /* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /* */
+#define SC_P_ENET0_MDIO 165 /* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
+#define SC_P_ENET0_MDC 166 /* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
+#define SC_P_ENET0_REFCLK_125M_25M 167 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
+#define SC_P_ENET1_REFCLK_125M_25M 168 /* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
+#define SC_P_ENET1_MDIO 169 /* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
+#define SC_P_ENET1_MDC 170 /* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /* */
+#define SC_P_QSPI1A_SS0_B 172 /* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
+#define SC_P_QSPI1A_SS1_B 173 /* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
+#define SC_P_QSPI1A_SCLK 174 /* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
+#define SC_P_QSPI1A_DQS 175 /* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_QSPI1A_DATA3 176 /* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
+#define SC_P_QSPI1A_DATA2 177 /* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
+#define SC_P_QSPI1A_DATA1 178 /* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
+#define SC_P_QSPI1A_DATA0 179 /* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /* */
+#define SC_P_QSPI0A_DATA0 181 /* LSIO.QSPI0A.DATA0 */
+#define SC_P_QSPI0A_DATA1 182 /* LSIO.QSPI0A.DATA1 */
+#define SC_P_QSPI0A_DATA2 183 /* LSIO.QSPI0A.DATA2 */
+#define SC_P_QSPI0A_DATA3 184 /* LSIO.QSPI0A.DATA3 */
+#define SC_P_QSPI0A_DQS 185 /* LSIO.QSPI0A.DQS */
+#define SC_P_QSPI0A_SS0_B 186 /* LSIO.QSPI0A.SS0_B */
+#define SC_P_QSPI0A_SS1_B 187 /* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
+#define SC_P_QSPI0A_SCLK 188 /* LSIO.QSPI0A.SCLK */
+#define SC_P_QSPI0B_SCLK 189 /* LSIO.QSPI0B.SCLK */
+#define SC_P_QSPI0B_DATA0 190 /* LSIO.QSPI0B.DATA0 */
+#define SC_P_QSPI0B_DATA1 191 /* LSIO.QSPI0B.DATA1 */
+#define SC_P_QSPI0B_DATA2 192 /* LSIO.QSPI0B.DATA2 */
+#define SC_P_QSPI0B_DATA3 193 /* LSIO.QSPI0B.DATA3 */
+#define SC_P_QSPI0B_DQS 194 /* LSIO.QSPI0B.DQS */
+#define SC_P_QSPI0B_SS0_B 195 /* LSIO.QSPI0B.SS0_B */
+#define SC_P_QSPI0B_SS1_B 196 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /* */
+#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
+#define SC_P_PCIE_CTRL0_WAKE_B 199 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
+#define SC_P_PCIE_CTRL0_PERST_B 200 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
+#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
+#define SC_P_PCIE_CTRL1_WAKE_B 202 /* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
+#define SC_P_PCIE_CTRL1_PERST_B 203 /* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /* */
+#define SC_P_USB_HSIC0_DATA 205 /* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
+#define SC_P_USB_HSIC0_STROBE 206 /* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
+#define SC_P_CALIBRATION_0_HSIC 207 /* */
+#define SC_P_CALIBRATION_1_HSIC 208 /* */
+#define SC_P_EMMC0_CLK 209 /* CONN.EMMC0.CLK, CONN.NAND.READY_B */
+#define SC_P_EMMC0_CMD 210 /* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
+#define SC_P_EMMC0_DATA0 211 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
+#define SC_P_EMMC0_DATA1 212 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
+#define SC_P_EMMC0_DATA2 213 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
+#define SC_P_EMMC0_DATA3 214 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
+#define SC_P_EMMC0_DATA4 215 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
+#define SC_P_EMMC0_DATA5 216 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
+#define SC_P_EMMC0_DATA6 217 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
+#define SC_P_EMMC0_DATA7 218 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
+#define SC_P_EMMC0_STROBE 219 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
+#define SC_P_EMMC0_RESET_B 220 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /* */
+#define SC_P_USDHC1_CLK 222 /* CONN.USDHC1.CLK, AUD.MQS.R */
+#define SC_P_USDHC1_CMD 223 /* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
+#define SC_P_USDHC1_DATA0 224 /* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
+#define SC_P_USDHC1_DATA1 225 /* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
+#define SC_P_CTL_NAND_RE_P_N 226 /* */
+#define SC_P_USDHC1_DATA2 227 /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
+#define SC_P_USDHC1_DATA3 228 /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
+#define SC_P_CTL_NAND_DQS_P_N 229 /* */
+#define SC_P_USDHC1_DATA4 230 /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
+#define SC_P_USDHC1_DATA5 231 /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
+#define SC_P_USDHC1_DATA6 232 /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
+#define SC_P_USDHC1_DATA7 233 /* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
+#define SC_P_USDHC1_STROBE 234 /* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /* */
+#define SC_P_USDHC2_CLK 236 /* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
+#define SC_P_USDHC2_CMD 237 /* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
+#define SC_P_USDHC2_DATA0 238 /* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
+#define SC_P_USDHC2_DATA1 239 /* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
+#define SC_P_USDHC2_DATA2 240 /* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
+#define SC_P_USDHC2_DATA3 241 /* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /* */
+#define SC_P_ENET0_RGMII_TXC 243 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
+#define SC_P_ENET0_RGMII_TX_CTL 244 /* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
+#define SC_P_ENET0_RGMII_TXD0 245 /* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
+#define SC_P_ENET0_RGMII_TXD1 246 /* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
+#define SC_P_ENET0_RGMII_TXD2 247 /* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
+#define SC_P_ENET0_RGMII_TXD3 248 /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
+#define SC_P_ENET0_RGMII_RXC 249 /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
+#define SC_P_ENET0_RGMII_RX_CTL 250 /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
+#define SC_P_ENET0_RGMII_RXD0 251 /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
+#define SC_P_ENET0_RGMII_RXD1 252 /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
+#define SC_P_ENET0_RGMII_RXD2 253 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
+#define SC_P_ENET0_RGMII_RXD3 254 /* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /* */
+#define SC_P_ENET1_RGMII_TXC 256 /* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
+#define SC_P_ENET1_RGMII_TX_CTL 257 /* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
+#define SC_P_ENET1_RGMII_TXD0 258 /* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
+#define SC_P_ENET1_RGMII_TXD1 259 /* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
+#define SC_P_ENET1_RGMII_TXD2 260 /* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
+#define SC_P_ENET1_RGMII_TXD3 261 /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
+#define SC_P_ENET1_RGMII_RXC 262 /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
+#define SC_P_ENET1_RGMII_RX_CTL 263 /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
+#define SC_P_ENET1_RGMII_RXD0 264 /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
+#define SC_P_ENET1_RGMII_RXD1 265 /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
+#define SC_P_ENET1_RGMII_RXD2 266 /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
+#define SC_P_ENET1_RGMII_RXD3 267 /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /* */
+/*@}*/
+
+/*!
+ * @name Pad Mux Definitions
+ * format: name padid padmux
+ */
+/*@{*/
+#define SC_P_SIM0_CLK_DMA_SIM0_CLK SC_P_SIM0_CLK 0
+#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 SC_P_SIM0_CLK 3
+#define SC_P_SIM0_RST_DMA_SIM0_RST SC_P_SIM0_RST 0
+#define SC_P_SIM0_RST_LSIO_GPIO0_IO01 SC_P_SIM0_RST 3
+#define SC_P_SIM0_IO_DMA_SIM0_IO SC_P_SIM0_IO 0
+#define SC_P_SIM0_IO_LSIO_GPIO0_IO02 SC_P_SIM0_IO 3
+#define SC_P_SIM0_PD_DMA_SIM0_PD SC_P_SIM0_PD 0
+#define SC_P_SIM0_PD_DMA_I2C3_SCL SC_P_SIM0_PD 1
+#define SC_P_SIM0_PD_LSIO_GPIO0_IO03 SC_P_SIM0_PD 3
+#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN SC_P_SIM0_POWER_EN 0
+#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA SC_P_SIM0_POWER_EN 1
+#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04 SC_P_SIM0_POWER_EN 3
+#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN SC_P_SIM0_GPIO0_00 0
+#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 SC_P_SIM0_GPIO0_00 3
+#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL SC_P_M40_I2C0_SCL 0
+#define SC_P_M40_I2C0_SCL_M40_UART0_RX SC_P_M40_I2C0_SCL 1
+#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02 SC_P_M40_I2C0_SCL 2
+#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 SC_P_M40_I2C0_SCL 3
+#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA SC_P_M40_I2C0_SDA 0
+#define SC_P_M40_I2C0_SDA_M40_UART0_TX SC_P_M40_I2C0_SDA 1
+#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03 SC_P_M40_I2C0_SDA 2
+#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 SC_P_M40_I2C0_SDA 3
+#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00 SC_P_M40_GPIO0_00 0
+#define SC_P_M40_GPIO0_00_M40_TPM0_CH0 SC_P_M40_GPIO0_00 1
+#define SC_P_M40_GPIO0_00_DMA_UART4_RX SC_P_M40_GPIO0_00 2
+#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 SC_P_M40_GPIO0_00 3
+#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01 SC_P_M40_GPIO0_01 0
+#define SC_P_M40_GPIO0_01_M40_TPM0_CH1 SC_P_M40_GPIO0_01 1
+#define SC_P_M40_GPIO0_01_DMA_UART4_TX SC_P_M40_GPIO0_01 2
+#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 SC_P_M40_GPIO0_01 3
+#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL SC_P_M41_I2C0_SCL 0
+#define SC_P_M41_I2C0_SCL_M41_UART0_RX SC_P_M41_I2C0_SCL 1
+#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02 SC_P_M41_I2C0_SCL 2
+#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 SC_P_M41_I2C0_SCL 3
+#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA SC_P_M41_I2C0_SDA 0
+#define SC_P_M41_I2C0_SDA_M41_UART0_TX SC_P_M41_I2C0_SDA 1
+#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03 SC_P_M41_I2C0_SDA 2
+#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 SC_P_M41_I2C0_SDA 3
+#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00 SC_P_M41_GPIO0_00 0
+#define SC_P_M41_GPIO0_00_M41_TPM0_CH0 SC_P_M41_GPIO0_00 1
+#define SC_P_M41_GPIO0_00_DMA_UART3_RX SC_P_M41_GPIO0_00 2
+#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 SC_P_M41_GPIO0_00 3
+#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01 SC_P_M41_GPIO0_01 0
+#define SC_P_M41_GPIO0_01_M41_TPM0_CH1 SC_P_M41_GPIO0_01 1
+#define SC_P_M41_GPIO0_01_DMA_UART3_TX SC_P_M41_GPIO0_01 2
+#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 SC_P_M41_GPIO0_01 3
+#define SC_P_GPT0_CLK_LSIO_GPT0_CLK SC_P_GPT0_CLK 0
+#define SC_P_GPT0_CLK_DMA_I2C1_SCL SC_P_GPT0_CLK 1
+#define SC_P_GPT0_CLK_LSIO_KPP0_COL4 SC_P_GPT0_CLK 2
+#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14 SC_P_GPT0_CLK 3
+#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE SC_P_GPT0_CAPTURE 0
+#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA SC_P_GPT0_CAPTURE 1
+#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5 SC_P_GPT0_CAPTURE 2
+#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15 SC_P_GPT0_CAPTURE 3
+#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE SC_P_GPT0_COMPARE 0
+#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT SC_P_GPT0_COMPARE 1
+#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6 SC_P_GPT0_COMPARE 2
+#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 SC_P_GPT0_COMPARE 3
+#define SC_P_GPT1_CLK_LSIO_GPT1_CLK SC_P_GPT1_CLK 0
+#define SC_P_GPT1_CLK_DMA_I2C2_SCL SC_P_GPT1_CLK 1
+#define SC_P_GPT1_CLK_LSIO_KPP0_COL7 SC_P_GPT1_CLK 2
+#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17 SC_P_GPT1_CLK 3
+#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE SC_P_GPT1_CAPTURE 0
+#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA SC_P_GPT1_CAPTURE 1
+#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4 SC_P_GPT1_CAPTURE 2
+#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18 SC_P_GPT1_CAPTURE 3
+#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE SC_P_GPT1_COMPARE 0
+#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT SC_P_GPT1_COMPARE 1
+#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5 SC_P_GPT1_COMPARE 2
+#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 SC_P_GPT1_COMPARE 3
+#define SC_P_UART0_RX_DMA_UART0_RX SC_P_UART0_RX 0
+#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 1
+#define SC_P_UART0_RX_LSIO_GPIO0_IO20 SC_P_UART0_RX 3
+#define SC_P_UART0_TX_DMA_UART0_TX SC_P_UART0_TX 0
+#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 1
+#define SC_P_UART0_TX_LSIO_GPIO0_IO21 SC_P_UART0_TX 3
+#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B SC_P_UART0_RTS_B 0
+#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT SC_P_UART0_RTS_B 1
+#define SC_P_UART0_RTS_B_DMA_UART2_RX SC_P_UART0_RTS_B 2
+#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 SC_P_UART0_RTS_B 3
+#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B SC_P_UART0_CTS_B 0
+#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT SC_P_UART0_CTS_B 1
+#define SC_P_UART0_CTS_B_DMA_UART2_TX SC_P_UART0_CTS_B 2
+#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 SC_P_UART0_CTS_B 3
+#define SC_P_UART1_TX_DMA_UART1_TX SC_P_UART1_TX 0
+#define SC_P_UART1_TX_DMA_SPI3_SCK SC_P_UART1_TX 1
+#define SC_P_UART1_TX_LSIO_GPIO0_IO24 SC_P_UART1_TX 3
+#define SC_P_UART1_RX_DMA_UART1_RX SC_P_UART1_RX 0
+#define SC_P_UART1_RX_DMA_SPI3_SDO SC_P_UART1_RX 1
+#define SC_P_UART1_RX_LSIO_GPIO0_IO25 SC_P_UART1_RX 3
+#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B SC_P_UART1_RTS_B 0
+#define SC_P_UART1_RTS_B_DMA_SPI3_SDI SC_P_UART1_RTS_B 1
+#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B SC_P_UART1_RTS_B 2
+#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26 SC_P_UART1_RTS_B 3
+#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B SC_P_UART1_CTS_B 0
+#define SC_P_UART1_CTS_B_DMA_SPI3_CS0 SC_P_UART1_CTS_B 1
+#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B SC_P_UART1_CTS_B 2
+#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27 SC_P_UART1_CTS_B 3
+#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON SC_P_SCU_PMIC_MEMC_ON 0
+#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT SC_P_SCU_WDOG_OUT 0
+#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
+#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
+#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING SC_P_PMIC_EARLY_WARNING 0
+#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
+#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
+#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
+#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28 SC_P_SCU_GPIO0_00 3
+#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
+#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
+#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29 SC_P_SCU_GPIO0_01 3
+#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02 SC_P_SCU_GPIO0_02 0
+#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON SC_P_SCU_GPIO0_02 1
+#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 SC_P_SCU_GPIO0_02 3
+#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03 SC_P_SCU_GPIO0_03 0
+#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON SC_P_SCU_GPIO0_03 1
+#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 SC_P_SCU_GPIO0_03 3
+#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04 SC_P_SCU_GPIO0_04 0
+#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON SC_P_SCU_GPIO0_04 1
+#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00 SC_P_SCU_GPIO0_04 3
+#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05 SC_P_SCU_GPIO0_05 0
+#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON SC_P_SCU_GPIO0_05 1
+#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 SC_P_SCU_GPIO0_05 3
+#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06 SC_P_SCU_GPIO0_06 0
+#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0 SC_P_SCU_GPIO0_06 1
+#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 SC_P_SCU_GPIO0_06 3
+#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07 SC_P_SCU_GPIO0_07 0
+#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1 SC_P_SCU_GPIO0_07 1
+#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_GPIO0_07 2
+#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03 SC_P_SCU_GPIO0_07 3
+#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
+#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
+#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 SC_P_SCU_BOOT_MODE4 0
+#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE4 1
+#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 SC_P_SCU_BOOT_MODE5 0
+#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE5 1
+#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00 SC_P_LVDS0_GPIO00 0
+#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT SC_P_LVDS0_GPIO00 1
+#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 SC_P_LVDS0_GPIO00 3
+#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01 SC_P_LVDS0_GPIO01 0
+#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 SC_P_LVDS0_GPIO01 3
+#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL SC_P_LVDS0_I2C0_SCL 0
+#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 SC_P_LVDS0_I2C0_SCL 1
+#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 SC_P_LVDS0_I2C0_SCL 3
+#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA SC_P_LVDS0_I2C0_SDA 0
+#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 SC_P_LVDS0_I2C0_SDA 1
+#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 SC_P_LVDS0_I2C0_SDA 3
+#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL SC_P_LVDS0_I2C1_SCL 0
+#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX SC_P_LVDS0_I2C1_SCL 1
+#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 SC_P_LVDS0_I2C1_SCL 3
+#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA SC_P_LVDS0_I2C1_SDA 0
+#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX SC_P_LVDS0_I2C1_SDA 1
+#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 SC_P_LVDS0_I2C1_SDA 3
+#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 SC_P_LVDS1_GPIO00 0
+#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT SC_P_LVDS1_GPIO00 1
+#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10 SC_P_LVDS1_GPIO00 3
+#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01 SC_P_LVDS1_GPIO01 0
+#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 SC_P_LVDS1_GPIO01 3
+#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL SC_P_LVDS1_I2C0_SCL 0
+#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 SC_P_LVDS1_I2C0_SCL 1
+#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 SC_P_LVDS1_I2C0_SCL 3
+#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA SC_P_LVDS1_I2C0_SDA 0
+#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 SC_P_LVDS1_I2C0_SDA 1
+#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 SC_P_LVDS1_I2C0_SDA 3
+#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL SC_P_LVDS1_I2C1_SCL 0
+#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX SC_P_LVDS1_I2C1_SCL 1
+#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 SC_P_LVDS1_I2C1_SCL 3
+#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA SC_P_LVDS1_I2C1_SDA 0
+#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX SC_P_LVDS1_I2C1_SDA 1
+#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 SC_P_LVDS1_I2C1_SDA 3
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
+#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 SC_P_MIPI_DSI0_I2C0_SCL 3
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
+#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 SC_P_MIPI_DSI0_I2C0_SDA 3
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 1
+#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 SC_P_MIPI_DSI0_GPIO0_00 3
+#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
+#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 SC_P_MIPI_DSI0_GPIO0_01 3
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
+#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 SC_P_MIPI_DSI1_I2C0_SCL 3
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
+#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 SC_P_MIPI_DSI1_I2C0_SDA 3
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 1
+#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 SC_P_MIPI_DSI1_GPIO0_00 3
+#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
+#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 SC_P_MIPI_DSI1_GPIO0_01 3
+#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
+#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 SC_P_MIPI_CSI0_MCLK_OUT 3
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
+#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_CSI0_I2C0_SCL 3
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
+#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_CSI0_I2C0_SDA 3
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
+#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 2
+#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_CSI0_GPIO0_00 3
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
+#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 2
+#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_CSI0_GPIO0_01 3
+#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT SC_P_MIPI_CSI1_MCLK_OUT 0
+#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 SC_P_MIPI_CSI1_MCLK_OUT 3
+#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 SC_P_MIPI_CSI1_GPIO0_00 0
+#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX SC_P_MIPI_CSI1_GPIO0_00 1
+#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 SC_P_MIPI_CSI1_GPIO0_00 3
+#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 SC_P_MIPI_CSI1_GPIO0_01 0
+#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX SC_P_MIPI_CSI1_GPIO0_01 1
+#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 SC_P_MIPI_CSI1_GPIO0_01 3
+#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI1_I2C0_SCL 0
+#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 SC_P_MIPI_CSI1_I2C0_SCL 3
+#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI1_I2C0_SDA 0
+#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 SC_P_MIPI_CSI1_I2C0_SDA 3
+#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 0
+#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 1
+#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 SC_P_HDMI_TX0_TS_SCL 3
+#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 0
+#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 1
+#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 SC_P_HDMI_TX0_TS_SDA 3
+#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR SC_P_ESAI1_FSR 0
+#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 SC_P_ESAI1_FSR 3
+#define SC_P_ESAI1_FST_AUD_ESAI1_FST SC_P_ESAI1_FST 0
+#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_FST 1
+#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05 SC_P_ESAI1_FST 3
+#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR SC_P_ESAI1_SCKR 0
+#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06 SC_P_ESAI1_SCKR 3
+#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT SC_P_ESAI1_SCKT 0
+#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC SC_P_ESAI1_SCKT 1
+#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_SCKT 2
+#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 SC_P_ESAI1_SCKT 3
+#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0 SC_P_ESAI1_TX0 0
+#define SC_P_ESAI1_TX0_AUD_SAI2_RXD SC_P_ESAI1_TX0 1
+#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX SC_P_ESAI1_TX0 2
+#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 SC_P_ESAI1_TX0 3
+#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1 SC_P_ESAI1_TX1 0
+#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS SC_P_ESAI1_TX1 1
+#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX SC_P_ESAI1_TX1 2
+#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 SC_P_ESAI1_TX1 3
+#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 SC_P_ESAI1_TX2_RX3 0
+#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX SC_P_ESAI1_TX2_RX3 1
+#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 SC_P_ESAI1_TX2_RX3 3
+#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 SC_P_ESAI1_TX3_RX2 0
+#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX SC_P_ESAI1_TX3_RX2 1
+#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 SC_P_ESAI1_TX3_RX2 3
+#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 SC_P_ESAI1_TX4_RX1 0
+#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 SC_P_ESAI1_TX4_RX1 3
+#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 SC_P_ESAI1_TX5_RX0 0
+#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 SC_P_ESAI1_TX5_RX0 3
+#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX SC_P_SPDIF0_RX 0
+#define SC_P_SPDIF0_RX_AUD_MQS_R SC_P_SPDIF0_RX 1
+#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1 SC_P_SPDIF0_RX 2
+#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14 SC_P_SPDIF0_RX 3
+#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX SC_P_SPDIF0_TX 0
+#define SC_P_SPDIF0_TX_AUD_MQS_L SC_P_SPDIF0_TX 1
+#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1 SC_P_SPDIF0_TX 2
+#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 SC_P_SPDIF0_TX 3
+#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
+#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 SC_P_SPDIF0_EXT_CLK 1
+#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 SC_P_SPDIF0_EXT_CLK 3
+#define SC_P_SPI3_SCK_DMA_SPI3_SCK SC_P_SPI3_SCK 0
+#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17 SC_P_SPI3_SCK 3
+#define SC_P_SPI3_SDO_DMA_SPI3_SDO SC_P_SPI3_SDO 0
+#define SC_P_SPI3_SDO_DMA_FTM_CH0 SC_P_SPI3_SDO 1
+#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18 SC_P_SPI3_SDO 3
+#define SC_P_SPI3_SDI_DMA_SPI3_SDI SC_P_SPI3_SDI 0
+#define SC_P_SPI3_SDI_DMA_FTM_CH1 SC_P_SPI3_SDI 1
+#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19 SC_P_SPI3_SDI 3
+#define SC_P_SPI3_CS0_DMA_SPI3_CS0 SC_P_SPI3_CS0 0
+#define SC_P_SPI3_CS0_DMA_FTM_CH2 SC_P_SPI3_CS0 1
+#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20 SC_P_SPI3_CS0 3
+#define SC_P_SPI3_CS1_DMA_SPI3_CS1 SC_P_SPI3_CS1 0
+#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21 SC_P_SPI3_CS1 3
+#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR SC_P_ESAI0_FSR 0
+#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 SC_P_ESAI0_FSR 3
+#define SC_P_ESAI0_FST_AUD_ESAI0_FST SC_P_ESAI0_FST 0
+#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23 SC_P_ESAI0_FST 3
+#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR SC_P_ESAI0_SCKR 0
+#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 SC_P_ESAI0_SCKR 3
+#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT SC_P_ESAI0_SCKT 0
+#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 SC_P_ESAI0_SCKT 3
+#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0 SC_P_ESAI0_TX0 0
+#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 SC_P_ESAI0_TX0 3
+#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1 SC_P_ESAI0_TX1 0
+#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 SC_P_ESAI0_TX1 3
+#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
+#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 SC_P_ESAI0_TX2_RX3 3
+#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
+#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 SC_P_ESAI0_TX3_RX2 3
+#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
+#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 SC_P_ESAI0_TX4_RX1 3
+#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
+#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 SC_P_ESAI0_TX5_RX0 3
+#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
+#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
+#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK SC_P_MCLK_IN0 2
+#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00 SC_P_MCLK_IN0 3
+#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
+#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
+#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK SC_P_MCLK_OUT0 2
+#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01 SC_P_MCLK_OUT0 3
+#define SC_P_SPI0_SCK_DMA_SPI0_SCK SC_P_SPI0_SCK 0
+#define SC_P_SPI0_SCK_AUD_SAI0_RXC SC_P_SPI0_SCK 1
+#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02 SC_P_SPI0_SCK 3
+#define SC_P_SPI0_SDO_DMA_SPI0_SDO SC_P_SPI0_SDO 0
+#define SC_P_SPI0_SDO_AUD_SAI0_TXD SC_P_SPI0_SDO 1
+#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03 SC_P_SPI0_SDO 3
+#define SC_P_SPI0_SDI_DMA_SPI0_SDI SC_P_SPI0_SDI 0
+#define SC_P_SPI0_SDI_AUD_SAI0_RXD SC_P_SPI0_SDI 1
+#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04 SC_P_SPI0_SDI 3
+#define SC_P_SPI0_CS0_DMA_SPI0_CS0 SC_P_SPI0_CS0 0
+#define SC_P_SPI0_CS0_AUD_SAI0_RXFS SC_P_SPI0_CS0 1
+#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05 SC_P_SPI0_CS0 3
+#define SC_P_SPI0_CS1_DMA_SPI0_CS1 SC_P_SPI0_CS1 0
+#define SC_P_SPI0_CS1_AUD_SAI0_TXC SC_P_SPI0_CS1 1
+#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06 SC_P_SPI0_CS1 3
+#define SC_P_SPI2_SCK_DMA_SPI2_SCK SC_P_SPI2_SCK 0
+#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07 SC_P_SPI2_SCK 3
+#define SC_P_SPI2_SDO_DMA_SPI2_SDO SC_P_SPI2_SDO 0
+#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08 SC_P_SPI2_SDO 3
+#define SC_P_SPI2_SDI_DMA_SPI2_SDI SC_P_SPI2_SDI 0
+#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09 SC_P_SPI2_SDI 3
+#define SC_P_SPI2_CS0_DMA_SPI2_CS0 SC_P_SPI2_CS0 0
+#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10 SC_P_SPI2_CS0 3
+#define SC_P_SPI2_CS1_DMA_SPI2_CS1 SC_P_SPI2_CS1 0
+#define SC_P_SPI2_CS1_AUD_SAI0_TXFS SC_P_SPI2_CS1 1
+#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11 SC_P_SPI2_CS1 3
+#define SC_P_SAI1_RXC_AUD_SAI1_RXC SC_P_SAI1_RXC 0
+#define SC_P_SAI1_RXC_AUD_SAI0_TXD SC_P_SAI1_RXC 1
+#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12 SC_P_SAI1_RXC 3
+#define SC_P_SAI1_RXD_AUD_SAI1_RXD SC_P_SAI1_RXD 0
+#define SC_P_SAI1_RXD_AUD_SAI0_TXFS SC_P_SAI1_RXD 1
+#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13 SC_P_SAI1_RXD 3
+#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS SC_P_SAI1_RXFS 0
+#define SC_P_SAI1_RXFS_AUD_SAI0_RXD SC_P_SAI1_RXFS 1
+#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 SC_P_SAI1_RXFS 3
+#define SC_P_SAI1_TXC_AUD_SAI1_TXC SC_P_SAI1_TXC 0
+#define SC_P_SAI1_TXC_AUD_SAI0_TXC SC_P_SAI1_TXC 1
+#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15 SC_P_SAI1_TXC 3
+#define SC_P_SAI1_TXD_AUD_SAI1_TXD SC_P_SAI1_TXD 0
+#define SC_P_SAI1_TXD_AUD_SAI1_RXC SC_P_SAI1_TXD 1
+#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16 SC_P_SAI1_TXD 3
+#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS SC_P_SAI1_TXFS 0
+#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS SC_P_SAI1_TXFS 1
+#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17 SC_P_SAI1_TXFS 3
+#define SC_P_ADC_IN7_DMA_ADC1_IN3 SC_P_ADC_IN7 0
+#define SC_P_ADC_IN7_DMA_SPI1_CS1 SC_P_ADC_IN7 1
+#define SC_P_ADC_IN7_LSIO_KPP0_ROW3 SC_P_ADC_IN7 2
+#define SC_P_ADC_IN7_LSIO_GPIO3_IO25 SC_P_ADC_IN7 3
+#define SC_P_ADC_IN6_DMA_ADC1_IN2 SC_P_ADC_IN6 0
+#define SC_P_ADC_IN6_DMA_SPI1_CS0 SC_P_ADC_IN6 1
+#define SC_P_ADC_IN6_LSIO_KPP0_ROW2 SC_P_ADC_IN6 2
+#define SC_P_ADC_IN6_LSIO_GPIO3_IO24 SC_P_ADC_IN6 3
+#define SC_P_ADC_IN5_DMA_ADC1_IN1 SC_P_ADC_IN5 0
+#define SC_P_ADC_IN5_DMA_SPI1_SDI SC_P_ADC_IN5 1
+#define SC_P_ADC_IN5_LSIO_KPP0_ROW1 SC_P_ADC_IN5 2
+#define SC_P_ADC_IN5_LSIO_GPIO3_IO23 SC_P_ADC_IN5 3
+#define SC_P_ADC_IN4_DMA_ADC1_IN0 SC_P_ADC_IN4 0
+#define SC_P_ADC_IN4_DMA_SPI1_SDO SC_P_ADC_IN4 1
+#define SC_P_ADC_IN4_LSIO_KPP0_ROW0 SC_P_ADC_IN4 2
+#define SC_P_ADC_IN4_LSIO_GPIO3_IO22 SC_P_ADC_IN4 3
+#define SC_P_ADC_IN3_DMA_ADC0_IN3 SC_P_ADC_IN3 0
+#define SC_P_ADC_IN3_DMA_SPI1_SCK SC_P_ADC_IN3 1
+#define SC_P_ADC_IN3_LSIO_KPP0_COL3 SC_P_ADC_IN3 2
+#define SC_P_ADC_IN3_LSIO_GPIO3_IO21 SC_P_ADC_IN3 3
+#define SC_P_ADC_IN2_DMA_ADC0_IN2 SC_P_ADC_IN2 0
+#define SC_P_ADC_IN2_LSIO_KPP0_COL2 SC_P_ADC_IN2 2
+#define SC_P_ADC_IN2_LSIO_GPIO3_IO20 SC_P_ADC_IN2 3
+#define SC_P_ADC_IN1_DMA_ADC0_IN1 SC_P_ADC_IN1 0
+#define SC_P_ADC_IN1_LSIO_KPP0_COL1 SC_P_ADC_IN1 2
+#define SC_P_ADC_IN1_LSIO_GPIO3_IO19 SC_P_ADC_IN1 3
+#define SC_P_ADC_IN0_DMA_ADC0_IN0 SC_P_ADC_IN0 0
+#define SC_P_ADC_IN0_LSIO_KPP0_COL0 SC_P_ADC_IN0 2
+#define SC_P_ADC_IN0_LSIO_GPIO3_IO18 SC_P_ADC_IN0 3
+#define SC_P_MLB_SIG_CONN_MLB_SIG SC_P_MLB_SIG 0
+#define SC_P_MLB_SIG_AUD_SAI3_RXC SC_P_MLB_SIG 1
+#define SC_P_MLB_SIG_LSIO_GPIO3_IO26 SC_P_MLB_SIG 3
+#define SC_P_MLB_CLK_CONN_MLB_CLK SC_P_MLB_CLK 0
+#define SC_P_MLB_CLK_AUD_SAI3_RXFS SC_P_MLB_CLK 1
+#define SC_P_MLB_CLK_LSIO_GPIO3_IO27 SC_P_MLB_CLK 3
+#define SC_P_MLB_DATA_CONN_MLB_DATA SC_P_MLB_DATA 0
+#define SC_P_MLB_DATA_AUD_SAI3_RXD SC_P_MLB_DATA 1
+#define SC_P_MLB_DATA_LSIO_GPIO3_IO28 SC_P_MLB_DATA 3
+#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29 SC_P_FLEXCAN0_RX 3
+#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30 SC_P_FLEXCAN0_TX 3
+#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 SC_P_FLEXCAN1_RX 3
+#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 SC_P_FLEXCAN1_TX 3
+#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 SC_P_FLEXCAN2_RX 3
+#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 SC_P_FLEXCAN2_TX 3
+#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL SC_P_USB_SS3_TC0 0
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
+#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 3
+#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL SC_P_USB_SS3_TC1 0
+#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
+#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 3
+#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA SC_P_USB_SS3_TC2 0
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
+#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 3
+#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA SC_P_USB_SS3_TC3 0
+#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
+#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 3
+#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 SC_P_USDHC1_RESET_B 3
+#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 SC_P_USDHC1_VSELECT 3
+#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B SC_P_USDHC2_RESET_B 0
+#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 SC_P_USDHC2_RESET_B 3
+#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT SC_P_USDHC2_VSELECT 0
+#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10 SC_P_USDHC2_VSELECT 3
+#define SC_P_USDHC2_WP_CONN_USDHC2_WP SC_P_USDHC2_WP 0
+#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11 SC_P_USDHC2_WP 3
+#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B SC_P_USDHC2_CD_B 0
+#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 SC_P_USDHC2_CD_B 3
+#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
+#define SC_P_ENET0_MDIO_DMA_I2C4_SDA SC_P_ENET0_MDIO 1
+#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 SC_P_ENET0_MDIO 3
+#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
+#define SC_P_ENET0_MDC_DMA_I2C4_SCL SC_P_ENET0_MDC 1
+#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14 SC_P_ENET0_MDC 3
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
+#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 SC_P_ENET0_REFCLK_125M_25M 3
+#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M SC_P_ENET1_REFCLK_125M_25M 0
+#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET1_REFCLK_125M_25M 1
+#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 SC_P_ENET1_REFCLK_125M_25M 3
+#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO SC_P_ENET1_MDIO 0
+#define SC_P_ENET1_MDIO_DMA_I2C4_SDA SC_P_ENET1_MDIO 1
+#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 SC_P_ENET1_MDIO 3
+#define SC_P_ENET1_MDC_CONN_ENET1_MDC SC_P_ENET1_MDC 0
+#define SC_P_ENET1_MDC_DMA_I2C4_SCL SC_P_ENET1_MDC 1
+#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18 SC_P_ENET1_MDC 3
+#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI1A_SS0_B 0
+#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 SC_P_QSPI1A_SS0_B 3
+#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI1A_SS1_B 0
+#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 SC_P_QSPI1A_SS1_B 1
+#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 SC_P_QSPI1A_SS1_B 3
+#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI1A_SCLK 0
+#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 SC_P_QSPI1A_SCLK 3
+#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS SC_P_QSPI1A_DQS 0
+#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 SC_P_QSPI1A_DQS 3
+#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI1A_DATA3 0
+#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA SC_P_QSPI1A_DATA3 1
+#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC SC_P_QSPI1A_DATA3 2
+#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 SC_P_QSPI1A_DATA3 3
+#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI1A_DATA2 0
+#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL SC_P_QSPI1A_DATA2 1
+#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR SC_P_QSPI1A_DATA2 2
+#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 SC_P_QSPI1A_DATA2 3
+#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI1A_DATA1 0
+#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA SC_P_QSPI1A_DATA1 1
+#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC SC_P_QSPI1A_DATA1 2
+#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 SC_P_QSPI1A_DATA1 3
+#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI1A_DATA0 0
+#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 SC_P_QSPI1A_DATA0 3
+#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
+#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
+#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
+#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
+#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
+#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 SC_P_QSPI0A_SS1_B 1
+#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
+#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 SC_P_QSPI0B_SS1_B 1
+#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 SC_P_PCIE_CTRL0_CLKREQ_B 3
+#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 SC_P_PCIE_CTRL0_WAKE_B 3
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 SC_P_PCIE_CTRL0_PERST_B 3
+#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B SC_P_PCIE_CTRL1_CLKREQ_B 0
+#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA SC_P_PCIE_CTRL1_CLKREQ_B 1
+#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC SC_P_PCIE_CTRL1_CLKREQ_B 2
+#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 SC_P_PCIE_CTRL1_CLKREQ_B 3
+#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B SC_P_PCIE_CTRL1_WAKE_B 0
+#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_WAKE_B 1
+#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR SC_P_PCIE_CTRL1_WAKE_B 2
+#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 SC_P_PCIE_CTRL1_WAKE_B 3
+#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B SC_P_PCIE_CTRL1_PERST_B 0
+#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_PERST_B 1
+#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR SC_P_PCIE_CTRL1_PERST_B 2
+#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 SC_P_PCIE_CTRL1_PERST_B 3
+#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA SC_P_USB_HSIC0_DATA 0
+#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA SC_P_USB_HSIC0_DATA 1
+#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01 SC_P_USB_HSIC0_DATA 3
+#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE SC_P_USB_HSIC0_STROBE 0
+#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL SC_P_USB_HSIC0_STROBE 1
+#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 SC_P_USB_HSIC0_STROBE 3
+#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
+#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
+#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
+#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
+#define SC_P_EMMC0_CMD_AUD_MQS_R SC_P_EMMC0_CMD 2
+#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03 SC_P_EMMC0_CMD 3
+#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
+#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
+#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04 SC_P_EMMC0_DATA0 3
+#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
+#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
+#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05 SC_P_EMMC0_DATA1 3
+#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
+#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
+#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06 SC_P_EMMC0_DATA2 3
+#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
+#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
+#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07 SC_P_EMMC0_DATA3 3
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
+#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
+#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08 SC_P_EMMC0_DATA4 3
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
+#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
+#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09 SC_P_EMMC0_DATA5 3
+#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
+#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
+#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10 SC_P_EMMC0_DATA6 3
+#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
+#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
+#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11 SC_P_EMMC0_DATA7 3
+#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
+#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
+#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12 SC_P_EMMC0_STROBE 3
+#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
+#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
+#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT SC_P_EMMC0_RESET_B 2
+#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13 SC_P_EMMC0_RESET_B 3
+#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
+#define SC_P_USDHC1_CLK_AUD_MQS_R SC_P_USDHC1_CLK 1
+#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
+#define SC_P_USDHC1_CMD_AUD_MQS_L SC_P_USDHC1_CMD 1
+#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14 SC_P_USDHC1_CMD 3
+#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
+#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N SC_P_USDHC1_DATA0 1
+#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15 SC_P_USDHC1_DATA0 3
+#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
+#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P SC_P_USDHC1_DATA1 1
+#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16 SC_P_USDHC1_DATA1 3
+#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
+#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N SC_P_USDHC1_DATA2 1
+#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17 SC_P_USDHC1_DATA2 3
+#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
+#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P SC_P_USDHC1_DATA3 1
+#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18 SC_P_USDHC1_DATA3 3
+#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 SC_P_USDHC1_DATA4 0
+#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B SC_P_USDHC1_DATA4 1
+#define SC_P_USDHC1_DATA4_AUD_MQS_R SC_P_USDHC1_DATA4 2
+#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19 SC_P_USDHC1_DATA4 3
+#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 SC_P_USDHC1_DATA5 0
+#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B SC_P_USDHC1_DATA5 1
+#define SC_P_USDHC1_DATA5_AUD_MQS_L SC_P_USDHC1_DATA5 2
+#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 SC_P_USDHC1_DATA5 3
+#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 SC_P_USDHC1_DATA6 0
+#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B SC_P_USDHC1_DATA6 1
+#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP SC_P_USDHC1_DATA6 2
+#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 SC_P_USDHC1_DATA6 3
+#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 SC_P_USDHC1_DATA7 0
+#define SC_P_USDHC1_DATA7_CONN_NAND_ALE SC_P_USDHC1_DATA7 1
+#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B SC_P_USDHC1_DATA7 2
+#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 SC_P_USDHC1_DATA7 3
+#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE SC_P_USDHC1_STROBE 0
+#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B SC_P_USDHC1_STROBE 1
+#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B SC_P_USDHC1_STROBE 2
+#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 SC_P_USDHC1_STROBE 3
+#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK SC_P_USDHC2_CLK 0
+#define SC_P_USDHC2_CLK_AUD_MQS_R SC_P_USDHC2_CLK 1
+#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24 SC_P_USDHC2_CLK 3
+#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD SC_P_USDHC2_CMD 0
+#define SC_P_USDHC2_CMD_AUD_MQS_L SC_P_USDHC2_CMD 1
+#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 SC_P_USDHC2_CMD 3
+#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 SC_P_USDHC2_DATA0 0
+#define SC_P_USDHC2_DATA0_DMA_UART4_RX SC_P_USDHC2_DATA0 1
+#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 SC_P_USDHC2_DATA0 3
+#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 SC_P_USDHC2_DATA1 0
+#define SC_P_USDHC2_DATA1_DMA_UART4_TX SC_P_USDHC2_DATA1 1
+#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 SC_P_USDHC2_DATA1 3
+#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 SC_P_USDHC2_DATA2 0
+#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B SC_P_USDHC2_DATA2 1
+#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28 SC_P_USDHC2_DATA2 3
+#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 SC_P_USDHC2_DATA3 0
+#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B SC_P_USDHC2_DATA3 1
+#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 SC_P_USDHC2_DATA3 3
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
+#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 SC_P_ENET0_RGMII_TXC 3
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
+#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 SC_P_ENET0_RGMII_TX_CTL 3
+#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
+#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 SC_P_ENET0_RGMII_TXD0 3
+#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
+#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 SC_P_ENET0_RGMII_TXD1 3
+#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
+#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX SC_P_ENET0_RGMII_TXD2 1
+#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET0_RGMII_TXD2 2
+#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 SC_P_ENET0_RGMII_TXD2 3
+#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
+#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET0_RGMII_TXD3 1
+#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET0_RGMII_TXD3 2
+#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 SC_P_ENET0_RGMII_TXD3 3
+#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
+#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET0_RGMII_RXC 1
+#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET0_RGMII_RXC 2
+#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 SC_P_ENET0_RGMII_RXC 3
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
+#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET0_RGMII_RX_CTL 2
+#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 SC_P_ENET0_RGMII_RX_CTL 3
+#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
+#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET0_RGMII_RXD0 2
+#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 SC_P_ENET0_RGMII_RXD0 3
+#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
+#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET0_RGMII_RXD1 2
+#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 SC_P_ENET0_RGMII_RXD1 3
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
+#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET0_RGMII_RXD2 2
+#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 SC_P_ENET0_RGMII_RXD2 3
+#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
+#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX SC_P_ENET0_RGMII_RXD3 1
+#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET0_RGMII_RXD3 2
+#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 SC_P_ENET0_RGMII_RXD3 3
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC SC_P_ENET1_RGMII_TXC 0
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT SC_P_ENET1_RGMII_TXC 1
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN SC_P_ENET1_RGMII_TXC 2
+#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 SC_P_ENET1_RGMII_TXC 3
+#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL SC_P_ENET1_RGMII_TX_CTL 0
+#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 SC_P_ENET1_RGMII_TX_CTL 3
+#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 SC_P_ENET1_RGMII_TXD0 0
+#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 SC_P_ENET1_RGMII_TXD0 3
+#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 SC_P_ENET1_RGMII_TXD1 0
+#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 SC_P_ENET1_RGMII_TXD1 3
+#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 SC_P_ENET1_RGMII_TXD2 0
+#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX SC_P_ENET1_RGMII_TXD2 1
+#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET1_RGMII_TXD2 2
+#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 SC_P_ENET1_RGMII_TXD2 3
+#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 SC_P_ENET1_RGMII_TXD3 0
+#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET1_RGMII_TXD3 1
+#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET1_RGMII_TXD3 2
+#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 SC_P_ENET1_RGMII_TXD3 3
+#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC SC_P_ENET1_RGMII_RXC 0
+#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET1_RGMII_RXC 1
+#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET1_RGMII_RXC 2
+#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 SC_P_ENET1_RGMII_RXC 3
+#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL SC_P_ENET1_RGMII_RX_CTL 0
+#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET1_RGMII_RX_CTL 2
+#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 SC_P_ENET1_RGMII_RX_CTL 3
+#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 SC_P_ENET1_RGMII_RXD0 0
+#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET1_RGMII_RXD0 2
+#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 SC_P_ENET1_RGMII_RXD0 3
+#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 SC_P_ENET1_RGMII_RXD1 0
+#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET1_RGMII_RXD1 2
+#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 SC_P_ENET1_RGMII_RXD1 3
+#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 SC_P_ENET1_RGMII_RXD2 0
+#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER SC_P_ENET1_RGMII_RXD2 1
+#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET1_RGMII_RXD2 2
+#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 SC_P_ENET1_RGMII_RXD2 3
+#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 SC_P_ENET1_RGMII_RXD3 0
+#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1
+#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2
+#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0
+
+#endif /* SC_PADS_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Defines macros and constants for Renesas RZ/A1 pin controller pin
+ * muxing functions.
+ */
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
+#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
+
+#define RZA1_PINS_PER_PORT 16
+
+/*
+ * Create the pin index from its bank and position numbers and store in
+ * the upper 16 bits the alternate function identifier
+ */
+#define RZA1_PINMUX(b, p, f) \
+ ((b) * RZA1_PINS_PER_PORT + (p) | ((f) << 16))
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */
#define RESET_SD_EMMC_A 44
#define RESET_SD_EMMC_B 45
#define RESET_SD_EMMC_C 46
-/* 47-60 */
+/* 47 */
+#define RESET_USB_PHY20 48
+#define RESET_USB_PHY21 49
+/* 50-60 */
#define RESET_AUDIO_CODEC 61
/* 62-63 */
/* RESET2 */
efi_status_t exit_status,
efi_uintn_t exitdata_size, u16 *exitdata);
efi_status_t (EFIAPI *unload_image)(efi_handle_t image_handle);
- efi_status_t (EFIAPI *exit_boot_services)(efi_handle_t, unsigned long);
+ efi_status_t (EFIAPI *exit_boot_services)(efi_handle_t image_handle,
+ efi_uintn_t map_key);
efi_status_t (EFIAPI *get_next_monotonic_count)(u64 *count);
efi_status_t (EFIAPI *stall)(unsigned long usecs);
aligned_u64 image_size;
unsigned int image_code_type;
unsigned int image_data_type;
- unsigned long unload;
+ efi_status_t (EFIAPI *unload)(efi_handle_t image_handle);
};
#define EFI_DEVICE_PATH_PROTOCOL_GUID \
struct efi_event *wait_for_key_ex;
efi_status_t (EFIAPI *set_state) (
struct efi_simple_text_input_ex_protocol *this,
- u8 key_toggle_state);
+ u8 *key_toggle_state);
efi_status_t (EFIAPI *register_key_notify) (
struct efi_simple_text_input_ex_protocol *this,
struct efi_key_data *key_data,
efi_handle_t driver_binding_handle;
};
+/* Deprecated version of the Unicode collation protocol */
+#define EFI_UNICODE_COLLATION_PROTOCOL_GUID \
+ EFI_GUID(0x1d85cd7f, 0xf43d, 0x11d2, \
+ 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+/* Current version of the Unicode collation protocol */
#define EFI_UNICODE_COLLATION_PROTOCOL2_GUID \
EFI_GUID(0xa4c751fc, 0x23ae, 0x4c3e, \
0x92, 0xe9, 0x49, 0x64, 0xcf, 0x63, 0xf3, 0x49)
/* implementation of the EFI_DEVICE_PATH_UTILITIES_PROTOCOL */
extern const struct efi_device_path_utilities_protocol
efi_device_path_utilities;
-/* Implementation of the EFI_UNICODE_COLLATION_PROTOCOL */
+/* deprecated version of the EFI_UNICODE_COLLATION_PROTOCOL */
extern const struct efi_unicode_collation_protocol
efi_unicode_collation_protocol;
+/* current version of the EFI_UNICODE_COLLATION_PROTOCOL */
+extern const struct efi_unicode_collation_protocol
+ efi_unicode_collation_protocol2;
extern const struct efi_hii_config_routing_protocol efi_hii_config_routing;
extern const struct efi_hii_config_access_protocol efi_hii_config_access;
extern const struct efi_hii_database_protocol efi_hii_database;
/* GUID for file system information */
extern const efi_guid_t efi_file_system_info_guid;
extern const efi_guid_t efi_guid_device_path_utilities_protocol;
-/* GUID of the Unicode collation protocol */
+/* GUID of the deprecated Unicode collation protocol */
extern const efi_guid_t efi_guid_unicode_collation_protocol;
+/* GUID of the Unicode collation protocol */
+extern const efi_guid_t efi_guid_unicode_collation_protocol2;
extern const efi_guid_t efi_guid_hii_config_routing_protocol;
extern const efi_guid_t efi_guid_hii_config_access_protocol;
extern const efi_guid_t efi_guid_hii_database_protocol;
extern unsigned int __efi_runtime_start, __efi_runtime_stop;
extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
-/*
+/**
+ * struct efi_open_protocol_info_item - open protocol info item
+ *
* When a protocol is opened a open protocol info entry is created.
* These are maintained in a list.
+ *
+ * @link: link to the list of open protocol info entries of a protocol
+ * @info: information about the opening of a protocol
*/
struct efi_open_protocol_info_item {
- /* Link to the list of open protocol info entries of a protocol */
struct list_head link;
struct efi_open_protocol_info_entry info;
};
-/*
+/**
+ * struct efi_handler - single protocol interface of a handle
+ *
* When the UEFI payload wants to open a protocol on an object to get its
* interface (usually a struct with callback functions), this struct maps the
* protocol GUID to the respective protocol interface
+ *
+ * @link: link to the list of protocols of a handle
+ * @guid: GUID of the protocol
+ * @protocol_interface: protocol interface
+ * @open_infos link to the list of open protocol info items
*/
struct efi_handler {
- /* Link to the list of protocols of a handle */
struct list_head link;
const efi_guid_t *guid;
void *protocol_interface;
- /* Link to the list of open protocol info items */
struct list_head open_infos;
};
+/**
+ * enum efi_object_type - type of EFI object
+ *
+ * In UnloadImage we must be able to identify if the handle relates to a
+ * started image.
+ */
+enum efi_object_type {
+ EFI_OBJECT_TYPE_UNDEFINED = 0,
+ EFI_OBJECT_TYPE_U_BOOT_FIRMWARE,
+ EFI_OBJECT_TYPE_LOADED_IMAGE,
+ EFI_OBJECT_TYPE_STARTED_IMAGE,
+};
+
/**
* struct efi_object - dereferenced EFI handle
*
struct list_head link;
/* The list of protocols */
struct list_head protocols;
+ enum efi_object_type type;
};
/**
* struct efi_loaded_image_obj - handle of a loaded image
*
* @header: EFI object header
+ * @exit_status: exit status passed to Exit()
+ * @exit_data_size: exit data size passed to Exit()
+ * @exit_data: exit data passed to Exit()
* @exit_jmp: long jump buffer for returning form started image
* @entry: entry address of the relocated image
*/
struct efi_loaded_image_obj {
struct efi_object header;
efi_status_t exit_status;
+ efi_uintn_t *exit_data_size;
+ u16 **exit_data;
struct jmp_buf_data exit_jmp;
EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
struct efi_system_table *st);
+ u16 image_type;
};
/**
/* List of all events */
extern struct list_head efi_events;
+/**
+ * struct efi_protocol_notification - handle for notified protocol
+ *
+ * When a protocol interface is installed for which an event was registered with
+ * the RegisterProtocolNotify() service this structure is used to hold the
+ * handle on which the protocol interface was installed.
+ *
+ * @link: link to list of all handles notified for this event
+ * @handle: handle on which the notified protocol interface was installed
+ */
+struct efi_protocol_notification {
+ struct list_head link;
+ efi_handle_t handle;
+};
+
+/**
+ * efi_register_notify_event - event registered by RegisterProtocolNotify()
+ *
+ * The address of this structure serves as registration value.
+ *
+ * @link: link to list of all registered events
+ * @event: registered event. The same event may registered for multiple
+ * GUIDs.
+ * @protocol: protocol for which the event is registered
+ * @handles: linked list of all handles on which the notified protocol was
+ * installed
+ */
+struct efi_register_notify_event {
+ struct list_head link;
+ struct efi_event *event;
+ efi_guid_t protocol;
+ struct list_head handles;
+};
+
+/* List of all events registered by RegisterProtocolNotify() */
+extern struct list_head efi_register_notify_events;
+
/* Initialize efi execution environment */
efi_status_t efi_init_obj_list(void);
/* Called by bootefi to initialize root node */
struct efi_time *time,
struct efi_time_cap *capabilities);
+efi_status_t __efi_runtime EFIAPI efi_set_time(struct efi_time *time);
+
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
/*
* Entry point for the tests of the EFI API.
u16 file_path_length;
u16 *label;
struct efi_device_path *file_path;
- u8 *optional_data;
+ const u8 *optional_data;
};
void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data);
#define EFI_ST_SUCCESS 0
#define EFI_ST_FAILURE 1
-
+#define EFI_ST_SUCCESS_STR L"SUCCESS"
/*
* Prints a message.
*/
*/
u16 *efi_st_translate_code(u16 code);
-/*
- * Compare memory.
- * We cannot use lib/string.c due to different CFLAGS values.
- *
- * @buf1: first buffer
- * @buf2: second buffer
- * @length: number of bytes to compare
- * @return: 0 if both buffers contain the same bytes
- */
-int efi_st_memcmp(const void *buf1, const void *buf2, size_t length);
-
/*
* Compare an u16 string to a char string.
*
typedef phys_addr_t fdt_addr_t;
typedef phys_size_t fdt_size_t;
-static inline fdt32_t fdt_addr_unpack(fdt_addr_t addr, fdt32_t *upper)
-{
- if (upper)
-#ifdef CONFIG_PHYS_64BIT
- *upper = addr >> 32;
-#else
- *upper = 0;
-#endif
-
- return addr;
-}
-
-static inline fdt32_t fdt_size_unpack(fdt_size_t size, fdt32_t *upper)
-{
- if (upper)
-#ifdef CONFIG_PHYS_64BIT
- *upper = size >> 32;
-#else
- *upper = 0;
-#endif
-
- return size;
-}
-
#ifdef CONFIG_PHYS_64BIT
#define FDT_ADDR_T_NONE (-1U)
#define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
*/
int fdtdec_setup_memory_banksize(void);
+/**
+ * fdtdec_set_ethernet_mac_address() - set MAC address for default interface
+ *
+ * Looks up the default interface via the "ethernet" alias (in the /aliases
+ * node) and stores the given MAC in its "local-mac-address" property. This
+ * is useful on platforms that store the MAC address in a custom location.
+ * Board code can call this in the late init stage to make sure that the
+ * interface device tree node has the right MAC address configured for the
+ * Ethernet uclass to pick it up.
+ *
+ * Typically the FDT passed into this function will be U-Boot's control DTB.
+ * Given that a lot of code may be holding offsets to various nodes in that
+ * tree, this code will only set the "local-mac-address" property in-place,
+ * which means that it needs to exist and have space for the 6-byte address.
+ * This ensures that the operation is non-destructive and does not invalidate
+ * offsets that other drivers may be using.
+ *
+ * @param fdt FDT blob
+ * @param mac buffer containing the MAC address to set
+ * @param size size of MAC address
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size);
+
/**
* fdtdec_set_phandle() - sets the phandle of a given node
*
*/
int fs_size(const char *filename, loff_t *size);
-/*
- * fs_read - Read file from the partition previously set by fs_set_blk_dev()
- * Note that not all filesystem types support either/both offset!=0 or len!=0.
+/**
+ * fs_read() - read file from the partition previously set by fs_set_blk_dev()
+ *
+ * Note that not all filesystem drivers support either or both of offset != 0
+ * and len != 0.
*
- * @filename: Name of file to read from
- * @addr: The address to read into
- * @offset: The offset in file to read from
- * @len: The number of bytes to read. Maybe 0 to read entire file
- * @actread: Returns the actual number of bytes read
- * @return 0 if ok with valid *actread, -1 on error conditions
+ * @filename: full path of the file to read from
+ * @addr: address of the buffer to write to
+ * @offset: offset in the file from where to start reading
+ * @len: the number of bytes to read. Use 0 to read entire file.
+ * @actread: returns the actual number of bytes read
+ * Return: 0 if OK with valid *actread, -1 on error conditions
*/
int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
loff_t *actread);
-/*
- * fs_write - Write file to the partition previously set by fs_set_blk_dev()
- * Note that not all filesystem types support offset!=0.
+/**
+ * fs_write() - write file to the partition previously set by fs_set_blk_dev()
+ *
+ * Note that not all filesystem drivers support offset != 0.
*
- * @filename: Name of file to read from
- * @addr: The address to read into
- * @offset: The offset in file to read from. Maybe 0 to write to start of file
- * @len: The number of bytes to write
- * @actwrite: Returns the actual number of bytes written
- * @return 0 if ok with valid *actwrite, -1 on error conditions
+ * @filename: full path of the file to write to
+ * @addr: address of the buffer to read from
+ * @offset: offset in the file from where to start writing
+ * @len: the number of bytes to write
+ * @actwrite: returns the actual number of bytes written
+ * Return: 0 if OK with valid *actwrite, -1 on error conditions
*/
int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
loff_t *actwrite);
#ifndef __GDSYS_FPGA_H
#define __GDSYS_FPGA_H
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
int init_func_fpga(void);
enum {
&fpga_ptr[ix]->fld, \
offsetof(struct ihs_fpga, fld), \
val)
+#endif
struct ihs_gpio {
u16 read;
};
#endif
-#ifdef CONFIG_IO
-struct ihs_fpga {
- u16 reflection_low; /* 0x0000 */
- u16 versions; /* 0x0002 */
- u16 fpga_features; /* 0x0004 */
- u16 fpga_version; /* 0x0006 */
- u16 reserved_0[5]; /* 0x0008 */
- u16 quad_serdes_reset; /* 0x0012 */
- u16 reserved_1[8181]; /* 0x0014 */
- u16 reflection_high; /* 0x3ffe */
-};
-#endif
-
-#ifdef CONFIG_IO64
-struct ihs_fpga_channel {
- u16 status_int;
- u16 config_int;
- u16 switch_connect_config;
- u16 tx_destination;
-};
-
-struct ihs_fpga_hicb {
- u16 status_int;
- u16 config_int;
-};
-
-struct ihs_fpga {
- u16 reflection_low; /* 0x0000 */
- u16 versions; /* 0x0002 */
- u16 fpga_features; /* 0x0004 */
- u16 fpga_version; /* 0x0006 */
- u16 reserved_0[5]; /* 0x0008 */
- u16 quad_serdes_reset; /* 0x0012 */
- u16 reserved_1[502]; /* 0x0014 */
- struct ihs_fpga_channel ch[32]; /* 0x0400 */
- struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */
- u16 reserved_2[7487]; /* 0x0580 */
- u16 reflection_high; /* 0x3ffe */
-};
-#endif
-
-#ifdef CONFIG_IOCON
-struct ihs_fpga {
- u16 reflection_low; /* 0x0000 */
- u16 versions; /* 0x0002 */
- u16 fpga_version; /* 0x0004 */
- u16 fpga_features; /* 0x0006 */
- u16 reserved_0[1]; /* 0x0008 */
- u16 top_interrupt; /* 0x000a */
- u16 reserved_1[4]; /* 0x000c */
- struct ihs_gpio gpio; /* 0x0014 */
- u16 mpc3w_control; /* 0x001a */
- u16 reserved_2[2]; /* 0x001c */
- struct ihs_io_ep ep; /* 0x0020 */
- u16 reserved_3[9]; /* 0x002e */
- struct ihs_i2c i2c0; /* 0x0040 */
- u16 reserved_4[10]; /* 0x004c */
- u16 mc_int; /* 0x0060 */
- u16 mc_int_en; /* 0x0062 */
- u16 mc_status; /* 0x0064 */
- u16 mc_control; /* 0x0066 */
- u16 mc_tx_data; /* 0x0068 */
- u16 mc_tx_address; /* 0x006a */
- u16 mc_tx_cmd; /* 0x006c */
- u16 mc_res; /* 0x006e */
- u16 mc_rx_cmd_status; /* 0x0070 */
- u16 mc_rx_data; /* 0x0072 */
- u16 reserved_5[69]; /* 0x0074 */
- u16 reflection_high; /* 0x00fe */
- struct ihs_osd osd0; /* 0x0100 */
- u16 reserved_6[889]; /* 0x010e */
- u16 videomem0[2048]; /* 0x0800 */
-};
-#endif
-
-#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
+#if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP)
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
};
#endif
-#ifdef CONFIG_DLVISION_10G
-struct ihs_fpga {
- u16 reflection_low; /* 0x0000 */
- u16 versions; /* 0x0002 */
- u16 fpga_version; /* 0x0004 */
- u16 fpga_features; /* 0x0006 */
- u16 reserved_0[10]; /* 0x0008 */
- u16 extended_interrupt; /* 0x001c */
- u16 reserved_1[29]; /* 0x001e */
- u16 mpc3w_control; /* 0x0058 */
- u16 reserved_2[3]; /* 0x005a */
- struct ihs_i2c i2c0; /* 0x0060 */
- u16 reserved_3[2]; /* 0x006c */
- struct ihs_i2c i2c1; /* 0x0070 */
- u16 reserved_4[194]; /* 0x007c */
- struct ihs_osd osd0; /* 0x0200 */
- u16 reserved_5[761]; /* 0x020e */
- u16 videomem0[2048]; /* 0x0800 */
-};
-#endif
-
#endif
# define IMAGE_ENABLE_SHA1 1
# endif
# else
-# define CONFIG_CRC32 /* FIT images need CRC32 support */
# define IMAGE_ENABLE_CRC32 1
# define IMAGE_ENABLE_MD5 1
# define IMAGE_ENABLE_SHA1 1
int fit_conf_find_compat(const void *fit, const void *fdt);
int fit_conf_get_node(const void *fit, const char *conf_uname);
+int fit_conf_get_prop_node_count(const void *fit, int noffset,
+ const char *prop_name);
+int fit_conf_get_prop_node_index(const void *fit, int noffset,
+ const char *prop_name, int index);
/**
* fit_conf_get_prop_node() - Get node refered to by a configuration
* At present we only support signing on the host, and verification on the
* device
*/
-#if defined(CONFIG_FIT_SIGNATURE)
-# ifdef USE_HOSTCC
+#if defined(USE_HOSTCC)
+# if defined(CONFIG_FIT_SIGNATURE)
# define IMAGE_ENABLE_SIGN 1
# define IMAGE_ENABLE_VERIFY 1
-# include <openssl/evp.h>
-#else
+# include <openssl/evp.h>
+# else
# define IMAGE_ENABLE_SIGN 0
-# define IMAGE_ENABLE_VERIFY 1
+# define IMAGE_ENABLE_VERIFY 0
# endif
#else
# define IMAGE_ENABLE_SIGN 0
-# define IMAGE_ENABLE_VERIFY 0
+# define IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(FIT_SIGNATURE)
#endif
#ifdef USE_HOSTCC
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2005-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2010
- * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
- */
-#ifndef _led_display_h_
-#define _led_display_h_
-
-/* Display Commands */
-#define DISPLAY_CLEAR 0x1 /* Clear the display */
-#define DISPLAY_HOME 0x2 /* Set cursor at home position */
-
-void display_set(int cmd);
-int display_putc(char c);
-#endif
#define __IMMAP_QE_H__
#ifdef CONFIG_MPC83xx
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
-#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309)
#define QE_MURAM_SIZE 0x4000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#ifndef __HAVE_ARCH_STRDUP
extern char * strdup(const char *);
#endif
+extern char * strndup(const char *, size_t);
#ifndef __HAVE_ARCH_STRSWAB
extern char * strswab(const char *);
#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) */
+/*
+ * xxHash - Extremely Fast Hash algorithm
+ * Copyright (C) 2012-2016, Yann Collet.
+ *
+ * You can contact the author at:
+ * - xxHash homepage: http://cyan4973.github.io/xxHash/
+ * - xxHash source repository: https://github.com/Cyan4973/xxHash
+ */
+
+/*
+ * Notice extracted from xxHash homepage:
+ *
+ * xxHash is an extremely fast Hash algorithm, running at RAM speed limits.
+ * It also successfully passes all tests from the SMHasher suite.
+ *
+ * Comparison (single thread, Windows Seven 32 bits, using SMHasher on a Core 2
+ * Duo @3GHz)
+ *
+ * Name Speed Q.Score Author
+ * xxHash 5.4 GB/s 10
+ * CrapWow 3.2 GB/s 2 Andrew
+ * MumurHash 3a 2.7 GB/s 10 Austin Appleby
+ * SpookyHash 2.0 GB/s 10 Bob Jenkins
+ * SBox 1.4 GB/s 9 Bret Mulvey
+ * Lookup3 1.2 GB/s 9 Bob Jenkins
+ * SuperFastHash 1.2 GB/s 1 Paul Hsieh
+ * CityHash64 1.05 GB/s 10 Pike & Alakuijala
+ * FNV 0.55 GB/s 5 Fowler, Noll, Vo
+ * CRC32 0.43 GB/s 9
+ * MD5-32 0.33 GB/s 10 Ronald L. Rivest
+ * SHA1-32 0.28 GB/s 10
+ *
+ * Q.Score is a measure of quality of the hash function.
+ * It depends on successfully passing SMHasher test set.
+ * 10 is a perfect score.
+ *
+ * A 64-bits version, named xxh64 offers much better speed,
+ * but for 64-bits applications only.
+ * Name Speed on 64 bits Speed on 32 bits
+ * xxh64 13.8 GB/s 1.9 GB/s
+ * xxh32 6.8 GB/s 6.0 GB/s
+ */
+
+#ifndef XXHASH_H
+#define XXHASH_H
+
+#include <linux/types.h>
+
+/*-****************************
+ * Simple Hash Functions
+ *****************************/
+
+/**
+ * xxh32() - calculate the 32-bit hash of the input with a given seed.
+ *
+ * @input: The data to hash.
+ * @length: The length of the data to hash.
+ * @seed: The seed can be used to alter the result predictably.
+ *
+ * Speed on Core 2 Duo @ 3 GHz (single thread, SMHasher benchmark) : 5.4 GB/s
+ *
+ * Return: The 32-bit hash of the data.
+ */
+uint32_t xxh32(const void *input, size_t length, uint32_t seed);
+
+/**
+ * xxh64() - calculate the 64-bit hash of the input with a given seed.
+ *
+ * @input: The data to hash.
+ * @length: The length of the data to hash.
+ * @seed: The seed can be used to alter the result predictably.
+ *
+ * This function runs 2x faster on 64-bit systems, but slower on 32-bit systems.
+ *
+ * Return: The 64-bit hash of the data.
+ */
+uint64_t xxh64(const void *input, size_t length, uint64_t seed);
+
+/**
+ * xxhash() - calculate wordsize hash of the input with a given seed
+ * @input: The data to hash.
+ * @length: The length of the data to hash.
+ * @seed: The seed can be used to alter the result predictably.
+ *
+ * If the hash does not need to be comparable between machines with
+ * different word sizes, this function will call whichever of xxh32()
+ * or xxh64() is faster.
+ *
+ * Return: wordsize hash of the data.
+ */
+
+static inline unsigned long xxhash(const void *input, size_t length,
+ uint64_t seed)
+{
+#if BITS_PER_LONG == 64
+ return xxh64(input, length, seed);
+#else
+ return xxh32(input, length, seed);
+#endif
+}
+
+/*-****************************
+ * Streaming Hash Functions
+ *****************************/
+
+/*
+ * These definitions are only meant to allow allocation of XXH state
+ * statically, on stack, or in a struct for example.
+ * Do not use members directly.
+ */
+
+/**
+ * struct xxh32_state - private xxh32 state, do not use members directly
+ */
+struct xxh32_state {
+ uint32_t total_len_32;
+ uint32_t large_len;
+ uint32_t v1;
+ uint32_t v2;
+ uint32_t v3;
+ uint32_t v4;
+ uint32_t mem32[4];
+ uint32_t memsize;
+};
+
+/**
+ * struct xxh32_state - private xxh64 state, do not use members directly
+ */
+struct xxh64_state {
+ uint64_t total_len;
+ uint64_t v1;
+ uint64_t v2;
+ uint64_t v3;
+ uint64_t v4;
+ uint64_t mem64[4];
+ uint32_t memsize;
+};
+
+/**
+ * xxh32_reset() - reset the xxh32 state to start a new hashing operation
+ *
+ * @state: The xxh32 state to reset.
+ * @seed: Initialize the hash state with this seed.
+ *
+ * Call this function on any xxh32_state to prepare for a new hashing operation.
+ */
+void xxh32_reset(struct xxh32_state *state, uint32_t seed);
+
+/**
+ * xxh32_update() - hash the data given and update the xxh32 state
+ *
+ * @state: The xxh32 state to update.
+ * @input: The data to hash.
+ * @length: The length of the data to hash.
+ *
+ * After calling xxh32_reset() call xxh32_update() as many times as necessary.
+ *
+ * Return: Zero on success, otherwise an error code.
+ */
+int xxh32_update(struct xxh32_state *state, const void *input, size_t length);
+
+/**
+ * xxh32_digest() - produce the current xxh32 hash
+ *
+ * @state: Produce the current xxh32 hash of this state.
+ *
+ * A hash value can be produced at any time. It is still possible to continue
+ * inserting input into the hash state after a call to xxh32_digest(), and
+ * generate new hashes later on, by calling xxh32_digest() again.
+ *
+ * Return: The xxh32 hash stored in the state.
+ */
+uint32_t xxh32_digest(const struct xxh32_state *state);
+
+/**
+ * xxh64_reset() - reset the xxh64 state to start a new hashing operation
+ *
+ * @state: The xxh64 state to reset.
+ * @seed: Initialize the hash state with this seed.
+ */
+void xxh64_reset(struct xxh64_state *state, uint64_t seed);
+
+/**
+ * xxh64_update() - hash the data given and update the xxh64 state
+ * @state: The xxh64 state to update.
+ * @input: The data to hash.
+ * @length: The length of the data to hash.
+ *
+ * After calling xxh64_reset() call xxh64_update() as many times as necessary.
+ *
+ * Return: Zero on success, otherwise an error code.
+ */
+int xxh64_update(struct xxh64_state *state, const void *input, size_t length);
+
+/**
+ * xxh64_digest() - produce the current xxh64 hash
+ *
+ * @state: Produce the current xxh64 hash of this state.
+ *
+ * A hash value can be produced at any time. It is still possible to continue
+ * inserting input into the hash state after a call to xxh64_digest(), and
+ * generate new hashes later on, by calling xxh64_digest() again.
+ *
+ * Return: The xxh64 hash stored in the state.
+ */
+uint64_t xxh64_digest(const struct xxh64_state *state);
+
+/*-**************************
+ * Utils
+ ***************************/
+
+/**
+ * xxh32_copy_state() - copy the source state into the destination state
+ *
+ * @src: The source xxh32 state.
+ * @dst: The destination xxh32 state.
+ */
+void xxh32_copy_state(struct xxh32_state *dst, const struct xxh32_state *src);
+
+/**
+ * xxh64_copy_state() - copy the source state into the destination state
+ *
+ * @src: The source xxh64 state.
+ * @dst: The destination xxh64 state.
+ */
+void xxh64_copy_state(struct xxh64_state *dst, const struct xxh64_state *src);
+
+#endif /* XXHASH_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */
+/*
+ * Copyright (c) 2016-present, Yann Collet, Facebook, Inc.
+ * All rights reserved.
+ */
+
+#ifndef ZSTD_H
+#define ZSTD_H
+
+/* ====== Dependency ======*/
+#include <linux/types.h> /* size_t */
+
+
+/*-*****************************************************************************
+ * Introduction
+ *
+ * zstd, short for Zstandard, is a fast lossless compression algorithm,
+ * targeting real-time compression scenarios at zlib-level and better
+ * compression ratios. The zstd compression library provides in-memory
+ * compression and decompression functions. The library supports compression
+ * levels from 1 up to ZSTD_maxCLevel() which is 22. Levels >= 20, labeled
+ * ultra, should be used with caution, as they require more memory.
+ * Compression can be done in:
+ * - a single step, reusing a context (described as Explicit memory management)
+ * - unbounded multiple steps (described as Streaming compression)
+ * The compression ratio achievable on small data can be highly improved using
+ * compression with a dictionary in:
+ * - a single step (described as Simple dictionary API)
+ * - a single step, reusing a dictionary (described as Fast dictionary API)
+ ******************************************************************************/
+
+/*====== Helper functions ======*/
+
+/**
+ * enum ZSTD_ErrorCode - zstd error codes
+ *
+ * Functions that return size_t can be checked for errors using ZSTD_isError()
+ * and the ZSTD_ErrorCode can be extracted using ZSTD_getErrorCode().
+ */
+typedef enum {
+ ZSTD_error_no_error,
+ ZSTD_error_GENERIC,
+ ZSTD_error_prefix_unknown,
+ ZSTD_error_version_unsupported,
+ ZSTD_error_parameter_unknown,
+ ZSTD_error_frameParameter_unsupported,
+ ZSTD_error_frameParameter_unsupportedBy32bits,
+ ZSTD_error_frameParameter_windowTooLarge,
+ ZSTD_error_compressionParameter_unsupported,
+ ZSTD_error_init_missing,
+ ZSTD_error_memory_allocation,
+ ZSTD_error_stage_wrong,
+ ZSTD_error_dstSize_tooSmall,
+ ZSTD_error_srcSize_wrong,
+ ZSTD_error_corruption_detected,
+ ZSTD_error_checksum_wrong,
+ ZSTD_error_tableLog_tooLarge,
+ ZSTD_error_maxSymbolValue_tooLarge,
+ ZSTD_error_maxSymbolValue_tooSmall,
+ ZSTD_error_dictionary_corrupted,
+ ZSTD_error_dictionary_wrong,
+ ZSTD_error_dictionaryCreation_failed,
+ ZSTD_error_maxCode
+} ZSTD_ErrorCode;
+
+/**
+ * ZSTD_maxCLevel() - maximum compression level available
+ *
+ * Return: Maximum compression level available.
+ */
+int ZSTD_maxCLevel(void);
+/**
+ * ZSTD_compressBound() - maximum compressed size in worst case scenario
+ * @srcSize: The size of the data to compress.
+ *
+ * Return: The maximum compressed size in the worst case scenario.
+ */
+size_t ZSTD_compressBound(size_t srcSize);
+/**
+ * ZSTD_isError() - tells if a size_t function result is an error code
+ * @code: The function result to check for error.
+ *
+ * Return: Non-zero iff the code is an error.
+ */
+static __attribute__((unused)) unsigned int ZSTD_isError(size_t code)
+{
+ return code > (size_t)-ZSTD_error_maxCode;
+}
+/**
+ * ZSTD_getErrorCode() - translates an error function result to a ZSTD_ErrorCode
+ * @functionResult: The result of a function for which ZSTD_isError() is true.
+ *
+ * Return: The ZSTD_ErrorCode corresponding to the functionResult or 0
+ * if the functionResult isn't an error.
+ */
+static __attribute__((unused)) ZSTD_ErrorCode ZSTD_getErrorCode(
+ size_t functionResult)
+{
+ if (!ZSTD_isError(functionResult))
+ return (ZSTD_ErrorCode)0;
+ return (ZSTD_ErrorCode)(0 - functionResult);
+}
+
+/**
+ * enum ZSTD_strategy - zstd compression search strategy
+ *
+ * From faster to stronger.
+ */
+typedef enum {
+ ZSTD_fast,
+ ZSTD_dfast,
+ ZSTD_greedy,
+ ZSTD_lazy,
+ ZSTD_lazy2,
+ ZSTD_btlazy2,
+ ZSTD_btopt,
+ ZSTD_btopt2
+} ZSTD_strategy;
+
+/**
+ * struct ZSTD_compressionParameters - zstd compression parameters
+ * @windowLog: Log of the largest match distance. Larger means more
+ * compression, and more memory needed during decompression.
+ * @chainLog: Fully searched segment. Larger means more compression, slower,
+ * and more memory (useless for fast).
+ * @hashLog: Dispatch table. Larger means more compression,
+ * slower, and more memory.
+ * @searchLog: Number of searches. Larger means more compression and slower.
+ * @searchLength: Match length searched. Larger means faster decompression,
+ * sometimes less compression.
+ * @targetLength: Acceptable match size for optimal parser (only). Larger means
+ * more compression, and slower.
+ * @strategy: The zstd compression strategy.
+ */
+typedef struct {
+ unsigned int windowLog;
+ unsigned int chainLog;
+ unsigned int hashLog;
+ unsigned int searchLog;
+ unsigned int searchLength;
+ unsigned int targetLength;
+ ZSTD_strategy strategy;
+} ZSTD_compressionParameters;
+
+/**
+ * struct ZSTD_frameParameters - zstd frame parameters
+ * @contentSizeFlag: Controls whether content size will be present in the frame
+ * header (when known).
+ * @checksumFlag: Controls whether a 32-bit checksum is generated at the end
+ * of the frame for error detection.
+ * @noDictIDFlag: Controls whether dictID will be saved into the frame header
+ * when using dictionary compression.
+ *
+ * The default value is all fields set to 0.
+ */
+typedef struct {
+ unsigned int contentSizeFlag;
+ unsigned int checksumFlag;
+ unsigned int noDictIDFlag;
+} ZSTD_frameParameters;
+
+/**
+ * struct ZSTD_parameters - zstd parameters
+ * @cParams: The compression parameters.
+ * @fParams: The frame parameters.
+ */
+typedef struct {
+ ZSTD_compressionParameters cParams;
+ ZSTD_frameParameters fParams;
+} ZSTD_parameters;
+
+/**
+ * ZSTD_getCParams() - returns ZSTD_compressionParameters for selected level
+ * @compressionLevel: The compression level from 1 to ZSTD_maxCLevel().
+ * @estimatedSrcSize: The estimated source size to compress or 0 if unknown.
+ * @dictSize: The dictionary size or 0 if a dictionary isn't being used.
+ *
+ * Return: The selected ZSTD_compressionParameters.
+ */
+ZSTD_compressionParameters ZSTD_getCParams(int compressionLevel,
+ unsigned long long estimatedSrcSize, size_t dictSize);
+
+/**
+ * ZSTD_getParams() - returns ZSTD_parameters for selected level
+ * @compressionLevel: The compression level from 1 to ZSTD_maxCLevel().
+ * @estimatedSrcSize: The estimated source size to compress or 0 if unknown.
+ * @dictSize: The dictionary size or 0 if a dictionary isn't being used.
+ *
+ * The same as ZSTD_getCParams() except also selects the default frame
+ * parameters (all zero).
+ *
+ * Return: The selected ZSTD_parameters.
+ */
+ZSTD_parameters ZSTD_getParams(int compressionLevel,
+ unsigned long long estimatedSrcSize, size_t dictSize);
+
+/*-*************************************
+ * Explicit memory management
+ **************************************/
+
+/**
+ * ZSTD_CCtxWorkspaceBound() - amount of memory needed to initialize a ZSTD_CCtx
+ * @cParams: The compression parameters to be used for compression.
+ *
+ * If multiple compression parameters might be used, the caller must call
+ * ZSTD_CCtxWorkspaceBound() for each set of parameters and use the maximum
+ * size.
+ *
+ * Return: A lower bound on the size of the workspace that is passed to
+ * ZSTD_initCCtx().
+ */
+size_t ZSTD_CCtxWorkspaceBound(ZSTD_compressionParameters cParams);
+
+/**
+ * struct ZSTD_CCtx - the zstd compression context
+ *
+ * When compressing many times it is recommended to allocate a context just once
+ * and reuse it for each successive compression operation.
+ */
+typedef struct ZSTD_CCtx_s ZSTD_CCtx;
+/**
+ * ZSTD_initCCtx() - initialize a zstd compression context
+ * @workspace: The workspace to emplace the context into. It must outlive
+ * the returned context.
+ * @workspaceSize: The size of workspace. Use ZSTD_CCtxWorkspaceBound() to
+ * determine how large the workspace must be.
+ *
+ * Return: A compression context emplaced into workspace.
+ */
+ZSTD_CCtx *ZSTD_initCCtx(void *workspace, size_t workspaceSize);
+
+/**
+ * ZSTD_compressCCtx() - compress src into dst
+ * @ctx: The context. Must have been initialized with a workspace at
+ * least as large as ZSTD_CCtxWorkspaceBound(params.cParams).
+ * @dst: The buffer to compress src into.
+ * @dstCapacity: The size of the destination buffer. May be any size, but
+ * ZSTD_compressBound(srcSize) is guaranteed to be large enough.
+ * @src: The data to compress.
+ * @srcSize: The size of the data to compress.
+ * @params: The parameters to use for compression. See ZSTD_getParams().
+ *
+ * Return: The compressed size or an error, which can be checked using
+ * ZSTD_isError().
+ */
+size_t ZSTD_compressCCtx(ZSTD_CCtx *ctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize, ZSTD_parameters params);
+
+/**
+ * ZSTD_DCtxWorkspaceBound() - amount of memory needed to initialize a ZSTD_DCtx
+ *
+ * Return: A lower bound on the size of the workspace that is passed to
+ * ZSTD_initDCtx().
+ */
+size_t ZSTD_DCtxWorkspaceBound(void);
+
+/**
+ * struct ZSTD_DCtx - the zstd decompression context
+ *
+ * When decompressing many times it is recommended to allocate a context just
+ * once and reuse it for each successive decompression operation.
+ */
+typedef struct ZSTD_DCtx_s ZSTD_DCtx;
+/**
+ * ZSTD_initDCtx() - initialize a zstd decompression context
+ * @workspace: The workspace to emplace the context into. It must outlive
+ * the returned context.
+ * @workspaceSize: The size of workspace. Use ZSTD_DCtxWorkspaceBound() to
+ * determine how large the workspace must be.
+ *
+ * Return: A decompression context emplaced into workspace.
+ */
+ZSTD_DCtx *ZSTD_initDCtx(void *workspace, size_t workspaceSize);
+
+/**
+ * ZSTD_decompressDCtx() - decompress zstd compressed src into dst
+ * @ctx: The decompression context.
+ * @dst: The buffer to decompress src into.
+ * @dstCapacity: The size of the destination buffer. Must be at least as large
+ * as the decompressed size. If the caller cannot upper bound the
+ * decompressed size, then it's better to use the streaming API.
+ * @src: The zstd compressed data to decompress. Multiple concatenated
+ * frames and skippable frames are allowed.
+ * @srcSize: The exact size of the data to decompress.
+ *
+ * Return: The decompressed size or an error, which can be checked using
+ * ZSTD_isError().
+ */
+size_t ZSTD_decompressDCtx(ZSTD_DCtx *ctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize);
+
+/*-************************
+ * Simple dictionary API
+ **************************/
+
+/**
+ * ZSTD_compress_usingDict() - compress src into dst using a dictionary
+ * @ctx: The context. Must have been initialized with a workspace at
+ * least as large as ZSTD_CCtxWorkspaceBound(params.cParams).
+ * @dst: The buffer to compress src into.
+ * @dstCapacity: The size of the destination buffer. May be any size, but
+ * ZSTD_compressBound(srcSize) is guaranteed to be large enough.
+ * @src: The data to compress.
+ * @srcSize: The size of the data to compress.
+ * @dict: The dictionary to use for compression.
+ * @dictSize: The size of the dictionary.
+ * @params: The parameters to use for compression. See ZSTD_getParams().
+ *
+ * Compression using a predefined dictionary. The same dictionary must be used
+ * during decompression.
+ *
+ * Return: The compressed size or an error, which can be checked using
+ * ZSTD_isError().
+ */
+size_t ZSTD_compress_usingDict(ZSTD_CCtx *ctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize, const void *dict, size_t dictSize,
+ ZSTD_parameters params);
+
+/**
+ * ZSTD_decompress_usingDict() - decompress src into dst using a dictionary
+ * @ctx: The decompression context.
+ * @dst: The buffer to decompress src into.
+ * @dstCapacity: The size of the destination buffer. Must be at least as large
+ * as the decompressed size. If the caller cannot upper bound the
+ * decompressed size, then it's better to use the streaming API.
+ * @src: The zstd compressed data to decompress. Multiple concatenated
+ * frames and skippable frames are allowed.
+ * @srcSize: The exact size of the data to decompress.
+ * @dict: The dictionary to use for decompression. The same dictionary
+ * must've been used to compress the data.
+ * @dictSize: The size of the dictionary.
+ *
+ * Return: The decompressed size or an error, which can be checked using
+ * ZSTD_isError().
+ */
+size_t ZSTD_decompress_usingDict(ZSTD_DCtx *ctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize, const void *dict, size_t dictSize);
+
+/*-**************************
+ * Fast dictionary API
+ ***************************/
+
+/**
+ * ZSTD_CDictWorkspaceBound() - memory needed to initialize a ZSTD_CDict
+ * @cParams: The compression parameters to be used for compression.
+ *
+ * Return: A lower bound on the size of the workspace that is passed to
+ * ZSTD_initCDict().
+ */
+size_t ZSTD_CDictWorkspaceBound(ZSTD_compressionParameters cParams);
+
+/**
+ * struct ZSTD_CDict - a digested dictionary to be used for compression
+ */
+typedef struct ZSTD_CDict_s ZSTD_CDict;
+
+/**
+ * ZSTD_initCDict() - initialize a digested dictionary for compression
+ * @dictBuffer: The dictionary to digest. The buffer is referenced by the
+ * ZSTD_CDict so it must outlive the returned ZSTD_CDict.
+ * @dictSize: The size of the dictionary.
+ * @params: The parameters to use for compression. See ZSTD_getParams().
+ * @workspace: The workspace. It must outlive the returned ZSTD_CDict.
+ * @workspaceSize: The workspace size. Must be at least
+ * ZSTD_CDictWorkspaceBound(params.cParams).
+ *
+ * When compressing multiple messages / blocks with the same dictionary it is
+ * recommended to load it just once. The ZSTD_CDict merely references the
+ * dictBuffer, so it must outlive the returned ZSTD_CDict.
+ *
+ * Return: The digested dictionary emplaced into workspace.
+ */
+ZSTD_CDict *ZSTD_initCDict(const void *dictBuffer, size_t dictSize,
+ ZSTD_parameters params, void *workspace, size_t workspaceSize);
+
+/**
+ * ZSTD_compress_usingCDict() - compress src into dst using a ZSTD_CDict
+ * @ctx: The context. Must have been initialized with a workspace at
+ * least as large as ZSTD_CCtxWorkspaceBound(cParams) where
+ * cParams are the compression parameters used to initialize the
+ * cdict.
+ * @dst: The buffer to compress src into.
+ * @dstCapacity: The size of the destination buffer. May be any size, but
+ * ZSTD_compressBound(srcSize) is guaranteed to be large enough.
+ * @src: The data to compress.
+ * @srcSize: The size of the data to compress.
+ * @cdict: The digested dictionary to use for compression.
+ * @params: The parameters to use for compression. See ZSTD_getParams().
+ *
+ * Compression using a digested dictionary. The same dictionary must be used
+ * during decompression.
+ *
+ * Return: The compressed size or an error, which can be checked using
+ * ZSTD_isError().
+ */
+size_t ZSTD_compress_usingCDict(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize, const ZSTD_CDict *cdict);
+
+
+/**
+ * ZSTD_DDictWorkspaceBound() - memory needed to initialize a ZSTD_DDict
+ *
+ * Return: A lower bound on the size of the workspace that is passed to
+ * ZSTD_initDDict().
+ */
+size_t ZSTD_DDictWorkspaceBound(void);
+
+/**
+ * struct ZSTD_DDict - a digested dictionary to be used for decompression
+ */
+typedef struct ZSTD_DDict_s ZSTD_DDict;
+
+/**
+ * ZSTD_initDDict() - initialize a digested dictionary for decompression
+ * @dictBuffer: The dictionary to digest. The buffer is referenced by the
+ * ZSTD_DDict so it must outlive the returned ZSTD_DDict.
+ * @dictSize: The size of the dictionary.
+ * @workspace: The workspace. It must outlive the returned ZSTD_DDict.
+ * @workspaceSize: The workspace size. Must be at least
+ * ZSTD_DDictWorkspaceBound().
+ *
+ * When decompressing multiple messages / blocks with the same dictionary it is
+ * recommended to load it just once. The ZSTD_DDict merely references the
+ * dictBuffer, so it must outlive the returned ZSTD_DDict.
+ *
+ * Return: The digested dictionary emplaced into workspace.
+ */
+ZSTD_DDict *ZSTD_initDDict(const void *dictBuffer, size_t dictSize,
+ void *workspace, size_t workspaceSize);
+
+/**
+ * ZSTD_decompress_usingDDict() - decompress src into dst using a ZSTD_DDict
+ * @ctx: The decompression context.
+ * @dst: The buffer to decompress src into.
+ * @dstCapacity: The size of the destination buffer. Must be at least as large
+ * as the decompressed size. If the caller cannot upper bound the
+ * decompressed size, then it's better to use the streaming API.
+ * @src: The zstd compressed data to decompress. Multiple concatenated
+ * frames and skippable frames are allowed.
+ * @srcSize: The exact size of the data to decompress.
+ * @ddict: The digested dictionary to use for decompression. The same
+ * dictionary must've been used to compress the data.
+ *
+ * Return: The decompressed size or an error, which can be checked using
+ * ZSTD_isError().
+ */
+size_t ZSTD_decompress_usingDDict(ZSTD_DCtx *dctx, void *dst,
+ size_t dstCapacity, const void *src, size_t srcSize,
+ const ZSTD_DDict *ddict);
+
+
+/*-**************************
+ * Streaming
+ ***************************/
+
+/**
+ * struct ZSTD_inBuffer - input buffer for streaming
+ * @src: Start of the input buffer.
+ * @size: Size of the input buffer.
+ * @pos: Position where reading stopped. Will be updated.
+ * Necessarily 0 <= pos <= size.
+ */
+typedef struct ZSTD_inBuffer_s {
+ const void *src;
+ size_t size;
+ size_t pos;
+} ZSTD_inBuffer;
+
+/**
+ * struct ZSTD_outBuffer - output buffer for streaming
+ * @dst: Start of the output buffer.
+ * @size: Size of the output buffer.
+ * @pos: Position where writing stopped. Will be updated.
+ * Necessarily 0 <= pos <= size.
+ */
+typedef struct ZSTD_outBuffer_s {
+ void *dst;
+ size_t size;
+ size_t pos;
+} ZSTD_outBuffer;
+
+
+
+/*-*****************************************************************************
+ * Streaming compression - HowTo
+ *
+ * A ZSTD_CStream object is required to track streaming operation.
+ * Use ZSTD_initCStream() to initialize a ZSTD_CStream object.
+ * ZSTD_CStream objects can be reused multiple times on consecutive compression
+ * operations. It is recommended to re-use ZSTD_CStream in situations where many
+ * streaming operations will be achieved consecutively. Use one separate
+ * ZSTD_CStream per thread for parallel execution.
+ *
+ * Use ZSTD_compressStream() repetitively to consume input stream.
+ * The function will automatically update both `pos` fields.
+ * Note that it may not consume the entire input, in which case `pos < size`,
+ * and it's up to the caller to present again remaining data.
+ * It returns a hint for the preferred number of bytes to use as an input for
+ * the next function call.
+ *
+ * At any moment, it's possible to flush whatever data remains within internal
+ * buffer, using ZSTD_flushStream(). `output->pos` will be updated. There might
+ * still be some content left within the internal buffer if `output->size` is
+ * too small. It returns the number of bytes left in the internal buffer and
+ * must be called until it returns 0.
+ *
+ * ZSTD_endStream() instructs to finish a frame. It will perform a flush and
+ * write frame epilogue. The epilogue is required for decoders to consider a
+ * frame completed. Similar to ZSTD_flushStream(), it may not be able to flush
+ * the full content if `output->size` is too small. In which case, call again
+ * ZSTD_endStream() to complete the flush. It returns the number of bytes left
+ * in the internal buffer and must be called until it returns 0.
+ ******************************************************************************/
+
+/**
+ * ZSTD_CStreamWorkspaceBound() - memory needed to initialize a ZSTD_CStream
+ * @cParams: The compression parameters to be used for compression.
+ *
+ * Return: A lower bound on the size of the workspace that is passed to
+ * ZSTD_initCStream() and ZSTD_initCStream_usingCDict().
+ */
+size_t ZSTD_CStreamWorkspaceBound(ZSTD_compressionParameters cParams);
+
+/**
+ * struct ZSTD_CStream - the zstd streaming compression context
+ */
+typedef struct ZSTD_CStream_s ZSTD_CStream;
+
+/*===== ZSTD_CStream management functions =====*/
+/**
+ * ZSTD_initCStream() - initialize a zstd streaming compression context
+ * @params: The zstd compression parameters.
+ * @pledgedSrcSize: If params.fParams.contentSizeFlag == 1 then the caller must
+ * pass the source size (zero means empty source). Otherwise,
+ * the caller may optionally pass the source size, or zero if
+ * unknown.
+ * @workspace: The workspace to emplace the context into. It must outlive
+ * the returned context.
+ * @workspaceSize: The size of workspace.
+ * Use ZSTD_CStreamWorkspaceBound(params.cParams) to determine
+ * how large the workspace must be.
+ *
+ * Return: The zstd streaming compression context.
+ */
+ZSTD_CStream *ZSTD_initCStream(ZSTD_parameters params,
+ unsigned long long pledgedSrcSize, void *workspace,
+ size_t workspaceSize);
+
+/**
+ * ZSTD_initCStream_usingCDict() - initialize a streaming compression context
+ * @cdict: The digested dictionary to use for compression.
+ * @pledgedSrcSize: Optionally the source size, or zero if unknown.
+ * @workspace: The workspace to emplace the context into. It must outlive
+ * the returned context.
+ * @workspaceSize: The size of workspace. Call ZSTD_CStreamWorkspaceBound()
+ * with the cParams used to initialize the cdict to determine
+ * how large the workspace must be.
+ *
+ * Return: The zstd streaming compression context.
+ */
+ZSTD_CStream *ZSTD_initCStream_usingCDict(const ZSTD_CDict *cdict,
+ unsigned long long pledgedSrcSize, void *workspace,
+ size_t workspaceSize);
+
+/*===== Streaming compression functions =====*/
+/**
+ * ZSTD_resetCStream() - reset the context using parameters from creation
+ * @zcs: The zstd streaming compression context to reset.
+ * @pledgedSrcSize: Optionally the source size, or zero if unknown.
+ *
+ * Resets the context using the parameters from creation. Skips dictionary
+ * loading, since it can be reused. If `pledgedSrcSize` is non-zero the frame
+ * content size is always written into the frame header.
+ *
+ * Return: Zero or an error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_resetCStream(ZSTD_CStream *zcs, unsigned long long pledgedSrcSize);
+/**
+ * ZSTD_compressStream() - streaming compress some of input into output
+ * @zcs: The zstd streaming compression context.
+ * @output: Destination buffer. `output->pos` is updated to indicate how much
+ * compressed data was written.
+ * @input: Source buffer. `input->pos` is updated to indicate how much data was
+ * read. Note that it may not consume the entire input, in which case
+ * `input->pos < input->size`, and it's up to the caller to present
+ * remaining data again.
+ *
+ * The `input` and `output` buffers may be any size. Guaranteed to make some
+ * forward progress if `input` and `output` are not empty.
+ *
+ * Return: A hint for the number of bytes to use as the input for the next
+ * function call or an error, which can be checked using
+ * ZSTD_isError().
+ */
+size_t ZSTD_compressStream(ZSTD_CStream *zcs, ZSTD_outBuffer *output,
+ ZSTD_inBuffer *input);
+/**
+ * ZSTD_flushStream() - flush internal buffers into output
+ * @zcs: The zstd streaming compression context.
+ * @output: Destination buffer. `output->pos` is updated to indicate how much
+ * compressed data was written.
+ *
+ * ZSTD_flushStream() must be called until it returns 0, meaning all the data
+ * has been flushed. Since ZSTD_flushStream() causes a block to be ended,
+ * calling it too often will degrade the compression ratio.
+ *
+ * Return: The number of bytes still present within internal buffers or an
+ * error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_flushStream(ZSTD_CStream *zcs, ZSTD_outBuffer *output);
+/**
+ * ZSTD_endStream() - flush internal buffers into output and end the frame
+ * @zcs: The zstd streaming compression context.
+ * @output: Destination buffer. `output->pos` is updated to indicate how much
+ * compressed data was written.
+ *
+ * ZSTD_endStream() must be called until it returns 0, meaning all the data has
+ * been flushed and the frame epilogue has been written.
+ *
+ * Return: The number of bytes still present within internal buffers or an
+ * error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_endStream(ZSTD_CStream *zcs, ZSTD_outBuffer *output);
+
+/**
+ * ZSTD_CStreamInSize() - recommended size for the input buffer
+ *
+ * Return: The recommended size for the input buffer.
+ */
+size_t ZSTD_CStreamInSize(void);
+/**
+ * ZSTD_CStreamOutSize() - recommended size for the output buffer
+ *
+ * When the output buffer is at least this large, it is guaranteed to be large
+ * enough to flush at least one complete compressed block.
+ *
+ * Return: The recommended size for the output buffer.
+ */
+size_t ZSTD_CStreamOutSize(void);
+
+
+
+/*-*****************************************************************************
+ * Streaming decompression - HowTo
+ *
+ * A ZSTD_DStream object is required to track streaming operations.
+ * Use ZSTD_initDStream() to initialize a ZSTD_DStream object.
+ * ZSTD_DStream objects can be re-used multiple times.
+ *
+ * Use ZSTD_decompressStream() repetitively to consume your input.
+ * The function will update both `pos` fields.
+ * If `input->pos < input->size`, some input has not been consumed.
+ * It's up to the caller to present again remaining data.
+ * If `output->pos < output->size`, decoder has flushed everything it could.
+ * Returns 0 iff a frame is completely decoded and fully flushed.
+ * Otherwise it returns a suggested next input size that will never load more
+ * than the current frame.
+ ******************************************************************************/
+
+/**
+ * ZSTD_DStreamWorkspaceBound() - memory needed to initialize a ZSTD_DStream
+ * @maxWindowSize: The maximum window size allowed for compressed frames.
+ *
+ * Return: A lower bound on the size of the workspace that is passed to
+ * ZSTD_initDStream() and ZSTD_initDStream_usingDDict().
+ */
+size_t ZSTD_DStreamWorkspaceBound(size_t maxWindowSize);
+
+/**
+ * struct ZSTD_DStream - the zstd streaming decompression context
+ */
+typedef struct ZSTD_DStream_s ZSTD_DStream;
+/*===== ZSTD_DStream management functions =====*/
+/**
+ * ZSTD_initDStream() - initialize a zstd streaming decompression context
+ * @maxWindowSize: The maximum window size allowed for compressed frames.
+ * @workspace: The workspace to emplace the context into. It must outlive
+ * the returned context.
+ * @workspaceSize: The size of workspace.
+ * Use ZSTD_DStreamWorkspaceBound(maxWindowSize) to determine
+ * how large the workspace must be.
+ *
+ * Return: The zstd streaming decompression context.
+ */
+ZSTD_DStream *ZSTD_initDStream(size_t maxWindowSize, void *workspace,
+ size_t workspaceSize);
+/**
+ * ZSTD_initDStream_usingDDict() - initialize streaming decompression context
+ * @maxWindowSize: The maximum window size allowed for compressed frames.
+ * @ddict: The digested dictionary to use for decompression.
+ * @workspace: The workspace to emplace the context into. It must outlive
+ * the returned context.
+ * @workspaceSize: The size of workspace.
+ * Use ZSTD_DStreamWorkspaceBound(maxWindowSize) to determine
+ * how large the workspace must be.
+ *
+ * Return: The zstd streaming decompression context.
+ */
+ZSTD_DStream *ZSTD_initDStream_usingDDict(size_t maxWindowSize,
+ const ZSTD_DDict *ddict, void *workspace, size_t workspaceSize);
+
+/*===== Streaming decompression functions =====*/
+/**
+ * ZSTD_resetDStream() - reset the context using parameters from creation
+ * @zds: The zstd streaming decompression context to reset.
+ *
+ * Resets the context using the parameters from creation. Skips dictionary
+ * loading, since it can be reused.
+ *
+ * Return: Zero or an error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_resetDStream(ZSTD_DStream *zds);
+/**
+ * ZSTD_decompressStream() - streaming decompress some of input into output
+ * @zds: The zstd streaming decompression context.
+ * @output: Destination buffer. `output.pos` is updated to indicate how much
+ * decompressed data was written.
+ * @input: Source buffer. `input.pos` is updated to indicate how much data was
+ * read. Note that it may not consume the entire input, in which case
+ * `input.pos < input.size`, and it's up to the caller to present
+ * remaining data again.
+ *
+ * The `input` and `output` buffers may be any size. Guaranteed to make some
+ * forward progress if `input` and `output` are not empty.
+ * ZSTD_decompressStream() will not consume the last byte of the frame until
+ * the entire frame is flushed.
+ *
+ * Return: Returns 0 iff a frame is completely decoded and fully flushed.
+ * Otherwise returns a hint for the number of bytes to use as the input
+ * for the next function call or an error, which can be checked using
+ * ZSTD_isError(). The size hint will never load more than the frame.
+ */
+size_t ZSTD_decompressStream(ZSTD_DStream *zds, ZSTD_outBuffer *output,
+ ZSTD_inBuffer *input);
+
+/**
+ * ZSTD_DStreamInSize() - recommended size for the input buffer
+ *
+ * Return: The recommended size for the input buffer.
+ */
+size_t ZSTD_DStreamInSize(void);
+/**
+ * ZSTD_DStreamOutSize() - recommended size for the output buffer
+ *
+ * When the output buffer is at least this large, it is guaranteed to be large
+ * enough to flush at least one complete decompressed block.
+ *
+ * Return: The recommended size for the output buffer.
+ */
+size_t ZSTD_DStreamOutSize(void);
+
+
+/* --- Constants ---*/
+#define ZSTD_MAGICNUMBER 0xFD2FB528 /* >= v0.8.0 */
+#define ZSTD_MAGIC_SKIPPABLE_START 0x184D2A50U
+
+#define ZSTD_CONTENTSIZE_UNKNOWN (0ULL - 1)
+#define ZSTD_CONTENTSIZE_ERROR (0ULL - 2)
+
+#define ZSTD_WINDOWLOG_MAX_32 27
+#define ZSTD_WINDOWLOG_MAX_64 27
+#define ZSTD_WINDOWLOG_MAX \
+ ((unsigned int)(sizeof(size_t) == 4 \
+ ? ZSTD_WINDOWLOG_MAX_32 \
+ : ZSTD_WINDOWLOG_MAX_64))
+#define ZSTD_WINDOWLOG_MIN 10
+#define ZSTD_HASHLOG_MAX ZSTD_WINDOWLOG_MAX
+#define ZSTD_HASHLOG_MIN 6
+#define ZSTD_CHAINLOG_MAX (ZSTD_WINDOWLOG_MAX+1)
+#define ZSTD_CHAINLOG_MIN ZSTD_HASHLOG_MIN
+#define ZSTD_HASHLOG3_MAX 17
+#define ZSTD_SEARCHLOG_MAX (ZSTD_WINDOWLOG_MAX-1)
+#define ZSTD_SEARCHLOG_MIN 1
+/* only for ZSTD_fast, other strategies are limited to 6 */
+#define ZSTD_SEARCHLENGTH_MAX 7
+/* only for ZSTD_btopt, other strategies are limited to 4 */
+#define ZSTD_SEARCHLENGTH_MIN 3
+#define ZSTD_TARGETLENGTH_MIN 4
+#define ZSTD_TARGETLENGTH_MAX 999
+
+/* for static allocation */
+#define ZSTD_FRAMEHEADERSIZE_MAX 18
+#define ZSTD_FRAMEHEADERSIZE_MIN 6
+static const size_t ZSTD_frameHeaderSize_prefix = 5;
+static const size_t ZSTD_frameHeaderSize_min = ZSTD_FRAMEHEADERSIZE_MIN;
+static const size_t ZSTD_frameHeaderSize_max = ZSTD_FRAMEHEADERSIZE_MAX;
+/* magic number + skippable frame length */
+static const size_t ZSTD_skippableHeaderSize = 8;
+
+
+/*-*************************************
+ * Compressed size functions
+ **************************************/
+
+/**
+ * ZSTD_findFrameCompressedSize() - returns the size of a compressed frame
+ * @src: Source buffer. It should point to the start of a zstd encoded frame
+ * or a skippable frame.
+ * @srcSize: The size of the source buffer. It must be at least as large as the
+ * size of the frame.
+ *
+ * Return: The compressed size of the frame pointed to by `src` or an error,
+ * which can be check with ZSTD_isError().
+ * Suitable to pass to ZSTD_decompress() or similar functions.
+ */
+size_t ZSTD_findFrameCompressedSize(const void *src, size_t srcSize);
+
+/*-*************************************
+ * Decompressed size functions
+ **************************************/
+/**
+ * ZSTD_getFrameContentSize() - returns the content size in a zstd frame header
+ * @src: It should point to the start of a zstd encoded frame.
+ * @srcSize: The size of the source buffer. It must be at least as large as the
+ * frame header. `ZSTD_frameHeaderSize_max` is always large enough.
+ *
+ * Return: The frame content size stored in the frame header if known.
+ * `ZSTD_CONTENTSIZE_UNKNOWN` if the content size isn't stored in the
+ * frame header. `ZSTD_CONTENTSIZE_ERROR` on invalid input.
+ */
+unsigned long long ZSTD_getFrameContentSize(const void *src, size_t srcSize);
+
+/**
+ * ZSTD_findDecompressedSize() - returns decompressed size of a series of frames
+ * @src: It should point to the start of a series of zstd encoded and/or
+ * skippable frames.
+ * @srcSize: The exact size of the series of frames.
+ *
+ * If any zstd encoded frame in the series doesn't have the frame content size
+ * set, `ZSTD_CONTENTSIZE_UNKNOWN` is returned. But frame content size is always
+ * set when using ZSTD_compress(). The decompressed size can be very large.
+ * If the source is untrusted, the decompressed size could be wrong or
+ * intentionally modified. Always ensure the result fits within the
+ * application's authorized limits. ZSTD_findDecompressedSize() handles multiple
+ * frames, and so it must traverse the input to read each frame header. This is
+ * efficient as most of the data is skipped, however it does mean that all frame
+ * data must be present and valid.
+ *
+ * Return: Decompressed size of all the data contained in the frames if known.
+ * `ZSTD_CONTENTSIZE_UNKNOWN` if the decompressed size is unknown.
+ * `ZSTD_CONTENTSIZE_ERROR` if an error occurred.
+ */
+unsigned long long ZSTD_findDecompressedSize(const void *src, size_t srcSize);
+
+/*-*************************************
+ * Advanced compression functions
+ **************************************/
+/**
+ * ZSTD_checkCParams() - ensure parameter values remain within authorized range
+ * @cParams: The zstd compression parameters.
+ *
+ * Return: Zero or an error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_checkCParams(ZSTD_compressionParameters cParams);
+
+/**
+ * ZSTD_adjustCParams() - optimize parameters for a given srcSize and dictSize
+ * @srcSize: Optionally the estimated source size, or zero if unknown.
+ * @dictSize: Optionally the estimated dictionary size, or zero if unknown.
+ *
+ * Return: The optimized parameters.
+ */
+ZSTD_compressionParameters ZSTD_adjustCParams(
+ ZSTD_compressionParameters cParams, unsigned long long srcSize,
+ size_t dictSize);
+
+/*--- Advanced decompression functions ---*/
+
+/**
+ * ZSTD_isFrame() - returns true iff the buffer starts with a valid frame
+ * @buffer: The source buffer to check.
+ * @size: The size of the source buffer, must be at least 4 bytes.
+ *
+ * Return: True iff the buffer starts with a zstd or skippable frame identifier.
+ */
+unsigned int ZSTD_isFrame(const void *buffer, size_t size);
+
+/**
+ * ZSTD_getDictID_fromDict() - returns the dictionary id stored in a dictionary
+ * @dict: The dictionary buffer.
+ * @dictSize: The size of the dictionary buffer.
+ *
+ * Return: The dictionary id stored within the dictionary or 0 if the
+ * dictionary is not a zstd dictionary. If it returns 0 the
+ * dictionary can still be loaded as a content-only dictionary.
+ */
+unsigned int ZSTD_getDictID_fromDict(const void *dict, size_t dictSize);
+
+/**
+ * ZSTD_getDictID_fromDDict() - returns the dictionary id stored in a ZSTD_DDict
+ * @ddict: The ddict to find the id of.
+ *
+ * Return: The dictionary id stored within `ddict` or 0 if the dictionary is not
+ * a zstd dictionary. If it returns 0 `ddict` will be loaded as a
+ * content-only dictionary.
+ */
+unsigned int ZSTD_getDictID_fromDDict(const ZSTD_DDict *ddict);
+
+/**
+ * ZSTD_getDictID_fromFrame() - returns the dictionary id stored in a zstd frame
+ * @src: Source buffer. It must be a zstd encoded frame.
+ * @srcSize: The size of the source buffer. It must be at least as large as the
+ * frame header. `ZSTD_frameHeaderSize_max` is always large enough.
+ *
+ * Return: The dictionary id required to decompress the frame stored within
+ * `src` or 0 if the dictionary id could not be decoded. It can return
+ * 0 if the frame does not require a dictionary, the dictionary id
+ * wasn't stored in the frame, `src` is not a zstd frame, or `srcSize`
+ * is too small.
+ */
+unsigned int ZSTD_getDictID_fromFrame(const void *src, size_t srcSize);
+
+/**
+ * struct ZSTD_frameParams - zstd frame parameters stored in the frame header
+ * @frameContentSize: The frame content size, or 0 if not present.
+ * @windowSize: The window size, or 0 if the frame is a skippable frame.
+ * @dictID: The dictionary id, or 0 if not present.
+ * @checksumFlag: Whether a checksum was used.
+ */
+typedef struct {
+ unsigned long long frameContentSize;
+ unsigned int windowSize;
+ unsigned int dictID;
+ unsigned int checksumFlag;
+} ZSTD_frameParams;
+
+/**
+ * ZSTD_getFrameParams() - extracts parameters from a zstd or skippable frame
+ * @fparamsPtr: On success the frame parameters are written here.
+ * @src: The source buffer. It must point to a zstd or skippable frame.
+ * @srcSize: The size of the source buffer. `ZSTD_frameHeaderSize_max` is
+ * always large enough to succeed.
+ *
+ * Return: 0 on success. If more data is required it returns how many bytes
+ * must be provided to make forward progress. Otherwise it returns
+ * an error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_getFrameParams(ZSTD_frameParams *fparamsPtr, const void *src,
+ size_t srcSize);
+
+/*-*****************************************************************************
+ * Buffer-less and synchronous inner streaming functions
+ *
+ * This is an advanced API, giving full control over buffer management, for
+ * users which need direct control over memory.
+ * But it's also a complex one, with many restrictions (documented below).
+ * Prefer using normal streaming API for an easier experience
+ ******************************************************************************/
+
+/*-*****************************************************************************
+ * Buffer-less streaming compression (synchronous mode)
+ *
+ * A ZSTD_CCtx object is required to track streaming operations.
+ * Use ZSTD_initCCtx() to initialize a context.
+ * ZSTD_CCtx object can be re-used multiple times within successive compression
+ * operations.
+ *
+ * Start by initializing a context.
+ * Use ZSTD_compressBegin(), or ZSTD_compressBegin_usingDict() for dictionary
+ * compression,
+ * or ZSTD_compressBegin_advanced(), for finer parameter control.
+ * It's also possible to duplicate a reference context which has already been
+ * initialized, using ZSTD_copyCCtx()
+ *
+ * Then, consume your input using ZSTD_compressContinue().
+ * There are some important considerations to keep in mind when using this
+ * advanced function :
+ * - ZSTD_compressContinue() has no internal buffer. It uses externally provided
+ * buffer only.
+ * - Interface is synchronous : input is consumed entirely and produce 1+
+ * (or more) compressed blocks.
+ * - Caller must ensure there is enough space in `dst` to store compressed data
+ * under worst case scenario. Worst case evaluation is provided by
+ * ZSTD_compressBound().
+ * ZSTD_compressContinue() doesn't guarantee recover after a failed
+ * compression.
+ * - ZSTD_compressContinue() presumes prior input ***is still accessible and
+ * unmodified*** (up to maximum distance size, see WindowLog).
+ * It remembers all previous contiguous blocks, plus one separated memory
+ * segment (which can itself consists of multiple contiguous blocks)
+ * - ZSTD_compressContinue() detects that prior input has been overwritten when
+ * `src` buffer overlaps. In which case, it will "discard" the relevant memory
+ * section from its history.
+ *
+ * Finish a frame with ZSTD_compressEnd(), which will write the last block(s)
+ * and optional checksum. It's possible to use srcSize==0, in which case, it
+ * will write a final empty block to end the frame. Without last block mark,
+ * frames will be considered unfinished (corrupted) by decoders.
+ *
+ * `ZSTD_CCtx` object can be re-used (ZSTD_compressBegin()) to compress some new
+ * frame.
+ ******************************************************************************/
+
+/*===== Buffer-less streaming compression functions =====*/
+size_t ZSTD_compressBegin(ZSTD_CCtx *cctx, int compressionLevel);
+size_t ZSTD_compressBegin_usingDict(ZSTD_CCtx *cctx, const void *dict,
+ size_t dictSize, int compressionLevel);
+size_t ZSTD_compressBegin_advanced(ZSTD_CCtx *cctx, const void *dict,
+ size_t dictSize, ZSTD_parameters params,
+ unsigned long long pledgedSrcSize);
+size_t ZSTD_copyCCtx(ZSTD_CCtx *cctx, const ZSTD_CCtx *preparedCCtx,
+ unsigned long long pledgedSrcSize);
+size_t ZSTD_compressBegin_usingCDict(ZSTD_CCtx *cctx, const ZSTD_CDict *cdict,
+ unsigned long long pledgedSrcSize);
+size_t ZSTD_compressContinue(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize);
+size_t ZSTD_compressEnd(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize);
+
+
+
+/*-*****************************************************************************
+ * Buffer-less streaming decompression (synchronous mode)
+ *
+ * A ZSTD_DCtx object is required to track streaming operations.
+ * Use ZSTD_initDCtx() to initialize a context.
+ * A ZSTD_DCtx object can be re-used multiple times.
+ *
+ * First typical operation is to retrieve frame parameters, using
+ * ZSTD_getFrameParams(). It fills a ZSTD_frameParams structure which provide
+ * important information to correctly decode the frame, such as the minimum
+ * rolling buffer size to allocate to decompress data (`windowSize`), and the
+ * dictionary ID used.
+ * Note: content size is optional, it may not be present. 0 means unknown.
+ * Note that these values could be wrong, either because of data malformation,
+ * or because an attacker is spoofing deliberate false information. As a
+ * consequence, check that values remain within valid application range,
+ * especially `windowSize`, before allocation. Each application can set its own
+ * limit, depending on local restrictions. For extended interoperability, it is
+ * recommended to support at least 8 MB.
+ * Frame parameters are extracted from the beginning of the compressed frame.
+ * Data fragment must be large enough to ensure successful decoding, typically
+ * `ZSTD_frameHeaderSize_max` bytes.
+ * Result: 0: successful decoding, the `ZSTD_frameParams` structure is filled.
+ * >0: `srcSize` is too small, provide at least this many bytes.
+ * errorCode, which can be tested using ZSTD_isError().
+ *
+ * Start decompression, with ZSTD_decompressBegin() or
+ * ZSTD_decompressBegin_usingDict(). Alternatively, you can copy a prepared
+ * context, using ZSTD_copyDCtx().
+ *
+ * Then use ZSTD_nextSrcSizeToDecompress() and ZSTD_decompressContinue()
+ * alternatively.
+ * ZSTD_nextSrcSizeToDecompress() tells how many bytes to provide as 'srcSize'
+ * to ZSTD_decompressContinue().
+ * ZSTD_decompressContinue() requires this _exact_ amount of bytes, or it will
+ * fail.
+ *
+ * The result of ZSTD_decompressContinue() is the number of bytes regenerated
+ * within 'dst' (necessarily <= dstCapacity). It can be zero, which is not an
+ * error; it just means ZSTD_decompressContinue() has decoded some metadata
+ * item. It can also be an error code, which can be tested with ZSTD_isError().
+ *
+ * ZSTD_decompressContinue() needs previous data blocks during decompression, up
+ * to `windowSize`. They should preferably be located contiguously, prior to
+ * current block. Alternatively, a round buffer of sufficient size is also
+ * possible. Sufficient size is determined by frame parameters.
+ * ZSTD_decompressContinue() is very sensitive to contiguity, if 2 blocks don't
+ * follow each other, make sure that either the compressor breaks contiguity at
+ * the same place, or that previous contiguous segment is large enough to
+ * properly handle maximum back-reference.
+ *
+ * A frame is fully decoded when ZSTD_nextSrcSizeToDecompress() returns zero.
+ * Context can then be reset to start a new decompression.
+ *
+ * Note: it's possible to know if next input to present is a header or a block,
+ * using ZSTD_nextInputType(). This information is not required to properly
+ * decode a frame.
+ *
+ * == Special case: skippable frames ==
+ *
+ * Skippable frames allow integration of user-defined data into a flow of
+ * concatenated frames. Skippable frames will be ignored (skipped) by a
+ * decompressor. The format of skippable frames is as follows:
+ * a) Skippable frame ID - 4 Bytes, Little endian format, any value from
+ * 0x184D2A50 to 0x184D2A5F
+ * b) Frame Size - 4 Bytes, Little endian format, unsigned 32-bits
+ * c) Frame Content - any content (User Data) of length equal to Frame Size
+ * For skippable frames ZSTD_decompressContinue() always returns 0.
+ * For skippable frames ZSTD_getFrameParams() returns fparamsPtr->windowLog==0
+ * what means that a frame is skippable.
+ * Note: If fparamsPtr->frameContentSize==0, it is ambiguous: the frame might
+ * actually be a zstd encoded frame with no content. For purposes of
+ * decompression, it is valid in both cases to skip the frame using
+ * ZSTD_findFrameCompressedSize() to find its size in bytes.
+ * It also returns frame size as fparamsPtr->frameContentSize.
+ ******************************************************************************/
+
+/*===== Buffer-less streaming decompression functions =====*/
+size_t ZSTD_decompressBegin(ZSTD_DCtx *dctx);
+size_t ZSTD_decompressBegin_usingDict(ZSTD_DCtx *dctx, const void *dict,
+ size_t dictSize);
+void ZSTD_copyDCtx(ZSTD_DCtx *dctx, const ZSTD_DCtx *preparedDCtx);
+size_t ZSTD_nextSrcSizeToDecompress(ZSTD_DCtx *dctx);
+size_t ZSTD_decompressContinue(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize);
+typedef enum {
+ ZSTDnit_frameHeader,
+ ZSTDnit_blockHeader,
+ ZSTDnit_block,
+ ZSTDnit_lastBlock,
+ ZSTDnit_checksum,
+ ZSTDnit_skippableFrame
+} ZSTD_nextInputType_e;
+ZSTD_nextInputType_e ZSTD_nextInputType(ZSTD_DCtx *dctx);
+
+/*-*****************************************************************************
+ * Block functions
+ *
+ * Block functions produce and decode raw zstd blocks, without frame metadata.
+ * Frame metadata cost is typically ~18 bytes, which can be non-negligible for
+ * very small blocks (< 100 bytes). User will have to take in charge required
+ * information to regenerate data, such as compressed and content sizes.
+ *
+ * A few rules to respect:
+ * - Compressing and decompressing require a context structure
+ * + Use ZSTD_initCCtx() and ZSTD_initDCtx()
+ * - It is necessary to init context before starting
+ * + compression : ZSTD_compressBegin()
+ * + decompression : ZSTD_decompressBegin()
+ * + variants _usingDict() are also allowed
+ * + copyCCtx() and copyDCtx() work too
+ * - Block size is limited, it must be <= ZSTD_getBlockSizeMax()
+ * + If you need to compress more, cut data into multiple blocks
+ * + Consider using the regular ZSTD_compress() instead, as frame metadata
+ * costs become negligible when source size is large.
+ * - When a block is considered not compressible enough, ZSTD_compressBlock()
+ * result will be zero. In which case, nothing is produced into `dst`.
+ * + User must test for such outcome and deal directly with uncompressed data
+ * + ZSTD_decompressBlock() doesn't accept uncompressed data as input!!!
+ * + In case of multiple successive blocks, decoder must be informed of
+ * uncompressed block existence to follow proper history. Use
+ * ZSTD_insertBlock() in such a case.
+ ******************************************************************************/
+
+/* Define for static allocation */
+#define ZSTD_BLOCKSIZE_ABSOLUTEMAX (128 * 1024)
+/*===== Raw zstd block functions =====*/
+size_t ZSTD_getBlockSizeMax(ZSTD_CCtx *cctx);
+size_t ZSTD_compressBlock(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize);
+size_t ZSTD_decompressBlock(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity,
+ const void *src, size_t srcSize);
+size_t ZSTD_insertBlock(ZSTD_DCtx *dctx, const void *blockStart,
+ size_t blockSize);
+
+#endif /* ZSTD_H */
#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
#define REVID_MINOR(spridr) (spridr & 0x000000FF)
#else
#define SPCR_COREPR 0x00300000
#define SPCR_COREPR_SHIFT (31-11)
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
/* SPCR bits - MPC8349 specific */
/* TSEC1 data priority */
#define SPCR_TSEC1DP 0x00003000
#define SPCR_TSEC2EP 0x00000003
#define SPCR_TSEC2EP_SHIFT (31-31)
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
-/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
+/* SPCR bits - MPC8308, MPC831x and MPC837X specific */
/* TSEC data priority */
#define SPCR_TSECDP 0x00003000
#define SPCR_TSECDP_SHIFT (31-19)
/* SICRL/H - System I/O Configuration Register Low/High
*/
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
/* SICRL bits - MPC8349 specific */
#define SICRL_LDP_A 0x80000000
#define SICRL_USB1 0x40000000
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC8360)
+#elif defined(CONFIG_ARCH_MPC8360)
/* SICRL bits - MPC8360 specific */
#define SICRL_LDP_A 0xC0000000
#define SICRL_LCLK_1 0x10000000
#define SICRH_UC2E1OBI 0x00000002
#define SICRH_UC2E2OBI 0x00000001
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
/* SICRL bits - MPC832x specific */
#define SICRL_LDP_LCS_A 0x80000000
#define SICRL_IRQ_CKS 0x20000000
#define SICRL_URT_CTPR 0x06000000
#define SICRL_IRQ_CTPR 0x00C00000
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
/* SICRL bits - MPC8313 specific */
#define SICRL_LBC 0x30000000
#define SICRL_UART 0x0C000000
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8315)
/* SICRL bits - MPC8315 specific */
#define SICRL_DMA_CH0 0xc0000000
#define SICRL_DMA_SPI 0x30000000
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC837x)
-/* SICRL bits - MPC837x specific */
+#elif defined(CONFIG_ARCH_MPC837X)
+/* SICRL bits - MPC837X specific */
#define SICRL_USB_A 0xC0000000
#define SICRL_USB_B 0x30000000
#define SICRL_USB_B_SD 0x20000000
#define SICRL_LDP_A 0x00000002
#define SICRL_LDP_B 0x00000001
-/* SICRH bits - MPC837x specific */
+/* SICRH bits - MPC837X specific */
#define SICRH_DDR 0x80000000
#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
#define SICRH_SPI 0x00000003
#define SICRH_SPI_SD 0x00000001
-#elif defined(CONFIG_MPC8308)
+#elif defined(CONFIG_ARCH_MPC8308)
/* SICRL bits - MPC8308 specific */
#define SICRL_SPI_PF0 (0 << 28)
#define SICRL_SPI_PF1 (1 << 28)
#define SICRH_TSOBI2_V3P3 (0 << 0)
#define SICRH_TSOBI2_V2P5 (1 << 0)
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
/* SICR_1 */
#define SICR_1_UART1_UART1S (0 << (30-2))
#define SICR_1_UART1_UART1RTS (1 << (30-2))
#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
#define HRCWL_CORE_TO_CSB_3X1 0x00060000
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X)
#define HRCWL_CEVCOD 0x000000C0
#define HRCWL_CEVCOD_SHIFT 6
#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_2 0x00000000
#define HRCWL_SVCOD_DIV_8 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC837X)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_4 0x00000000
#define HRCWL_SVCOD_DIV_8 0x10000000
#define HRCWL_SVCOD_DIV_2 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
#define HRCWL_CEVCOD 0x000000C0
#define HRCWL_CEVCOD_SHIFT 6
#define HRCWH_PCI_HOST_SHIFT 31
#define HRCWH_PCI_AGENT 0x00000000
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_32_BIT_PCI 0x00000000
#define HRCWH_64_BIT_PCI 0x40000000
#endif
#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
-#elif defined(CONFIG_MPC8360)
+#elif defined(CONFIG_ARCH_MPC8360)
#define HRCWH_PCICKDRV_DISABLE 0x00000000
#define HRCWH_PCICKDRV_ENABLE 0x10000000
#endif
#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
#define HRCWH_ROM_LOC_PCI1 0x00100000
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
-#if defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC837X)
#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
#define HRCWH_TSEC2M_IN_SGMII 0x00001800
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_TSEC1M_IN_RGMII 0x00000000
#define HRCWH_TSEC1M_IN_RTBI 0x00004000
#define HRCWH_TSEC1M_IN_GMII 0x00008000
#define HRCWH_TSEC2M_IN_TBI 0x00003000
#endif
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
#endif
/*
* RSR - Reset Status Register
*/
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
#else
#define SCCR_PCICM 0x00010000
#define SCCR_PCICM_SHIFT 16
-#if defined(CONFIG_MPC834x)
-/* SCCR bits - MPC834x specific */
+#if defined(CONFIG_ARCH_MPC834X)
+/* SCCR bits - MPC834X specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
#define SCCR_USBCM_2 0x00A00000
#define SCCR_USBCM_3 0x00F00000
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
/* TSEC1 bits are for TSEC2 as well */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
/* SCCR bits - MPC8315/MPC8308 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TDMCM_2 0x00000020
#define SCCR_TDMCM_3 0x00000030
-#elif defined(CONFIG_MPC837x)
-/* SCCR bits - MPC837x specific */
+#elif defined(CONFIG_ARCH_MPC837X)
+/* SCCR bits - MPC837X specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
/* SCCR bits - MPC8309 specific */
#define SCCR_SDHCCM 0x0c000000
#define SCCR_SDHCCM_SHIFT 26
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
-#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
#define CSCONFIG_ODT_WR_ALL 0x00040000
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
#define CSCONFIG_ODT_RD_CFG 0x00400000
#define CSCONFIG_ODT_WR_CFG 0x00040000
-#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_DBW_16 0x00100000
#define SDRAM_CFG_DBW_32 0x00080000
#else
#define SDRAM_CFG_32_BE 0x00080000
#endif
-#if !defined(CONFIG_MPC8308)
+#if !defined(CONFIG_ARCH_MPC8308)
#define SDRAM_CFG_8_BE 0x00040000
#endif
#define SDRAM_CFG_NCAP 0x00020000
/* Returns HDA config info if Azalia V1CTL enabled, -ENOENT if not */
PCH_REQ_HDA_CONFIG,
+ /* Fills out a struct pch_pmbase_info if available */
+ PCH_REQ_PMBASE_INFO,
+
PCH_REQ_TEST1, /* Test requests for sandbox driver */
PCH_REQ_TEST2,
PCH_REQ_TEST3,
PCH_REQ_COUNT, /* Number of ioctrls supported */
};
+/**
+ * struct pch_pmbase_info - Information filled in by PCH_REQ_PMBASE_INFO
+ *
+ * @pmbase: IO address of power-management controller
+ * @gpio0_en_ofs: Offset of GPIO0 enable register
+ * @pm1_sts_ofs: Offset of status register
+ * @pm1_cnt_ofs: Offset of control register
+ */
+struct pch_pmbase_info {
+ u16 base;
+ u8 gpio0_en_ofs;
+ u8 pm1_sts_ofs;
+ u8 pm1_cnt_ofs;
+};
+
/**
* struct pch_ops - Operations for the Platform Controller Hub
*
extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
-#ifdef CONFIG_NR_DRAM_BANKS
-#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7)
-#else
-#define MAX_PCI_REGIONS 7
-#endif
+#define MAX_PCI_REGIONS 7
#define INDIRECT_TYPE_NO_PCIE_LINK 1
int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
u16 val);
+
+ /* Phy specific driver override for reading a MMD register */
+ int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
+
+ /* Phy specific driver override for writing a MMD register */
+ int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
+ u16 val);
+
struct list_head list;
};
return bus->write(bus, phydev->addr, devad, regnum, val);
}
+static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ /* Write the desired MMD Devad */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
+
+ /* Write the desired MMD register address */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
+
+ /* Select the Function : DATA with no post increment */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
+ (devad | MII_MMD_CTRL_NOINCR));
+}
+
+static inline int phy_read_mmd(struct phy_device *phydev, int devad,
+ int regnum)
+{
+ struct phy_driver *drv = phydev->drv;
+
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ /* driver-specific access */
+ if (drv->read_mmd)
+ return drv->read_mmd(phydev, devad, regnum);
+
+ /* direct C45 / C22 access */
+ if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
+ devad == MDIO_DEVAD_NONE || !devad)
+ return phy_read(phydev, devad, regnum);
+
+ /* indirect C22 access */
+ phy_mmd_start_indirect(phydev, devad, regnum);
+
+ /* Read the content of the MMD's selected register */
+ return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
+}
+
+static inline int phy_write_mmd(struct phy_device *phydev, int devad,
+ int regnum, u16 val)
+{
+ struct phy_driver *drv = phydev->drv;
+
+ if (regnum > (u16)~0 || devad > 32)
+ return -EINVAL;
+
+ /* driver-specific access */
+ if (drv->write_mmd)
+ return drv->write_mmd(phydev, devad, regnum, val);
+
+ /* direct C45 / C22 access */
+ if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
+ devad == MDIO_DEVAD_NONE || !devad)
+ return phy_write(phydev, devad, regnum, val);
+
+ /* indirect C22 access */
+ phy_mmd_start_indirect(phydev, devad, regnum);
+
+ /* Write the data into MMD's selected register */
+ return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
+}
+
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
#define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR
#else
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
#include <linux/immap_qe.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
#ifndef _RESET_H
#define _RESET_H
+#include <dm/ofnode.h>
#include <linux/errno.h>
/**
int reset_get_by_index(struct udevice *dev, int index,
struct reset_ctl *reset_ctl);
+/**
+ * reset_get_by_index_nodev - Get/request a reset signal by integer index
+ * without a device.
+ *
+ * This is a version of reset_get_by_index() that does not use a device.
+ *
+ * @node: The client ofnode.
+ * @index: The index of the reset signal to request, within the client's
+ * list of reset signals.
+ * @reset_ctl A pointer to a reset control struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_index_nodev(ofnode node, int index,
+ struct reset_ctl *reset_ctl);
+
/**
* reset_get_bulk - Get/request all reset signals of a device.
*
*/
unsigned long rtc_mktime(const struct rtc_time *time);
+/**
+ * rtc_month_days() - The number of days in the month
+ *
+ * @month: month (January = 0)
+ * @year: year (4 digits)
+ */
+int rtc_month_days(unsigned int month, unsigned int year);
+
#endif /* _RTC_H_ */
/* 55-57 reserved */
#define SDHCI_ADMA_ADDRESS 0x58
+#define SDHCI_ADMA_ADDRESS_HI 0x5c
/* 60-FB reserved */
void (*set_delay)(struct sdhci_host *host);
};
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+#define ADMA_MAX_LEN 65532
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+#define ADMA_DESC_LEN 16
+#else
+#define ADMA_DESC_LEN 8
+#endif
+#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
+ MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
+
+#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
+
+/* Decriptor table defines */
+#define ADMA_DESC_ATTR_VALID BIT(0)
+#define ADMA_DESC_ATTR_END BIT(1)
+#define ADMA_DESC_ATTR_INT BIT(2)
+#define ADMA_DESC_ATTR_ACT1 BIT(4)
+#define ADMA_DESC_ATTR_ACT2 BIT(5)
+
+#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
+#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
+
+struct sdhci_adma_desc {
+ u8 attr;
+ u8 reserved;
+ u16 len;
+ u32 addr_lo;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ u32 addr_hi;
+#endif
+} __packed;
+#endif
struct sdhci_host {
const char *name;
void *ioaddr;
uint voltages;
struct mmc_config cfg;
+ dma_addr_t start_addr;
+ int flags;
+#define USE_SDMA (0x1 << 0)
+#define USE_ADMA (0x1 << 1)
+#define USE_ADMA64 (0x1 << 2)
+#define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64)
+ dma_addr_t adma_addr;
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+ struct sdhci_adma_desc *adma_desc_table;
+ uint desc_slot;
+#endif
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
u8 os;
uintptr_t load_addr;
uintptr_t entry_point;
-#if CONFIG_IS_ENABLED(LOAD_FIT)
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
void *fdt_addr;
#endif
u32 boot_device;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Dummy file to allow libraries linked with U-Boot to include stdint.h without
+ * getting the system version.
+ *
+ * U-Boot uses linux types (linux/types.h) so does not make use of stdint.h
+ */
#define _TIME_H
#include <linux/typecheck.h>
+#include <linux/types.h>
unsigned long get_timer(unsigned long base);
*/
void timer_test_add_offset(unsigned long offset);
+/**
+ * usec_to_tick() - convert microseconds to clock ticks
+ *
+ * @usec: duration in microseconds
+ * Return: duration in clock ticks
+ */
+uint64_t usec_to_tick(unsigned long usec);
+
/*
* These inlines deal with timer wrapping correctly. You are
* strongly encouraged to use them
#if defined(CONFIG_MPC83xx)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
#else
#define CONFIG_SYS_FSL_USB2_ADDR 0
#ifndef __UUID_H__
#define __UUID_H__
+#include <linux/bitops.h>
+
/* This is structure is in big-endian */
struct uuid {
unsigned int time_low;
unsigned char node[6];
} __packed;
-enum {
- UUID_STR_FORMAT_STD,
- UUID_STR_FORMAT_GUID
-};
+/* Bits of a bitmask specifying the output format for GUIDs */
+#define UUID_STR_FORMAT_STD 0
+#define UUID_STR_FORMAT_GUID BIT(0)
+#define UUID_STR_UPPER_CASE BIT(1)
#define UUID_STR_LEN 36
#define UUID_BIN_LEN sizeof(struct uuid)
*/
int vidconsole_put_char(struct udevice *dev, char ch);
+/**
+ * vidconsole_put_string() - Output a string to the current console position
+ *
+ * Outputs a string to the console and advances the cursor. This function
+ * handles wrapping to new lines and scrolling the console. Special
+ * characters are handled also: \n, \r, \b and \t.
+ *
+ * The device always starts with the cursor at position 0,0 (top left). It
+ * can be adjusted manually using vidconsole_position_cursor().
+ *
+ * @dev: Device to adjust
+ * @str: String to write
+ * @return 0 if OK, -ve on error
+ */
+int vidconsole_put_string(struct udevice *dev, const char *str);
+
/**
* vidconsole_position_cursor() - Move the text cursor
*
config CRC32C
bool
+config XXHASH
+ bool
+
endmenu
menu "Compression Support"
This enables support for LZO compression algorithm.r
config GZIP
- bool "Enable gzip decompression support for SPL build"
+ bool "Enable gzip decompression support"
select ZLIB
default y
help
help
This enables ZLIB compression lib.
+config ZSTD
+ bool "Enable Zstandard decompression support"
+ select XXHASH
+ help
+ This enables Zstandard decompression library.
+
config SPL_LZ4
bool "Enable LZ4 decompression support in SPL"
help
help
This enables compression lib for SPL boot.
+config SPL_ZSTD
+ bool "Enable Zstandard decompression support in SPL"
+ select XXHASH
+ help
+ This enables Zstandard decompression library in the SPL.
+
endmenu
config ERRNO_STR
obj-$(CONFIG_IMAGE_SPARSE) += image-sparse.o
obj-y += ldiv.o
obj-$(CONFIG_MD5) += md5.o
+obj-$(CONFIG_XXHASH) += xxhash.o
obj-y += net_utils.o
obj-$(CONFIG_PHYSMEM) += physmem.o
obj-y += rc4.o
obj-$(CONFIG_SHA256) += sha256.o
obj-$(CONFIG_$(SPL_)ZLIB) += zlib/
+obj-$(CONFIG_$(SPL_)ZSTD) += zstd/
obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o
obj-$(CONFIG_$(SPL_)LZO) += lzo/
obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
build_tag);
if (len > size - 3)
len = size - 3;
- strcpy(buf + len, "\n\n");
+ if (len < 0)
+ len = 0;
+ snprintf(buf + len, size - len, "\n\n");
return buf;
}
config EFI_LOADER
- bool "Support running EFI Applications in U-Boot"
+ bool "Support running UEFI applications"
depends on (ARM || X86 || RISCV || SANDBOX) && OF_LIBFDT
# We need EFI_STUB_64BIT to be set on x86_64 with EFI_STUB
depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
select REGEX
imply CFB_CONSOLE_ANSI
help
- Select this option if you want to run EFI applications (like grub2)
- on top of U-Boot. If this option is enabled, U-Boot will expose EFI
- interfaces to a loaded EFI application, enabling it to reuse U-Boot's
- device drivers.
+ Select this option if you want to run UEFI applications (like GNU
+ GRUB or iPXE) on top of U-Boot. If this option is enabled, U-Boot
+ will expose the UEFI API to a loaded application, enabling it to
+ reuse U-Boot's device drivers.
+
+if EFI_LOADER
+
+config EFI_GET_TIME
+ bool "GetTime() runtime service"
+ depends on DM_RTC
+ default y
+ help
+ Provide the GetTime() runtime service at boottime. This service
+ can be used by an EFI application to read the real time clock.
+
+config EFI_SET_TIME
+ bool "SetTime() runtime service"
+ depends on EFI_GET_TIME
+ default n
+ help
+ Provide the SetTime() runtime service at boottime. This service
+ can be used by an EFI application to adjust the real time clock.
+
+config EFI_DEVICE_PATH_TO_TEXT
+ bool "Device path to text protocol"
+ default y
+ help
+ The device path to text protocol converts device nodes and paths to
+ human readable strings.
+
+config EFI_LOADER_HII
+ bool "HII protocols"
+ default y
+ help
+ The Human Interface Infrastructure is a complicated framework that
+ allows UEFI applications to draw fancy menus and hook strings using
+ a translation framework.
+
+ U-Boot implements enough of its features to be able to run the UEFI
+ Shell, but not more than that.
+
+config EFI_UNICODE_COLLATION_PROTOCOL2
+ bool "Unicode collation protocol"
+ default y
+ help
+ The Unicode collation protocol is used for lexical comparisons. It is
+ required to run the UEFI shell.
+
+if EFI_UNICODE_COLLATION_PROTOCOL2
config EFI_UNICODE_CAPITALIZATION
bool "Support Unicode capitalization"
- depends on EFI_LOADER
default y
help
Select this option to enable correct handling of the capitalization of
set, only the the correct handling of the letters of the codepage
used by the FAT file system is ensured.
-config EFI_PLATFORM_LANG_CODES
- string "Language codes supported by firmware"
- depends on EFI_LOADER
- default "en-US"
+config EFI_UNICODE_COLLATION_PROTOCOL
+ bool "Deprecated version of the Unicode collation protocol"
+ default n
help
- This value is used to initialize the PlatformLangCodes variable. Its
- value is a semicolon (;) separated list of language codes in native
- RFC 4646 format, e.g. "en-US;de-DE". The first language code is used
- to initialize the PlatformLang variable.
+ In EFI 1.10 a version of the Unicode collation protocol using ISO
+ 639-2 language codes existed. This protocol is not part of the UEFI
+ specification any longer. Unfortunately it is required to run the
+ UEFI Self Certification Test (SCT) II, version 2.6, 2017.
+
+ Choose this option for testing only. It is bound to be removed.
+
+endif
config EFI_LOADER_BOUNCE_BUFFER
bool "EFI Applications use bounce buffers for DMA operations"
- depends on EFI_LOADER && ARM64
+ depends on ARM64
default n
help
Some hardware does not support DMA to full 64bit addresses. For this
hardware we can create a bounce buffer so that payloads don't have to
worry about platform details.
-config EFI_LOADER_HII
- bool "Expose HII protocols to EFI applications"
- depends on EFI_LOADER
- default y
+config EFI_PLATFORM_LANG_CODES
+ string "Language codes supported by firmware"
+ default "en-US"
help
- The Human Interface Infrastructure is a complicated framework that
- allows UEFI applications to draw fancy menus and hook strings using
- a translation framework.
+ This value is used to initialize the PlatformLangCodes variable. Its
+ value is a semicolon (;) separated list of language codes in native
+ RFC 4646 format, e.g. "en-US;de-DE". The first language code is used
+ to initialize the PlatformLang variable.
- U-Boot implements enough of its features to be able to run the UEFI
- Shell, but not more than that.
+endif
obj-y += efi_boottime.o
obj-y += efi_console.o
obj-y += efi_device_path.o
-obj-y += efi_device_path_to_text.o
+obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o
obj-y += efi_device_path_utilities.o
obj-y += efi_file.o
-obj-y += efi_hii.o efi_hii_config.o
+obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o efi_hii_config.o
obj-y += efi_image_loader.o
obj-y += efi_memory.o
obj-y += efi_root_node.o
obj-y += efi_runtime.o
obj-y += efi_setup.o
-obj-y += efi_unicode_collation.o
+obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += efi_unicode_collation.o
obj-y += efi_variable.o
obj-y += efi_watchdog.o
obj-$(CONFIG_LCD) += efi_gop.o
*/
unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data)
{
- unsigned long label_len, option_len;
+ unsigned long label_len;
unsigned long size;
u8 *p;
label_len = (u16_strlen(lo->label) + 1) * sizeof(u16);
- option_len = strlen((char *)lo->optional_data);
/* total size */
size = sizeof(lo->attributes);
size += sizeof(lo->file_path_length);
size += label_len;
size += lo->file_path_length;
- size += option_len + 1;
+ if (lo->optional_data)
+ size += (utf8_utf16_strlen((const char *)lo->optional_data)
+ + 1) * sizeof(u16);
p = malloc(size);
if (!p)
return 0;
memcpy(p, lo->file_path, lo->file_path_length);
p += lo->file_path_length;
- memcpy(p, lo->optional_data, option_len);
- p += option_len;
- *(char *)p = '\0';
-
+ if (lo->optional_data) {
+ utf8_utf16_strcpy((u16 **)&p, (const char *)lo->optional_data);
+ p += sizeof(u16); /* size of trailing \0 */
+ }
return size;
}
ret = EFI_CALL(efi_load_image(true, efi_root, lo.file_path,
NULL, 0, handle));
- if (ret != EFI_SUCCESS)
+ if (ret != EFI_SUCCESS) {
+ printf("Loading from Boot%04X '%ls' failed\n", n,
+ lo.label);
goto error;
+ }
attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS;
ret = EFI_CALL(efi_set_variable(
L"BootNext",
(efi_guid_t *)&efi_global_variable_guid,
- 0, 0, &bootnext));
+ EFI_VARIABLE_NON_VOLATILE, 0,
+ &bootnext));
/* load BootNext */
if (ret == EFI_SUCCESS) {
ret = try_load_entry(bootnext, handle);
if (ret == EFI_SUCCESS)
return ret;
+ printf("Loading from BootNext failed, falling back to BootOrder\n");
}
} else {
printf("Deleting BootNext failed\n");
#include <linux/libfdt_env.h>
#include <u-boot/crc.h>
#include <bootm.h>
+#include <pe.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
/* List of all events */
LIST_HEAD(efi_events);
+/* List of all events registered by RegisterProtocolNotify() */
+LIST_HEAD(efi_register_notify_events);
+
/* Handle of the currently executing image */
static efi_handle_t current_image;
/* Check TPL */
if (check_tpl && efi_tpl >= event->notify_tpl)
return;
+ event->is_queued = false;
EFI_CALL_VOID(event->notify_function(event,
event->notify_context));
+ } else {
+ event->is_queued = false;
}
- event->is_queued = false;
}
/**
if (evt->is_queued)
efi_queue_event(evt, check_tpl);
}
- } else if (!event->is_signaled) {
+ } else {
event->is_signaled = true;
if (event->type & EVT_NOTIFY_SIGNAL)
efi_queue_event(event, check_tpl);
EFI_ENTRY("0x%zx", new_tpl);
if (new_tpl < efi_tpl)
- debug("WARNING: new_tpl < current_tpl in %s\n", __func__);
+ EFI_PRINT("WARNING: new_tpl < current_tpl in %s\n", __func__);
efi_tpl = new_tpl;
if (efi_tpl > TPL_HIGH_LEVEL)
efi_tpl = TPL_HIGH_LEVEL;
EFI_ENTRY("0x%zx", old_tpl);
if (old_tpl > efi_tpl)
- debug("WARNING: old_tpl > current_tpl in %s\n", __func__);
+ EFI_PRINT("WARNING: old_tpl > current_tpl in %s\n", __func__);
efi_tpl = old_tpl;
if (efi_tpl > TPL_HIGH_LEVEL)
efi_tpl = TPL_HIGH_LEVEL;
}
/**
- * efi_add_handle() - add a new object to the object list
- * @obj: object to be added
+ * efi_add_handle() - add a new handle to the object list
*
- * The protocols list is initialized. The object handle is set.
+ * @handle: handle to be added
+ *
+ * The protocols list is initialized. The handle is added to the list of known
+ * UEFI objects.
*/
void efi_add_handle(efi_handle_t handle)
{
ret = efi_search_protocol(handle, protocol, &handler);
if (ret != EFI_SUCCESS)
return ret;
- if (guidcmp(handler->guid, protocol))
- return EFI_INVALID_PARAMETER;
if (handler->protocol_interface != protocol_interface)
- return EFI_INVALID_PARAMETER;
+ return EFI_NOT_FOUND;
list_del(&handler->link);
free(handler);
return EFI_SUCCESS;
}
if ((type & (EVT_NOTIFY_WAIT | EVT_NOTIFY_SIGNAL)) &&
- (is_valid_tpl(notify_tpl) != EFI_SUCCESS))
+ (!notify_function || is_valid_tpl(notify_tpl) != EFI_SUCCESS))
return EFI_INVALID_PARAMETER;
evt = calloc(1, sizeof(struct efi_event));
efi_guid_t *event_group,
struct efi_event **event)
{
+ efi_status_t ret;
+
EFI_ENTRY("%d, 0x%zx, %p, %p, %pUl", type, notify_tpl, notify_function,
notify_context, event_group);
- return EFI_EXIT(efi_create_event(type, notify_tpl, notify_function,
- notify_context, event_group, event));
+
+ /*
+ * The allowable input parameters are the same as in CreateEvent()
+ * except for the following two disallowed event types.
+ */
+ switch (type) {
+ case EVT_SIGNAL_EXIT_BOOT_SERVICES:
+ case EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE:
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ ret = efi_create_event(type, notify_tpl, notify_function,
+ notify_context, event_group, event);
+out:
+ return EFI_EXIT(ret);
}
/**
*/
static efi_status_t EFIAPI efi_close_event(struct efi_event *event)
{
+ struct efi_register_notify_event *item, *next;
+
EFI_ENTRY("%p", event);
if (efi_is_event(event) != EFI_SUCCESS)
return EFI_EXIT(EFI_INVALID_PARAMETER);
+
+ /* Remove protocol notify registrations for the event */
+ list_for_each_entry_safe(item, next, &efi_register_notify_events,
+ link) {
+ if (event == item->event) {
+ struct efi_protocol_notification *hitem, *hnext;
+
+ /* Remove signaled handles */
+ list_for_each_entry_safe(hitem, hnext, &item->handles,
+ link) {
+ list_del(&hitem->link);
+ free(hitem);
+ }
+ list_del(&item->link);
+ free(item);
+ }
+ }
+
list_del(&event->link);
free(event);
return EFI_EXIT(EFI_SUCCESS);
{
struct efi_object *efiobj;
+ if (!handle)
+ return NULL;
+
list_for_each_entry(efiobj, &efi_obj_list, link) {
if (efiobj == handle)
return efiobj;
}
-
return NULL;
}
struct efi_object *efiobj;
struct efi_handler *handler;
efi_status_t ret;
+ struct efi_register_notify_event *event;
efiobj = efi_search_obj(handle);
if (!efiobj)
handler->protocol_interface = protocol_interface;
INIT_LIST_HEAD(&handler->open_infos);
list_add_tail(&handler->link, &efiobj->protocols);
+
+ /* Notify registered events */
+ list_for_each_entry(event, &efi_register_notify_events, link) {
+ if (!guidcmp(protocol, &event->protocol)) {
+ struct efi_protocol_notification *notif;
+
+ notif = calloc(1, sizeof(*notif));
+ if (!notif) {
+ list_del(&handler->link);
+ free(handler);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ notif->handle = handle;
+ list_add_tail(¬if->link, &event->handles);
+ efi_signal_event(event->event, true);
+ }
+ }
+
if (!guidcmp(&efi_guid_device_path, protocol))
EFI_PRINT("installed device path '%pD'\n", protocol_interface);
return EFI_SUCCESS;
r = efi_create_handle(handle);
if (r != EFI_SUCCESS)
goto out;
- debug("%sEFI: new handle %p\n", indent_string(nesting_level),
- *handle);
+ EFI_PRINT("new handle %p\n", *handle);
} else {
- debug("%sEFI: handle %p\n", indent_string(nesting_level),
- *handle);
+ EFI_PRINT("handle %p\n", *handle);
}
/* Add new protocol */
r = efi_add_protocol(*handle, protocol, protocol_interface);
++count;
}
}
+ *number_of_drivers = 0;
+ if (!count) {
+ *driver_handle_buffer = NULL;
+ return EFI_SUCCESS;
+ }
/*
* Create buffer. In case of duplicate driver assignments the buffer
* will be too large. But that does not harm.
*/
- *number_of_drivers = 0;
*driver_handle_buffer = calloc(count, sizeof(efi_handle_t));
if (!*driver_handle_buffer)
return EFI_OUT_OF_RESOURCES;
&driver_handle_buffer);
if (ret != EFI_SUCCESS)
return ret;
-
+ if (!number_of_drivers)
+ return EFI_SUCCESS;
ret = EFI_NOT_FOUND;
while (number_of_drivers) {
r = EFI_CALL(efi_disconnect_controller(
goto out;
/* Disconnect controllers */
efi_disconnect_all_drivers(efiobj, protocol, NULL);
- if (!list_empty(&handler->open_infos)) {
- r = EFI_ACCESS_DENIED;
- goto out;
- }
/* Close protocol */
list_for_each_entry_safe(item, pos, &handler->open_infos, link) {
if (item->info.attributes ==
struct efi_event *event,
void **registration)
{
+ struct efi_register_notify_event *item;
+ efi_status_t ret = EFI_SUCCESS;
+
EFI_ENTRY("%pUl, %p, %p", protocol, event, registration);
- return EFI_EXIT(EFI_OUT_OF_RESOURCES);
+
+ if (!protocol || !event || !registration) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ item = calloc(1, sizeof(struct efi_register_notify_event));
+ if (!item) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto out;
+ }
+
+ item->event = event;
+ memcpy(&item->protocol, protocol, sizeof(efi_guid_t));
+ INIT_LIST_HEAD(&item->handles);
+
+ list_add_tail(&item->link, &efi_register_notify_events);
+
+ *registration = item;
+out:
+ return EFI_EXIT(ret);
}
/**
* Return: 0 if the handle implements the protocol
*/
static int efi_search(enum efi_locate_search_type search_type,
- const efi_guid_t *protocol, void *search_key,
- efi_handle_t handle)
+ const efi_guid_t *protocol, efi_handle_t handle)
{
efi_status_t ret;
switch (search_type) {
case ALL_HANDLES:
return 0;
- case BY_REGISTER_NOTIFY:
- /* TODO: RegisterProtocolNotify is not implemented yet */
- return -1;
case BY_PROTOCOL:
ret = efi_search_protocol(handle, protocol, NULL);
return (ret != EFI_SUCCESS);
}
}
+/**
+ * efi_check_register_notify_event() - check if registration key is valid
+ *
+ * Check that a pointer is a valid registration key as returned by
+ * RegisterProtocolNotify().
+ *
+ * @key: registration key
+ * Return: valid registration key or NULL
+ */
+static struct efi_register_notify_event *efi_check_register_notify_event
+ (void *key)
+{
+ struct efi_register_notify_event *event;
+
+ list_for_each_entry(event, &efi_register_notify_events, link) {
+ if (event == (struct efi_register_notify_event *)key)
+ return event;
+ }
+ return NULL;
+}
+
/**
* efi_locate_handle() - locate handles implementing a protocol
- * @search_type: selection criterion
- * @protocol: GUID of the protocol
- * @search_key: registration key
- * @buffer_size: size of the buffer to receive the handles in bytes
- * @buffer: buffer to receive the relevant handles
+ *
+ * @search_type: selection criterion
+ * @protocol: GUID of the protocol
+ * @search_key: registration key
+ * @buffer_size: size of the buffer to receive the handles in bytes
+ * @buffer: buffer to receive the relevant handles
*
* This function is meant for U-Boot internal calls. For the API implementation
* of the LocateHandle service see efi_locate_handle_ext.
{
struct efi_object *efiobj;
efi_uintn_t size = 0;
+ struct efi_register_notify_event *event;
+ struct efi_protocol_notification *handle = NULL;
/* Check parameters */
switch (search_type) {
case BY_REGISTER_NOTIFY:
if (!search_key)
return EFI_INVALID_PARAMETER;
- /* RegisterProtocolNotify is not implemented yet */
- return EFI_UNSUPPORTED;
+ /* Check that the registration key is valid */
+ event = efi_check_register_notify_event(search_key);
+ if (!event)
+ return EFI_INVALID_PARAMETER;
+ break;
case BY_PROTOCOL:
if (!protocol)
return EFI_INVALID_PARAMETER;
return EFI_INVALID_PARAMETER;
}
- /*
- * efi_locate_handle_buffer uses this function for
- * the calculation of the necessary buffer size.
- * So do not require a buffer for buffersize == 0.
- */
- if (!buffer_size || (*buffer_size && !buffer))
- return EFI_INVALID_PARAMETER;
-
/* Count how much space we need */
- list_for_each_entry(efiobj, &efi_obj_list, link) {
- if (!efi_search(search_type, protocol, search_key, efiobj))
- size += sizeof(void *);
+ if (search_type == BY_REGISTER_NOTIFY) {
+ if (list_empty(&event->handles))
+ return EFI_NOT_FOUND;
+ handle = list_first_entry(&event->handles,
+ struct efi_protocol_notification,
+ link);
+ efiobj = handle->handle;
+ size += sizeof(void *);
+ } else {
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ if (!efi_search(search_type, protocol, efiobj))
+ size += sizeof(void *);
+ }
+ if (size == 0)
+ return EFI_NOT_FOUND;
}
+ if (!buffer_size)
+ return EFI_INVALID_PARAMETER;
+
if (*buffer_size < size) {
*buffer_size = size;
return EFI_BUFFER_TOO_SMALL;
}
*buffer_size = size;
- if (size == 0)
- return EFI_NOT_FOUND;
+
+ /* The buffer size is sufficient but there is no buffer */
+ if (!buffer)
+ return EFI_INVALID_PARAMETER;
/* Then fill the array */
- list_for_each_entry(efiobj, &efi_obj_list, link) {
- if (!efi_search(search_type, protocol, search_key, efiobj))
- *buffer++ = efiobj;
+ if (search_type == BY_REGISTER_NOTIFY) {
+ *buffer = efiobj;
+ list_del(&handle->link);
+ } else {
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ if (!efi_search(search_type, protocol, efiobj))
+ *buffer++ = efiobj;
+ }
}
return EFI_SUCCESS;
free(info);
return EFI_OUT_OF_RESOURCES;
}
+ obj->header.type = EFI_OBJECT_TYPE_LOADED_IMAGE;
/* Add internal object to object list */
efi_add_handle(&obj->header);
EFI_ENTRY("%d, %p, %pD, %p, %zd, %p", boot_policy, parent_image,
file_path, source_buffer, source_size, image_handle);
- if (!image_handle || !parent_image) {
+ if (!image_handle || !efi_search_obj(parent_image)) {
ret = EFI_INVALID_PARAMETER;
goto error;
}
ret = EFI_NOT_FOUND;
goto error;
}
+ /* The parent image handle must refer to a loaded image */
+ if (!parent_image->type) {
+ ret = EFI_INVALID_PARAMETER;
+ goto error;
+ }
if (!source_buffer) {
ret = efi_load_image_from_path(file_path, &dest_buffer,
if (ret != EFI_SUCCESS)
goto error;
} else {
+ if (!source_size) {
+ ret = EFI_LOAD_ERROR;
+ goto error;
+ }
dest_buffer = source_buffer;
}
/* split file_path which contains both the device and file parts */
return EFI_EXIT(ret);
}
-/**
- * efi_unload_image() - unload an EFI image
- * @image_handle: handle of the image to be unloaded
- *
- * This function implements the UnloadImage service.
- *
- * See the Unified Extensible Firmware Interface (UEFI) specification for
- * details.
- *
- * Return: status code
- */
-efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle)
-{
- struct efi_object *efiobj;
-
- EFI_ENTRY("%p", image_handle);
- efiobj = efi_search_obj(image_handle);
- if (efiobj)
- list_del(&efiobj->link);
-
- return EFI_EXIT(EFI_SUCCESS);
-}
-
/**
* efi_exit_caches() - fix up caches for EFI payloads if necessary
*/
* Return: status code
*/
static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle,
- unsigned long map_key)
+ efi_uintn_t map_key)
{
struct efi_event *evt;
- EFI_ENTRY("%p, %ld", image_handle, map_key);
+ EFI_ENTRY("%p, %zx", image_handle, map_key);
/* Check that the caller has read the current memory map */
if (map_key != efi_memory_map_key)
static efi_status_t EFIAPI efi_get_next_monotonic_count(uint64_t *count)
{
static uint64_t mono;
+ efi_status_t ret;
EFI_ENTRY("%p", count);
+ if (!count) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
*count = mono++;
- return EFI_EXIT(EFI_SUCCESS);
+ ret = EFI_SUCCESS;
+out:
+ return EFI_EXIT(ret);
}
/**
*/
static efi_status_t EFIAPI efi_stall(unsigned long microseconds)
{
+ u64 end_tick;
+
EFI_ENTRY("%ld", microseconds);
- udelay(microseconds);
+
+ end_tick = get_ticks() + usec_to_tick(microseconds);
+ while (get_ticks() < end_tick)
+ efi_timer_check();
+
return EFI_EXIT(EFI_SUCCESS);
}
EFI_ENTRY("%p, %pUl, %p, %p", handle, protocol, agent_handle,
controller_handle);
- if (!agent_handle) {
+ if (!efi_search_obj(agent_handle) ||
+ (controller_handle && !efi_search_obj(controller_handle))) {
r = EFI_INVALID_PARAMETER;
goto out;
}
item->info.controller_handle == controller_handle) {
efi_delete_open_info(item);
r = EFI_SUCCESS;
- break;
}
}
out:
void *registration,
void **protocol_interface)
{
- struct list_head *lhandle;
+ struct efi_handler *handler;
efi_status_t ret;
+ struct efi_object *efiobj;
EFI_ENTRY("%pUl, %p, %p", protocol, registration, protocol_interface);
+ /*
+ * The UEFI spec explicitly requires a protocol even if a registration
+ * key is provided. This differs from the logic in LocateHandle().
+ */
if (!protocol || !protocol_interface)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- list_for_each(lhandle, &efi_obj_list) {
- struct efi_object *efiobj;
- struct efi_handler *handler;
-
- efiobj = list_entry(lhandle, struct efi_object, link);
+ if (registration) {
+ struct efi_register_notify_event *event;
+ struct efi_protocol_notification *handle;
+ event = efi_check_register_notify_event(registration);
+ if (!event)
+ return EFI_EXIT(EFI_INVALID_PARAMETER);
+ /*
+ * The UEFI spec requires to return EFI_NOT_FOUND if no
+ * protocol instance matches protocol and registration.
+ * So let's do the same for a mismatch between protocol and
+ * registration.
+ */
+ if (guidcmp(&event->protocol, protocol))
+ goto not_found;
+ if (list_empty(&event->handles))
+ goto not_found;
+ handle = list_first_entry(&event->handles,
+ struct efi_protocol_notification,
+ link);
+ efiobj = handle->handle;
+ list_del(&handle->link);
+ free(handle);
ret = efi_search_protocol(efiobj, protocol, &handler);
- if (ret == EFI_SUCCESS) {
- *protocol_interface = handler->protocol_interface;
- return EFI_EXIT(EFI_SUCCESS);
+ if (ret == EFI_SUCCESS)
+ goto found;
+ } else {
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ ret = efi_search_protocol(efiobj, protocol, &handler);
+ if (ret == EFI_SUCCESS)
+ goto found;
}
}
+not_found:
*protocol_interface = NULL;
-
return EFI_EXIT(EFI_NOT_FOUND);
+found:
+ *protocol_interface = handler->protocol_interface;
+ return EFI_EXIT(EFI_SUCCESS);
}
/**
EFI_ENTRY("%pUl, %p, %p", protocol, device_path, device);
- if (!protocol || !device_path || !*device_path || !device) {
+ if (!protocol || !device_path || !*device_path) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
/* Check if dp is a subpath of device_path */
if (memcmp(*device_path, dp, len_dp))
continue;
+ if (!device) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
*device = handles[i];
len_best = len_dp;
}
efi_va_list argptr;
const efi_guid_t *protocol;
void *protocol_interface;
+ efi_handle_t old_handle;
efi_status_t r = EFI_SUCCESS;
int i = 0;
if (!protocol)
break;
protocol_interface = efi_va_arg(argptr, void*);
+ /* Check that a device path has not been installed before */
+ if (!guidcmp(protocol, &efi_guid_device_path)) {
+ struct efi_device_path *dp = protocol_interface;
+
+ r = EFI_CALL(efi_locate_device_path(protocol, &dp,
+ &old_handle));
+ if (r == EFI_SUCCESS &&
+ dp->type == DEVICE_PATH_TYPE_END) {
+ EFI_PRINT("Path %pD already installed\n",
+ protocol_interface);
+ r = EFI_ALREADY_STARTED;
+ break;
+ }
+ }
r = EFI_CALL(efi_install_protocol_interface(
handle, protocol,
EFI_NATIVE_INTERFACE,
efi_uintn_t data_size,
u32 *crc32_p)
{
+ efi_status_t ret = EFI_SUCCESS;
+
EFI_ENTRY("%p, %zu", data, data_size);
+ if (!data || !data_size || !crc32_p) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
*crc32_p = crc32(0, data, data_size);
- return EFI_EXIT(EFI_SUCCESS);
+out:
+ return EFI_EXIT(ret);
}
/**
if ((attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) &&
(item->info.attributes == attributes))
return EFI_ALREADY_STARTED;
+ } else {
+ if (item->info.attributes &
+ EFI_OPEN_PROTOCOL_BY_DRIVER)
+ opened_by_driver = true;
}
if (item->info.attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE)
opened_exclusive = true;
}
/* Only one controller can open the protocol exclusively */
- if (opened_exclusive && attributes &
- (EFI_OPEN_PROTOCOL_EXCLUSIVE | EFI_OPEN_PROTOCOL_BY_DRIVER))
- return EFI_ACCESS_DENIED;
+ if (attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE) {
+ if (opened_exclusive)
+ return EFI_ACCESS_DENIED;
+ } else if (attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) {
+ if (opened_exclusive || opened_by_driver)
+ return EFI_ACCESS_DENIED;
+ }
/* Prepare exclusive opening */
if (attributes & EFI_OPEN_PROTOCOL_EXCLUSIVE) {
/* Try to disconnect controllers */
+disconnect_next:
+ opened_by_driver = false;
list_for_each_entry(item, &handler->open_infos, link) {
+ efi_status_t ret;
+
if (item->info.attributes ==
- EFI_OPEN_PROTOCOL_BY_DRIVER)
- EFI_CALL(efi_disconnect_controller(
+ EFI_OPEN_PROTOCOL_BY_DRIVER) {
+ ret = EFI_CALL(efi_disconnect_controller(
item->info.controller_handle,
item->info.agent_handle,
NULL));
+ if (ret == EFI_SUCCESS)
+ /*
+ * Child controllers may have been
+ * removed from the open_infos list. So
+ * let's restart the loop.
+ */
+ goto disconnect_next;
+ else
+ opened_by_driver = true;
+ }
}
- opened_by_driver = false;
- /* Check if all controllers are disconnected */
- list_for_each_entry(item, &handler->open_infos, link) {
- if (item->info.attributes & EFI_OPEN_PROTOCOL_BY_DRIVER)
- opened_by_driver = true;
- }
- /* Only one controller can be connected */
+ /* Only one driver can be connected */
if (opened_by_driver)
return EFI_ACCESS_DENIED;
}
/* Find existing entry */
list_for_each_entry(item, &handler->open_infos, link) {
if (item->info.agent_handle == agent_handle &&
- item->info.controller_handle == controller_handle)
+ item->info.controller_handle == controller_handle &&
+ item->info.attributes == attributes)
match = &item->info;
}
/* None found, create one */
}
r = efi_search_protocol(handle, protocol, &handler);
- if (r != EFI_SUCCESS)
+ switch (r) {
+ case EFI_SUCCESS:
+ break;
+ case EFI_NOT_FOUND:
+ r = EFI_UNSUPPORTED;
+ goto out;
+ default:
goto out;
+ }
r = efi_protocol_open(handler, protocol_interface, agent_handle,
controller_handle, attributes);
efi_is_direct_boot = false;
+ image_obj->exit_data_size = exit_data_size;
+ image_obj->exit_data = exit_data;
+
/* call the image! */
if (setjmp(&image_obj->exit_jmp)) {
/*
* missed out steps of EFI_CALL.
*/
assert(__efi_entry_check());
- debug("%sEFI: %lu returned by started image\n",
- __efi_nesting_dec(),
- (unsigned long)((uintptr_t)image_obj->exit_status &
- ~EFI_ERROR_MASK));
+ EFI_PRINT("%lu returned by started image\n",
+ (unsigned long)((uintptr_t)image_obj->exit_status &
+ ~EFI_ERROR_MASK));
current_image = parent_image;
return EFI_EXIT(image_obj->exit_status);
}
current_image = image_handle;
+ image_obj->header.type = EFI_OBJECT_TYPE_STARTED_IMAGE;
EFI_PRINT("Jumping into 0x%p\n", image_obj->entry);
ret = EFI_CALL(image_obj->entry(image_handle, &systab));
return EFI_CALL(systab.boottime->exit(image_handle, ret, 0, NULL));
}
+/**
+ * efi_delete_image() - delete loaded image from memory)
+ *
+ * @image_obj: handle of the loaded image
+ * @loaded_image_protocol: loaded image protocol
+ */
+static efi_status_t efi_delete_image
+ (struct efi_loaded_image_obj *image_obj,
+ struct efi_loaded_image *loaded_image_protocol)
+{
+ struct efi_object *efiobj;
+ efi_status_t r, ret = EFI_SUCCESS;
+
+close_next:
+ list_for_each_entry(efiobj, &efi_obj_list, link) {
+ struct efi_handler *protocol;
+
+ list_for_each_entry(protocol, &efiobj->protocols, link) {
+ struct efi_open_protocol_info_item *info;
+
+ list_for_each_entry(info, &protocol->open_infos, link) {
+ if (info->info.agent_handle !=
+ (efi_handle_t)image_obj)
+ continue;
+ r = EFI_CALL(efi_close_protocol
+ (efiobj, protocol->guid,
+ info->info.agent_handle,
+ info->info.controller_handle
+ ));
+ if (r != EFI_SUCCESS)
+ ret = r;
+ /*
+ * Closing protocols may results in further
+ * items being deleted. To play it safe loop
+ * over all elements again.
+ */
+ goto close_next;
+ }
+ }
+ }
+
+ efi_free_pages((uintptr_t)loaded_image_protocol->image_base,
+ efi_size_in_pages(loaded_image_protocol->image_size));
+ efi_delete_handle(&image_obj->header);
+
+ return ret;
+}
+
+/**
+ * efi_unload_image() - unload an EFI image
+ * @image_handle: handle of the image to be unloaded
+ *
+ * This function implements the UnloadImage service.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * Return: status code
+ */
+efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle)
+{
+ efi_status_t ret = EFI_SUCCESS;
+ struct efi_object *efiobj;
+ struct efi_loaded_image *loaded_image_protocol;
+
+ EFI_ENTRY("%p", image_handle);
+
+ efiobj = efi_search_obj(image_handle);
+ if (!efiobj) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ /* Find the loaded image protocol */
+ ret = EFI_CALL(efi_open_protocol(image_handle, &efi_guid_loaded_image,
+ (void **)&loaded_image_protocol,
+ NULL, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (ret != EFI_SUCCESS) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ switch (efiobj->type) {
+ case EFI_OBJECT_TYPE_STARTED_IMAGE:
+ /* Call the unload function */
+ if (!loaded_image_protocol->unload) {
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+ ret = EFI_CALL(loaded_image_protocol->unload(image_handle));
+ if (ret != EFI_SUCCESS)
+ goto out;
+ break;
+ case EFI_OBJECT_TYPE_LOADED_IMAGE:
+ break;
+ default:
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ efi_delete_image((struct efi_loaded_image_obj *)efiobj,
+ loaded_image_protocol);
+out:
+ return EFI_EXIT(ret);
+}
+
+/**
+ * efi_update_exit_data() - fill exit data parameters of StartImage()
+ *
+ * @image_obj image handle
+ * @exit_data_size size of the exit data buffer
+ * @exit_data buffer with data returned by UEFI payload
+ * Return: status code
+ */
+static efi_status_t efi_update_exit_data(struct efi_loaded_image_obj *image_obj,
+ efi_uintn_t exit_data_size,
+ u16 *exit_data)
+{
+ efi_status_t ret;
+
+ /*
+ * If exit_data is not provided to StartImage(), exit_data_size must be
+ * ignored.
+ */
+ if (!image_obj->exit_data)
+ return EFI_SUCCESS;
+ if (image_obj->exit_data_size)
+ *image_obj->exit_data_size = exit_data_size;
+ if (exit_data_size && exit_data) {
+ ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA,
+ exit_data_size,
+ (void **)image_obj->exit_data);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ memcpy(*image_obj->exit_data, exit_data, exit_data_size);
+ } else {
+ image_obj->exit_data = NULL;
+ }
+ return EFI_SUCCESS;
+}
+
/**
* efi_exit() - leave an EFI application or driver
* @image_handle: handle of the application or driver that is exiting
* image protocol.
*/
efi_status_t ret;
- void *info;
+ struct efi_loaded_image *loaded_image_protocol;
struct efi_loaded_image_obj *image_obj =
(struct efi_loaded_image_obj *)image_handle;
exit_data_size, exit_data);
/* Check parameters */
- if (image_handle != current_image)
- goto out;
ret = EFI_CALL(efi_open_protocol(image_handle, &efi_guid_loaded_image,
- &info, NULL, NULL,
+ (void **)&loaded_image_protocol,
+ NULL, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL));
- if (ret != EFI_SUCCESS)
+ if (ret != EFI_SUCCESS) {
+ ret = EFI_INVALID_PARAMETER;
goto out;
+ }
+
+ /* Unloading of unstarted images */
+ switch (image_obj->header.type) {
+ case EFI_OBJECT_TYPE_STARTED_IMAGE:
+ break;
+ case EFI_OBJECT_TYPE_LOADED_IMAGE:
+ efi_delete_image(image_obj, loaded_image_protocol);
+ ret = EFI_SUCCESS;
+ goto out;
+ default:
+ /* Handle does not refer to loaded image */
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ /* A started image can only be unloaded it is the last one started. */
+ if (image_handle != current_image) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ /* Exit data is only foreseen in case of failure. */
+ if (exit_status != EFI_SUCCESS) {
+ ret = efi_update_exit_data(image_obj, exit_data_size,
+ exit_data);
+ /* Exiting has priority. Don't return error to caller. */
+ if (ret != EFI_SUCCESS)
+ EFI_PRINT("%s: out of memory\n", __func__);
+ }
+ if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION ||
+ exit_status != EFI_SUCCESS)
+ efi_delete_image(image_obj, loaded_image_protocol);
/* Make sure entry/exit counts for EFI world cross-overs match */
EFI_EXIT(exit_status);
panic("EFI application exited");
out:
- return EFI_EXIT(EFI_INVALID_PARAMETER);
+ return EFI_EXIT(ret);
}
/**
const efi_guid_t *protocol,
void **protocol_interface)
{
- return efi_open_protocol(handle, protocol, protocol_interface, NULL,
+ return efi_open_protocol(handle, protocol, protocol_interface, efi_root,
NULL, EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL);
}
EFI_ENTRY("%p, %p", this, string);
+ if (!this || !string) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
buf = malloc(utf16_utf8_strlen(string) + 1);
if (!buf) {
ret = EFI_OUT_OF_RESOURCES;
EFI_ENTRY("%p, %d", this, enable);
printf(ESC"[?25%c", enable ? 'h' : 'l');
+ efi_con_mode.cursor_visible = !!enable;
return EFI_EXIT(EFI_SUCCESS);
}
* efi_cin_set_state() - set toggle key state
*
* @this: instance of the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
- * @key_toggle_state: key toggle state
+ * @key_toggle_state: pointer to key toggle state
* Return: status code
*
* This function implements the SetState service of the
*/
static efi_status_t EFIAPI efi_cin_set_state(
struct efi_simple_text_input_ex_protocol *this,
- u8 key_toggle_state)
+ u8 *key_toggle_state)
{
- EFI_ENTRY("%p, %u", this, key_toggle_state);
+ EFI_ENTRY("%p, %p", this, key_toggle_state);
/*
* U-Boot supports multiple console input sources like serial and
* net console for which a key toggle state cannot be set at all.
case DEVICE_PATH_SUB_TYPE_ACPI_DEVICE: {
struct efi_device_path_acpi_path *adp =
(struct efi_device_path_acpi_path *)dp;
- s += sprintf(s, "Acpi(PNP%04x", EISA_PNP_NUM(adp->hid));
- if (adp->uid)
- s += sprintf(s, ",%d", adp->uid);
- s += sprintf(s, ")");
+
+ s += sprintf(s, "Acpi(PNP%04X,%d)", EISA_PNP_NUM(adp->hid),
+ adp->uid);
break;
}
default:
IMAGE_OPTIONAL_HEADER64 *opt = &nt64->OptionalHeader;
image_base = opt->ImageBase;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
+ handle->image_type = opt->Subsystem;
efi_reloc = efi_alloc(virt_size,
loaded_image_info->image_code_type);
if (!efi_reloc) {
IMAGE_OPTIONAL_HEADER32 *opt = &nt->OptionalHeader;
image_base = opt->ImageBase;
efi_set_code_and_data_type(loaded_image_info, opt->Subsystem);
+ handle->image_type = opt->Subsystem;
efi_reloc = efi_alloc(virt_size,
loaded_image_info->image_code_type);
if (!efi_reloc) {
struct efi_mem_list *newlist;
bool carve_again;
uint64_t carved_pages = 0;
+ struct efi_event *evt;
EFI_PRINT("%s: 0x%llx 0x%llx %d %s\n", __func__,
start, pages, memory_type, overlap_only_ram ? "yes" : "no");
/* And make sure memory is listed in descending order */
efi_mem_sort();
+ /* Notify that the memory map was changed */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group &&
+ !guidcmp(evt->group,
+ &efi_guid_event_group_memory_map_change)) {
+ efi_signal_event(evt, false);
+ break;
+ }
+ }
+
return start;
}
+/**
+ * efi_check_allocated() - validate address to be freed
+ *
+ * Check that the address is within allocated memory:
+ *
+ * * The address cannot be NULL.
+ * * The address must be in a range of the memory map.
+ * * The address may not point to EFI_CONVENTIONAL_MEMORY.
+ *
+ * Page alignment is not checked as this is not a requirement of
+ * efi_free_pool().
+ *
+ * @addr: address of page to be freed
+ * @must_be_allocated: return success if the page is allocated
+ * Return: status code
+ */
+static efi_status_t efi_check_allocated(u64 addr, bool must_be_allocated)
+{
+ struct efi_mem_list *item;
+
+ if (!addr)
+ return EFI_INVALID_PARAMETER;
+ list_for_each_entry(item, &efi_mem, link) {
+ u64 start = item->desc.physical_start;
+ u64 end = start + (item->desc.num_pages << EFI_PAGE_SHIFT);
+
+ if (addr >= start && addr < end) {
+ if (must_be_allocated ^
+ (item->desc.type == EFI_CONVENTIONAL_MEMORY))
+ return EFI_SUCCESS;
+ else
+ return EFI_NOT_FOUND;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
static uint64_t efi_find_free_memory(uint64_t len, uint64_t max_addr)
{
struct list_head *lhandle;
efi_uintn_t pages, uint64_t *memory)
{
u64 len = pages << EFI_PAGE_SHIFT;
- efi_status_t r = EFI_SUCCESS;
+ efi_status_t ret;
uint64_t addr;
/* Check import parameters */
case EFI_ALLOCATE_ANY_PAGES:
/* Any page */
addr = efi_find_free_memory(len, -1ULL);
- if (!addr) {
- r = EFI_NOT_FOUND;
- break;
- }
+ if (!addr)
+ return EFI_OUT_OF_RESOURCES;
break;
case EFI_ALLOCATE_MAX_ADDRESS:
/* Max address */
addr = efi_find_free_memory(len, *memory);
- if (!addr) {
- r = EFI_NOT_FOUND;
- break;
- }
+ if (!addr)
+ return EFI_OUT_OF_RESOURCES;
break;
case EFI_ALLOCATE_ADDRESS:
/* Exact address, reserve it. The addr is already in *memory. */
+ ret = efi_check_allocated(*memory, false);
+ if (ret != EFI_SUCCESS)
+ return EFI_NOT_FOUND;
addr = *memory;
break;
default:
/* UEFI doesn't specify other allocation types */
- r = EFI_INVALID_PARAMETER;
- break;
+ return EFI_INVALID_PARAMETER;
}
- if (r == EFI_SUCCESS) {
- uint64_t ret;
+ /* Reserve that map in our memory maps */
+ if (efi_add_memory_map(addr, pages, memory_type, true) != addr)
+ /* Map would overlap, bail out */
+ return EFI_OUT_OF_RESOURCES;
- /* Reserve that map in our memory maps */
- ret = efi_add_memory_map(addr, pages, memory_type, true);
- if (ret == addr) {
- *memory = addr;
- } else {
- /* Map would overlap, bail out */
- r = EFI_OUT_OF_RESOURCES;
- }
- }
+ *memory = addr;
- return r;
+ return EFI_SUCCESS;
}
void *efi_alloc(uint64_t len, int memory_type)
efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
{
uint64_t r = 0;
+ efi_status_t ret;
+
+ ret = efi_check_allocated(memory, true);
+ if (ret != EFI_SUCCESS)
+ return ret;
/* Sanity check */
- if (!memory || (memory & EFI_PAGE_MASK)) {
+ if (!memory || (memory & EFI_PAGE_MASK) || !pages) {
printf("%s: illegal free 0x%llx, 0x%zx\n", __func__,
memory, pages);
return EFI_INVALID_PARAMETER;
*/
efi_status_t efi_free_pool(void *buffer)
{
- efi_status_t r;
+ efi_status_t ret;
struct efi_pool_allocation *alloc;
- if (buffer == NULL)
- return EFI_INVALID_PARAMETER;
+ ret = efi_check_allocated((uintptr_t)buffer, true);
+ if (ret != EFI_SUCCESS)
+ return ret;
alloc = container_of(buffer, struct efi_pool_allocation, data);
/* Avoid double free */
alloc->checksum = 0;
- r = efi_free_pages((uintptr_t)alloc, alloc->num_pages);
+ ret = efi_free_pages((uintptr_t)alloc, alloc->num_pages);
- return r;
+ return ret;
}
/*
efi_timer_check();
/* Check parameters */
- if (!this) {
+ if (!this || !buffer) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
* TODO: We would need to create the header
* if header_size != 0
*/
- ret = EFI_INVALID_PARAMETER;
+ ret = EFI_UNSUPPORTED;
goto out;
}
efi_timer_check();
/* Check parameters */
- if (!this) {
+ if (!this || !buffer || !buffer_size) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
*/
efi_status_t efi_root_node_register(void)
{
+ efi_status_t ret;
struct efi_root_dp *dp;
/* Create device path protocol */
dp->end.length = sizeof(struct efi_device_path);
/* Create root node and install protocols */
- return EFI_CALL(efi_install_multiple_protocol_interfaces(&efi_root,
- /* Device path protocol */
- &efi_guid_device_path, dp,
- /* Device path to text protocol */
- &efi_guid_device_path_to_text_protocol,
- (void *)&efi_device_path_to_text,
- /* Device path utilities protocol */
- &efi_guid_device_path_utilities_protocol,
- (void *)&efi_device_path_utilities,
- /* Unicode collation protocol */
- &efi_guid_unicode_collation_protocol,
- (void *)&efi_unicode_collation_protocol,
+ ret = EFI_CALL(efi_install_multiple_protocol_interfaces
+ (&efi_root,
+ /* Device path protocol */
+ &efi_guid_device_path, dp,
+#if CONFIG_IS_ENABLED(EFI_DEVICE_PATH_TO_TEXT)
+ /* Device path to text protocol */
+ &efi_guid_device_path_to_text_protocol,
+ (void *)&efi_device_path_to_text,
+#endif
+ /* Device path utilities protocol */
+ &efi_guid_device_path_utilities_protocol,
+ (void *)&efi_device_path_utilities,
+#if CONFIG_IS_ENABLED(EFI_UNICODE_COLLATION_PROTOCOL2)
+#if CONFIG_IS_ENABLED(EFI_UNICODE_COLLATION_PROTOCOL)
+ /* Deprecated Unicode collation protocol */
+ &efi_guid_unicode_collation_protocol,
+ (void *)&efi_unicode_collation_protocol,
+#endif
+ /* Current Unicode collation protocol */
+ &efi_guid_unicode_collation_protocol2,
+ (void *)&efi_unicode_collation_protocol2,
+#endif
#if CONFIG_IS_ENABLED(EFI_LOADER_HII)
- /* HII string protocol */
- &efi_guid_hii_string_protocol,
- (void *)&efi_hii_string,
- /* HII database protocol */
- &efi_guid_hii_database_protocol,
- (void *)&efi_hii_database,
- /* HII configuration routing protocol */
- &efi_guid_hii_config_routing_protocol,
- (void *)&efi_hii_config_routing,
+ /* HII string protocol */
+ &efi_guid_hii_string_protocol,
+ (void *)&efi_hii_string,
+ /* HII database protocol */
+ &efi_guid_hii_database_protocol,
+ (void *)&efi_hii_database,
+ /* HII configuration routing protocol */
+ &efi_guid_hii_config_routing_protocol,
+ (void *)&efi_hii_config_routing,
#endif
- NULL));
+ NULL));
+ efi_root->type = EFI_OBJECT_TYPE_U_BOOT_FIRMWARE;
+ return ret;
}
struct efi_time *time,
struct efi_time_cap *capabilities)
{
-#ifdef CONFIG_DM_RTC
+#ifdef CONFIG_EFI_GET_TIME
efi_status_t ret = EFI_SUCCESS;
- int r;
struct rtc_time tm;
struct udevice *dev;
ret = EFI_INVALID_PARAMETER;
goto out;
}
-
- r = uclass_get_device(UCLASS_RTC, 0, &dev);
- if (!r)
- r = dm_rtc_get(dev, &tm);
- if (r) {
+ if (uclass_get_device(UCLASS_RTC, 0, &dev) ||
+ dm_rtc_get(dev, &tm)) {
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+ if (dm_rtc_get(dev, &tm)) {
ret = EFI_DEVICE_ERROR;
goto out;
}
time->hour = tm.tm_hour;
time->minute = tm.tm_min;
time->second = tm.tm_sec;
- time->daylight = EFI_TIME_ADJUST_DAYLIGHT;
- if (tm.tm_isdst > 0)
- time->daylight |= EFI_TIME_IN_DAYLIGHT;
+ if (tm.tm_isdst)
+ time->daylight =
+ EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT;
time->timezone = EFI_UNSPECIFIED_TIMEZONE;
if (capabilities) {
return EFI_EXIT(ret);
#else
EFI_ENTRY("%p %p", time, capabilities);
- return EFI_EXIT(EFI_DEVICE_ERROR);
+ return EFI_EXIT(EFI_UNSUPPORTED);
#endif
}
+#ifdef CONFIG_EFI_SET_TIME
+
+/**
+ * efi_validate_time() - checks if timestamp is valid
+ *
+ * @time: timestamp to validate
+ * Returns: 0 if timestamp is valid, 1 otherwise
+ */
+static int efi_validate_time(struct efi_time *time)
+{
+ return (!time ||
+ time->year < 1900 || time->year > 9999 ||
+ !time->month || time->month > 12 || !time->day ||
+ time->day > rtc_month_days(time->month - 1, time->year) ||
+ time->hour > 23 || time->minute > 59 || time->second > 59 ||
+ time->nanosecond > 999999999 ||
+ time->daylight &
+ ~(EFI_TIME_IN_DAYLIGHT | EFI_TIME_ADJUST_DAYLIGHT) ||
+ ((time->timezone < -1440 || time->timezone > 1440) &&
+ time->timezone != EFI_UNSPECIFIED_TIMEZONE));
+}
+
+#endif
+
+/**
+ * efi_set_time_boottime() - set current time
+ *
+ * This function implements the SetTime() runtime service before
+ * SetVirtualAddressMap() is called.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @time: pointer to structure to with current time
+ * Returns: status code
+ */
+static efi_status_t EFIAPI efi_set_time_boottime(struct efi_time *time)
+{
+#ifdef CONFIG_EFI_SET_TIME
+ efi_status_t ret = EFI_SUCCESS;
+ struct rtc_time tm;
+ struct udevice *dev;
+
+ EFI_ENTRY("%p", time);
+
+ if (efi_validate_time(time)) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+ if (uclass_get_device(UCLASS_RTC, 0, &dev)) {
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+
+ memset(&tm, 0, sizeof(tm));
+ tm.tm_year = time->year;
+ tm.tm_mon = time->month;
+ tm.tm_mday = time->day;
+ tm.tm_hour = time->hour;
+ tm.tm_min = time->minute;
+ tm.tm_sec = time->second;
+ tm.tm_isdst = time->daylight ==
+ (EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT);
+ /* Calculate day of week */
+ rtc_calc_weekday(&tm);
+
+ if (dm_rtc_set(dev, &tm))
+ ret = EFI_DEVICE_ERROR;
+out:
+ return EFI_EXIT(ret);
+#else
+ EFI_ENTRY("%p", time);
+ return EFI_EXIT(EFI_UNSUPPORTED);
+#endif
+}
/**
* efi_reset_system() - reset system
*
return EFI_DEVICE_ERROR;
}
+/**
+ * efi_set_time() - set current time
+ *
+ * This function implements the SetTime runtime service after
+ * SetVirtualAddressMap() is called. As the U-Boot driver are not available
+ * anymore only an error code is returned.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @time: pointer to structure to with current time
+ * Returns: status code
+ */
+efi_status_t __weak __efi_runtime EFIAPI efi_set_time(struct efi_time *time)
+{
+ return EFI_UNSUPPORTED;
+}
+
struct efi_runtime_detach_list_struct {
void *ptr;
void *patchto;
/* RTC accessors are gone */
.ptr = &efi_runtime_services.get_time,
.patchto = &efi_get_time,
+ }, {
+ .ptr = &efi_runtime_services.set_time,
+ .patchto = &efi_set_time,
}, {
/* Clean up system table */
.ptr = &systab.con_in,
.headersize = sizeof(struct efi_runtime_services),
},
.get_time = &efi_get_time_boottime,
- .set_time = (void *)&efi_device_error,
+ .set_time = &efi_set_time_boottime,
.get_wakeup_time = (void *)&efi_unimplemented,
.set_wakeup_time = (void *)&efi_unimplemented,
.set_virtual_address_map = &efi_set_virtual_address_map,
*/
#include <common.h>
+#include <bootm.h>
#include <efi_loader.h>
#define OBJ_LIST_NOT_INITIALIZED 1
static efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
+/*
+ * Allow unaligned memory access.
+ *
+ * This routine is overridden by architectures providing this feature.
+ */
+void __weak allow_unaligned(void)
+{
+}
+
/**
* efi_init_platform_lang() - define supported languages
*
*/
efi_status_t efi_init_obj_list(void)
{
+ u64 os_indications_supported = 0; /* None */
efi_status_t ret = EFI_SUCCESS;
/* Initialize once only */
if (efi_obj_list_initialized != OBJ_LIST_NOT_INITIALIZED)
return efi_obj_list_initialized;
+ /* Allow unaligned memory access */
+ allow_unaligned();
+
+ /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
+ switch_to_non_secure_mode();
+
/* Define supported languages */
ret = efi_init_platform_lang();
if (ret != EFI_SUCCESS)
goto out;
+ /* Indicate supported features */
+ ret = EFI_CALL(efi_set_variable(L"OsIndicationsSupported",
+ &efi_global_variable_guid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof(os_indications_supported),
+ &os_indications_supported));
+ if (ret != EFI_SUCCESS)
+ goto out;
+
/* Initialize system table */
ret = efi_initialize_system_table();
if (ret != EFI_SUCCESS)
#include <efi_loader.h>
/* Characters that may not be used in file names */
-static const char illegal[] = "<>:\"/\\|?*";
+static const char illegal[] = "<>:\"/\\|?*\x7f";
/*
* EDK2 assumes codepage 1250 when creating FAT 8.3 file names.
static const u16 codepage[] = CP437;
#endif
-/* GUID of the EFI_UNICODE_COLLATION_PROTOCOL */
-const efi_guid_t efi_guid_unicode_collation_protocol =
+/* GUID of the EFI_UNICODE_COLLATION_PROTOCOL2 */
+const efi_guid_t efi_guid_unicode_collation_protocol2 =
EFI_UNICODE_COLLATION_PROTOCOL2_GUID;
/**
return ret;
}
-const struct efi_unicode_collation_protocol efi_unicode_collation_protocol = {
+const struct efi_unicode_collation_protocol efi_unicode_collation_protocol2 = {
.stri_coll = efi_stri_coll,
.metai_match = efi_metai_match,
.str_lwr = efi_str_lwr,
.str_to_fat = efi_str_to_fat,
.supported_languages = "en",
};
+
+/*
+ * In EFI 1.10 a version of the Unicode collation protocol using ISO 639-2
+ * language codes existed. This protocol is not part of the UEFI specification
+ * any longer. Unfortunately it is required to run the UEFI Self Certification
+ * Test (SCT) II, version 2.6, 2017. So we implement it here for the sole
+ * purpose of running the SCT. It can be removed when a compliant SCT is
+ * available.
+ */
+#if CONFIG_IS_ENABLED(EFI_UNICODE_COLLATION_PROTOCOL)
+
+/* GUID of the EFI_UNICODE_COLLATION_PROTOCOL */
+const efi_guid_t efi_guid_unicode_collation_protocol =
+ EFI_UNICODE_COLLATION_PROTOCOL_GUID;
+
+const struct efi_unicode_collation_protocol efi_unicode_collation_protocol = {
+ .stri_coll = efi_stri_coll,
+ .metai_match = efi_metai_match,
+ .str_lwr = efi_str_lwr,
+ .str_upr = efi_str_upr,
+ .fat_to_str = efi_fat_to_str,
+ .str_to_fat = efi_str_to_fat,
+ /* ISO 639-2 language code */
+ .supported_languages = "eng",
+};
+
+#endif
if ((s = prefix(str, "ro"))) {
attr |= READ_ONLY;
+ } else if ((s = prefix(str, "nv"))) {
+ attr |= EFI_VARIABLE_NON_VOLATILE;
} else if ((s = prefix(str, "boot"))) {
attr |= EFI_VARIABLE_BOOTSERVICE_ACCESS;
} else if ((s = prefix(str, "run"))) {
len /= 2;
*data_size = len;
- if (in_size < len)
- return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+ if (in_size < len) {
+ ret = EFI_BUFFER_TOO_SMALL;
+ goto out;
+ }
if (!data)
return EFI_EXIT(EFI_INVALID_PARAMETER);
*data_size = len;
- if (in_size < len)
- return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+ if (in_size < len) {
+ ret = EFI_BUFFER_TOO_SMALL;
+ goto out;
+ }
if (!data)
return EFI_EXIT(EFI_INVALID_PARAMETER);
return EFI_EXIT(EFI_DEVICE_ERROR);
}
+out:
if (attributes)
*attributes = attr & EFI_VARIABLE_MASK;
- return EFI_EXIT(EFI_SUCCESS);
+ return EFI_EXIT(ret);
}
static char *efi_variables_list;
EFI_ENTRY("\"%ls\" %pUl %x %zu %p", variable_name, vendor, attributes,
data_size, data);
- if (!variable_name || !vendor) {
+ /* TODO: implement APPEND_WRITE */
+ if (!variable_name || !vendor ||
+ (attributes & EFI_VARIABLE_APPEND_WRITE)) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
if (val) {
parse_attr(val, &attr);
+ /* We should not free val */
+ val = NULL;
if (attr & READ_ONLY) {
- /* We should not free val */
- val = NULL;
ret = EFI_WRITE_PROTECTED;
goto out;
}
+
+ /*
+ * attributes won't be changed
+ * TODO: take care of APPEND_WRITE once supported
+ */
+ if (attr != attributes) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
}
- val = malloc(2 * data_size + strlen("{ro,run,boot}(blob)") + 1);
+ val = malloc(2 * data_size + strlen("{ro,run,boot,nv}(blob)") + 1);
if (!val) {
ret = EFI_OUT_OF_RESOURCES;
goto out;
* store attributes
* TODO: several attributes are not supported
*/
- attributes &= (EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS);
+ attributes &= (EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS);
s += sprintf(s, "{");
while (attributes) {
u32 attr = 1 << (ffs(attributes) - 1);
- if (attr == EFI_VARIABLE_BOOTSERVICE_ACCESS)
+ if (attr == EFI_VARIABLE_NON_VOLATILE)
+ s += sprintf(s, "nv");
+ else if (attr == EFI_VARIABLE_BOOTSERVICE_ACCESS)
s += sprintf(s, "boot");
else if (attr == EFI_VARIABLE_RUNTIME_ACCESS)
s += sprintf(s, "run");
efi_selftest_controllers.o \
efi_selftest_console.o \
efi_selftest_crc32.o \
-efi_selftest_devicepath.o \
efi_selftest_devicepath_util.o \
efi_selftest_events.o \
efi_selftest_event_groups.o \
efi_selftest_loaded_image.o \
efi_selftest_manageprotocols.o \
efi_selftest_memory.o \
-efi_selftest_rtc.o \
+efi_selftest_open_protocol.o \
+efi_selftest_register_notify.o \
efi_selftest_snp.o \
efi_selftest_textinput.o \
efi_selftest_textinputex.o \
efi_selftest_textoutput.o \
efi_selftest_tpl.o \
-efi_selftest_unicode_collation.o \
efi_selftest_util.o \
efi_selftest_variables.o \
efi_selftest_watchdog.o
+obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_selftest_devicepath.o
+obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += \
+efi_selftest_unicode_collation.o
+
obj-$(CONFIG_CPU_V7) += efi_selftest_unaligned.o
obj-$(CONFIG_EFI_LOADER_HII) += efi_selftest_hii.o
+obj-$(CONFIG_EFI_GET_TIME) += efi_selftest_rtc.o
ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
obj-y += efi_selftest_fdt.o
}
if (len >= dp_size(dp_partition))
continue;
- if (efi_st_memcmp(dp, dp_partition, len))
+ if (memcmp(dp, dp_partition, len))
continue;
handle_partition = handles[i];
break;
(unsigned int)buf_size);
return EFI_ST_FAILURE;
}
- if (efi_st_memcmp(buf, "ello world!", 11)) {
+ if (memcmp(buf, "ello world!", 11)) {
efi_st_error("Unexpected file content\n");
return EFI_ST_FAILURE;
}
(unsigned int)buf_size);
return EFI_ST_FAILURE;
}
- if (efi_st_memcmp(buf, "U-Boot", 7)) {
+ if (memcmp(buf, "U-Boot", 7)) {
efi_st_error("Unexpected file content %s\n", buf);
return EFI_ST_FAILURE;
}
}
table = NULL;
for (i = 0; i < sys_table->nr_tables; ++i) {
- if (!efi_st_memcmp(&sys_table->tables[i].guid, &table_guid,
- sizeof(efi_guid_t)))
+ if (!memcmp(&sys_table->tables[i].guid, &table_guid,
+ sizeof(efi_guid_t)))
table = sys_table->tables[i].table;
}
if (!table) {
table = NULL;
tabcnt = 0;
for (i = 0; i < sys_table->nr_tables; ++i) {
- if (!efi_st_memcmp(&sys_table->tables[i].guid, &table_guid,
- sizeof(efi_guid_t))) {
+ if (!memcmp(&sys_table->tables[i].guid, &table_guid,
+ sizeof(efi_guid_t))) {
table = sys_table->tables[i].table;
++tabcnt;
}
}
table = NULL;
for (i = 0; i < sys_table->nr_tables; ++i) {
- if (!efi_st_memcmp(&sys_table->tables[i].guid, &table_guid,
- sizeof(efi_guid_t))) {
+ if (!memcmp(&sys_table->tables[i].guid, &table_guid,
+ sizeof(efi_guid_t))) {
table = sys_table->tables[i].table;
}
}
efi_st_printf("%u protocols installed on image handle\n",
(unsigned int)protocol_buffer_count);
for (i = 0; i < protocol_buffer_count; ++i) {
- if (efi_st_memcmp(protocol_buffer[i],
- &loaded_image_protocol_guid,
- sizeof(efi_guid_t)))
+ if (memcmp(protocol_buffer[i], &loaded_image_protocol_guid,
+ sizeof(efi_guid_t)))
found = true;
}
if (!found) {
efi_uintn_t *buffer_size, void *buffer)
{
if (this == &file) {
- if (efi_st_memcmp(info_type, &guid_file_info,
- sizeof(efi_guid_t)))
+ if (memcmp(info_type, &guid_file_info, sizeof(efi_guid_t)))
return EFI_INVALID_PARAMETER;
if (*buffer_size >= sizeof(struct file_info)) {
boottime->copy_mem(buffer, file_info,
return EFI_BUFFER_TOO_SMALL;
}
} else if (this == &volume) {
- if (efi_st_memcmp(info_type, &guid_file_system_info,
- sizeof(efi_guid_t)))
+ if (memcmp(info_type, &guid_file_system_info,
+ sizeof(efi_guid_t)))
return EFI_INVALID_PARAMETER;
if (*buffer_size >= sizeof(struct file_system_info)) {
boottime->copy_mem(buffer, file_system_info,
efi_st_error("Failed to get protocols per handle\n");
return EFI_ST_FAILURE;
}
- if (efi_st_memcmp(prot_buffer[0], &guid1, 16) &&
- efi_st_memcmp(prot_buffer[1], &guid1, 16)) {
+ if (memcmp(prot_buffer[0], &guid1, 16) &&
+ memcmp(prot_buffer[1], &guid1, 16)) {
efi_st_error("Failed to get protocols per handle\n");
return EFI_ST_FAILURE;
}
- if (efi_st_memcmp(prot_buffer[0], &guid3, 16) &&
- efi_st_memcmp(prot_buffer[1], &guid3, 16)) {
+ if (memcmp(prot_buffer[0], &guid3, 16) &&
+ memcmp(prot_buffer[1], &guid3, 16)) {
efi_st_error("Failed to get protocols per handle\n");
return EFI_ST_FAILURE;
}
boottime = systable->boottime;
for (i = 0; i < systable->nr_tables; ++i) {
- if (!efi_st_memcmp(&systable->tables[i].guid, &fdt_guid,
- sizeof(efi_guid_t))) {
+ if (!memcmp(&systable->tables[i].guid, &fdt_guid,
+ sizeof(efi_guid_t))) {
if (fdt_addr) {
efi_st_error("Duplicate device tree\n");
return EFI_ST_FAILURE;
*/
#include <common.h>
-#include <efi_api.h>
+#include <efi_selftest.h>
static efi_guid_t loaded_image_protocol_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID;
struct efi_system_table *systable)
{
struct efi_simple_text_output_protocol *con_out = systable->con_out;
- efi_status_t ret = EFI_UNSUPPORTED;
+ efi_status_t ret;
+ u16 text[] = EFI_ST_SUCCESS_STR;
con_out->output_string(con_out, L"EFI application calling Exit\n");
- if (check_loaded_image_protocol(handle, systable) != EFI_SUCCESS)
+ if (check_loaded_image_protocol(handle, systable) != EFI_SUCCESS) {
+ con_out->output_string(con_out,
+ L"Loaded image protocol missing\n");
ret = EFI_NOT_FOUND;
+ goto out;
+ }
- /* The return value is checked by the calling test */
- systable->boottime->exit(handle, ret, 0, NULL);
+ /* This return value is expected by the calling test */
+ ret = EFI_UNSUPPORTED;
+out:
+ systable->boottime->exit(handle, ret, sizeof(text), text);
/*
* This statement should not be reached.
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_open_protocol
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This unit test checks that open protocol information is correctly updated
+ * when calling:
+ * HandleProtocol, OpenProtocol, OpenProtocolInformation, CloseProtocol.
+ */
+
+#include <efi_selftest.h>
+
+/*
+ * The test currently does not actually call the interface function.
+ * So this is just a dummy structure.
+ */
+struct interface {
+ void (EFIAPI *inc)(void);
+};
+
+static struct efi_boot_services *boottime;
+static efi_guid_t guid1 =
+ EFI_GUID(0x492a0e38, 0x1442, 0xf819,
+ 0x14, 0xaa, 0x4b, 0x8d, 0x09, 0xfe, 0x5a, 0xb9);
+static efi_handle_t handle1;
+static struct interface interface1;
+
+/*
+ * Setup unit test.
+ *
+ * Create a handle and install a protocol interface on it.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+
+ boottime = systable->boottime;
+
+ ret = boottime->install_protocol_interface(&handle1, &guid1,
+ EFI_NATIVE_INTERFACE,
+ &interface1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("InstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!handle1) {
+ efi_st_error
+ ("InstallProtocolInterface failed to create handle\n");
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ */
+static int teardown(void)
+{
+ efi_status_t ret;
+
+ if (handle1) {
+ ret = boottime->uninstall_protocol_interface(handle1, &guid1,
+ &interface1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallProtocolInterface failed\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Open the installed protocol twice via HandleProtocol() and once via
+ * OpenProtocol(EFI_OPEN_PROTOCOL_GET_PROTOCOL). Read the open protocol
+ * information and check the open counts. Finally close the protocol and
+ * check again.
+ */
+static int execute(void)
+{
+ void *interface;
+ struct efi_open_protocol_info_entry *entry_buffer;
+ efi_uintn_t entry_count;
+ efi_handle_t firmware_handle;
+ efi_status_t ret;
+
+ ret = boottime->handle_protocol(handle1, &guid1, &interface);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("HandleProtocol failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (interface != &interface1) {
+ efi_st_error("HandleProtocol returned wrong interface\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->open_protocol_information(handle1, &guid1,
+ &entry_buffer, &entry_count);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocolInformation failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (entry_count != 1) {
+ efi_st_error("Incorrect OpenProtocolInformation count\n");
+ efi_st_printf("Expected 1, got %u\n",
+ (unsigned int)entry_count);
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(entry_buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->handle_protocol(handle1, &guid1, &interface);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("HandleProtocol failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->open_protocol_information(handle1, &guid1,
+ &entry_buffer, &entry_count);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocolInformation failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (entry_count != 1) {
+ efi_st_error("Incorrect OpenProtocolInformation count\n");
+ efi_st_printf("Expected 1, got %u\n",
+ (unsigned int)entry_count);
+ return EFI_ST_FAILURE;
+ }
+ if (entry_buffer[0].open_count != 2) {
+ efi_st_error("Incorrect open count: expected 2 got %u\n",
+ entry_buffer[0].open_count);
+ return EFI_ST_FAILURE;
+ }
+ firmware_handle = entry_buffer[0].agent_handle;
+ ret = boottime->free_pool(entry_buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->open_protocol(handle1, &guid1, &interface,
+ firmware_handle, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocol failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->open_protocol_information(handle1, &guid1,
+ &entry_buffer, &entry_count);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocolInformation failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (entry_count != 2) {
+ efi_st_error("Incorrect OpenProtocolInformation count\n");
+ efi_st_printf("Expected 2, got %u\n",
+ (unsigned int)entry_count);
+ return EFI_ST_FAILURE;
+ }
+ if (entry_buffer[0].open_count + entry_buffer[1].open_count != 3) {
+ efi_st_error("Incorrect open count: expected 3 got %u\n",
+ entry_buffer[0].open_count +
+ entry_buffer[1].open_count);
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(entry_buffer);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->close_protocol(handle1, &guid1, firmware_handle, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("CloseProtocol failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->open_protocol_information(handle1, &guid1,
+ &entry_buffer, &entry_count);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("OpenProtocolInformation failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (entry_count) {
+ efi_st_error("Incorrect OpenProtocolInformation count\n");
+ efi_st_printf("Expected 0, got %u\n",
+ (unsigned int)entry_count);
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(openprot) = {
+ .name = "open protocol",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_register_notify
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This unit test checks the following protocol services:
+ * InstallProtocolInterface, UninstallProtocolInterface,
+ * RegisterProtocolNotify, CreateEvent, CloseEvent.
+ */
+
+#include <efi_selftest.h>
+
+/*
+ * The test currently does not actually call the interface function.
+ * So this is just a dummy structure.
+ */
+struct interface {
+ void (EFIAPI * inc)(void);
+};
+
+struct context {
+ void *registration_key;
+ efi_uintn_t notify_count;
+ efi_uintn_t handle_count;
+ efi_handle_t *handles;
+};
+
+static struct efi_boot_services *boottime;
+static efi_guid_t guid1 =
+ EFI_GUID(0x2e7ca819, 0x21d3, 0x0a3a,
+ 0xf7, 0x91, 0x82, 0x1f, 0x7a, 0x83, 0x67, 0xaf);
+static efi_guid_t guid2 =
+ EFI_GUID(0xf909f2bb, 0x90a8, 0x0d77,
+ 0x94, 0x0c, 0x3e, 0xa8, 0xea, 0x38, 0xd6, 0x6f);
+static struct context context;
+static struct efi_event *event;
+
+/*
+ * Notification function, increments the notification count if parameter
+ * context is provided.
+ *
+ * @event notified event
+ * @context pointer to the notification count
+ */
+static void EFIAPI notify(struct efi_event *event, void *context)
+{
+ struct context *cp = context;
+ efi_status_t ret;
+ efi_uintn_t handle_count;
+ efi_handle_t *handles;
+
+ cp->notify_count++;
+
+ for (;;) {
+ ret = boottime->locate_handle_buffer(BY_REGISTER_NOTIFY, NULL,
+ cp->registration_key,
+ &handle_count, &handles);
+ if (ret != EFI_SUCCESS)
+ break;
+ cp->handle_count += handle_count;
+ cp->handles = handles;
+ }
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+
+ boottime = systable->boottime;
+
+ ret = boottime->create_event(EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK, notify, &context,
+ &event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not create event\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->register_protocol_notify(&guid1, event,
+ &context.registration_key);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not register event\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ */
+static int teardown(void)
+{
+ efi_status_t ret;
+
+ if (event) {
+ ret = boottime->close_event(event);
+ event = NULL;
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not close event\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_handle_t handle1 = NULL, handle2 = NULL;
+ struct interface interface1, interface2;
+
+ ret = boottime->install_protocol_interface(&handle1, &guid1,
+ EFI_NATIVE_INTERFACE,
+ &interface1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not install interface\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!context.notify_count) {
+ efi_st_error("install was not notified\n");
+ return EFI_ST_FAILURE;
+ }
+ if (context.notify_count > 1) {
+ efi_st_error("install was notified too often\n");
+ return EFI_ST_FAILURE;
+ }
+ if (context.handle_count != 1) {
+ efi_st_error("LocateHandle failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(context.handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ context.notify_count = 0;
+ ret = boottime->install_protocol_interface(&handle1, &guid2,
+ EFI_NATIVE_INTERFACE,
+ &interface1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not install interface\n");
+ return EFI_ST_FAILURE;
+ }
+ if (context.notify_count) {
+ efi_st_error("wrong protocol was notified\n");
+ return EFI_ST_FAILURE;
+ }
+ context.notify_count = 0;
+ ret = boottime->reinstall_protocol_interface(handle1, &guid1,
+ &interface1, &interface2);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not reinstall interface\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!context.notify_count) {
+ efi_st_error("reinstall was not notified\n");
+ return EFI_ST_FAILURE;
+ }
+ if (context.notify_count > 1) {
+ efi_st_error("reinstall was notified too often\n");
+ return EFI_ST_FAILURE;
+ }
+ if (context.handle_count != 2) {
+ efi_st_error("LocateHandle failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(context.handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ context.notify_count = 0;
+ ret = boottime->install_protocol_interface(&handle2, &guid1,
+ EFI_NATIVE_INTERFACE,
+ &interface1);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("could not install interface\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!context.notify_count) {
+ efi_st_error("install was not notified\n");
+ return EFI_ST_FAILURE;
+ }
+ if (context.notify_count > 1) {
+ efi_st_error("install was notified too often\n");
+ return EFI_ST_FAILURE;
+ }
+ if (context.handle_count != 3) {
+ efi_st_error("LocateHandle failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(context.handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->uninstall_multiple_protocol_interfaces
+ (handle1, &guid1, &interface2,
+ &guid2, &interface1, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallMultipleProtocolInterfaces failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_multiple_protocol_interfaces
+ (handle2, &guid1, &interface1, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("UninstallMultipleProtocolInterfaces failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(regprotnot) = {
+ .name = "register protocol notify",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
#include <efi_selftest.h>
#define EFI_ST_NO_RTC "Could not read real time clock\n"
+#define EFI_ST_NO_RTC_SET "Could not set real time clock\n"
static struct efi_runtime_services *runtime;
/*
* Execute unit test.
*
- * Display current time.
+ * Read and display current time.
+ * Set a new value and read it back.
+ * Set the real time clock back the current time.
*
* @return: EFI_ST_SUCCESS for success
*/
static int execute(void)
{
efi_status_t ret;
- struct efi_time tm;
+ struct efi_time tm_old;
+#ifdef CONFIG_EFI_SET_TIME
+ struct efi_time tm, tm_new = {
+ .year = 2017,
+ .month = 5,
+ .day = 19,
+ .hour = 13,
+ .minute = 47,
+ .second = 53,
+ };
+#endif
/* Display current time */
+ ret = runtime->get_time(&tm_old, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error(EFI_ST_NO_RTC);
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("Time according to real time clock: "
+ "%.4u-%.2u-%.2u %.2u:%.2u:%.2u\n",
+ tm_old.year, tm_old.month, tm_old.day,
+ tm_old.hour, tm_old.minute, tm_old.second);
+#ifdef CONFIG_EFI_SET_TIME
+ ret = runtime->set_time(&tm_new);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error(EFI_ST_NO_RTC_SET);
+ return EFI_ST_FAILURE;
+ }
ret = runtime->get_time(&tm, NULL);
if (ret != EFI_SUCCESS) {
-#ifdef CONFIG_CMD_DATE
efi_st_error(EFI_ST_NO_RTC);
return EFI_ST_FAILURE;
-#else
- efi_st_todo(EFI_ST_NO_RTC);
- return EFI_ST_SUCCESS;
-#endif
- } else {
- efi_st_printf("Time according to real time clock: "
- "%.4u-%.2u-%.2u %.2u:%.2u:%.2u\n",
- tm.year, tm.month, tm.day,
- tm.hour, tm.minute, tm.second);
}
+ if (tm.year != tm_new.year ||
+ tm.month != tm_new.month ||
+ tm.day != tm_new.day ||
+ tm.hour != tm_new.hour ||
+ tm.minute != tm_new.minute ||
+ tm.second < tm_new.second ||
+ tm.second > tm_new.second + 2) {
+ efi_st_error(EFI_ST_NO_RTC_SET);
+ return EFI_ST_FAILURE;
+ }
+ /* Set time back to old value */
+ ret = runtime->set_time(&tm_old);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error(EFI_ST_NO_RTC_SET);
+ return EFI_ST_FAILURE;
+ }
+#endif
return EFI_ST_SUCCESS;
}
* Unfortunately QEMU ignores the broadcast flag.
* So we have to check for broadcasts too.
*/
- if (efi_st_memcmp(&destaddr, &net->mode->current_address,
- ARP_HLEN) &&
- efi_st_memcmp(&destaddr, BROADCAST_MAC, ARP_HLEN))
+ if (memcmp(&destaddr, &net->mode->current_address, ARP_HLEN) &&
+ memcmp(&destaddr, BROADCAST_MAC, ARP_HLEN))
continue;
/*
* Check this is a DHCP reply
addr = (u8 *)&buffer.p.ip_udp.ip_src;
efi_st_printf("DHCP reply received from %u.%u.%u.%u (%pm) ",
addr[0], addr[1], addr[2], addr[3], &srcaddr);
- if (!efi_st_memcmp(&destaddr, BROADCAST_MAC, ARP_HLEN))
+ if (!memcmp(&destaddr, BROADCAST_MAC, ARP_HLEN))
efi_st_printf("as broadcast message.\n");
else
efi_st_printf("as unicast message.\n");
{
efi_status_t ret;
efi_handle_t handle;
+ efi_uintn_t exit_data_size = 0;
+ u16 *exit_data = NULL;
+ u16 expected_text[] = EFI_ST_SUCCESS_STR;
ret = boottime->load_image(false, image_handle, NULL, image,
img.length, &handle);
efi_st_error("Failed to load image\n");
return EFI_ST_FAILURE;
}
- ret = boottime->start_image(handle, NULL, NULL);
+ ret = boottime->start_image(handle, &exit_data_size, &exit_data);
if (ret != EFI_UNSUPPORTED) {
efi_st_error("Wrong return value from application\n");
return EFI_ST_FAILURE;
}
+ if (!exit_data || exit_data_size != sizeof(expected_text) ||
+ memcmp(exit_data, expected_text, sizeof(expected_text))) {
+ efi_st_error("Incorrect exit data\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(exit_data);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to free exit data\n");
+ return EFI_ST_FAILURE;
+ }
return EFI_ST_SUCCESS;
}
return efi_st_unknown;
}
-int efi_st_memcmp(const void *buf1, const void *buf2, size_t length)
-{
- const u8 *pos1 = buf1;
- const u8 *pos2 = buf2;
-
- for (; length; --length) {
- if (*pos1 != *pos2)
- return *pos1 - *pos2;
- ++pos1;
- ++pos2;
- }
- return 0;
-}
-
int efi_st_strcmp_16_8(const u16 *buf1, const char *buf2)
{
for (; *buf1 || *buf2; ++buf1, ++buf2) {
efi_st_error("GetVariable failed\n");
return EFI_ST_FAILURE;
}
- if (efi_st_memcmp(data, v + 4, 3)) {
+ if (memcmp(data, v + 4, 3)) {
efi_st_error("GetVariable returned wrong value\n");
return EFI_ST_FAILURE;
}
(unsigned int)len);
return EFI_ST_FAILURE;
}
- if (efi_st_memcmp(data, v, 8)) {
+ if (memcmp(data, v, 8)) {
efi_st_error("GetVariable returned wrong value\n");
return EFI_ST_FAILURE;
}
EFI_VARIABLE_APPEND_WRITE,
7, v + 8);
if (ret != EFI_SUCCESS) {
- efi_st_error("SetVariable failed\n");
- return EFI_ST_FAILURE;
- }
- len = EFI_ST_MAX_DATA_SIZE;
- ret = runtime->get_variable(L"efi_st_var1", &guid_vendor1,
- &attr, &len, data);
- if (ret != EFI_SUCCESS) {
- efi_st_error("GetVariable failed\n");
- return EFI_ST_FAILURE;
+ efi_st_todo("SetVariable(APPEND_WRITE) failed\n");
+ } else {
+ len = EFI_ST_MAX_DATA_SIZE;
+ ret = runtime->get_variable(L"efi_st_var1", &guid_vendor1,
+ &attr, &len, data);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("GetVariable failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (len != 15)
+ efi_st_todo("GetVariable returned wrong length %u\n",
+ (unsigned int)len);
+ if (memcmp(data, v, len))
+ efi_st_todo("GetVariable returned wrong value\n");
}
- if (len != 15)
- efi_st_todo("GetVariable returned wrong length %u\n",
- (unsigned int)len);
- if (efi_st_memcmp(data, v, len))
- efi_st_todo("GetVariable returned wrong value\n");
/* Enumerate variables */
boottime->set_mem(&guid, 16, 0);
*varname = 0;
(unsigned int)ret);
return EFI_ST_FAILURE;
}
- if (!efi_st_memcmp(&guid, &guid_vendor0, sizeof(efi_guid_t)) &&
+ if (!memcmp(&guid, &guid_vendor0, sizeof(efi_guid_t)) &&
!efi_st_strcmp_16_8(varname, "efi_st_var0"))
flag |= 1;
- if (!efi_st_memcmp(&guid, &guid_vendor1, sizeof(efi_guid_t)) &&
+ if (!memcmp(&guid, &guid_vendor1, sizeof(efi_guid_t)) &&
!efi_st_strcmp_16_8(varname, "efi_st_var1"))
flag |= 2;
}
}
#endif
+int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size)
+{
+ const char *path;
+ int offset, err;
+
+ if (!is_valid_ethaddr(mac))
+ return -EINVAL;
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return 0;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ debug("ethernet alias points to absent node %s\n", path);
+ return -ENOENT;
+ }
+
+ err = fdt_setprop_inplace(fdt, offset, "local-mac-address", mac, size);
+ if (err < 0)
+ return err;
+
+ debug("MAC address: %pM\n", mac);
+
+ return 0;
+}
+
static int fdtdec_init_reserved_memory(void *blob)
{
int na, ns, node, err;
fdt32_t cells[4] = {}, *ptr = cells;
uint32_t upper, lower, phandle;
int parent, node, na, ns, err;
+ fdt_size_t size;
char name[64];
/* create an empty /reserved-memory node if one doesn't exist */
* Unpack the start address and generate the name of the new node
* base on the basename and the unit-address.
*/
- lower = fdt_addr_unpack(carveout->start, &upper);
+ upper = upper_32_bits(carveout->start);
+ lower = lower_32_bits(carveout->start);
if (na > 1 && upper > 0)
snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
*ptr++ = cpu_to_fdt32(lower);
/* store one or two size cells */
- lower = fdt_size_unpack(carveout->end - carveout->start + 1, &upper);
+ size = carveout->end - carveout->start + 1;
+ upper = upper_32_bits(size);
+ lower = lower_32_bits(size);
if (ns > 1)
*ptr++ = cpu_to_fdt32(upper);
};
fdt32_t cells[4], *ptr = cells;
uint32_t upper, lower;
+ fdt_size_t size;
char name[32];
int offset;
/* store one or two address cells */
- lower = fdt_addr_unpack(carveout.start, &upper);
+ upper = upper_32_bits(carveout.start);
+ lower = lower_32_bits(carveout.start);
if (na > 1 && upper > 0)
snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
*ptr++ = cpu_to_fdt32(lower);
/* store one or two size cells */
- lower = fdt_size_unpack(carveout.end - carveout.start + 1, &upper);
+ size = carveout.end - carveout.start + 1;
+ upper = upper_32_bits(size);
+ lower = lower_32_bits(size);
if (ns > 1)
*ptr++ = cpu_to_fdt32(upper);
}
#endif
+char * strndup(const char *s, size_t n)
+{
+ size_t len;
+ char *new;
+
+ if (s == NULL)
+ return NULL;
+
+ len = strlen(s);
+
+ if (n < len)
+ len = n;
+
+ new = malloc(len + 1);
+ if (new == NULL)
+ return NULL;
+
+ strncpy(new, s, len);
+ new[len] = '\0';
+
+ return new;
+}
+
#ifndef __HAVE_ARCH_STRSPN
/**
* strspn - Calculate the length of the initial substring of @s which only
return tick_to_time(get_ticks() * 1000);
}
-static uint64_t usec_to_tick(unsigned long usec)
+uint64_t usec_to_tick(unsigned long usec)
{
uint64_t tick = usec;
tick *= get_tbclk();
/*
* uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
*
- * @param uuid_bin - pointer to binary data of UUID (big endian) [16B]
- * @param uuid_str - pointer to allocated array for output string [37B]
- * @str_format - UUID string format: 0 - UUID; 1 - GUID
+ * @param uuid_bin: pointer to binary data of UUID (big endian) [16B]
+ * @param uuid_str: pointer to allocated array for output string [37B]
+ * @str_format: bit 0: 0 - UUID; 1 - GUID
+ * bit 1: 0 - lower case; 2 - upper case
*/
void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format)
{
const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8,
9, 10, 11, 12, 13, 14, 15};
const u8 *char_order;
+ const char *format;
int i;
/*
* 4B-2B-2B-2B-6B
* be be be be be
*/
- if (str_format == UUID_STR_FORMAT_STD)
+ if (str_format & UUID_STR_FORMAT_GUID)
+ char_order = guid_char_order;
+ else
char_order = uuid_char_order;
+ if (str_format & UUID_STR_UPPER_CASE)
+ format = "%02X";
else
- char_order = guid_char_order;
+ format = "%02x";
for (i = 0; i < 16; i++) {
- sprintf(uuid_str, "%02x", uuid_bin[char_order[i]]);
+ sprintf(uuid_str, format, uuid_bin[char_order[i]]);
uuid_str += 2;
switch (i) {
case 3:
unsigned int *ptr = (unsigned int *)&uuid;
int i;
+ srand(get_ticks() + rand());
+
/* Set all fields randomly */
for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++)
*(ptr + i) = cpu_to_be32(rand());
#include <efi_loader.h>
#include <div64.h>
#include <hexdump.h>
-#include <uuid.h>
#include <stdarg.h>
#include <linux/ctype.h>
#include <linux/err.h>
return buf;
}
+#if CONFIG_IS_ENABLED(EFI_DEVICE_PATH_TO_TEXT)
static char *device_path_string(char *buf, char *end, void *dp, int field_width,
int precision, int flags)
{
return buf;
}
#endif
+#endif
#ifdef CONFIG_CMD_NET
static char *mac_address_string(char *buf, char *end, u8 *addr, int field_width,
#ifdef CONFIG_LIB_UUID
/*
- * This works (roughly) the same way as linux's, but we currently always
- * print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
- * mostly just because that is what uuid_bin_to_str() supports.
+ * This works (roughly) the same way as Linux's.
*
* %pUb: 01020304-0506-0708-090a-0b0c0d0e0f10
+ * %pUB: 01020304-0506-0708-090A-0B0C0D0E0F10
* %pUl: 04030201-0605-0807-090a-0b0c0d0e0f10
+ * %pUL: 04030201-0605-0807-090A-0B0C0D0E0F10
*/
static char *uuid_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags, const char *fmt)
{
char uuid[UUID_STR_LEN + 1];
- int str_format = UUID_STR_FORMAT_STD;
+ int str_format;
switch (*(++fmt)) {
case 'L':
+ str_format = UUID_STR_FORMAT_GUID | UUID_STR_UPPER_CASE;
+ break;
case 'l':
str_format = UUID_STR_FORMAT_GUID;
break;
case 'B':
- case 'b':
- /* this is the default */
+ str_format = UUID_STR_FORMAT_STD | UUID_STR_UPPER_CASE;
break;
default:
+ str_format = UUID_STR_FORMAT_STD;
break;
}
switch (*fmt) {
/* Device paths only exist in the EFI context. */
-#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
+#if CONFIG_IS_ENABLED(EFI_DEVICE_PATH_TO_TEXT) && !defined(API_BUILD)
case 'D':
return device_path_string(buf, end, ptr, field_width,
precision, flags);
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause)
+/*
+ * xxHash - Extremely Fast Hash algorithm
+ * Copyright (C) 2012-2016, Yann Collet.
+ *
+ * You can contact the author at:
+ * - xxHash homepage: http://cyan4973.github.io/xxHash/
+ * - xxHash source repository: https://github.com/Cyan4973/xxHash
+ */
+
+#include <asm/unaligned.h>
+#include <linux/errno.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/compat.h>
+#include <linux/string.h>
+#include <linux/xxhash.h>
+
+/*-*************************************
+ * Macros
+ **************************************/
+#define xxh_rotl32(x, r) ((x << r) | (x >> (32 - r)))
+#define xxh_rotl64(x, r) ((x << r) | (x >> (64 - r)))
+
+#ifdef __LITTLE_ENDIAN
+# define XXH_CPU_LITTLE_ENDIAN 1
+#else
+# define XXH_CPU_LITTLE_ENDIAN 0
+#endif
+
+/*-*************************************
+ * Constants
+ **************************************/
+static const uint32_t PRIME32_1 = 2654435761U;
+static const uint32_t PRIME32_2 = 2246822519U;
+static const uint32_t PRIME32_3 = 3266489917U;
+static const uint32_t PRIME32_4 = 668265263U;
+static const uint32_t PRIME32_5 = 374761393U;
+
+static const uint64_t PRIME64_1 = 11400714785074694791ULL;
+static const uint64_t PRIME64_2 = 14029467366897019727ULL;
+static const uint64_t PRIME64_3 = 1609587929392839161ULL;
+static const uint64_t PRIME64_4 = 9650029242287828579ULL;
+static const uint64_t PRIME64_5 = 2870177450012600261ULL;
+
+/*-**************************
+ * Utils
+ ***************************/
+void xxh32_copy_state(struct xxh32_state *dst, const struct xxh32_state *src)
+{
+ memcpy(dst, src, sizeof(*dst));
+}
+EXPORT_SYMBOL(xxh32_copy_state);
+
+void xxh64_copy_state(struct xxh64_state *dst, const struct xxh64_state *src)
+{
+ memcpy(dst, src, sizeof(*dst));
+}
+EXPORT_SYMBOL(xxh64_copy_state);
+
+/*-***************************
+ * Simple Hash Functions
+ ****************************/
+static uint32_t xxh32_round(uint32_t seed, const uint32_t input)
+{
+ seed += input * PRIME32_2;
+ seed = xxh_rotl32(seed, 13);
+ seed *= PRIME32_1;
+ return seed;
+}
+
+uint32_t xxh32(const void *input, const size_t len, const uint32_t seed)
+{
+ const uint8_t *p = (const uint8_t *)input;
+ const uint8_t *b_end = p + len;
+ uint32_t h32;
+
+ if (len >= 16) {
+ const uint8_t *const limit = b_end - 16;
+ uint32_t v1 = seed + PRIME32_1 + PRIME32_2;
+ uint32_t v2 = seed + PRIME32_2;
+ uint32_t v3 = seed + 0;
+ uint32_t v4 = seed - PRIME32_1;
+
+ do {
+ v1 = xxh32_round(v1, get_unaligned_le32(p));
+ p += 4;
+ v2 = xxh32_round(v2, get_unaligned_le32(p));
+ p += 4;
+ v3 = xxh32_round(v3, get_unaligned_le32(p));
+ p += 4;
+ v4 = xxh32_round(v4, get_unaligned_le32(p));
+ p += 4;
+ } while (p <= limit);
+
+ h32 = xxh_rotl32(v1, 1) + xxh_rotl32(v2, 7) +
+ xxh_rotl32(v3, 12) + xxh_rotl32(v4, 18);
+ } else {
+ h32 = seed + PRIME32_5;
+ }
+
+ h32 += (uint32_t)len;
+
+ while (p + 4 <= b_end) {
+ h32 += get_unaligned_le32(p) * PRIME32_3;
+ h32 = xxh_rotl32(h32, 17) * PRIME32_4;
+ p += 4;
+ }
+
+ while (p < b_end) {
+ h32 += (*p) * PRIME32_5;
+ h32 = xxh_rotl32(h32, 11) * PRIME32_1;
+ p++;
+ }
+
+ h32 ^= h32 >> 15;
+ h32 *= PRIME32_2;
+ h32 ^= h32 >> 13;
+ h32 *= PRIME32_3;
+ h32 ^= h32 >> 16;
+
+ return h32;
+}
+EXPORT_SYMBOL(xxh32);
+
+static uint64_t xxh64_round(uint64_t acc, const uint64_t input)
+{
+ acc += input * PRIME64_2;
+ acc = xxh_rotl64(acc, 31);
+ acc *= PRIME64_1;
+ return acc;
+}
+
+static uint64_t xxh64_merge_round(uint64_t acc, uint64_t val)
+{
+ val = xxh64_round(0, val);
+ acc ^= val;
+ acc = acc * PRIME64_1 + PRIME64_4;
+ return acc;
+}
+
+uint64_t xxh64(const void *input, const size_t len, const uint64_t seed)
+{
+ const uint8_t *p = (const uint8_t *)input;
+ const uint8_t *const b_end = p + len;
+ uint64_t h64;
+
+ if (len >= 32) {
+ const uint8_t *const limit = b_end - 32;
+ uint64_t v1 = seed + PRIME64_1 + PRIME64_2;
+ uint64_t v2 = seed + PRIME64_2;
+ uint64_t v3 = seed + 0;
+ uint64_t v4 = seed - PRIME64_1;
+
+ do {
+ v1 = xxh64_round(v1, get_unaligned_le64(p));
+ p += 8;
+ v2 = xxh64_round(v2, get_unaligned_le64(p));
+ p += 8;
+ v3 = xxh64_round(v3, get_unaligned_le64(p));
+ p += 8;
+ v4 = xxh64_round(v4, get_unaligned_le64(p));
+ p += 8;
+ } while (p <= limit);
+
+ h64 = xxh_rotl64(v1, 1) + xxh_rotl64(v2, 7) +
+ xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18);
+ h64 = xxh64_merge_round(h64, v1);
+ h64 = xxh64_merge_round(h64, v2);
+ h64 = xxh64_merge_round(h64, v3);
+ h64 = xxh64_merge_round(h64, v4);
+
+ } else {
+ h64 = seed + PRIME64_5;
+ }
+
+ h64 += (uint64_t)len;
+
+ while (p + 8 <= b_end) {
+ const uint64_t k1 = xxh64_round(0, get_unaligned_le64(p));
+
+ h64 ^= k1;
+ h64 = xxh_rotl64(h64, 27) * PRIME64_1 + PRIME64_4;
+ p += 8;
+ }
+
+ if (p + 4 <= b_end) {
+ h64 ^= (uint64_t)(get_unaligned_le32(p)) * PRIME64_1;
+ h64 = xxh_rotl64(h64, 23) * PRIME64_2 + PRIME64_3;
+ p += 4;
+ }
+
+ while (p < b_end) {
+ h64 ^= (*p) * PRIME64_5;
+ h64 = xxh_rotl64(h64, 11) * PRIME64_1;
+ p++;
+ }
+
+ h64 ^= h64 >> 33;
+ h64 *= PRIME64_2;
+ h64 ^= h64 >> 29;
+ h64 *= PRIME64_3;
+ h64 ^= h64 >> 32;
+
+ return h64;
+}
+EXPORT_SYMBOL(xxh64);
+
+/*-**************************************************
+ * Advanced Hash Functions
+ ***************************************************/
+void xxh32_reset(struct xxh32_state *statePtr, const uint32_t seed)
+{
+ /* use a local state for memcpy() to avoid strict-aliasing warnings */
+ struct xxh32_state state;
+
+ memset(&state, 0, sizeof(state));
+ state.v1 = seed + PRIME32_1 + PRIME32_2;
+ state.v2 = seed + PRIME32_2;
+ state.v3 = seed + 0;
+ state.v4 = seed - PRIME32_1;
+ memcpy(statePtr, &state, sizeof(state));
+}
+EXPORT_SYMBOL(xxh32_reset);
+
+void xxh64_reset(struct xxh64_state *statePtr, const uint64_t seed)
+{
+ /* use a local state for memcpy() to avoid strict-aliasing warnings */
+ struct xxh64_state state;
+
+ memset(&state, 0, sizeof(state));
+ state.v1 = seed + PRIME64_1 + PRIME64_2;
+ state.v2 = seed + PRIME64_2;
+ state.v3 = seed + 0;
+ state.v4 = seed - PRIME64_1;
+ memcpy(statePtr, &state, sizeof(state));
+}
+EXPORT_SYMBOL(xxh64_reset);
+
+int xxh32_update(struct xxh32_state *state, const void *input, const size_t len)
+{
+ const uint8_t *p = (const uint8_t *)input;
+ const uint8_t *const b_end = p + len;
+
+ if (input == NULL)
+ return -EINVAL;
+
+ state->total_len_32 += (uint32_t)len;
+ state->large_len |= (len >= 16) | (state->total_len_32 >= 16);
+
+ if (state->memsize + len < 16) { /* fill in tmp buffer */
+ memcpy((uint8_t *)(state->mem32) + state->memsize, input, len);
+ state->memsize += (uint32_t)len;
+ return 0;
+ }
+
+ if (state->memsize) { /* some data left from previous update */
+ const uint32_t *p32 = state->mem32;
+
+ memcpy((uint8_t *)(state->mem32) + state->memsize, input,
+ 16 - state->memsize);
+
+ state->v1 = xxh32_round(state->v1, get_unaligned_le32(p32));
+ p32++;
+ state->v2 = xxh32_round(state->v2, get_unaligned_le32(p32));
+ p32++;
+ state->v3 = xxh32_round(state->v3, get_unaligned_le32(p32));
+ p32++;
+ state->v4 = xxh32_round(state->v4, get_unaligned_le32(p32));
+ p32++;
+
+ p += 16-state->memsize;
+ state->memsize = 0;
+ }
+
+ if (p <= b_end - 16) {
+ const uint8_t *const limit = b_end - 16;
+ uint32_t v1 = state->v1;
+ uint32_t v2 = state->v2;
+ uint32_t v3 = state->v3;
+ uint32_t v4 = state->v4;
+
+ do {
+ v1 = xxh32_round(v1, get_unaligned_le32(p));
+ p += 4;
+ v2 = xxh32_round(v2, get_unaligned_le32(p));
+ p += 4;
+ v3 = xxh32_round(v3, get_unaligned_le32(p));
+ p += 4;
+ v4 = xxh32_round(v4, get_unaligned_le32(p));
+ p += 4;
+ } while (p <= limit);
+
+ state->v1 = v1;
+ state->v2 = v2;
+ state->v3 = v3;
+ state->v4 = v4;
+ }
+
+ if (p < b_end) {
+ memcpy(state->mem32, p, (size_t)(b_end-p));
+ state->memsize = (uint32_t)(b_end-p);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(xxh32_update);
+
+uint32_t xxh32_digest(const struct xxh32_state *state)
+{
+ const uint8_t *p = (const uint8_t *)state->mem32;
+ const uint8_t *const b_end = (const uint8_t *)(state->mem32) +
+ state->memsize;
+ uint32_t h32;
+
+ if (state->large_len) {
+ h32 = xxh_rotl32(state->v1, 1) + xxh_rotl32(state->v2, 7) +
+ xxh_rotl32(state->v3, 12) + xxh_rotl32(state->v4, 18);
+ } else {
+ h32 = state->v3 /* == seed */ + PRIME32_5;
+ }
+
+ h32 += state->total_len_32;
+
+ while (p + 4 <= b_end) {
+ h32 += get_unaligned_le32(p) * PRIME32_3;
+ h32 = xxh_rotl32(h32, 17) * PRIME32_4;
+ p += 4;
+ }
+
+ while (p < b_end) {
+ h32 += (*p) * PRIME32_5;
+ h32 = xxh_rotl32(h32, 11) * PRIME32_1;
+ p++;
+ }
+
+ h32 ^= h32 >> 15;
+ h32 *= PRIME32_2;
+ h32 ^= h32 >> 13;
+ h32 *= PRIME32_3;
+ h32 ^= h32 >> 16;
+
+ return h32;
+}
+EXPORT_SYMBOL(xxh32_digest);
+
+int xxh64_update(struct xxh64_state *state, const void *input, const size_t len)
+{
+ const uint8_t *p = (const uint8_t *)input;
+ const uint8_t *const b_end = p + len;
+
+ if (input == NULL)
+ return -EINVAL;
+
+ state->total_len += len;
+
+ if (state->memsize + len < 32) { /* fill in tmp buffer */
+ memcpy(((uint8_t *)state->mem64) + state->memsize, input, len);
+ state->memsize += (uint32_t)len;
+ return 0;
+ }
+
+ if (state->memsize) { /* tmp buffer is full */
+ uint64_t *p64 = state->mem64;
+
+ memcpy(((uint8_t *)p64) + state->memsize, input,
+ 32 - state->memsize);
+
+ state->v1 = xxh64_round(state->v1, get_unaligned_le64(p64));
+ p64++;
+ state->v2 = xxh64_round(state->v2, get_unaligned_le64(p64));
+ p64++;
+ state->v3 = xxh64_round(state->v3, get_unaligned_le64(p64));
+ p64++;
+ state->v4 = xxh64_round(state->v4, get_unaligned_le64(p64));
+
+ p += 32 - state->memsize;
+ state->memsize = 0;
+ }
+
+ if (p + 32 <= b_end) {
+ const uint8_t *const limit = b_end - 32;
+ uint64_t v1 = state->v1;
+ uint64_t v2 = state->v2;
+ uint64_t v3 = state->v3;
+ uint64_t v4 = state->v4;
+
+ do {
+ v1 = xxh64_round(v1, get_unaligned_le64(p));
+ p += 8;
+ v2 = xxh64_round(v2, get_unaligned_le64(p));
+ p += 8;
+ v3 = xxh64_round(v3, get_unaligned_le64(p));
+ p += 8;
+ v4 = xxh64_round(v4, get_unaligned_le64(p));
+ p += 8;
+ } while (p <= limit);
+
+ state->v1 = v1;
+ state->v2 = v2;
+ state->v3 = v3;
+ state->v4 = v4;
+ }
+
+ if (p < b_end) {
+ memcpy(state->mem64, p, (size_t)(b_end-p));
+ state->memsize = (uint32_t)(b_end - p);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(xxh64_update);
+
+uint64_t xxh64_digest(const struct xxh64_state *state)
+{
+ const uint8_t *p = (const uint8_t *)state->mem64;
+ const uint8_t *const b_end = (const uint8_t *)state->mem64 +
+ state->memsize;
+ uint64_t h64;
+
+ if (state->total_len >= 32) {
+ const uint64_t v1 = state->v1;
+ const uint64_t v2 = state->v2;
+ const uint64_t v3 = state->v3;
+ const uint64_t v4 = state->v4;
+
+ h64 = xxh_rotl64(v1, 1) + xxh_rotl64(v2, 7) +
+ xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18);
+ h64 = xxh64_merge_round(h64, v1);
+ h64 = xxh64_merge_round(h64, v2);
+ h64 = xxh64_merge_round(h64, v3);
+ h64 = xxh64_merge_round(h64, v4);
+ } else {
+ h64 = state->v3 + PRIME64_5;
+ }
+
+ h64 += (uint64_t)state->total_len;
+
+ while (p + 8 <= b_end) {
+ const uint64_t k1 = xxh64_round(0, get_unaligned_le64(p));
+
+ h64 ^= k1;
+ h64 = xxh_rotl64(h64, 27) * PRIME64_1 + PRIME64_4;
+ p += 8;
+ }
+
+ if (p + 4 <= b_end) {
+ h64 ^= (uint64_t)(get_unaligned_le32(p)) * PRIME64_1;
+ h64 = xxh_rotl64(h64, 23) * PRIME64_2 + PRIME64_3;
+ p += 4;
+ }
+
+ while (p < b_end) {
+ h64 ^= (*p) * PRIME64_5;
+ h64 = xxh_rotl64(h64, 11) * PRIME64_1;
+ p++;
+ }
+
+ h64 ^= h64 >> 33;
+ h64 *= PRIME64_2;
+ h64 ^= h64 >> 29;
+ h64 *= PRIME64_3;
+ h64 ^= h64 >> 32;
+
+ return h64;
+}
+EXPORT_SYMBOL(xxh64_digest);
--- /dev/null
+obj-y += zstd_decompress.o
+
+zstd_decompress-y := huf_decompress.o decompress.o \
+ entropy_common.o fse_decompress.o zstd_common.o
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) */
+/*
+ * bitstream
+ * Part of FSE library
+ * header file (to include)
+ * Copyright (C) 2013-2016, Yann Collet.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ */
+#ifndef BITSTREAM_H_MODULE
+#define BITSTREAM_H_MODULE
+
+/*
+* This API consists of small unitary functions, which must be inlined for best performance.
+* Since link-time-optimization is not available for all compilers,
+* these functions are defined into a .h to be included.
+*/
+
+/*-****************************************
+* Dependencies
+******************************************/
+#include "error_private.h" /* error codes and messages */
+#include "mem.h" /* unaligned access routines */
+
+/*=========================================
+* Target specific
+=========================================*/
+#define STREAM_ACCUMULATOR_MIN_32 25
+#define STREAM_ACCUMULATOR_MIN_64 57
+#define STREAM_ACCUMULATOR_MIN ((U32)(ZSTD_32bits() ? STREAM_ACCUMULATOR_MIN_32 : STREAM_ACCUMULATOR_MIN_64))
+
+/*-******************************************
+* bitStream encoding API (write forward)
+********************************************/
+/* bitStream can mix input from multiple sources.
+* A critical property of these streams is that they encode and decode in **reverse** direction.
+* So the first bit sequence you add will be the last to be read, like a LIFO stack.
+*/
+typedef struct {
+ size_t bitContainer;
+ int bitPos;
+ char *startPtr;
+ char *ptr;
+ char *endPtr;
+} BIT_CStream_t;
+
+ZSTD_STATIC size_t BIT_initCStream(BIT_CStream_t *bitC, void *dstBuffer, size_t dstCapacity);
+ZSTD_STATIC void BIT_addBits(BIT_CStream_t *bitC, size_t value, unsigned nbBits);
+ZSTD_STATIC void BIT_flushBits(BIT_CStream_t *bitC);
+ZSTD_STATIC size_t BIT_closeCStream(BIT_CStream_t *bitC);
+
+/* Start with initCStream, providing the size of buffer to write into.
+* bitStream will never write outside of this buffer.
+* `dstCapacity` must be >= sizeof(bitD->bitContainer), otherwise @return will be an error code.
+*
+* bits are first added to a local register.
+* Local register is size_t, hence 64-bits on 64-bits systems, or 32-bits on 32-bits systems.
+* Writing data into memory is an explicit operation, performed by the flushBits function.
+* Hence keep track how many bits are potentially stored into local register to avoid register overflow.
+* After a flushBits, a maximum of 7 bits might still be stored into local register.
+*
+* Avoid storing elements of more than 24 bits if you want compatibility with 32-bits bitstream readers.
+*
+* Last operation is to close the bitStream.
+* The function returns the final size of CStream in bytes.
+* If data couldn't fit into `dstBuffer`, it will return a 0 ( == not storable)
+*/
+
+/*-********************************************
+* bitStream decoding API (read backward)
+**********************************************/
+typedef struct {
+ size_t bitContainer;
+ unsigned bitsConsumed;
+ const char *ptr;
+ const char *start;
+} BIT_DStream_t;
+
+typedef enum {
+ BIT_DStream_unfinished = 0,
+ BIT_DStream_endOfBuffer = 1,
+ BIT_DStream_completed = 2,
+ BIT_DStream_overflow = 3
+} BIT_DStream_status; /* result of BIT_reloadDStream() */
+/* 1,2,4,8 would be better for bitmap combinations, but slows down performance a bit ... :( */
+
+ZSTD_STATIC size_t BIT_initDStream(BIT_DStream_t *bitD, const void *srcBuffer, size_t srcSize);
+ZSTD_STATIC size_t BIT_readBits(BIT_DStream_t *bitD, unsigned nbBits);
+ZSTD_STATIC BIT_DStream_status BIT_reloadDStream(BIT_DStream_t *bitD);
+ZSTD_STATIC unsigned BIT_endOfDStream(const BIT_DStream_t *bitD);
+
+/* Start by invoking BIT_initDStream().
+* A chunk of the bitStream is then stored into a local register.
+* Local register size is 64-bits on 64-bits systems, 32-bits on 32-bits systems (size_t).
+* You can then retrieve bitFields stored into the local register, **in reverse order**.
+* Local register is explicitly reloaded from memory by the BIT_reloadDStream() method.
+* A reload guarantee a minimum of ((8*sizeof(bitD->bitContainer))-7) bits when its result is BIT_DStream_unfinished.
+* Otherwise, it can be less than that, so proceed accordingly.
+* Checking if DStream has reached its end can be performed with BIT_endOfDStream().
+*/
+
+/*-****************************************
+* unsafe API
+******************************************/
+ZSTD_STATIC void BIT_addBitsFast(BIT_CStream_t *bitC, size_t value, unsigned nbBits);
+/* faster, but works only if value is "clean", meaning all high bits above nbBits are 0 */
+
+ZSTD_STATIC void BIT_flushBitsFast(BIT_CStream_t *bitC);
+/* unsafe version; does not check buffer overflow */
+
+ZSTD_STATIC size_t BIT_readBitsFast(BIT_DStream_t *bitD, unsigned nbBits);
+/* faster, but works only if nbBits >= 1 */
+
+/*-**************************************************************
+* Internal functions
+****************************************************************/
+ZSTD_STATIC unsigned BIT_highbit32(register U32 val) { return 31 - __builtin_clz(val); }
+
+/*===== Local Constants =====*/
+static const unsigned BIT_mask[] = {0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF,
+ 0x1FF, 0x3FF, 0x7FF, 0xFFF, 0x1FFF, 0x3FFF, 0x7FFF, 0xFFFF, 0x1FFFF,
+ 0x3FFFF, 0x7FFFF, 0xFFFFF, 0x1FFFFF, 0x3FFFFF, 0x7FFFFF, 0xFFFFFF, 0x1FFFFFF, 0x3FFFFFF}; /* up to 26 bits */
+
+/*-**************************************************************
+* bitStream encoding
+****************************************************************/
+/*! BIT_initCStream() :
+ * `dstCapacity` must be > sizeof(void*)
+ * @return : 0 if success,
+ otherwise an error code (can be tested using ERR_isError() ) */
+ZSTD_STATIC size_t BIT_initCStream(BIT_CStream_t *bitC, void *startPtr, size_t dstCapacity)
+{
+ bitC->bitContainer = 0;
+ bitC->bitPos = 0;
+ bitC->startPtr = (char *)startPtr;
+ bitC->ptr = bitC->startPtr;
+ bitC->endPtr = bitC->startPtr + dstCapacity - sizeof(bitC->ptr);
+ if (dstCapacity <= sizeof(bitC->ptr))
+ return ERROR(dstSize_tooSmall);
+ return 0;
+}
+
+/*! BIT_addBits() :
+ can add up to 26 bits into `bitC`.
+ Does not check for register overflow ! */
+ZSTD_STATIC void BIT_addBits(BIT_CStream_t *bitC, size_t value, unsigned nbBits)
+{
+ bitC->bitContainer |= (value & BIT_mask[nbBits]) << bitC->bitPos;
+ bitC->bitPos += nbBits;
+}
+
+/*! BIT_addBitsFast() :
+ * works only if `value` is _clean_, meaning all high bits above nbBits are 0 */
+ZSTD_STATIC void BIT_addBitsFast(BIT_CStream_t *bitC, size_t value, unsigned nbBits)
+{
+ bitC->bitContainer |= value << bitC->bitPos;
+ bitC->bitPos += nbBits;
+}
+
+/*! BIT_flushBitsFast() :
+ * unsafe version; does not check buffer overflow */
+ZSTD_STATIC void BIT_flushBitsFast(BIT_CStream_t *bitC)
+{
+ size_t const nbBytes = bitC->bitPos >> 3;
+ ZSTD_writeLEST(bitC->ptr, bitC->bitContainer);
+ bitC->ptr += nbBytes;
+ bitC->bitPos &= 7;
+ bitC->bitContainer >>= nbBytes * 8; /* if bitPos >= sizeof(bitContainer)*8 --> undefined behavior */
+}
+
+/*! BIT_flushBits() :
+ * safe version; check for buffer overflow, and prevents it.
+ * note : does not signal buffer overflow. This will be revealed later on using BIT_closeCStream() */
+ZSTD_STATIC void BIT_flushBits(BIT_CStream_t *bitC)
+{
+ size_t const nbBytes = bitC->bitPos >> 3;
+ ZSTD_writeLEST(bitC->ptr, bitC->bitContainer);
+ bitC->ptr += nbBytes;
+ if (bitC->ptr > bitC->endPtr)
+ bitC->ptr = bitC->endPtr;
+ bitC->bitPos &= 7;
+ bitC->bitContainer >>= nbBytes * 8; /* if bitPos >= sizeof(bitContainer)*8 --> undefined behavior */
+}
+
+/*! BIT_closeCStream() :
+ * @return : size of CStream, in bytes,
+ or 0 if it could not fit into dstBuffer */
+ZSTD_STATIC size_t BIT_closeCStream(BIT_CStream_t *bitC)
+{
+ BIT_addBitsFast(bitC, 1, 1); /* endMark */
+ BIT_flushBits(bitC);
+
+ if (bitC->ptr >= bitC->endPtr)
+ return 0; /* doesn't fit within authorized budget : cancel */
+
+ return (bitC->ptr - bitC->startPtr) + (bitC->bitPos > 0);
+}
+
+/*-********************************************************
+* bitStream decoding
+**********************************************************/
+/*! BIT_initDStream() :
+* Initialize a BIT_DStream_t.
+* `bitD` : a pointer to an already allocated BIT_DStream_t structure.
+* `srcSize` must be the *exact* size of the bitStream, in bytes.
+* @return : size of stream (== srcSize) or an errorCode if a problem is detected
+*/
+ZSTD_STATIC size_t BIT_initDStream(BIT_DStream_t *bitD, const void *srcBuffer, size_t srcSize)
+{
+ if (srcSize < 1) {
+ memset(bitD, 0, sizeof(*bitD));
+ return ERROR(srcSize_wrong);
+ }
+
+ if (srcSize >= sizeof(bitD->bitContainer)) { /* normal case */
+ bitD->start = (const char *)srcBuffer;
+ bitD->ptr = (const char *)srcBuffer + srcSize - sizeof(bitD->bitContainer);
+ bitD->bitContainer = ZSTD_readLEST(bitD->ptr);
+ {
+ BYTE const lastByte = ((const BYTE *)srcBuffer)[srcSize - 1];
+ bitD->bitsConsumed = lastByte ? 8 - BIT_highbit32(lastByte) : 0; /* ensures bitsConsumed is always set */
+ if (lastByte == 0)
+ return ERROR(GENERIC); /* endMark not present */
+ }
+ } else {
+ bitD->start = (const char *)srcBuffer;
+ bitD->ptr = bitD->start;
+ bitD->bitContainer = *(const BYTE *)(bitD->start);
+ switch (srcSize) {
+ case 7: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[6]) << (sizeof(bitD->bitContainer) * 8 - 16);
+ case 6: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[5]) << (sizeof(bitD->bitContainer) * 8 - 24);
+ case 5: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[4]) << (sizeof(bitD->bitContainer) * 8 - 32);
+ case 4: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[3]) << 24;
+ case 3: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[2]) << 16;
+ case 2: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[1]) << 8;
+ default:;
+ }
+ {
+ BYTE const lastByte = ((const BYTE *)srcBuffer)[srcSize - 1];
+ bitD->bitsConsumed = lastByte ? 8 - BIT_highbit32(lastByte) : 0;
+ if (lastByte == 0)
+ return ERROR(GENERIC); /* endMark not present */
+ }
+ bitD->bitsConsumed += (U32)(sizeof(bitD->bitContainer) - srcSize) * 8;
+ }
+
+ return srcSize;
+}
+
+ZSTD_STATIC size_t BIT_getUpperBits(size_t bitContainer, U32 const start) { return bitContainer >> start; }
+
+ZSTD_STATIC size_t BIT_getMiddleBits(size_t bitContainer, U32 const start, U32 const nbBits) { return (bitContainer >> start) & BIT_mask[nbBits]; }
+
+ZSTD_STATIC size_t BIT_getLowerBits(size_t bitContainer, U32 const nbBits) { return bitContainer & BIT_mask[nbBits]; }
+
+/*! BIT_lookBits() :
+ * Provides next n bits from local register.
+ * local register is not modified.
+ * On 32-bits, maxNbBits==24.
+ * On 64-bits, maxNbBits==56.
+ * @return : value extracted
+ */
+ZSTD_STATIC size_t BIT_lookBits(const BIT_DStream_t *bitD, U32 nbBits)
+{
+ U32 const bitMask = sizeof(bitD->bitContainer) * 8 - 1;
+ return ((bitD->bitContainer << (bitD->bitsConsumed & bitMask)) >> 1) >> ((bitMask - nbBits) & bitMask);
+}
+
+/*! BIT_lookBitsFast() :
+* unsafe version; only works only if nbBits >= 1 */
+ZSTD_STATIC size_t BIT_lookBitsFast(const BIT_DStream_t *bitD, U32 nbBits)
+{
+ U32 const bitMask = sizeof(bitD->bitContainer) * 8 - 1;
+ return (bitD->bitContainer << (bitD->bitsConsumed & bitMask)) >> (((bitMask + 1) - nbBits) & bitMask);
+}
+
+ZSTD_STATIC void BIT_skipBits(BIT_DStream_t *bitD, U32 nbBits) { bitD->bitsConsumed += nbBits; }
+
+/*! BIT_readBits() :
+ * Read (consume) next n bits from local register and update.
+ * Pay attention to not read more than nbBits contained into local register.
+ * @return : extracted value.
+ */
+ZSTD_STATIC size_t BIT_readBits(BIT_DStream_t *bitD, U32 nbBits)
+{
+ size_t const value = BIT_lookBits(bitD, nbBits);
+ BIT_skipBits(bitD, nbBits);
+ return value;
+}
+
+/*! BIT_readBitsFast() :
+* unsafe version; only works only if nbBits >= 1 */
+ZSTD_STATIC size_t BIT_readBitsFast(BIT_DStream_t *bitD, U32 nbBits)
+{
+ size_t const value = BIT_lookBitsFast(bitD, nbBits);
+ BIT_skipBits(bitD, nbBits);
+ return value;
+}
+
+/*! BIT_reloadDStream() :
+* Refill `bitD` from buffer previously set in BIT_initDStream() .
+* This function is safe, it guarantees it will not read beyond src buffer.
+* @return : status of `BIT_DStream_t` internal register.
+ if status == BIT_DStream_unfinished, internal register is filled with >= (sizeof(bitD->bitContainer)*8 - 7) bits */
+ZSTD_STATIC BIT_DStream_status BIT_reloadDStream(BIT_DStream_t *bitD)
+{
+ if (bitD->bitsConsumed > (sizeof(bitD->bitContainer) * 8)) /* should not happen => corruption detected */
+ return BIT_DStream_overflow;
+
+ if (bitD->ptr >= bitD->start + sizeof(bitD->bitContainer)) {
+ bitD->ptr -= bitD->bitsConsumed >> 3;
+ bitD->bitsConsumed &= 7;
+ bitD->bitContainer = ZSTD_readLEST(bitD->ptr);
+ return BIT_DStream_unfinished;
+ }
+ if (bitD->ptr == bitD->start) {
+ if (bitD->bitsConsumed < sizeof(bitD->bitContainer) * 8)
+ return BIT_DStream_endOfBuffer;
+ return BIT_DStream_completed;
+ }
+ {
+ U32 nbBytes = bitD->bitsConsumed >> 3;
+ BIT_DStream_status result = BIT_DStream_unfinished;
+ if (bitD->ptr - nbBytes < bitD->start) {
+ nbBytes = (U32)(bitD->ptr - bitD->start); /* ptr > start */
+ result = BIT_DStream_endOfBuffer;
+ }
+ bitD->ptr -= nbBytes;
+ bitD->bitsConsumed -= nbBytes * 8;
+ bitD->bitContainer = ZSTD_readLEST(bitD->ptr); /* reminder : srcSize > sizeof(bitD) */
+ return result;
+ }
+}
+
+/*! BIT_endOfDStream() :
+* @return Tells if DStream has exactly reached its end (all bits consumed).
+*/
+ZSTD_STATIC unsigned BIT_endOfDStream(const BIT_DStream_t *DStream)
+{
+ return ((DStream->ptr == DStream->start) && (DStream->bitsConsumed == sizeof(DStream->bitContainer) * 8));
+}
+
+#endif /* BITSTREAM_H_MODULE */
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear)
+/**
+ * Copyright (c) 2016-present, Yann Collet, Facebook, Inc.
+ * All rights reserved.
+ */
+
+/* ***************************************************************
+* Tuning parameters
+*****************************************************************/
+/*!
+* MAXWINDOWSIZE_DEFAULT :
+* maximum window size accepted by DStream, by default.
+* Frames requiring more memory will be rejected.
+*/
+#ifndef ZSTD_MAXWINDOWSIZE_DEFAULT
+#define ZSTD_MAXWINDOWSIZE_DEFAULT ((1 << ZSTD_WINDOWLOG_MAX) + 1) /* defined within zstd.h */
+#endif
+
+/*-*******************************************************
+* Dependencies
+*********************************************************/
+#include "fse.h"
+#include "huf.h"
+#include "mem.h" /* low level memory routines */
+#include "zstd_internal.h"
+#include <linux/kernel.h>
+#include <linux/compat.h>
+#include <linux/string.h> /* memcpy, memmove, memset */
+
+#define ZSTD_PREFETCH(ptr) __builtin_prefetch(ptr, 0, 0)
+
+/*-*************************************
+* Macros
+***************************************/
+#define ZSTD_isError ERR_isError /* for inlining */
+#define FSE_isError ERR_isError
+#define HUF_isError ERR_isError
+
+/*_*******************************************************
+* Memory operations
+**********************************************************/
+static void ZSTD_copy4(void *dst, const void *src) { memcpy(dst, src, 4); }
+
+/*-*************************************************************
+* Context management
+***************************************************************/
+typedef enum {
+ ZSTDds_getFrameHeaderSize,
+ ZSTDds_decodeFrameHeader,
+ ZSTDds_decodeBlockHeader,
+ ZSTDds_decompressBlock,
+ ZSTDds_decompressLastBlock,
+ ZSTDds_checkChecksum,
+ ZSTDds_decodeSkippableHeader,
+ ZSTDds_skipFrame
+} ZSTD_dStage;
+
+typedef struct {
+ FSE_DTable LLTable[FSE_DTABLE_SIZE_U32(LLFSELog)];
+ FSE_DTable OFTable[FSE_DTABLE_SIZE_U32(OffFSELog)];
+ FSE_DTable MLTable[FSE_DTABLE_SIZE_U32(MLFSELog)];
+ HUF_DTable hufTable[HUF_DTABLE_SIZE(HufLog)]; /* can accommodate HUF_decompress4X */
+ U64 workspace[HUF_DECOMPRESS_WORKSPACE_SIZE_U32 / 2];
+ U32 rep[ZSTD_REP_NUM];
+} ZSTD_entropyTables_t;
+
+struct ZSTD_DCtx_s {
+ const FSE_DTable *LLTptr;
+ const FSE_DTable *MLTptr;
+ const FSE_DTable *OFTptr;
+ const HUF_DTable *HUFptr;
+ ZSTD_entropyTables_t entropy;
+ const void *previousDstEnd; /* detect continuity */
+ const void *base; /* start of curr segment */
+ const void *vBase; /* virtual start of previous segment if it was just before curr one */
+ const void *dictEnd; /* end of previous segment */
+ size_t expected;
+ ZSTD_frameParams fParams;
+ blockType_e bType; /* used in ZSTD_decompressContinue(), to transfer blockType between header decoding and block decoding stages */
+ ZSTD_dStage stage;
+ U32 litEntropy;
+ U32 fseEntropy;
+ struct xxh64_state xxhState;
+ size_t headerSize;
+ U32 dictID;
+ const BYTE *litPtr;
+ ZSTD_customMem customMem;
+ size_t litSize;
+ size_t rleSize;
+ BYTE litBuffer[ZSTD_BLOCKSIZE_ABSOLUTEMAX + WILDCOPY_OVERLENGTH];
+ BYTE headerBuffer[ZSTD_FRAMEHEADERSIZE_MAX];
+}; /* typedef'd to ZSTD_DCtx within "zstd.h" */
+
+size_t ZSTD_DCtxWorkspaceBound(void) { return ZSTD_ALIGN(sizeof(ZSTD_stack)) + ZSTD_ALIGN(sizeof(ZSTD_DCtx)); }
+
+size_t ZSTD_decompressBegin(ZSTD_DCtx *dctx)
+{
+ dctx->expected = ZSTD_frameHeaderSize_prefix;
+ dctx->stage = ZSTDds_getFrameHeaderSize;
+ dctx->previousDstEnd = NULL;
+ dctx->base = NULL;
+ dctx->vBase = NULL;
+ dctx->dictEnd = NULL;
+ dctx->entropy.hufTable[0] = (HUF_DTable)((HufLog)*0x1000001); /* cover both little and big endian */
+ dctx->litEntropy = dctx->fseEntropy = 0;
+ dctx->dictID = 0;
+ ZSTD_STATIC_ASSERT(sizeof(dctx->entropy.rep) == sizeof(repStartValue));
+ memcpy(dctx->entropy.rep, repStartValue, sizeof(repStartValue)); /* initial repcodes */
+ dctx->LLTptr = dctx->entropy.LLTable;
+ dctx->MLTptr = dctx->entropy.MLTable;
+ dctx->OFTptr = dctx->entropy.OFTable;
+ dctx->HUFptr = dctx->entropy.hufTable;
+ return 0;
+}
+
+ZSTD_DCtx *ZSTD_createDCtx_advanced(ZSTD_customMem customMem)
+{
+ ZSTD_DCtx *dctx;
+
+ if (!customMem.customAlloc || !customMem.customFree)
+ return NULL;
+
+ dctx = (ZSTD_DCtx *)ZSTD_malloc(sizeof(ZSTD_DCtx), customMem);
+ if (!dctx)
+ return NULL;
+ memcpy(&dctx->customMem, &customMem, sizeof(customMem));
+ ZSTD_decompressBegin(dctx);
+ return dctx;
+}
+
+ZSTD_DCtx *ZSTD_initDCtx(void *workspace, size_t workspaceSize)
+{
+ ZSTD_customMem const stackMem = ZSTD_initStack(workspace, workspaceSize);
+ return ZSTD_createDCtx_advanced(stackMem);
+}
+
+size_t ZSTD_freeDCtx(ZSTD_DCtx *dctx)
+{
+ if (dctx == NULL)
+ return 0; /* support free on NULL */
+ ZSTD_free(dctx, dctx->customMem);
+ return 0; /* reserved as a potential error code in the future */
+}
+
+void ZSTD_copyDCtx(ZSTD_DCtx *dstDCtx, const ZSTD_DCtx *srcDCtx)
+{
+ size_t const workSpaceSize = (ZSTD_BLOCKSIZE_ABSOLUTEMAX + WILDCOPY_OVERLENGTH) + ZSTD_frameHeaderSize_max;
+ memcpy(dstDCtx, srcDCtx, sizeof(ZSTD_DCtx) - workSpaceSize); /* no need to copy workspace */
+}
+
+static void ZSTD_refDDict(ZSTD_DCtx *dstDCtx, const ZSTD_DDict *ddict);
+
+/*-*************************************************************
+* Decompression section
+***************************************************************/
+
+/*! ZSTD_isFrame() :
+ * Tells if the content of `buffer` starts with a valid Frame Identifier.
+ * Note : Frame Identifier is 4 bytes. If `size < 4`, @return will always be 0.
+ * Note 2 : Legacy Frame Identifiers are considered valid only if Legacy Support is enabled.
+ * Note 3 : Skippable Frame Identifiers are considered valid. */
+unsigned ZSTD_isFrame(const void *buffer, size_t size)
+{
+ if (size < 4)
+ return 0;
+ {
+ U32 const magic = ZSTD_readLE32(buffer);
+ if (magic == ZSTD_MAGICNUMBER)
+ return 1;
+ if ((magic & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START)
+ return 1;
+ }
+ return 0;
+}
+
+/** ZSTD_frameHeaderSize() :
+* srcSize must be >= ZSTD_frameHeaderSize_prefix.
+* @return : size of the Frame Header */
+static size_t ZSTD_frameHeaderSize(const void *src, size_t srcSize)
+{
+ if (srcSize < ZSTD_frameHeaderSize_prefix)
+ return ERROR(srcSize_wrong);
+ {
+ BYTE const fhd = ((const BYTE *)src)[4];
+ U32 const dictID = fhd & 3;
+ U32 const singleSegment = (fhd >> 5) & 1;
+ U32 const fcsId = fhd >> 6;
+ return ZSTD_frameHeaderSize_prefix + !singleSegment + ZSTD_did_fieldSize[dictID] + ZSTD_fcs_fieldSize[fcsId] + (singleSegment && !fcsId);
+ }
+}
+
+/** ZSTD_getFrameParams() :
+* decode Frame Header, or require larger `srcSize`.
+* @return : 0, `fparamsPtr` is correctly filled,
+* >0, `srcSize` is too small, result is expected `srcSize`,
+* or an error code, which can be tested using ZSTD_isError() */
+size_t ZSTD_getFrameParams(ZSTD_frameParams *fparamsPtr, const void *src, size_t srcSize)
+{
+ const BYTE *ip = (const BYTE *)src;
+
+ if (srcSize < ZSTD_frameHeaderSize_prefix)
+ return ZSTD_frameHeaderSize_prefix;
+ if (ZSTD_readLE32(src) != ZSTD_MAGICNUMBER) {
+ if ((ZSTD_readLE32(src) & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) {
+ if (srcSize < ZSTD_skippableHeaderSize)
+ return ZSTD_skippableHeaderSize; /* magic number + skippable frame length */
+ memset(fparamsPtr, 0, sizeof(*fparamsPtr));
+ fparamsPtr->frameContentSize = ZSTD_readLE32((const char *)src + 4);
+ fparamsPtr->windowSize = 0; /* windowSize==0 means a frame is skippable */
+ return 0;
+ }
+ return ERROR(prefix_unknown);
+ }
+
+ /* ensure there is enough `srcSize` to fully read/decode frame header */
+ {
+ size_t const fhsize = ZSTD_frameHeaderSize(src, srcSize);
+ if (srcSize < fhsize)
+ return fhsize;
+ }
+
+ {
+ BYTE const fhdByte = ip[4];
+ size_t pos = 5;
+ U32 const dictIDSizeCode = fhdByte & 3;
+ U32 const checksumFlag = (fhdByte >> 2) & 1;
+ U32 const singleSegment = (fhdByte >> 5) & 1;
+ U32 const fcsID = fhdByte >> 6;
+ U32 const windowSizeMax = 1U << ZSTD_WINDOWLOG_MAX;
+ U32 windowSize = 0;
+ U32 dictID = 0;
+ U64 frameContentSize = 0;
+ if ((fhdByte & 0x08) != 0)
+ return ERROR(frameParameter_unsupported); /* reserved bits, which must be zero */
+ if (!singleSegment) {
+ BYTE const wlByte = ip[pos++];
+ U32 const windowLog = (wlByte >> 3) + ZSTD_WINDOWLOG_ABSOLUTEMIN;
+ if (windowLog > ZSTD_WINDOWLOG_MAX)
+ return ERROR(frameParameter_windowTooLarge); /* avoids issue with 1 << windowLog */
+ windowSize = (1U << windowLog);
+ windowSize += (windowSize >> 3) * (wlByte & 7);
+ }
+
+ switch (dictIDSizeCode) {
+ default: /* impossible */
+ case 0: break;
+ case 1:
+ dictID = ip[pos];
+ pos++;
+ break;
+ case 2:
+ dictID = ZSTD_readLE16(ip + pos);
+ pos += 2;
+ break;
+ case 3:
+ dictID = ZSTD_readLE32(ip + pos);
+ pos += 4;
+ break;
+ }
+ switch (fcsID) {
+ default: /* impossible */
+ case 0:
+ if (singleSegment)
+ frameContentSize = ip[pos];
+ break;
+ case 1: frameContentSize = ZSTD_readLE16(ip + pos) + 256; break;
+ case 2: frameContentSize = ZSTD_readLE32(ip + pos); break;
+ case 3: frameContentSize = ZSTD_readLE64(ip + pos); break;
+ }
+ if (!windowSize)
+ windowSize = (U32)frameContentSize;
+ if (windowSize > windowSizeMax)
+ return ERROR(frameParameter_windowTooLarge);
+ fparamsPtr->frameContentSize = frameContentSize;
+ fparamsPtr->windowSize = windowSize;
+ fparamsPtr->dictID = dictID;
+ fparamsPtr->checksumFlag = checksumFlag;
+ }
+ return 0;
+}
+
+/** ZSTD_getFrameContentSize() :
+* compatible with legacy mode
+* @return : decompressed size of the single frame pointed to be `src` if known, otherwise
+* - ZSTD_CONTENTSIZE_UNKNOWN if the size cannot be determined
+* - ZSTD_CONTENTSIZE_ERROR if an error occurred (e.g. invalid magic number, srcSize too small) */
+unsigned long long ZSTD_getFrameContentSize(const void *src, size_t srcSize)
+{
+ {
+ ZSTD_frameParams fParams;
+ if (ZSTD_getFrameParams(&fParams, src, srcSize) != 0)
+ return ZSTD_CONTENTSIZE_ERROR;
+ if (fParams.windowSize == 0) {
+ /* Either skippable or empty frame, size == 0 either way */
+ return 0;
+ } else if (fParams.frameContentSize != 0) {
+ return fParams.frameContentSize;
+ } else {
+ return ZSTD_CONTENTSIZE_UNKNOWN;
+ }
+ }
+}
+
+/** ZSTD_findDecompressedSize() :
+ * compatible with legacy mode
+ * `srcSize` must be the exact length of some number of ZSTD compressed and/or
+ * skippable frames
+ * @return : decompressed size of the frames contained */
+unsigned long long ZSTD_findDecompressedSize(const void *src, size_t srcSize)
+{
+ {
+ unsigned long long totalDstSize = 0;
+ while (srcSize >= ZSTD_frameHeaderSize_prefix) {
+ const U32 magicNumber = ZSTD_readLE32(src);
+
+ if ((magicNumber & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) {
+ size_t skippableSize;
+ if (srcSize < ZSTD_skippableHeaderSize)
+ return ERROR(srcSize_wrong);
+ skippableSize = ZSTD_readLE32((const BYTE *)src + 4) + ZSTD_skippableHeaderSize;
+ if (srcSize < skippableSize) {
+ return ZSTD_CONTENTSIZE_ERROR;
+ }
+
+ src = (const BYTE *)src + skippableSize;
+ srcSize -= skippableSize;
+ continue;
+ }
+
+ {
+ unsigned long long const ret = ZSTD_getFrameContentSize(src, srcSize);
+ if (ret >= ZSTD_CONTENTSIZE_ERROR)
+ return ret;
+
+ /* check for overflow */
+ if (totalDstSize + ret < totalDstSize)
+ return ZSTD_CONTENTSIZE_ERROR;
+ totalDstSize += ret;
+ }
+ {
+ size_t const frameSrcSize = ZSTD_findFrameCompressedSize(src, srcSize);
+ if (ZSTD_isError(frameSrcSize)) {
+ return ZSTD_CONTENTSIZE_ERROR;
+ }
+
+ src = (const BYTE *)src + frameSrcSize;
+ srcSize -= frameSrcSize;
+ }
+ }
+
+ if (srcSize) {
+ return ZSTD_CONTENTSIZE_ERROR;
+ }
+
+ return totalDstSize;
+ }
+}
+
+/** ZSTD_decodeFrameHeader() :
+* `headerSize` must be the size provided by ZSTD_frameHeaderSize().
+* @return : 0 if success, or an error code, which can be tested using ZSTD_isError() */
+static size_t ZSTD_decodeFrameHeader(ZSTD_DCtx *dctx, const void *src, size_t headerSize)
+{
+ size_t const result = ZSTD_getFrameParams(&(dctx->fParams), src, headerSize);
+ if (ZSTD_isError(result))
+ return result; /* invalid header */
+ if (result > 0)
+ return ERROR(srcSize_wrong); /* headerSize too small */
+ if (dctx->fParams.dictID && (dctx->dictID != dctx->fParams.dictID))
+ return ERROR(dictionary_wrong);
+ if (dctx->fParams.checksumFlag)
+ xxh64_reset(&dctx->xxhState, 0);
+ return 0;
+}
+
+typedef struct {
+ blockType_e blockType;
+ U32 lastBlock;
+ U32 origSize;
+} blockProperties_t;
+
+/*! ZSTD_getcBlockSize() :
+* Provides the size of compressed block from block header `src` */
+size_t ZSTD_getcBlockSize(const void *src, size_t srcSize, blockProperties_t *bpPtr)
+{
+ if (srcSize < ZSTD_blockHeaderSize)
+ return ERROR(srcSize_wrong);
+ {
+ U32 const cBlockHeader = ZSTD_readLE24(src);
+ U32 const cSize = cBlockHeader >> 3;
+ bpPtr->lastBlock = cBlockHeader & 1;
+ bpPtr->blockType = (blockType_e)((cBlockHeader >> 1) & 3);
+ bpPtr->origSize = cSize; /* only useful for RLE */
+ if (bpPtr->blockType == bt_rle)
+ return 1;
+ if (bpPtr->blockType == bt_reserved)
+ return ERROR(corruption_detected);
+ return cSize;
+ }
+}
+
+static size_t ZSTD_copyRawBlock(void *dst, size_t dstCapacity, const void *src, size_t srcSize)
+{
+ if (srcSize > dstCapacity)
+ return ERROR(dstSize_tooSmall);
+ memcpy(dst, src, srcSize);
+ return srcSize;
+}
+
+static size_t ZSTD_setRleBlock(void *dst, size_t dstCapacity, const void *src, size_t srcSize, size_t regenSize)
+{
+ if (srcSize != 1)
+ return ERROR(srcSize_wrong);
+ if (regenSize > dstCapacity)
+ return ERROR(dstSize_tooSmall);
+ memset(dst, *(const BYTE *)src, regenSize);
+ return regenSize;
+}
+
+/*! ZSTD_decodeLiteralsBlock() :
+ @return : nb of bytes read from src (< srcSize ) */
+size_t ZSTD_decodeLiteralsBlock(ZSTD_DCtx *dctx, const void *src, size_t srcSize) /* note : srcSize < BLOCKSIZE */
+{
+ if (srcSize < MIN_CBLOCK_SIZE)
+ return ERROR(corruption_detected);
+
+ {
+ const BYTE *const istart = (const BYTE *)src;
+ symbolEncodingType_e const litEncType = (symbolEncodingType_e)(istart[0] & 3);
+
+ switch (litEncType) {
+ case set_repeat:
+ if (dctx->litEntropy == 0)
+ return ERROR(dictionary_corrupted);
+ /* fall-through */
+ case set_compressed:
+ if (srcSize < 5)
+ return ERROR(corruption_detected); /* srcSize >= MIN_CBLOCK_SIZE == 3; here we need up to 5 for case 3 */
+ {
+ size_t lhSize, litSize, litCSize;
+ U32 singleStream = 0;
+ U32 const lhlCode = (istart[0] >> 2) & 3;
+ U32 const lhc = ZSTD_readLE32(istart);
+ switch (lhlCode) {
+ case 0:
+ case 1:
+ default: /* note : default is impossible, since lhlCode into [0..3] */
+ /* 2 - 2 - 10 - 10 */
+ singleStream = !lhlCode;
+ lhSize = 3;
+ litSize = (lhc >> 4) & 0x3FF;
+ litCSize = (lhc >> 14) & 0x3FF;
+ break;
+ case 2:
+ /* 2 - 2 - 14 - 14 */
+ lhSize = 4;
+ litSize = (lhc >> 4) & 0x3FFF;
+ litCSize = lhc >> 18;
+ break;
+ case 3:
+ /* 2 - 2 - 18 - 18 */
+ lhSize = 5;
+ litSize = (lhc >> 4) & 0x3FFFF;
+ litCSize = (lhc >> 22) + (istart[4] << 10);
+ break;
+ }
+ if (litSize > ZSTD_BLOCKSIZE_ABSOLUTEMAX)
+ return ERROR(corruption_detected);
+ if (litCSize + lhSize > srcSize)
+ return ERROR(corruption_detected);
+
+ if (HUF_isError(
+ (litEncType == set_repeat)
+ ? (singleStream ? HUF_decompress1X_usingDTable(dctx->litBuffer, litSize, istart + lhSize, litCSize, dctx->HUFptr)
+ : HUF_decompress4X_usingDTable(dctx->litBuffer, litSize, istart + lhSize, litCSize, dctx->HUFptr))
+ : (singleStream
+ ? HUF_decompress1X2_DCtx_wksp(dctx->entropy.hufTable, dctx->litBuffer, litSize, istart + lhSize, litCSize,
+ dctx->entropy.workspace, sizeof(dctx->entropy.workspace))
+ : HUF_decompress4X_hufOnly_wksp(dctx->entropy.hufTable, dctx->litBuffer, litSize, istart + lhSize, litCSize,
+ dctx->entropy.workspace, sizeof(dctx->entropy.workspace)))))
+ return ERROR(corruption_detected);
+
+ dctx->litPtr = dctx->litBuffer;
+ dctx->litSize = litSize;
+ dctx->litEntropy = 1;
+ if (litEncType == set_compressed)
+ dctx->HUFptr = dctx->entropy.hufTable;
+ memset(dctx->litBuffer + dctx->litSize, 0, WILDCOPY_OVERLENGTH);
+ return litCSize + lhSize;
+ }
+
+ case set_basic: {
+ size_t litSize, lhSize;
+ U32 const lhlCode = ((istart[0]) >> 2) & 3;
+ switch (lhlCode) {
+ case 0:
+ case 2:
+ default: /* note : default is impossible, since lhlCode into [0..3] */
+ lhSize = 1;
+ litSize = istart[0] >> 3;
+ break;
+ case 1:
+ lhSize = 2;
+ litSize = ZSTD_readLE16(istart) >> 4;
+ break;
+ case 3:
+ lhSize = 3;
+ litSize = ZSTD_readLE24(istart) >> 4;
+ break;
+ }
+
+ if (lhSize + litSize + WILDCOPY_OVERLENGTH > srcSize) { /* risk reading beyond src buffer with wildcopy */
+ if (litSize + lhSize > srcSize)
+ return ERROR(corruption_detected);
+ memcpy(dctx->litBuffer, istart + lhSize, litSize);
+ dctx->litPtr = dctx->litBuffer;
+ dctx->litSize = litSize;
+ memset(dctx->litBuffer + dctx->litSize, 0, WILDCOPY_OVERLENGTH);
+ return lhSize + litSize;
+ }
+ /* direct reference into compressed stream */
+ dctx->litPtr = istart + lhSize;
+ dctx->litSize = litSize;
+ return lhSize + litSize;
+ }
+
+ case set_rle: {
+ U32 const lhlCode = ((istart[0]) >> 2) & 3;
+ size_t litSize, lhSize;
+ switch (lhlCode) {
+ case 0:
+ case 2:
+ default: /* note : default is impossible, since lhlCode into [0..3] */
+ lhSize = 1;
+ litSize = istart[0] >> 3;
+ break;
+ case 1:
+ lhSize = 2;
+ litSize = ZSTD_readLE16(istart) >> 4;
+ break;
+ case 3:
+ lhSize = 3;
+ litSize = ZSTD_readLE24(istart) >> 4;
+ if (srcSize < 4)
+ return ERROR(corruption_detected); /* srcSize >= MIN_CBLOCK_SIZE == 3; here we need lhSize+1 = 4 */
+ break;
+ }
+ if (litSize > ZSTD_BLOCKSIZE_ABSOLUTEMAX)
+ return ERROR(corruption_detected);
+ memset(dctx->litBuffer, istart[lhSize], litSize + WILDCOPY_OVERLENGTH);
+ dctx->litPtr = dctx->litBuffer;
+ dctx->litSize = litSize;
+ return lhSize + 1;
+ }
+ default:
+ return ERROR(corruption_detected); /* impossible */
+ }
+ }
+}
+
+typedef union {
+ FSE_decode_t realData;
+ U32 alignedBy4;
+} FSE_decode_t4;
+
+static const FSE_decode_t4 LL_defaultDTable[(1 << LL_DEFAULTNORMLOG) + 1] = {
+ {{LL_DEFAULTNORMLOG, 1, 1}}, /* header : tableLog, fastMode, fastMode */
+ {{0, 0, 4}}, /* 0 : base, symbol, bits */
+ {{16, 0, 4}},
+ {{32, 1, 5}},
+ {{0, 3, 5}},
+ {{0, 4, 5}},
+ {{0, 6, 5}},
+ {{0, 7, 5}},
+ {{0, 9, 5}},
+ {{0, 10, 5}},
+ {{0, 12, 5}},
+ {{0, 14, 6}},
+ {{0, 16, 5}},
+ {{0, 18, 5}},
+ {{0, 19, 5}},
+ {{0, 21, 5}},
+ {{0, 22, 5}},
+ {{0, 24, 5}},
+ {{32, 25, 5}},
+ {{0, 26, 5}},
+ {{0, 27, 6}},
+ {{0, 29, 6}},
+ {{0, 31, 6}},
+ {{32, 0, 4}},
+ {{0, 1, 4}},
+ {{0, 2, 5}},
+ {{32, 4, 5}},
+ {{0, 5, 5}},
+ {{32, 7, 5}},
+ {{0, 8, 5}},
+ {{32, 10, 5}},
+ {{0, 11, 5}},
+ {{0, 13, 6}},
+ {{32, 16, 5}},
+ {{0, 17, 5}},
+ {{32, 19, 5}},
+ {{0, 20, 5}},
+ {{32, 22, 5}},
+ {{0, 23, 5}},
+ {{0, 25, 4}},
+ {{16, 25, 4}},
+ {{32, 26, 5}},
+ {{0, 28, 6}},
+ {{0, 30, 6}},
+ {{48, 0, 4}},
+ {{16, 1, 4}},
+ {{32, 2, 5}},
+ {{32, 3, 5}},
+ {{32, 5, 5}},
+ {{32, 6, 5}},
+ {{32, 8, 5}},
+ {{32, 9, 5}},
+ {{32, 11, 5}},
+ {{32, 12, 5}},
+ {{0, 15, 6}},
+ {{32, 17, 5}},
+ {{32, 18, 5}},
+ {{32, 20, 5}},
+ {{32, 21, 5}},
+ {{32, 23, 5}},
+ {{32, 24, 5}},
+ {{0, 35, 6}},
+ {{0, 34, 6}},
+ {{0, 33, 6}},
+ {{0, 32, 6}},
+}; /* LL_defaultDTable */
+
+static const FSE_decode_t4 ML_defaultDTable[(1 << ML_DEFAULTNORMLOG) + 1] = {
+ {{ML_DEFAULTNORMLOG, 1, 1}}, /* header : tableLog, fastMode, fastMode */
+ {{0, 0, 6}}, /* 0 : base, symbol, bits */
+ {{0, 1, 4}},
+ {{32, 2, 5}},
+ {{0, 3, 5}},
+ {{0, 5, 5}},
+ {{0, 6, 5}},
+ {{0, 8, 5}},
+ {{0, 10, 6}},
+ {{0, 13, 6}},
+ {{0, 16, 6}},
+ {{0, 19, 6}},
+ {{0, 22, 6}},
+ {{0, 25, 6}},
+ {{0, 28, 6}},
+ {{0, 31, 6}},
+ {{0, 33, 6}},
+ {{0, 35, 6}},
+ {{0, 37, 6}},
+ {{0, 39, 6}},
+ {{0, 41, 6}},
+ {{0, 43, 6}},
+ {{0, 45, 6}},
+ {{16, 1, 4}},
+ {{0, 2, 4}},
+ {{32, 3, 5}},
+ {{0, 4, 5}},
+ {{32, 6, 5}},
+ {{0, 7, 5}},
+ {{0, 9, 6}},
+ {{0, 12, 6}},
+ {{0, 15, 6}},
+ {{0, 18, 6}},
+ {{0, 21, 6}},
+ {{0, 24, 6}},
+ {{0, 27, 6}},
+ {{0, 30, 6}},
+ {{0, 32, 6}},
+ {{0, 34, 6}},
+ {{0, 36, 6}},
+ {{0, 38, 6}},
+ {{0, 40, 6}},
+ {{0, 42, 6}},
+ {{0, 44, 6}},
+ {{32, 1, 4}},
+ {{48, 1, 4}},
+ {{16, 2, 4}},
+ {{32, 4, 5}},
+ {{32, 5, 5}},
+ {{32, 7, 5}},
+ {{32, 8, 5}},
+ {{0, 11, 6}},
+ {{0, 14, 6}},
+ {{0, 17, 6}},
+ {{0, 20, 6}},
+ {{0, 23, 6}},
+ {{0, 26, 6}},
+ {{0, 29, 6}},
+ {{0, 52, 6}},
+ {{0, 51, 6}},
+ {{0, 50, 6}},
+ {{0, 49, 6}},
+ {{0, 48, 6}},
+ {{0, 47, 6}},
+ {{0, 46, 6}},
+}; /* ML_defaultDTable */
+
+static const FSE_decode_t4 OF_defaultDTable[(1 << OF_DEFAULTNORMLOG) + 1] = {
+ {{OF_DEFAULTNORMLOG, 1, 1}}, /* header : tableLog, fastMode, fastMode */
+ {{0, 0, 5}}, /* 0 : base, symbol, bits */
+ {{0, 6, 4}},
+ {{0, 9, 5}},
+ {{0, 15, 5}},
+ {{0, 21, 5}},
+ {{0, 3, 5}},
+ {{0, 7, 4}},
+ {{0, 12, 5}},
+ {{0, 18, 5}},
+ {{0, 23, 5}},
+ {{0, 5, 5}},
+ {{0, 8, 4}},
+ {{0, 14, 5}},
+ {{0, 20, 5}},
+ {{0, 2, 5}},
+ {{16, 7, 4}},
+ {{0, 11, 5}},
+ {{0, 17, 5}},
+ {{0, 22, 5}},
+ {{0, 4, 5}},
+ {{16, 8, 4}},
+ {{0, 13, 5}},
+ {{0, 19, 5}},
+ {{0, 1, 5}},
+ {{16, 6, 4}},
+ {{0, 10, 5}},
+ {{0, 16, 5}},
+ {{0, 28, 5}},
+ {{0, 27, 5}},
+ {{0, 26, 5}},
+ {{0, 25, 5}},
+ {{0, 24, 5}},
+}; /* OF_defaultDTable */
+
+/*! ZSTD_buildSeqTable() :
+ @return : nb bytes read from src,
+ or an error code if it fails, testable with ZSTD_isError()
+*/
+static size_t ZSTD_buildSeqTable(FSE_DTable *DTableSpace, const FSE_DTable **DTablePtr, symbolEncodingType_e type, U32 max, U32 maxLog, const void *src,
+ size_t srcSize, const FSE_decode_t4 *defaultTable, U32 flagRepeatTable, void *workspace, size_t workspaceSize)
+{
+ const void *const tmpPtr = defaultTable; /* bypass strict aliasing */
+ switch (type) {
+ case set_rle:
+ if (!srcSize)
+ return ERROR(srcSize_wrong);
+ if ((*(const BYTE *)src) > max)
+ return ERROR(corruption_detected);
+ FSE_buildDTable_rle(DTableSpace, *(const BYTE *)src);
+ *DTablePtr = DTableSpace;
+ return 1;
+ case set_basic: *DTablePtr = (const FSE_DTable *)tmpPtr; return 0;
+ case set_repeat:
+ if (!flagRepeatTable)
+ return ERROR(corruption_detected);
+ return 0;
+ default: /* impossible */
+ case set_compressed: {
+ U32 tableLog;
+ S16 *norm = (S16 *)workspace;
+ size_t const spaceUsed32 = ALIGN(sizeof(S16) * (MaxSeq + 1), sizeof(U32)) >> 2;
+
+ if ((spaceUsed32 << 2) > workspaceSize)
+ return ERROR(GENERIC);
+ workspace = (U32 *)workspace + spaceUsed32;
+ workspaceSize -= (spaceUsed32 << 2);
+ {
+ size_t const headerSize = FSE_readNCount(norm, &max, &tableLog, src, srcSize);
+ if (FSE_isError(headerSize))
+ return ERROR(corruption_detected);
+ if (tableLog > maxLog)
+ return ERROR(corruption_detected);
+ FSE_buildDTable_wksp(DTableSpace, norm, max, tableLog, workspace, workspaceSize);
+ *DTablePtr = DTableSpace;
+ return headerSize;
+ }
+ }
+ }
+}
+
+size_t ZSTD_decodeSeqHeaders(ZSTD_DCtx *dctx, int *nbSeqPtr, const void *src, size_t srcSize)
+{
+ const BYTE *const istart = (const BYTE *const)src;
+ const BYTE *const iend = istart + srcSize;
+ const BYTE *ip = istart;
+
+ /* check */
+ if (srcSize < MIN_SEQUENCES_SIZE)
+ return ERROR(srcSize_wrong);
+
+ /* SeqHead */
+ {
+ int nbSeq = *ip++;
+ if (!nbSeq) {
+ *nbSeqPtr = 0;
+ return 1;
+ }
+ if (nbSeq > 0x7F) {
+ if (nbSeq == 0xFF) {
+ if (ip + 2 > iend)
+ return ERROR(srcSize_wrong);
+ nbSeq = ZSTD_readLE16(ip) + LONGNBSEQ, ip += 2;
+ } else {
+ if (ip >= iend)
+ return ERROR(srcSize_wrong);
+ nbSeq = ((nbSeq - 0x80) << 8) + *ip++;
+ }
+ }
+ *nbSeqPtr = nbSeq;
+ }
+
+ /* FSE table descriptors */
+ if (ip + 4 > iend)
+ return ERROR(srcSize_wrong); /* minimum possible size */
+ {
+ symbolEncodingType_e const LLtype = (symbolEncodingType_e)(*ip >> 6);
+ symbolEncodingType_e const OFtype = (symbolEncodingType_e)((*ip >> 4) & 3);
+ symbolEncodingType_e const MLtype = (symbolEncodingType_e)((*ip >> 2) & 3);
+ ip++;
+
+ /* Build DTables */
+ {
+ size_t const llhSize = ZSTD_buildSeqTable(dctx->entropy.LLTable, &dctx->LLTptr, LLtype, MaxLL, LLFSELog, ip, iend - ip,
+ LL_defaultDTable, dctx->fseEntropy, dctx->entropy.workspace, sizeof(dctx->entropy.workspace));
+ if (ZSTD_isError(llhSize))
+ return ERROR(corruption_detected);
+ ip += llhSize;
+ }
+ {
+ size_t const ofhSize = ZSTD_buildSeqTable(dctx->entropy.OFTable, &dctx->OFTptr, OFtype, MaxOff, OffFSELog, ip, iend - ip,
+ OF_defaultDTable, dctx->fseEntropy, dctx->entropy.workspace, sizeof(dctx->entropy.workspace));
+ if (ZSTD_isError(ofhSize))
+ return ERROR(corruption_detected);
+ ip += ofhSize;
+ }
+ {
+ size_t const mlhSize = ZSTD_buildSeqTable(dctx->entropy.MLTable, &dctx->MLTptr, MLtype, MaxML, MLFSELog, ip, iend - ip,
+ ML_defaultDTable, dctx->fseEntropy, dctx->entropy.workspace, sizeof(dctx->entropy.workspace));
+ if (ZSTD_isError(mlhSize))
+ return ERROR(corruption_detected);
+ ip += mlhSize;
+ }
+ }
+
+ return ip - istart;
+}
+
+typedef struct {
+ size_t litLength;
+ size_t matchLength;
+ size_t offset;
+ const BYTE *match;
+} seq_t;
+
+typedef struct {
+ BIT_DStream_t DStream;
+ FSE_DState_t stateLL;
+ FSE_DState_t stateOffb;
+ FSE_DState_t stateML;
+ size_t prevOffset[ZSTD_REP_NUM];
+ const BYTE *base;
+ size_t pos;
+ uPtrDiff gotoDict;
+} seqState_t;
+
+FORCE_NOINLINE
+size_t ZSTD_execSequenceLast7(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base,
+ const BYTE *const vBase, const BYTE *const dictEnd)
+{
+ BYTE *const oLitEnd = op + sequence.litLength;
+ size_t const sequenceLength = sequence.litLength + sequence.matchLength;
+ BYTE *const oMatchEnd = op + sequenceLength; /* risk : address space overflow (32-bits) */
+ BYTE *const oend_w = oend - WILDCOPY_OVERLENGTH;
+ const BYTE *const iLitEnd = *litPtr + sequence.litLength;
+ const BYTE *match = oLitEnd - sequence.offset;
+
+ /* check */
+ if (oMatchEnd > oend)
+ return ERROR(dstSize_tooSmall); /* last match must start at a minimum distance of WILDCOPY_OVERLENGTH from oend */
+ if (iLitEnd > litLimit)
+ return ERROR(corruption_detected); /* over-read beyond lit buffer */
+ if (oLitEnd <= oend_w)
+ return ERROR(GENERIC); /* Precondition */
+
+ /* copy literals */
+ if (op < oend_w) {
+ ZSTD_wildcopy(op, *litPtr, oend_w - op);
+ *litPtr += oend_w - op;
+ op = oend_w;
+ }
+ while (op < oLitEnd)
+ *op++ = *(*litPtr)++;
+
+ /* copy Match */
+ if (sequence.offset > (size_t)(oLitEnd - base)) {
+ /* offset beyond prefix */
+ if (sequence.offset > (size_t)(oLitEnd - vBase))
+ return ERROR(corruption_detected);
+ match = dictEnd - (base - match);
+ if (match + sequence.matchLength <= dictEnd) {
+ memmove(oLitEnd, match, sequence.matchLength);
+ return sequenceLength;
+ }
+ /* span extDict & currPrefixSegment */
+ {
+ size_t const length1 = dictEnd - match;
+ memmove(oLitEnd, match, length1);
+ op = oLitEnd + length1;
+ sequence.matchLength -= length1;
+ match = base;
+ }
+ }
+ while (op < oMatchEnd)
+ *op++ = *match++;
+ return sequenceLength;
+}
+
+static seq_t ZSTD_decodeSequence(seqState_t *seqState)
+{
+ seq_t seq;
+
+ U32 const llCode = FSE_peekSymbol(&seqState->stateLL);
+ U32 const mlCode = FSE_peekSymbol(&seqState->stateML);
+ U32 const ofCode = FSE_peekSymbol(&seqState->stateOffb); /* <= maxOff, by table construction */
+
+ U32 const llBits = LL_bits[llCode];
+ U32 const mlBits = ML_bits[mlCode];
+ U32 const ofBits = ofCode;
+ U32 const totalBits = llBits + mlBits + ofBits;
+
+ static const U32 LL_base[MaxLL + 1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18,
+ 20, 22, 24, 28, 32, 40, 48, 64, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000, 0x10000};
+
+ static const U32 ML_base[MaxML + 1] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
+ 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 37, 39, 41,
+ 43, 47, 51, 59, 67, 83, 99, 0x83, 0x103, 0x203, 0x403, 0x803, 0x1003, 0x2003, 0x4003, 0x8003, 0x10003};
+
+ static const U32 OF_base[MaxOff + 1] = {0, 1, 1, 5, 0xD, 0x1D, 0x3D, 0x7D, 0xFD, 0x1FD,
+ 0x3FD, 0x7FD, 0xFFD, 0x1FFD, 0x3FFD, 0x7FFD, 0xFFFD, 0x1FFFD, 0x3FFFD, 0x7FFFD,
+ 0xFFFFD, 0x1FFFFD, 0x3FFFFD, 0x7FFFFD, 0xFFFFFD, 0x1FFFFFD, 0x3FFFFFD, 0x7FFFFFD, 0xFFFFFFD};
+
+ /* sequence */
+ {
+ size_t offset;
+ if (!ofCode)
+ offset = 0;
+ else {
+ offset = OF_base[ofCode] + BIT_readBitsFast(&seqState->DStream, ofBits); /* <= (ZSTD_WINDOWLOG_MAX-1) bits */
+ if (ZSTD_32bits())
+ BIT_reloadDStream(&seqState->DStream);
+ }
+
+ if (ofCode <= 1) {
+ offset += (llCode == 0);
+ if (offset) {
+ size_t temp = (offset == 3) ? seqState->prevOffset[0] - 1 : seqState->prevOffset[offset];
+ temp += !temp; /* 0 is not valid; input is corrupted; force offset to 1 */
+ if (offset != 1)
+ seqState->prevOffset[2] = seqState->prevOffset[1];
+ seqState->prevOffset[1] = seqState->prevOffset[0];
+ seqState->prevOffset[0] = offset = temp;
+ } else {
+ offset = seqState->prevOffset[0];
+ }
+ } else {
+ seqState->prevOffset[2] = seqState->prevOffset[1];
+ seqState->prevOffset[1] = seqState->prevOffset[0];
+ seqState->prevOffset[0] = offset;
+ }
+ seq.offset = offset;
+ }
+
+ seq.matchLength = ML_base[mlCode] + ((mlCode > 31) ? BIT_readBitsFast(&seqState->DStream, mlBits) : 0); /* <= 16 bits */
+ if (ZSTD_32bits() && (mlBits + llBits > 24))
+ BIT_reloadDStream(&seqState->DStream);
+
+ seq.litLength = LL_base[llCode] + ((llCode > 15) ? BIT_readBitsFast(&seqState->DStream, llBits) : 0); /* <= 16 bits */
+ if (ZSTD_32bits() || (totalBits > 64 - 7 - (LLFSELog + MLFSELog + OffFSELog)))
+ BIT_reloadDStream(&seqState->DStream);
+
+ /* ANS state update */
+ FSE_updateState(&seqState->stateLL, &seqState->DStream); /* <= 9 bits */
+ FSE_updateState(&seqState->stateML, &seqState->DStream); /* <= 9 bits */
+ if (ZSTD_32bits())
+ BIT_reloadDStream(&seqState->DStream); /* <= 18 bits */
+ FSE_updateState(&seqState->stateOffb, &seqState->DStream); /* <= 8 bits */
+
+ seq.match = NULL;
+
+ return seq;
+}
+
+FORCE_INLINE
+size_t ZSTD_execSequence(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base,
+ const BYTE *const vBase, const BYTE *const dictEnd)
+{
+ BYTE *const oLitEnd = op + sequence.litLength;
+ size_t const sequenceLength = sequence.litLength + sequence.matchLength;
+ BYTE *const oMatchEnd = op + sequenceLength; /* risk : address space overflow (32-bits) */
+ BYTE *const oend_w = oend - WILDCOPY_OVERLENGTH;
+ const BYTE *const iLitEnd = *litPtr + sequence.litLength;
+ const BYTE *match = oLitEnd - sequence.offset;
+
+ /* check */
+ if (oMatchEnd > oend)
+ return ERROR(dstSize_tooSmall); /* last match must start at a minimum distance of WILDCOPY_OVERLENGTH from oend */
+ if (iLitEnd > litLimit)
+ return ERROR(corruption_detected); /* over-read beyond lit buffer */
+ if (oLitEnd > oend_w)
+ return ZSTD_execSequenceLast7(op, oend, sequence, litPtr, litLimit, base, vBase, dictEnd);
+
+ /* copy Literals */
+ ZSTD_copy8(op, *litPtr);
+ if (sequence.litLength > 8)
+ ZSTD_wildcopy(op + 8, (*litPtr) + 8,
+ sequence.litLength - 8); /* note : since oLitEnd <= oend-WILDCOPY_OVERLENGTH, no risk of overwrite beyond oend */
+ op = oLitEnd;
+ *litPtr = iLitEnd; /* update for next sequence */
+
+ /* copy Match */
+ if (sequence.offset > (size_t)(oLitEnd - base)) {
+ /* offset beyond prefix */
+ if (sequence.offset > (size_t)(oLitEnd - vBase))
+ return ERROR(corruption_detected);
+ match = dictEnd + (match - base);
+ if (match + sequence.matchLength <= dictEnd) {
+ memmove(oLitEnd, match, sequence.matchLength);
+ return sequenceLength;
+ }
+ /* span extDict & currPrefixSegment */
+ {
+ size_t const length1 = dictEnd - match;
+ memmove(oLitEnd, match, length1);
+ op = oLitEnd + length1;
+ sequence.matchLength -= length1;
+ match = base;
+ if (op > oend_w || sequence.matchLength < MINMATCH) {
+ U32 i;
+ for (i = 0; i < sequence.matchLength; ++i)
+ op[i] = match[i];
+ return sequenceLength;
+ }
+ }
+ }
+ /* Requirement: op <= oend_w && sequence.matchLength >= MINMATCH */
+
+ /* match within prefix */
+ if (sequence.offset < 8) {
+ /* close range match, overlap */
+ static const U32 dec32table[] = {0, 1, 2, 1, 4, 4, 4, 4}; /* added */
+ static const int dec64table[] = {8, 8, 8, 7, 8, 9, 10, 11}; /* subtracted */
+ int const sub2 = dec64table[sequence.offset];
+ op[0] = match[0];
+ op[1] = match[1];
+ op[2] = match[2];
+ op[3] = match[3];
+ match += dec32table[sequence.offset];
+ ZSTD_copy4(op + 4, match);
+ match -= sub2;
+ } else {
+ ZSTD_copy8(op, match);
+ }
+ op += 8;
+ match += 8;
+
+ if (oMatchEnd > oend - (16 - MINMATCH)) {
+ if (op < oend_w) {
+ ZSTD_wildcopy(op, match, oend_w - op);
+ match += oend_w - op;
+ op = oend_w;
+ }
+ while (op < oMatchEnd)
+ *op++ = *match++;
+ } else {
+ ZSTD_wildcopy(op, match, (ptrdiff_t)sequence.matchLength - 8); /* works even if matchLength < 8 */
+ }
+ return sequenceLength;
+}
+
+static size_t ZSTD_decompressSequences(ZSTD_DCtx *dctx, void *dst, size_t maxDstSize, const void *seqStart, size_t seqSize)
+{
+ const BYTE *ip = (const BYTE *)seqStart;
+ const BYTE *const iend = ip + seqSize;
+ BYTE *const ostart = (BYTE * const)dst;
+ BYTE *const oend = ostart + maxDstSize;
+ BYTE *op = ostart;
+ const BYTE *litPtr = dctx->litPtr;
+ const BYTE *const litEnd = litPtr + dctx->litSize;
+ const BYTE *const base = (const BYTE *)(dctx->base);
+ const BYTE *const vBase = (const BYTE *)(dctx->vBase);
+ const BYTE *const dictEnd = (const BYTE *)(dctx->dictEnd);
+ int nbSeq;
+
+ /* Build Decoding Tables */
+ {
+ size_t const seqHSize = ZSTD_decodeSeqHeaders(dctx, &nbSeq, ip, seqSize);
+ if (ZSTD_isError(seqHSize))
+ return seqHSize;
+ ip += seqHSize;
+ }
+
+ /* Regen sequences */
+ if (nbSeq) {
+ seqState_t seqState;
+ dctx->fseEntropy = 1;
+ {
+ U32 i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ seqState.prevOffset[i] = dctx->entropy.rep[i];
+ }
+ CHECK_E(BIT_initDStream(&seqState.DStream, ip, iend - ip), corruption_detected);
+ FSE_initDState(&seqState.stateLL, &seqState.DStream, dctx->LLTptr);
+ FSE_initDState(&seqState.stateOffb, &seqState.DStream, dctx->OFTptr);
+ FSE_initDState(&seqState.stateML, &seqState.DStream, dctx->MLTptr);
+
+ for (; (BIT_reloadDStream(&(seqState.DStream)) <= BIT_DStream_completed) && nbSeq;) {
+ nbSeq--;
+ {
+ seq_t const sequence = ZSTD_decodeSequence(&seqState);
+ size_t const oneSeqSize = ZSTD_execSequence(op, oend, sequence, &litPtr, litEnd, base, vBase, dictEnd);
+ if (ZSTD_isError(oneSeqSize))
+ return oneSeqSize;
+ op += oneSeqSize;
+ }
+ }
+
+ /* check if reached exact end */
+ if (nbSeq)
+ return ERROR(corruption_detected);
+ /* save reps for next block */
+ {
+ U32 i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ dctx->entropy.rep[i] = (U32)(seqState.prevOffset[i]);
+ }
+ }
+
+ /* last literal segment */
+ {
+ size_t const lastLLSize = litEnd - litPtr;
+ if (lastLLSize > (size_t)(oend - op))
+ return ERROR(dstSize_tooSmall);
+ memcpy(op, litPtr, lastLLSize);
+ op += lastLLSize;
+ }
+
+ return op - ostart;
+}
+
+FORCE_INLINE seq_t ZSTD_decodeSequenceLong_generic(seqState_t *seqState, int const longOffsets)
+{
+ seq_t seq;
+
+ U32 const llCode = FSE_peekSymbol(&seqState->stateLL);
+ U32 const mlCode = FSE_peekSymbol(&seqState->stateML);
+ U32 const ofCode = FSE_peekSymbol(&seqState->stateOffb); /* <= maxOff, by table construction */
+
+ U32 const llBits = LL_bits[llCode];
+ U32 const mlBits = ML_bits[mlCode];
+ U32 const ofBits = ofCode;
+ U32 const totalBits = llBits + mlBits + ofBits;
+
+ static const U32 LL_base[MaxLL + 1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18,
+ 20, 22, 24, 28, 32, 40, 48, 64, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000, 0x10000};
+
+ static const U32 ML_base[MaxML + 1] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
+ 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 37, 39, 41,
+ 43, 47, 51, 59, 67, 83, 99, 0x83, 0x103, 0x203, 0x403, 0x803, 0x1003, 0x2003, 0x4003, 0x8003, 0x10003};
+
+ static const U32 OF_base[MaxOff + 1] = {0, 1, 1, 5, 0xD, 0x1D, 0x3D, 0x7D, 0xFD, 0x1FD,
+ 0x3FD, 0x7FD, 0xFFD, 0x1FFD, 0x3FFD, 0x7FFD, 0xFFFD, 0x1FFFD, 0x3FFFD, 0x7FFFD,
+ 0xFFFFD, 0x1FFFFD, 0x3FFFFD, 0x7FFFFD, 0xFFFFFD, 0x1FFFFFD, 0x3FFFFFD, 0x7FFFFFD, 0xFFFFFFD};
+
+ /* sequence */
+ {
+ size_t offset;
+ if (!ofCode)
+ offset = 0;
+ else {
+ if (longOffsets) {
+ int const extraBits = ofBits - MIN(ofBits, STREAM_ACCUMULATOR_MIN);
+ offset = OF_base[ofCode] + (BIT_readBitsFast(&seqState->DStream, ofBits - extraBits) << extraBits);
+ if (ZSTD_32bits() || extraBits)
+ BIT_reloadDStream(&seqState->DStream);
+ if (extraBits)
+ offset += BIT_readBitsFast(&seqState->DStream, extraBits);
+ } else {
+ offset = OF_base[ofCode] + BIT_readBitsFast(&seqState->DStream, ofBits); /* <= (ZSTD_WINDOWLOG_MAX-1) bits */
+ if (ZSTD_32bits())
+ BIT_reloadDStream(&seqState->DStream);
+ }
+ }
+
+ if (ofCode <= 1) {
+ offset += (llCode == 0);
+ if (offset) {
+ size_t temp = (offset == 3) ? seqState->prevOffset[0] - 1 : seqState->prevOffset[offset];
+ temp += !temp; /* 0 is not valid; input is corrupted; force offset to 1 */
+ if (offset != 1)
+ seqState->prevOffset[2] = seqState->prevOffset[1];
+ seqState->prevOffset[1] = seqState->prevOffset[0];
+ seqState->prevOffset[0] = offset = temp;
+ } else {
+ offset = seqState->prevOffset[0];
+ }
+ } else {
+ seqState->prevOffset[2] = seqState->prevOffset[1];
+ seqState->prevOffset[1] = seqState->prevOffset[0];
+ seqState->prevOffset[0] = offset;
+ }
+ seq.offset = offset;
+ }
+
+ seq.matchLength = ML_base[mlCode] + ((mlCode > 31) ? BIT_readBitsFast(&seqState->DStream, mlBits) : 0); /* <= 16 bits */
+ if (ZSTD_32bits() && (mlBits + llBits > 24))
+ BIT_reloadDStream(&seqState->DStream);
+
+ seq.litLength = LL_base[llCode] + ((llCode > 15) ? BIT_readBitsFast(&seqState->DStream, llBits) : 0); /* <= 16 bits */
+ if (ZSTD_32bits() || (totalBits > 64 - 7 - (LLFSELog + MLFSELog + OffFSELog)))
+ BIT_reloadDStream(&seqState->DStream);
+
+ {
+ size_t const pos = seqState->pos + seq.litLength;
+ seq.match = seqState->base + pos - seq.offset; /* single memory segment */
+ if (seq.offset > pos)
+ seq.match += seqState->gotoDict; /* separate memory segment */
+ seqState->pos = pos + seq.matchLength;
+ }
+
+ /* ANS state update */
+ FSE_updateState(&seqState->stateLL, &seqState->DStream); /* <= 9 bits */
+ FSE_updateState(&seqState->stateML, &seqState->DStream); /* <= 9 bits */
+ if (ZSTD_32bits())
+ BIT_reloadDStream(&seqState->DStream); /* <= 18 bits */
+ FSE_updateState(&seqState->stateOffb, &seqState->DStream); /* <= 8 bits */
+
+ return seq;
+}
+
+static seq_t ZSTD_decodeSequenceLong(seqState_t *seqState, unsigned const windowSize)
+{
+ if (ZSTD_highbit32(windowSize) > STREAM_ACCUMULATOR_MIN) {
+ return ZSTD_decodeSequenceLong_generic(seqState, 1);
+ } else {
+ return ZSTD_decodeSequenceLong_generic(seqState, 0);
+ }
+}
+
+FORCE_INLINE
+size_t ZSTD_execSequenceLong(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base,
+ const BYTE *const vBase, const BYTE *const dictEnd)
+{
+ BYTE *const oLitEnd = op + sequence.litLength;
+ size_t const sequenceLength = sequence.litLength + sequence.matchLength;
+ BYTE *const oMatchEnd = op + sequenceLength; /* risk : address space overflow (32-bits) */
+ BYTE *const oend_w = oend - WILDCOPY_OVERLENGTH;
+ const BYTE *const iLitEnd = *litPtr + sequence.litLength;
+ const BYTE *match = sequence.match;
+
+ /* check */
+ if (oMatchEnd > oend)
+ return ERROR(dstSize_tooSmall); /* last match must start at a minimum distance of WILDCOPY_OVERLENGTH from oend */
+ if (iLitEnd > litLimit)
+ return ERROR(corruption_detected); /* over-read beyond lit buffer */
+ if (oLitEnd > oend_w)
+ return ZSTD_execSequenceLast7(op, oend, sequence, litPtr, litLimit, base, vBase, dictEnd);
+
+ /* copy Literals */
+ ZSTD_copy8(op, *litPtr);
+ if (sequence.litLength > 8)
+ ZSTD_wildcopy(op + 8, (*litPtr) + 8,
+ sequence.litLength - 8); /* note : since oLitEnd <= oend-WILDCOPY_OVERLENGTH, no risk of overwrite beyond oend */
+ op = oLitEnd;
+ *litPtr = iLitEnd; /* update for next sequence */
+
+ /* copy Match */
+ if (sequence.offset > (size_t)(oLitEnd - base)) {
+ /* offset beyond prefix */
+ if (sequence.offset > (size_t)(oLitEnd - vBase))
+ return ERROR(corruption_detected);
+ if (match + sequence.matchLength <= dictEnd) {
+ memmove(oLitEnd, match, sequence.matchLength);
+ return sequenceLength;
+ }
+ /* span extDict & currPrefixSegment */
+ {
+ size_t const length1 = dictEnd - match;
+ memmove(oLitEnd, match, length1);
+ op = oLitEnd + length1;
+ sequence.matchLength -= length1;
+ match = base;
+ if (op > oend_w || sequence.matchLength < MINMATCH) {
+ U32 i;
+ for (i = 0; i < sequence.matchLength; ++i)
+ op[i] = match[i];
+ return sequenceLength;
+ }
+ }
+ }
+ /* Requirement: op <= oend_w && sequence.matchLength >= MINMATCH */
+
+ /* match within prefix */
+ if (sequence.offset < 8) {
+ /* close range match, overlap */
+ static const U32 dec32table[] = {0, 1, 2, 1, 4, 4, 4, 4}; /* added */
+ static const int dec64table[] = {8, 8, 8, 7, 8, 9, 10, 11}; /* subtracted */
+ int const sub2 = dec64table[sequence.offset];
+ op[0] = match[0];
+ op[1] = match[1];
+ op[2] = match[2];
+ op[3] = match[3];
+ match += dec32table[sequence.offset];
+ ZSTD_copy4(op + 4, match);
+ match -= sub2;
+ } else {
+ ZSTD_copy8(op, match);
+ }
+ op += 8;
+ match += 8;
+
+ if (oMatchEnd > oend - (16 - MINMATCH)) {
+ if (op < oend_w) {
+ ZSTD_wildcopy(op, match, oend_w - op);
+ match += oend_w - op;
+ op = oend_w;
+ }
+ while (op < oMatchEnd)
+ *op++ = *match++;
+ } else {
+ ZSTD_wildcopy(op, match, (ptrdiff_t)sequence.matchLength - 8); /* works even if matchLength < 8 */
+ }
+ return sequenceLength;
+}
+
+static size_t ZSTD_decompressSequencesLong(ZSTD_DCtx *dctx, void *dst, size_t maxDstSize, const void *seqStart, size_t seqSize)
+{
+ const BYTE *ip = (const BYTE *)seqStart;
+ const BYTE *const iend = ip + seqSize;
+ BYTE *const ostart = (BYTE * const)dst;
+ BYTE *const oend = ostart + maxDstSize;
+ BYTE *op = ostart;
+ const BYTE *litPtr = dctx->litPtr;
+ const BYTE *const litEnd = litPtr + dctx->litSize;
+ const BYTE *const base = (const BYTE *)(dctx->base);
+ const BYTE *const vBase = (const BYTE *)(dctx->vBase);
+ const BYTE *const dictEnd = (const BYTE *)(dctx->dictEnd);
+ unsigned const windowSize = dctx->fParams.windowSize;
+ int nbSeq;
+
+ /* Build Decoding Tables */
+ {
+ size_t const seqHSize = ZSTD_decodeSeqHeaders(dctx, &nbSeq, ip, seqSize);
+ if (ZSTD_isError(seqHSize))
+ return seqHSize;
+ ip += seqHSize;
+ }
+
+ /* Regen sequences */
+ if (nbSeq) {
+#define STORED_SEQS 4
+#define STOSEQ_MASK (STORED_SEQS - 1)
+#define ADVANCED_SEQS 4
+ seq_t *sequences = (seq_t *)dctx->entropy.workspace;
+ int const seqAdvance = MIN(nbSeq, ADVANCED_SEQS);
+ seqState_t seqState;
+ int seqNb;
+ ZSTD_STATIC_ASSERT(sizeof(dctx->entropy.workspace) >= sizeof(seq_t) * STORED_SEQS);
+ dctx->fseEntropy = 1;
+ {
+ U32 i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ seqState.prevOffset[i] = dctx->entropy.rep[i];
+ }
+ seqState.base = base;
+ seqState.pos = (size_t)(op - base);
+ seqState.gotoDict = (uPtrDiff)dictEnd - (uPtrDiff)base; /* cast to avoid undefined behaviour */
+ CHECK_E(BIT_initDStream(&seqState.DStream, ip, iend - ip), corruption_detected);
+ FSE_initDState(&seqState.stateLL, &seqState.DStream, dctx->LLTptr);
+ FSE_initDState(&seqState.stateOffb, &seqState.DStream, dctx->OFTptr);
+ FSE_initDState(&seqState.stateML, &seqState.DStream, dctx->MLTptr);
+
+ /* prepare in advance */
+ for (seqNb = 0; (BIT_reloadDStream(&seqState.DStream) <= BIT_DStream_completed) && seqNb < seqAdvance; seqNb++) {
+ sequences[seqNb] = ZSTD_decodeSequenceLong(&seqState, windowSize);
+ }
+ if (seqNb < seqAdvance)
+ return ERROR(corruption_detected);
+
+ /* decode and decompress */
+ for (; (BIT_reloadDStream(&(seqState.DStream)) <= BIT_DStream_completed) && seqNb < nbSeq; seqNb++) {
+ seq_t const sequence = ZSTD_decodeSequenceLong(&seqState, windowSize);
+ size_t const oneSeqSize =
+ ZSTD_execSequenceLong(op, oend, sequences[(seqNb - ADVANCED_SEQS) & STOSEQ_MASK], &litPtr, litEnd, base, vBase, dictEnd);
+ if (ZSTD_isError(oneSeqSize))
+ return oneSeqSize;
+ ZSTD_PREFETCH(sequence.match);
+ sequences[seqNb & STOSEQ_MASK] = sequence;
+ op += oneSeqSize;
+ }
+ if (seqNb < nbSeq)
+ return ERROR(corruption_detected);
+
+ /* finish queue */
+ seqNb -= seqAdvance;
+ for (; seqNb < nbSeq; seqNb++) {
+ size_t const oneSeqSize = ZSTD_execSequenceLong(op, oend, sequences[seqNb & STOSEQ_MASK], &litPtr, litEnd, base, vBase, dictEnd);
+ if (ZSTD_isError(oneSeqSize))
+ return oneSeqSize;
+ op += oneSeqSize;
+ }
+
+ /* save reps for next block */
+ {
+ U32 i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ dctx->entropy.rep[i] = (U32)(seqState.prevOffset[i]);
+ }
+ }
+
+ /* last literal segment */
+ {
+ size_t const lastLLSize = litEnd - litPtr;
+ if (lastLLSize > (size_t)(oend - op))
+ return ERROR(dstSize_tooSmall);
+ memcpy(op, litPtr, lastLLSize);
+ op += lastLLSize;
+ }
+
+ return op - ostart;
+}
+
+static size_t ZSTD_decompressBlock_internal(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize)
+{ /* blockType == blockCompressed */
+ const BYTE *ip = (const BYTE *)src;
+
+ if (srcSize >= ZSTD_BLOCKSIZE_ABSOLUTEMAX)
+ return ERROR(srcSize_wrong);
+
+ /* Decode literals section */
+ {
+ size_t const litCSize = ZSTD_decodeLiteralsBlock(dctx, src, srcSize);
+ if (ZSTD_isError(litCSize))
+ return litCSize;
+ ip += litCSize;
+ srcSize -= litCSize;
+ }
+ if (sizeof(size_t) > 4) /* do not enable prefetching on 32-bits x86, as it's performance detrimental */
+ /* likely because of register pressure */
+ /* if that's the correct cause, then 32-bits ARM should be affected differently */
+ /* it would be good to test this on ARM real hardware, to see if prefetch version improves speed */
+ if (dctx->fParams.windowSize > (1 << 23))
+ return ZSTD_decompressSequencesLong(dctx, dst, dstCapacity, ip, srcSize);
+ return ZSTD_decompressSequences(dctx, dst, dstCapacity, ip, srcSize);
+}
+
+static void ZSTD_checkContinuity(ZSTD_DCtx *dctx, const void *dst)
+{
+ if (dst != dctx->previousDstEnd) { /* not contiguous */
+ dctx->dictEnd = dctx->previousDstEnd;
+ dctx->vBase = (const char *)dst - ((const char *)(dctx->previousDstEnd) - (const char *)(dctx->base));
+ dctx->base = dst;
+ dctx->previousDstEnd = dst;
+ }
+}
+
+size_t ZSTD_decompressBlock(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize)
+{
+ size_t dSize;
+ ZSTD_checkContinuity(dctx, dst);
+ dSize = ZSTD_decompressBlock_internal(dctx, dst, dstCapacity, src, srcSize);
+ dctx->previousDstEnd = (char *)dst + dSize;
+ return dSize;
+}
+
+/** ZSTD_insertBlock() :
+ insert `src` block into `dctx` history. Useful to track uncompressed blocks. */
+size_t ZSTD_insertBlock(ZSTD_DCtx *dctx, const void *blockStart, size_t blockSize)
+{
+ ZSTD_checkContinuity(dctx, blockStart);
+ dctx->previousDstEnd = (const char *)blockStart + blockSize;
+ return blockSize;
+}
+
+size_t ZSTD_generateNxBytes(void *dst, size_t dstCapacity, BYTE byte, size_t length)
+{
+ if (length > dstCapacity)
+ return ERROR(dstSize_tooSmall);
+ memset(dst, byte, length);
+ return length;
+}
+
+/** ZSTD_findFrameCompressedSize() :
+ * compatible with legacy mode
+ * `src` must point to the start of a ZSTD frame, ZSTD legacy frame, or skippable frame
+ * `srcSize` must be at least as large as the frame contained
+ * @return : the compressed size of the frame starting at `src` */
+size_t ZSTD_findFrameCompressedSize(const void *src, size_t srcSize)
+{
+ if (srcSize >= ZSTD_skippableHeaderSize && (ZSTD_readLE32(src) & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) {
+ return ZSTD_skippableHeaderSize + ZSTD_readLE32((const BYTE *)src + 4);
+ } else {
+ const BYTE *ip = (const BYTE *)src;
+ const BYTE *const ipstart = ip;
+ size_t remainingSize = srcSize;
+ ZSTD_frameParams fParams;
+
+ size_t const headerSize = ZSTD_frameHeaderSize(ip, remainingSize);
+ if (ZSTD_isError(headerSize))
+ return headerSize;
+
+ /* Frame Header */
+ {
+ size_t const ret = ZSTD_getFrameParams(&fParams, ip, remainingSize);
+ if (ZSTD_isError(ret))
+ return ret;
+ if (ret > 0)
+ return ERROR(srcSize_wrong);
+ }
+
+ ip += headerSize;
+ remainingSize -= headerSize;
+
+ /* Loop on each block */
+ while (1) {
+ blockProperties_t blockProperties;
+ size_t const cBlockSize = ZSTD_getcBlockSize(ip, remainingSize, &blockProperties);
+ if (ZSTD_isError(cBlockSize))
+ return cBlockSize;
+
+ if (ZSTD_blockHeaderSize + cBlockSize > remainingSize)
+ return ERROR(srcSize_wrong);
+
+ ip += ZSTD_blockHeaderSize + cBlockSize;
+ remainingSize -= ZSTD_blockHeaderSize + cBlockSize;
+
+ if (blockProperties.lastBlock)
+ break;
+ }
+
+ if (fParams.checksumFlag) { /* Frame content checksum */
+ if (remainingSize < 4)
+ return ERROR(srcSize_wrong);
+ ip += 4;
+ remainingSize -= 4;
+ }
+
+ return ip - ipstart;
+ }
+}
+
+/*! ZSTD_decompressFrame() :
+* @dctx must be properly initialized */
+static size_t ZSTD_decompressFrame(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void **srcPtr, size_t *srcSizePtr)
+{
+ const BYTE *ip = (const BYTE *)(*srcPtr);
+ BYTE *const ostart = (BYTE * const)dst;
+ BYTE *const oend = ostart + dstCapacity;
+ BYTE *op = ostart;
+ size_t remainingSize = *srcSizePtr;
+
+ /* check */
+ if (remainingSize < ZSTD_frameHeaderSize_min + ZSTD_blockHeaderSize)
+ return ERROR(srcSize_wrong);
+
+ /* Frame Header */
+ {
+ size_t const frameHeaderSize = ZSTD_frameHeaderSize(ip, ZSTD_frameHeaderSize_prefix);
+ if (ZSTD_isError(frameHeaderSize))
+ return frameHeaderSize;
+ if (remainingSize < frameHeaderSize + ZSTD_blockHeaderSize)
+ return ERROR(srcSize_wrong);
+ CHECK_F(ZSTD_decodeFrameHeader(dctx, ip, frameHeaderSize));
+ ip += frameHeaderSize;
+ remainingSize -= frameHeaderSize;
+ }
+
+ /* Loop on each block */
+ while (1) {
+ size_t decodedSize;
+ blockProperties_t blockProperties;
+ size_t const cBlockSize = ZSTD_getcBlockSize(ip, remainingSize, &blockProperties);
+ if (ZSTD_isError(cBlockSize))
+ return cBlockSize;
+
+ ip += ZSTD_blockHeaderSize;
+ remainingSize -= ZSTD_blockHeaderSize;
+ if (cBlockSize > remainingSize)
+ return ERROR(srcSize_wrong);
+
+ switch (blockProperties.blockType) {
+ case bt_compressed: decodedSize = ZSTD_decompressBlock_internal(dctx, op, oend - op, ip, cBlockSize); break;
+ case bt_raw: decodedSize = ZSTD_copyRawBlock(op, oend - op, ip, cBlockSize); break;
+ case bt_rle: decodedSize = ZSTD_generateNxBytes(op, oend - op, *ip, blockProperties.origSize); break;
+ case bt_reserved:
+ default: return ERROR(corruption_detected);
+ }
+
+ if (ZSTD_isError(decodedSize))
+ return decodedSize;
+ if (dctx->fParams.checksumFlag)
+ xxh64_update(&dctx->xxhState, op, decodedSize);
+ op += decodedSize;
+ ip += cBlockSize;
+ remainingSize -= cBlockSize;
+ if (blockProperties.lastBlock)
+ break;
+ }
+
+ if (dctx->fParams.checksumFlag) { /* Frame content checksum verification */
+ U32 const checkCalc = (U32)xxh64_digest(&dctx->xxhState);
+ U32 checkRead;
+ if (remainingSize < 4)
+ return ERROR(checksum_wrong);
+ checkRead = ZSTD_readLE32(ip);
+ if (checkRead != checkCalc)
+ return ERROR(checksum_wrong);
+ ip += 4;
+ remainingSize -= 4;
+ }
+
+ /* Allow caller to get size read */
+ *srcPtr = ip;
+ *srcSizePtr = remainingSize;
+ return op - ostart;
+}
+
+static const void *ZSTD_DDictDictContent(const ZSTD_DDict *ddict);
+static size_t ZSTD_DDictDictSize(const ZSTD_DDict *ddict);
+
+static size_t ZSTD_decompressMultiFrame(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize, const void *dict, size_t dictSize,
+ const ZSTD_DDict *ddict)
+{
+ void *const dststart = dst;
+
+ if (ddict) {
+ if (dict) {
+ /* programmer error, these two cases should be mutually exclusive */
+ return ERROR(GENERIC);
+ }
+
+ dict = ZSTD_DDictDictContent(ddict);
+ dictSize = ZSTD_DDictDictSize(ddict);
+ }
+
+ while (srcSize >= ZSTD_frameHeaderSize_prefix) {
+ U32 magicNumber;
+
+ magicNumber = ZSTD_readLE32(src);
+ if (magicNumber != ZSTD_MAGICNUMBER) {
+ if ((magicNumber & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) {
+ size_t skippableSize;
+ if (srcSize < ZSTD_skippableHeaderSize)
+ return ERROR(srcSize_wrong);
+ skippableSize = ZSTD_readLE32((const BYTE *)src + 4) + ZSTD_skippableHeaderSize;
+ if (srcSize < skippableSize) {
+ return ERROR(srcSize_wrong);
+ }
+
+ src = (const BYTE *)src + skippableSize;
+ srcSize -= skippableSize;
+ continue;
+ } else {
+ return ERROR(prefix_unknown);
+ }
+ }
+
+ if (ddict) {
+ /* we were called from ZSTD_decompress_usingDDict */
+ ZSTD_refDDict(dctx, ddict);
+ } else {
+ /* this will initialize correctly with no dict if dict == NULL, so
+ * use this in all cases but ddict */
+ CHECK_F(ZSTD_decompressBegin_usingDict(dctx, dict, dictSize));
+ }
+ ZSTD_checkContinuity(dctx, dst);
+
+ {
+ const size_t res = ZSTD_decompressFrame(dctx, dst, dstCapacity, &src, &srcSize);
+ if (ZSTD_isError(res))
+ return res;
+ /* don't need to bounds check this, ZSTD_decompressFrame will have
+ * already */
+ dst = (BYTE *)dst + res;
+ dstCapacity -= res;
+ }
+ }
+
+ if (srcSize)
+ return ERROR(srcSize_wrong); /* input not entirely consumed */
+
+ return (BYTE *)dst - (BYTE *)dststart;
+}
+
+size_t ZSTD_decompress_usingDict(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize, const void *dict, size_t dictSize)
+{
+ return ZSTD_decompressMultiFrame(dctx, dst, dstCapacity, src, srcSize, dict, dictSize, NULL);
+}
+
+size_t ZSTD_decompressDCtx(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize)
+{
+ return ZSTD_decompress_usingDict(dctx, dst, dstCapacity, src, srcSize, NULL, 0);
+}
+
+/*-**************************************
+* Advanced Streaming Decompression API
+* Bufferless and synchronous
+****************************************/
+size_t ZSTD_nextSrcSizeToDecompress(ZSTD_DCtx *dctx) { return dctx->expected; }
+
+ZSTD_nextInputType_e ZSTD_nextInputType(ZSTD_DCtx *dctx)
+{
+ switch (dctx->stage) {
+ default: /* should not happen */
+ case ZSTDds_getFrameHeaderSize:
+ case ZSTDds_decodeFrameHeader: return ZSTDnit_frameHeader;
+ case ZSTDds_decodeBlockHeader: return ZSTDnit_blockHeader;
+ case ZSTDds_decompressBlock: return ZSTDnit_block;
+ case ZSTDds_decompressLastBlock: return ZSTDnit_lastBlock;
+ case ZSTDds_checkChecksum: return ZSTDnit_checksum;
+ case ZSTDds_decodeSkippableHeader:
+ case ZSTDds_skipFrame: return ZSTDnit_skippableFrame;
+ }
+}
+
+int ZSTD_isSkipFrame(ZSTD_DCtx *dctx) { return dctx->stage == ZSTDds_skipFrame; } /* for zbuff */
+
+/** ZSTD_decompressContinue() :
+* @return : nb of bytes generated into `dst` (necessarily <= `dstCapacity)
+* or an error code, which can be tested using ZSTD_isError() */
+size_t ZSTD_decompressContinue(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize)
+{
+ /* Sanity check */
+ if (srcSize != dctx->expected)
+ return ERROR(srcSize_wrong);
+ if (dstCapacity)
+ ZSTD_checkContinuity(dctx, dst);
+
+ switch (dctx->stage) {
+ case ZSTDds_getFrameHeaderSize:
+ if (srcSize != ZSTD_frameHeaderSize_prefix)
+ return ERROR(srcSize_wrong); /* impossible */
+ if ((ZSTD_readLE32(src) & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) { /* skippable frame */
+ memcpy(dctx->headerBuffer, src, ZSTD_frameHeaderSize_prefix);
+ dctx->expected = ZSTD_skippableHeaderSize - ZSTD_frameHeaderSize_prefix; /* magic number + skippable frame length */
+ dctx->stage = ZSTDds_decodeSkippableHeader;
+ return 0;
+ }
+ dctx->headerSize = ZSTD_frameHeaderSize(src, ZSTD_frameHeaderSize_prefix);
+ if (ZSTD_isError(dctx->headerSize))
+ return dctx->headerSize;
+ memcpy(dctx->headerBuffer, src, ZSTD_frameHeaderSize_prefix);
+ if (dctx->headerSize > ZSTD_frameHeaderSize_prefix) {
+ dctx->expected = dctx->headerSize - ZSTD_frameHeaderSize_prefix;
+ dctx->stage = ZSTDds_decodeFrameHeader;
+ return 0;
+ }
+ dctx->expected = 0; /* not necessary to copy more */
+
+ case ZSTDds_decodeFrameHeader:
+ memcpy(dctx->headerBuffer + ZSTD_frameHeaderSize_prefix, src, dctx->expected);
+ CHECK_F(ZSTD_decodeFrameHeader(dctx, dctx->headerBuffer, dctx->headerSize));
+ dctx->expected = ZSTD_blockHeaderSize;
+ dctx->stage = ZSTDds_decodeBlockHeader;
+ return 0;
+
+ case ZSTDds_decodeBlockHeader: {
+ blockProperties_t bp;
+ size_t const cBlockSize = ZSTD_getcBlockSize(src, ZSTD_blockHeaderSize, &bp);
+ if (ZSTD_isError(cBlockSize))
+ return cBlockSize;
+ dctx->expected = cBlockSize;
+ dctx->bType = bp.blockType;
+ dctx->rleSize = bp.origSize;
+ if (cBlockSize) {
+ dctx->stage = bp.lastBlock ? ZSTDds_decompressLastBlock : ZSTDds_decompressBlock;
+ return 0;
+ }
+ /* empty block */
+ if (bp.lastBlock) {
+ if (dctx->fParams.checksumFlag) {
+ dctx->expected = 4;
+ dctx->stage = ZSTDds_checkChecksum;
+ } else {
+ dctx->expected = 0; /* end of frame */
+ dctx->stage = ZSTDds_getFrameHeaderSize;
+ }
+ } else {
+ dctx->expected = 3; /* go directly to next header */
+ dctx->stage = ZSTDds_decodeBlockHeader;
+ }
+ return 0;
+ }
+ case ZSTDds_decompressLastBlock:
+ case ZSTDds_decompressBlock: {
+ size_t rSize;
+ switch (dctx->bType) {
+ case bt_compressed: rSize = ZSTD_decompressBlock_internal(dctx, dst, dstCapacity, src, srcSize); break;
+ case bt_raw: rSize = ZSTD_copyRawBlock(dst, dstCapacity, src, srcSize); break;
+ case bt_rle: rSize = ZSTD_setRleBlock(dst, dstCapacity, src, srcSize, dctx->rleSize); break;
+ case bt_reserved: /* should never happen */
+ default: return ERROR(corruption_detected);
+ }
+ if (ZSTD_isError(rSize))
+ return rSize;
+ if (dctx->fParams.checksumFlag)
+ xxh64_update(&dctx->xxhState, dst, rSize);
+
+ if (dctx->stage == ZSTDds_decompressLastBlock) { /* end of frame */
+ if (dctx->fParams.checksumFlag) { /* another round for frame checksum */
+ dctx->expected = 4;
+ dctx->stage = ZSTDds_checkChecksum;
+ } else {
+ dctx->expected = 0; /* ends here */
+ dctx->stage = ZSTDds_getFrameHeaderSize;
+ }
+ } else {
+ dctx->stage = ZSTDds_decodeBlockHeader;
+ dctx->expected = ZSTD_blockHeaderSize;
+ dctx->previousDstEnd = (char *)dst + rSize;
+ }
+ return rSize;
+ }
+ case ZSTDds_checkChecksum: {
+ U32 const h32 = (U32)xxh64_digest(&dctx->xxhState);
+ U32 const check32 = ZSTD_readLE32(src); /* srcSize == 4, guaranteed by dctx->expected */
+ if (check32 != h32)
+ return ERROR(checksum_wrong);
+ dctx->expected = 0;
+ dctx->stage = ZSTDds_getFrameHeaderSize;
+ return 0;
+ }
+ case ZSTDds_decodeSkippableHeader: {
+ memcpy(dctx->headerBuffer + ZSTD_frameHeaderSize_prefix, src, dctx->expected);
+ dctx->expected = ZSTD_readLE32(dctx->headerBuffer + 4);
+ dctx->stage = ZSTDds_skipFrame;
+ return 0;
+ }
+ case ZSTDds_skipFrame: {
+ dctx->expected = 0;
+ dctx->stage = ZSTDds_getFrameHeaderSize;
+ return 0;
+ }
+ default:
+ return ERROR(GENERIC); /* impossible */
+ }
+}
+
+static size_t ZSTD_refDictContent(ZSTD_DCtx *dctx, const void *dict, size_t dictSize)
+{
+ dctx->dictEnd = dctx->previousDstEnd;
+ dctx->vBase = (const char *)dict - ((const char *)(dctx->previousDstEnd) - (const char *)(dctx->base));
+ dctx->base = dict;
+ dctx->previousDstEnd = (const char *)dict + dictSize;
+ return 0;
+}
+
+/* ZSTD_loadEntropy() :
+ * dict : must point at beginning of a valid zstd dictionary
+ * @return : size of entropy tables read */
+static size_t ZSTD_loadEntropy(ZSTD_entropyTables_t *entropy, const void *const dict, size_t const dictSize)
+{
+ const BYTE *dictPtr = (const BYTE *)dict;
+ const BYTE *const dictEnd = dictPtr + dictSize;
+
+ if (dictSize <= 8)
+ return ERROR(dictionary_corrupted);
+ dictPtr += 8; /* skip header = magic + dictID */
+
+ {
+ size_t const hSize = HUF_readDTableX4_wksp(entropy->hufTable, dictPtr, dictEnd - dictPtr, entropy->workspace, sizeof(entropy->workspace));
+ if (HUF_isError(hSize))
+ return ERROR(dictionary_corrupted);
+ dictPtr += hSize;
+ }
+
+ {
+ short offcodeNCount[MaxOff + 1];
+ U32 offcodeMaxValue = MaxOff, offcodeLog;
+ size_t const offcodeHeaderSize = FSE_readNCount(offcodeNCount, &offcodeMaxValue, &offcodeLog, dictPtr, dictEnd - dictPtr);
+ if (FSE_isError(offcodeHeaderSize))
+ return ERROR(dictionary_corrupted);
+ if (offcodeLog > OffFSELog)
+ return ERROR(dictionary_corrupted);
+ CHECK_E(FSE_buildDTable_wksp(entropy->OFTable, offcodeNCount, offcodeMaxValue, offcodeLog, entropy->workspace, sizeof(entropy->workspace)), dictionary_corrupted);
+ dictPtr += offcodeHeaderSize;
+ }
+
+ {
+ short matchlengthNCount[MaxML + 1];
+ unsigned matchlengthMaxValue = MaxML, matchlengthLog;
+ size_t const matchlengthHeaderSize = FSE_readNCount(matchlengthNCount, &matchlengthMaxValue, &matchlengthLog, dictPtr, dictEnd - dictPtr);
+ if (FSE_isError(matchlengthHeaderSize))
+ return ERROR(dictionary_corrupted);
+ if (matchlengthLog > MLFSELog)
+ return ERROR(dictionary_corrupted);
+ CHECK_E(FSE_buildDTable_wksp(entropy->MLTable, matchlengthNCount, matchlengthMaxValue, matchlengthLog, entropy->workspace, sizeof(entropy->workspace)), dictionary_corrupted);
+ dictPtr += matchlengthHeaderSize;
+ }
+
+ {
+ short litlengthNCount[MaxLL + 1];
+ unsigned litlengthMaxValue = MaxLL, litlengthLog;
+ size_t const litlengthHeaderSize = FSE_readNCount(litlengthNCount, &litlengthMaxValue, &litlengthLog, dictPtr, dictEnd - dictPtr);
+ if (FSE_isError(litlengthHeaderSize))
+ return ERROR(dictionary_corrupted);
+ if (litlengthLog > LLFSELog)
+ return ERROR(dictionary_corrupted);
+ CHECK_E(FSE_buildDTable_wksp(entropy->LLTable, litlengthNCount, litlengthMaxValue, litlengthLog, entropy->workspace, sizeof(entropy->workspace)), dictionary_corrupted);
+ dictPtr += litlengthHeaderSize;
+ }
+
+ if (dictPtr + 12 > dictEnd)
+ return ERROR(dictionary_corrupted);
+ {
+ int i;
+ size_t const dictContentSize = (size_t)(dictEnd - (dictPtr + 12));
+ for (i = 0; i < 3; i++) {
+ U32 const rep = ZSTD_readLE32(dictPtr);
+ dictPtr += 4;
+ if (rep == 0 || rep >= dictContentSize)
+ return ERROR(dictionary_corrupted);
+ entropy->rep[i] = rep;
+ }
+ }
+
+ return dictPtr - (const BYTE *)dict;
+}
+
+static size_t ZSTD_decompress_insertDictionary(ZSTD_DCtx *dctx, const void *dict, size_t dictSize)
+{
+ if (dictSize < 8)
+ return ZSTD_refDictContent(dctx, dict, dictSize);
+ {
+ U32 const magic = ZSTD_readLE32(dict);
+ if (magic != ZSTD_DICT_MAGIC) {
+ return ZSTD_refDictContent(dctx, dict, dictSize); /* pure content mode */
+ }
+ }
+ dctx->dictID = ZSTD_readLE32((const char *)dict + 4);
+
+ /* load entropy tables */
+ {
+ size_t const eSize = ZSTD_loadEntropy(&dctx->entropy, dict, dictSize);
+ if (ZSTD_isError(eSize))
+ return ERROR(dictionary_corrupted);
+ dict = (const char *)dict + eSize;
+ dictSize -= eSize;
+ }
+ dctx->litEntropy = dctx->fseEntropy = 1;
+
+ /* reference dictionary content */
+ return ZSTD_refDictContent(dctx, dict, dictSize);
+}
+
+size_t ZSTD_decompressBegin_usingDict(ZSTD_DCtx *dctx, const void *dict, size_t dictSize)
+{
+ CHECK_F(ZSTD_decompressBegin(dctx));
+ if (dict && dictSize)
+ CHECK_E(ZSTD_decompress_insertDictionary(dctx, dict, dictSize), dictionary_corrupted);
+ return 0;
+}
+
+/* ====== ZSTD_DDict ====== */
+
+struct ZSTD_DDict_s {
+ void *dictBuffer;
+ const void *dictContent;
+ size_t dictSize;
+ ZSTD_entropyTables_t entropy;
+ U32 dictID;
+ U32 entropyPresent;
+ ZSTD_customMem cMem;
+}; /* typedef'd to ZSTD_DDict within "zstd.h" */
+
+size_t ZSTD_DDictWorkspaceBound(void) { return ZSTD_ALIGN(sizeof(ZSTD_stack)) + ZSTD_ALIGN(sizeof(ZSTD_DDict)); }
+
+static const void *ZSTD_DDictDictContent(const ZSTD_DDict *ddict) { return ddict->dictContent; }
+
+static size_t ZSTD_DDictDictSize(const ZSTD_DDict *ddict) { return ddict->dictSize; }
+
+static void ZSTD_refDDict(ZSTD_DCtx *dstDCtx, const ZSTD_DDict *ddict)
+{
+ ZSTD_decompressBegin(dstDCtx); /* init */
+ if (ddict) { /* support refDDict on NULL */
+ dstDCtx->dictID = ddict->dictID;
+ dstDCtx->base = ddict->dictContent;
+ dstDCtx->vBase = ddict->dictContent;
+ dstDCtx->dictEnd = (const BYTE *)ddict->dictContent + ddict->dictSize;
+ dstDCtx->previousDstEnd = dstDCtx->dictEnd;
+ if (ddict->entropyPresent) {
+ dstDCtx->litEntropy = 1;
+ dstDCtx->fseEntropy = 1;
+ dstDCtx->LLTptr = ddict->entropy.LLTable;
+ dstDCtx->MLTptr = ddict->entropy.MLTable;
+ dstDCtx->OFTptr = ddict->entropy.OFTable;
+ dstDCtx->HUFptr = ddict->entropy.hufTable;
+ dstDCtx->entropy.rep[0] = ddict->entropy.rep[0];
+ dstDCtx->entropy.rep[1] = ddict->entropy.rep[1];
+ dstDCtx->entropy.rep[2] = ddict->entropy.rep[2];
+ } else {
+ dstDCtx->litEntropy = 0;
+ dstDCtx->fseEntropy = 0;
+ }
+ }
+}
+
+static size_t ZSTD_loadEntropy_inDDict(ZSTD_DDict *ddict)
+{
+ ddict->dictID = 0;
+ ddict->entropyPresent = 0;
+ if (ddict->dictSize < 8)
+ return 0;
+ {
+ U32 const magic = ZSTD_readLE32(ddict->dictContent);
+ if (magic != ZSTD_DICT_MAGIC)
+ return 0; /* pure content mode */
+ }
+ ddict->dictID = ZSTD_readLE32((const char *)ddict->dictContent + 4);
+
+ /* load entropy tables */
+ CHECK_E(ZSTD_loadEntropy(&ddict->entropy, ddict->dictContent, ddict->dictSize), dictionary_corrupted);
+ ddict->entropyPresent = 1;
+ return 0;
+}
+
+static ZSTD_DDict *ZSTD_createDDict_advanced(const void *dict, size_t dictSize, unsigned byReference, ZSTD_customMem customMem)
+{
+ if (!customMem.customAlloc || !customMem.customFree)
+ return NULL;
+
+ {
+ ZSTD_DDict *const ddict = (ZSTD_DDict *)ZSTD_malloc(sizeof(ZSTD_DDict), customMem);
+ if (!ddict)
+ return NULL;
+ ddict->cMem = customMem;
+
+ if ((byReference) || (!dict) || (!dictSize)) {
+ ddict->dictBuffer = NULL;
+ ddict->dictContent = dict;
+ } else {
+ void *const internalBuffer = ZSTD_malloc(dictSize, customMem);
+ if (!internalBuffer) {
+ ZSTD_freeDDict(ddict);
+ return NULL;
+ }
+ memcpy(internalBuffer, dict, dictSize);
+ ddict->dictBuffer = internalBuffer;
+ ddict->dictContent = internalBuffer;
+ }
+ ddict->dictSize = dictSize;
+ ddict->entropy.hufTable[0] = (HUF_DTable)((HufLog)*0x1000001); /* cover both little and big endian */
+ /* parse dictionary content */
+ {
+ size_t const errorCode = ZSTD_loadEntropy_inDDict(ddict);
+ if (ZSTD_isError(errorCode)) {
+ ZSTD_freeDDict(ddict);
+ return NULL;
+ }
+ }
+
+ return ddict;
+ }
+}
+
+/*! ZSTD_initDDict() :
+* Create a digested dictionary, to start decompression without startup delay.
+* `dict` content is copied inside DDict.
+* Consequently, `dict` can be released after `ZSTD_DDict` creation */
+ZSTD_DDict *ZSTD_initDDict(const void *dict, size_t dictSize, void *workspace, size_t workspaceSize)
+{
+ ZSTD_customMem const stackMem = ZSTD_initStack(workspace, workspaceSize);
+ return ZSTD_createDDict_advanced(dict, dictSize, 1, stackMem);
+}
+
+size_t ZSTD_freeDDict(ZSTD_DDict *ddict)
+{
+ if (ddict == NULL)
+ return 0; /* support free on NULL */
+ {
+ ZSTD_customMem const cMem = ddict->cMem;
+ ZSTD_free(ddict->dictBuffer, cMem);
+ ZSTD_free(ddict, cMem);
+ return 0;
+ }
+}
+
+/*! ZSTD_getDictID_fromDict() :
+ * Provides the dictID stored within dictionary.
+ * if @return == 0, the dictionary is not conformant with Zstandard specification.
+ * It can still be loaded, but as a content-only dictionary. */
+unsigned ZSTD_getDictID_fromDict(const void *dict, size_t dictSize)
+{
+ if (dictSize < 8)
+ return 0;
+ if (ZSTD_readLE32(dict) != ZSTD_DICT_MAGIC)
+ return 0;
+ return ZSTD_readLE32((const char *)dict + 4);
+}
+
+/*! ZSTD_getDictID_fromDDict() :
+ * Provides the dictID of the dictionary loaded into `ddict`.
+ * If @return == 0, the dictionary is not conformant to Zstandard specification, or empty.
+ * Non-conformant dictionaries can still be loaded, but as content-only dictionaries. */
+unsigned ZSTD_getDictID_fromDDict(const ZSTD_DDict *ddict)
+{
+ if (ddict == NULL)
+ return 0;
+ return ZSTD_getDictID_fromDict(ddict->dictContent, ddict->dictSize);
+}
+
+/*! ZSTD_getDictID_fromFrame() :
+ * Provides the dictID required to decompressed the frame stored within `src`.
+ * If @return == 0, the dictID could not be decoded.
+ * This could for one of the following reasons :
+ * - The frame does not require a dictionary to be decoded (most common case).
+ * - The frame was built with dictID intentionally removed. Whatever dictionary is necessary is a hidden information.
+ * Note : this use case also happens when using a non-conformant dictionary.
+ * - `srcSize` is too small, and as a result, the frame header could not be decoded (only possible if `srcSize < ZSTD_FRAMEHEADERSIZE_MAX`).
+ * - This is not a Zstandard frame.
+ * When identifying the exact failure cause, it's possible to used ZSTD_getFrameParams(), which will provide a more precise error code. */
+unsigned ZSTD_getDictID_fromFrame(const void *src, size_t srcSize)
+{
+ ZSTD_frameParams zfp = {0, 0, 0, 0};
+ size_t const hError = ZSTD_getFrameParams(&zfp, src, srcSize);
+ if (ZSTD_isError(hError))
+ return 0;
+ return zfp.dictID;
+}
+
+/*! ZSTD_decompress_usingDDict() :
+* Decompression using a pre-digested Dictionary
+* Use dictionary without significant overhead. */
+size_t ZSTD_decompress_usingDDict(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize, const ZSTD_DDict *ddict)
+{
+ /* pass content and size in case legacy frames are encountered */
+ return ZSTD_decompressMultiFrame(dctx, dst, dstCapacity, src, srcSize, NULL, 0, ddict);
+}
+
+/*=====================================
+* Streaming decompression
+*====================================*/
+
+typedef enum { zdss_init, zdss_loadHeader, zdss_read, zdss_load, zdss_flush } ZSTD_dStreamStage;
+
+/* *** Resource management *** */
+struct ZSTD_DStream_s {
+ ZSTD_DCtx *dctx;
+ ZSTD_DDict *ddictLocal;
+ const ZSTD_DDict *ddict;
+ ZSTD_frameParams fParams;
+ ZSTD_dStreamStage stage;
+ char *inBuff;
+ size_t inBuffSize;
+ size_t inPos;
+ size_t maxWindowSize;
+ char *outBuff;
+ size_t outBuffSize;
+ size_t outStart;
+ size_t outEnd;
+ size_t blockSize;
+ BYTE headerBuffer[ZSTD_FRAMEHEADERSIZE_MAX]; /* tmp buffer to store frame header */
+ size_t lhSize;
+ ZSTD_customMem customMem;
+ void *legacyContext;
+ U32 previousLegacyVersion;
+ U32 legacyVersion;
+ U32 hostageByte;
+}; /* typedef'd to ZSTD_DStream within "zstd.h" */
+
+size_t ZSTD_DStreamWorkspaceBound(size_t maxWindowSize)
+{
+ size_t const blockSize = MIN(maxWindowSize, ZSTD_BLOCKSIZE_ABSOLUTEMAX);
+ size_t const inBuffSize = blockSize;
+ size_t const outBuffSize = maxWindowSize + blockSize + WILDCOPY_OVERLENGTH * 2;
+ return ZSTD_DCtxWorkspaceBound() + ZSTD_ALIGN(sizeof(ZSTD_DStream)) + ZSTD_ALIGN(inBuffSize) + ZSTD_ALIGN(outBuffSize);
+}
+
+static ZSTD_DStream *ZSTD_createDStream_advanced(ZSTD_customMem customMem)
+{
+ ZSTD_DStream *zds;
+
+ if (!customMem.customAlloc || !customMem.customFree)
+ return NULL;
+
+ zds = (ZSTD_DStream *)ZSTD_malloc(sizeof(ZSTD_DStream), customMem);
+ if (zds == NULL)
+ return NULL;
+ memset(zds, 0, sizeof(ZSTD_DStream));
+ memcpy(&zds->customMem, &customMem, sizeof(ZSTD_customMem));
+ zds->dctx = ZSTD_createDCtx_advanced(customMem);
+ if (zds->dctx == NULL) {
+ ZSTD_freeDStream(zds);
+ return NULL;
+ }
+ zds->stage = zdss_init;
+ zds->maxWindowSize = ZSTD_MAXWINDOWSIZE_DEFAULT;
+ return zds;
+}
+
+ZSTD_DStream *ZSTD_initDStream(size_t maxWindowSize, void *workspace, size_t workspaceSize)
+{
+ ZSTD_customMem const stackMem = ZSTD_initStack(workspace, workspaceSize);
+ ZSTD_DStream *zds = ZSTD_createDStream_advanced(stackMem);
+ if (!zds) {
+ return NULL;
+ }
+
+ zds->maxWindowSize = maxWindowSize;
+ zds->stage = zdss_loadHeader;
+ zds->lhSize = zds->inPos = zds->outStart = zds->outEnd = 0;
+ ZSTD_freeDDict(zds->ddictLocal);
+ zds->ddictLocal = NULL;
+ zds->ddict = zds->ddictLocal;
+ zds->legacyVersion = 0;
+ zds->hostageByte = 0;
+
+ {
+ size_t const blockSize = MIN(zds->maxWindowSize, ZSTD_BLOCKSIZE_ABSOLUTEMAX);
+ size_t const neededOutSize = zds->maxWindowSize + blockSize + WILDCOPY_OVERLENGTH * 2;
+
+ zds->inBuff = (char *)ZSTD_malloc(blockSize, zds->customMem);
+ zds->inBuffSize = blockSize;
+ zds->outBuff = (char *)ZSTD_malloc(neededOutSize, zds->customMem);
+ zds->outBuffSize = neededOutSize;
+ if (zds->inBuff == NULL || zds->outBuff == NULL) {
+ ZSTD_freeDStream(zds);
+ return NULL;
+ }
+ }
+ return zds;
+}
+
+ZSTD_DStream *ZSTD_initDStream_usingDDict(size_t maxWindowSize, const ZSTD_DDict *ddict, void *workspace, size_t workspaceSize)
+{
+ ZSTD_DStream *zds = ZSTD_initDStream(maxWindowSize, workspace, workspaceSize);
+ if (zds) {
+ zds->ddict = ddict;
+ }
+ return zds;
+}
+
+size_t ZSTD_freeDStream(ZSTD_DStream *zds)
+{
+ if (zds == NULL)
+ return 0; /* support free on null */
+ {
+ ZSTD_customMem const cMem = zds->customMem;
+ ZSTD_freeDCtx(zds->dctx);
+ zds->dctx = NULL;
+ ZSTD_freeDDict(zds->ddictLocal);
+ zds->ddictLocal = NULL;
+ ZSTD_free(zds->inBuff, cMem);
+ zds->inBuff = NULL;
+ ZSTD_free(zds->outBuff, cMem);
+ zds->outBuff = NULL;
+ ZSTD_free(zds, cMem);
+ return 0;
+ }
+}
+
+/* *** Initialization *** */
+
+size_t ZSTD_DStreamInSize(void) { return ZSTD_BLOCKSIZE_ABSOLUTEMAX + ZSTD_blockHeaderSize; }
+size_t ZSTD_DStreamOutSize(void) { return ZSTD_BLOCKSIZE_ABSOLUTEMAX; }
+
+size_t ZSTD_resetDStream(ZSTD_DStream *zds)
+{
+ zds->stage = zdss_loadHeader;
+ zds->lhSize = zds->inPos = zds->outStart = zds->outEnd = 0;
+ zds->legacyVersion = 0;
+ zds->hostageByte = 0;
+ return ZSTD_frameHeaderSize_prefix;
+}
+
+/* ***** Decompression ***** */
+
+ZSTD_STATIC size_t ZSTD_limitCopy(void *dst, size_t dstCapacity, const void *src, size_t srcSize)
+{
+ size_t const length = MIN(dstCapacity, srcSize);
+ memcpy(dst, src, length);
+ return length;
+}
+
+size_t ZSTD_decompressStream(ZSTD_DStream *zds, ZSTD_outBuffer *output, ZSTD_inBuffer *input)
+{
+ const char *const istart = (const char *)(input->src) + input->pos;
+ const char *const iend = (const char *)(input->src) + input->size;
+ const char *ip = istart;
+ char *const ostart = (char *)(output->dst) + output->pos;
+ char *const oend = (char *)(output->dst) + output->size;
+ char *op = ostart;
+ U32 someMoreWork = 1;
+
+ while (someMoreWork) {
+ switch (zds->stage) {
+ case zdss_init:
+ ZSTD_resetDStream(zds); /* transparent reset on starting decoding a new frame */
+ /* fall-through */
+
+ case zdss_loadHeader: {
+ size_t const hSize = ZSTD_getFrameParams(&zds->fParams, zds->headerBuffer, zds->lhSize);
+ if (ZSTD_isError(hSize))
+ return hSize;
+ if (hSize != 0) { /* need more input */
+ size_t const toLoad = hSize - zds->lhSize; /* if hSize!=0, hSize > zds->lhSize */
+ if (toLoad > (size_t)(iend - ip)) { /* not enough input to load full header */
+ memcpy(zds->headerBuffer + zds->lhSize, ip, iend - ip);
+ zds->lhSize += iend - ip;
+ input->pos = input->size;
+ return (MAX(ZSTD_frameHeaderSize_min, hSize) - zds->lhSize) +
+ ZSTD_blockHeaderSize; /* remaining header bytes + next block header */
+ }
+ memcpy(zds->headerBuffer + zds->lhSize, ip, toLoad);
+ zds->lhSize = hSize;
+ ip += toLoad;
+ break;
+ }
+
+ /* check for single-pass mode opportunity */
+ if (zds->fParams.frameContentSize && zds->fParams.windowSize /* skippable frame if == 0 */
+ && (U64)(size_t)(oend - op) >= zds->fParams.frameContentSize) {
+ size_t const cSize = ZSTD_findFrameCompressedSize(istart, iend - istart);
+ if (cSize <= (size_t)(iend - istart)) {
+ size_t const decompressedSize = ZSTD_decompress_usingDDict(zds->dctx, op, oend - op, istart, cSize, zds->ddict);
+ if (ZSTD_isError(decompressedSize))
+ return decompressedSize;
+ ip = istart + cSize;
+ op += decompressedSize;
+ zds->dctx->expected = 0;
+ zds->stage = zdss_init;
+ someMoreWork = 0;
+ break;
+ }
+ }
+
+ /* Consume header */
+ ZSTD_refDDict(zds->dctx, zds->ddict);
+ {
+ size_t const h1Size = ZSTD_nextSrcSizeToDecompress(zds->dctx); /* == ZSTD_frameHeaderSize_prefix */
+ CHECK_F(ZSTD_decompressContinue(zds->dctx, NULL, 0, zds->headerBuffer, h1Size));
+ {
+ size_t const h2Size = ZSTD_nextSrcSizeToDecompress(zds->dctx);
+ CHECK_F(ZSTD_decompressContinue(zds->dctx, NULL, 0, zds->headerBuffer + h1Size, h2Size));
+ }
+ }
+
+ zds->fParams.windowSize = MAX(zds->fParams.windowSize, 1U << ZSTD_WINDOWLOG_ABSOLUTEMIN);
+ if (zds->fParams.windowSize > zds->maxWindowSize)
+ return ERROR(frameParameter_windowTooLarge);
+
+ /* Buffers are preallocated, but double check */
+ {
+ size_t const blockSize = MIN(zds->maxWindowSize, ZSTD_BLOCKSIZE_ABSOLUTEMAX);
+ size_t const neededOutSize = zds->maxWindowSize + blockSize + WILDCOPY_OVERLENGTH * 2;
+ if (zds->inBuffSize < blockSize) {
+ return ERROR(GENERIC);
+ }
+ if (zds->outBuffSize < neededOutSize) {
+ return ERROR(GENERIC);
+ }
+ zds->blockSize = blockSize;
+ }
+ zds->stage = zdss_read;
+ }
+ /* pass-through */
+
+ case zdss_read: {
+ size_t const neededInSize = ZSTD_nextSrcSizeToDecompress(zds->dctx);
+ if (neededInSize == 0) { /* end of frame */
+ zds->stage = zdss_init;
+ someMoreWork = 0;
+ break;
+ }
+ if ((size_t)(iend - ip) >= neededInSize) { /* decode directly from src */
+ const int isSkipFrame = ZSTD_isSkipFrame(zds->dctx);
+ size_t const decodedSize = ZSTD_decompressContinue(zds->dctx, zds->outBuff + zds->outStart,
+ (isSkipFrame ? 0 : zds->outBuffSize - zds->outStart), ip, neededInSize);
+ if (ZSTD_isError(decodedSize))
+ return decodedSize;
+ ip += neededInSize;
+ if (!decodedSize && !isSkipFrame)
+ break; /* this was just a header */
+ zds->outEnd = zds->outStart + decodedSize;
+ zds->stage = zdss_flush;
+ break;
+ }
+ if (ip == iend) {
+ someMoreWork = 0;
+ break;
+ } /* no more input */
+ zds->stage = zdss_load;
+ /* pass-through */
+ }
+
+ case zdss_load: {
+ size_t const neededInSize = ZSTD_nextSrcSizeToDecompress(zds->dctx);
+ size_t const toLoad = neededInSize - zds->inPos; /* should always be <= remaining space within inBuff */
+ size_t loadedSize;
+ if (toLoad > zds->inBuffSize - zds->inPos)
+ return ERROR(corruption_detected); /* should never happen */
+ loadedSize = ZSTD_limitCopy(zds->inBuff + zds->inPos, toLoad, ip, iend - ip);
+ ip += loadedSize;
+ zds->inPos += loadedSize;
+ if (loadedSize < toLoad) {
+ someMoreWork = 0;
+ break;
+ } /* not enough input, wait for more */
+
+ /* decode loaded input */
+ {
+ const int isSkipFrame = ZSTD_isSkipFrame(zds->dctx);
+ size_t const decodedSize = ZSTD_decompressContinue(zds->dctx, zds->outBuff + zds->outStart, zds->outBuffSize - zds->outStart,
+ zds->inBuff, neededInSize);
+ if (ZSTD_isError(decodedSize))
+ return decodedSize;
+ zds->inPos = 0; /* input is consumed */
+ if (!decodedSize && !isSkipFrame) {
+ zds->stage = zdss_read;
+ break;
+ } /* this was just a header */
+ zds->outEnd = zds->outStart + decodedSize;
+ zds->stage = zdss_flush;
+ /* pass-through */
+ }
+ }
+
+ case zdss_flush: {
+ size_t const toFlushSize = zds->outEnd - zds->outStart;
+ size_t const flushedSize = ZSTD_limitCopy(op, oend - op, zds->outBuff + zds->outStart, toFlushSize);
+ op += flushedSize;
+ zds->outStart += flushedSize;
+ if (flushedSize == toFlushSize) { /* flush completed */
+ zds->stage = zdss_read;
+ if (zds->outStart + zds->blockSize > zds->outBuffSize)
+ zds->outStart = zds->outEnd = 0;
+ break;
+ }
+ /* cannot complete flush */
+ someMoreWork = 0;
+ break;
+ }
+ default:
+ return ERROR(GENERIC); /* impossible */
+ }
+ }
+
+ /* result */
+ input->pos += (size_t)(ip - istart);
+ output->pos += (size_t)(op - ostart);
+ {
+ size_t nextSrcSizeHint = ZSTD_nextSrcSizeToDecompress(zds->dctx);
+ if (!nextSrcSizeHint) { /* frame fully decoded */
+ if (zds->outEnd == zds->outStart) { /* output fully flushed */
+ if (zds->hostageByte) {
+ if (input->pos >= input->size) {
+ zds->stage = zdss_read;
+ return 1;
+ } /* can't release hostage (not present) */
+ input->pos++; /* release hostage */
+ }
+ return 0;
+ }
+ if (!zds->hostageByte) { /* output not fully flushed; keep last byte as hostage; will be released when all output is flushed */
+ input->pos--; /* note : pos > 0, otherwise, impossible to finish reading last block */
+ zds->hostageByte = 1;
+ }
+ return 1;
+ }
+ nextSrcSizeHint += ZSTD_blockHeaderSize * (ZSTD_nextInputType(zds->dctx) == ZSTDnit_block); /* preload header of next block */
+ if (zds->inPos > nextSrcSizeHint)
+ return ERROR(GENERIC); /* should never happen */
+ nextSrcSizeHint -= zds->inPos; /* already loaded*/
+ return nextSrcSizeHint;
+ }
+}
+
+EXPORT_SYMBOL(ZSTD_DCtxWorkspaceBound);
+EXPORT_SYMBOL(ZSTD_initDCtx);
+EXPORT_SYMBOL(ZSTD_decompressDCtx);
+EXPORT_SYMBOL(ZSTD_decompress_usingDict);
+
+EXPORT_SYMBOL(ZSTD_DDictWorkspaceBound);
+EXPORT_SYMBOL(ZSTD_initDDict);
+EXPORT_SYMBOL(ZSTD_decompress_usingDDict);
+
+EXPORT_SYMBOL(ZSTD_DStreamWorkspaceBound);
+EXPORT_SYMBOL(ZSTD_initDStream);
+EXPORT_SYMBOL(ZSTD_initDStream_usingDDict);
+EXPORT_SYMBOL(ZSTD_resetDStream);
+EXPORT_SYMBOL(ZSTD_decompressStream);
+EXPORT_SYMBOL(ZSTD_DStreamInSize);
+EXPORT_SYMBOL(ZSTD_DStreamOutSize);
+
+EXPORT_SYMBOL(ZSTD_findFrameCompressedSize);
+EXPORT_SYMBOL(ZSTD_getFrameContentSize);
+EXPORT_SYMBOL(ZSTD_findDecompressedSize);
+
+EXPORT_SYMBOL(ZSTD_isFrame);
+EXPORT_SYMBOL(ZSTD_getDictID_fromDict);
+EXPORT_SYMBOL(ZSTD_getDictID_fromDDict);
+EXPORT_SYMBOL(ZSTD_getDictID_fromFrame);
+
+EXPORT_SYMBOL(ZSTD_getFrameParams);
+EXPORT_SYMBOL(ZSTD_decompressBegin);
+EXPORT_SYMBOL(ZSTD_decompressBegin_usingDict);
+EXPORT_SYMBOL(ZSTD_copyDCtx);
+EXPORT_SYMBOL(ZSTD_nextSrcSizeToDecompress);
+EXPORT_SYMBOL(ZSTD_decompressContinue);
+EXPORT_SYMBOL(ZSTD_nextInputType);
+
+EXPORT_SYMBOL(ZSTD_decompressBlock);
+EXPORT_SYMBOL(ZSTD_insertBlock);
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause)
+/*
+ * Common functions of New Generation Entropy library
+ * Copyright (C) 2016, Yann Collet.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ */
+
+/* *************************************
+* Dependencies
+***************************************/
+#include "error_private.h" /* ERR_*, ERROR */
+#include "fse.h"
+#include "huf.h"
+#include "mem.h"
+
+/*=== Version ===*/
+unsigned FSE_versionNumber(void) { return FSE_VERSION_NUMBER; }
+
+/*=== Error Management ===*/
+unsigned FSE_isError(size_t code) { return ERR_isError(code); }
+
+unsigned HUF_isError(size_t code) { return ERR_isError(code); }
+
+/*-**************************************************************
+* FSE NCount encoding-decoding
+****************************************************************/
+size_t FSE_readNCount(short *normalizedCounter, unsigned *maxSVPtr, unsigned *tableLogPtr, const void *headerBuffer, size_t hbSize)
+{
+ const BYTE *const istart = (const BYTE *)headerBuffer;
+ const BYTE *const iend = istart + hbSize;
+ const BYTE *ip = istart;
+ int nbBits;
+ int remaining;
+ int threshold;
+ U32 bitStream;
+ int bitCount;
+ unsigned charnum = 0;
+ int previous0 = 0;
+
+ if (hbSize < 4)
+ return ERROR(srcSize_wrong);
+ bitStream = ZSTD_readLE32(ip);
+ nbBits = (bitStream & 0xF) + FSE_MIN_TABLELOG; /* extract tableLog */
+ if (nbBits > FSE_TABLELOG_ABSOLUTE_MAX)
+ return ERROR(tableLog_tooLarge);
+ bitStream >>= 4;
+ bitCount = 4;
+ *tableLogPtr = nbBits;
+ remaining = (1 << nbBits) + 1;
+ threshold = 1 << nbBits;
+ nbBits++;
+
+ while ((remaining > 1) & (charnum <= *maxSVPtr)) {
+ if (previous0) {
+ unsigned n0 = charnum;
+ while ((bitStream & 0xFFFF) == 0xFFFF) {
+ n0 += 24;
+ if (ip < iend - 5) {
+ ip += 2;
+ bitStream = ZSTD_readLE32(ip) >> bitCount;
+ } else {
+ bitStream >>= 16;
+ bitCount += 16;
+ }
+ }
+ while ((bitStream & 3) == 3) {
+ n0 += 3;
+ bitStream >>= 2;
+ bitCount += 2;
+ }
+ n0 += bitStream & 3;
+ bitCount += 2;
+ if (n0 > *maxSVPtr)
+ return ERROR(maxSymbolValue_tooSmall);
+ while (charnum < n0)
+ normalizedCounter[charnum++] = 0;
+ if ((ip <= iend - 7) || (ip + (bitCount >> 3) <= iend - 4)) {
+ ip += bitCount >> 3;
+ bitCount &= 7;
+ bitStream = ZSTD_readLE32(ip) >> bitCount;
+ } else {
+ bitStream >>= 2;
+ }
+ }
+ {
+ int const max = (2 * threshold - 1) - remaining;
+ int count;
+
+ if ((bitStream & (threshold - 1)) < (U32)max) {
+ count = bitStream & (threshold - 1);
+ bitCount += nbBits - 1;
+ } else {
+ count = bitStream & (2 * threshold - 1);
+ if (count >= threshold)
+ count -= max;
+ bitCount += nbBits;
+ }
+
+ count--; /* extra accuracy */
+ remaining -= count < 0 ? -count : count; /* -1 means +1 */
+ normalizedCounter[charnum++] = (short)count;
+ previous0 = !count;
+ while (remaining < threshold) {
+ nbBits--;
+ threshold >>= 1;
+ }
+
+ if ((ip <= iend - 7) || (ip + (bitCount >> 3) <= iend - 4)) {
+ ip += bitCount >> 3;
+ bitCount &= 7;
+ } else {
+ bitCount -= (int)(8 * (iend - 4 - ip));
+ ip = iend - 4;
+ }
+ bitStream = ZSTD_readLE32(ip) >> (bitCount & 31);
+ }
+ } /* while ((remaining>1) & (charnum<=*maxSVPtr)) */
+ if (remaining != 1)
+ return ERROR(corruption_detected);
+ if (bitCount > 32)
+ return ERROR(corruption_detected);
+ *maxSVPtr = charnum - 1;
+
+ ip += (bitCount + 7) >> 3;
+ return ip - istart;
+}
+
+/*! HUF_readStats() :
+ Read compact Huffman tree, saved by HUF_writeCTable().
+ `huffWeight` is destination buffer.
+ `rankStats` is assumed to be a table of at least HUF_TABLELOG_MAX U32.
+ @return : size read from `src` , or an error Code .
+ Note : Needed by HUF_readCTable() and HUF_readDTableX?() .
+*/
+size_t HUF_readStats_wksp(BYTE *huffWeight, size_t hwSize, U32 *rankStats, U32 *nbSymbolsPtr, U32 *tableLogPtr, const void *src, size_t srcSize, void *workspace, size_t workspaceSize)
+{
+ U32 weightTotal;
+ const BYTE *ip = (const BYTE *)src;
+ size_t iSize;
+ size_t oSize;
+
+ if (!srcSize)
+ return ERROR(srcSize_wrong);
+ iSize = ip[0];
+ /* memset(huffWeight, 0, hwSize); */ /* is not necessary, even though some analyzer complain ... */
+
+ if (iSize >= 128) { /* special header */
+ oSize = iSize - 127;
+ iSize = ((oSize + 1) / 2);
+ if (iSize + 1 > srcSize)
+ return ERROR(srcSize_wrong);
+ if (oSize >= hwSize)
+ return ERROR(corruption_detected);
+ ip += 1;
+ {
+ U32 n;
+ for (n = 0; n < oSize; n += 2) {
+ huffWeight[n] = ip[n / 2] >> 4;
+ huffWeight[n + 1] = ip[n / 2] & 15;
+ }
+ }
+ } else { /* header compressed with FSE (normal case) */
+ if (iSize + 1 > srcSize)
+ return ERROR(srcSize_wrong);
+ oSize = FSE_decompress_wksp(huffWeight, hwSize - 1, ip + 1, iSize, 6, workspace, workspaceSize); /* max (hwSize-1) values decoded, as last one is implied */
+ if (FSE_isError(oSize))
+ return oSize;
+ }
+
+ /* collect weight stats */
+ memset(rankStats, 0, (HUF_TABLELOG_MAX + 1) * sizeof(U32));
+ weightTotal = 0;
+ {
+ U32 n;
+ for (n = 0; n < oSize; n++) {
+ if (huffWeight[n] >= HUF_TABLELOG_MAX)
+ return ERROR(corruption_detected);
+ rankStats[huffWeight[n]]++;
+ weightTotal += (1 << huffWeight[n]) >> 1;
+ }
+ }
+ if (weightTotal == 0)
+ return ERROR(corruption_detected);
+
+ /* get last non-null symbol weight (implied, total must be 2^n) */
+ {
+ U32 const tableLog = BIT_highbit32(weightTotal) + 1;
+ if (tableLog > HUF_TABLELOG_MAX)
+ return ERROR(corruption_detected);
+ *tableLogPtr = tableLog;
+ /* determine last weight */
+ {
+ U32 const total = 1 << tableLog;
+ U32 const rest = total - weightTotal;
+ U32 const verif = 1 << BIT_highbit32(rest);
+ U32 const lastWeight = BIT_highbit32(rest) + 1;
+ if (verif != rest)
+ return ERROR(corruption_detected); /* last value must be a clean power of 2 */
+ huffWeight[oSize] = (BYTE)lastWeight;
+ rankStats[lastWeight]++;
+ }
+ }
+
+ /* check tree construction validity */
+ if ((rankStats[1] < 2) || (rankStats[1] & 1))
+ return ERROR(corruption_detected); /* by construction : at least 2 elts of rank 1, must be even */
+
+ /* results */
+ *nbSymbolsPtr = (U32)(oSize + 1);
+ return iSize + 1;
+}
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */
+/**
+ * Copyright (c) 2016-present, Yann Collet, Facebook, Inc.
+ * All rights reserved.
+ */
+
+/* Note : this module is expected to remain private, do not expose it */
+
+#ifndef ERROR_H_MODULE
+#define ERROR_H_MODULE
+
+/* ****************************************
+* Dependencies
+******************************************/
+#include <linux/types.h> /* size_t */
+#include <linux/zstd.h> /* enum list */
+
+/* ****************************************
+* Compiler-specific
+******************************************/
+#define ERR_STATIC static __attribute__((unused))
+
+/*-****************************************
+* Customization (error_public.h)
+******************************************/
+typedef ZSTD_ErrorCode ERR_enum;
+#define PREFIX(name) ZSTD_error_##name
+
+/*-****************************************
+* Error codes handling
+******************************************/
+#define ERROR(name) ((size_t)-PREFIX(name))
+
+ERR_STATIC unsigned ERR_isError(size_t code) { return (code > ERROR(maxCode)); }
+
+ERR_STATIC ERR_enum ERR_getErrorCode(size_t code)
+{
+ if (!ERR_isError(code))
+ return (ERR_enum)0;
+ return (ERR_enum)(0 - code);
+}
+
+#endif /* ERROR_H_MODULE */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) */
+/*
+ * FSE : Finite State Entropy codec
+ * Public Prototypes declaration
+ * Copyright (C) 2013-2016, Yann Collet.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ */
+#ifndef FSE_H
+#define FSE_H
+
+/*-*****************************************
+* Dependencies
+******************************************/
+#include <linux/types.h> /* size_t, ptrdiff_t */
+
+/*-*****************************************
+* FSE_PUBLIC_API : control library symbols visibility
+******************************************/
+#define FSE_PUBLIC_API
+
+/*------ Version ------*/
+#define FSE_VERSION_MAJOR 0
+#define FSE_VERSION_MINOR 9
+#define FSE_VERSION_RELEASE 0
+
+#define FSE_LIB_VERSION FSE_VERSION_MAJOR.FSE_VERSION_MINOR.FSE_VERSION_RELEASE
+#define FSE_QUOTE(str) #str
+#define FSE_EXPAND_AND_QUOTE(str) FSE_QUOTE(str)
+#define FSE_VERSION_STRING FSE_EXPAND_AND_QUOTE(FSE_LIB_VERSION)
+
+#define FSE_VERSION_NUMBER (FSE_VERSION_MAJOR * 100 * 100 + FSE_VERSION_MINOR * 100 + FSE_VERSION_RELEASE)
+FSE_PUBLIC_API unsigned FSE_versionNumber(void); /**< library version number; to be used when checking dll version */
+
+/*-*****************************************
+* Tool functions
+******************************************/
+FSE_PUBLIC_API size_t FSE_compressBound(size_t size); /* maximum compressed size */
+
+/* Error Management */
+FSE_PUBLIC_API unsigned FSE_isError(size_t code); /* tells if a return value is an error code */
+
+/*-*****************************************
+* FSE detailed API
+******************************************/
+/*!
+FSE_compress() does the following:
+1. count symbol occurrence from source[] into table count[]
+2. normalize counters so that sum(count[]) == Power_of_2 (2^tableLog)
+3. save normalized counters to memory buffer using writeNCount()
+4. build encoding table 'CTable' from normalized counters
+5. encode the data stream using encoding table 'CTable'
+
+FSE_decompress() does the following:
+1. read normalized counters with readNCount()
+2. build decoding table 'DTable' from normalized counters
+3. decode the data stream using decoding table 'DTable'
+
+The following API allows targeting specific sub-functions for advanced tasks.
+For example, it's possible to compress several blocks using the same 'CTable',
+or to save and provide normalized distribution using external method.
+*/
+
+/* *** COMPRESSION *** */
+/*! FSE_optimalTableLog():
+ dynamically downsize 'tableLog' when conditions are met.
+ It saves CPU time, by using smaller tables, while preserving or even improving compression ratio.
+ @return : recommended tableLog (necessarily <= 'maxTableLog') */
+FSE_PUBLIC_API unsigned FSE_optimalTableLog(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue);
+
+/*! FSE_normalizeCount():
+ normalize counts so that sum(count[]) == Power_of_2 (2^tableLog)
+ 'normalizedCounter' is a table of short, of minimum size (maxSymbolValue+1).
+ @return : tableLog,
+ or an errorCode, which can be tested using FSE_isError() */
+FSE_PUBLIC_API size_t FSE_normalizeCount(short *normalizedCounter, unsigned tableLog, const unsigned *count, size_t srcSize, unsigned maxSymbolValue);
+
+/*! FSE_NCountWriteBound():
+ Provides the maximum possible size of an FSE normalized table, given 'maxSymbolValue' and 'tableLog'.
+ Typically useful for allocation purpose. */
+FSE_PUBLIC_API size_t FSE_NCountWriteBound(unsigned maxSymbolValue, unsigned tableLog);
+
+/*! FSE_writeNCount():
+ Compactly save 'normalizedCounter' into 'buffer'.
+ @return : size of the compressed table,
+ or an errorCode, which can be tested using FSE_isError(). */
+FSE_PUBLIC_API size_t FSE_writeNCount(void *buffer, size_t bufferSize, const short *normalizedCounter, unsigned maxSymbolValue, unsigned tableLog);
+
+/*! Constructor and Destructor of FSE_CTable.
+ Note that FSE_CTable size depends on 'tableLog' and 'maxSymbolValue' */
+typedef unsigned FSE_CTable; /* don't allocate that. It's only meant to be more restrictive than void* */
+
+/*! FSE_compress_usingCTable():
+ Compress `src` using `ct` into `dst` which must be already allocated.
+ @return : size of compressed data (<= `dstCapacity`),
+ or 0 if compressed data could not fit into `dst`,
+ or an errorCode, which can be tested using FSE_isError() */
+FSE_PUBLIC_API size_t FSE_compress_usingCTable(void *dst, size_t dstCapacity, const void *src, size_t srcSize, const FSE_CTable *ct);
+
+/*!
+Tutorial :
+----------
+The first step is to count all symbols. FSE_count() does this job very fast.
+Result will be saved into 'count', a table of unsigned int, which must be already allocated, and have 'maxSymbolValuePtr[0]+1' cells.
+'src' is a table of bytes of size 'srcSize'. All values within 'src' MUST be <= maxSymbolValuePtr[0]
+maxSymbolValuePtr[0] will be updated, with its real value (necessarily <= original value)
+FSE_count() will return the number of occurrence of the most frequent symbol.
+This can be used to know if there is a single symbol within 'src', and to quickly evaluate its compressibility.
+If there is an error, the function will return an ErrorCode (which can be tested using FSE_isError()).
+
+The next step is to normalize the frequencies.
+FSE_normalizeCount() will ensure that sum of frequencies is == 2 ^'tableLog'.
+It also guarantees a minimum of 1 to any Symbol with frequency >= 1.
+You can use 'tableLog'==0 to mean "use default tableLog value".
+If you are unsure of which tableLog value to use, you can ask FSE_optimalTableLog(),
+which will provide the optimal valid tableLog given sourceSize, maxSymbolValue, and a user-defined maximum (0 means "default").
+
+The result of FSE_normalizeCount() will be saved into a table,
+called 'normalizedCounter', which is a table of signed short.
+'normalizedCounter' must be already allocated, and have at least 'maxSymbolValue+1' cells.
+The return value is tableLog if everything proceeded as expected.
+It is 0 if there is a single symbol within distribution.
+If there is an error (ex: invalid tableLog value), the function will return an ErrorCode (which can be tested using FSE_isError()).
+
+'normalizedCounter' can be saved in a compact manner to a memory area using FSE_writeNCount().
+'buffer' must be already allocated.
+For guaranteed success, buffer size must be at least FSE_headerBound().
+The result of the function is the number of bytes written into 'buffer'.
+If there is an error, the function will return an ErrorCode (which can be tested using FSE_isError(); ex : buffer size too small).
+
+'normalizedCounter' can then be used to create the compression table 'CTable'.
+The space required by 'CTable' must be already allocated, using FSE_createCTable().
+You can then use FSE_buildCTable() to fill 'CTable'.
+If there is an error, both functions will return an ErrorCode (which can be tested using FSE_isError()).
+
+'CTable' can then be used to compress 'src', with FSE_compress_usingCTable().
+Similar to FSE_count(), the convention is that 'src' is assumed to be a table of char of size 'srcSize'
+The function returns the size of compressed data (without header), necessarily <= `dstCapacity`.
+If it returns '0', compressed data could not fit into 'dst'.
+If there is an error, the function will return an ErrorCode (which can be tested using FSE_isError()).
+*/
+
+/* *** DECOMPRESSION *** */
+
+/*! FSE_readNCount():
+ Read compactly saved 'normalizedCounter' from 'rBuffer'.
+ @return : size read from 'rBuffer',
+ or an errorCode, which can be tested using FSE_isError().
+ maxSymbolValuePtr[0] and tableLogPtr[0] will also be updated with their respective values */
+FSE_PUBLIC_API size_t FSE_readNCount(short *normalizedCounter, unsigned *maxSymbolValuePtr, unsigned *tableLogPtr, const void *rBuffer, size_t rBuffSize);
+
+/*! Constructor and Destructor of FSE_DTable.
+ Note that its size depends on 'tableLog' */
+typedef unsigned FSE_DTable; /* don't allocate that. It's just a way to be more restrictive than void* */
+
+/*! FSE_buildDTable():
+ Builds 'dt', which must be already allocated, using FSE_createDTable().
+ return : 0, or an errorCode, which can be tested using FSE_isError() */
+FSE_PUBLIC_API size_t FSE_buildDTable_wksp(FSE_DTable *dt, const short *normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void *workspace, size_t workspaceSize);
+
+/*! FSE_decompress_usingDTable():
+ Decompress compressed source `cSrc` of size `cSrcSize` using `dt`
+ into `dst` which must be already allocated.
+ @return : size of regenerated data (necessarily <= `dstCapacity`),
+ or an errorCode, which can be tested using FSE_isError() */
+FSE_PUBLIC_API size_t FSE_decompress_usingDTable(void *dst, size_t dstCapacity, const void *cSrc, size_t cSrcSize, const FSE_DTable *dt);
+
+/*!
+Tutorial :
+----------
+(Note : these functions only decompress FSE-compressed blocks.
+ If block is uncompressed, use memcpy() instead
+ If block is a single repeated byte, use memset() instead )
+
+The first step is to obtain the normalized frequencies of symbols.
+This can be performed by FSE_readNCount() if it was saved using FSE_writeNCount().
+'normalizedCounter' must be already allocated, and have at least 'maxSymbolValuePtr[0]+1' cells of signed short.
+In practice, that means it's necessary to know 'maxSymbolValue' beforehand,
+or size the table to handle worst case situations (typically 256).
+FSE_readNCount() will provide 'tableLog' and 'maxSymbolValue'.
+The result of FSE_readNCount() is the number of bytes read from 'rBuffer'.
+Note that 'rBufferSize' must be at least 4 bytes, even if useful information is less than that.
+If there is an error, the function will return an error code, which can be tested using FSE_isError().
+
+The next step is to build the decompression tables 'FSE_DTable' from 'normalizedCounter'.
+This is performed by the function FSE_buildDTable().
+The space required by 'FSE_DTable' must be already allocated using FSE_createDTable().
+If there is an error, the function will return an error code, which can be tested using FSE_isError().
+
+`FSE_DTable` can then be used to decompress `cSrc`, with FSE_decompress_usingDTable().
+`cSrcSize` must be strictly correct, otherwise decompression will fail.
+FSE_decompress_usingDTable() result will tell how many bytes were regenerated (<=`dstCapacity`).
+If there is an error, the function will return an error code, which can be tested using FSE_isError(). (ex: dst buffer too small)
+*/
+
+/* *** Dependency *** */
+#include "bitstream.h"
+
+/* *****************************************
+* Static allocation
+*******************************************/
+/* FSE buffer bounds */
+#define FSE_NCOUNTBOUND 512
+#define FSE_BLOCKBOUND(size) (size + (size >> 7))
+#define FSE_COMPRESSBOUND(size) (FSE_NCOUNTBOUND + FSE_BLOCKBOUND(size)) /* Macro version, useful for static allocation */
+
+/* It is possible to statically allocate FSE CTable/DTable as a table of FSE_CTable/FSE_DTable using below macros */
+#define FSE_CTABLE_SIZE_U32(maxTableLog, maxSymbolValue) (1 + (1 << (maxTableLog - 1)) + ((maxSymbolValue + 1) * 2))
+#define FSE_DTABLE_SIZE_U32(maxTableLog) (1 + (1 << maxTableLog))
+
+/* *****************************************
+* FSE advanced API
+*******************************************/
+/* FSE_count_wksp() :
+ * Same as FSE_count(), but using an externally provided scratch buffer.
+ * `workSpace` size must be table of >= `1024` unsigned
+ */
+size_t FSE_count_wksp(unsigned *count, unsigned *maxSymbolValuePtr, const void *source, size_t sourceSize, unsigned *workSpace);
+
+/* FSE_countFast_wksp() :
+ * Same as FSE_countFast(), but using an externally provided scratch buffer.
+ * `workSpace` must be a table of minimum `1024` unsigned
+ */
+size_t FSE_countFast_wksp(unsigned *count, unsigned *maxSymbolValuePtr, const void *src, size_t srcSize, unsigned *workSpace);
+
+/*! FSE_count_simple
+ * Same as FSE_countFast(), but does not use any additional memory (not even on stack).
+ * This function is unsafe, and will segfault if any value within `src` is `> *maxSymbolValuePtr` (presuming it's also the size of `count`).
+*/
+size_t FSE_count_simple(unsigned *count, unsigned *maxSymbolValuePtr, const void *src, size_t srcSize);
+
+unsigned FSE_optimalTableLog_internal(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue, unsigned minus);
+/**< same as FSE_optimalTableLog(), which used `minus==2` */
+
+size_t FSE_buildCTable_raw(FSE_CTable *ct, unsigned nbBits);
+/**< build a fake FSE_CTable, designed for a flat distribution, where each symbol uses nbBits */
+
+size_t FSE_buildCTable_rle(FSE_CTable *ct, unsigned char symbolValue);
+/**< build a fake FSE_CTable, designed to compress always the same symbolValue */
+
+/* FSE_buildCTable_wksp() :
+ * Same as FSE_buildCTable(), but using an externally allocated scratch buffer (`workSpace`).
+ * `wkspSize` must be >= `(1<<tableLog)`.
+ */
+size_t FSE_buildCTable_wksp(FSE_CTable *ct, const short *normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void *workSpace, size_t wkspSize);
+
+size_t FSE_buildDTable_raw(FSE_DTable *dt, unsigned nbBits);
+/**< build a fake FSE_DTable, designed to read a flat distribution where each symbol uses nbBits */
+
+size_t FSE_buildDTable_rle(FSE_DTable *dt, unsigned char symbolValue);
+/**< build a fake FSE_DTable, designed to always generate the same symbolValue */
+
+size_t FSE_decompress_wksp(void *dst, size_t dstCapacity, const void *cSrc, size_t cSrcSize, unsigned maxLog, void *workspace, size_t workspaceSize);
+/**< same as FSE_decompress(), using an externally allocated `workSpace` produced with `FSE_DTABLE_SIZE_U32(maxLog)` */
+
+/* *****************************************
+* FSE symbol compression API
+*******************************************/
+/*!
+ This API consists of small unitary functions, which highly benefit from being inlined.
+ Hence their body are included in next section.
+*/
+typedef struct {
+ ptrdiff_t value;
+ const void *stateTable;
+ const void *symbolTT;
+ unsigned stateLog;
+} FSE_CState_t;
+
+static void FSE_initCState(FSE_CState_t *CStatePtr, const FSE_CTable *ct);
+
+static void FSE_encodeSymbol(BIT_CStream_t *bitC, FSE_CState_t *CStatePtr, unsigned symbol);
+
+static void FSE_flushCState(BIT_CStream_t *bitC, const FSE_CState_t *CStatePtr);
+
+/**<
+These functions are inner components of FSE_compress_usingCTable().
+They allow the creation of custom streams, mixing multiple tables and bit sources.
+
+A key property to keep in mind is that encoding and decoding are done **in reverse direction**.
+So the first symbol you will encode is the last you will decode, like a LIFO stack.
+
+You will need a few variables to track your CStream. They are :
+
+FSE_CTable ct; // Provided by FSE_buildCTable()
+BIT_CStream_t bitStream; // bitStream tracking structure
+FSE_CState_t state; // State tracking structure (can have several)
+
+
+The first thing to do is to init bitStream and state.
+ size_t errorCode = BIT_initCStream(&bitStream, dstBuffer, maxDstSize);
+ FSE_initCState(&state, ct);
+
+Note that BIT_initCStream() can produce an error code, so its result should be tested, using FSE_isError();
+You can then encode your input data, byte after byte.
+FSE_encodeSymbol() outputs a maximum of 'tableLog' bits at a time.
+Remember decoding will be done in reverse direction.
+ FSE_encodeByte(&bitStream, &state, symbol);
+
+At any time, you can also add any bit sequence.
+Note : maximum allowed nbBits is 25, for compatibility with 32-bits decoders
+ BIT_addBits(&bitStream, bitField, nbBits);
+
+The above methods don't commit data to memory, they just store it into local register, for speed.
+Local register size is 64-bits on 64-bits systems, 32-bits on 32-bits systems (size_t).
+Writing data to memory is a manual operation, performed by the flushBits function.
+ BIT_flushBits(&bitStream);
+
+Your last FSE encoding operation shall be to flush your last state value(s).
+ FSE_flushState(&bitStream, &state);
+
+Finally, you must close the bitStream.
+The function returns the size of CStream in bytes.
+If data couldn't fit into dstBuffer, it will return a 0 ( == not compressible)
+If there is an error, it returns an errorCode (which can be tested using FSE_isError()).
+ size_t size = BIT_closeCStream(&bitStream);
+*/
+
+/* *****************************************
+* FSE symbol decompression API
+*******************************************/
+typedef struct {
+ size_t state;
+ const void *table; /* precise table may vary, depending on U16 */
+} FSE_DState_t;
+
+static void FSE_initDState(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD, const FSE_DTable *dt);
+
+static unsigned char FSE_decodeSymbol(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD);
+
+static unsigned FSE_endOfDState(const FSE_DState_t *DStatePtr);
+
+/**<
+Let's now decompose FSE_decompress_usingDTable() into its unitary components.
+You will decode FSE-encoded symbols from the bitStream,
+and also any other bitFields you put in, **in reverse order**.
+
+You will need a few variables to track your bitStream. They are :
+
+BIT_DStream_t DStream; // Stream context
+FSE_DState_t DState; // State context. Multiple ones are possible
+FSE_DTable* DTablePtr; // Decoding table, provided by FSE_buildDTable()
+
+The first thing to do is to init the bitStream.
+ errorCode = BIT_initDStream(&DStream, srcBuffer, srcSize);
+
+You should then retrieve your initial state(s)
+(in reverse flushing order if you have several ones) :
+ errorCode = FSE_initDState(&DState, &DStream, DTablePtr);
+
+You can then decode your data, symbol after symbol.
+For information the maximum number of bits read by FSE_decodeSymbol() is 'tableLog'.
+Keep in mind that symbols are decoded in reverse order, like a LIFO stack (last in, first out).
+ unsigned char symbol = FSE_decodeSymbol(&DState, &DStream);
+
+You can retrieve any bitfield you eventually stored into the bitStream (in reverse order)
+Note : maximum allowed nbBits is 25, for 32-bits compatibility
+ size_t bitField = BIT_readBits(&DStream, nbBits);
+
+All above operations only read from local register (which size depends on size_t).
+Refueling the register from memory is manually performed by the reload method.
+ endSignal = FSE_reloadDStream(&DStream);
+
+BIT_reloadDStream() result tells if there is still some more data to read from DStream.
+BIT_DStream_unfinished : there is still some data left into the DStream.
+BIT_DStream_endOfBuffer : Dstream reached end of buffer. Its container may no longer be completely filled.
+BIT_DStream_completed : Dstream reached its exact end, corresponding in general to decompression completed.
+BIT_DStream_tooFar : Dstream went too far. Decompression result is corrupted.
+
+When reaching end of buffer (BIT_DStream_endOfBuffer), progress slowly, notably if you decode multiple symbols per loop,
+to properly detect the exact end of stream.
+After each decoded symbol, check if DStream is fully consumed using this simple test :
+ BIT_reloadDStream(&DStream) >= BIT_DStream_completed
+
+When it's done, verify decompression is fully completed, by checking both DStream and the relevant states.
+Checking if DStream has reached its end is performed by :
+ BIT_endOfDStream(&DStream);
+Check also the states. There might be some symbols left there, if some high probability ones (>50%) are possible.
+ FSE_endOfDState(&DState);
+*/
+
+/* *****************************************
+* FSE unsafe API
+*******************************************/
+static unsigned char FSE_decodeSymbolFast(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD);
+/* faster, but works only if nbBits is always >= 1 (otherwise, result will be corrupted) */
+
+/* *****************************************
+* Implementation of inlined functions
+*******************************************/
+typedef struct {
+ int deltaFindState;
+ U32 deltaNbBits;
+} FSE_symbolCompressionTransform; /* total 8 bytes */
+
+ZSTD_STATIC void FSE_initCState(FSE_CState_t *statePtr, const FSE_CTable *ct)
+{
+ const void *ptr = ct;
+ const U16 *u16ptr = (const U16 *)ptr;
+ const U32 tableLog = ZSTD_read16(ptr);
+ statePtr->value = (ptrdiff_t)1 << tableLog;
+ statePtr->stateTable = u16ptr + 2;
+ statePtr->symbolTT = ((const U32 *)ct + 1 + (tableLog ? (1 << (tableLog - 1)) : 1));
+ statePtr->stateLog = tableLog;
+}
+
+/*! FSE_initCState2() :
+* Same as FSE_initCState(), but the first symbol to include (which will be the last to be read)
+* uses the smallest state value possible, saving the cost of this symbol */
+ZSTD_STATIC void FSE_initCState2(FSE_CState_t *statePtr, const FSE_CTable *ct, U32 symbol)
+{
+ FSE_initCState(statePtr, ct);
+ {
+ const FSE_symbolCompressionTransform symbolTT = ((const FSE_symbolCompressionTransform *)(statePtr->symbolTT))[symbol];
+ const U16 *stateTable = (const U16 *)(statePtr->stateTable);
+ U32 nbBitsOut = (U32)((symbolTT.deltaNbBits + (1 << 15)) >> 16);
+ statePtr->value = (nbBitsOut << 16) - symbolTT.deltaNbBits;
+ statePtr->value = stateTable[(statePtr->value >> nbBitsOut) + symbolTT.deltaFindState];
+ }
+}
+
+ZSTD_STATIC void FSE_encodeSymbol(BIT_CStream_t *bitC, FSE_CState_t *statePtr, U32 symbol)
+{
+ const FSE_symbolCompressionTransform symbolTT = ((const FSE_symbolCompressionTransform *)(statePtr->symbolTT))[symbol];
+ const U16 *const stateTable = (const U16 *)(statePtr->stateTable);
+ U32 nbBitsOut = (U32)((statePtr->value + symbolTT.deltaNbBits) >> 16);
+ BIT_addBits(bitC, statePtr->value, nbBitsOut);
+ statePtr->value = stateTable[(statePtr->value >> nbBitsOut) + symbolTT.deltaFindState];
+}
+
+ZSTD_STATIC void FSE_flushCState(BIT_CStream_t *bitC, const FSE_CState_t *statePtr)
+{
+ BIT_addBits(bitC, statePtr->value, statePtr->stateLog);
+ BIT_flushBits(bitC);
+}
+
+/* ====== Decompression ====== */
+
+typedef struct {
+ U16 tableLog;
+ U16 fastMode;
+} FSE_DTableHeader; /* sizeof U32 */
+
+typedef struct {
+ unsigned short newState;
+ unsigned char symbol;
+ unsigned char nbBits;
+} FSE_decode_t; /* size == U32 */
+
+ZSTD_STATIC void FSE_initDState(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD, const FSE_DTable *dt)
+{
+ const void *ptr = dt;
+ const FSE_DTableHeader *const DTableH = (const FSE_DTableHeader *)ptr;
+ DStatePtr->state = BIT_readBits(bitD, DTableH->tableLog);
+ BIT_reloadDStream(bitD);
+ DStatePtr->table = dt + 1;
+}
+
+ZSTD_STATIC BYTE FSE_peekSymbol(const FSE_DState_t *DStatePtr)
+{
+ FSE_decode_t const DInfo = ((const FSE_decode_t *)(DStatePtr->table))[DStatePtr->state];
+ return DInfo.symbol;
+}
+
+ZSTD_STATIC void FSE_updateState(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD)
+{
+ FSE_decode_t const DInfo = ((const FSE_decode_t *)(DStatePtr->table))[DStatePtr->state];
+ U32 const nbBits = DInfo.nbBits;
+ size_t const lowBits = BIT_readBits(bitD, nbBits);
+ DStatePtr->state = DInfo.newState + lowBits;
+}
+
+ZSTD_STATIC BYTE FSE_decodeSymbol(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD)
+{
+ FSE_decode_t const DInfo = ((const FSE_decode_t *)(DStatePtr->table))[DStatePtr->state];
+ U32 const nbBits = DInfo.nbBits;
+ BYTE const symbol = DInfo.symbol;
+ size_t const lowBits = BIT_readBits(bitD, nbBits);
+
+ DStatePtr->state = DInfo.newState + lowBits;
+ return symbol;
+}
+
+/*! FSE_decodeSymbolFast() :
+ unsafe, only works if no symbol has a probability > 50% */
+ZSTD_STATIC BYTE FSE_decodeSymbolFast(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD)
+{
+ FSE_decode_t const DInfo = ((const FSE_decode_t *)(DStatePtr->table))[DStatePtr->state];
+ U32 const nbBits = DInfo.nbBits;
+ BYTE const symbol = DInfo.symbol;
+ size_t const lowBits = BIT_readBitsFast(bitD, nbBits);
+
+ DStatePtr->state = DInfo.newState + lowBits;
+ return symbol;
+}
+
+ZSTD_STATIC unsigned FSE_endOfDState(const FSE_DState_t *DStatePtr) { return DStatePtr->state == 0; }
+
+/* **************************************************************
+* Tuning parameters
+****************************************************************/
+/*!MEMORY_USAGE :
+* Memory usage formula : N->2^N Bytes (examples : 10 -> 1KB; 12 -> 4KB ; 16 -> 64KB; 20 -> 1MB; etc.)
+* Increasing memory usage improves compression ratio
+* Reduced memory usage can improve speed, due to cache effect
+* Recommended max value is 14, for 16KB, which nicely fits into Intel x86 L1 cache */
+#ifndef FSE_MAX_MEMORY_USAGE
+#define FSE_MAX_MEMORY_USAGE 14
+#endif
+#ifndef FSE_DEFAULT_MEMORY_USAGE
+#define FSE_DEFAULT_MEMORY_USAGE 13
+#endif
+
+/*!FSE_MAX_SYMBOL_VALUE :
+* Maximum symbol value authorized.
+* Required for proper stack allocation */
+#ifndef FSE_MAX_SYMBOL_VALUE
+#define FSE_MAX_SYMBOL_VALUE 255
+#endif
+
+/* **************************************************************
+* template functions type & suffix
+****************************************************************/
+#define FSE_FUNCTION_TYPE BYTE
+#define FSE_FUNCTION_EXTENSION
+#define FSE_DECODE_TYPE FSE_decode_t
+
+/* ***************************************************************
+* Constants
+*****************************************************************/
+#define FSE_MAX_TABLELOG (FSE_MAX_MEMORY_USAGE - 2)
+#define FSE_MAX_TABLESIZE (1U << FSE_MAX_TABLELOG)
+#define FSE_MAXTABLESIZE_MASK (FSE_MAX_TABLESIZE - 1)
+#define FSE_DEFAULT_TABLELOG (FSE_DEFAULT_MEMORY_USAGE - 2)
+#define FSE_MIN_TABLELOG 5
+
+#define FSE_TABLELOG_ABSOLUTE_MAX 15
+#if FSE_MAX_TABLELOG > FSE_TABLELOG_ABSOLUTE_MAX
+#error "FSE_MAX_TABLELOG > FSE_TABLELOG_ABSOLUTE_MAX is not supported"
+#endif
+
+#define FSE_TABLESTEP(tableSize) ((tableSize >> 1) + (tableSize >> 3) + 3)
+
+#endif /* FSE_H */
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause)
+/*
+ * FSE : Finite State Entropy decoder
+ * Copyright (C) 2013-2015, Yann Collet.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ */
+
+/* **************************************************************
+* Compiler specifics
+****************************************************************/
+#define FORCE_INLINE static __always_inline
+
+/* **************************************************************
+* Includes
+****************************************************************/
+#include "bitstream.h"
+#include "fse.h"
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/string.h> /* memcpy, memset */
+
+/* **************************************************************
+* Error Management
+****************************************************************/
+#define FSE_isError ERR_isError
+#define FSE_STATIC_ASSERT(c) \
+ { \
+ enum { FSE_static_assert = 1 / (int)(!!(c)) }; \
+ } /* use only *after* variable declarations */
+
+/* check and forward error code */
+#define CHECK_F(f) \
+ { \
+ size_t const e = f; \
+ if (FSE_isError(e)) \
+ return e; \
+ }
+
+/* **************************************************************
+* Templates
+****************************************************************/
+/*
+ designed to be included
+ for type-specific functions (template emulation in C)
+ Objective is to write these functions only once, for improved maintenance
+*/
+
+/* safety checks */
+#ifndef FSE_FUNCTION_EXTENSION
+#error "FSE_FUNCTION_EXTENSION must be defined"
+#endif
+#ifndef FSE_FUNCTION_TYPE
+#error "FSE_FUNCTION_TYPE must be defined"
+#endif
+
+/* Function names */
+#define FSE_CAT(X, Y) X##Y
+#define FSE_FUNCTION_NAME(X, Y) FSE_CAT(X, Y)
+#define FSE_TYPE_NAME(X, Y) FSE_CAT(X, Y)
+
+/* Function templates */
+
+size_t FSE_buildDTable_wksp(FSE_DTable *dt, const short *normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void *workspace, size_t workspaceSize)
+{
+ void *const tdPtr = dt + 1; /* because *dt is unsigned, 32-bits aligned on 32-bits */
+ FSE_DECODE_TYPE *const tableDecode = (FSE_DECODE_TYPE *)(tdPtr);
+ U16 *symbolNext = (U16 *)workspace;
+
+ U32 const maxSV1 = maxSymbolValue + 1;
+ U32 const tableSize = 1 << tableLog;
+ U32 highThreshold = tableSize - 1;
+
+ /* Sanity Checks */
+ if (workspaceSize < sizeof(U16) * (FSE_MAX_SYMBOL_VALUE + 1))
+ return ERROR(tableLog_tooLarge);
+ if (maxSymbolValue > FSE_MAX_SYMBOL_VALUE)
+ return ERROR(maxSymbolValue_tooLarge);
+ if (tableLog > FSE_MAX_TABLELOG)
+ return ERROR(tableLog_tooLarge);
+
+ /* Init, lay down lowprob symbols */
+ {
+ FSE_DTableHeader DTableH;
+ DTableH.tableLog = (U16)tableLog;
+ DTableH.fastMode = 1;
+ {
+ S16 const largeLimit = (S16)(1 << (tableLog - 1));
+ U32 s;
+ for (s = 0; s < maxSV1; s++) {
+ if (normalizedCounter[s] == -1) {
+ tableDecode[highThreshold--].symbol = (FSE_FUNCTION_TYPE)s;
+ symbolNext[s] = 1;
+ } else {
+ if (normalizedCounter[s] >= largeLimit)
+ DTableH.fastMode = 0;
+ symbolNext[s] = normalizedCounter[s];
+ }
+ }
+ }
+ memcpy(dt, &DTableH, sizeof(DTableH));
+ }
+
+ /* Spread symbols */
+ {
+ U32 const tableMask = tableSize - 1;
+ U32 const step = FSE_TABLESTEP(tableSize);
+ U32 s, position = 0;
+ for (s = 0; s < maxSV1; s++) {
+ int i;
+ for (i = 0; i < normalizedCounter[s]; i++) {
+ tableDecode[position].symbol = (FSE_FUNCTION_TYPE)s;
+ position = (position + step) & tableMask;
+ while (position > highThreshold)
+ position = (position + step) & tableMask; /* lowprob area */
+ }
+ }
+ if (position != 0)
+ return ERROR(GENERIC); /* position must reach all cells once, otherwise normalizedCounter is incorrect */
+ }
+
+ /* Build Decoding table */
+ {
+ U32 u;
+ for (u = 0; u < tableSize; u++) {
+ FSE_FUNCTION_TYPE const symbol = (FSE_FUNCTION_TYPE)(tableDecode[u].symbol);
+ U16 nextState = symbolNext[symbol]++;
+ tableDecode[u].nbBits = (BYTE)(tableLog - BIT_highbit32((U32)nextState));
+ tableDecode[u].newState = (U16)((nextState << tableDecode[u].nbBits) - tableSize);
+ }
+ }
+
+ return 0;
+}
+
+/*-*******************************************************
+* Decompression (Byte symbols)
+*********************************************************/
+size_t FSE_buildDTable_rle(FSE_DTable *dt, BYTE symbolValue)
+{
+ void *ptr = dt;
+ FSE_DTableHeader *const DTableH = (FSE_DTableHeader *)ptr;
+ void *dPtr = dt + 1;
+ FSE_decode_t *const cell = (FSE_decode_t *)dPtr;
+
+ DTableH->tableLog = 0;
+ DTableH->fastMode = 0;
+
+ cell->newState = 0;
+ cell->symbol = symbolValue;
+ cell->nbBits = 0;
+
+ return 0;
+}
+
+size_t FSE_buildDTable_raw(FSE_DTable *dt, unsigned nbBits)
+{
+ void *ptr = dt;
+ FSE_DTableHeader *const DTableH = (FSE_DTableHeader *)ptr;
+ void *dPtr = dt + 1;
+ FSE_decode_t *const dinfo = (FSE_decode_t *)dPtr;
+ const unsigned tableSize = 1 << nbBits;
+ const unsigned tableMask = tableSize - 1;
+ const unsigned maxSV1 = tableMask + 1;
+ unsigned s;
+
+ /* Sanity checks */
+ if (nbBits < 1)
+ return ERROR(GENERIC); /* min size */
+
+ /* Build Decoding Table */
+ DTableH->tableLog = (U16)nbBits;
+ DTableH->fastMode = 1;
+ for (s = 0; s < maxSV1; s++) {
+ dinfo[s].newState = 0;
+ dinfo[s].symbol = (BYTE)s;
+ dinfo[s].nbBits = (BYTE)nbBits;
+ }
+
+ return 0;
+}
+
+FORCE_INLINE size_t FSE_decompress_usingDTable_generic(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const FSE_DTable *dt,
+ const unsigned fast)
+{
+ BYTE *const ostart = (BYTE *)dst;
+ BYTE *op = ostart;
+ BYTE *const omax = op + maxDstSize;
+ BYTE *const olimit = omax - 3;
+
+ BIT_DStream_t bitD;
+ FSE_DState_t state1;
+ FSE_DState_t state2;
+
+ /* Init */
+ CHECK_F(BIT_initDStream(&bitD, cSrc, cSrcSize));
+
+ FSE_initDState(&state1, &bitD, dt);
+ FSE_initDState(&state2, &bitD, dt);
+
+#define FSE_GETSYMBOL(statePtr) fast ? FSE_decodeSymbolFast(statePtr, &bitD) : FSE_decodeSymbol(statePtr, &bitD)
+
+ /* 4 symbols per loop */
+ for (; (BIT_reloadDStream(&bitD) == BIT_DStream_unfinished) & (op < olimit); op += 4) {
+ op[0] = FSE_GETSYMBOL(&state1);
+
+ if (FSE_MAX_TABLELOG * 2 + 7 > sizeof(bitD.bitContainer) * 8) /* This test must be static */
+ BIT_reloadDStream(&bitD);
+
+ op[1] = FSE_GETSYMBOL(&state2);
+
+ if (FSE_MAX_TABLELOG * 4 + 7 > sizeof(bitD.bitContainer) * 8) /* This test must be static */
+ {
+ if (BIT_reloadDStream(&bitD) > BIT_DStream_unfinished) {
+ op += 2;
+ break;
+ }
+ }
+
+ op[2] = FSE_GETSYMBOL(&state1);
+
+ if (FSE_MAX_TABLELOG * 2 + 7 > sizeof(bitD.bitContainer) * 8) /* This test must be static */
+ BIT_reloadDStream(&bitD);
+
+ op[3] = FSE_GETSYMBOL(&state2);
+ }
+
+ /* tail */
+ /* note : BIT_reloadDStream(&bitD) >= FSE_DStream_partiallyFilled; Ends at exactly BIT_DStream_completed */
+ while (1) {
+ if (op > (omax - 2))
+ return ERROR(dstSize_tooSmall);
+ *op++ = FSE_GETSYMBOL(&state1);
+ if (BIT_reloadDStream(&bitD) == BIT_DStream_overflow) {
+ *op++ = FSE_GETSYMBOL(&state2);
+ break;
+ }
+
+ if (op > (omax - 2))
+ return ERROR(dstSize_tooSmall);
+ *op++ = FSE_GETSYMBOL(&state2);
+ if (BIT_reloadDStream(&bitD) == BIT_DStream_overflow) {
+ *op++ = FSE_GETSYMBOL(&state1);
+ break;
+ }
+ }
+
+ return op - ostart;
+}
+
+size_t FSE_decompress_usingDTable(void *dst, size_t originalSize, const void *cSrc, size_t cSrcSize, const FSE_DTable *dt)
+{
+ const void *ptr = dt;
+ const FSE_DTableHeader *DTableH = (const FSE_DTableHeader *)ptr;
+ const U32 fastMode = DTableH->fastMode;
+
+ /* select fast mode (static) */
+ if (fastMode)
+ return FSE_decompress_usingDTable_generic(dst, originalSize, cSrc, cSrcSize, dt, 1);
+ return FSE_decompress_usingDTable_generic(dst, originalSize, cSrc, cSrcSize, dt, 0);
+}
+
+size_t FSE_decompress_wksp(void *dst, size_t dstCapacity, const void *cSrc, size_t cSrcSize, unsigned maxLog, void *workspace, size_t workspaceSize)
+{
+ const BYTE *const istart = (const BYTE *)cSrc;
+ const BYTE *ip = istart;
+ unsigned tableLog;
+ unsigned maxSymbolValue = FSE_MAX_SYMBOL_VALUE;
+ size_t NCountLength;
+
+ FSE_DTable *dt;
+ short *counting;
+ size_t spaceUsed32 = 0;
+
+ FSE_STATIC_ASSERT(sizeof(FSE_DTable) == sizeof(U32));
+
+ dt = (FSE_DTable *)((U32 *)workspace + spaceUsed32);
+ spaceUsed32 += FSE_DTABLE_SIZE_U32(maxLog);
+ counting = (short *)((U32 *)workspace + spaceUsed32);
+ spaceUsed32 += ALIGN(sizeof(short) * (FSE_MAX_SYMBOL_VALUE + 1), sizeof(U32)) >> 2;
+
+ if ((spaceUsed32 << 2) > workspaceSize)
+ return ERROR(tableLog_tooLarge);
+ workspace = (U32 *)workspace + spaceUsed32;
+ workspaceSize -= (spaceUsed32 << 2);
+
+ /* normal FSE decoding mode */
+ NCountLength = FSE_readNCount(counting, &maxSymbolValue, &tableLog, istart, cSrcSize);
+ if (FSE_isError(NCountLength))
+ return NCountLength;
+ // if (NCountLength >= cSrcSize) return ERROR(srcSize_wrong); /* too small input size; supposed to be already checked in NCountLength, only remaining
+ // case : NCountLength==cSrcSize */
+ if (tableLog > maxLog)
+ return ERROR(tableLog_tooLarge);
+ ip += NCountLength;
+ cSrcSize -= NCountLength;
+
+ CHECK_F(FSE_buildDTable_wksp(dt, counting, maxSymbolValue, tableLog, workspace, workspaceSize));
+
+ return FSE_decompress_usingDTable(dst, dstCapacity, ip, cSrcSize, dt); /* always return, even if it is an error code */
+}
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) */
+/*
+ * Huffman coder, part of New Generation Entropy library
+ * header file
+ * Copyright (C) 2013-2016, Yann Collet.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ */
+#ifndef HUF_H_298734234
+#define HUF_H_298734234
+
+/* *** Dependencies *** */
+#include <linux/types.h> /* size_t */
+
+/* *** Tool functions *** */
+#define HUF_BLOCKSIZE_MAX (128 * 1024) /**< maximum input size for a single block compressed with HUF_compress */
+size_t HUF_compressBound(size_t size); /**< maximum compressed size (worst case) */
+
+/* Error Management */
+unsigned HUF_isError(size_t code); /**< tells if a return value is an error code */
+
+/* *** Advanced function *** */
+
+/** HUF_compress4X_wksp() :
+* Same as HUF_compress2(), but uses externally allocated `workSpace`, which must be a table of >= 1024 unsigned */
+size_t HUF_compress4X_wksp(void *dst, size_t dstSize, const void *src, size_t srcSize, unsigned maxSymbolValue, unsigned tableLog, void *workSpace,
+ size_t wkspSize); /**< `workSpace` must be a table of at least HUF_COMPRESS_WORKSPACE_SIZE_U32 unsigned */
+
+/* *** Dependencies *** */
+#include "mem.h" /* U32 */
+
+/* *** Constants *** */
+#define HUF_TABLELOG_MAX 12 /* max configured tableLog (for static allocation); can be modified up to HUF_ABSOLUTEMAX_TABLELOG */
+#define HUF_TABLELOG_DEFAULT 11 /* tableLog by default, when not specified */
+#define HUF_SYMBOLVALUE_MAX 255
+
+#define HUF_TABLELOG_ABSOLUTEMAX 15 /* absolute limit of HUF_MAX_TABLELOG. Beyond that value, code does not work */
+#if (HUF_TABLELOG_MAX > HUF_TABLELOG_ABSOLUTEMAX)
+#error "HUF_TABLELOG_MAX is too large !"
+#endif
+
+/* ****************************************
+* Static allocation
+******************************************/
+/* HUF buffer bounds */
+#define HUF_CTABLEBOUND 129
+#define HUF_BLOCKBOUND(size) (size + (size >> 8) + 8) /* only true if incompressible pre-filtered with fast heuristic */
+#define HUF_COMPRESSBOUND(size) (HUF_CTABLEBOUND + HUF_BLOCKBOUND(size)) /* Macro version, useful for static allocation */
+
+/* static allocation of HUF's Compression Table */
+#define HUF_CREATE_STATIC_CTABLE(name, maxSymbolValue) \
+ U32 name##hb[maxSymbolValue + 1]; \
+ void *name##hv = &(name##hb); \
+ HUF_CElt *name = (HUF_CElt *)(name##hv) /* no final ; */
+
+/* static allocation of HUF's DTable */
+typedef U32 HUF_DTable;
+#define HUF_DTABLE_SIZE(maxTableLog) (1 + (1 << (maxTableLog)))
+#define HUF_CREATE_STATIC_DTABLEX2(DTable, maxTableLog) HUF_DTable DTable[HUF_DTABLE_SIZE((maxTableLog)-1)] = {((U32)((maxTableLog)-1) * 0x01000001)}
+#define HUF_CREATE_STATIC_DTABLEX4(DTable, maxTableLog) HUF_DTable DTable[HUF_DTABLE_SIZE(maxTableLog)] = {((U32)(maxTableLog)*0x01000001)}
+
+/* The workspace must have alignment at least 4 and be at least this large */
+#define HUF_COMPRESS_WORKSPACE_SIZE (6 << 10)
+#define HUF_COMPRESS_WORKSPACE_SIZE_U32 (HUF_COMPRESS_WORKSPACE_SIZE / sizeof(U32))
+
+/* The workspace must have alignment at least 4 and be at least this large */
+#define HUF_DECOMPRESS_WORKSPACE_SIZE (3 << 10)
+#define HUF_DECOMPRESS_WORKSPACE_SIZE_U32 (HUF_DECOMPRESS_WORKSPACE_SIZE / sizeof(U32))
+
+/* ****************************************
+* Advanced decompression functions
+******************************************/
+size_t HUF_decompress4X_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize); /**< decodes RLE and uncompressed */
+size_t HUF_decompress4X_hufOnly_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace,
+ size_t workspaceSize); /**< considers RLE and uncompressed as errors */
+size_t HUF_decompress4X2_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace,
+ size_t workspaceSize); /**< single-symbol decoder */
+size_t HUF_decompress4X4_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace,
+ size_t workspaceSize); /**< double-symbols decoder */
+
+/* ****************************************
+* HUF detailed API
+******************************************/
+/*!
+HUF_compress() does the following:
+1. count symbol occurrence from source[] into table count[] using FSE_count()
+2. (optional) refine tableLog using HUF_optimalTableLog()
+3. build Huffman table from count using HUF_buildCTable()
+4. save Huffman table to memory buffer using HUF_writeCTable_wksp()
+5. encode the data stream using HUF_compress4X_usingCTable()
+
+The following API allows targeting specific sub-functions for advanced tasks.
+For example, it's possible to compress several blocks using the same 'CTable',
+or to save and regenerate 'CTable' using external methods.
+*/
+/* FSE_count() : find it within "fse.h" */
+unsigned HUF_optimalTableLog(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue);
+typedef struct HUF_CElt_s HUF_CElt; /* incomplete type */
+size_t HUF_writeCTable_wksp(void *dst, size_t maxDstSize, const HUF_CElt *CTable, unsigned maxSymbolValue, unsigned huffLog, void *workspace, size_t workspaceSize);
+size_t HUF_compress4X_usingCTable(void *dst, size_t dstSize, const void *src, size_t srcSize, const HUF_CElt *CTable);
+
+typedef enum {
+ HUF_repeat_none, /**< Cannot use the previous table */
+ HUF_repeat_check, /**< Can use the previous table but it must be checked. Note : The previous table must have been constructed by HUF_compress{1,
+ 4}X_repeat */
+ HUF_repeat_valid /**< Can use the previous table and it is asumed to be valid */
+} HUF_repeat;
+/** HUF_compress4X_repeat() :
+* Same as HUF_compress4X_wksp(), but considers using hufTable if *repeat != HUF_repeat_none.
+* If it uses hufTable it does not modify hufTable or repeat.
+* If it doesn't, it sets *repeat = HUF_repeat_none, and it sets hufTable to the table used.
+* If preferRepeat then the old table will always be used if valid. */
+size_t HUF_compress4X_repeat(void *dst, size_t dstSize, const void *src, size_t srcSize, unsigned maxSymbolValue, unsigned tableLog, void *workSpace,
+ size_t wkspSize, HUF_CElt *hufTable, HUF_repeat *repeat,
+ int preferRepeat); /**< `workSpace` must be a table of at least HUF_COMPRESS_WORKSPACE_SIZE_U32 unsigned */
+
+/** HUF_buildCTable_wksp() :
+ * Same as HUF_buildCTable(), but using externally allocated scratch buffer.
+ * `workSpace` must be aligned on 4-bytes boundaries, and be at least as large as a table of 1024 unsigned.
+ */
+size_t HUF_buildCTable_wksp(HUF_CElt *tree, const U32 *count, U32 maxSymbolValue, U32 maxNbBits, void *workSpace, size_t wkspSize);
+
+/*! HUF_readStats() :
+ Read compact Huffman tree, saved by HUF_writeCTable().
+ `huffWeight` is destination buffer.
+ @return : size read from `src` , or an error Code .
+ Note : Needed by HUF_readCTable() and HUF_readDTableXn() . */
+size_t HUF_readStats_wksp(BYTE *huffWeight, size_t hwSize, U32 *rankStats, U32 *nbSymbolsPtr, U32 *tableLogPtr, const void *src, size_t srcSize,
+ void *workspace, size_t workspaceSize);
+
+/** HUF_readCTable() :
+* Loading a CTable saved with HUF_writeCTable() */
+size_t HUF_readCTable_wksp(HUF_CElt *CTable, unsigned maxSymbolValue, const void *src, size_t srcSize, void *workspace, size_t workspaceSize);
+
+/*
+HUF_decompress() does the following:
+1. select the decompression algorithm (X2, X4) based on pre-computed heuristics
+2. build Huffman table from save, using HUF_readDTableXn()
+3. decode 1 or 4 segments in parallel using HUF_decompressSXn_usingDTable
+*/
+
+/** HUF_selectDecoder() :
+* Tells which decoder is likely to decode faster,
+* based on a set of pre-determined metrics.
+* @return : 0==HUF_decompress4X2, 1==HUF_decompress4X4 .
+* Assumption : 0 < cSrcSize < dstSize <= 128 KB */
+U32 HUF_selectDecoder(size_t dstSize, size_t cSrcSize);
+
+size_t HUF_readDTableX2_wksp(HUF_DTable *DTable, const void *src, size_t srcSize, void *workspace, size_t workspaceSize);
+size_t HUF_readDTableX4_wksp(HUF_DTable *DTable, const void *src, size_t srcSize, void *workspace, size_t workspaceSize);
+
+size_t HUF_decompress4X_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable);
+size_t HUF_decompress4X2_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable);
+size_t HUF_decompress4X4_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable);
+
+/* single stream variants */
+
+size_t HUF_compress1X_wksp(void *dst, size_t dstSize, const void *src, size_t srcSize, unsigned maxSymbolValue, unsigned tableLog, void *workSpace,
+ size_t wkspSize); /**< `workSpace` must be a table of at least HUF_COMPRESS_WORKSPACE_SIZE_U32 unsigned */
+size_t HUF_compress1X_usingCTable(void *dst, size_t dstSize, const void *src, size_t srcSize, const HUF_CElt *CTable);
+/** HUF_compress1X_repeat() :
+* Same as HUF_compress1X_wksp(), but considers using hufTable if *repeat != HUF_repeat_none.
+* If it uses hufTable it does not modify hufTable or repeat.
+* If it doesn't, it sets *repeat = HUF_repeat_none, and it sets hufTable to the table used.
+* If preferRepeat then the old table will always be used if valid. */
+size_t HUF_compress1X_repeat(void *dst, size_t dstSize, const void *src, size_t srcSize, unsigned maxSymbolValue, unsigned tableLog, void *workSpace,
+ size_t wkspSize, HUF_CElt *hufTable, HUF_repeat *repeat,
+ int preferRepeat); /**< `workSpace` must be a table of at least HUF_COMPRESS_WORKSPACE_SIZE_U32 unsigned */
+
+size_t HUF_decompress1X_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize);
+size_t HUF_decompress1X2_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace,
+ size_t workspaceSize); /**< single-symbol decoder */
+size_t HUF_decompress1X4_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace,
+ size_t workspaceSize); /**< double-symbols decoder */
+
+size_t HUF_decompress1X_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize,
+ const HUF_DTable *DTable); /**< automatic selection of sing or double symbol decoder, based on DTable */
+size_t HUF_decompress1X2_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable);
+size_t HUF_decompress1X4_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable);
+
+#endif /* HUF_H_298734234 */
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause)
+/*
+ * Huffman decoder, part of New Generation Entropy library
+ * Copyright (C) 2013-2016, Yann Collet.
+ *
+ * You can contact the author at :
+ * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy
+ */
+
+/* **************************************************************
+* Compiler specifics
+****************************************************************/
+#define FORCE_INLINE static __always_inline
+
+/* **************************************************************
+* Dependencies
+****************************************************************/
+#include "bitstream.h" /* BIT_* */
+#include "fse.h" /* header compression */
+#include "huf.h"
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/string.h> /* memcpy, memset */
+
+/* **************************************************************
+* Error Management
+****************************************************************/
+#define HUF_STATIC_ASSERT(c) \
+ { \
+ enum { HUF_static_assert = 1 / (int)(!!(c)) }; \
+ } /* use only *after* variable declarations */
+
+/*-***************************/
+/* generic DTableDesc */
+/*-***************************/
+
+typedef struct {
+ BYTE maxTableLog;
+ BYTE tableType;
+ BYTE tableLog;
+ BYTE reserved;
+} DTableDesc;
+
+static DTableDesc HUF_getDTableDesc(const HUF_DTable *table)
+{
+ DTableDesc dtd;
+ memcpy(&dtd, table, sizeof(dtd));
+ return dtd;
+}
+
+/*-***************************/
+/* single-symbol decoding */
+/*-***************************/
+
+typedef struct {
+ BYTE byte;
+ BYTE nbBits;
+} HUF_DEltX2; /* single-symbol decoding */
+
+size_t HUF_readDTableX2_wksp(HUF_DTable *DTable, const void *src, size_t srcSize, void *workspace, size_t workspaceSize)
+{
+ U32 tableLog = 0;
+ U32 nbSymbols = 0;
+ size_t iSize;
+ void *const dtPtr = DTable + 1;
+ HUF_DEltX2 *const dt = (HUF_DEltX2 *)dtPtr;
+
+ U32 *rankVal;
+ BYTE *huffWeight;
+ size_t spaceUsed32 = 0;
+
+ rankVal = (U32 *)workspace + spaceUsed32;
+ spaceUsed32 += HUF_TABLELOG_ABSOLUTEMAX + 1;
+ huffWeight = (BYTE *)((U32 *)workspace + spaceUsed32);
+ spaceUsed32 += ALIGN(HUF_SYMBOLVALUE_MAX + 1, sizeof(U32)) >> 2;
+
+ if ((spaceUsed32 << 2) > workspaceSize)
+ return ERROR(tableLog_tooLarge);
+ workspace = (U32 *)workspace + spaceUsed32;
+ workspaceSize -= (spaceUsed32 << 2);
+
+ HUF_STATIC_ASSERT(sizeof(DTableDesc) == sizeof(HUF_DTable));
+ /* memset(huffWeight, 0, sizeof(huffWeight)); */ /* is not necessary, even though some analyzer complain ... */
+
+ iSize = HUF_readStats_wksp(huffWeight, HUF_SYMBOLVALUE_MAX + 1, rankVal, &nbSymbols, &tableLog, src, srcSize, workspace, workspaceSize);
+ if (HUF_isError(iSize))
+ return iSize;
+
+ /* Table header */
+ {
+ DTableDesc dtd = HUF_getDTableDesc(DTable);
+ if (tableLog > (U32)(dtd.maxTableLog + 1))
+ return ERROR(tableLog_tooLarge); /* DTable too small, Huffman tree cannot fit in */
+ dtd.tableType = 0;
+ dtd.tableLog = (BYTE)tableLog;
+ memcpy(DTable, &dtd, sizeof(dtd));
+ }
+
+ /* Calculate starting value for each rank */
+ {
+ U32 n, nextRankStart = 0;
+ for (n = 1; n < tableLog + 1; n++) {
+ U32 const curr = nextRankStart;
+ nextRankStart += (rankVal[n] << (n - 1));
+ rankVal[n] = curr;
+ }
+ }
+
+ /* fill DTable */
+ {
+ U32 n;
+ for (n = 0; n < nbSymbols; n++) {
+ U32 const w = huffWeight[n];
+ U32 const length = (1 << w) >> 1;
+ U32 u;
+ HUF_DEltX2 D;
+ D.byte = (BYTE)n;
+ D.nbBits = (BYTE)(tableLog + 1 - w);
+ for (u = rankVal[w]; u < rankVal[w] + length; u++)
+ dt[u] = D;
+ rankVal[w] += length;
+ }
+ }
+
+ return iSize;
+}
+
+static BYTE HUF_decodeSymbolX2(BIT_DStream_t *Dstream, const HUF_DEltX2 *dt, const U32 dtLog)
+{
+ size_t const val = BIT_lookBitsFast(Dstream, dtLog); /* note : dtLog >= 1 */
+ BYTE const c = dt[val].byte;
+ BIT_skipBits(Dstream, dt[val].nbBits);
+ return c;
+}
+
+#define HUF_DECODE_SYMBOLX2_0(ptr, DStreamPtr) *ptr++ = HUF_decodeSymbolX2(DStreamPtr, dt, dtLog)
+
+#define HUF_DECODE_SYMBOLX2_1(ptr, DStreamPtr) \
+ if (ZSTD_64bits() || (HUF_TABLELOG_MAX <= 12)) \
+ HUF_DECODE_SYMBOLX2_0(ptr, DStreamPtr)
+
+#define HUF_DECODE_SYMBOLX2_2(ptr, DStreamPtr) \
+ if (ZSTD_64bits()) \
+ HUF_DECODE_SYMBOLX2_0(ptr, DStreamPtr)
+
+FORCE_INLINE size_t HUF_decodeStreamX2(BYTE *p, BIT_DStream_t *const bitDPtr, BYTE *const pEnd, const HUF_DEltX2 *const dt, const U32 dtLog)
+{
+ BYTE *const pStart = p;
+
+ /* up to 4 symbols at a time */
+ while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) && (p <= pEnd - 4)) {
+ HUF_DECODE_SYMBOLX2_2(p, bitDPtr);
+ HUF_DECODE_SYMBOLX2_1(p, bitDPtr);
+ HUF_DECODE_SYMBOLX2_2(p, bitDPtr);
+ HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+ }
+
+ /* closer to the end */
+ while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) && (p < pEnd))
+ HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+
+ /* no more data to retrieve from bitstream, hence no need to reload */
+ while (p < pEnd)
+ HUF_DECODE_SYMBOLX2_0(p, bitDPtr);
+
+ return pEnd - pStart;
+}
+
+static size_t HUF_decompress1X2_usingDTable_internal(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ BYTE *op = (BYTE *)dst;
+ BYTE *const oend = op + dstSize;
+ const void *dtPtr = DTable + 1;
+ const HUF_DEltX2 *const dt = (const HUF_DEltX2 *)dtPtr;
+ BIT_DStream_t bitD;
+ DTableDesc const dtd = HUF_getDTableDesc(DTable);
+ U32 const dtLog = dtd.tableLog;
+
+ {
+ size_t const errorCode = BIT_initDStream(&bitD, cSrc, cSrcSize);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+
+ HUF_decodeStreamX2(op, &bitD, oend, dt, dtLog);
+
+ /* check */
+ if (!BIT_endOfDStream(&bitD))
+ return ERROR(corruption_detected);
+
+ return dstSize;
+}
+
+size_t HUF_decompress1X2_usingDTable(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ DTableDesc dtd = HUF_getDTableDesc(DTable);
+ if (dtd.tableType != 0)
+ return ERROR(GENERIC);
+ return HUF_decompress1X2_usingDTable_internal(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+
+size_t HUF_decompress1X2_DCtx_wksp(HUF_DTable *DCtx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize)
+{
+ const BYTE *ip = (const BYTE *)cSrc;
+
+ size_t const hSize = HUF_readDTableX2_wksp(DCtx, cSrc, cSrcSize, workspace, workspaceSize);
+ if (HUF_isError(hSize))
+ return hSize;
+ if (hSize >= cSrcSize)
+ return ERROR(srcSize_wrong);
+ ip += hSize;
+ cSrcSize -= hSize;
+
+ return HUF_decompress1X2_usingDTable_internal(dst, dstSize, ip, cSrcSize, DCtx);
+}
+
+static size_t HUF_decompress4X2_usingDTable_internal(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ /* Check */
+ if (cSrcSize < 10)
+ return ERROR(corruption_detected); /* strict minimum : jump table + 1 byte per stream */
+
+ {
+ const BYTE *const istart = (const BYTE *)cSrc;
+ BYTE *const ostart = (BYTE *)dst;
+ BYTE *const oend = ostart + dstSize;
+ const void *const dtPtr = DTable + 1;
+ const HUF_DEltX2 *const dt = (const HUF_DEltX2 *)dtPtr;
+
+ /* Init */
+ BIT_DStream_t bitD1;
+ BIT_DStream_t bitD2;
+ BIT_DStream_t bitD3;
+ BIT_DStream_t bitD4;
+ size_t const length1 = ZSTD_readLE16(istart);
+ size_t const length2 = ZSTD_readLE16(istart + 2);
+ size_t const length3 = ZSTD_readLE16(istart + 4);
+ size_t const length4 = cSrcSize - (length1 + length2 + length3 + 6);
+ const BYTE *const istart1 = istart + 6; /* jumpTable */
+ const BYTE *const istart2 = istart1 + length1;
+ const BYTE *const istart3 = istart2 + length2;
+ const BYTE *const istart4 = istart3 + length3;
+ const size_t segmentSize = (dstSize + 3) / 4;
+ BYTE *const opStart2 = ostart + segmentSize;
+ BYTE *const opStart3 = opStart2 + segmentSize;
+ BYTE *const opStart4 = opStart3 + segmentSize;
+ BYTE *op1 = ostart;
+ BYTE *op2 = opStart2;
+ BYTE *op3 = opStart3;
+ BYTE *op4 = opStart4;
+ U32 endSignal;
+ DTableDesc const dtd = HUF_getDTableDesc(DTable);
+ U32 const dtLog = dtd.tableLog;
+
+ if (length4 > cSrcSize)
+ return ERROR(corruption_detected); /* overflow */
+ {
+ size_t const errorCode = BIT_initDStream(&bitD1, istart1, length1);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+ {
+ size_t const errorCode = BIT_initDStream(&bitD2, istart2, length2);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+ {
+ size_t const errorCode = BIT_initDStream(&bitD3, istart3, length3);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+ {
+ size_t const errorCode = BIT_initDStream(&bitD4, istart4, length4);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+
+ /* 16-32 symbols per loop (4-8 symbols per stream) */
+ endSignal = BIT_reloadDStream(&bitD1) | BIT_reloadDStream(&bitD2) | BIT_reloadDStream(&bitD3) | BIT_reloadDStream(&bitD4);
+ for (; (endSignal == BIT_DStream_unfinished) && (op4 < (oend - 7));) {
+ HUF_DECODE_SYMBOLX2_2(op1, &bitD1);
+ HUF_DECODE_SYMBOLX2_2(op2, &bitD2);
+ HUF_DECODE_SYMBOLX2_2(op3, &bitD3);
+ HUF_DECODE_SYMBOLX2_2(op4, &bitD4);
+ HUF_DECODE_SYMBOLX2_1(op1, &bitD1);
+ HUF_DECODE_SYMBOLX2_1(op2, &bitD2);
+ HUF_DECODE_SYMBOLX2_1(op3, &bitD3);
+ HUF_DECODE_SYMBOLX2_1(op4, &bitD4);
+ HUF_DECODE_SYMBOLX2_2(op1, &bitD1);
+ HUF_DECODE_SYMBOLX2_2(op2, &bitD2);
+ HUF_DECODE_SYMBOLX2_2(op3, &bitD3);
+ HUF_DECODE_SYMBOLX2_2(op4, &bitD4);
+ HUF_DECODE_SYMBOLX2_0(op1, &bitD1);
+ HUF_DECODE_SYMBOLX2_0(op2, &bitD2);
+ HUF_DECODE_SYMBOLX2_0(op3, &bitD3);
+ HUF_DECODE_SYMBOLX2_0(op4, &bitD4);
+ endSignal = BIT_reloadDStream(&bitD1) | BIT_reloadDStream(&bitD2) | BIT_reloadDStream(&bitD3) | BIT_reloadDStream(&bitD4);
+ }
+
+ /* check corruption */
+ if (op1 > opStart2)
+ return ERROR(corruption_detected);
+ if (op2 > opStart3)
+ return ERROR(corruption_detected);
+ if (op3 > opStart4)
+ return ERROR(corruption_detected);
+ /* note : op4 supposed already verified within main loop */
+
+ /* finish bitStreams one by one */
+ HUF_decodeStreamX2(op1, &bitD1, opStart2, dt, dtLog);
+ HUF_decodeStreamX2(op2, &bitD2, opStart3, dt, dtLog);
+ HUF_decodeStreamX2(op3, &bitD3, opStart4, dt, dtLog);
+ HUF_decodeStreamX2(op4, &bitD4, oend, dt, dtLog);
+
+ /* check */
+ endSignal = BIT_endOfDStream(&bitD1) & BIT_endOfDStream(&bitD2) & BIT_endOfDStream(&bitD3) & BIT_endOfDStream(&bitD4);
+ if (!endSignal)
+ return ERROR(corruption_detected);
+
+ /* decoded size */
+ return dstSize;
+ }
+}
+
+size_t HUF_decompress4X2_usingDTable(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ DTableDesc dtd = HUF_getDTableDesc(DTable);
+ if (dtd.tableType != 0)
+ return ERROR(GENERIC);
+ return HUF_decompress4X2_usingDTable_internal(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+
+size_t HUF_decompress4X2_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize)
+{
+ const BYTE *ip = (const BYTE *)cSrc;
+
+ size_t const hSize = HUF_readDTableX2_wksp(dctx, cSrc, cSrcSize, workspace, workspaceSize);
+ if (HUF_isError(hSize))
+ return hSize;
+ if (hSize >= cSrcSize)
+ return ERROR(srcSize_wrong);
+ ip += hSize;
+ cSrcSize -= hSize;
+
+ return HUF_decompress4X2_usingDTable_internal(dst, dstSize, ip, cSrcSize, dctx);
+}
+
+/* *************************/
+/* double-symbols decoding */
+/* *************************/
+typedef struct {
+ U16 sequence;
+ BYTE nbBits;
+ BYTE length;
+} HUF_DEltX4; /* double-symbols decoding */
+
+typedef struct {
+ BYTE symbol;
+ BYTE weight;
+} sortedSymbol_t;
+
+/* HUF_fillDTableX4Level2() :
+ * `rankValOrigin` must be a table of at least (HUF_TABLELOG_MAX + 1) U32 */
+static void HUF_fillDTableX4Level2(HUF_DEltX4 *DTable, U32 sizeLog, const U32 consumed, const U32 *rankValOrigin, const int minWeight,
+ const sortedSymbol_t *sortedSymbols, const U32 sortedListSize, U32 nbBitsBaseline, U16 baseSeq)
+{
+ HUF_DEltX4 DElt;
+ U32 rankVal[HUF_TABLELOG_MAX + 1];
+
+ /* get pre-calculated rankVal */
+ memcpy(rankVal, rankValOrigin, sizeof(rankVal));
+
+ /* fill skipped values */
+ if (minWeight > 1) {
+ U32 i, skipSize = rankVal[minWeight];
+ ZSTD_writeLE16(&(DElt.sequence), baseSeq);
+ DElt.nbBits = (BYTE)(consumed);
+ DElt.length = 1;
+ for (i = 0; i < skipSize; i++)
+ DTable[i] = DElt;
+ }
+
+ /* fill DTable */
+ {
+ U32 s;
+ for (s = 0; s < sortedListSize; s++) { /* note : sortedSymbols already skipped */
+ const U32 symbol = sortedSymbols[s].symbol;
+ const U32 weight = sortedSymbols[s].weight;
+ const U32 nbBits = nbBitsBaseline - weight;
+ const U32 length = 1 << (sizeLog - nbBits);
+ const U32 start = rankVal[weight];
+ U32 i = start;
+ const U32 end = start + length;
+
+ ZSTD_writeLE16(&(DElt.sequence), (U16)(baseSeq + (symbol << 8)));
+ DElt.nbBits = (BYTE)(nbBits + consumed);
+ DElt.length = 2;
+ do {
+ DTable[i++] = DElt;
+ } while (i < end); /* since length >= 1 */
+
+ rankVal[weight] += length;
+ }
+ }
+}
+
+typedef U32 rankVal_t[HUF_TABLELOG_MAX][HUF_TABLELOG_MAX + 1];
+typedef U32 rankValCol_t[HUF_TABLELOG_MAX + 1];
+
+static void HUF_fillDTableX4(HUF_DEltX4 *DTable, const U32 targetLog, const sortedSymbol_t *sortedList, const U32 sortedListSize, const U32 *rankStart,
+ rankVal_t rankValOrigin, const U32 maxWeight, const U32 nbBitsBaseline)
+{
+ U32 rankVal[HUF_TABLELOG_MAX + 1];
+ const int scaleLog = nbBitsBaseline - targetLog; /* note : targetLog >= srcLog, hence scaleLog <= 1 */
+ const U32 minBits = nbBitsBaseline - maxWeight;
+ U32 s;
+
+ memcpy(rankVal, rankValOrigin, sizeof(rankVal));
+
+ /* fill DTable */
+ for (s = 0; s < sortedListSize; s++) {
+ const U16 symbol = sortedList[s].symbol;
+ const U32 weight = sortedList[s].weight;
+ const U32 nbBits = nbBitsBaseline - weight;
+ const U32 start = rankVal[weight];
+ const U32 length = 1 << (targetLog - nbBits);
+
+ if (targetLog - nbBits >= minBits) { /* enough room for a second symbol */
+ U32 sortedRank;
+ int minWeight = nbBits + scaleLog;
+ if (minWeight < 1)
+ minWeight = 1;
+ sortedRank = rankStart[minWeight];
+ HUF_fillDTableX4Level2(DTable + start, targetLog - nbBits, nbBits, rankValOrigin[nbBits], minWeight, sortedList + sortedRank,
+ sortedListSize - sortedRank, nbBitsBaseline, symbol);
+ } else {
+ HUF_DEltX4 DElt;
+ ZSTD_writeLE16(&(DElt.sequence), symbol);
+ DElt.nbBits = (BYTE)(nbBits);
+ DElt.length = 1;
+ {
+ U32 const end = start + length;
+ U32 u;
+ for (u = start; u < end; u++)
+ DTable[u] = DElt;
+ }
+ }
+ rankVal[weight] += length;
+ }
+}
+
+size_t HUF_readDTableX4_wksp(HUF_DTable *DTable, const void *src, size_t srcSize, void *workspace, size_t workspaceSize)
+{
+ U32 tableLog, maxW, sizeOfSort, nbSymbols;
+ DTableDesc dtd = HUF_getDTableDesc(DTable);
+ U32 const maxTableLog = dtd.maxTableLog;
+ size_t iSize;
+ void *dtPtr = DTable + 1; /* force compiler to avoid strict-aliasing */
+ HUF_DEltX4 *const dt = (HUF_DEltX4 *)dtPtr;
+ U32 *rankStart;
+
+ rankValCol_t *rankVal;
+ U32 *rankStats;
+ U32 *rankStart0;
+ sortedSymbol_t *sortedSymbol;
+ BYTE *weightList;
+ size_t spaceUsed32 = 0;
+
+ HUF_STATIC_ASSERT((sizeof(rankValCol_t) & 3) == 0);
+
+ rankVal = (rankValCol_t *)((U32 *)workspace + spaceUsed32);
+ spaceUsed32 += (sizeof(rankValCol_t) * HUF_TABLELOG_MAX) >> 2;
+ rankStats = (U32 *)workspace + spaceUsed32;
+ spaceUsed32 += HUF_TABLELOG_MAX + 1;
+ rankStart0 = (U32 *)workspace + spaceUsed32;
+ spaceUsed32 += HUF_TABLELOG_MAX + 2;
+ sortedSymbol = (sortedSymbol_t *)((U32 *)workspace + spaceUsed32);
+ spaceUsed32 += ALIGN(sizeof(sortedSymbol_t) * (HUF_SYMBOLVALUE_MAX + 1), sizeof(U32)) >> 2;
+ weightList = (BYTE *)((U32 *)workspace + spaceUsed32);
+ spaceUsed32 += ALIGN(HUF_SYMBOLVALUE_MAX + 1, sizeof(U32)) >> 2;
+
+ if ((spaceUsed32 << 2) > workspaceSize)
+ return ERROR(tableLog_tooLarge);
+ workspace = (U32 *)workspace + spaceUsed32;
+ workspaceSize -= (spaceUsed32 << 2);
+
+ rankStart = rankStart0 + 1;
+ memset(rankStats, 0, sizeof(U32) * (2 * HUF_TABLELOG_MAX + 2 + 1));
+
+ HUF_STATIC_ASSERT(sizeof(HUF_DEltX4) == sizeof(HUF_DTable)); /* if compiler fails here, assertion is wrong */
+ if (maxTableLog > HUF_TABLELOG_MAX)
+ return ERROR(tableLog_tooLarge);
+ /* memset(weightList, 0, sizeof(weightList)); */ /* is not necessary, even though some analyzer complain ... */
+
+ iSize = HUF_readStats_wksp(weightList, HUF_SYMBOLVALUE_MAX + 1, rankStats, &nbSymbols, &tableLog, src, srcSize, workspace, workspaceSize);
+ if (HUF_isError(iSize))
+ return iSize;
+
+ /* check result */
+ if (tableLog > maxTableLog)
+ return ERROR(tableLog_tooLarge); /* DTable can't fit code depth */
+
+ /* find maxWeight */
+ for (maxW = tableLog; rankStats[maxW] == 0; maxW--) {
+ } /* necessarily finds a solution before 0 */
+
+ /* Get start index of each weight */
+ {
+ U32 w, nextRankStart = 0;
+ for (w = 1; w < maxW + 1; w++) {
+ U32 curr = nextRankStart;
+ nextRankStart += rankStats[w];
+ rankStart[w] = curr;
+ }
+ rankStart[0] = nextRankStart; /* put all 0w symbols at the end of sorted list*/
+ sizeOfSort = nextRankStart;
+ }
+
+ /* sort symbols by weight */
+ {
+ U32 s;
+ for (s = 0; s < nbSymbols; s++) {
+ U32 const w = weightList[s];
+ U32 const r = rankStart[w]++;
+ sortedSymbol[r].symbol = (BYTE)s;
+ sortedSymbol[r].weight = (BYTE)w;
+ }
+ rankStart[0] = 0; /* forget 0w symbols; this is beginning of weight(1) */
+ }
+
+ /* Build rankVal */
+ {
+ U32 *const rankVal0 = rankVal[0];
+ {
+ int const rescale = (maxTableLog - tableLog) - 1; /* tableLog <= maxTableLog */
+ U32 nextRankVal = 0;
+ U32 w;
+ for (w = 1; w < maxW + 1; w++) {
+ U32 curr = nextRankVal;
+ nextRankVal += rankStats[w] << (w + rescale);
+ rankVal0[w] = curr;
+ }
+ }
+ {
+ U32 const minBits = tableLog + 1 - maxW;
+ U32 consumed;
+ for (consumed = minBits; consumed < maxTableLog - minBits + 1; consumed++) {
+ U32 *const rankValPtr = rankVal[consumed];
+ U32 w;
+ for (w = 1; w < maxW + 1; w++) {
+ rankValPtr[w] = rankVal0[w] >> consumed;
+ }
+ }
+ }
+ }
+
+ HUF_fillDTableX4(dt, maxTableLog, sortedSymbol, sizeOfSort, rankStart0, rankVal, maxW, tableLog + 1);
+
+ dtd.tableLog = (BYTE)maxTableLog;
+ dtd.tableType = 1;
+ memcpy(DTable, &dtd, sizeof(dtd));
+ return iSize;
+}
+
+static U32 HUF_decodeSymbolX4(void *op, BIT_DStream_t *DStream, const HUF_DEltX4 *dt, const U32 dtLog)
+{
+ size_t const val = BIT_lookBitsFast(DStream, dtLog); /* note : dtLog >= 1 */
+ memcpy(op, dt + val, 2);
+ BIT_skipBits(DStream, dt[val].nbBits);
+ return dt[val].length;
+}
+
+static U32 HUF_decodeLastSymbolX4(void *op, BIT_DStream_t *DStream, const HUF_DEltX4 *dt, const U32 dtLog)
+{
+ size_t const val = BIT_lookBitsFast(DStream, dtLog); /* note : dtLog >= 1 */
+ memcpy(op, dt + val, 1);
+ if (dt[val].length == 1)
+ BIT_skipBits(DStream, dt[val].nbBits);
+ else {
+ if (DStream->bitsConsumed < (sizeof(DStream->bitContainer) * 8)) {
+ BIT_skipBits(DStream, dt[val].nbBits);
+ if (DStream->bitsConsumed > (sizeof(DStream->bitContainer) * 8))
+ /* ugly hack; works only because it's the last symbol. Note : can't easily extract nbBits from just this symbol */
+ DStream->bitsConsumed = (sizeof(DStream->bitContainer) * 8);
+ }
+ }
+ return 1;
+}
+
+#define HUF_DECODE_SYMBOLX4_0(ptr, DStreamPtr) ptr += HUF_decodeSymbolX4(ptr, DStreamPtr, dt, dtLog)
+
+#define HUF_DECODE_SYMBOLX4_1(ptr, DStreamPtr) \
+ if (ZSTD_64bits() || (HUF_TABLELOG_MAX <= 12)) \
+ ptr += HUF_decodeSymbolX4(ptr, DStreamPtr, dt, dtLog)
+
+#define HUF_DECODE_SYMBOLX4_2(ptr, DStreamPtr) \
+ if (ZSTD_64bits()) \
+ ptr += HUF_decodeSymbolX4(ptr, DStreamPtr, dt, dtLog)
+
+FORCE_INLINE size_t HUF_decodeStreamX4(BYTE *p, BIT_DStream_t *bitDPtr, BYTE *const pEnd, const HUF_DEltX4 *const dt, const U32 dtLog)
+{
+ BYTE *const pStart = p;
+
+ /* up to 8 symbols at a time */
+ while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) & (p < pEnd - (sizeof(bitDPtr->bitContainer) - 1))) {
+ HUF_DECODE_SYMBOLX4_2(p, bitDPtr);
+ HUF_DECODE_SYMBOLX4_1(p, bitDPtr);
+ HUF_DECODE_SYMBOLX4_2(p, bitDPtr);
+ HUF_DECODE_SYMBOLX4_0(p, bitDPtr);
+ }
+
+ /* closer to end : up to 2 symbols at a time */
+ while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) & (p <= pEnd - 2))
+ HUF_DECODE_SYMBOLX4_0(p, bitDPtr);
+
+ while (p <= pEnd - 2)
+ HUF_DECODE_SYMBOLX4_0(p, bitDPtr); /* no need to reload : reached the end of DStream */
+
+ if (p < pEnd)
+ p += HUF_decodeLastSymbolX4(p, bitDPtr, dt, dtLog);
+
+ return p - pStart;
+}
+
+static size_t HUF_decompress1X4_usingDTable_internal(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ BIT_DStream_t bitD;
+
+ /* Init */
+ {
+ size_t const errorCode = BIT_initDStream(&bitD, cSrc, cSrcSize);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+
+ /* decode */
+ {
+ BYTE *const ostart = (BYTE *)dst;
+ BYTE *const oend = ostart + dstSize;
+ const void *const dtPtr = DTable + 1; /* force compiler to not use strict-aliasing */
+ const HUF_DEltX4 *const dt = (const HUF_DEltX4 *)dtPtr;
+ DTableDesc const dtd = HUF_getDTableDesc(DTable);
+ HUF_decodeStreamX4(ostart, &bitD, oend, dt, dtd.tableLog);
+ }
+
+ /* check */
+ if (!BIT_endOfDStream(&bitD))
+ return ERROR(corruption_detected);
+
+ /* decoded size */
+ return dstSize;
+}
+
+size_t HUF_decompress1X4_usingDTable(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ DTableDesc dtd = HUF_getDTableDesc(DTable);
+ if (dtd.tableType != 1)
+ return ERROR(GENERIC);
+ return HUF_decompress1X4_usingDTable_internal(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+
+size_t HUF_decompress1X4_DCtx_wksp(HUF_DTable *DCtx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize)
+{
+ const BYTE *ip = (const BYTE *)cSrc;
+
+ size_t const hSize = HUF_readDTableX4_wksp(DCtx, cSrc, cSrcSize, workspace, workspaceSize);
+ if (HUF_isError(hSize))
+ return hSize;
+ if (hSize >= cSrcSize)
+ return ERROR(srcSize_wrong);
+ ip += hSize;
+ cSrcSize -= hSize;
+
+ return HUF_decompress1X4_usingDTable_internal(dst, dstSize, ip, cSrcSize, DCtx);
+}
+
+static size_t HUF_decompress4X4_usingDTable_internal(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ if (cSrcSize < 10)
+ return ERROR(corruption_detected); /* strict minimum : jump table + 1 byte per stream */
+
+ {
+ const BYTE *const istart = (const BYTE *)cSrc;
+ BYTE *const ostart = (BYTE *)dst;
+ BYTE *const oend = ostart + dstSize;
+ const void *const dtPtr = DTable + 1;
+ const HUF_DEltX4 *const dt = (const HUF_DEltX4 *)dtPtr;
+
+ /* Init */
+ BIT_DStream_t bitD1;
+ BIT_DStream_t bitD2;
+ BIT_DStream_t bitD3;
+ BIT_DStream_t bitD4;
+ size_t const length1 = ZSTD_readLE16(istart);
+ size_t const length2 = ZSTD_readLE16(istart + 2);
+ size_t const length3 = ZSTD_readLE16(istart + 4);
+ size_t const length4 = cSrcSize - (length1 + length2 + length3 + 6);
+ const BYTE *const istart1 = istart + 6; /* jumpTable */
+ const BYTE *const istart2 = istart1 + length1;
+ const BYTE *const istart3 = istart2 + length2;
+ const BYTE *const istart4 = istart3 + length3;
+ size_t const segmentSize = (dstSize + 3) / 4;
+ BYTE *const opStart2 = ostart + segmentSize;
+ BYTE *const opStart3 = opStart2 + segmentSize;
+ BYTE *const opStart4 = opStart3 + segmentSize;
+ BYTE *op1 = ostart;
+ BYTE *op2 = opStart2;
+ BYTE *op3 = opStart3;
+ BYTE *op4 = opStart4;
+ U32 endSignal;
+ DTableDesc const dtd = HUF_getDTableDesc(DTable);
+ U32 const dtLog = dtd.tableLog;
+
+ if (length4 > cSrcSize)
+ return ERROR(corruption_detected); /* overflow */
+ {
+ size_t const errorCode = BIT_initDStream(&bitD1, istart1, length1);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+ {
+ size_t const errorCode = BIT_initDStream(&bitD2, istart2, length2);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+ {
+ size_t const errorCode = BIT_initDStream(&bitD3, istart3, length3);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+ {
+ size_t const errorCode = BIT_initDStream(&bitD4, istart4, length4);
+ if (HUF_isError(errorCode))
+ return errorCode;
+ }
+
+ /* 16-32 symbols per loop (4-8 symbols per stream) */
+ endSignal = BIT_reloadDStream(&bitD1) | BIT_reloadDStream(&bitD2) | BIT_reloadDStream(&bitD3) | BIT_reloadDStream(&bitD4);
+ for (; (endSignal == BIT_DStream_unfinished) & (op4 < (oend - (sizeof(bitD4.bitContainer) - 1)));) {
+ HUF_DECODE_SYMBOLX4_2(op1, &bitD1);
+ HUF_DECODE_SYMBOLX4_2(op2, &bitD2);
+ HUF_DECODE_SYMBOLX4_2(op3, &bitD3);
+ HUF_DECODE_SYMBOLX4_2(op4, &bitD4);
+ HUF_DECODE_SYMBOLX4_1(op1, &bitD1);
+ HUF_DECODE_SYMBOLX4_1(op2, &bitD2);
+ HUF_DECODE_SYMBOLX4_1(op3, &bitD3);
+ HUF_DECODE_SYMBOLX4_1(op4, &bitD4);
+ HUF_DECODE_SYMBOLX4_2(op1, &bitD1);
+ HUF_DECODE_SYMBOLX4_2(op2, &bitD2);
+ HUF_DECODE_SYMBOLX4_2(op3, &bitD3);
+ HUF_DECODE_SYMBOLX4_2(op4, &bitD4);
+ HUF_DECODE_SYMBOLX4_0(op1, &bitD1);
+ HUF_DECODE_SYMBOLX4_0(op2, &bitD2);
+ HUF_DECODE_SYMBOLX4_0(op3, &bitD3);
+ HUF_DECODE_SYMBOLX4_0(op4, &bitD4);
+
+ endSignal = BIT_reloadDStream(&bitD1) | BIT_reloadDStream(&bitD2) | BIT_reloadDStream(&bitD3) | BIT_reloadDStream(&bitD4);
+ }
+
+ /* check corruption */
+ if (op1 > opStart2)
+ return ERROR(corruption_detected);
+ if (op2 > opStart3)
+ return ERROR(corruption_detected);
+ if (op3 > opStart4)
+ return ERROR(corruption_detected);
+ /* note : op4 already verified within main loop */
+
+ /* finish bitStreams one by one */
+ HUF_decodeStreamX4(op1, &bitD1, opStart2, dt, dtLog);
+ HUF_decodeStreamX4(op2, &bitD2, opStart3, dt, dtLog);
+ HUF_decodeStreamX4(op3, &bitD3, opStart4, dt, dtLog);
+ HUF_decodeStreamX4(op4, &bitD4, oend, dt, dtLog);
+
+ /* check */
+ {
+ U32 const endCheck = BIT_endOfDStream(&bitD1) & BIT_endOfDStream(&bitD2) & BIT_endOfDStream(&bitD3) & BIT_endOfDStream(&bitD4);
+ if (!endCheck)
+ return ERROR(corruption_detected);
+ }
+
+ /* decoded size */
+ return dstSize;
+ }
+}
+
+size_t HUF_decompress4X4_usingDTable(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ DTableDesc dtd = HUF_getDTableDesc(DTable);
+ if (dtd.tableType != 1)
+ return ERROR(GENERIC);
+ return HUF_decompress4X4_usingDTable_internal(dst, dstSize, cSrc, cSrcSize, DTable);
+}
+
+size_t HUF_decompress4X4_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize)
+{
+ const BYTE *ip = (const BYTE *)cSrc;
+
+ size_t hSize = HUF_readDTableX4_wksp(dctx, cSrc, cSrcSize, workspace, workspaceSize);
+ if (HUF_isError(hSize))
+ return hSize;
+ if (hSize >= cSrcSize)
+ return ERROR(srcSize_wrong);
+ ip += hSize;
+ cSrcSize -= hSize;
+
+ return HUF_decompress4X4_usingDTable_internal(dst, dstSize, ip, cSrcSize, dctx);
+}
+
+/* ********************************/
+/* Generic decompression selector */
+/* ********************************/
+
+size_t HUF_decompress1X_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ DTableDesc const dtd = HUF_getDTableDesc(DTable);
+ return dtd.tableType ? HUF_decompress1X4_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable)
+ : HUF_decompress1X2_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable);
+}
+
+size_t HUF_decompress4X_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable)
+{
+ DTableDesc const dtd = HUF_getDTableDesc(DTable);
+ return dtd.tableType ? HUF_decompress4X4_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable)
+ : HUF_decompress4X2_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable);
+}
+
+typedef struct {
+ U32 tableTime;
+ U32 decode256Time;
+} algo_time_t;
+static const algo_time_t algoTime[16 /* Quantization */][3 /* single, double, quad */] = {
+ /* single, double, quad */
+ {{0, 0}, {1, 1}, {2, 2}}, /* Q==0 : impossible */
+ {{0, 0}, {1, 1}, {2, 2}}, /* Q==1 : impossible */
+ {{38, 130}, {1313, 74}, {2151, 38}}, /* Q == 2 : 12-18% */
+ {{448, 128}, {1353, 74}, {2238, 41}}, /* Q == 3 : 18-25% */
+ {{556, 128}, {1353, 74}, {2238, 47}}, /* Q == 4 : 25-32% */
+ {{714, 128}, {1418, 74}, {2436, 53}}, /* Q == 5 : 32-38% */
+ {{883, 128}, {1437, 74}, {2464, 61}}, /* Q == 6 : 38-44% */
+ {{897, 128}, {1515, 75}, {2622, 68}}, /* Q == 7 : 44-50% */
+ {{926, 128}, {1613, 75}, {2730, 75}}, /* Q == 8 : 50-56% */
+ {{947, 128}, {1729, 77}, {3359, 77}}, /* Q == 9 : 56-62% */
+ {{1107, 128}, {2083, 81}, {4006, 84}}, /* Q ==10 : 62-69% */
+ {{1177, 128}, {2379, 87}, {4785, 88}}, /* Q ==11 : 69-75% */
+ {{1242, 128}, {2415, 93}, {5155, 84}}, /* Q ==12 : 75-81% */
+ {{1349, 128}, {2644, 106}, {5260, 106}}, /* Q ==13 : 81-87% */
+ {{1455, 128}, {2422, 124}, {4174, 124}}, /* Q ==14 : 87-93% */
+ {{722, 128}, {1891, 145}, {1936, 146}}, /* Q ==15 : 93-99% */
+};
+
+/** HUF_selectDecoder() :
+* Tells which decoder is likely to decode faster,
+* based on a set of pre-determined metrics.
+* @return : 0==HUF_decompress4X2, 1==HUF_decompress4X4 .
+* Assumption : 0 < cSrcSize < dstSize <= 128 KB */
+U32 HUF_selectDecoder(size_t dstSize, size_t cSrcSize)
+{
+ /* decoder timing evaluation */
+ U32 const Q = (U32)(cSrcSize * 16 / dstSize); /* Q < 16 since dstSize > cSrcSize */
+ U32 const D256 = (U32)(dstSize >> 8);
+ U32 const DTime0 = algoTime[Q][0].tableTime + (algoTime[Q][0].decode256Time * D256);
+ U32 DTime1 = algoTime[Q][1].tableTime + (algoTime[Q][1].decode256Time * D256);
+ DTime1 += DTime1 >> 3; /* advantage to algorithm using less memory, for cache eviction */
+
+ return DTime1 < DTime0;
+}
+
+typedef size_t (*decompressionAlgo)(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize);
+
+size_t HUF_decompress4X_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize)
+{
+ /* validation checks */
+ if (dstSize == 0)
+ return ERROR(dstSize_tooSmall);
+ if (cSrcSize > dstSize)
+ return ERROR(corruption_detected); /* invalid */
+ if (cSrcSize == dstSize) {
+ memcpy(dst, cSrc, dstSize);
+ return dstSize;
+ } /* not compressed */
+ if (cSrcSize == 1) {
+ memset(dst, *(const BYTE *)cSrc, dstSize);
+ return dstSize;
+ } /* RLE */
+
+ {
+ U32 const algoNb = HUF_selectDecoder(dstSize, cSrcSize);
+ return algoNb ? HUF_decompress4X4_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize)
+ : HUF_decompress4X2_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize);
+ }
+}
+
+size_t HUF_decompress4X_hufOnly_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize)
+{
+ /* validation checks */
+ if (dstSize == 0)
+ return ERROR(dstSize_tooSmall);
+ if ((cSrcSize >= dstSize) || (cSrcSize <= 1))
+ return ERROR(corruption_detected); /* invalid */
+
+ {
+ U32 const algoNb = HUF_selectDecoder(dstSize, cSrcSize);
+ return algoNb ? HUF_decompress4X4_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize)
+ : HUF_decompress4X2_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize);
+ }
+}
+
+size_t HUF_decompress1X_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize)
+{
+ /* validation checks */
+ if (dstSize == 0)
+ return ERROR(dstSize_tooSmall);
+ if (cSrcSize > dstSize)
+ return ERROR(corruption_detected); /* invalid */
+ if (cSrcSize == dstSize) {
+ memcpy(dst, cSrc, dstSize);
+ return dstSize;
+ } /* not compressed */
+ if (cSrcSize == 1) {
+ memset(dst, *(const BYTE *)cSrc, dstSize);
+ return dstSize;
+ } /* RLE */
+
+ {
+ U32 const algoNb = HUF_selectDecoder(dstSize, cSrcSize);
+ return algoNb ? HUF_decompress1X4_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize)
+ : HUF_decompress1X2_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize);
+ }
+}
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */
+/**
+ * Copyright (c) 2016-present, Yann Collet, Facebook, Inc.
+ * All rights reserved.
+ */
+
+#ifndef MEM_H_MODULE
+#define MEM_H_MODULE
+
+/*-****************************************
+* Dependencies
+******************************************/
+#include <asm/unaligned.h>
+#include <compiler.h>
+#include <linux/string.h> /* memcpy */
+#include <linux/types.h> /* size_t, ptrdiff_t */
+
+/*-****************************************
+* Compiler specifics
+******************************************/
+#define ZSTD_STATIC static __inline __attribute__((unused))
+
+/*-**************************************************************
+* Basic Types
+*****************************************************************/
+typedef uint8_t BYTE;
+typedef uint16_t U16;
+typedef int16_t S16;
+typedef uint32_t U32;
+typedef int32_t S32;
+typedef uint64_t U64;
+typedef int64_t S64;
+typedef ptrdiff_t iPtrDiff;
+typedef uintptr_t uPtrDiff;
+
+/*-**************************************************************
+* Memory I/O
+*****************************************************************/
+ZSTD_STATIC unsigned ZSTD_32bits(void) { return sizeof(size_t) == 4; }
+ZSTD_STATIC unsigned ZSTD_64bits(void) { return sizeof(size_t) == 8; }
+
+#if defined(__LITTLE_ENDIAN)
+#define ZSTD_LITTLE_ENDIAN 1
+#else
+#define ZSTD_LITTLE_ENDIAN 0
+#endif
+
+ZSTD_STATIC unsigned ZSTD_isLittleEndian(void) { return ZSTD_LITTLE_ENDIAN; }
+
+ZSTD_STATIC U16 ZSTD_read16(const void *memPtr) { return get_unaligned((const U16 *)memPtr); }
+
+ZSTD_STATIC U32 ZSTD_read32(const void *memPtr) { return get_unaligned((const U32 *)memPtr); }
+
+ZSTD_STATIC U64 ZSTD_read64(const void *memPtr) { return get_unaligned((const U64 *)memPtr); }
+
+ZSTD_STATIC size_t ZSTD_readST(const void *memPtr) { return get_unaligned((const size_t *)memPtr); }
+
+ZSTD_STATIC void ZSTD_write16(void *memPtr, U16 value) { put_unaligned(value, (U16 *)memPtr); }
+
+ZSTD_STATIC void ZSTD_write32(void *memPtr, U32 value) { put_unaligned(value, (U32 *)memPtr); }
+
+ZSTD_STATIC void ZSTD_write64(void *memPtr, U64 value) { put_unaligned(value, (U64 *)memPtr); }
+
+/*=== Little endian r/w ===*/
+
+ZSTD_STATIC U16 ZSTD_readLE16(const void *memPtr) { return get_unaligned_le16(memPtr); }
+
+ZSTD_STATIC void ZSTD_writeLE16(void *memPtr, U16 val) { put_unaligned_le16(val, memPtr); }
+
+ZSTD_STATIC U32 ZSTD_readLE24(const void *memPtr) { return ZSTD_readLE16(memPtr) + (((const BYTE *)memPtr)[2] << 16); }
+
+ZSTD_STATIC void ZSTD_writeLE24(void *memPtr, U32 val)
+{
+ ZSTD_writeLE16(memPtr, (U16)val);
+ ((BYTE *)memPtr)[2] = (BYTE)(val >> 16);
+}
+
+ZSTD_STATIC U32 ZSTD_readLE32(const void *memPtr) { return get_unaligned_le32(memPtr); }
+
+ZSTD_STATIC void ZSTD_writeLE32(void *memPtr, U32 val32) { put_unaligned_le32(val32, memPtr); }
+
+ZSTD_STATIC U64 ZSTD_readLE64(const void *memPtr) { return get_unaligned_le64(memPtr); }
+
+ZSTD_STATIC void ZSTD_writeLE64(void *memPtr, U64 val64) { put_unaligned_le64(val64, memPtr); }
+
+ZSTD_STATIC size_t ZSTD_readLEST(const void *memPtr)
+{
+ if (ZSTD_32bits())
+ return (size_t)ZSTD_readLE32(memPtr);
+ else
+ return (size_t)ZSTD_readLE64(memPtr);
+}
+
+ZSTD_STATIC void ZSTD_writeLEST(void *memPtr, size_t val)
+{
+ if (ZSTD_32bits())
+ ZSTD_writeLE32(memPtr, (U32)val);
+ else
+ ZSTD_writeLE64(memPtr, (U64)val);
+}
+
+/*=== Big endian r/w ===*/
+
+ZSTD_STATIC U32 ZSTD_readBE32(const void *memPtr) { return get_unaligned_be32(memPtr); }
+
+ZSTD_STATIC void ZSTD_writeBE32(void *memPtr, U32 val32) { put_unaligned_be32(val32, memPtr); }
+
+ZSTD_STATIC U64 ZSTD_readBE64(const void *memPtr) { return get_unaligned_be64(memPtr); }
+
+ZSTD_STATIC void ZSTD_writeBE64(void *memPtr, U64 val64) { put_unaligned_be64(val64, memPtr); }
+
+ZSTD_STATIC size_t ZSTD_readBEST(const void *memPtr)
+{
+ if (ZSTD_32bits())
+ return (size_t)ZSTD_readBE32(memPtr);
+ else
+ return (size_t)ZSTD_readBE64(memPtr);
+}
+
+ZSTD_STATIC void ZSTD_writeBEST(void *memPtr, size_t val)
+{
+ if (ZSTD_32bits())
+ ZSTD_writeBE32(memPtr, (U32)val);
+ else
+ ZSTD_writeBE64(memPtr, (U64)val);
+}
+
+/* function safe only for comparisons */
+ZSTD_STATIC U32 ZSTD_readMINMATCH(const void *memPtr, U32 length)
+{
+ switch (length) {
+ default:
+ case 4: return ZSTD_read32(memPtr);
+ case 3:
+ if (ZSTD_isLittleEndian())
+ return ZSTD_read32(memPtr) << 8;
+ else
+ return ZSTD_read32(memPtr) >> 8;
+ }
+}
+
+#endif /* MEM_H_MODULE */
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear)
+/**
+ * Copyright (c) 2016-present, Yann Collet, Facebook, Inc.
+ * All rights reserved.
+ */
+
+/*-*************************************
+* Dependencies
+***************************************/
+#include "error_private.h"
+#include "zstd_internal.h" /* declaration of ZSTD_isError, ZSTD_getErrorName, ZSTD_getErrorCode, ZSTD_getErrorString, ZSTD_versionNumber */
+#include <linux/kernel.h>
+
+/*=**************************************************************
+* Custom allocator
+****************************************************************/
+
+#define stack_push(stack, size) \
+ ({ \
+ void *const ptr = ZSTD_PTR_ALIGN((stack)->ptr); \
+ (stack)->ptr = (char *)ptr + (size); \
+ (stack)->ptr <= (stack)->end ? ptr : NULL; \
+ })
+
+ZSTD_customMem ZSTD_initStack(void *workspace, size_t workspaceSize)
+{
+ ZSTD_customMem stackMem = {ZSTD_stackAlloc, ZSTD_stackFree, workspace};
+ ZSTD_stack *stack = (ZSTD_stack *)workspace;
+ /* Verify preconditions */
+ if (!workspace || workspaceSize < sizeof(ZSTD_stack) || workspace != ZSTD_PTR_ALIGN(workspace)) {
+ ZSTD_customMem error = {NULL, NULL, NULL};
+ return error;
+ }
+ /* Initialize the stack */
+ stack->ptr = workspace;
+ stack->end = (char *)workspace + workspaceSize;
+ stack_push(stack, sizeof(ZSTD_stack));
+ return stackMem;
+}
+
+void *ZSTD_stackAllocAll(void *opaque, size_t *size)
+{
+ ZSTD_stack *stack = (ZSTD_stack *)opaque;
+ *size = (BYTE const *)stack->end - (BYTE *)ZSTD_PTR_ALIGN(stack->ptr);
+ return stack_push(stack, *size);
+}
+
+void *ZSTD_stackAlloc(void *opaque, size_t size)
+{
+ ZSTD_stack *stack = (ZSTD_stack *)opaque;
+ return stack_push(stack, size);
+}
+void ZSTD_stackFree(void *opaque, void *address)
+{
+ (void)opaque;
+ (void)address;
+}
+
+void *ZSTD_malloc(size_t size, ZSTD_customMem customMem) { return customMem.customAlloc(customMem.opaque, size); }
+
+void ZSTD_free(void *ptr, ZSTD_customMem customMem)
+{
+ if (ptr != NULL)
+ customMem.customFree(customMem.opaque, ptr);
+}
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */
+/**
+ * Copyright (c) 2016-present, Yann Collet, Facebook, Inc.
+ * All rights reserved.
+ */
+
+#ifndef ZSTD_CCOMMON_H_MODULE
+#define ZSTD_CCOMMON_H_MODULE
+
+/*-*******************************************************
+* Compiler specifics
+*********************************************************/
+#define FORCE_INLINE static __always_inline
+#define FORCE_NOINLINE static noinline
+
+/*-*************************************
+* Dependencies
+***************************************/
+#include "error_private.h"
+#include "mem.h"
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/xxhash.h>
+#include <linux/zstd.h>
+
+/*-*************************************
+* shared macros
+***************************************/
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define CHECK_F(f) \
+ { \
+ size_t const errcod = f; \
+ if (ERR_isError(errcod)) \
+ return errcod; \
+ } /* check and Forward error code */
+#define CHECK_E(f, e) \
+ { \
+ size_t const errcod = f; \
+ if (ERR_isError(errcod)) \
+ return ERROR(e); \
+ } /* check and send Error code */
+#define ZSTD_STATIC_ASSERT(c) \
+ { \
+ enum { ZSTD_static_assert = 1 / (int)(!!(c)) }; \
+ }
+
+/*-*************************************
+* Common constants
+***************************************/
+#define ZSTD_OPT_NUM (1 << 12)
+#define ZSTD_DICT_MAGIC 0xEC30A437 /* v0.7+ */
+
+#define ZSTD_REP_NUM 3 /* number of repcodes */
+#define ZSTD_REP_CHECK (ZSTD_REP_NUM) /* number of repcodes to check by the optimal parser */
+#define ZSTD_REP_MOVE (ZSTD_REP_NUM - 1)
+#define ZSTD_REP_MOVE_OPT (ZSTD_REP_NUM)
+static const U32 repStartValue[ZSTD_REP_NUM] = {1, 4, 8};
+
+#define KB *(1 << 10)
+#define MB *(1 << 20)
+#define GB *(1U << 30)
+
+#define BIT7 128
+#define BIT6 64
+#define BIT5 32
+#define BIT4 16
+#define BIT1 2
+#define BIT0 1
+
+#define ZSTD_WINDOWLOG_ABSOLUTEMIN 10
+static const size_t ZSTD_fcs_fieldSize[4] = {0, 2, 4, 8};
+static const size_t ZSTD_did_fieldSize[4] = {0, 1, 2, 4};
+
+#define ZSTD_BLOCKHEADERSIZE 3 /* C standard doesn't allow `static const` variable to be init using another `static const` variable */
+static const size_t ZSTD_blockHeaderSize = ZSTD_BLOCKHEADERSIZE;
+typedef enum { bt_raw, bt_rle, bt_compressed, bt_reserved } blockType_e;
+
+#define MIN_SEQUENCES_SIZE 1 /* nbSeq==0 */
+#define MIN_CBLOCK_SIZE (1 /*litCSize*/ + 1 /* RLE or RAW */ + MIN_SEQUENCES_SIZE /* nbSeq==0 */) /* for a non-null block */
+
+#define HufLog 12
+typedef enum { set_basic, set_rle, set_compressed, set_repeat } symbolEncodingType_e;
+
+#define LONGNBSEQ 0x7F00
+
+#define MINMATCH 3
+#define EQUAL_READ32 4
+
+#define Litbits 8
+#define MaxLit ((1 << Litbits) - 1)
+#define MaxML 52
+#define MaxLL 35
+#define MaxOff 28
+#define MaxSeq MAX(MaxLL, MaxML) /* Assumption : MaxOff < MaxLL,MaxML */
+#define MLFSELog 9
+#define LLFSELog 9
+#define OffFSELog 8
+
+static const U32 LL_bits[MaxLL + 1] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+static const S16 LL_defaultNorm[MaxLL + 1] = {4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 2, 1, 1, 1, 1, 1, -1, -1, -1, -1};
+#define LL_DEFAULTNORMLOG 6 /* for static allocation */
+static const U32 LL_defaultNormLog = LL_DEFAULTNORMLOG;
+
+static const U32 ML_bits[MaxML + 1] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+static const S16 ML_defaultNorm[MaxML + 1] = {1, 4, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1};
+#define ML_DEFAULTNORMLOG 6 /* for static allocation */
+static const U32 ML_defaultNormLog = ML_DEFAULTNORMLOG;
+
+static const S16 OF_defaultNorm[MaxOff + 1] = {1, 1, 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1};
+#define OF_DEFAULTNORMLOG 5 /* for static allocation */
+static const U32 OF_defaultNormLog = OF_DEFAULTNORMLOG;
+
+/*-*******************************************
+* Shared functions to include for inlining
+*********************************************/
+ZSTD_STATIC void ZSTD_copy8(void *dst, const void *src) {
+ memcpy(dst, src, 8);
+}
+/*! ZSTD_wildcopy() :
+* custom version of memcpy(), can copy up to 7 bytes too many (8 bytes if length==0) */
+#define WILDCOPY_OVERLENGTH 8
+ZSTD_STATIC void ZSTD_wildcopy(void *dst, const void *src, ptrdiff_t length)
+{
+ const BYTE* ip = (const BYTE*)src;
+ BYTE* op = (BYTE*)dst;
+ BYTE* const oend = op + length;
+ /* Work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81388.
+ * Avoid the bad case where the loop only runs once by handling the
+ * special case separately. This doesn't trigger the bug because it
+ * doesn't involve pointer/integer overflow.
+ */
+ if (length <= 8)
+ return ZSTD_copy8(dst, src);
+ do {
+ ZSTD_copy8(op, ip);
+ op += 8;
+ ip += 8;
+ } while (op < oend);
+}
+
+/*-*******************************************
+* Private interfaces
+*********************************************/
+typedef struct ZSTD_stats_s ZSTD_stats_t;
+
+typedef struct {
+ U32 off;
+ U32 len;
+} ZSTD_match_t;
+
+typedef struct {
+ U32 price;
+ U32 off;
+ U32 mlen;
+ U32 litlen;
+ U32 rep[ZSTD_REP_NUM];
+} ZSTD_optimal_t;
+
+typedef struct seqDef_s {
+ U32 offset;
+ U16 litLength;
+ U16 matchLength;
+} seqDef;
+
+typedef struct {
+ seqDef *sequencesStart;
+ seqDef *sequences;
+ BYTE *litStart;
+ BYTE *lit;
+ BYTE *llCode;
+ BYTE *mlCode;
+ BYTE *ofCode;
+ U32 longLengthID; /* 0 == no longLength; 1 == Lit.longLength; 2 == Match.longLength; */
+ U32 longLengthPos;
+ /* opt */
+ ZSTD_optimal_t *priceTable;
+ ZSTD_match_t *matchTable;
+ U32 *matchLengthFreq;
+ U32 *litLengthFreq;
+ U32 *litFreq;
+ U32 *offCodeFreq;
+ U32 matchLengthSum;
+ U32 matchSum;
+ U32 litLengthSum;
+ U32 litSum;
+ U32 offCodeSum;
+ U32 log2matchLengthSum;
+ U32 log2matchSum;
+ U32 log2litLengthSum;
+ U32 log2litSum;
+ U32 log2offCodeSum;
+ U32 factor;
+ U32 staticPrices;
+ U32 cachedPrice;
+ U32 cachedLitLength;
+ const BYTE *cachedLiterals;
+} seqStore_t;
+
+const seqStore_t *ZSTD_getSeqStore(const ZSTD_CCtx *ctx);
+void ZSTD_seqToCodes(const seqStore_t *seqStorePtr);
+int ZSTD_isSkipFrame(ZSTD_DCtx *dctx);
+
+/*= Custom memory allocation functions */
+typedef void *(*ZSTD_allocFunction)(void *opaque, size_t size);
+typedef void (*ZSTD_freeFunction)(void *opaque, void *address);
+typedef struct {
+ ZSTD_allocFunction customAlloc;
+ ZSTD_freeFunction customFree;
+ void *opaque;
+} ZSTD_customMem;
+
+void *ZSTD_malloc(size_t size, ZSTD_customMem customMem);
+void ZSTD_free(void *ptr, ZSTD_customMem customMem);
+
+/*====== stack allocation ======*/
+
+typedef struct {
+ void *ptr;
+ const void *end;
+} ZSTD_stack;
+
+#define ZSTD_ALIGN(x) ALIGN(x, sizeof(size_t))
+#define ZSTD_PTR_ALIGN(p) PTR_ALIGN(p, sizeof(size_t))
+
+ZSTD_customMem ZSTD_initStack(void *workspace, size_t workspaceSize);
+
+void *ZSTD_stackAllocAll(void *opaque, size_t *size);
+void *ZSTD_stackAlloc(void *opaque, size_t size);
+void ZSTD_stackFree(void *opaque, void *address);
+
+/*====== common function ======*/
+
+ZSTD_STATIC U32 ZSTD_highbit32(U32 val) { return 31 - __builtin_clz(val); }
+
+/* hidden functions */
+
+/* ZSTD_invalidateRepCodes() :
+ * ensures next compression will not use repcodes from previous block.
+ * Note : only works with regular variant;
+ * do not use with extDict variant ! */
+void ZSTD_invalidateRepCodes(ZSTD_CCtx *cctx);
+
+size_t ZSTD_freeCCtx(ZSTD_CCtx *cctx);
+size_t ZSTD_freeDCtx(ZSTD_DCtx *dctx);
+size_t ZSTD_freeCDict(ZSTD_CDict *cdict);
+size_t ZSTD_freeDDict(ZSTD_DDict *cdict);
+size_t ZSTD_freeCStream(ZSTD_CStream *zcs);
+size_t ZSTD_freeDStream(ZSTD_DStream *zds);
+
+#endif /* ZSTD_CCOMMON_H_MODULE */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */
+/**
+ * Copyright (c) 2016-present, Przemyslaw Skibinski, Yann Collet, Facebook, Inc.
+ * All rights reserved.
+ */
+
+/* Note : this file is intended to be included within zstd_compress.c */
+
+#ifndef ZSTD_OPT_H_91842398743
+#define ZSTD_OPT_H_91842398743
+
+#define ZSTD_LITFREQ_ADD 2
+#define ZSTD_FREQ_DIV 4
+#define ZSTD_MAX_PRICE (1 << 30)
+
+/*-*************************************
+* Price functions for optimal parser
+***************************************/
+FORCE_INLINE void ZSTD_setLog2Prices(seqStore_t *ssPtr)
+{
+ ssPtr->log2matchLengthSum = ZSTD_highbit32(ssPtr->matchLengthSum + 1);
+ ssPtr->log2litLengthSum = ZSTD_highbit32(ssPtr->litLengthSum + 1);
+ ssPtr->log2litSum = ZSTD_highbit32(ssPtr->litSum + 1);
+ ssPtr->log2offCodeSum = ZSTD_highbit32(ssPtr->offCodeSum + 1);
+ ssPtr->factor = 1 + ((ssPtr->litSum >> 5) / ssPtr->litLengthSum) + ((ssPtr->litSum << 1) / (ssPtr->litSum + ssPtr->matchSum));
+}
+
+ZSTD_STATIC void ZSTD_rescaleFreqs(seqStore_t *ssPtr, const BYTE *src, size_t srcSize)
+{
+ unsigned u;
+
+ ssPtr->cachedLiterals = NULL;
+ ssPtr->cachedPrice = ssPtr->cachedLitLength = 0;
+ ssPtr->staticPrices = 0;
+
+ if (ssPtr->litLengthSum == 0) {
+ if (srcSize <= 1024)
+ ssPtr->staticPrices = 1;
+
+ for (u = 0; u <= MaxLit; u++)
+ ssPtr->litFreq[u] = 0;
+ for (u = 0; u < srcSize; u++)
+ ssPtr->litFreq[src[u]]++;
+
+ ssPtr->litSum = 0;
+ ssPtr->litLengthSum = MaxLL + 1;
+ ssPtr->matchLengthSum = MaxML + 1;
+ ssPtr->offCodeSum = (MaxOff + 1);
+ ssPtr->matchSum = (ZSTD_LITFREQ_ADD << Litbits);
+
+ for (u = 0; u <= MaxLit; u++) {
+ ssPtr->litFreq[u] = 1 + (ssPtr->litFreq[u] >> ZSTD_FREQ_DIV);
+ ssPtr->litSum += ssPtr->litFreq[u];
+ }
+ for (u = 0; u <= MaxLL; u++)
+ ssPtr->litLengthFreq[u] = 1;
+ for (u = 0; u <= MaxML; u++)
+ ssPtr->matchLengthFreq[u] = 1;
+ for (u = 0; u <= MaxOff; u++)
+ ssPtr->offCodeFreq[u] = 1;
+ } else {
+ ssPtr->matchLengthSum = 0;
+ ssPtr->litLengthSum = 0;
+ ssPtr->offCodeSum = 0;
+ ssPtr->matchSum = 0;
+ ssPtr->litSum = 0;
+
+ for (u = 0; u <= MaxLit; u++) {
+ ssPtr->litFreq[u] = 1 + (ssPtr->litFreq[u] >> (ZSTD_FREQ_DIV + 1));
+ ssPtr->litSum += ssPtr->litFreq[u];
+ }
+ for (u = 0; u <= MaxLL; u++) {
+ ssPtr->litLengthFreq[u] = 1 + (ssPtr->litLengthFreq[u] >> (ZSTD_FREQ_DIV + 1));
+ ssPtr->litLengthSum += ssPtr->litLengthFreq[u];
+ }
+ for (u = 0; u <= MaxML; u++) {
+ ssPtr->matchLengthFreq[u] = 1 + (ssPtr->matchLengthFreq[u] >> ZSTD_FREQ_DIV);
+ ssPtr->matchLengthSum += ssPtr->matchLengthFreq[u];
+ ssPtr->matchSum += ssPtr->matchLengthFreq[u] * (u + 3);
+ }
+ ssPtr->matchSum *= ZSTD_LITFREQ_ADD;
+ for (u = 0; u <= MaxOff; u++) {
+ ssPtr->offCodeFreq[u] = 1 + (ssPtr->offCodeFreq[u] >> ZSTD_FREQ_DIV);
+ ssPtr->offCodeSum += ssPtr->offCodeFreq[u];
+ }
+ }
+
+ ZSTD_setLog2Prices(ssPtr);
+}
+
+FORCE_INLINE U32 ZSTD_getLiteralPrice(seqStore_t *ssPtr, U32 litLength, const BYTE *literals)
+{
+ U32 price, u;
+
+ if (ssPtr->staticPrices)
+ return ZSTD_highbit32((U32)litLength + 1) + (litLength * 6);
+
+ if (litLength == 0)
+ return ssPtr->log2litLengthSum - ZSTD_highbit32(ssPtr->litLengthFreq[0] + 1);
+
+ /* literals */
+ if (ssPtr->cachedLiterals == literals) {
+ U32 const additional = litLength - ssPtr->cachedLitLength;
+ const BYTE *literals2 = ssPtr->cachedLiterals + ssPtr->cachedLitLength;
+ price = ssPtr->cachedPrice + additional * ssPtr->log2litSum;
+ for (u = 0; u < additional; u++)
+ price -= ZSTD_highbit32(ssPtr->litFreq[literals2[u]] + 1);
+ ssPtr->cachedPrice = price;
+ ssPtr->cachedLitLength = litLength;
+ } else {
+ price = litLength * ssPtr->log2litSum;
+ for (u = 0; u < litLength; u++)
+ price -= ZSTD_highbit32(ssPtr->litFreq[literals[u]] + 1);
+
+ if (litLength >= 12) {
+ ssPtr->cachedLiterals = literals;
+ ssPtr->cachedPrice = price;
+ ssPtr->cachedLitLength = litLength;
+ }
+ }
+
+ /* literal Length */
+ {
+ const BYTE LL_deltaCode = 19;
+ const BYTE llCode = (litLength > 63) ? (BYTE)ZSTD_highbit32(litLength) + LL_deltaCode : LL_Code[litLength];
+ price += LL_bits[llCode] + ssPtr->log2litLengthSum - ZSTD_highbit32(ssPtr->litLengthFreq[llCode] + 1);
+ }
+
+ return price;
+}
+
+FORCE_INLINE U32 ZSTD_getPrice(seqStore_t *seqStorePtr, U32 litLength, const BYTE *literals, U32 offset, U32 matchLength, const int ultra)
+{
+ /* offset */
+ U32 price;
+ BYTE const offCode = (BYTE)ZSTD_highbit32(offset + 1);
+
+ if (seqStorePtr->staticPrices)
+ return ZSTD_getLiteralPrice(seqStorePtr, litLength, literals) + ZSTD_highbit32((U32)matchLength + 1) + 16 + offCode;
+
+ price = offCode + seqStorePtr->log2offCodeSum - ZSTD_highbit32(seqStorePtr->offCodeFreq[offCode] + 1);
+ if (!ultra && offCode >= 20)
+ price += (offCode - 19) * 2;
+
+ /* match Length */
+ {
+ const BYTE ML_deltaCode = 36;
+ const BYTE mlCode = (matchLength > 127) ? (BYTE)ZSTD_highbit32(matchLength) + ML_deltaCode : ML_Code[matchLength];
+ price += ML_bits[mlCode] + seqStorePtr->log2matchLengthSum - ZSTD_highbit32(seqStorePtr->matchLengthFreq[mlCode] + 1);
+ }
+
+ return price + ZSTD_getLiteralPrice(seqStorePtr, litLength, literals) + seqStorePtr->factor;
+}
+
+ZSTD_STATIC void ZSTD_updatePrice(seqStore_t *seqStorePtr, U32 litLength, const BYTE *literals, U32 offset, U32 matchLength)
+{
+ U32 u;
+
+ /* literals */
+ seqStorePtr->litSum += litLength * ZSTD_LITFREQ_ADD;
+ for (u = 0; u < litLength; u++)
+ seqStorePtr->litFreq[literals[u]] += ZSTD_LITFREQ_ADD;
+
+ /* literal Length */
+ {
+ const BYTE LL_deltaCode = 19;
+ const BYTE llCode = (litLength > 63) ? (BYTE)ZSTD_highbit32(litLength) + LL_deltaCode : LL_Code[litLength];
+ seqStorePtr->litLengthFreq[llCode]++;
+ seqStorePtr->litLengthSum++;
+ }
+
+ /* match offset */
+ {
+ BYTE const offCode = (BYTE)ZSTD_highbit32(offset + 1);
+ seqStorePtr->offCodeSum++;
+ seqStorePtr->offCodeFreq[offCode]++;
+ }
+
+ /* match Length */
+ {
+ const BYTE ML_deltaCode = 36;
+ const BYTE mlCode = (matchLength > 127) ? (BYTE)ZSTD_highbit32(matchLength) + ML_deltaCode : ML_Code[matchLength];
+ seqStorePtr->matchLengthFreq[mlCode]++;
+ seqStorePtr->matchLengthSum++;
+ }
+
+ ZSTD_setLog2Prices(seqStorePtr);
+}
+
+#define SET_PRICE(pos, mlen_, offset_, litlen_, price_) \
+ { \
+ while (last_pos < pos) { \
+ opt[last_pos + 1].price = ZSTD_MAX_PRICE; \
+ last_pos++; \
+ } \
+ opt[pos].mlen = mlen_; \
+ opt[pos].off = offset_; \
+ opt[pos].litlen = litlen_; \
+ opt[pos].price = price_; \
+ }
+
+/* Update hashTable3 up to ip (excluded)
+ Assumption : always within prefix (i.e. not within extDict) */
+FORCE_INLINE
+U32 ZSTD_insertAndFindFirstIndexHash3(ZSTD_CCtx *zc, const BYTE *ip)
+{
+ U32 *const hashTable3 = zc->hashTable3;
+ U32 const hashLog3 = zc->hashLog3;
+ const BYTE *const base = zc->base;
+ U32 idx = zc->nextToUpdate3;
+ const U32 target = zc->nextToUpdate3 = (U32)(ip - base);
+ const size_t hash3 = ZSTD_hash3Ptr(ip, hashLog3);
+
+ while (idx < target) {
+ hashTable3[ZSTD_hash3Ptr(base + idx, hashLog3)] = idx;
+ idx++;
+ }
+
+ return hashTable3[hash3];
+}
+
+/*-*************************************
+* Binary Tree search
+***************************************/
+static U32 ZSTD_insertBtAndGetAllMatches(ZSTD_CCtx *zc, const BYTE *const ip, const BYTE *const iLimit, U32 nbCompares, const U32 mls, U32 extDict,
+ ZSTD_match_t *matches, const U32 minMatchLen)
+{
+ const BYTE *const base = zc->base;
+ const U32 curr = (U32)(ip - base);
+ const U32 hashLog = zc->params.cParams.hashLog;
+ const size_t h = ZSTD_hashPtr(ip, hashLog, mls);
+ U32 *const hashTable = zc->hashTable;
+ U32 matchIndex = hashTable[h];
+ U32 *const bt = zc->chainTable;
+ const U32 btLog = zc->params.cParams.chainLog - 1;
+ const U32 btMask = (1U << btLog) - 1;
+ size_t commonLengthSmaller = 0, commonLengthLarger = 0;
+ const BYTE *const dictBase = zc->dictBase;
+ const U32 dictLimit = zc->dictLimit;
+ const BYTE *const dictEnd = dictBase + dictLimit;
+ const BYTE *const prefixStart = base + dictLimit;
+ const U32 btLow = btMask >= curr ? 0 : curr - btMask;
+ const U32 windowLow = zc->lowLimit;
+ U32 *smallerPtr = bt + 2 * (curr & btMask);
+ U32 *largerPtr = bt + 2 * (curr & btMask) + 1;
+ U32 matchEndIdx = curr + 8;
+ U32 dummy32; /* to be nullified at the end */
+ U32 mnum = 0;
+
+ const U32 minMatch = (mls == 3) ? 3 : 4;
+ size_t bestLength = minMatchLen - 1;
+
+ if (minMatch == 3) { /* HC3 match finder */
+ U32 const matchIndex3 = ZSTD_insertAndFindFirstIndexHash3(zc, ip);
+ if (matchIndex3 > windowLow && (curr - matchIndex3 < (1 << 18))) {
+ const BYTE *match;
+ size_t currMl = 0;
+ if ((!extDict) || matchIndex3 >= dictLimit) {
+ match = base + matchIndex3;
+ if (match[bestLength] == ip[bestLength])
+ currMl = ZSTD_count(ip, match, iLimit);
+ } else {
+ match = dictBase + matchIndex3;
+ if (ZSTD_readMINMATCH(match, MINMATCH) ==
+ ZSTD_readMINMATCH(ip, MINMATCH)) /* assumption : matchIndex3 <= dictLimit-4 (by table construction) */
+ currMl = ZSTD_count_2segments(ip + MINMATCH, match + MINMATCH, iLimit, dictEnd, prefixStart) + MINMATCH;
+ }
+
+ /* save best solution */
+ if (currMl > bestLength) {
+ bestLength = currMl;
+ matches[mnum].off = ZSTD_REP_MOVE_OPT + curr - matchIndex3;
+ matches[mnum].len = (U32)currMl;
+ mnum++;
+ if (currMl > ZSTD_OPT_NUM)
+ goto update;
+ if (ip + currMl == iLimit)
+ goto update; /* best possible, and avoid read overflow*/
+ }
+ }
+ }
+
+ hashTable[h] = curr; /* Update Hash Table */
+
+ while (nbCompares-- && (matchIndex > windowLow)) {
+ U32 *nextPtr = bt + 2 * (matchIndex & btMask);
+ size_t matchLength = MIN(commonLengthSmaller, commonLengthLarger); /* guaranteed minimum nb of common bytes */
+ const BYTE *match;
+
+ if ((!extDict) || (matchIndex + matchLength >= dictLimit)) {
+ match = base + matchIndex;
+ if (match[matchLength] == ip[matchLength]) {
+ matchLength += ZSTD_count(ip + matchLength + 1, match + matchLength + 1, iLimit) + 1;
+ }
+ } else {
+ match = dictBase + matchIndex;
+ matchLength += ZSTD_count_2segments(ip + matchLength, match + matchLength, iLimit, dictEnd, prefixStart);
+ if (matchIndex + matchLength >= dictLimit)
+ match = base + matchIndex; /* to prepare for next usage of match[matchLength] */
+ }
+
+ if (matchLength > bestLength) {
+ if (matchLength > matchEndIdx - matchIndex)
+ matchEndIdx = matchIndex + (U32)matchLength;
+ bestLength = matchLength;
+ matches[mnum].off = ZSTD_REP_MOVE_OPT + curr - matchIndex;
+ matches[mnum].len = (U32)matchLength;
+ mnum++;
+ if (matchLength > ZSTD_OPT_NUM)
+ break;
+ if (ip + matchLength == iLimit) /* equal : no way to know if inf or sup */
+ break; /* drop, to guarantee consistency (miss a little bit of compression) */
+ }
+
+ if (match[matchLength] < ip[matchLength]) {
+ /* match is smaller than curr */
+ *smallerPtr = matchIndex; /* update smaller idx */
+ commonLengthSmaller = matchLength; /* all smaller will now have at least this guaranteed common length */
+ if (matchIndex <= btLow) {
+ smallerPtr = &dummy32;
+ break;
+ } /* beyond tree size, stop the search */
+ smallerPtr = nextPtr + 1; /* new "smaller" => larger of match */
+ matchIndex = nextPtr[1]; /* new matchIndex larger than previous (closer to curr) */
+ } else {
+ /* match is larger than curr */
+ *largerPtr = matchIndex;
+ commonLengthLarger = matchLength;
+ if (matchIndex <= btLow) {
+ largerPtr = &dummy32;
+ break;
+ } /* beyond tree size, stop the search */
+ largerPtr = nextPtr;
+ matchIndex = nextPtr[0];
+ }
+ }
+
+ *smallerPtr = *largerPtr = 0;
+
+update:
+ zc->nextToUpdate = (matchEndIdx > curr + 8) ? matchEndIdx - 8 : curr + 1;
+ return mnum;
+}
+
+/** Tree updater, providing best match */
+static U32 ZSTD_BtGetAllMatches(ZSTD_CCtx *zc, const BYTE *const ip, const BYTE *const iLimit, const U32 maxNbAttempts, const U32 mls, ZSTD_match_t *matches,
+ const U32 minMatchLen)
+{
+ if (ip < zc->base + zc->nextToUpdate)
+ return 0; /* skipped area */
+ ZSTD_updateTree(zc, ip, iLimit, maxNbAttempts, mls);
+ return ZSTD_insertBtAndGetAllMatches(zc, ip, iLimit, maxNbAttempts, mls, 0, matches, minMatchLen);
+}
+
+static U32 ZSTD_BtGetAllMatches_selectMLS(ZSTD_CCtx *zc, /* Index table will be updated */
+ const BYTE *ip, const BYTE *const iHighLimit, const U32 maxNbAttempts, const U32 matchLengthSearch,
+ ZSTD_match_t *matches, const U32 minMatchLen)
+{
+ switch (matchLengthSearch) {
+ case 3: return ZSTD_BtGetAllMatches(zc, ip, iHighLimit, maxNbAttempts, 3, matches, minMatchLen);
+ default:
+ case 4: return ZSTD_BtGetAllMatches(zc, ip, iHighLimit, maxNbAttempts, 4, matches, minMatchLen);
+ case 5: return ZSTD_BtGetAllMatches(zc, ip, iHighLimit, maxNbAttempts, 5, matches, minMatchLen);
+ case 7:
+ case 6: return ZSTD_BtGetAllMatches(zc, ip, iHighLimit, maxNbAttempts, 6, matches, minMatchLen);
+ }
+}
+
+/** Tree updater, providing best match */
+static U32 ZSTD_BtGetAllMatches_extDict(ZSTD_CCtx *zc, const BYTE *const ip, const BYTE *const iLimit, const U32 maxNbAttempts, const U32 mls,
+ ZSTD_match_t *matches, const U32 minMatchLen)
+{
+ if (ip < zc->base + zc->nextToUpdate)
+ return 0; /* skipped area */
+ ZSTD_updateTree_extDict(zc, ip, iLimit, maxNbAttempts, mls);
+ return ZSTD_insertBtAndGetAllMatches(zc, ip, iLimit, maxNbAttempts, mls, 1, matches, minMatchLen);
+}
+
+static U32 ZSTD_BtGetAllMatches_selectMLS_extDict(ZSTD_CCtx *zc, /* Index table will be updated */
+ const BYTE *ip, const BYTE *const iHighLimit, const U32 maxNbAttempts, const U32 matchLengthSearch,
+ ZSTD_match_t *matches, const U32 minMatchLen)
+{
+ switch (matchLengthSearch) {
+ case 3: return ZSTD_BtGetAllMatches_extDict(zc, ip, iHighLimit, maxNbAttempts, 3, matches, minMatchLen);
+ default:
+ case 4: return ZSTD_BtGetAllMatches_extDict(zc, ip, iHighLimit, maxNbAttempts, 4, matches, minMatchLen);
+ case 5: return ZSTD_BtGetAllMatches_extDict(zc, ip, iHighLimit, maxNbAttempts, 5, matches, minMatchLen);
+ case 7:
+ case 6: return ZSTD_BtGetAllMatches_extDict(zc, ip, iHighLimit, maxNbAttempts, 6, matches, minMatchLen);
+ }
+}
+
+/*-*******************************
+* Optimal parser
+*********************************/
+FORCE_INLINE
+void ZSTD_compressBlock_opt_generic(ZSTD_CCtx *ctx, const void *src, size_t srcSize, const int ultra)
+{
+ seqStore_t *seqStorePtr = &(ctx->seqStore);
+ const BYTE *const istart = (const BYTE *)src;
+ const BYTE *ip = istart;
+ const BYTE *anchor = istart;
+ const BYTE *const iend = istart + srcSize;
+ const BYTE *const ilimit = iend - 8;
+ const BYTE *const base = ctx->base;
+ const BYTE *const prefixStart = base + ctx->dictLimit;
+
+ const U32 maxSearches = 1U << ctx->params.cParams.searchLog;
+ const U32 sufficient_len = ctx->params.cParams.targetLength;
+ const U32 mls = ctx->params.cParams.searchLength;
+ const U32 minMatch = (ctx->params.cParams.searchLength == 3) ? 3 : 4;
+
+ ZSTD_optimal_t *opt = seqStorePtr->priceTable;
+ ZSTD_match_t *matches = seqStorePtr->matchTable;
+ const BYTE *inr;
+ U32 offset, rep[ZSTD_REP_NUM];
+
+ /* init */
+ ctx->nextToUpdate3 = ctx->nextToUpdate;
+ ZSTD_rescaleFreqs(seqStorePtr, (const BYTE *)src, srcSize);
+ ip += (ip == prefixStart);
+ {
+ U32 i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ rep[i] = ctx->rep[i];
+ }
+
+ /* Match Loop */
+ while (ip < ilimit) {
+ U32 cur, match_num, last_pos, litlen, price;
+ U32 u, mlen, best_mlen, best_off, litLength;
+ memset(opt, 0, sizeof(ZSTD_optimal_t));
+ last_pos = 0;
+ litlen = (U32)(ip - anchor);
+
+ /* check repCode */
+ {
+ U32 i, last_i = ZSTD_REP_CHECK + (ip == anchor);
+ for (i = (ip == anchor); i < last_i; i++) {
+ const S32 repCur = (i == ZSTD_REP_MOVE_OPT) ? (rep[0] - 1) : rep[i];
+ if ((repCur > 0) && (repCur < (S32)(ip - prefixStart)) &&
+ (ZSTD_readMINMATCH(ip, minMatch) == ZSTD_readMINMATCH(ip - repCur, minMatch))) {
+ mlen = (U32)ZSTD_count(ip + minMatch, ip + minMatch - repCur, iend) + minMatch;
+ if (mlen > sufficient_len || mlen >= ZSTD_OPT_NUM) {
+ best_mlen = mlen;
+ best_off = i;
+ cur = 0;
+ last_pos = 1;
+ goto _storeSequence;
+ }
+ best_off = i - (ip == anchor);
+ do {
+ price = ZSTD_getPrice(seqStorePtr, litlen, anchor, best_off, mlen - MINMATCH, ultra);
+ if (mlen > last_pos || price < opt[mlen].price)
+ SET_PRICE(mlen, mlen, i, litlen, price); /* note : macro modifies last_pos */
+ mlen--;
+ } while (mlen >= minMatch);
+ }
+ }
+ }
+
+ match_num = ZSTD_BtGetAllMatches_selectMLS(ctx, ip, iend, maxSearches, mls, matches, minMatch);
+
+ if (!last_pos && !match_num) {
+ ip++;
+ continue;
+ }
+
+ if (match_num && (matches[match_num - 1].len > sufficient_len || matches[match_num - 1].len >= ZSTD_OPT_NUM)) {
+ best_mlen = matches[match_num - 1].len;
+ best_off = matches[match_num - 1].off;
+ cur = 0;
+ last_pos = 1;
+ goto _storeSequence;
+ }
+
+ /* set prices using matches at position = 0 */
+ best_mlen = (last_pos) ? last_pos : minMatch;
+ for (u = 0; u < match_num; u++) {
+ mlen = (u > 0) ? matches[u - 1].len + 1 : best_mlen;
+ best_mlen = matches[u].len;
+ while (mlen <= best_mlen) {
+ price = ZSTD_getPrice(seqStorePtr, litlen, anchor, matches[u].off - 1, mlen - MINMATCH, ultra);
+ if (mlen > last_pos || price < opt[mlen].price)
+ SET_PRICE(mlen, mlen, matches[u].off, litlen, price); /* note : macro modifies last_pos */
+ mlen++;
+ }
+ }
+
+ if (last_pos < minMatch) {
+ ip++;
+ continue;
+ }
+
+ /* initialize opt[0] */
+ {
+ U32 i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ opt[0].rep[i] = rep[i];
+ }
+ opt[0].mlen = 1;
+ opt[0].litlen = litlen;
+
+ /* check further positions */
+ for (cur = 1; cur <= last_pos; cur++) {
+ inr = ip + cur;
+
+ if (opt[cur - 1].mlen == 1) {
+ litlen = opt[cur - 1].litlen + 1;
+ if (cur > litlen) {
+ price = opt[cur - litlen].price + ZSTD_getLiteralPrice(seqStorePtr, litlen, inr - litlen);
+ } else
+ price = ZSTD_getLiteralPrice(seqStorePtr, litlen, anchor);
+ } else {
+ litlen = 1;
+ price = opt[cur - 1].price + ZSTD_getLiteralPrice(seqStorePtr, litlen, inr - 1);
+ }
+
+ if (cur > last_pos || price <= opt[cur].price)
+ SET_PRICE(cur, 1, 0, litlen, price);
+
+ if (cur == last_pos)
+ break;
+
+ if (inr > ilimit) /* last match must start at a minimum distance of 8 from oend */
+ continue;
+
+ mlen = opt[cur].mlen;
+ if (opt[cur].off > ZSTD_REP_MOVE_OPT) {
+ opt[cur].rep[2] = opt[cur - mlen].rep[1];
+ opt[cur].rep[1] = opt[cur - mlen].rep[0];
+ opt[cur].rep[0] = opt[cur].off - ZSTD_REP_MOVE_OPT;
+ } else {
+ opt[cur].rep[2] = (opt[cur].off > 1) ? opt[cur - mlen].rep[1] : opt[cur - mlen].rep[2];
+ opt[cur].rep[1] = (opt[cur].off > 0) ? opt[cur - mlen].rep[0] : opt[cur - mlen].rep[1];
+ opt[cur].rep[0] =
+ ((opt[cur].off == ZSTD_REP_MOVE_OPT) && (mlen != 1)) ? (opt[cur - mlen].rep[0] - 1) : (opt[cur - mlen].rep[opt[cur].off]);
+ }
+
+ best_mlen = minMatch;
+ {
+ U32 i, last_i = ZSTD_REP_CHECK + (mlen != 1);
+ for (i = (opt[cur].mlen != 1); i < last_i; i++) { /* check rep */
+ const S32 repCur = (i == ZSTD_REP_MOVE_OPT) ? (opt[cur].rep[0] - 1) : opt[cur].rep[i];
+ if ((repCur > 0) && (repCur < (S32)(inr - prefixStart)) &&
+ (ZSTD_readMINMATCH(inr, minMatch) == ZSTD_readMINMATCH(inr - repCur, minMatch))) {
+ mlen = (U32)ZSTD_count(inr + minMatch, inr + minMatch - repCur, iend) + minMatch;
+
+ if (mlen > sufficient_len || cur + mlen >= ZSTD_OPT_NUM) {
+ best_mlen = mlen;
+ best_off = i;
+ last_pos = cur + 1;
+ goto _storeSequence;
+ }
+
+ best_off = i - (opt[cur].mlen != 1);
+ if (mlen > best_mlen)
+ best_mlen = mlen;
+
+ do {
+ if (opt[cur].mlen == 1) {
+ litlen = opt[cur].litlen;
+ if (cur > litlen) {
+ price = opt[cur - litlen].price + ZSTD_getPrice(seqStorePtr, litlen, inr - litlen,
+ best_off, mlen - MINMATCH, ultra);
+ } else
+ price = ZSTD_getPrice(seqStorePtr, litlen, anchor, best_off, mlen - MINMATCH, ultra);
+ } else {
+ litlen = 0;
+ price = opt[cur].price + ZSTD_getPrice(seqStorePtr, 0, NULL, best_off, mlen - MINMATCH, ultra);
+ }
+
+ if (cur + mlen > last_pos || price <= opt[cur + mlen].price)
+ SET_PRICE(cur + mlen, mlen, i, litlen, price);
+ mlen--;
+ } while (mlen >= minMatch);
+ }
+ }
+ }
+
+ match_num = ZSTD_BtGetAllMatches_selectMLS(ctx, inr, iend, maxSearches, mls, matches, best_mlen);
+
+ if (match_num > 0 && (matches[match_num - 1].len > sufficient_len || cur + matches[match_num - 1].len >= ZSTD_OPT_NUM)) {
+ best_mlen = matches[match_num - 1].len;
+ best_off = matches[match_num - 1].off;
+ last_pos = cur + 1;
+ goto _storeSequence;
+ }
+
+ /* set prices using matches at position = cur */
+ for (u = 0; u < match_num; u++) {
+ mlen = (u > 0) ? matches[u - 1].len + 1 : best_mlen;
+ best_mlen = matches[u].len;
+
+ while (mlen <= best_mlen) {
+ if (opt[cur].mlen == 1) {
+ litlen = opt[cur].litlen;
+ if (cur > litlen)
+ price = opt[cur - litlen].price + ZSTD_getPrice(seqStorePtr, litlen, ip + cur - litlen,
+ matches[u].off - 1, mlen - MINMATCH, ultra);
+ else
+ price = ZSTD_getPrice(seqStorePtr, litlen, anchor, matches[u].off - 1, mlen - MINMATCH, ultra);
+ } else {
+ litlen = 0;
+ price = opt[cur].price + ZSTD_getPrice(seqStorePtr, 0, NULL, matches[u].off - 1, mlen - MINMATCH, ultra);
+ }
+
+ if (cur + mlen > last_pos || (price < opt[cur + mlen].price))
+ SET_PRICE(cur + mlen, mlen, matches[u].off, litlen, price);
+
+ mlen++;
+ }
+ }
+ }
+
+ best_mlen = opt[last_pos].mlen;
+ best_off = opt[last_pos].off;
+ cur = last_pos - best_mlen;
+
+ /* store sequence */
+_storeSequence: /* cur, last_pos, best_mlen, best_off have to be set */
+ opt[0].mlen = 1;
+
+ while (1) {
+ mlen = opt[cur].mlen;
+ offset = opt[cur].off;
+ opt[cur].mlen = best_mlen;
+ opt[cur].off = best_off;
+ best_mlen = mlen;
+ best_off = offset;
+ if (mlen > cur)
+ break;
+ cur -= mlen;
+ }
+
+ for (u = 0; u <= last_pos;) {
+ u += opt[u].mlen;
+ }
+
+ for (cur = 0; cur < last_pos;) {
+ mlen = opt[cur].mlen;
+ if (mlen == 1) {
+ ip++;
+ cur++;
+ continue;
+ }
+ offset = opt[cur].off;
+ cur += mlen;
+ litLength = (U32)(ip - anchor);
+
+ if (offset > ZSTD_REP_MOVE_OPT) {
+ rep[2] = rep[1];
+ rep[1] = rep[0];
+ rep[0] = offset - ZSTD_REP_MOVE_OPT;
+ offset--;
+ } else {
+ if (offset != 0) {
+ best_off = (offset == ZSTD_REP_MOVE_OPT) ? (rep[0] - 1) : (rep[offset]);
+ if (offset != 1)
+ rep[2] = rep[1];
+ rep[1] = rep[0];
+ rep[0] = best_off;
+ }
+ if (litLength == 0)
+ offset--;
+ }
+
+ ZSTD_updatePrice(seqStorePtr, litLength, anchor, offset, mlen - MINMATCH);
+ ZSTD_storeSeq(seqStorePtr, litLength, anchor, offset, mlen - MINMATCH);
+ anchor = ip = ip + mlen;
+ }
+ } /* for (cur=0; cur < last_pos; ) */
+
+ /* Save reps for next block */
+ {
+ int i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ ctx->repToConfirm[i] = rep[i];
+ }
+
+ /* Last Literals */
+ {
+ size_t const lastLLSize = iend - anchor;
+ memcpy(seqStorePtr->lit, anchor, lastLLSize);
+ seqStorePtr->lit += lastLLSize;
+ }
+}
+
+FORCE_INLINE
+void ZSTD_compressBlock_opt_extDict_generic(ZSTD_CCtx *ctx, const void *src, size_t srcSize, const int ultra)
+{
+ seqStore_t *seqStorePtr = &(ctx->seqStore);
+ const BYTE *const istart = (const BYTE *)src;
+ const BYTE *ip = istart;
+ const BYTE *anchor = istart;
+ const BYTE *const iend = istart + srcSize;
+ const BYTE *const ilimit = iend - 8;
+ const BYTE *const base = ctx->base;
+ const U32 lowestIndex = ctx->lowLimit;
+ const U32 dictLimit = ctx->dictLimit;
+ const BYTE *const prefixStart = base + dictLimit;
+ const BYTE *const dictBase = ctx->dictBase;
+ const BYTE *const dictEnd = dictBase + dictLimit;
+
+ const U32 maxSearches = 1U << ctx->params.cParams.searchLog;
+ const U32 sufficient_len = ctx->params.cParams.targetLength;
+ const U32 mls = ctx->params.cParams.searchLength;
+ const U32 minMatch = (ctx->params.cParams.searchLength == 3) ? 3 : 4;
+
+ ZSTD_optimal_t *opt = seqStorePtr->priceTable;
+ ZSTD_match_t *matches = seqStorePtr->matchTable;
+ const BYTE *inr;
+
+ /* init */
+ U32 offset, rep[ZSTD_REP_NUM];
+ {
+ U32 i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ rep[i] = ctx->rep[i];
+ }
+
+ ctx->nextToUpdate3 = ctx->nextToUpdate;
+ ZSTD_rescaleFreqs(seqStorePtr, (const BYTE *)src, srcSize);
+ ip += (ip == prefixStart);
+
+ /* Match Loop */
+ while (ip < ilimit) {
+ U32 cur, match_num, last_pos, litlen, price;
+ U32 u, mlen, best_mlen, best_off, litLength;
+ U32 curr = (U32)(ip - base);
+ memset(opt, 0, sizeof(ZSTD_optimal_t));
+ last_pos = 0;
+ opt[0].litlen = (U32)(ip - anchor);
+
+ /* check repCode */
+ {
+ U32 i, last_i = ZSTD_REP_CHECK + (ip == anchor);
+ for (i = (ip == anchor); i < last_i; i++) {
+ const S32 repCur = (i == ZSTD_REP_MOVE_OPT) ? (rep[0] - 1) : rep[i];
+ const U32 repIndex = (U32)(curr - repCur);
+ const BYTE *const repBase = repIndex < dictLimit ? dictBase : base;
+ const BYTE *const repMatch = repBase + repIndex;
+ if ((repCur > 0 && repCur <= (S32)curr) &&
+ (((U32)((dictLimit - 1) - repIndex) >= 3) & (repIndex > lowestIndex)) /* intentional overflow */
+ && (ZSTD_readMINMATCH(ip, minMatch) == ZSTD_readMINMATCH(repMatch, minMatch))) {
+ /* repcode detected we should take it */
+ const BYTE *const repEnd = repIndex < dictLimit ? dictEnd : iend;
+ mlen = (U32)ZSTD_count_2segments(ip + minMatch, repMatch + minMatch, iend, repEnd, prefixStart) + minMatch;
+
+ if (mlen > sufficient_len || mlen >= ZSTD_OPT_NUM) {
+ best_mlen = mlen;
+ best_off = i;
+ cur = 0;
+ last_pos = 1;
+ goto _storeSequence;
+ }
+
+ best_off = i - (ip == anchor);
+ litlen = opt[0].litlen;
+ do {
+ price = ZSTD_getPrice(seqStorePtr, litlen, anchor, best_off, mlen - MINMATCH, ultra);
+ if (mlen > last_pos || price < opt[mlen].price)
+ SET_PRICE(mlen, mlen, i, litlen, price); /* note : macro modifies last_pos */
+ mlen--;
+ } while (mlen >= minMatch);
+ }
+ }
+ }
+
+ match_num = ZSTD_BtGetAllMatches_selectMLS_extDict(ctx, ip, iend, maxSearches, mls, matches, minMatch); /* first search (depth 0) */
+
+ if (!last_pos && !match_num) {
+ ip++;
+ continue;
+ }
+
+ {
+ U32 i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ opt[0].rep[i] = rep[i];
+ }
+ opt[0].mlen = 1;
+
+ if (match_num && (matches[match_num - 1].len > sufficient_len || matches[match_num - 1].len >= ZSTD_OPT_NUM)) {
+ best_mlen = matches[match_num - 1].len;
+ best_off = matches[match_num - 1].off;
+ cur = 0;
+ last_pos = 1;
+ goto _storeSequence;
+ }
+
+ best_mlen = (last_pos) ? last_pos : minMatch;
+
+ /* set prices using matches at position = 0 */
+ for (u = 0; u < match_num; u++) {
+ mlen = (u > 0) ? matches[u - 1].len + 1 : best_mlen;
+ best_mlen = matches[u].len;
+ litlen = opt[0].litlen;
+ while (mlen <= best_mlen) {
+ price = ZSTD_getPrice(seqStorePtr, litlen, anchor, matches[u].off - 1, mlen - MINMATCH, ultra);
+ if (mlen > last_pos || price < opt[mlen].price)
+ SET_PRICE(mlen, mlen, matches[u].off, litlen, price);
+ mlen++;
+ }
+ }
+
+ if (last_pos < minMatch) {
+ ip++;
+ continue;
+ }
+
+ /* check further positions */
+ for (cur = 1; cur <= last_pos; cur++) {
+ inr = ip + cur;
+
+ if (opt[cur - 1].mlen == 1) {
+ litlen = opt[cur - 1].litlen + 1;
+ if (cur > litlen) {
+ price = opt[cur - litlen].price + ZSTD_getLiteralPrice(seqStorePtr, litlen, inr - litlen);
+ } else
+ price = ZSTD_getLiteralPrice(seqStorePtr, litlen, anchor);
+ } else {
+ litlen = 1;
+ price = opt[cur - 1].price + ZSTD_getLiteralPrice(seqStorePtr, litlen, inr - 1);
+ }
+
+ if (cur > last_pos || price <= opt[cur].price)
+ SET_PRICE(cur, 1, 0, litlen, price);
+
+ if (cur == last_pos)
+ break;
+
+ if (inr > ilimit) /* last match must start at a minimum distance of 8 from oend */
+ continue;
+
+ mlen = opt[cur].mlen;
+ if (opt[cur].off > ZSTD_REP_MOVE_OPT) {
+ opt[cur].rep[2] = opt[cur - mlen].rep[1];
+ opt[cur].rep[1] = opt[cur - mlen].rep[0];
+ opt[cur].rep[0] = opt[cur].off - ZSTD_REP_MOVE_OPT;
+ } else {
+ opt[cur].rep[2] = (opt[cur].off > 1) ? opt[cur - mlen].rep[1] : opt[cur - mlen].rep[2];
+ opt[cur].rep[1] = (opt[cur].off > 0) ? opt[cur - mlen].rep[0] : opt[cur - mlen].rep[1];
+ opt[cur].rep[0] =
+ ((opt[cur].off == ZSTD_REP_MOVE_OPT) && (mlen != 1)) ? (opt[cur - mlen].rep[0] - 1) : (opt[cur - mlen].rep[opt[cur].off]);
+ }
+
+ best_mlen = minMatch;
+ {
+ U32 i, last_i = ZSTD_REP_CHECK + (mlen != 1);
+ for (i = (mlen != 1); i < last_i; i++) {
+ const S32 repCur = (i == ZSTD_REP_MOVE_OPT) ? (opt[cur].rep[0] - 1) : opt[cur].rep[i];
+ const U32 repIndex = (U32)(curr + cur - repCur);
+ const BYTE *const repBase = repIndex < dictLimit ? dictBase : base;
+ const BYTE *const repMatch = repBase + repIndex;
+ if ((repCur > 0 && repCur <= (S32)(curr + cur)) &&
+ (((U32)((dictLimit - 1) - repIndex) >= 3) & (repIndex > lowestIndex)) /* intentional overflow */
+ && (ZSTD_readMINMATCH(inr, minMatch) == ZSTD_readMINMATCH(repMatch, minMatch))) {
+ /* repcode detected */
+ const BYTE *const repEnd = repIndex < dictLimit ? dictEnd : iend;
+ mlen = (U32)ZSTD_count_2segments(inr + minMatch, repMatch + minMatch, iend, repEnd, prefixStart) + minMatch;
+
+ if (mlen > sufficient_len || cur + mlen >= ZSTD_OPT_NUM) {
+ best_mlen = mlen;
+ best_off = i;
+ last_pos = cur + 1;
+ goto _storeSequence;
+ }
+
+ best_off = i - (opt[cur].mlen != 1);
+ if (mlen > best_mlen)
+ best_mlen = mlen;
+
+ do {
+ if (opt[cur].mlen == 1) {
+ litlen = opt[cur].litlen;
+ if (cur > litlen) {
+ price = opt[cur - litlen].price + ZSTD_getPrice(seqStorePtr, litlen, inr - litlen,
+ best_off, mlen - MINMATCH, ultra);
+ } else
+ price = ZSTD_getPrice(seqStorePtr, litlen, anchor, best_off, mlen - MINMATCH, ultra);
+ } else {
+ litlen = 0;
+ price = opt[cur].price + ZSTD_getPrice(seqStorePtr, 0, NULL, best_off, mlen - MINMATCH, ultra);
+ }
+
+ if (cur + mlen > last_pos || price <= opt[cur + mlen].price)
+ SET_PRICE(cur + mlen, mlen, i, litlen, price);
+ mlen--;
+ } while (mlen >= minMatch);
+ }
+ }
+ }
+
+ match_num = ZSTD_BtGetAllMatches_selectMLS_extDict(ctx, inr, iend, maxSearches, mls, matches, minMatch);
+
+ if (match_num > 0 && (matches[match_num - 1].len > sufficient_len || cur + matches[match_num - 1].len >= ZSTD_OPT_NUM)) {
+ best_mlen = matches[match_num - 1].len;
+ best_off = matches[match_num - 1].off;
+ last_pos = cur + 1;
+ goto _storeSequence;
+ }
+
+ /* set prices using matches at position = cur */
+ for (u = 0; u < match_num; u++) {
+ mlen = (u > 0) ? matches[u - 1].len + 1 : best_mlen;
+ best_mlen = matches[u].len;
+
+ while (mlen <= best_mlen) {
+ if (opt[cur].mlen == 1) {
+ litlen = opt[cur].litlen;
+ if (cur > litlen)
+ price = opt[cur - litlen].price + ZSTD_getPrice(seqStorePtr, litlen, ip + cur - litlen,
+ matches[u].off - 1, mlen - MINMATCH, ultra);
+ else
+ price = ZSTD_getPrice(seqStorePtr, litlen, anchor, matches[u].off - 1, mlen - MINMATCH, ultra);
+ } else {
+ litlen = 0;
+ price = opt[cur].price + ZSTD_getPrice(seqStorePtr, 0, NULL, matches[u].off - 1, mlen - MINMATCH, ultra);
+ }
+
+ if (cur + mlen > last_pos || (price < opt[cur + mlen].price))
+ SET_PRICE(cur + mlen, mlen, matches[u].off, litlen, price);
+
+ mlen++;
+ }
+ }
+ } /* for (cur = 1; cur <= last_pos; cur++) */
+
+ best_mlen = opt[last_pos].mlen;
+ best_off = opt[last_pos].off;
+ cur = last_pos - best_mlen;
+
+ /* store sequence */
+_storeSequence: /* cur, last_pos, best_mlen, best_off have to be set */
+ opt[0].mlen = 1;
+
+ while (1) {
+ mlen = opt[cur].mlen;
+ offset = opt[cur].off;
+ opt[cur].mlen = best_mlen;
+ opt[cur].off = best_off;
+ best_mlen = mlen;
+ best_off = offset;
+ if (mlen > cur)
+ break;
+ cur -= mlen;
+ }
+
+ for (u = 0; u <= last_pos;) {
+ u += opt[u].mlen;
+ }
+
+ for (cur = 0; cur < last_pos;) {
+ mlen = opt[cur].mlen;
+ if (mlen == 1) {
+ ip++;
+ cur++;
+ continue;
+ }
+ offset = opt[cur].off;
+ cur += mlen;
+ litLength = (U32)(ip - anchor);
+
+ if (offset > ZSTD_REP_MOVE_OPT) {
+ rep[2] = rep[1];
+ rep[1] = rep[0];
+ rep[0] = offset - ZSTD_REP_MOVE_OPT;
+ offset--;
+ } else {
+ if (offset != 0) {
+ best_off = (offset == ZSTD_REP_MOVE_OPT) ? (rep[0] - 1) : (rep[offset]);
+ if (offset != 1)
+ rep[2] = rep[1];
+ rep[1] = rep[0];
+ rep[0] = best_off;
+ }
+
+ if (litLength == 0)
+ offset--;
+ }
+
+ ZSTD_updatePrice(seqStorePtr, litLength, anchor, offset, mlen - MINMATCH);
+ ZSTD_storeSeq(seqStorePtr, litLength, anchor, offset, mlen - MINMATCH);
+ anchor = ip = ip + mlen;
+ }
+ } /* for (cur=0; cur < last_pos; ) */
+
+ /* Save reps for next block */
+ {
+ int i;
+ for (i = 0; i < ZSTD_REP_NUM; i++)
+ ctx->repToConfirm[i] = rep[i];
+ }
+
+ /* Last Literals */
+ {
+ size_t lastLLSize = iend - anchor;
+ memcpy(seqStorePtr->lit, anchor, lastLLSize);
+ seqStorePtr->lit += lastLLSize;
+ }
+}
+
+#endif /* ZSTD_OPT_H_91842398743 */
return 0;
}
+static bool eth_dev_get_mac_address(struct udevice *dev, u8 mac[ARP_HLEN])
+{
+#if IS_ENABLED(CONFIG_OF_CONTROL)
+ const uint8_t *p;
+
+ p = dev_read_u8_array_ptr(dev, "mac-address", ARP_HLEN);
+ if (!p)
+ p = dev_read_u8_array_ptr(dev, "local-mac-address", ARP_HLEN);
+
+ if (!p)
+ return false;
+
+ memcpy(mac, p, ARP_HLEN);
+
+ return true;
+#else
+ return false;
+#endif
+}
+
static int eth_post_probe(struct udevice *dev)
{
struct eth_device_priv *priv = dev->uclass_priv;
priv->state = ETH_STATE_INIT;
- /* Check if the device has a MAC address in ROM */
- if (eth_get_ops(dev)->read_rom_hwaddr)
- eth_get_ops(dev)->read_rom_hwaddr(dev);
+ /* Check if the device has a valid MAC address in device tree */
+ if (!eth_dev_get_mac_address(dev, pdata->enetaddr) ||
+ !is_valid_ethaddr(pdata->enetaddr)) {
+ /* Check if the device has a MAC address in ROM */
+ if (eth_get_ops(dev)->read_rom_hwaddr)
+ eth_get_ops(dev)->read_rom_hwaddr(dev);
+ }
eth_env_get_enetaddr_by_index("eth", dev->seq, env_enetaddr);
if (!is_zero_ethaddr(env_enetaddr)) {
#endif
}
+ eth_write_hwaddr(dev);
+
return 0;
}
ALL-y += $(obj)/boot.bin
endif
+ifdef CONFIG_TPL_BUILD
+ALL-$(CONFIG_TPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-tpl.bin
+else
ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin
+endif
ALL-$(CONFIG_ARCH_ZYNQ) += $(obj)/boot.bin
ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
FINAL_DTB_CONTAINER = $(obj)/$(SPL_BIN).multidtb.fit
endif
+# Build the .dtb file if:
+# - we are not using OF_PLATDATA
+# - we are using OF_CONTROL
+# - we have either OF_SEPARATE or OF_HOSTFILE
+build_dtb :=
+ifeq ($(CONFIG_$(SPL_TPL_)OF_PLATDATA),)
+ifneq ($(CONFIG_$(SPL_TPL_)OF_CONTROL),)
+ifeq ($(CONFIG_OF_SEPARATE)$(CONFIG_OF_HOSTFILE),y)
+build_dtb := y
+endif
+endif
+endif
-ifeq ($(CONFIG_$(SPL_TPL_)OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
+ifneq ($(build_dtb),)
$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \
$(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \
$(FINAL_DTB_CONTAINER) FORCE
cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary \
- $(if $(CONFIG_SPL_X86_16BIT_INIT),-R .start16 -R .resetvec)
+ $(if $(CONFIG_$(SPL_TPL_)X86_16BIT_INIT),-R .start16 -R .resetvec)
$(obj)/$(SPL_BIN)-nodtb.bin: $(obj)/$(SPL_BIN) FORCE
$(call if_changed,objcopy)
$(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE
$(call if_changed,objcopy)
+OBJCOPYFLAGS_u-boot-x86-16bit-tpl.bin := -O binary -j .start16 -j .resetvec
+$(obj)/u-boot-x86-16bit-tpl.bin: $(obj)/u-boot-tpl FORCE
+ $(call if_changed,objcopy)
+
LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
CONFIG_BOARDDIR
CONFIG_BOARDNAME
CONFIG_BOARDNAME_LOCAL
-CONFIG_BOARD_AXM
CONFIG_BOARD_COMMON
CONFIG_BOARD_ECC_SUPPORT
CONFIG_BOARD_IS_OPENRD_BASE
CONFIG_BOARD_POSTCLK_INIT
CONFIG_BOARD_REVISION_TAG
CONFIG_BOARD_SIZE_LIMIT
-CONFIG_BOARD_TAURUS
CONFIG_BOOGER
CONFIG_BOOTBLOCK
CONFIG_BOOTFILE
CONFIG_BUILD_ENVCRC
CONFIG_BUS_WIDTH
CONFIG_BZIP2
-CONFIG_CADDY2
CONFIG_CALXEDA_XGMAC
CONFIG_CDP_APPLIANCE_VLAN_TYPE
CONFIG_CDP_CAPABILITIES
CONFIG_CM_REMAP
CONFIG_CM_SPD_DETECT
CONFIG_CM_T335
-CONFIG_CM_T3517
CONFIG_CM_T3X
CONFIG_CM_T43
CONFIG_CM_T54
CONFIG_CONS_SCIF3
CONFIG_CONS_SCIF4
CONFIG_CONS_SCIF5
-CONFIG_CONS_SCIF7
CONFIG_CONTROL
CONFIG_CONTROLCENTERD
CONFIG_CON_ROT
CONFIG_CPU_PXA27X
CONFIG_CPU_PXA300
CONFIG_CPU_R8000
-CONFIG_CPU_SH7203
-CONFIG_CPU_SH7264
-CONFIG_CPU_SH7269
-CONFIG_CPU_SH7706
-CONFIG_CPU_SH7720
CONFIG_CPU_SH7722
CONFIG_CPU_SH7723
-CONFIG_CPU_SH7724
CONFIG_CPU_SH7734
CONFIG_CPU_SH7750
CONFIG_CPU_SH7751
CONFIG_CPU_SH7757
CONFIG_CPU_SH7763
CONFIG_CPU_SH7780
-CONFIG_CPU_SH7785
CONFIG_CPU_TYPE_R
CONFIG_CPU_VR41XX
CONFIG_CQSPI_REF_CLK
-CONFIG_CRC32
CONFIG_CS8900_BUS16
CONFIG_CS8900_BUS32
CONFIG_CSF_SIZE
CONFIG_DISCONTIGMEM
CONFIG_DISCOVER_PHY
CONFIG_DISPLAY_AER_xxxx
-CONFIG_DLVISION_10G
CONFIG_DM9000_BASE
CONFIG_DM9000_BYTE_SWAPPED
CONFIG_DM9000_DEBUG
CONFIG_DRIVER_AX88796L
CONFIG_DRIVER_DM9000
CONFIG_DRIVER_EP93XX_MAC
-CONFIG_DRIVER_ETHER
CONFIG_DRIVER_NE2000
CONFIG_DRIVER_NE2000_BASE
CONFIG_DRIVER_NE2000_CCR
CONFIG_DRIVER_SMC911X_BASE
CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
CONFIG_DRIVER_TI_EMAC_USE_RMII
-CONFIG_DRIVE_MMC
-CONFIG_DRIVE_SATA
-CONFIG_DRIVE_TYPES
CONFIG_DSP_CLUSTER_START
CONFIG_DUOVERO
CONFIG_DWC2_DFLT_SPEED_FULL
CONFIG_ECC_SRAM_ADDR_MASK
CONFIG_ECC_SRAM_ADDR_SHIFT
CONFIG_ECC_SRAM_REQ_BIT
-CONFIG_ECOVEC_ROMIMAGE_ADDR
CONFIG_EDB9301
CONFIG_EDB9302
CONFIG_EDB9302A
CONFIG_EHCI_MXS_PORT0
CONFIG_EHCI_MXS_PORT1
CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
-CONFIG_EMMC_BOOT
CONFIG_EMU
CONFIG_ENABLE_36BIT_PHYS
CONFIG_ENABLE_MMU
CONFIG_ENV_SETTINGS_V2
CONFIG_ENV_SIZE_FLEX
CONFIG_ENV_SIZE_REDUND
-CONFIG_ENV_SPI_BUS
-CONFIG_ENV_SPI_CS
-CONFIG_ENV_SPI_MAX_HZ
-CONFIG_ENV_SPI_MODE
CONFIG_ENV_SROM_BANK
CONFIG_ENV_TOTAL_SIZE
CONFIG_ENV_UBIFS_OPTION
CONFIG_ESBC_HDR_LS
CONFIG_ESDHC_DETECT_8_BIT_QUIRK
CONFIG_ESDHC_DETECT_QUIRK
-CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1
CONFIG_ESDHC_HC_BLK_ADDR
CONFIG_ESPRESSO7420
CONFIG_ET1100_BASE
CONFIG_FLASH_SHOW_PROGRESS
CONFIG_FLASH_SPANSION_S29WS_N
CONFIG_FLASH_VERIFY
-CONFIG_FMAN_ENET
CONFIG_FM_PLAT_CLK_DIV
CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
CONFIG_FORMIKE
CONFIG_GMII
CONFIG_GOOD_SESH4
CONFIG_GPCNTRL
-CONFIG_GPIO
CONFIG_GPIO_ENABLE_SPI_FLASH
CONFIG_GPIO_LED_INVERTED_TABLE
CONFIG_GPIO_LED_STUBS
CONFIG_GREEN_LED
CONFIG_GURNARD_FPGA
CONFIG_GURNARD_SPLASH
-CONFIG_GZIP
CONFIG_GZIP_COMPRESSED
CONFIG_GZIP_COMPRESS_DEF_SZ
CONFIG_G_DNL_THOR_PRODUCT_NUM
CONFIG_G_DNL_UMS_PRODUCT_NUM
CONFIG_G_DNL_UMS_VENDOR_NUM
CONFIG_H264_FREQ
-CONFIG_H8300
CONFIG_HAS_ETH0
CONFIG_HAS_ETH1
CONFIG_HAS_ETH2
CONFIG_HDMI_ENCODER_I2C_ADDR
CONFIG_HETROGENOUS_CLUSTERS
CONFIG_HIDE_LOGO_VERSION
-CONFIG_HIGH_BATS
CONFIG_HIKEY_GPIO
CONFIG_HITACHI_SX14
CONFIG_HOSTNAME
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
-CONFIG_HRCON
CONFIG_HRCON_DH
CONFIG_HRCON_FANS
CONFIG_HSMMC2_8BIT
CONFIG_I2C_TIMEOUT
CONFIG_ICACHE
CONFIG_ICS307_REFCLK_HZ
-CONFIG_IDE_PCMCIA
CONFIG_IDE_PREINIT
CONFIG_IDE_RESET
CONFIG_IDE_SWAP_IO
CONFIG_INI_MAX_SECTION
CONFIG_INTEGRITY
CONFIG_INTERRUPTS
-CONFIG_IO
-CONFIG_IO64
-CONFIG_IOCON
CONFIG_IODELAY_RECALIBRATION
CONFIG_IOMUX_LPSR
CONFIG_IOMUX_SHARE_CONF_REG
CONFIG_KIRQ_EN
CONFIG_KM8321
CONFIG_KMCOGE4
-CONFIG_KMCOGE5NE
-CONFIG_KMETER1
CONFIG_KMLION1
-CONFIG_KMOPTI2
CONFIG_KMP204X
-CONFIG_KMSUPX5
CONFIG_KMTEGR1
-CONFIG_KMTEPR2
CONFIG_KMVECT1
CONFIG_KM_BOARD_EXTRA_ENV
CONFIG_KM_BOARD_NAME
CONFIG_MCFPIT
CONFIG_MCFRTC
CONFIG_MCFTMR
-CONFIG_MCFUART
CONFIG_MCLK_DIS
CONFIG_MDIO_TIMEOUT
CONFIG_MEMSIZE
CONFIG_MMC_SUNXI_SLOT
CONFIG_MMU
CONFIG_MONITOR_IS_IN_RAM
-CONFIG_MPC8308
-CONFIG_MPC8309
-CONFIG_MPC830x
-CONFIG_MPC8313
-CONFIG_MPC8313ERDB
-CONFIG_MPC8315
-CONFIG_MPC8315ERDB
-CONFIG_MPC831x
-CONFIG_MPC832XEMDS
-CONFIG_MPC832x
-CONFIG_MPC8349
-CONFIG_MPC8349ITX
-CONFIG_MPC834x
-CONFIG_MPC8360
-CONFIG_MPC837XEMDS
-CONFIG_MPC837XERDB
-CONFIG_MPC837x
CONFIG_MPC83XX_GPIO
CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
CONFIG_NO_ETH
CONFIG_NO_RELOCATION
CONFIG_NO_WAIT
-CONFIG_NR_CPUS
CONFIG_NR_DRAM_POPULATED
CONFIG_NS16550_MIN_FUNCTIONS
CONFIG_NS8382X
CONFIG_PQ_MDS_PIB
CONFIG_PQ_MDS_PIB_ATM
CONFIG_PRAM
-CONFIG_PREBOOT
CONFIG_PRINTK
CONFIG_PROC_FS
CONFIG_PROFILE_ALL_BRANCHES
CONFIG_PXA_VGA
CONFIG_PXA_VIDEO
CONFIG_QBMAN_CLK_DIV
-CONFIG_QE
CONFIG_QEMU_MIPS
CONFIG_QIXIS_I2C_ACCESS
CONFIG_QSPI
CONFIG_RD_LVL
CONFIG_REALMODE_DEBUG
CONFIG_RED_LED
-CONFIG_REFCLK_FREQ
CONFIG_REG
CONFIG_REG_0
CONFIG_REG_1_BASE
CONFIG_SCF0403_LCD
CONFIG_SCIF
CONFIG_SCIF_A
-CONFIG_SCIF_EXT_CLOCK
CONFIG_SCIF_USE_EXT_CLK
CONFIG_SCSI_AHCI_PLAT
CONFIG_SCSI_DEV_LIST
CONFIG_SHARP_LQ035Q7DH06
CONFIG_SHEEVA_88SV131
CONFIG_SHEEVA_88SV331xV5
-CONFIG_SHMIN
CONFIG_SHOW_ACTIVITY
CONFIG_SHOW_BOOT_PROGRESS
CONFIG_SH_CMT_CLK_FREQ
CONFIG_SMSTP8_ENA
CONFIG_SMSTP9_ENA
CONFIG_SOCRATES
-CONFIG_SOC_DM355
-CONFIG_SOC_DM365
CONFIG_SOC_DM644X
-CONFIG_SOC_DM646X
CONFIG_SOC_K2E
CONFIG_SOC_K2G
CONFIG_SOC_K2HK
CONFIG_STATIC_BOARD_REV
CONFIG_STD_DEVICES_SETTINGS
CONFIG_STM32_FLASH
-CONFIG_STRIDER
CONFIG_STRIDER_CON
CONFIG_STRIDER_CON_DP
CONFIG_STRIDER_CPU
CONFIG_ST_SMI
CONFIG_SUNXI_GPIO
CONFIG_SUNXI_MAX_FB_SIZE
-CONFIG_SUPERH_ON_CHIP_R8A66597
-CONFIG_SUPPORT_EMMC_BOOT
CONFIG_SUVD3
CONFIG_SXNI855T
CONFIG_SYSFLAGS_ADDR
CONFIG_SYS_66MHZ
CONFIG_SYS_8313ERDB_BROKEN_PMC
CONFIG_SYS_83XX_DDR_USES_CS0
-CONFIG_SYS_ACR_APARK
-CONFIG_SYS_ACR_PARKM
-CONFIG_SYS_ACR_PIPE_DEP
-CONFIG_SYS_ACR_RPTCNT
CONFIG_SYS_ADDRESS_MAP_A
CONFIG_SYS_ADV7611_I2C
CONFIG_SYS_ALT_BOOT
CONFIG_SYS_AMASK5
CONFIG_SYS_AMASK6
CONFIG_SYS_AMASK7
-CONFIG_SYS_APP1_BASE
-CONFIG_SYS_APP1_SIZE
-CONFIG_SYS_APP2_BASE
-CONFIG_SYS_APP2_SIZE
CONFIG_SYS_ARM_CACHE_WRITETHROUGH
CONFIG_SYS_AT91_CPU_NAME
CONFIG_SYS_AT91_MAIN_CLOCK
CONFIG_SYS_DDRD
CONFIG_SYS_DDRTC
CONFIG_SYS_DDRUA
-CONFIG_SYS_DDR_BASE
CONFIG_SYS_DDR_BLOCK1_SIZE
CONFIG_SYS_DDR_BLOCK2_BASE
CONFIG_SYS_DDR_CDR_1
CONFIG_SYS_DIRECT_FLASH_TFTP
CONFIG_SYS_DISCOVER_PHY
CONFIG_SYS_DIU_ADDR
-CONFIG_SYS_DM36x_PINMUX0
-CONFIG_SYS_DM36x_PINMUX1
-CONFIG_SYS_DM36x_PINMUX2
-CONFIG_SYS_DM36x_PINMUX3
-CONFIG_SYS_DM36x_PINMUX4
-CONFIG_SYS_DM36x_PLL1_PREDIV
-CONFIG_SYS_DM36x_PLL2_PREDIV
CONFIG_SYS_DMA_USE_INTSRAM
CONFIG_SYS_DP501_BASE
CONFIG_SYS_DP501_DIFFERENTIAL
CONFIG_SYS_FORM_PMC_XMC
CONFIG_SYS_FORM_VME
CONFIG_SYS_FORM_XMC
-CONFIG_SYS_FPGA0_BASE
-CONFIG_SYS_FPGA0_SIZE
CONFIG_SYS_FPGAREG_DATE
CONFIG_SYS_FPGAREG_DIPSW
CONFIG_SYS_FPGAREG_FREQ
CONFIG_SYS_GAFR2_U_VAL
CONFIG_SYS_GAFR3_L_VAL
CONFIG_SYS_GAFR3_U_VAL
-CONFIG_SYS_GBIT_MII1_BUSNAME
-CONFIG_SYS_GBIT_MII_BUSNAME
CONFIG_SYS_GBL_DATA_OFFSET
CONFIG_SYS_GBL_DATA_SIZE
CONFIG_SYS_GIC400_ADDR
CONFIG_SYS_GPSR3_VAL
CONFIG_SYS_HALT_BEFOR_RAM_JUMP
CONFIG_SYS_HELP_CMD_WIDTH
-CONFIG_SYS_HID0_FINAL
-CONFIG_SYS_HID0_INIT
-CONFIG_SYS_HID2
CONFIG_SYS_HIGH
CONFIG_SYS_HMI_BASE
-CONFIG_SYS_HOSTNAME
CONFIG_SYS_HRCW_HIGH
-CONFIG_SYS_HRCW_HIGH_BASE
CONFIG_SYS_HRCW_LOW
CONFIG_SYS_HZ_CLOCK
CONFIG_SYS_I2C
CONFIG_SYS_LBC_SDRAM_BASE
CONFIG_SYS_LBC_SDRAM_BASE_PHYS
CONFIG_SYS_LBC_SDRAM_SIZE
-CONFIG_SYS_LBLAWAR0_PRELIM
-CONFIG_SYS_LBLAWAR1_PRELIM
-CONFIG_SYS_LBLAWAR2_PRELIM
-CONFIG_SYS_LBLAWAR3_PRELIM
-CONFIG_SYS_LBLAWAR4_PRELIM
-CONFIG_SYS_LBLAWAR5_PRELIM
-CONFIG_SYS_LBLAWAR6_PRELIM
-CONFIG_SYS_LBLAWAR7_PRELIM
-CONFIG_SYS_LBLAWBAR0_PRELIM
-CONFIG_SYS_LBLAWBAR1_PRELIM
-CONFIG_SYS_LBLAWBAR2_PRELIM
-CONFIG_SYS_LBLAWBAR3_PRELIM
-CONFIG_SYS_LBLAWBAR4_PRELIM
-CONFIG_SYS_LBLAWBAR5_PRELIM
-CONFIG_SYS_LBLAWBAR6_PRELIM
-CONFIG_SYS_LBLAWBAR7_PRELIM
CONFIG_SYS_LB_SDRAM
CONFIG_SYS_LCD_BASE
-CONFIG_SYS_LCRR_CLKDIV
-CONFIG_SYS_LCRR_DBYP
-CONFIG_SYS_LCRR_EADC
CONFIG_SYS_LDB_CLOCK
CONFIG_SYS_LDSCRIPT
CONFIG_SYS_LED_BASE
CONFIG_SYS_LOAD_ADDR
CONFIG_SYS_LOAD_ADDR2
CONFIG_SYS_LOW
-CONFIG_SYS_LOWBOOT
CONFIG_SYS_LOWMEM_BASE
CONFIG_SYS_LOW_RES_TIMER
CONFIG_SYS_LPAE_SDRAM_BASE
CONFIG_SYS_MAPLE
CONFIG_SYS_MAPLE_MEM_PHYS
CONFIG_SYS_MAPPED_RAM_BASE
-CONFIG_SYS_MARUBUN_IO
-CONFIG_SYS_MARUBUN_MRSHPC
-CONFIG_SYS_MARUBUN_MW1
-CONFIG_SYS_MARUBUN_MW2
CONFIG_SYS_MASTER_CLOCK
CONFIG_SYS_MATRIX_EBI0CSA_VAL
CONFIG_SYS_MATRIX_EBICSA_VAL
CONFIG_SYS_MCLINK_MAX
CONFIG_SYS_MCMEM0_VAL
CONFIG_SYS_MCMEM1_VAL
-CONFIG_SYS_MDC1_PIN
CONFIG_SYS_MDCNFG_VAL
-CONFIG_SYS_MDC_PIN
CONFIG_SYS_MDIO1_OFFSET
-CONFIG_SYS_MDIO1_PIN
CONFIG_SYS_MDIO_BASE_ADDR
-CONFIG_SYS_MDIO_PIN
CONFIG_SYS_MDMRS_VAL
CONFIG_SYS_MDREFR_VAL
CONFIG_SYS_MECR_VAL
CONFIG_SYS_NOR1_CSPR_EXT
CONFIG_SYS_NOR_AMASK
CONFIG_SYS_NOR_AMASK_EARLY
-CONFIG_SYS_NOR_BR_PRELIM
CONFIG_SYS_NOR_CSOR
CONFIG_SYS_NOR_CSPR
CONFIG_SYS_NOR_CSPR_EXT
CONFIG_SYS_NOR_FTIM1
CONFIG_SYS_NOR_FTIM2
CONFIG_SYS_NOR_FTIM3
-CONFIG_SYS_NOR_OR_PRELIM
CONFIG_SYS_NO_DCACHE
CONFIG_SYS_NS16550_CLK
CONFIG_SYS_NS16550_CLK_DIV
CONFIG_SYS_OR1_REMAP
CONFIG_SYS_OR6_64M
CONFIG_SYS_OR6_8M
-CONFIG_SYS_OR_TIMING_FLASH
CONFIG_SYS_OR_TIMING_MRAM
CONFIG_SYS_OSCIN_FREQ
CONFIG_SYS_OSD_DH
CONFIG_SYS_POST_WORD_ADDR
CONFIG_SYS_PPC_DDR_WIMGE
CONFIG_SYS_PQSPAR
-CONFIG_SYS_PRELIM_OR_AM
CONFIG_SYS_PROMPT_HUSH_PS2
CONFIG_SYS_PSDPAR
CONFIG_SYS_PSSR_VAL
CONFIG_SYS_PTDPAR
CONFIG_SYS_PTV
CONFIG_SYS_PUAPAR
-CONFIG_SYS_QE_FMAN_FW_IN_MMC
-CONFIG_SYS_QE_FMAN_FW_IN_NAND
-CONFIG_SYS_QE_FMAN_FW_IN_NOR
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
CONFIG_SYS_QE_FMAN_FW_LENGTH
CONFIG_SYS_QE_FW_ADDR
-CONFIG_SYS_QE_FW_IN_SPIFLASH
CONFIG_SYS_QMAN_CENA_BASE
CONFIG_SYS_QMAN_CENA_SIZE
CONFIG_SYS_QMAN_CINH_BASE
CONFIG_SYS_SDRAM_DRVSTRENGTH
CONFIG_SYS_SDRAM_DRV_STRENGTH
CONFIG_SYS_SDRAM_EMOD
-CONFIG_SYS_SDRAM_LOWER
CONFIG_SYS_SDRAM_MODE
CONFIG_SYS_SDRAM_SIZE
CONFIG_SYS_SDRAM_SIZE0
CONFIG_SYS_SDRAM_SIZE1
CONFIG_SYS_SDRAM_SIZE_LAW
-CONFIG_SYS_SDRAM_UPPER
CONFIG_SYS_SDRAM_VAL
CONFIG_SYS_SDRAM_VAL1
CONFIG_SYS_SDRAM_VAL10
CONFIG_SYS_SPCR_OPT
CONFIG_SYS_SPCR_TSEC1EP
CONFIG_SYS_SPCR_TSEC2EP
-CONFIG_SYS_SPCR_TSECEP
CONFIG_SYS_SPD_BUS_NUM
CONFIG_SYS_SPI0
CONFIG_SYS_SPI0_NUM_CS
CONFIG_SYS_USE_DATAFLASH_CS0
CONFIG_SYS_USE_DATAFLASH_CS1
CONFIG_SYS_USE_DATAFLASH_CS3
-CONFIG_SYS_USE_DSPLINK
CONFIG_SYS_USE_FLASH
CONFIG_SYS_USE_MAIN_OSCILLATOR
CONFIG_SYS_USE_MMC
CONFIG_TSECV2_1
CONFIG_TSEC_TBI
CONFIG_TSEC_TBICR_SETTINGS
-CONFIG_TUGE1
CONFIG_TULIP
CONFIG_TULIP_FIX_DAVICOM
CONFIG_TULIP_SELECT_MEDIA
CONFIG_TULIP_USE_IO
-CONFIG_TUXX1
CONFIG_TWL6030_INPUT
CONFIG_TWL6030_POWER
CONFIG_TWR
CONFIG_TWR_P1025
CONFIG_TX_DESCR_NUM
CONFIG_TZSW_RESERVED_DRAM_SIZE
-CONFIG_T_SH7706LSR
CONFIG_UART_BR_PRELIM
CONFIG_UART_OR_PRELIM
CONFIG_UBIBLOCK
CONFIG_USB_EHCI_EXYNOS
CONFIG_USB_EHCI_FARADAY
CONFIG_USB_EHCI_KIRKWOOD
-CONFIG_USB_EHCI_MX5
CONFIG_USB_EHCI_MXC
CONFIG_USB_EHCI_MXS
CONFIG_USB_EHCI_SPEAR
CONFIG_USB_GADGET_PXA27X
CONFIG_USB_GADGET_PXA2XX
CONFIG_USB_GADGET_SA1100
-CONFIG_USB_GADGET_SUPERH
CONFIG_USB_INVENTRA_DMA
CONFIG_USB_ISP1301_I2C_ADDR
CONFIG_USB_MAX_CONTROLLER_COUNT
CONFIG_USB_OTG_BLACKLIST_HUB
CONFIG_USB_PHY_TYPE
CONFIG_USB_PXA25X_SMALL
-CONFIG_USB_R8A66597_HCD
CONFIG_USB_SERIALNO
CONFIG_USB_TI_CPPI_DMA
CONFIG_USB_TTY
CONFIG_VIDEO_VCXK
CONFIG_VID_FLS_ENV
CONFIG_VM86
-CONFIG_VME8349
CONFIG_VOIPAC_LCD
CONFIG_VOL_MONITOR_INA220
CONFIG_VOL_MONITOR_IR36021_READ
CONFIG_YAFFS_UTIL
CONFIG_YAFFS_WINCE
CONFIG_YELLOW_LED
-CONFIG_ZLIB
CONFIG_ZLT
CONFIG_ZM7300
-CONFIG_ZYNQMP_EEPROM
CONFIG_ZYNQ_HISPD_BROKEN
CONFIG_eTSEC_MDIO_BUS
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+
+static int dm_test_reset(struct unit_test_state *uts)
+{
+ struct udevice *dev_cache;
+ struct cache_info;
+
+ ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
+ ut_assertok(cache_get_info(dev, &info));
+
+ return 0;
+}
+DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <asm/clk.h>
#include <dm/test.h>
#include <linux/err.h>
#include <test/ut.h>
+/* Base test of the clk uclass */
+static int dm_test_clk_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct clk clk_method1;
+ struct clk clk_method2;
+
+ /* Get the device using the clk device */
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &dev));
+
+ /* Get the same clk port in 2 different ways and compare */
+ ut_assertok(clk_get_by_index(dev, 1, &clk_method1));
+ ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2));
+ ut_asserteq(clk_method1.id, clk_method2.id);
+
+ return 0;
+}
+
+DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_FDT);
+
static int dm_test_clk(struct unit_test_state *uts)
{
struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test;
#include <common.h>
#include <dm.h>
+#include <reset.h>
#include <dm/test.h>
#include <asm/reset.h>
#include <test/ut.h>
/* This is the other reset phandle specifier handled by bulk */
#define OTHER_RESET_ID 2
+/* Base test of the reset uclass */
+static int dm_test_reset_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct reset_ctl reset_method1;
+ struct reset_ctl reset_method2;
+
+ /* Get the device using the reset device */
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
+ &dev));
+
+ /* Get the same reset port in 2 different ways and compare */
+ ut_assertok(reset_get_by_index(dev, 1, &reset_method1));
+ ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 1,
+ &reset_method2));
+ ut_asserteq(reset_method1.id, reset_method2.id);
+
+ return 0;
+}
+
+DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_FDT);
+
static int dm_test_reset(struct unit_test_state *uts)
{
struct udevice *dev_reset;
return 0;
}
-static void vidconsole_put_string(struct udevice *dev, const char *str)
-{
- const char *s;
-
- for (s = str; *s; s++)
- vidconsole_put_char(dev, *s);
-}
-
/* Test text output works on the video console */
static int dm_test_video_text(struct unit_test_state *uts)
{
#define FAKE_BUILD_TAG "jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \
"and a lot more text to come"
+/* Test printing GUIDs */
+static void guid_ut_print(void)
+{
+#if CONFIG_IS_ENABLED(LIB_UUID)
+ unsigned char guid[16] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
+ };
+ char str[40];
+
+ sprintf(str, "%pUb", guid);
+ assert(!strcmp("01020304-0506-0708-090a-0b0c0d0e0f10", str));
+ sprintf(str, "%pUB", guid);
+ assert(!strcmp("01020304-0506-0708-090A-0B0C0D0E0F10", str));
+ sprintf(str, "%pUl", guid);
+ assert(!strcmp("04030201-0605-0807-090a-0b0c0d0e0f10", str));
+ sprintf(str, "%pUL", guid);
+ assert(!strcmp("04030201-0605-0807-090A-0B0C0D0E0F10", str));
+#endif
+}
+
/* Test efi_loader specific printing */
static void efi_ut_print(void)
{
assert(s == str);
assert(!strcmp("\n\nU-Boo\n\n", s));
- s = display_options_get_banner(true, str, 1);
- assert(s == str);
- assert(!strcmp("", s));
+ /* Assert that we do not overwrite memory before the buffer */
+ str[0] = '`';
+ s = display_options_get_banner(true, str + 1, 1);
+ assert(s == str + 1);
+ assert(!strcmp("`", str));
- s = display_options_get_banner(true, str, 2);
- assert(s == str);
- assert(!strcmp("\n", s));
+ str[0] = '~';
+ s = display_options_get_banner(true, str + 1, 2);
+ assert(s == str + 1);
+ assert(!strcmp("~\n", str));
+ /* The last two characters are set to \n\n for all buffer sizes > 2 */
s = display_options_get_banner(false, str, sizeof(str));
assert(s == str);
assert(!strcmp("U-Boot \n\n", s));
/* Test efi_loader specific printing */
efi_ut_print();
+ /* Test printing GUIDs */
+ guid_ut_print();
+
printf("%s: Everything went swimmingly\n", __func__);
return 0;
}
This test relies on boardenv_* to containing configuration values to define
which MMC devices should be tested. For example:
+# Configuration data for test_mmc_dev, test_mmc_rescan, test_mmc_info; defines
+# whole MMC devices that mmc dev/rescan/info commands may operate upon.
+env__mmc_dev_configs = (
+ {
+ 'fixture_id': 'emmc-boot0',
+ 'is_emmc': True,
+ 'devid': 0,
+ 'partid': 1,
+ 'info_device': ???,
+ 'info_speed': ???,
+ 'info_mode': ???,
+ 'info_buswidth': ???.
+ },
+ {
+ 'fixture_id': 'emmc-boot1',
+ 'is_emmc': True,
+ 'devid': 0,
+ 'partid': 2,
+ 'info_device': ???,
+ 'info_speed': ???,
+ 'info_mode': ???,
+ 'info_buswidth': ???.
+ },
+ {
+ 'fixture_id': 'emmc-data',
+ 'is_emmc': True,
+ 'devid': 0,
+ 'partid': 0,
+ 'info_device': ???,
+ 'info_speed': ???,
+ 'info_mode': ???,
+ 'info_buswidth': ???.
+ },
+ {
+ 'fixture_id': 'sd',
+ 'is_emmc': False,
+ 'devid': 1,
+ 'partid': None,
+ 'info_device': ???,
+ 'info_speed': ???,
+ 'info_mode': ???,
+ 'info_buswidth': ???.
+ },
+}
+
+# Configuration data for test_mmc_rd; defines regions of the MMC (entire
+# devices, or ranges of sectors) which can be read:
env__mmc_rd_configs = (
{
'fixture_id': 'emmc-boot0',
assert good_response in response
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_dev(u_boot_console, env__mmc_rd_config):
+def test_mmc_dev(u_boot_console, env__mmc_dev_config):
"""Test the "mmc dev" command.
Args:
u_boot_console: A U-Boot console connection.
- env__mmc_rd_config: The single MMC configuration on which
+ env__mmc_dev_config: The single MMC configuration on which
to run the test. See the file-level comment above for details
of the format.
Nothing.
"""
- is_emmc = env__mmc_rd_config['is_emmc']
- devid = env__mmc_rd_config['devid']
- partid = env__mmc_rd_config.get('partid', 0)
+ is_emmc = env__mmc_dev_config['is_emmc']
+ devid = env__mmc_dev_config['devid']
+ partid = env__mmc_dev_config.get('partid', 0)
# Select MMC device
mmc_dev(u_boot_console, is_emmc, devid, partid)
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_rescan(u_boot_console, env__mmc_rd_config):
+def test_mmc_rescan(u_boot_console, env__mmc_dev_config):
"""Test the "mmc rescan" command.
Args:
u_boot_console: A U-Boot console connection.
- env__mmc_rd_config: The single MMC configuration on which
+ env__mmc_dev_config: The single MMC configuration on which
to run the test. See the file-level comment above for details
of the format.
Nothing.
"""
- is_emmc = env__mmc_rd_config['is_emmc']
- devid = env__mmc_rd_config['devid']
- partid = env__mmc_rd_config.get('partid', 0)
+ is_emmc = env__mmc_dev_config['is_emmc']
+ devid = env__mmc_dev_config['devid']
+ partid = env__mmc_dev_config.get('partid', 0)
# Select MMC device
mmc_dev(u_boot_console, is_emmc, devid, partid)
assert 'no card present' not in response
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_info(u_boot_console, env__mmc_rd_config):
+def test_mmc_info(u_boot_console, env__mmc_dev_config):
"""Test the "mmc info" command.
Args:
u_boot_console: A U-Boot console connection.
- env__mmc_rd_config: The single MMC configuration on which
+ env__mmc_dev_config: The single MMC configuration on which
to run the test. See the file-level comment above for details
of the format.
Nothing.
"""
- is_emmc = env__mmc_rd_config['is_emmc']
- devid = env__mmc_rd_config['devid']
- partid = env__mmc_rd_config.get('partid', 0)
- info_device = env__mmc_rd_config['info_device']
- info_speed = env__mmc_rd_config['info_speed']
- info_mode = env__mmc_rd_config['info_mode']
- info_buswidth = env__mmc_rd_config['info_buswidth']
+ is_emmc = env__mmc_dev_config['is_emmc']
+ devid = env__mmc_dev_config['devid']
+ partid = env__mmc_dev_config.get('partid', 0)
+ info_device = env__mmc_dev_config['info_device']
+ info_speed = env__mmc_dev_config['info_speed']
+ info_mode = env__mmc_dev_config['info_mode']
+ info_buswidth = env__mmc_dev_config['info_buswidth']
# Select MMC device
mmc_dev(u_boot_console, is_emmc, devid, partid)
hostprogs-$(CONFIG_CMD_BOOTEFI_SELFTEST) += file2include
+FIT_OBJS-$(CONFIG_FIT) := fit_common.o fit_image.o image-host.o common/image-fit.o
FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o
# The following files are synced with upstream DTC.
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
atmelimage.o \
+ $(FIT_OBJS-y) \
$(FIT_SIG_OBJS-y) \
common/bootm.o \
lib/crc32.o \
default_image.o \
lib/fdtdec_common.o \
lib/fdtdec.o \
- fit_common.o \
- fit_image.o \
- common/image-fit.o \
- image-host.o \
common/image.o \
imagetool.o \
imximage.o \
hostprogs-y += fdtgrep
fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o
+ifneq ($(TOOLS_ONLY),y)
+hostprogs-y += spl_size_limit
+endif
+
hostprogs-$(CONFIG_MIPS) += mips-relocs
# We build some files with extra pedantic flags to try to minimize things
ifneq ($(CROSS_BUILD_TOOLS),)
override HOSTCC = $(CC)
+override HOSTCFLAGS = $(CFLAGS)
quiet_cmd_crosstools_strip = STRIP $^
cmd_crosstools_strip = $(STRIP) $^; touch $@
Sets the image size in bytes, for example 'size = <0x100000>' for a
1MB image.
+offset:
+ This is similar to 'offset' in entries, setting the offset of a section
+ within the image or section containing it. The first byte of the section
+ is normally at offset 0. If 'offset' is not provided, binman sets it to
+ the end of the previous region, or the start of the image's entry area
+ (normally 0) if there is no previous region.
+
align-size:
This sets the alignment of the image size. For example, to ensure
that the image ends on a 512-byte boundary, use 'align-size = <512>'.
self._name = name
self._node = node
self._image = image
- self._offset = 0
+ self._offset = None
self._size = None
self._align_size = None
self._pad_before = 0
def _ReadNode(self):
"""Read properties from the section node"""
+ self._offset = fdt_util.GetInt(self._node, 'offset')
self._size = fdt_util.GetInt(self._node, 'size')
self._align_size = fdt_util.GetInt(self._node, 'align-size')
if tools.NotPowerOfTwo(self._align_size):
entry.AddMissingProperties()
def SetCalculatedProperties(self):
- state.SetInt(self._node, 'offset', self._offset)
+ state.SetInt(self._node, 'offset', self._offset or 0)
state.SetInt(self._node, 'size', self._size)
image_pos = self._image_pos
if self._parent_section:
Args:
fd: File to write the map to
"""
- Entry.WriteMapLine(fd, indent, self._name, self._offset, self._size,
- self._image_pos)
+ Entry.WriteMapLine(fd, indent, self._name, self._offset or 0,
+ self._size, self._image_pos)
for entry in self._entries.values():
entry.WriteMap(fd, indent + 1)
if name not in options.image:
del images[name]
skip.append(name)
- if skip:
- print 'Skipping images: %s\n' % ', '.join(skip)
+ if skip and options.verbosity >= 2:
+ print 'Skipping images: %s' % ', '.join(skip)
state.Prepare(images, dtb)
def Pack(self, offset):
"""Pack all entries into the section"""
self._section.PackEntries()
- self._section.SetOffset(offset)
+ if self._section._offset is None:
+ self._section.SetOffset(offset)
self.size = self._section.GetSize()
return super(Entry_section, self).Pack(offset)
self.text_label, = self.GetEntryArgsOrProps(
[EntryArg('text-label', str)])
self.value, = self.GetEntryArgsOrProps([EntryArg(self.text_label, str)])
+
+ def ObtainContents(self):
if not self.value:
self.Raise("No value provided for text label '%s'" %
self.text_label)
-
- def ObtainContents(self):
self.SetContents(self.value)
return True
"""An entry which contains a Chromium OS verified boot block
Properties / Entry arguments:
+ - content: List of phandles to entries to sign
- keydir: Directory containing the public keys to use
- keyblock: Name of the key file to use (inside keydir)
- signprivate: Name of provide key file to use (inside keydir)
return control.Binman(options, args)
def _DoTestFile(self, fname, debug=False, map=False, update_dtb=False,
- entry_args=None, images=None, use_real_dtb=False):
+ entry_args=None, images=None, use_real_dtb=False,
+ verbosity=None):
"""Run binman with a given test file
Args:
args.append('-up')
if not use_real_dtb:
args.append('--fake-dtb')
+ if verbosity is not None:
+ args.append('-v%d' % verbosity)
if entry_args:
for arg, value in entry_args.iteritems():
args.append('-a%s=%s' % (arg, value))
def testSelectImage(self):
"""Test that we can select which images to build"""
- with test_util.capture_sys_output() as (stdout, stderr):
- retcode = self._DoTestFile('006_dual_image.dts', images=['image2'])
- self.assertEqual(0, retcode)
- self.assertIn('Skipping images: image1', stdout.getvalue())
+ expected = 'Skipping images: image1'
+
+ # We should only get the expected message in verbose mode
+ for verbosity in (None, 2):
+ with test_util.capture_sys_output() as (stdout, stderr):
+ retcode = self._DoTestFile('006_dual_image.dts',
+ verbosity=verbosity,
+ images=['image2'])
+ self.assertEqual(0, retcode)
+ if verbosity:
+ self.assertIn(expected, stdout.getvalue())
+ else:
+ self.assertNotIn(expected, stdout.getvalue())
- self.assertFalse(os.path.exists(tools.GetOutputFilename('image1.bin')))
- self.assertTrue(os.path.exists(tools.GetOutputFilename('image2.bin')))
+ self.assertFalse(os.path.exists(tools.GetOutputFilename('image1.bin')))
+ self.assertTrue(os.path.exists(tools.GetOutputFilename('image2.bin')))
def testUpdateFdtAll(self):
"""Test that all device trees are updated with offset/size info"""
data = self._DoReadFile('100_intel_refcode.dts')
self.assertEqual(REFCODE_DATA, data[:len(REFCODE_DATA)])
+ def testSectionOffset(self):
+ """Tests use of a section with an offset"""
+ data, _, map_data, _ = self._DoReadFileDtb('101_sections_offset.dts',
+ map=True)
+ self.assertEqual('''ImagePos Offset Size Name
+00000000 00000000 00000038 main-section
+00000004 00000004 00000010 section@0
+00000004 00000000 00000004 u-boot
+00000018 00000018 00000010 section@1
+00000018 00000000 00000004 u-boot
+0000002c 0000002c 00000004 section@2
+0000002c 00000000 00000004 u-boot
+''', map_data)
+ self.assertEqual(data,
+ 4 * chr(0x26) + U_BOOT_DATA + 12 * chr(0x21) +
+ 4 * chr(0x26) + U_BOOT_DATA + 12 * chr(0x61) +
+ 4 * chr(0x26) + U_BOOT_DATA + 8 * chr(0x26))
+
if __name__ == "__main__":
unittest.main()
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ pad-byte = <0x26>;
+ size = <0x38>;
+ section@0 {
+ read-only;
+ offset = <0x4>;
+ size = <0x10>;
+ pad-byte = <0x21>;
+
+ u-boot {
+ };
+ };
+ section@1 {
+ size = <0x10>;
+ pad-byte = <0x61>;
+ offset = <0x18>;
+
+ u-boot {
+ };
+ };
+ section@2 {
+ offset = <0x2c>;
+ u-boot {
+ };
+ };
+ };
+};
environment = {}
if os.path.exists(done_file):
with open(done_file, 'r') as fd:
- return_code = int(fd.readline())
+ try:
+ return_code = int(fd.readline())
+ except ValueError:
+ # The file may be empty due to running out of disk space.
+ # Try a rebuild
+ return_code = 1
err_lines = []
err_file = self.GetErrFile(commit_upto, target)
if os.path.exists(err_file):
if (ENVSIZE(0) != ENVSIZE(1)) {
fprintf(stderr,
- "Redundant environments have unequal size");
+ "Redundant environments have unequal size\n");
return -1;
}
}
usage(*argv);
}
- ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false);
+ ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false, true);
if (ffd < 0)
return EXIT_FAILURE;
- kfd = mmap_fdt(cmdname, keyfile, 0, &key_blob, &ksbuf, false);
+ kfd = mmap_fdt(cmdname, keyfile, 0, &key_blob, &ksbuf, false, true);
if (kfd < 0)
return EXIT_FAILURE;
}
int mmap_fdt(const char *cmdname, const char *fname, size_t size_inc,
- void **blobp, struct stat *sbuf, bool delete_on_error)
+ void **blobp, struct stat *sbuf, bool delete_on_error,
+ bool read_only)
{
void *ptr;
int fd;
/* Load FIT blob into memory (we need to write hashes/signatures) */
- fd = open(fname, O_RDWR | O_BINARY);
+ fd = open(fname, (read_only ? O_RDONLY : O_RDWR) | O_BINARY);
if (fd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
}
errno = 0;
- ptr = mmap(0, sbuf->st_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
+ ptr = mmap(0, sbuf->st_size,
+ (read_only ? PROT_READ : PROT_READ | PROT_WRITE), MAP_SHARED,
+ fd, 0);
if ((ptr == MAP_FAILED) || (errno != 0)) {
fprintf(stderr, "%s: Can't read %s: %s\n",
cmdname, fname, strerror(errno));
* @blobp: Returns pointer to FDT blob
* @sbuf: File status information is stored here
* @delete_on_error: true to delete the file if we get an error
+ * @read_only: true to open in read-only mode
* @return 0 if OK, -1 on error.
*/
int mmap_fdt(const char *cmdname, const char *fname, size_t size_inc,
- void **blobp, struct stat *sbuf, bool delete_on_error);
+ void **blobp, struct stat *sbuf, bool delete_on_error,
+ bool read_only);
#endif /* _FIT_COMMON_H_ */
void *ptr;
int ret = 0;
- tfd = mmap_fdt(params->cmdname, tmpfile, size_inc, &ptr, &sbuf, true);
+ tfd = mmap_fdt(params->cmdname, tmpfile, size_inc, &ptr, &sbuf, true,
+ false);
if (tfd < 0)
return -EIO;
struct stat dest_sbuf;
destfd = mmap_fdt(params->cmdname, params->keydest, size_inc,
- &dest_blob, &dest_sbuf, false);
+ &dest_blob, &dest_sbuf, false,
+ false);
if (destfd < 0) {
ret = -EIO;
goto err_keydest;
int images;
int node;
- fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false);
+ fd = mmap_fdt(params->cmdname, fname, 0, &fdt, &sbuf, false, false);
if (fd < 0)
return -EIO;
fit_size = fdt_totalsize(fdt);
int images;
int node;
- fd = mmap_fdt(params->cmdname, fname, 0, &old_fdt, &sbuf, false);
+ fd = mmap_fdt(params->cmdname, fname, 0, &old_fdt, &sbuf, false, false);
if (fd < 0)
return -EIO;
fit_size = fdt_totalsize(old_fdt);
fprintf(stderr, "%s: Missing property name\n", *argv);
usage(*argv);
}
- ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false);
+ ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false, false);
if (ffd < 0) {
printf("Could not open %s\n", fdtfile);
--- /dev/null
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Script to add K3 specific x509 cetificate to a binary.
+#
+
+# Variables
+OUTPUT=tiboot3.bin
+TEMP_X509=x509-temp.cert
+CERT=certificate.bin
+RAND_KEY=eckey.pem
+LOADADDR=0x41c00000
+BOOTCORE_OPTS=0
+BOOTCORE=16
+
+gen_degen_template() {
+cat << 'EOF' > degen-template.txt
+
+asn1=SEQUENCE:rsa_key
+
+[rsa_key]
+version=INTEGER:0
+modulus=INTEGER:0xDEGEN_MODULUS
+pubExp=INTEGER:1
+privExp=INTEGER:1
+p=INTEGER:0xDEGEN_P
+q=INTEGER:0xDEGEN_Q
+e1=INTEGER:1
+e2=INTEGER:1
+coeff=INTEGER:0xDEGEN_COEFF
+EOF
+}
+
+# Generate x509 Template
+gen_template() {
+cat << 'EOF' > x509-template.txt
+ [ req ]
+ distinguished_name = req_distinguished_name
+ x509_extensions = v3_ca
+ prompt = no
+ dirstring_type = nobmp
+
+ [ req_distinguished_name ]
+ C = US
+ ST = TX
+ L = Dallas
+ O = Texas Instruments Incorporated
+ OU = Processors
+ CN = TI support
+ emailAddress = support@ti.com
+
+ [ v3_ca ]
+ basicConstraints = CA:true
+ 1.3.6.1.4.1.294.1.1 = ASN1:SEQUENCE:boot_seq
+ 1.3.6.1.4.1.294.1.2 = ASN1:SEQUENCE:image_integrity
+ 1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv
+# 1.3.6.1.4.1.294.1.4 = ASN1:SEQUENCE:encryption
+ 1.3.6.1.4.1.294.1.8 = ASN1:SEQUENCE:debug
+
+ [ boot_seq ]
+ certType = INTEGER:TEST_CERT_TYPE
+ bootCore = INTEGER:TEST_BOOT_CORE
+ bootCoreOpts = INTEGER:TEST_BOOT_CORE_OPTS
+ destAddr = FORMAT:HEX,OCT:TEST_BOOT_ADDR
+ imageSize = INTEGER:TEST_IMAGE_LENGTH
+
+ [ image_integrity ]
+ shaType = OID:2.16.840.1.101.3.4.2.3
+ shaValue = FORMAT:HEX,OCT:TEST_IMAGE_SHA_VAL
+
+ [ swrv ]
+ swrv = INTEGER:0
+
+# [ encryption ]
+# initalVector = FORMAT:HEX,OCT:TEST_IMAGE_ENC_IV
+# randomString = FORMAT:HEX,OCT:TEST_IMAGE_ENC_RS
+# iterationCnt = INTEGER:TEST_IMAGE_KEY_DERIVE_INDEX
+# salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT
+
+ [ debug ]
+ debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000
+ debugType = INTEGER:4
+ coreDbgEn = INTEGER:0
+ coreDbgSecEn = INTEGER:0
+EOF
+}
+
+parse_key() {
+ sed '/\ \ \ \ /s/://g' key.txt | awk '!/\ \ \ \ / {printf("\n%s\n", $0)}; /\ \ \ \ / {printf("%s", $0)}' | sed 's/\ \ \ \ //g' | awk "/$1:/{getline; print}"
+}
+
+gen_degen_key() {
+# Generate a 4096 bit RSA Key
+ openssl genrsa -out key.pem 1024 >>/dev/null 2>&1
+ openssl rsa -in key.pem -text -out key.txt >>/dev/null 2>&1
+ DEGEN_MODULUS=$( parse_key 'modulus' )
+ DEGEN_P=$( parse_key 'prime1' )
+ DEGEN_Q=$( parse_key 'prime2' )
+ DEGEN_COEFF=$( parse_key 'coefficient' )
+ gen_degen_template
+
+ sed -e "s/DEGEN_MODULUS/$DEGEN_MODULUS/"\
+ -e "s/DEGEN_P/$DEGEN_P/" \
+ -e "s/DEGEN_Q/$DEGEN_Q/" \
+ -e "s/DEGEN_COEFF/$DEGEN_COEFF/" \
+ degen-template.txt > degenerateKey.txt
+
+ openssl asn1parse -genconf degenerateKey.txt -out degenerateKey.der >>/dev/null 2>&1
+ openssl rsa -in degenerateKey.der -inform DER -outform PEM -out $RAND_KEY >>/dev/null 2>&1
+ KEY=$RAND_KEY
+ rm key.pem key.txt degen-template.txt degenerateKey.txt degenerateKey.der
+}
+
+declare -A options_help
+usage() {
+ if [ -n "$*" ]; then
+ echo "ERROR: $*"
+ fi
+ echo -n "Usage: $0 "
+ for option in "${!options_help[@]}"
+ do
+ arg=`echo ${options_help[$option]}|cut -d ':' -f1`
+ if [ -n "$arg" ]; then
+ arg=" $arg"
+ fi
+ echo -n "[-$option$arg] "
+ done
+ echo
+ echo -e "\nWhere:"
+ for option in "${!options_help[@]}"
+ do
+ arg=`echo ${options_help[$option]}|cut -d ':' -f1`
+ txt=`echo ${options_help[$option]}|cut -d ':' -f2`
+ tb="\t\t\t"
+ if [ -n "$arg" ]; then
+ arg=" $arg"
+ tb="\t"
+ fi
+ echo -e " -$option$arg:$tb$txt"
+ done
+ echo
+ echo "Examples of usage:-"
+ echo "# Example of signing the SYSFW binary with rsa degenerate key"
+ echo " $0 -c 0 -b ti-sci-firmware-am6x.bin -o sysfw.bin -l 0x40000"
+ echo "# Example of signing the SPL binary with rsa degenerate key"
+ echo " $0 -c 16 -b spl/u-boot-spl.bin -o tiboot3.bin -l 0x41c00000"
+}
+
+options_help[b]="bin_file:Bin file that needs to be signed"
+options_help[k]="key_file:file with key inside it. If not provided script generates a rsa degenerate key."
+options_help[o]="output_file:Name of the final output file. default to $OUTPUT"
+options_help[c]="core_id:target core id on which the image would be running. Default to $BOOTCORE"
+options_help[l]="loadaddr: Target load address of the binary in hex. Default to $LOADADDR"
+
+while getopts "b:k:o:c:l:h" opt
+do
+ case $opt in
+ b)
+ BIN=$OPTARG
+ ;;
+ k)
+ KEY=$OPTARG
+ ;;
+ o)
+ OUTPUT=$OPTARG
+ ;;
+ l)
+ LOADADDR=$OPTARG
+ ;;
+ c)
+ BOOTCORE=$OPTARG
+ ;;
+ h)
+ usage
+ exit 0
+ ;;
+ \?)
+ usage "Invalid Option '-$OPTARG'"
+ exit 1
+ ;;
+ :)
+ usage "Option '-$OPTARG' Needs an argument."
+ exit 1
+ ;;
+ esac
+done
+
+if [ "$#" -eq 0 ]; then
+ usage "Arguments missing"
+ exit 1
+fi
+
+if [ -z "$BIN" ]; then
+ usage "Bin file missing in arguments"
+ exit 1
+fi
+
+# Generate rsa degenerate key if user doesn't provide a key
+if [ -z "$KEY" ]; then
+ gen_degen_key
+fi
+
+if [ $BOOTCORE == 0 ]; then # BOOTCORE M3, loaded by ROM
+ CERTTYPE=2
+elif [ $BOOTCORE == 16 ]; then # BOOTCORE R5, loaded by ROM
+ CERTTYPE=1
+else # Non BOOTCORE, loaded by SYSFW
+ BOOTCORE_OPTS_VER=$(printf "%01x" 1)
+ # Add input args option for SET and CLR flags.
+ BOOTCORE_OPTS_SETFLAG=$(printf "%08x" 0)
+ BOOTCORE_OPTS_CLRFLAG=$(printf "%08x" 0x100) # Clear FLAG_ARMV8_AARCH32
+ BOOTCORE_OPTS="0x$BOOTCORE_OPTS_VER$BOOTCORE_OPTS_SETFLAG$BOOTCORE_OPTS_CLRFLAG"
+ # Set the cert type to zero.
+ # We are not using public/private key store now
+ CERTTYPE=$(printf "0x%08x" 0)
+fi
+
+SHA_VAL=`openssl dgst -sha512 -hex $BIN | sed -e "s/^.*= //g"`
+BIN_SIZE=`cat $BIN | wc -c`
+ADDR=`printf "%08x" $LOADADDR`
+
+gen_cert() {
+ #echo "Certificate being generated :"
+ #echo " LOADADDR = 0x$ADDR"
+ #echo " IMAGE_SIZE = $BIN_SIZE"
+ #echo " CERT_TYPE = $CERTTYPE"
+ sed -e "s/TEST_IMAGE_LENGTH/$BIN_SIZE/" \
+ -e "s/TEST_IMAGE_SHA_VAL/$SHA_VAL/" \
+ -e "s/TEST_CERT_TYPE/$CERTTYPE/" \
+ -e "s/TEST_BOOT_CORE_OPTS/$BOOTCORE_OPTS/" \
+ -e "s/TEST_BOOT_CORE/$BOOTCORE/" \
+ -e "s/TEST_BOOT_ADDR/$ADDR/" x509-template.txt > $TEMP_X509
+ openssl req -new -x509 -key $KEY -nodes -outform DER -out $CERT -config $TEMP_X509 -sha512
+}
+
+gen_template
+gen_cert
+cat $CERT $BIN > $OUTPUT
+
+# Remove all intermediate files
+rm $TEMP_X509 $CERT x509-template.txt
+if [ "$KEY" == "$RAND_KEY" ]; then
+ rm $RAND_KEY
+fi
+++ /dev/null
- [ req ]
- distinguished_name = req_distinguished_name
- x509_extensions = v3_ca
- prompt = no
- dirstring_type = nobmp
-
- [ req_distinguished_name ]
- C = US
- ST = TX
- L = Dallas
- O = Texas Instruments Incorporated
- OU = Processors
- CN = TI Support
- emailAddress = support@ti.com
-
- [ v3_ca ]
- basicConstraints = CA:true
- 1.3.6.1.4.1.294.1.1 = ASN1:SEQUENCE:boot_seq
- 1.3.6.1.4.1.294.1.2 = ASN1:SEQUENCE:image_integrity
- 1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv
-# 1.3.6.1.4.1.294.1.4 = ASN1:SEQUENCE:encryption
- 1.3.6.1.4.1.294.1.8 = ASN1:SEQUENCE:debug
-
- [ boot_seq ]
- certType = INTEGER:TEST_CERT_TYPE
- bootCore = INTEGER:TEST_BOOT_CORE
- bootCoreOpts = INTEGER:TEST_BOOT_ARCH_WIDTH
- destAddr = FORMAT:HEX,OCT:TEST_BOOT_ADDR
- imageSize = INTEGER:TEST_IMAGE_LENGTH
-
- [ image_integrity ]
- shaType = OID:2.16.840.1.101.3.4.2.3
- shaValue = FORMAT:HEX,OCT:TEST_IMAGE_SHA_VAL
-
- [ swrv ]
- swrv = INTEGER:0
-
-# [ encryption ]
-# initalVector = FORMAT:HEX,OCT:TEST_IMAGE_ENC_IV
-# randomString = FORMAT:HEX,OCT:TEST_IMAGE_ENC_RS
-# iterationCnt = INTEGER:TEST_IMAGE_KEY_DERIVE_INDEX
-# salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT
-
- [ debug ]
- debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000
- debugType = INTEGER:4
- coreDbgEn = INTEGER:0
- coreDbgSecEn = INTEGER:0
goto err_ctx;
}
- if (!EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key)) {
+ if (EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key) != 1) {
ret = openssl_err("Could not verify signature");
goto err_ctx;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019, Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
+ *
+ * This tool helps to return the size available for SPL image during build
+ */
+
+#include <generated/autoconf.h>
+#include <generated/generic-asm-offsets.h>
+
+int main(int argc, char *argv[])
+{
+ int spl_size_limit = 0;
+
+#ifdef CONFIG_SPL_SIZE_LIMIT
+ spl_size_limit = CONFIG_SPL_SIZE_LIMIT;
+#ifdef CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD
+ spl_size_limit -= GENERATED_GBL_DATA_SIZE;
+#endif
+#ifdef CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC
+ spl_size_limit -= CONFIG_SPL_SYS_MALLOC_F_LEN;
+#endif
+#ifdef CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK
+ spl_size_limit -= CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK;
+#endif
+#endif
+
+ printf("%d", spl_size_limit);
+ return 0;
+}
#define HEADER_VERSION_V1 0x1
/* default option : bit0 => no signature */
#define HEADER_DEFAULT_OPTION (cpu_to_le32(0x00000001))
+/* default binary type for U-Boot */
+#define HEADER_TYPE_UBOOT (cpu_to_le32(0x00000000))
struct stm32_header {
uint32_t magic_number;
uint32_t option_flags;
uint32_t ecdsa_algorithm;
uint32_t ecdsa_public_key[64 / 4];
- uint32_t padding[84 / 4];
+ uint32_t padding[83 / 4];
+ uint32_t binary_type;
};
static struct stm32_header stm32image_header;
ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1;
ptr->option_flags = HEADER_DEFAULT_OPTION;
ptr->ecdsa_algorithm = 1;
+ ptr->binary_type = HEADER_TYPE_UBOOT;
}
static uint32_t stm32image_checksum(void *start, uint32_t len)
le32_to_cpu(stm32hdr->image_checksum));
printf("Option : 0x%08x\n",
le32_to_cpu(stm32hdr->option_flags));
+ printf("BinaryType : 0x%08x\n",
+ le32_to_cpu(stm32hdr->binary_type));
}
static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd,
projects / project / bcm63xx / u-boot.git / commitdiff