fdts: stm32mp1: realign device tree files with internal devs

Update DDR parameters to version 1.45.
Remove useless sdmmc1_dir_pins_b node.
Add USART3 and UART7 nodes.
Correct a PMIC value for USB regulator.
Add TIMER12, TIMER15, CRYP, HASH and USBOTG_HS nodes.
Update DTSI file for SDMMC compatible, but overwrite it with the former
name.
Move BSEC board_id node to boards DTS files, as this OTP is specific to
STMicroelectronics boards.

Change-Id: If4d2fe090c6a8368afe8e21e5ac70579911d3939
Signed-off-by: Yann Gautier <yann.gautier@st.com>

diff --git a/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
index 16b8cf623be3683318263b6a750b60ab387cb92b..11e8f2bef69f815f22cbb66bdf56a93c6a36721a 100644 (file)
--- a/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
+++ b/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-/* STM32MP157C DK1/DK2 BOARD configuration
+ *
+ * STM32MP157C DK1/DK2 BOARD configuration
  * 1x DDR3L 4Gb, 16-bit, 533MHz.
  * Reference used NT5CC256M16DP-DI from NANYA
  *
@@ -16,8 +16,7 @@
  * address mapping : RBC
  * Tc > + 85C : N
  */
-
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.41"
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
 #define DDR_MEM_SPEED 533000
 #define DDR_MEM_SIZE 0x20000000
 
@@ -90,7 +89,7 @@
 #define DDR_PTR2 0x042DA068
 #define DDR_ACIOCR 0x10400812
 #define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
 #define DDR_DCR 0x0000000B
 #define DDR_DTPR0 0x38D488D0
 #define DDR_DTPR1 0x098B00D8
@@ -109,11 +108,11 @@
 #define DDR_DX1DLLCR 0x40000000
 #define DDR_DX1DQTR 0xFFFFFFFF
 #define DDR_DX1DQSTR 0x3DB02000
-#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2GCR 0x0000CE80
 #define DDR_DX2DLLCR 0x40000000
 #define DDR_DX2DQTR 0xFFFFFFFF
 #define DDR_DX2DQSTR 0x3DB02000
-#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3GCR 0x0000CE80
 #define DDR_DX3DLLCR 0x40000000
 #define DDR_DX3DQTR 0xFFFFFFFF
 #define DDR_DX3DQSTR 0x3DB02000

diff --git a/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
index 82e710468d5c2b592f6637b34fba4f082c68da25..4b70b605541bdda9dd80c357c723a24254ad896b 100644 (file)
--- a/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
+++ b/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -1,9 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-/* STM32MP157C ED1 BOARD configuration
+ *
+ * STM32MP157C ED1 BOARD configuration
  * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
  * Reference used NT5CC256M16DP-DI from NANYA
  *
@@ -17,8 +16,7 @@
  * address mapping : RBC
  * Tc > + 85C : N
  */
-
-#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.41"
+#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
 #define DDR_MEM_SPEED 533000
 #define DDR_MEM_SIZE 0x40000000
 
@@ -91,7 +89,7 @@
 #define DDR_PTR2 0x042DA068
 #define DDR_ACIOCR 0x10400812
 #define DDR_DXCCR 0x00000C40
-#define DDR_DSGCR 0xF200001F
+#define DDR_DSGCR 0xF200011F
 #define DDR_DCR 0x0000000B
 #define DDR_DTPR0 0x38D488D0
 #define DDR_DTPR1 0x098B00D8

diff --git a/fdts/stm32mp157-pinctrl.dtsi b/fdts/stm32mp157-pinctrl.dtsi
index c7553ca50dbda892f783dc0080b398bfbee7f6c5..8e480b2c19ec01722e95acefd6698748d8f93643 100644 (file)
--- a/fdts/stm32mp157-pinctrl.dtsi
+++ b/fdts/stm32mp157-pinctrl.dtsi
@@ -214,21 +214,6 @@
                                };
                        };
 
-                       sdmmc1_dir_pins_b: sdmmc1-dir-1 {
-                               pins1 {
-                                       pinmux = <STM32_PINMUX('E', 12, AF8)>, /* SDMMC1_D0DIR */
-                                                <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
-                                                <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
-                                       slew-rate = <3>;
-                                       drive-push-pull;
-                                       bias-pull-up;
-                               };
-                               pins2 {
-                                       pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
-                                       bias-pull-up;
-                               };
-                       };
-
                        sdmmc2_b4_pins_a: sdmmc2-b4-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
@@ -286,6 +271,19 @@
                                };
                        };
 
+                       uart7_pins_a: uart7-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <0>;
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
+                                       bias-disable;
+                               };
+                       };
+
                        usart3_pins_a: usart3-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@@ -300,6 +298,21 @@
                                        bias-disable;
                                };
                        };
+
+                       usart3_pins_b: usart3-1 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+                                                <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <0>;
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+                                                <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
+                                       bias-disable;
+                               };
+                       };
                };
 
                pinctrl_z: pin-controller-z@54004000 {

diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts
index 9016b0f5b0a679caa5afc421ff86129ca6239d0a..b17d50194e203081749d7813be2e4210b18d89c8 100644 (file)
--- a/fdts/stm32mp157a-dk1.dts
+++ b/fdts/stm32mp157a-dk1.dts
@@ -15,6 +15,8 @@
 
        aliases {
                serial0 = &uart4;
+               serial1 = &usart3;
+               serial2 = &uart7;
        };
 
        chosen {
@@ -176,6 +178,18 @@
        status = "okay";
 };
 
+&uart7 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart7_pins_a>;
+       status = "disabled";
+};
+
+&usart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&usart3_pins_b>;
+       status = "disabled";
+};
+
 /* ATF Specific */
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
 #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
@@ -287,3 +301,11 @@
                cfg = < 3 98 5 7 7 PQR(1,1,1) >;
        };
 };
+
+&bsec {
+       board_id: board_id@ec {
+               reg = <0xec 0x4>;
+               status = "okay";
+               secure-status = "okay";
+       };
+};

diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index 7b16616b041263b019a35b97ef7b7200d673944e..ed55725b02b4bfa5eafc8f3f5b153dd908345937 100644 (file)
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -42,7 +42,7 @@
 
                st,main-control-register = <0x04>;
                st,vin-control-register = <0xc0>;
-               st,usb-control-register = <0x30>;
+               st,usb-control-register = <0x20>;
 
                regulators {
                        compatible = "st,stpmic1-regulators";
@@ -308,4 +308,10 @@
        };
 };
 
-/delete-node/ &clk_csi;
+&bsec {
+       board_id: board_id@ec {
+               reg = <0xec 0x4>;
+               status = "okay";
+               secure-status = "okay";
+       };
+};

diff --git a/fdts/stm32mp157c-security.dtsi b/fdts/stm32mp157c-security.dtsi
index 59119c5298d16fdf3bb18c341e5edbd799de2c49..f7e55b3672bc683cd659c220ce6122a59ff9ca1b 100644 (file)
--- a/fdts/stm32mp157c-security.dtsi
+++ b/fdts/stm32mp157c-security.dtsi
@@ -26,9 +26,12 @@
                status = "okay";
                secure-status = "okay";
        };
-       board_id: board_id@ec {
-               reg = <0xec 0x4>;
-               status = "okay";
-               secure-status = "okay";
-       };
+};
+
+&sdmmc1 {
+       compatible = "st,stm32-sdmmc2";
+};
+
+&sdmmc2 {
+       compatible = "st,stm32-sdmmc2";
 };

diff --git a/fdts/stm32mp157c.dtsi b/fdts/stm32mp157c.dtsi
index 1df76fa752e7fbaa33a8ae9b1bce24ef83fcbdb7..0942a91c2aa6d2b3d90af12166b8f75ae8efd495 100644 (file)
--- a/fdts/stm32mp157c.dtsi
+++ b/fdts/stm32mp157c.dtsi
@@ -70,6 +70,16 @@
                interrupt-parent = <&intc>;
                ranges;
 
+               timers12: timer@40006000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32-timers";
+                       reg = <0x40006000 0x400>;
+                       clocks = <&rcc TIM12_K>;
+                       clock-names = "int";
+                       status = "disabled";
+               };
+
                usart2: serial@4000e000 {
                        compatible = "st,stm32h7-uart";
                        reg = <0x4000e000 0x400>;
@@ -127,8 +137,19 @@
                        status = "disabled";
                };
 
+               timers15: timer@44006000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "st,stm32-timers";
+                       reg = <0x44006000 0x400>;
+                       clocks = <&rcc TIM15_K>;
+                       clock-names = "int";
+                       status = "disabled";
+               };
+
                sdmmc3: sdmmc@48004000 {
-                       compatible = "st,stm32-sdmmc2";
+                       compatible = "arm,pl18x", "arm,primecell";
+                       arm,primecell-periphid = <0x00253180>;
                        reg = <0x48004000 0x400>, <0x48005000 0x400>;
                        clocks = <&rcc SDMMC3_K>;
                        clock-names = "apb_pclk";
@@ -139,6 +160,16 @@
                        status = "disabled";
                };
 
+               usbotg_hs: usb-otg@49000000 {
+                       compatible = "st,stm32mp1-hsotg", "snps,dwc2";
+                       reg = <0x49000000 0x10000>;
+                       clocks = <&rcc USBO_K>;
+                       clock-names = "otg";
+                       resets = <&rcc USBO_R>;
+                       reset-names = "dwc2";
+                       status = "disabled";
+               };
+
                rcc: rcc@50000000 {
                        compatible = "st,stm32mp1-rcc", "syscon";
                        reg = <0x50000000 0x1000>;
@@ -176,6 +207,24 @@
                        clocks = <&rcc SYSCFG>;
                };
 
+               cryp1: cryp@54001000 {
+                       compatible = "st,stm32mp1-cryp";
+                       reg = <0x54001000 0x400>;
+                       interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc CRYP1>;
+                       resets = <&rcc CRYP1_R>;
+                       status = "disabled";
+               };
+
+               hash1: hash@54002000 {
+                       compatible = "st,stm32f756-hash";
+                       reg = <0x54002000 0x400>;
+                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&rcc HASH1>;
+                       resets = <&rcc HASH1_R>;
+                       status = "disabled";
+               };
+
                rng1: rng@54003000 {
                        compatible = "st,stm32-rng";
                        reg = <0x54003000 0x400>;
@@ -208,7 +257,8 @@
                };
 
                sdmmc1: sdmmc@58005000 {
-                       compatible = "st,stm32-sdmmc2";
+                       compatible = "arm,pl18x", "arm,primecell";
+                       arm,primecell-periphid = <0x00253180>;
                        reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
                        clocks = <&rcc SDMMC1_K>;
                        clock-names = "apb_pclk";
@@ -220,7 +270,8 @@
                };
 
                sdmmc2: sdmmc@58007000 {
-                       compatible = "st,stm32-sdmmc2";
+                       compatible = "arm,pl18x", "arm,primecell";
+                       arm,primecell-periphid = <0x00253180>;
                        reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
                        clocks = <&rcc SDMMC2_K>;
                        clock-names = "apb_pclk";