amlogic: Fix prefixes in the helpers file

The code is the common directory is now generic, no need to have the SoC
prefix hardcoded in the function names.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ied3a5e506b9abd4c2d6f893bafef50019bff24f1

diff --git a/plat/amlogic/common/aarch64/aml_helpers.S b/plat/amlogic/common/aarch64/aml_helpers.S
index 760d6c46d9f36823464c3a3af70229ae92f53d52..39bff0833cc8a9dad9d825cfbabd83d90825fd76 100644 (file)
--- a/plat/amlogic/common/aarch64/aml_helpers.S
+++ b/plat/amlogic/common/aarch64/aml_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,7 @@
        .globl  plat_is_my_cpu_primary
        .globl  plat_my_core_pos
        .globl  plat_reset_handler
-       .globl  plat_gxbb_calc_core_pos
+       .globl  plat_calc_core_pos
 
        /* -----------------------------------------------------
         * unsigned int plat_my_core_pos(void);
@@ -24,17 +24,17 @@
         */
 func plat_my_core_pos
        mrs     x0, mpidr_el1
-       b       plat_gxbb_calc_core_pos
+       b       plat_calc_core_pos
 endfunc plat_my_core_pos
 
        /* -----------------------------------------------------
-        *  unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
+        *  unsigned int plat_calc_core_pos(u_register_t mpidr);
         * -----------------------------------------------------
         */
-func plat_gxbb_calc_core_pos
+func plat_calc_core_pos
        and     x0, x0, #MPIDR_CPU_MASK
        ret
-endfunc plat_gxbb_calc_core_pos
+endfunc plat_calc_core_pos
 
        /* -----------------------------------------------------
         * unsigned int plat_is_my_cpu_primary(void);
@@ -43,7 +43,7 @@ endfunc plat_gxbb_calc_core_pos
 func plat_is_my_cpu_primary
        mrs     x0, mpidr_el1
        and     x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
-       cmp     x0, #GXBB_PRIMARY_CPU
+       cmp     x0, #AML_PRIMARY_CPU
        cset    w0, eq
        ret
 endfunc plat_is_my_cpu_primary
@@ -61,9 +61,9 @@ endfunc platform_mem_init
         * ---------------------------------------------
         */
 func plat_crash_console_init
-       mov_imm x0, GXBB_UART0_AO_BASE
-       mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ
-       mov_imm x2, GXBB_UART_BAUDRATE
+       mov_imm x0, AML_UART0_AO_BASE
+       mov_imm x1, AML_UART0_AO_CLK_IN_HZ
+       mov_imm x2, AML_UART_BAUDRATE
        b       console_meson_init
 endfunc plat_crash_console_init
 
@@ -73,7 +73,7 @@ endfunc plat_crash_console_init
         * ---------------------------------------------
         */
 func plat_crash_console_putc
-       mov_imm x1, GXBB_UART0_AO_BASE
+       mov_imm x1, AML_UART0_AO_BASE
        b       console_meson_core_putc
 endfunc plat_crash_console_putc
 
@@ -84,7 +84,7 @@ endfunc plat_crash_console_putc
         * ---------------------------------------------
         */
 func plat_crash_console_flush
-       mov_imm x0, GXBB_UART0_AO_BASE
+       mov_imm x0, AML_UART0_AO_BASE
        b       console_meson_core_flush
 endfunc plat_crash_console_flush
 

diff --git a/plat/amlogic/common/aml_topology.c b/plat/amlogic/common/aml_topology.c
index 5fbad73525a0c3ff5281d44424a76d68c2e9f648..0a04c1105d13dca635da6fb071afec9bee3a1ff5 100644 (file)
--- a/plat/amlogic/common/aml_topology.c
+++ b/plat/amlogic/common/aml_topology.c
@@ -49,5 +49,5 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
        if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
                return -1;
 
-       return plat_gxbb_calc_core_pos(mpidr);
+       return plat_calc_core_pos(mpidr);
 }

diff --git a/plat/amlogic/common/include/aml_private.h b/plat/amlogic/common/include/aml_private.h
index 6f1855f6368a45ac0f101b3a745f9a16498cc9fa..c06004f8dbace62605e264bc7750b48274253de8 100644 (file)
--- a/plat/amlogic/common/include/aml_private.h
+++ b/plat/amlogic/common/include/aml_private.h
@@ -11,7 +11,7 @@
 #include <stdint.h>
 
 /* Utility functions */
-unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
+unsigned int plat_calc_core_pos(u_register_t mpidr);
 void gxbb_console_init(void);
 void gxbb_setup_page_tables(void);
 

diff --git a/plat/amlogic/gxbb/gxbb_common.c b/plat/amlogic/gxbb/gxbb_common.c
index eb688f77274e1c2fde2ef2a66b3ca5891521a47d..06ff0082aeca674dc2ba347da8a2cbd23b363e87 100644 (file)
--- a/plat/amlogic/gxbb/gxbb_common.c
+++ b/plat/amlogic/gxbb/gxbb_common.c
@@ -109,9 +109,9 @@ static console_meson_t gxbb_console;
 
 void gxbb_console_init(void)
 {
-       int rc = console_meson_register(GXBB_UART0_AO_BASE,
-                                       GXBB_UART0_AO_CLK_IN_HZ,
-                                       GXBB_UART_BAUDRATE,
+       int rc = console_meson_register(AML_UART0_AO_BASE,
+                                       AML_UART0_AO_CLK_IN_HZ,
+                                       AML_UART_BAUDRATE,
                                        &gxbb_console);
        if (rc == 0) {
                /*

diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h
index 3e27097c34db9b20573e8b251d5030f91b7a25cb..e43bb1d26c81c281bf61bc4802655b4faf17431f 100644 (file)
--- a/plat/amlogic/gxbb/gxbb_def.h
+++ b/plat/amlogic/gxbb/gxbb_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -75,9 +75,9 @@
 /*******************************************************************************
  * UART definitions
  ******************************************************************************/
-#define GXBB_UART0_AO_BASE                     UL(0xC81004C0)
-#define GXBB_UART0_AO_CLK_IN_HZ                        GXBB_OSC24M_CLK_IN_HZ
-#define GXBB_UART_BAUDRATE                     U(115200)
+#define AML_UART0_AO_BASE                      UL(0xC81004C0)
+#define AML_UART0_AO_CLK_IN_HZ                 GXBB_OSC24M_CLK_IN_HZ
+#define AML_UART_BAUDRATE                      U(115200)
 
 /*******************************************************************************
  * Memory-mapped I/O Registers

diff --git a/plat/amlogic/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c
index 4b0d755b41502df795c09492412103cdaf6b8b9e..0d542a56c595a672736ea8d80651c0a7594685c8 100644 (file)
--- a/plat/amlogic/gxbb/gxbb_pm.c
+++ b/plat/amlogic/gxbb/gxbb_pm.c
@@ -31,7 +31,7 @@ static volatile uint32_t gxbb_cpu0_go;
 
 static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value)
 {
-       unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+       unsigned int core = plat_calc_core_pos(mpidr);
        uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
 
        mmio_write_64(cpu_mailbox_addr, value);
@@ -86,10 +86,10 @@ static void __dead2 gxbb_system_off(void)
 
 static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 {
-       unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+       unsigned int core = plat_calc_core_pos(mpidr);
 
        /* CPU0 can't be turned OFF, emulate it with a WFE loop */
-       if (core == GXBB_PRIMARY_CPU) {
+       if (core == AML_PRIMARY_CPU) {
                VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
 
                gxbb_cpu0_go = 1;
@@ -113,12 +113,12 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 
 static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
-       unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+       unsigned int core = plat_calc_core_pos(read_mpidr_el1());
 
        assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
                                        PLAT_LOCAL_STATE_OFF);
 
-       if (core == GXBB_PRIMARY_CPU) {
+       if (core == AML_PRIMARY_CPU) {
                gxbb_cpu0_go = 0;
                flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go));
                dsb();
@@ -132,7 +132,7 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
 static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
 {
        u_register_t mpidr = read_mpidr_el1();
-       unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+       unsigned int core = plat_calc_core_pos(mpidr);
        uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4);
 
        mmio_write_32(addr, 0xFFFFFFFF);
@@ -141,7 +141,7 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
        gicv2_cpuif_disable();
 
        /* CPU0 can't be turned OFF, emulate it with a WFE loop */
-       if (core == GXBB_PRIMARY_CPU)
+       if (core == AML_PRIMARY_CPU)
                return;
 
        scpi_set_css_power_state(mpidr,
@@ -151,10 +151,10 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
 static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
                                                 *target_state)
 {
-       unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+       unsigned int core = plat_calc_core_pos(read_mpidr_el1());
 
        /* CPU0 can't be turned OFF, emulate it with a WFE loop */
-       if (core == GXBB_PRIMARY_CPU) {
+       if (core == AML_PRIMARY_CPU) {
                VERBOSE("BL31: CPU0 entering wait loop...\n");
 
                while (gxbb_cpu0_go == 0)

diff --git a/plat/amlogic/gxbb/include/platform_def.h b/plat/amlogic/gxbb/include/platform_def.h
index da4aedde85da71301c6d75d190efe88837647628..bd6ce32d9bb85487717d1983007871d3373b856f 100644 (file)
--- a/plat/amlogic/gxbb/include/platform_def.h
+++ b/plat/amlogic/gxbb/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,7 +25,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT   PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT            PLATFORM_CLUSTER0_CORE_COUNT
 
-#define GXBB_PRIMARY_CPU               U(0)
+#define AML_PRIMARY_CPU                        U(0)
 
 #define PLAT_MAX_PWR_LVL               MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS           (PLATFORM_CLUSTER_COUNT + \

diff --git a/plat/amlogic/gxl/gxl_common.c b/plat/amlogic/gxl/gxl_common.c
index e3bd6048af8d9007e16c9eb865908891ee1b2a78..cede8d8c8e91c8dc19b713a65710df6dd0cc95b0 100644 (file)
--- a/plat/amlogic/gxl/gxl_common.c
+++ b/plat/amlogic/gxl/gxl_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -107,9 +107,9 @@ static console_meson_t gxbb_console;
 
 void gxbb_console_init(void)
 {
-       int rc = console_meson_register(GXBB_UART0_AO_BASE,
-                                       GXBB_UART0_AO_CLK_IN_HZ,
-                                       GXBB_UART_BAUDRATE,
+       int rc = console_meson_register(AML_UART0_AO_BASE,
+                                       AML_UART0_AO_CLK_IN_HZ,
+                                       AML_UART_BAUDRATE,
                                        &gxbb_console);
        if (rc == 0) {
                /*

diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h
index 089fa8db906bbd44cd1d38d195aede9cb90f808b..ced811d94a623c2c76957495f6f6eb07f579032f 100644 (file)
--- a/plat/amlogic/gxl/gxl_def.h
+++ b/plat/amlogic/gxl/gxl_def.h
@@ -79,9 +79,9 @@
 /*******************************************************************************
  * UART definitions
  ******************************************************************************/
-#define GXBB_UART0_AO_BASE                     UL(0xC81004C0)
-#define GXBB_UART0_AO_CLK_IN_HZ                        GXBB_OSC24M_CLK_IN_HZ
-#define GXBB_UART_BAUDRATE                     U(115200)
+#define AML_UART0_AO_BASE                      UL(0xC81004C0)
+#define AML_UART0_AO_CLK_IN_HZ                 GXBB_OSC24M_CLK_IN_HZ
+#define AML_UART_BAUDRATE                      U(115200)
 
 /*******************************************************************************
  * Memory-mapped I/O Registers

diff --git a/plat/amlogic/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c
index 544ae20396190c8a714d2a27b81bf1667f4275a5..d6071bfc6c61a6a8e5c037bc427fe9e240b983eb 100644 (file)
--- a/plat/amlogic/gxl/gxl_pm.c
+++ b/plat/amlogic/gxl/gxl_pm.c
@@ -29,7 +29,7 @@ static volatile uint32_t gxbb_cpu0_go;
 
 static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
 {
-       unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+       unsigned int core = plat_calc_core_pos(mpidr);
        uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
 
        mmio_write_64(cpu_mailbox_addr, value);
@@ -37,7 +37,7 @@ static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
 
 static void gxl_pm_reset(u_register_t mpidr)
 {
-       unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+       unsigned int core = plat_calc_core_pos(mpidr);
        uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8;
 
        mmio_write_32(cpu_mailbox_addr, 0);
@@ -99,10 +99,10 @@ static void __dead2 gxbb_system_off(void)
 
 static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 {
-       unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+       unsigned int core = plat_calc_core_pos(mpidr);
 
        /* CPU0 can't be turned OFF, emulate it with a WFE loop */
-       if (core == GXBB_PRIMARY_CPU) {
+       if (core == AML_PRIMARY_CPU) {
                VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
 
                gxbb_cpu0_go = 1;
@@ -127,12 +127,12 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 
 static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
-       unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+       unsigned int core = plat_calc_core_pos(read_mpidr_el1());
 
        assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
                                        PLAT_LOCAL_STATE_OFF);
 
-       if (core == GXBB_PRIMARY_CPU) {
+       if (core == AML_PRIMARY_CPU) {
                gxbb_cpu0_go = 0;
                flush_dcache_range((uintptr_t)&gxbb_cpu0_go,
                                sizeof(gxbb_cpu0_go));
@@ -147,12 +147,12 @@ static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
 static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
 {
        u_register_t mpidr = read_mpidr_el1();
-       unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+       unsigned int core = plat_calc_core_pos(mpidr);
 
        gicv2_cpuif_disable();
 
        /* CPU0 can't be turned OFF, emulate it with a WFE loop */
-       if (core == GXBB_PRIMARY_CPU)
+       if (core == AML_PRIMARY_CPU)
                return;
 
        scpi_set_css_power_state(mpidr,
@@ -163,10 +163,10 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
                                                 *target_state)
 {
        u_register_t mpidr = read_mpidr_el1();
-       unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+       unsigned int core = plat_calc_core_pos(mpidr);
 
        /* CPU0 can't be turned OFF, emulate it with a WFE loop */
-       if (core == GXBB_PRIMARY_CPU) {
+       if (core == AML_PRIMARY_CPU) {
                VERBOSE("BL31: CPU0 entering wait loop...\n");
 
                while (gxbb_cpu0_go == 0)

diff --git a/plat/amlogic/gxl/include/platform_def.h b/plat/amlogic/gxl/include/platform_def.h
index b32ec56dab4b7995d2685a676952156974ad5777..80b0d6463eb64c0aa39f70cf1b7ac0cf99e7a600 100644 (file)
--- a/plat/amlogic/gxl/include/platform_def.h
+++ b/plat/amlogic/gxl/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,7 +25,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT   PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT            PLATFORM_CLUSTER0_CORE_COUNT
 
-#define GXBB_PRIMARY_CPU               U(0)
+#define AML_PRIMARY_CPU                        U(0)
 
 #define PLAT_MAX_PWR_LVL               MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS           (PLATFORM_CLUSTER_COUNT + \