Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- SPL size check for Gen5, i2c enablement for S10

diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
index 2745050810ff4509e72b1b2aed941a71bc6d3862..c5409df026ec1db7826841360c520853b53a43d2 100755 (executable)
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -9,6 +9,7 @@
        model = "SoCFPGA Stratix 10 SoCDK";
 
        aliases {
+               i2c0 = &i2c1;
                serial0 = &uart0;
        };
 
@@ -77,6 +78,10 @@
        };
 };
 
+&i2c1 {
+       status = "okay";
+};
+
 &mmc {
        status = "okay";
        cap-sd-highspeed;

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 48f02f08d4454a992b29c5e1eaeb49ab5d6ee3f7..1d914648e314fbfde805c3947c2a1d927b3fb486 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -3,6 +3,12 @@ if ARCH_SOCFPGA
 config NR_DRAM_BANKS
        default 1
 
+config SPL_SIZE_LIMIT
+       default 65536 if TARGET_SOCFPGA_GEN5
+
+config SPL_SIZE_LIMIT_PROVIDE_STACK
+       default 0x200 if TARGET_SOCFPGA_GEN5
+
 config SPL_STACK_R_ADDR
        default 0x00800000 if TARGET_SOCFPGA_GEN5
 
@@ -49,6 +55,8 @@ config TARGET_SOCFPGA_GEN5
        bool
        select SPL_ALTERA_SDRAM
        imply FPGA_SOCFPGA
+       imply SPL_SIZE_LIMIT_SUBTRACT_GD
+       imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
        imply SPL_STACK_R
        imply SPL_SYS_MALLOC_SIMPLE
        imply USE_TINY_PRINTF