ipq806x: 5.15: backport qcom clk fixes for krait and hfpll

Backport some qcom clock fixes for krait and hfpll driver.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

diff --git a/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch b/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch
new file mode 100644 (file)
index 0000000..3008fff
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.15/117-v6.0-01-clk-qcom-clk-hfpll-use-poll_timeout-macro.patch
@@ -0,0 +1,41 @@
+From fcfbfe373d41b4728ffec075f8f91b6572a88c27 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sat, 30 Apr 2022 07:44:56 +0200
+Subject: [PATCH 1/3] clk: qcom: clk-hfpll: use poll_timeout macro
+
+Use regmap_read_poll_timeout macro instead of do-while structure to tidy
+things up. Also set a timeout to prevent any sort of system stall.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/clk-hfpll.c | 15 +++++++++------
+ 1 file changed, 9 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/qcom/clk-hfpll.c
++++ b/drivers/clk/qcom/clk-hfpll.c
+@@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct cl
+       regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
+ 
+       /* Wait for PLL to lock. */
+-      if (hd->status_reg) {
+-              do {
+-                      regmap_read(regmap, hd->status_reg, &val);
+-              } while (!(val & BIT(hd->lock_bit)));
+-      } else {
++      if (hd->status_reg)
++              /*
++               * Busy wait. Should never timeout, we add a timeout to
++               * prevent any sort of stall.
++               */
++              regmap_read_poll_timeout(regmap, hd->status_reg, val,
++                                       !(val & BIT(hd->lock_bit)), 0,
++                                       100 * USEC_PER_MSEC);
++      else
+               udelay(60);
+-      }
+ 
+       /* Enable PLL output. */
+       regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);