York Sun <yorksun@freescale.com>
York Sun <york.sun@nxp.com>
Łukasz Majewski <l.majewski@samsung.com>
+Lukasz Majewski <lukma@denx.de>
Mirza <Taimoor_Mirza@mentor.com>
- BUILDMAN="arm11 arm7 arm920t arm946es"
- env:
- JOB="arm926ejs"
- BUILDMAN="arm926ejs -x mx,siemens,atmel"
+ BUILDMAN="arm926ejs -x mx,siemens,atmel,kirkwood"
- env:
- BUILDMAN="atmel"
- env:
- BUILDMAN="sandbox x86"
TOOLCHAIN="x86_64"
- env:
- - BUILDMAN="kirkwood"
+ - BUILDMAN="kirkwood -x openrd"
- env:
- BUILDMAN="mvebu"
- env:
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
- imply USE_BOOTCOMMAND
- select CMD_BOOTZ if ARM && !ARM64
+ select AUTO_COMPLETE
+ select CMDLINE_EDITING
select CMD_BOOTI if ARM64
+ select CMD_BOOTZ if ARM && !ARM64
select CMD_DHCP if CMD_NET
- select CMD_PING if CMD_NET
- select CMD_PXE if NET
select CMD_ENV_EXISTS
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
select CMD_FS_GENERIC
- imply CMD_MII if NET
select CMD_PART if PARTITIONS
+ select CMD_PING if CMD_NET
+ select CMD_PXE if NET
+ select ENV_VARS_UBOOT_CONFIG
select HUSH_PARSER
- select CMDLINE_EDITING
- select AUTO_COMPLETE
- select SYS_LONGHELP
select SUPPORT_RAW_INITRD
- select ENV_VARS_UBOOT_CONFIG
+ select SYS_LONGHELP
+ imply CMD_MII if NET
+ imply USE_BOOTCOMMAND
help
Select this to enable various options and commands which are suitable
for building u-boot for booting general purpose Linux distributions.
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
+config SYS_MALLOC_LEN
+ hex "Define memory for Dynamic allocation"
+ depends on ARCH_ZYNQ
+ help
+ This defines memory to be allocated for Dynamic allocation
+ TODO: Use for other architectures
+
config SPL_SYS_MALLOC_F_LEN
- hex "Size of malloc() pool in SPL before relocation"
- depends on SYS_MALLOC_F
- default SYS_MALLOC_F_LEN
- help
- Before relocation, memory is very limited on many platforms. Still,
- we can provide a small malloc() pool if needed. Driver model in
- particular needs this to operate, so that it can allocate the
- initial serial device and any others that are needed.
+ hex "Size of malloc() pool in SPL before relocation"
+ depends on SYS_MALLOC_F
+ default SYS_MALLOC_F_LEN
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
config TPL_SYS_MALLOC_F_LEN
- hex "Size of malloc() pool in TPL before relocation"
- depends on SYS_MALLOC_F
- default SYS_MALLOC_F_LEN
- help
- Before relocation, memory is very limited on many platforms. Still,
- we can provide a small malloc() pool if needed. Driver model in
- particular needs this to operate, so that it can allocate the
- initial serial device and any others that are needed.
+ hex "Size of malloc() pool in TPL before relocation"
+ depends on SYS_MALLOC_F
+ default SYS_MALLOC_F_LEN
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
config FIT_ENABLE_SHA256_SUPPORT
bool "Support SHA256 checksum of FIT image contents"
- select SHA256
default y
+ select SHA256
help
Enable this to support SHA256 checksum of FIT image contents. A
SHA256 checksum is a 256-bit (32-byte) hash value used to check that
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
depends on DM
- select RSA
select HASH
+ select RSA
help
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA. If
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
S: Maintained
L: uboot-snps-arc@synopsys.com
+F: doc/device-tree-bindings/gpio/snps,creg-gpio.txt
F: drivers/gpio/hsdk-creg-gpio.c
ARM
F: drivers/watchdog/cdns_wdt.c
F: include/zynqmppl.h
F: tools/zynqmp*
+N: ultra96
N: zynqmp
ARM ZYNQMP R5
F: include/efi*
F: include/pe.h
F: include/asm-generic/pe.h
+F: lib/charset.c
F: lib/efi*/
F: test/py/tests/test_efi*
F: cmd/bootefi.c
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2018
-PATCHLEVEL = 07
+PATCHLEVEL = 09
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
-ifdef CONFIG_TPL
-SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
+ifneq ($(CONFIG_SPL_PAYLOAD),)
+SPL_PAYLOAD := $(CONFIG_SPL_PAYLOAD:"%"=%)
else
SPL_PAYLOAD := u-boot.bin
endif
config ARC
bool "ARC architecture"
- select HAVE_PRIVATE_LIBGCC
- select SUPPORT_OF_CONTROL
select ARCH_EARLY_INIT_R
+ select ARC_TIMER
select CLK
+ select HAVE_PRIVATE_LIBGCC
+ select SUPPORT_OF_CONTROL
select TIMER
- select ARC_TIMER
config ARM
bool "ARM architecture"
config NIOS2
bool "Nios II architecture"
- select SUPPORT_OF_CONTROL
- select OF_CONTROL
- select DM
select CPU
+ select DM
+ select OF_CONTROL
+ select SUPPORT_OF_CONTROL
+ imply CMD_DM
config PPC
bool "PowerPC architecture"
config SANDBOX
bool "Sandbox"
select BOARD_LATE_INIT
- select SUPPORT_OF_CONTROL
select DM
+ select DM_GPIO
+ select DM_I2C
select DM_KEYBOARD
- select DM_SPI_FLASH
+ select DM_MMC
select DM_SERIAL
- select DM_I2C
select DM_SPI
- select DM_GPIO
- select DM_MMC
+ select DM_SPI_FLASH
select HAVE_BLOCK_DEVICE
- select SPI
select LZO
+ select SPI
+ select SUPPORT_OF_CONTROL
+ imply CMD_DM
imply CMD_GETTIME
imply CMD_HASH
imply CMD_IO
imply CMD_IOTRACE
imply CMD_LZMADEC
+ imply CMD_SATA
+ imply CMD_SF_TEST
imply CRC32_VERIFY
imply FAT_WRITE
imply HASH_VERIFY
imply LZMA
imply SCSI
- imply CMD_SATA
- imply CMD_SF_TEST
config SH
bool "SuperH architecture"
config X86
bool "x86 architecture"
select CREATE_ARCH_SYMLINK
- select HAVE_PRIVATE_LIBGCC
- select USE_PRIVATE_LIBGCC
- select SUPPORT_OF_CONTROL
- select OF_CONTROL
select DM
select DM_PCI
+ select HAVE_PRIVATE_LIBGCC
+ select OF_CONTROL
select PCI
+ select SUPPORT_OF_CONTROL
select TIMER
+ select USE_PRIVATE_LIBGCC
select X86_TSC_TIMER
imply BLK
+ imply CMD_DM
+ imply CMD_FPGA_LOADMK
+ imply CMD_GETTIME
+ imply CMD_IO
+ imply CMD_IRQ
+ imply CMD_PCI
+ imply CMD_SF_TEST
+ imply CMD_ZBOOT
imply DM_ETH
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
- imply DM_SERIAL
imply DM_SCSI
+ imply DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
imply DM_USB
imply DM_VIDEO
imply SYSRESET
imply SYSRESET_X86
- imply CMD_FPGA_LOADMK
- imply CMD_GETTIME
- imply CMD_IO
- imply CMD_IRQ
- imply CMD_PCI
- imply CMD_SF_TEST
- imply CMD_ZBOOT
- imply USB_HOST_ETHER
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
+ imply USB_HOST_ETHER
config XTENSA
bool "Xtensa architecture"
config CPU_ARC750D
bool "ARC 750D"
- select ARC_MMU_V2
depends on ISA_ARCOMPACT
+ select ARC_MMU_V2
help
Choose this option to build an U-Boot for ARC750D CPU.
config CPU_ARC770D
bool "ARC 770D"
- select ARC_MMU_V3
depends on ISA_ARCOMPACT
+ select ARC_MMU_V3
help
Choose this option to build an U-Boot for ARC770D CPU.
config CPU_ARCEM6
bool "ARC EM6"
- select ARC_MMU_ABSENT
depends on ISA_ARCV2
+ select ARC_MMU_ABSENT
help
Next Generation ARC Core based on ISA-v2 ISA without MMU.
config CPU_ARCHS36
bool "ARC HS36"
- select ARC_MMU_ABSENT
depends on ISA_ARCV2
+ select ARC_MMU_ABSENT
help
Next Generation ARC Core based on ISA-v2 ISA without MMU.
config CPU_ARCHS38
bool "ARC HS38"
- select ARC_MMU_V4
depends on ISA_ARCV2
+ select ARC_MMU_V4
help
Next Generation ARC Core based on ISA-v2 ISA with MMU.
*/
/ {
+ aliases {
+ spi0 = &spi0;
+ };
+
axs10x_mb@e0000000 {
compatible = "simple-bus";
#address-cells = <1>;
reg-shift = <2>;
reg-io-width = <4>;
};
+
+ spi0: spi@0 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <4000000>;
+ clocks = <&apbclk>;
+ clock-names = "spi_clk";
+ cs-gpio = <&cs_gpio 0>;
+ spi_flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+ };
+
+ cs_gpio: gpio@11218 {
+ compatible = "snps,creg-gpio";
+ reg = <0x11218 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "axs-spi-cs";
+ gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <1>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
+ };
};
};
};
cs_gpio: gpio@f00014b0 {
- compatible = "snps,hsdk-creg-gpio";
+ compatible = "snps,creg-gpio";
reg = <0xf00014b0 0x4>;
gpio-controller;
#gpio-cells = <1>;
gpio-bank-name = "hsdk-spi-cs";
gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <2>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
};
};
#define ARC_AUX_IDENTITY 0x04
#define ARC_AUX_STATUS32 0x0a
+/* STATUS32 Bits Positions */
+#define STATUS_AD_BIT 19 /* Enable unaligned access */
+
/* Instruction cache related auxiliary registers */
#define ARC_AUX_IC_IVIC 0x10
#define ARC_AUX_IC_CTRL 0x11
1:
#endif
+#ifdef __ARC_UNALIGNED__
+ /*
+ * Enable handling of unaligned access in the CPU as by default
+ * this HW feature is disabled while GCC starting from 8.1.0
+ * unconditionally uses it for ARC HS cores.
+ */
+ flag 1 << STATUS_AD_BIT
+#endif
+
/* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
bool
config ARM_ERRATA_845369
- bool
+ bool
config ARM_ERRATA_852421
bool
config CPU_V7A
bool
- select HAS_VBAR
select HAS_THUMB2
+ select HAS_VBAR
select SYS_CACHE_SHIFT_6
imply SYS_ARM_MMU
config CPU_V7M
bool
select HAS_THUMB2
- select THUMB2_KERNEL
- select SYS_CACHE_SHIFT_5
select SYS_ARM_MPU
+ select SYS_CACHE_SHIFT_5
select SYS_THUMB_BUILD
+ select THUMB2_KERNEL
config CPU_V7R
bool
select HAS_THUMB2
- select SYS_CACHE_SHIFT_6
- select SYS_ARM_MPU
select SYS_ARM_CACHE_CP15
+ select SYS_ARM_MPU
+ select SYS_CACHE_SHIFT_6
config CPU_PXA
bool
config KIRKWOOD
bool "Marvell Kirkwood"
- select CPU_ARM926EJS
- select BOARD_EARLY_INIT_F
select ARCH_MISC_INIT
+ select BOARD_EARLY_INIT_F
+ select CPU_ARM926EJS
config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
- select OF_CONTROL
- select OF_SEPARATE
select DM
select DM_ETH
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select OF_CONTROL
+ select OF_SEPARATE
select SPI
+ imply CMD_DM
config TARGET_DEVKIT3250
bool "Support devkit3250"
config TARGET_SPEAR300
bool "Support spear300"
- select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
- imply CMD_SAVES
+ select CPU_ARM926EJS
select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_SPEAR310
bool "Support spear310"
- select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
- imply CMD_SAVES
+ select CPU_ARM926EJS
select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_SPEAR320
bool "Support spear320"
- select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
- imply CMD_SAVES
+ select CPU_ARM926EJS
select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_SPEAR600
bool "Support spear600"
- select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
- imply CMD_SAVES
+ select CPU_ARM926EJS
select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_STV0991
bool "Support stv0991"
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select PL01X_SERIAL
select SPI
select SPI_FLASH
- select PL01X_SERIAL
+ imply CMD_DM
config TARGET_X600
bool "Support x600"
select BOARD_LATE_INIT
select CPU_ARM926EJS
- select SUPPORT_SPL
select PL011_SERIAL
+ select SUPPORT_SPL
config TARGET_WOODBURN
bool "Support woodburn"
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OF_CONTROL
select PL01X_SERIAL
select SERIAL_SEARCH_ALL
+ imply CMD_DM
imply FAT_WRITE
config TARGET_VEXPRESS_CA15_TC2
select DM
select OF_CONTROL
select OF_PRIOR_STAGE
+ imply CMD_DM
help
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7A
- imply CRC32_VERIFY
+ imply BCM_SF2_ETH
+ imply BCM_SF2_ETH_GMAC
imply CMD_HASH
+ imply CRC32_VERIFY
imply FAT_WRITE
imply HASH_VERIFY
imply NETDEVICES
- imply BCM_SF2_ETH
- imply BCM_SF2_ETH_GMAC
config TARGET_BCMNSP
bool "Support bcmnsp"
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select DM
+ select DM_GPIO
select DM_I2C
- select DM_SPI_FLASH
+ select DM_KEYBOARD
select DM_SERIAL
select DM_SPI
- select DM_GPIO
- select DM_KEYBOARD
+ select DM_SPI_FLASH
select SPI
+ imply CMD_DM
imply FAT_WRITE
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
select CPU_V7A
select DM
- select DM_SERIAL
select DM_GPIO
select DM_I2C
+ select DM_SERIAL
+ imply CMD_DM
config ARCH_HIGHBANK
bool "Calxeda Highbank"
select DM
select DM_SERIAL
select PL01X_SERIAL
+ imply CMD_DM
config ARCH_KEYSTONE
bool "TI Keystone"
+ select CMD_POWEROFF
select CPU_V7A
select SUPPORT_SPL
- select SYS_THUMB_BUILD
- select CMD_POWEROFF
select SYS_ARCH_TIMER
+ select SYS_THUMB_BUILD
imply CMD_MTDPARTS
- imply FIT
imply CMD_SAVES
+ imply FIT
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
select ARM64
select DM
select SUPPORT_SPL
+ imply CMD_DM
config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM1136
config ARCH_MX7ULP
- bool "NXP MX7ULP"
+ bool "NXP MX7ULP"
select CPU_V7A
select ROM_UNIFIED_SECTIONS
imply MXC_GPIO
config ARCH_MX7
bool "Freescale MX7"
+ select ARCH_MISC_INIT
+ select BOARD_EARLY_INIT_F
select CPU_V7A
select SYS_FSL_HAS_SEC if SECURE_BOOT
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
- select BOARD_EARLY_INIT_F
- select ARCH_MISC_INIT
imply MXC_GPIO
config ARCH_MX6
if ARCH_MX6
config SPL_LDSCRIPT
- default "arch/arm/mach-omap2/u-boot-spl.lds"
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
endif
config ARCH_MX5
bool "Freescale MX5"
- select CPU_V7A
select BOARD_EARLY_INIT_F
+ select CPU_V7A
imply MXC_GPIO
config ARCH_OWL
select DM
select DM_SERIAL
select OF_CONTROL
+ imply CMD_DM
config ARCH_QEMU
bool "QEMU Virtual Platform"
select DM_SERIAL
select OF_CONTROL
select PL01X_SERIAL
+ imply CMD_DM
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
+ select BOARD_EARLY_INIT_F
select DM
select DM_SERIAL
- select BOARD_EARLY_INIT_F
+ imply CMD_DM
imply FAT_WRITE
imply SYS_THUMB_BUILD
select DM
select DM_GPIO
select DM_SERIAL
- select SPMI
+ select MSM_SMEM
select OF_CONTROL
select OF_SEPARATE
select SMEM
- select MSM_SMEM
+ select SPMI
+ imply CMD_DM
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
+ select ARM64 if TARGET_SOCFPGA_STRATIX10
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
select SPL_DM_RESET if DM_RESET
+ select SPL_DM_SERIAL
select SPL_LIBCOMMON_SUPPORT
select SPL_LIBDISK_SUPPORT
select SPL_LIBGENERIC_SUPPORT
select SPL_MMC_SUPPORT if DM_MMC
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
+ select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
select SPL_SERIAL_SUPPORT
- select SPL_DM_SERIAL
select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
select SYS_NS16550
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select ARM64 if TARGET_SOCFPGA_STRATIX10
+ imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
imply DM_SPI
imply DM_SPI_FLASH
imply FAT_WRITE
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
select SPECIFY_CONSOLE_INDEX
select SPL_STACK_R if SPL
select SPL_SYS_MALLOC_SIMPLE if SPL
- select SYS_NS16550
select SPL_SYS_THUMB_BUILD if !ARM64
+ select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
- select USB_STORAGE if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS
+ select USB_STORAGE if DISTRO_DEFAULTS
select USE_TINY_PRINTF
+ imply CMD_DM
imply CMD_GPT
imply DISTRO_DEFAULTS
imply FAT_WRITE
config ARCH_ZYNQ
bool "Xilinx Zynq based platform"
+ select BOARD_EARLY_INIT_F if WDT
select BOARD_LATE_INIT
+ select CLK
+ select CLK_ZYNQ
select CPU_V7A
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_BOARD_INIT if SPL
- select BOARD_EARLY_INIT_F if WDT
- select SPL_OF_CONTROL if SPL
select DM
select DM_ETH if NET
- select SPL_DM if SPL
select DM_MMC if MMC
- select DM_SPI
select DM_SERIAL
+ select DM_SPI
select DM_SPI_FLASH
- select SPL_SEPARATE_BSS if SPL
select DM_USB if USB
- select CLK
- select SPL_CLK if SPL
- select CLK_ZYNQ
+ select OF_CONTROL
select SPI
+ select SPL_BOARD_INIT if SPL
+ select SPL_CLK if SPL
+ select SPL_DM if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SUPPORT_SPL
+ imply ARCH_EARLY_INIT_R
imply CMD_CLK
- imply FAT_WRITE
+ imply CMD_DM
imply CMD_SPL
- imply ARCH_EARLY_INIT_R
+ imply FAT_WRITE
config ARCH_ZYNQMP_R5
bool "Xilinx ZynqMP R5 based platform"
+ select CLK
select CPU_V7R
- select OF_CONTROL
select DM
select DM_SERIAL
- select CLK
+ select OF_CONTROL
+ imply CMD_DM
config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform"
select ARM64
select BOARD_LATE_INIT
+ select CLK
select DM
- select OF_CONTROL
select DM_SERIAL
- select SUPPORT_SPL
- select CLK
+ select DM_USB if USB
+ select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
- select DM_USB if USB
+ select SUPPORT_SPL
+ imply CMD_DM
imply FAT_WRITE
config TEGRA
config TARGET_VEXPRESS64_BASE_FVP
bool "Support Versatile Express ARMv8a FVP BASE model"
select ARM64
- select SEMIHOSTING
select PL01X_SERIAL
+ select SEMIHOSTING
config TARGET_VEXPRESS64_BASE_FVP_DRAM
bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM"
config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
- select ARCH_MISC_INIT
help
Support for Freescale LS2080A_EMU platform
The LS2080A Development System (EMULATOR) is a pre silicon
config TARGET_LS2080A_SIMU
bool "Support ls2080a_simu"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
- select ARCH_MISC_INIT
help
Support for Freescale LS2080A_SIMU platform
The LS2080A Development System (QDS) is a pre silicon
config TARGET_LS1088AQDS
bool "Support ls1088aqds"
select ARCH_LS1088A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
- select ARCH_MISC_INIT
select BOARD_LATE_INIT
select SUPPORT_SPL
help
config TARGET_LS2080AQDS
bool "Support ls2080aqds"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
select SUPPORT_SPL
- select ARCH_MISC_INIT
imply SCSI
imply SCSI_AHCI
help
config TARGET_LS2080ARDB
bool "Support ls2080ardb"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
select SUPPORT_SPL
- select ARCH_MISC_INIT
imply SCSI
imply SCSI_AHCI
help
config TARGET_LS2081ARDB
bool "Support ls2081ardb"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
select SUPPORT_SPL
- select ARCH_MISC_INIT
help
Support for Freescale LS2081ARDB platform.
The LS2081A Reference design board (RDB) is a high-performance
select OF_CONTROL
select PL01X_SERIAL
select SPECIFY_CONSOLE_INDEX
+ imply CMD_DM
help
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
bool "Support Poplar 96boards Enterprise Edition Platform"
select ARM64
select DM
- select OF_CONTROL
select DM_SERIAL
select DM_USB
+ select OF_CONTROL
select PL01X_SERIAL
+ imply CMD_DM
help
Support for Poplar 96boards EE platform. It features a HI3798cv200
SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
config TARGET_LS1012AFRWY
bool "Support ls1012afrwy"
select ARCH_LS1012A
- select BOARD_LATE_INIT
select ARM64
+ select BOARD_LATE_INIT
imply SCSI
imply SCSI_AHCI
help
config TARGET_LS1088ARDB
bool "Support ls1088ardb"
select ARCH_LS1088A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
- select ARCH_MISC_INIT
select BOARD_LATE_INIT
select SUPPORT_SPL
help
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select SUPPORT_SPL
- select ARCH_LS1021A
- select ARCH_SUPPORT_PSCI
select LS1_DEEP_SLEEP
+ select SUPPORT_SPL
select SYS_FSL_DDR
- select BOARD_EARLY_INIT_F
imply SCSI
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select SUPPORT_SPL
- select ARCH_LS1021A
- select ARCH_SUPPORT_PSCI
select LS1_DEEP_SLEEP
- select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
imply SCSI
config TARGET_LS1021AIOT
bool "Support ls1021aiot"
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
- select ARCH_LS1021A
- select ARCH_SUPPORT_PSCI
imply SCSI
help
Support for Freescale LS1021AIOT platform.
select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1043AQDS platform.
select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1043ARDB platform.
select ARCH_LS1046A
select ARM64
select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM_SPI_FLASH if DM_SPI
- select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
imply SCSI
help
Support for Freescale LS1046AQDS platform.
select ARCH_LS1046A
select ARM64
select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM_SPI_FLASH if DM_SPI
select POWER_MC34VR500
- select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
imply SCSI
help
Support for Freescale LS1046ARDB platform.
select SPL_OF_CONTROL if SPL
select SPL_PINCTRL if SPL
select SUPPORT_SPL
+ imply CMD_DM
imply DISTRO_DEFAULTS
imply FAT_WRITE
help
select DM
select DM_SERIAL
select SYS_THUMB_BUILD
+ imply CMD_DM
config ARCH_STI
bool "Support STMicrolectronics SoCs"
+ select BLK
select CPU_V7A
select DM
- select DM_SERIAL
- select BLK
select DM_MMC
select DM_RESET
+ select DM_SERIAL
+ imply CMD_DM
help
Support for STMicroelectronics STiH407/10 SoC family.
This SoC is used on Linaro 96Board STiH410-B2260
select DM_GPIO
select DM_RESET
select DM_SERIAL
+ select MISC
select OF_CONTROL
select OF_LIBFDT
- select MISC
select PINCTRL
select REGMAP
select SUPPORT_SPL
select SYSCON
select SYSRESET
select SYS_THUMB_BUILD
+ imply CMD_DM
help
Support for STM32MP SoC family developed by STMicroelectronics,
MPUs based on ARM cortex A core
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
- select OF_CONTROL
select BLK
select DM
- select SPL_DM if SPL
- select SYS_MALLOC_F
- select SYS_THUMB_BUILD if !ARM64
- select SPL_SYS_MALLOC_SIMPLE if SPL
select DM_GPIO
select DM_I2C
select DM_MMC
+ select DM_PWM
+ select DM_REGULATOR
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select DM_USB if USB
- select DM_PWM
- select DM_REGULATOR
select ENABLE_ARM_SOC_BOOT0_HOOK
+ select OF_CONTROL
select SPI
+ select SPL_DM if SPL
+ select SPL_SYS_MALLOC_SIMPLE if SPL
+ select SYS_MALLOC_F
+ select SYS_THUMB_BUILD if !ARM64
+ imply ADC
+ imply CMD_DM
imply DISTRO_DEFAULTS
imply FAT_WRITE
- imply USB_FUNCTION_FASTBOOT
- imply SPL_SYSRESET
- imply TPL_SYSRESET
- imply ADC
imply SARADC_ROCKCHIP
+ imply SPL_SYSRESET
imply SYS_NS16550
+ imply TPL_SYSRESET
+ imply USB_FUNCTION_FASTBOOT
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
select OF_CONTROL
- select SYS_CACHE_SHIFT_7
select PL01X_SERIAL
+ select SYS_CACHE_SHIFT_7
config ARCH_ASPEED
bool "Support Aspeed SoCs"
- select OF_CONTROL
select DM
+ select OF_CONTROL
+ imply CMD_DM
endchoice
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
-source "board/gdsys/a38x/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
endmenu
config SPL_LDSCRIPT
- default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
- default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
+ default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
+ default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
- -j .binman_sym_table
+ -j .binman_sym_table -j .text_rest
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
- -j .binman_sym_table
+ -j .binman_sym_table -j .text_rest
endif
# if a dtb section exists we always have to include it
config ARMV7_LPAE
bool "Use LPAE page table format" if EXPERT
depends on CPU_V7A
- default n
+ default y if ARMV7_VIRT
---help---
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
config ARCH_LS1021A
bool
+ select SYS_FSL_DDR_BE if SYS_FSL_DDR
+ select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008407
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_HAS_CCI400
- select SYS_FSL_SRDS_1
- select SYS_HAS_SERDES
- select SYS_FSL_DDR_BE if SYS_FSL_DDR
- select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+ imply CMD_PCI
imply SCSI
imply SCSI_AHCI
- imply CMD_PCI
menu "LS102xA architecture"
depends on ARCH_LS1021A
#ifdef CONFIG_ARMV7_VIRT
orreq r5, r5, #0x100 @ allow HVC instruction
moveq r6, #HYP_MODE @ Enter the kernel as HYP
+ mrseq r3, sp_svc
+ msreq sp_hyp, r3 @ migrate SP
#endif
mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
if ARM64
+config ARMV8_SPL_EXCEPTION_VECTORS
+ bool "Install crash dump exception vectors"
+ depends on SPL
+ default y
+ help
+ The default exception vector table is only used for the crash
+ dump, but still takes quite a lot of space in the image size.
+
+ Say N here if you are running out of code space in the image
+ and want to save some space at the cost of less debugging info.
+
config ARMV8_MULTIENTRY
bool "Enable multiple CPUs to enter into U-Boot"
menu "ARMv8 secure monitor firmware"
config ARMV8_SEC_FIRMWARE_SUPPORT
bool "Enable ARMv8 secure monitor firmware framework support"
- select OF_LIBFDT
select FIT
+ select OF_LIBFDT
help
This framework is aimed at making secure monitor firmware load
process brief.
config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
bool "Enable ARMv8 secure monitor firmware framework support for SPL"
- select SPL_OF_LIBFDT
select SPL_FIT
+ select SPL_OF_LIBFDT
help
Say Y here to support this framework in SPL phase.
obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
endif
obj-y += cache_v8.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o
+else
obj-y += exceptions.o
+endif
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
#include <linux/linkage.h>
/*
- * Exception vectors.
+ * AArch64 exception vectors:
+ * We have four types of exceptions:
+ * - synchronous: traps, data aborts, undefined instructions, ...
+ * - IRQ: group 1 (normal) interrupts
+ * - FIQ: group 0 or secure interrupts
+ * - SError: fatal system errors
+ * There are entries for all four of those for different contexts:
+ * - from same exception level, when using the SP_EL0 stack pointer
+ * - from same exception level, when using the SP_ELx stack pointer
+ * - from lower exception level, when this is AArch64
+ * - from lower exception level, when this is AArch32
+ * Each of those 16 entries have space for 32 instructions, each entry must
+ * be 128 byte aligned, the whole table must be 2K aligned.
+ * The 32 instructions are not enough to save and restore all registers and
+ * to branch to the actual handler, so we split this up:
+ * Each entry saves the LR, branches to the save routine, then to the actual
+ * handler, then to the restore routine. The save and restore routines are
+ * each split in half and stuffed in the unused gap between the entries.
+ * Also as we do not run anything in a lower exception level, we just provide
+ * the first 8 entries for exceptions from the same EL.
*/
.align 11
.globl vectors
bl do_bad_sync
b exception_exit
- .align 7 /* Current EL IRQ Thread */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_bad_irq
- b exception_exit
-
- .align 7 /* Current EL FIQ Thread */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_bad_fiq
- b exception_exit
-
- .align 7 /* Current EL Error Thread */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_bad_error
- b exception_exit
-
- .align 7 /* Current EL Synchronous Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_sync
- b exception_exit
-
- .align 7 /* Current EL IRQ Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_irq
- b exception_exit
-
- .align 7 /* Current EL FIQ Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_fiq
- b exception_exit
-
- .align 7 /* Current EL Error Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_error
- b exception_exit
-
/*
- * Enter Exception.
- * This will save the processor state that is ELR/X0~X30
- * to the stack frame.
+ * Save (most of) the GP registers to the stack frame.
+ * This is the first part of the shared routine called into from all entries.
*/
_exception_entry:
stp x27, x28, [sp, #-16]!
stp x5, x6, [sp, #-16]!
stp x3, x4, [sp, #-16]!
stp x1, x2, [sp, #-16]!
+ b _save_el_regs /* jump to the second part */
+ .align 7 /* Current EL IRQ Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_irq
+ b exception_exit
+
+/*
+ * Save exception specific context: ESR and ELR, for all exception levels.
+ * This is the second part of the shared routine called into from all entries.
+ */
+_save_el_regs:
/* Could be running at EL3/EL2/EL1 */
switch_el x11, 3f, 2f, 1f
3: mrs x1, esr_el3
mov x0, sp
ret
-
+ .align 7 /* Current EL FIQ Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_fiq
+ /* falling through to _exception_exit */
+/*
+ * Restore the exception return address, for all exception levels.
+ * This is the first part of the shared routine called into from all entries.
+ */
exception_exit:
ldp x2, x0, [sp],#16
switch_el x11, 3f, 2f, 1f
3: msr elr_el3, x2
- b 0f
+ b _restore_regs
2: msr elr_el2, x2
- b 0f
+ b _restore_regs
1: msr elr_el1, x2
-0:
+ b _restore_regs /* jump to the second part */
+
+ .align 7 /* Current EL Error Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_error
+ b exception_exit
+
+/*
+ * Restore the general purpose registers from the exception stack, then return.
+ * This is the second part of the shared routine called into from all entries.
+ */
+_restore_regs:
ldp x1, x2, [sp],#16
ldp x3, x4, [sp],#16
ldp x5, x6, [sp],#16
ldp x27, x28, [sp],#16
ldp x29, x30, [sp],#16
eret
+
+ .align 7 /* Current EL (SP_ELx) Synchronous Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_sync
+ b exception_exit
+
+ .align 7 /* Current EL (SP_ELx) IRQ Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_irq
+ b exception_exit
+
+ .align 7 /* Current EL (SP_ELx) FIQ Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_fiq
+ b exception_exit
+
+ .align 7 /* Current EL (SP_ELx) Error Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_error
+ b exception_exit
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/system.h>
+#include <fm_eth.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl_immap.h>
#include <asm/arch/mp.h>
#include <efi_loader.h>
-#include <fm_eth.h>
#include <fsl-mc/fsl_mc.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
The "loadables" is not optional. It tells SPL which images to load into memory.
+Falcon mode with QSPI boot
+--------------------------
+To use falcon mode with QSPI boot, SPL needs to be enabled. Similar to SD or
+NAND boot, a RAM version full feature U-Boot is needed. Unlike SD or NAND boot,
+SPL with QSPI doesn't need to combine SPL image with RAM version image. Two
+separated images are used, u-boot-spl.pbl and u-boot.img. The former is SPL
+image with RCW and PBI commands to load the SPL payload into On-Chip RAM. The
+latter is RAM version U-Boot in FIT format (or legacy format if FIT is not
+used).
+
Other things to consider
-----------------------
Falcon boot skips a lot of initialization in U-Boot. If Linux expects the
#include <common.h>
#include <fsl_immap.h>
#include <fsl_ifc.h>
-#include <ahci.h>
-#include <scsi.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
#endif
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci;
-
-#ifdef CONFIG_SYS_SATA2
- ccsr_ahci = (void *)CONFIG_SYS_SATA2;
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-#endif
-
-#ifdef CONFIG_SYS_SATA1
- ccsr_ahci = (void *)CONFIG_SYS_SATA1;
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
- ahci_init((void __iomem *)CONFIG_SYS_SATA1);
- scsi_scan(false);
-#endif
-
- return 0;
-}
-#endif
-
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
}
#elif defined(CONFIG_FSL_LSCH2)
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
-
- /* Disable SATA ECC */
- out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
- ahci_init((void __iomem *)CONFIG_SYS_SATA);
- scsi_scan(false);
-
- return 0;
-}
-#endif
static void erratum_a009929(void)
{
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- sata_init();
-#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
#include <fsl_csu.h>
#include <asm/arch/fdt.h>
#include <asm/arch/ppa.h>
+#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
return BOOT_DEVICE_NAND;
+#endif
+#ifdef CONFIG_QSPI_BOOT
+ return BOOT_DEVICE_NOR;
#endif
return 0;
}
void board_init_f(ulong dummy)
{
+ icache_enable();
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
board_early_init_f();
gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
gd->arch.tlb_allocated = gd->arch.tlb_addr;
#endif /* CONFIG_SPL_FSL_LS_PPA */
+#if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
+ qspi_ahb_init();
+#endif
}
#ifdef CONFIG_SPL_OS_BOOT
#ifdef CONFIG_SYS_RESET_SCTRL
bl reset_sctrl
+#endif
+
+#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+.macro set_vbar, regname, reg
+ msr \regname, \reg
+.endm
+ adr x0, vectors
+#else
+.macro set_vbar, regname, reg
+.endm
#endif
/*
* Could be EL3/EL2/EL1, Initial State:
* Little Endian, MMU Disabled, i/dCache Disabled
*/
- adr x0, vectors
switch_el x1, 3f, 2f, 1f
-3: msr vbar_el3, x0
+3: set_vbar vbar_el3, x0
mrs x0, scr_el3
orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
msr scr_el3, x0
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
#endif
b 0f
-2: msr vbar_el2, x0
+2: set_vbar vbar_el2, x0
mov x0, #0x33ff
msr cptr_el2, x0 /* Enable FP/SIMD */
b 0f
-1: msr vbar_el1, x0
+1: set_vbar vbar_el1, x0
mov x0, #3 << 20
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
/*-----------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
+#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
b 0f
1: msr vbar_el1, x0
0:
+#endif
ret
ENDPROC(c_runtime_cpu_setup)
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ __efi_runtime_stop = .;
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(8);
- .efi_runtime : {
- __efi_runtime_start = .;
- *(efi_runtime_text)
- *(efi_runtime_data)
- __efi_runtime_stop = .;
- }
-
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
- *(.relaefi_runtime_text)
- *(.relaefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
*(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(4);
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
- zynq-zybo.dtb
+ zynq-zybo.dtb \
+ zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
+ avnet-ultra96-rev1.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
+dtb-$(CONFIG_MACH_SUN50I_H6) += \
+ sun50i-h6-orangepi-one-plus.dtb \
+ sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
sun50i-a64-bananapi-m64.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+&spi1 {
+ u-boot,dm-spl;
+
+ spi-flash@0 {
+ u-boot,dm-spl;
+ };
+};
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-388.dtsi"
+#include "armada-38x-solidrun-microsom.dtsi"
/ {
model = "SolidRun Clearfog A1";
stdout-path = "serial0:115200n8";
};
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>; /* 256 MB */
- };
-
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
};
soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
-
internal-regs {
- ethernet@30000 {
- mac-address = [00 50 43 02 02 02];
- phy-mode = "sgmii";
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- ethernet@34000 {
- mac-address = [00 50 43 02 02 03];
- managed = "in-band-status";
- phy-mode = "sgmii";
- status = "okay";
- };
-
- ethernet@70000 {
- mac-address = [00 50 43 02 02 01];
- pinctrl-0 = <&ge0_rgmii_pins>;
- pinctrl-names = "default";
- phy = <&phy_dedicated>;
- phy-mode = "rgmii-id";
- status = "okay";
- };
-
- i2c@11000 {
- /* Is there anything on this? */
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /*
- * PCA9655 GPIO expander, up to 1MHz clock.
- * 0-CON3 CLKREQ#
- * 1-CON3 PERST#
- * 2-CON2 PERST#
- * 3-CON3 W_DISABLE
- * 4-CON2 CLKREQ#
- * 5-USB3 overcurrent
- * 6-USB3 power
- * 7-CON2 W_DISABLE
- * 8-JP4 P1
- * 9-JP4 P4
- * 10-JP4 P5
- * 11-m.2 DEVSLP
- * 12-SFP_LOS
- * 13-SFP_TX_FAULT
- * 14-SFP_TX_DISABLE
- * 15-SFP_MOD_DEF0
- */
- expander0: gpio-expander@20 {
- /*
- * This is how it should be:
- * compatible = "onnn,pca9655",
- * "nxp,pca9555";
- * but you can't do this because of
- * the way I2C works.
- */
- compatible = "nxp,pca9555";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x20>;
-
- pcie1_0_clkreq {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie1.0-clkreq";
- };
- pcie1_0_w_disable {
- gpio-hog;
- gpios = <3 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie1.0-w-disable";
- };
- pcie2_0_clkreq {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie2.0-clkreq";
- };
- pcie2_0_w_disable {
- gpio-hog;
- gpios = <7 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie2.0-w-disable";
- };
- usb3_ilimit {
- gpio-hog;
- gpios = <5 GPIO_ACTIVE_LOW>;
- input;
- line-name = "usb3-current-limit";
- };
- usb3_power {
- gpio-hog;
- gpios = <6 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb3-power";
- };
- m2_devslp {
- gpio-hog;
- gpios = <11 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "m.2 devslp";
- };
- };
-
- /* The MCP3021 is 100kHz clock only */
- mikrobus_adc: mcp3021@4c {
- compatible = "microchip,mcp3021";
- reg = <0x4c>;
- };
-
- /* Also something at 0x64 */
- };
-
- i2c@11100 {
- /*
- * Routed to SFP, mikrobus, and PCIe.
- * SFP limits this to 100kHz, and requires
- * an AT24C01A/02/04 with address pins tied
- * low, which takes addresses 0x50 and 0x51.
- * Mikrobus doesn't specify beyond an I2C
- * bus being present.
- * PCIe uses ARP to assign addresses, or
- * 0x63-0x64.
- */
- clock-frequency = <100000>;
- pinctrl-0 = <&clearfog_i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- mdio@72004 {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- phy_dedicated: ethernet-phy@0 {
- /*
- * Annoyingly, the marvell phy driver
- * configures the LED register, rather
- * than preserving reset-loaded setting.
- * We undo that rubbish here.
- */
- marvell,reg-init = <3 16 0 0x101e>;
- reg = <0>;
- };
- };
-
- pinctrl@18000 {
- clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
- marvell,pins = "mpp46";
- marvell,function = "ref";
- };
- clearfog_dsa0_pins: clearfog-dsa0-pins {
- marvell,pins = "mpp23", "mpp41";
- marvell,function = "gpio";
- };
- clearfog_i2c1_pins: i2c1-pins {
- /* SFP, PCIe, mSATA, mikrobus */
- marvell,pins = "mpp26", "mpp27";
- marvell,function = "i2c1";
- };
- clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
- marvell,pins = "mpp20";
- marvell,function = "gpio";
- };
- clearfog_sdhci_pins: clearfog-sdhci-pins {
- marvell,pins = "mpp21", "mpp28",
- "mpp37", "mpp38",
- "mpp39", "mpp40";
- marvell,function = "sd0";
- };
- clearfog_spi1_cs_pins: spi1-cs-pins {
- marvell,pins = "mpp55";
- marvell,function = "spi1";
- };
- mikro_pins: mikro-pins {
- /* int: mpp22 rst: mpp29 */
- marvell,pins = "mpp22", "mpp29";
- marvell,function = "gpio";
- };
- mikro_spi_pins: mikro-spi-pins {
- marvell,pins = "mpp43";
- marvell,function = "spi1";
- };
- mikro_uart_pins: mikro-uart-pins {
- marvell,pins = "mpp24", "mpp25";
- marvell,function = "ua1";
- };
- rear_button_pins: rear-button-pins {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
- };
-
rtc@a3800 {
/*
* If the rtc doesn't work, run "date reset"
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
- pinctrl-0 = <&clearfog_sdhci_pins
+ pinctrl-0 = <µsom_sdhci_pins
&clearfog_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
wp-inverted;
};
- serial@12000 {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
- status = "okay";
- u-boot,dm-pre-reloc;
- };
-
serial@12100 {
/* mikrobus uart */
pinctrl-0 = <&mikro_uart_pins>;
pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "w25q32", "jedec,spi-nor", "spi-flash";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <3000000>;
- };
};
- usb3@f8000 {
+ usb0: usb3@f8000 {
+ /* CON7, USB-A port on back of device */
status = "okay";
};
};
};
};
- sfp: sfp {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
- moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
- sfp,ethernet = <ð2>;
- tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
- };
-
- dsa@0 {
- compatible = "marvell,dsa";
- dsa,ethernet = <ð1>;
- dsa,mii-bus = <&mdio>;
- pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
- pinctrl-names = "default";
- #address-cells = <2>;
- #size-cells = <0>;
-
- switch@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4 0>;
-
- port@0 {
- reg = <0>;
- label = "lan1";
- };
-
- port@1 {
- reg = <1>;
- label = "lan2";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- };
-
- port@3 {
- reg = <3>;
- label = "lan4";
- };
-
- port@4 {
- reg = <4>;
- label = "lan5";
- };
-
- port@5 {
- reg = <5>;
- label = "cpu";
- };
-
- port@6 {
- /* 88E1512 external phy */
- reg = <6>;
- label = "lan6";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&rear_button_pins>;
};
};
+&w25q32 {
+ status = "okay";
+};
+
+ð1 {
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+ð2 {
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * PCA9655 GPIO expander, up to 1MHz clock.
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ expander0: gpio-expander@20 {
+ /*
+ * This is how it should be:
+ * compatible = "onnn,pca9655",
+ * "nxp,pca9555";
+ * but you can't do this because of
+ * the way I2C works.
+ */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+
+ pcie1_0_clkreq {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+ pcie1_0_w_disable {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+ usb3_ilimit {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+ usb3_power {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb3-power";
+ };
+ m2_devslp {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ };
+
+ mikrobus_adc: mcp3021@4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+};
+
+&i2c1 {
+ /*
+ * Routed to SFP, mikrobus, and PCIe.
+ * SFP limits this to 100kHz, and requires
+ * an AT24C01A/02/04 with address pins tied
+ * low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C
+ * bus being present.
+ * PCIe uses ARP to assign addresses, or
+ * 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&clearfog_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pinctrl {
+ clearfog_i2c1_pins: i2c1-pins {
+ /* SFP, PCIe, mSATA, mikrobus */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+ clearfog_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "spi1";
+ };
+ mikro_pins: mikro-pins {
+ /* int: mpp22 rst: mpp29 */
+ marvell,pins = "mpp22", "mpp29";
+ marvell,function = "gpio";
+ };
+ mikro_spi_pins: mikro-spi-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "spi1";
+ };
+ mikro_uart_pins: mikro-uart-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "ua1";
+ };
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+};
+
/*
+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
MPP18: gpio ? (pca9655 int?)
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
- pinctrl-0 = <&helios_sdhci_pins
+ pinctrl-0 = <µsom_sdhci_pins
&helios_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
marvell,pins = "mpp20";
marvell,function = "gpio";
};
- helios_sdhci_pins: helios-sdhci-pins {
- marvell,pins = "mpp21", "mpp28",
- "mpp37", "mpp38",
- "mpp39", "mpp40";
- marvell,function = "sd0";
- };
helios_led_pins: helios-led-pins {
marvell,pins = "mpp24", "mpp25",
"mpp49", "mpp50",
w25q32: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "w25q32", "jedec,spi-nor";
+ compatible = "w25q32", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
status = "disabled";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Avnet Ultra96 rev1
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp-zcu100-revC.dts"
+
+/ {
+ model = "Avnet Ultra96 Rev1";
+ compatible = "avnet,ultra96-rev1", "avnet,ultra96",
+ "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100",
+ "xlnx,zynqmp";
+};
&duart0 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
status = "okay";
phy_type = "ulpi";
};
+
+&sata {
+ status = "okay";
+};
&duart0 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+ sata: sata@3200000 {
+ compatible = "fsl,ls1012a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 69 4>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
usb0: usb2@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-98dx4122.dtsi"
+
+/ {
+ model = "Allied Telesis SBx81LIFXCAT Board";
+ compatible = "atl,SBx8LIFXCAT", "marvell,kirkwood-98DX4122",
+ "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>; /* 128 MB */
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ ethernet0 = ð0;
+ i2c0 = &i2c0;
+ spi0 = &spi0;
+ };
+
+ dsa {
+ compatible = "marvell,dsa";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ dsa,ethernet = <ð0>;
+ dsa,mii-bus = <&mdio>;
+ status = "okay";
+
+ switch@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1 0>;
+
+ port@0 {
+ reg = <0>;
+ label = "internal0";
+ };
+ port@1 {
+ reg = <1>;
+ label = "internal1";
+ };
+ port@8 {
+ reg = <8>;
+ label = "internal8";
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port@9 {
+ reg = <9>;
+ label = "internal9";
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port@10 {
+ reg = <10>;
+ label = "cpu";
+ };
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ ledn {
+ label = "status:ledn";
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ ledp {
+ label = "status:ledp";
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition@u-boot {
+ reg = <0x00000000 0x00c00000>;
+ label = "u-boot";
+ };
+ partition@u-boot-env {
+ reg = <0x00c00000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition@unused {
+ reg = <0x00100000 0x00f00000>;
+ label = "unused";
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ };
+
+ gpio3: gpio@76 {
+ #gpio-cells = <2>;
+ compatible = "nxp,pca9539";
+ reg = <0x76>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
+ð0 {
+ status = "okay";
+
+ ethernet0-port@0 {
+ speed = <1000>;
+ duplex = <1>;
+ };
+};
&sdio {
status = "okay";
vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi One Plus";
+ compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_cldo1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp805: pmic@36 {
+ compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x36>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ x-powers,self-working-mode;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-ac200";
+ };
+
+ reg_aldo3: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc25-dram";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-bias-pll";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-efuse-pcie-hdmi-io";
+ };
+
+ reg_bldo3: bldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dcxoio";
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ reg_cldo1: cldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+ };
+
+ reg_cldo2: cldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+ };
+
+ reg_cldo3: cldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <960000>;
+ regulator-max-microvolt = <960000>;
+ regulator-name = "vdd-sys";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Pine H64";
+ compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ label = "pine-h64:green:heartbeat";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ };
+
+ link {
+ label = "pine-h64:white:link";
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */
+ };
+
+ status {
+ label = "pine-h64:blue:status";
+ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_cldo1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <®_cldo1>;
+ vqmmc-supply = <®_bldo2>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp805: pmic@36 {
+ compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x36>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ x-powers,self-working-mode;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-ac200";
+ };
+
+ reg_aldo3: aldo3 {
+ /* This regulator is connected with CLDO1 */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3-1";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-bias-pll";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-efuse-pcie-hdmi-io";
+ };
+
+ reg_bldo3: bldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dcxoio";
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ reg_cldo1: cldo1 {
+ /* This regulator is connected with ALDO3 */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3-2";
+ };
+
+ reg_cldo2: cldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+ };
+
+ reg_cldo3: cldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <960000>;
+ regulator-max-microvolt = <960000>;
+ regulator-name = "vdd-sys";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun50i-h6-ccu.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ iosc: internal-osc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16000000>;
+ clock-accuracy = <300000000>;
+ clock-output-names = "iosc";
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h6-ccu";
+ reg = <0x03001000 0x1000>;
+ clocks = <&osc24M>, <&osc32k>, <&iosc>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ pio: pinctrl@300b000 {
+ compatible = "allwinner,sun50i-h6-pinctrl";
+ reg = <0x0300b000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_pins: mmc2-pins {
+ pins = "PC1", "PC4", "PC5", "PC6",
+ "PC7", "PC8", "PC9", "PC10",
+ "PC11", "PC12", "PC13", "PC14";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ uart0_ph_pins: uart0-ph {
+ pins = "PH0", "PH1";
+ function = "uart0";
+ };
+ };
+
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun50i-h6-mmc",
+ "allwinner,sun50i-a64-mmc";
+ reg = <0x04020000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun50i-h6-mmc",
+ "allwinner,sun50i-a64-mmc";
+ reg = <0x04021000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun50i-h6-emmc",
+ "allwinner,sun50i-a64-emmc";
+ reg = <0x04022000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: serial@5000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@5000400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@5000800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@5000c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ status = "disabled";
+ };
+
+ r_ccu: clock@7010000 {
+ compatible = "allwinner,sun50i-h6-r-ccu";
+ reg = <0x07010000 0x400>;
+ clocks = <&osc24M>, <&osc32k>, <&iosc>,
+ <&ccu CLK_PLL_PERIPH0>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ r_intc: interrupt-controller@7021000 {
+ compatible = "allwinner,sun50i-h6-r-intc",
+ "allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x07021000 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ r_pio: pinctrl@7022000 {
+ compatible = "allwinner,sun50i-h6-r-pinctrl";
+ reg = <0x07022000 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ r_i2c_pins: r-i2c {
+ pins = "PL0", "PL1";
+ function = "s_i2c";
+ };
+ };
+
+ r_i2c: i2c@7081400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x07081400 0x400>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB2_I2C>;
+ resets = <&r_ccu RST_R_APB2_I2C>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
filename = "spl/sunxi-spl.bin";
};
u-boot-img {
- pos = <CONFIG_SPL_PAD_TO>;
+ offset = <CONFIG_SPL_PAD_TO>;
};
};
};
u-boot-spl {
};
u-boot {
- pos = <(U_BOOT_OFFSET)>;
+ offset = <(U_BOOT_OFFSET)>;
};
};
u-boot-spl {
};
u-boot {
- pos = <(U_BOOT_OFFSET)>;
+ offset = <(U_BOOT_OFFSET)>;
};
};
u-boot-spl {
};
u-boot-nodtb {
- pos = <(U_BOOT_OFFSET)>;
+ offset = <(U_BOOT_OFFSET)>;
};
};
};
vccio-supply = <&sys_3v3_reg>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
/* SW1: +V1.35_VDDIO_DDR */
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v35";
vccio-supply = <&vdd_5v_in_reg>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v2";
regulator-min-microvolt = <1200000>;
#size-cells = <1>;
ranges;
- slcr: slcr@f8000000 {
+ slcr: slcr@f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
-
};
&dcc {
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
- fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll",
"iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x",
};
};
};
-
};
&dcc {
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
+ num-cs = <1>;
+ flash@0 {
+ compatible = "spansion,s25fl256s", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+ m25p,fast-read;
+ };
};
&sdhci0 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Digilent Zybo Z7 board";
+ compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ ld4 {
+ label = "zynq-zybo-z7:green:ld4";
+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ usb_phy0: phy0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&sdhci0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
reg = <0x0 0xff170000 0x0 0x1000>;
- clock-names = "clk_xin", "clk_xin";
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk_xin &clk_xin>;
xlnx,device_id = <1>;
};
};
#define SVR_DEV(svr) ((svr) >> 8)
#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
-/* ahci port register default value */
-#define AHCI_PORT_PHY_1_CFG 0xa003fffe
-#define AHCI_PORT_PHY2_CFG 0x28184d1f
-#define AHCI_PORT_PHY3_CFG 0x0e081509
-#define AHCI_PORT_TRANS_CFG 0x08000029
-#define AHCI_PORT_AXICC_CFG 0x3fffffff
-
#ifndef __ASSEMBLY__
-/* AHCI (sata) register map */
-struct ccsr_ahci {
- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
- u32 pcfg; /* port config */
- u32 ppcfg; /* port phy1 config */
- u32 pp2c; /* port phy2 config */
- u32 pp3c; /* port phy3 config */
- u32 pp4c; /* port phy4 config */
- u32 pp5c; /* port phy5 config */
- u32 axicc; /* AXI cache control */
- u32 paxic; /* port AXI config */
- u32 axipc; /* AXI PROT control */
- u32 ptc; /* port Trans Config */
- u32 pts; /* port Trans Status */
- u32 plc; /* port link config */
- u32 plc1; /* port link config1 */
- u32 plc2; /* port link config2 */
- u32 pls; /* port link status */
- u32 pls1; /* port link status1 */
- u32 pcmdc; /* port CMD config */
- u32 ppcs; /* port phy control status */
- u32 pberr; /* port 0/1 BIST error */
- u32 cmds; /* port 0/1 CMD status error */
-};
-
#ifdef CONFIG_FSL_LSCH3
void fsl_lsch3_early_init_f(void);
int get_core_volt_from_fuse(void);
void init_pfe_scfg_dcfg_regs(void);
#endif
#endif
+#ifdef CONFIG_QSPI_AHB_INIT
+int qspi_ahb_init(void);
+#endif
void cpu_name(char *name);
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
.word 0xf57ff06f // isb sy
.word 0xe320f003 // wfi
.word 0xeafffffd // b @wfi
+#ifndef CONFIG_MACH_SUN50I_H6
.word 0x017000a0 // writeable RVBAR mapping address
+#else
+ .word 0x09010040 // writeable RVBAR mapping address
+#endif
#ifdef CONFIG_SPL_BUILD
.word CONFIG_SPL_TEXT_BASE
#else
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/clock_sun8i_a83t.h>
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include <asm/arch/clock_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
defined(CONFIG_MACH_SUN50I)
#include <asm/arch/clock_sun6i.h>
--- /dev/null
+/*
+ * Allwinner H6 clock register definitions
+ *
+ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN50I_H6_H
+#define _SUNXI_CLOCK_SUN50I_H6_H
+
+struct sunxi_ccm_reg {
+ u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
+ u8 reserved_0x004[12];
+ u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
+ u8 reserved_0x014[12];
+ u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
+ u8 reserved_0x020[4];
+ u32 pll_periph1_cfg; /* 0x028 pll periph1 control */
+ u8 reserved_0x028[4];
+ u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
+ u8 reserved_0x034[12];
+ u32 pll3_cfg; /* 0x040 pll3 (video0) control */
+ u8 reserved_0x044[4];
+ u32 pll_video1_cfg; /* 0x048 pll video1 control */
+ u8 reserved_0x04c[12];
+ u32 pll4_cfg; /* 0x058 pll4 (ve) control */
+ u8 reserved_0x05c[4];
+ u32 pll10_cfg; /* 0x060 pll10 (de) control */
+ u8 reserved_0x064[12];
+ u32 pll9_cfg; /* 0x070 pll9 (hsic) control */
+ u8 reserved_0x074[4];
+ u32 pll2_cfg; /* 0x078 pll2 (audio) control */
+ u8 reserved_0x07c[148];
+ u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */
+ u8 reserved_0x114[20];
+ u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */
+ u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */
+ u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */
+ u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */
+ u8 reserved_0x138[8];
+ u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */
+ u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */
+ u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */
+ u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */
+ u8 reserved_0x150[8];
+ u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */
+ u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */
+ u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */
+ u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */
+ u8 reserved_0x168[8];
+ u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */
+ u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */
+ u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */
+ u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */
+ u8 reserved_0x180[384];
+ u32 pll1_bias; /* 0x300 pll1 (cpux) bias */
+ u8 reserved_0x304[12];
+ u32 pll5_bias; /* 0x310 pll5 (ddr) bias */
+ u8 reserved_0x314[12];
+ u32 pll6_bias; /* 0x320 pll6 (periph0) bias */
+ u8 reserved_0x324[4];
+ u32 pll_periph1_bias; /* 0x328 pll periph1 bias */
+ u8 reserved_0x32c[4];
+ u32 pll7_bias; /* 0x330 pll7 (gpu) bias */
+ u8 reserved_0x334[12];
+ u32 pll3_bias; /* 0x340 pll3 (video0) bias */
+ u8 reserved_0x344[4];
+ u32 pll_video1_bias; /* 0x348 pll video1 bias */
+ u8 reserved_0x34c[12];
+ u32 pll4_bias; /* 0x358 pll4 (ve) bias */
+ u8 reserved_0x35c[4];
+ u32 pll10_bias; /* 0x360 pll10 (de) bias */
+ u8 reserved_0x364[12];
+ u32 pll9_bias; /* 0x370 pll9 (hsic) bias */
+ u8 reserved_0x374[4];
+ u32 pll2_bias; /* 0x378 pll2 (audio) bias */
+ u8 reserved_0x37c[132];
+ u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */
+ u8 reserved_0x404[252];
+ u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/
+ u8 reserved_0x504[12];
+ u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */
+ u8 reserved_0x514[8];
+ u32 ahb3_cfg; /* 0x51c AHB3 clock control */
+ u32 apb1_cfg; /* 0x520 APB1 clock control */
+ u32 apb2_cfg; /* 0x524 APB2 clock control */
+ u8 reserved_0x528[24];
+ u32 mbus_cfg; /* 0x540 MBUS clock control */
+ u8 reserved_0x544[188];
+ u32 de_clk_cfg; /* 0x600 DE clock control */
+ u8 reserved_0x604[8];
+ u32 de_gate_reset; /* 0x60c DE gate/reset control */
+ u8 reserved_0x610[16];
+ u32 di_clk_cfg; /* 0x620 DI clock control */
+ u8 reserved_0x024[8];
+ u32 di_gate_reset; /* 0x62c DI gate/reset control */
+ u8 reserved_0x630[64];
+ u32 gpu_clk_cfg; /* 0x670 GPU clock control */
+ u8 reserved_0x674[8];
+ u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */
+ u32 ce_clk_cfg; /* 0x680 CE clock control */
+ u8 reserved_0x684[8];
+ u32 ce_gate_reset; /* 0x68c CE gate/reset control */
+ u32 ve_clk_cfg; /* 0x690 VE clock control */
+ u8 reserved_0x694[8];
+ u32 ve_gate_reset; /* 0x69c VE gate/reset control */
+ u8 reserved_0x6a0[16];
+ u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */
+ u8 reserved_0x6b4[8];
+ u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */
+ u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */
+ u8 reserved_0x6c4[8];
+ u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */
+ u8 reserved_0x6d0[60];
+ u32 dma_gate_reset; /* 0x70c DMA gate/reset control */
+ u8 reserved_0x710[12];
+ u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */
+ u8 reserved_0x720[12];
+ u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */
+ u8 reserved_0x730[12];
+ u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */
+ u32 avs_gate_reset; /* 0x740 AVS gate/reset control */
+ u8 reserved_0x744[72];
+ u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */
+ u8 reserved_0x790[12];
+ u32 psi_gate_reset; /* 0x79c PSI gate/reset control */
+ u8 reserved_0x7a0[12];
+ u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */
+ u8 reserved_0x7b0[12];
+ u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */
+ u8 reserved_0x7c0[64];
+ u32 dram_clk_cfg; /* 0x800 DRAM clock control */
+ u32 mbus_gate; /* 0x804 MBUS gate control */
+ u8 reserved_0x808[4];
+ u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */
+ u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */
+ u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */
+ u8 reserved_0x818[20];
+ u32 nand_gate_reset; /* 0x82c NAND gate/reset control */
+ u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */
+ u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */
+ u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */
+ u8 reserved_0x83c[16];
+ u32 sd_gate_reset; /* 0x84c MMC gate/reset control */
+ u8 reserved_0x850[188];
+ u32 uart_gate_reset; /* 0x90c UART gate/reset control */
+ u8 reserved_0x910[12];
+ u32 twi_gate_reset; /* 0x91c I2C gate/reset control */
+ u8 reserved_0x920[28];
+ u32 scr_gate_reset; /* 0x93c SCR gate/reset control */
+ u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */
+ u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */
+ u8 reserved_0x948[36];
+ u32 spi_gate_reset; /* 0x96c SPI gate/reset control */
+ u8 reserved_0x970[12];
+ u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */
+ u8 reserved_0x980[48];
+ u32 ts_clk_cfg; /* 0x9b0 TS clock control */
+ u8 reserved_0x9b4[8];
+ u32 ts_gate_reset; /* 0x9bc TS gate/reset control */
+ u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */
+ u8 reserved_0x9c4[8];
+ u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */
+ u8 reserved_0x9d0[44];
+ u32 ths_gate_reset; /* 0x9fc THS gate/reset control */
+ u8 reserved_0xa00[12];
+ u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */
+ u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */
+ u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */
+ u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */
+ u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */
+ u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */
+ u8 reserved_0xa24[8];
+ u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */
+ u8 reserved_0xa30[16];
+ u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */
+ u8 reserved_0xa44[8];
+ u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */
+ u8 reserved_0xa50[16];
+ u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */
+ u8 reserved_0xa64[8];
+ u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */
+ u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */
+ u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */
+ u8 reserved_0xa78[4];
+ u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */
+ u8 reserved_0xa80[12];
+ u32 usb_gate_reset; /* 0xa8c USB gate/reset control */
+ u8 reserved_0xa90[32];
+ u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */
+ u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */
+ u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */
+ u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */
+ u8 reserved_0xac0[64];
+ u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */
+ u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */
+ u8 reserved_0xb08[8];
+ u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */
+ u8 reserved_0xb14[8];
+ u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */
+ u8 reserved_0xb20[60];
+ u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */
+ u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */
+ u8 reserved_0xb64[24];
+ u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */
+ u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */
+ u8 reserved_0xb84[24];
+ u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */
+ u8 reserved_0xba0[96];
+ u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */
+ u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */
+ u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */
+ u8 reserved_0xc0c[32];
+ u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */
+ u8 reserved_0xc30[16];
+ u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */
+ u8 reserved_0xc44[8];
+ u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */
+ u8 reserved_0xc50[688];
+ u32 ccu_sec_switch; /* 0xf00 CCU security switch */
+ u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */
+};
+
+/* pll1 bit field */
+#define CCM_PLL1_CTRL_EN BIT(31)
+#define CCM_PLL1_LOCK_EN BIT(29)
+#define CCM_PLL1_LOCK BIT(28)
+#define CCM_PLL1_CLOCK_TIME_2 (2 << 24)
+#define CCM_PLL1_CTRL_P(p) ((p) << 16)
+#define CCM_PLL1_CTRL_N(n) ((n) << 8)
+
+/* pll5 bit field */
+#define CCM_PLL5_CTRL_EN BIT(31)
+#define CCM_PLL5_LOCK_EN BIT(29)
+#define CCM_PLL5_LOCK BIT(28)
+#define CCM_PLL5_CTRL_N(n) ((n) << 8)
+#define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0)
+#define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1)
+
+/* pll6 bit field */
+#define CCM_PLL6_CTRL_EN BIT(31)
+#define CCM_PLL6_LOCK_EN BIT(29)
+#define CCM_PLL6_LOCK BIT(28)
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_DIV1_SHIFT 0
+#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT)
+#define CCM_PLL6_CTRL_DIV2_SHIFT 1
+#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT)
+#define CCM_PLL6_DEFAULT 0xa0006300
+
+/* cpu_axi bit field*/
+#define CCM_CPU_AXI_MUX_MASK (0x3 << 24)
+#define CCM_CPU_AXI_MUX_OSC24M (0x0 << 24)
+#define CCM_CPU_AXI_MUX_PLL_CPUX (0x3 << 24)
+#define CCM_CPU_AXI_APB_MASK 0x300
+#define CCM_CPU_AXI_AXI_MASK 0x3
+#define CCM_CPU_AXI_DEFAULT_FACTORS 0x301
+
+/* psi_ahb1_ahb2 bit field */
+#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102
+
+/* ahb3 bit field */
+#define CCM_AHB3_DEFAULT 0x03000002
+
+/* apb1 bit field */
+#define CCM_APB1_DEFAULT 0x03000102
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_OSC24M (0x0 << 24)
+#define APB2_CLK_SRC_OSC32K (0x1 << 24)
+#define APB2_CLK_SRC_PSI (0x2 << 24)
+#define APB2_CLK_SRC_PLL6 (0x3 << 24)
+#define APB2_CLK_SRC_MASK (0x3 << 24)
+#define APB2_CLK_RATE_N_1 (0x0 << 8)
+#define APB2_CLK_RATE_N_2 (0x1 << 8)
+#define APB2_CLK_RATE_N_4 (0x2 << 8)
+#define APB2_CLK_RATE_N_8 (0x3 << 8)
+#define APB2_CLK_RATE_N_MASK (3 << 8)
+#define APB2_CLK_RATE_M(m) (((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK (3 << 0)
+
+/* MBUS clock bit field */
+#define MBUS_ENABLE BIT(31)
+#define MBUS_RESET BIT(30)
+#define MBUS_CLK_SRC_MASK GENMASK(25, 24)
+#define MBUS_CLK_SRC_OSCM24 (0 << 24)
+#define MBUS_CLK_SRC_PLL6X2 (1 << 24)
+#define MBUS_CLK_SRC_PLL5 (2 << 24)
+#define MBUS_CLK_SRC_PLL6X4 (3 << 24)
+#define MBUS_CLK_M(m) (((m)-1) << 0)
+
+/* Module gate/reset shift*/
+#define RESET_SHIFT (16)
+
+/* DRAM clock bit field */
+#define DRAM_MOD_RESET BIT(30)
+#define DRAM_CLK_UPDATE BIT(27)
+#define DRAM_CLK_SRC_MASK GENMASK(25, 24)
+#define DRAM_CLK_SRC_PLL5 (0 << 24)
+#define DRAM_CLK_M(m) (((m)-1) << 0)
+
+/* MMC clock bit field */
+#define CCM_MMC_CTRL_M(x) ((x) - 1)
+#define CCM_MMC_CTRL_N(x) ((x) << 8)
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6X2 (0x1 << 24)
+#define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24)
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+/* H6 doesn't have these delays */
+#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0)
+#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0)
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+unsigned int clock_get_pll6(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN50I_H6_H */
#if defined(CONFIG_MACH_SUN9I)
#include <asm/arch/cpu_sun9i.h>
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include <asm/arch/cpu_sun50i_h6.h>
#else
#include <asm/arch/cpu_sun4i.h>
#endif
--- /dev/null
+/*
+ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN50I_H6_H
+#define _SUNXI_CPU_SUN50I_H6_H
+
+#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS
+#define SUNXI_SRAM_C_BASE 0x00028000
+#define SUNXI_SRAM_A2_BASE 0x00100000
+
+#define SUNXI_DE3_BASE 0x01000000
+#define SUNXI_SS_BASE 0x01904000
+#define SUNXI_EMCE_BASE 0x01905000
+
+#define SUNXI_SRAMC_BASE 0x03000000
+#define SUNXI_CCM_BASE 0x03001000
+#define SUNXI_DMA_BASE 0x03002000
+/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
+#define SUNXI_SIDC_BASE 0x03006000
+#define SNUXI_SID_BASE 0x03006200
+#define SUNXI_TIMER_BASE 0x03009000
+#define SUNXI_PIO_BASE 0x0300B000
+#define SUNXI_PSI_BASE 0x0300C000
+
+#define SUNXI_GIC400_BASE 0x03020000
+#define SUNXI_IOMMU_BASE 0x030F0000
+
+#define SUNXI_DRAM_COM_BASE 0x04002000
+#define SUNXI_DRAM_CTL0_BASE 0x04003000
+#define SUNXI_DRAM_PHY0_BASE 0x04005000
+#define SUNXI_NFC_BASE 0x04011000
+#define SUNXI_MMC0_BASE 0x04020000
+#define SUNXI_MMC1_BASE 0x04021000
+#define SUNXI_MMC2_BASE 0x04022000
+
+#define SUNXI_UART0_BASE 0x05000000
+#define SUNXI_UART1_BASE 0x05000400
+#define SUNXI_UART2_BASE 0x05000800
+#define SUNXI_UART3_BASE 0x05000C00
+#define SUNXI_TWI0_BASE 0x05002000
+#define SUNXI_TWI1_BASE 0x05002400
+#define SUNXI_TWI2_BASE 0x05002800
+#define SUNXI_TWI3_BASE 0x05002C00
+#define SUNXI_SPI0_BASE 0x05010000
+#define SUNXI_SPI1_BASE 0x05011000
+#define SUNXI_GMAC_BASE 0x05020000
+#define SUNXI_USB0_BASE 0x05100000
+#define SUNXI_XHCI_BASE 0x05200000
+#define SUNXI_USB3_BASE 0x05311000
+#define SUNXI_PCIE_BASE 0x05400000
+
+#define SUNXI_HDMI_BASE 0x06000000
+#define SUNXI_TCON_TOP_BASE 0x06510000
+#define SUNXI_TCON_LCD0_BASE 0x06511000
+#define SUNXI_TCON_TV0_BASE 0x06515000
+
+#define SUNXI_RTC_BASE 0x07000000
+#define SUNXI_R_CPUCFG_BASE 0x07000400
+#define SUNXI_PRCM_BASE 0x07010000
+#define SUNXI_R_PIO_BASE 0x07022000
+#define SUNXI_R_UART_BASE 0x07080000
+#define SUNXI_R_TWI_BASE 0x07081400
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif
+
+#endif /* _SUNXI_CPU_SUN9I_H */
#include <asm/arch/dram_sunxi_dw.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/dram_sun9i.h>
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include <asm/arch/dram_sun50i_h6.h>
#else
#include <asm/arch/dram_sun4i.h>
#endif
--- /dev/null
+/*
+ * H6 dram controller register and constant defines
+ *
+ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN50I_H6_H
+#define _SUNXI_DRAM_SUN50I_H6_H
+
+enum sunxi_dram_type {
+ SUNXI_DRAM_TYPE_DDR3 = 3,
+ SUNXI_DRAM_TYPE_DDR4,
+ SUNXI_DRAM_TYPE_LPDDR2 = 6,
+ SUNXI_DRAM_TYPE_LPDDR3,
+};
+
+/*
+ * The following information is mainly retrieved by disassembly and some FPGA
+ * test code of sun50iw3 platform.
+ */
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x000 control register */
+ u8 reserved_0x004[4]; /* 0x004 */
+ u32 unk_0x008; /* 0x008 */
+ u32 tmr; /* 0x00c timer register */
+ u8 reserved_0x010[4]; /* 0x010 */
+ u32 unk_0x014; /* 0x014 */
+ u8 reserved_0x018[8]; /* 0x018 */
+ u32 maer0; /* 0x020 master enable register 0 */
+ u32 maer1; /* 0x024 master enable register 1 */
+ u32 maer2; /* 0x028 master enable register 2 */
+ u8 reserved_0x02c[468]; /* 0x02c */
+ u32 bwcr; /* 0x200 bandwidth control register */
+ u8 reserved_0x204[12]; /* 0x204 */
+ /*
+ * The last master configured by BSP libdram is at 0x49x, so the
+ * size of this struct array is set to 41 (0x29) now.
+ */
+ struct {
+ u32 cfg0; /* 0x0 */
+ u32 cfg1; /* 0x4 */
+ u8 reserved_0x8[8]; /* 0x8 */
+ } master[41]; /* 0x210 + index * 0x10 */
+};
+check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498);
+
+/*
+ * The following register information are retrieved from some similar DRAM
+ * controllers, including the DRAM controllers in Allwinner A23/A80 SoCs,
+ * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs.
+ *
+ * The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems
+ * to be older than the one in Allwinner H6, as the DRAMTMG9 register
+ * is missing in these SoCs. (From the product specifications of these
+ * SoCs they're not capable of DDR4)
+ *
+ * Information sources:
+ * - dram_sun9i.h and dram_sun8i_a23.h in the same directory.
+ * - sdram_rk3328.h from the RK3328 TPL DRAM patchset
+ * - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM)
+ * - Zynq UltraScale+ MPSoC Register Reference (UG1087)
+ */
+struct sunxi_mctl_ctl_reg {
+ u32 mstr; /* 0x000 */
+ u32 statr; /* 0x004 unused */
+ u32 mstr1; /* 0x008 unused */
+ u32 unk_0x00c; /* 0x00c */
+ u32 mrctrl0; /* 0x010 unused */
+ u32 mrctrl1; /* 0x014 unused */
+ u32 mrstatr; /* 0x018 unused */
+ u32 mrctrl2; /* 0x01c unused */
+ u32 derateen; /* 0x020 unused */
+ u32 derateint; /* 0x024 unused */
+ u8 reserved_0x028[8]; /* 0x028 */
+ u32 pwrctl; /* 0x030 unused */
+ u32 pwrtmg; /* 0x034 unused */
+ u32 hwlpctl; /* 0x038 unused */
+ u8 reserved_0x03c[20]; /* 0x03c */
+ u32 rfshctl0; /* 0x050 unused */
+ u32 rfshctl1; /* 0x054 unused */
+ u8 reserved_0x058[8]; /* 0x05c */
+ u32 rfshctl3; /* 0x060 */
+ u32 rfshtmg; /* 0x064 */
+ u8 reserved_0x068[104]; /* 0x068 reserved for ECC&CRC (from ZynqMP) */
+ u32 init[8]; /* 0x0d0 */
+ u32 dimmctl; /* 0x0f0 unused */
+ u32 rankctl; /* 0x0f4 */
+ u8 reserved_0x0f8[8]; /* 0x0f8 */
+ u32 dramtmg[17]; /* 0x100 */
+ u8 reserved_0x144[60]; /* 0x144 */
+ u32 zqctl[3]; /* 0x180 */
+ u32 zqstat; /* 0x18c unused */
+ u32 dfitmg0; /* 0x190 */
+ u32 dfitmg1; /* 0x194 */
+ u32 dfilpcfg[2]; /* 0x198 unused */
+ u32 dfiupd[3]; /* 0x1a0 */
+ u32 reserved_0x1ac; /* 0x1ac */
+ u32 dfimisc; /* 0x1b0 */
+ u32 dfitmg2; /* 0x1b4 unused, may not exist */
+ u8 reserved_0x1b8[8]; /* 0x1b8 */
+ u32 dbictl; /* 0x1c0 */
+ u8 reserved_0x1c4[60]; /* 0x1c4 */
+ u32 addrmap[12]; /* 0x200 */
+ u8 reserved_0x230[16]; /* 0x230 */
+ u32 odtcfg; /* 0x240 */
+ u32 odtmap; /* 0x244 */
+ u8 reserved_0x248[8]; /* 0x248 */
+ u32 sched[2]; /* 0x250 */
+ u8 reserved_0x258[180]; /* 0x258 */
+ u32 dbgcmd; /* 0x30c unused */
+ u32 dbgstat; /* 0x310 unused */
+ u8 reserved_0x314[12]; /* 0x314 */
+ u32 swctl; /* 0x320 */
+ u32 swstat; /* 0x324 */
+};
+check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
+
+#define MSTR_DEVICETYPE_DDR3 BIT(0)
+#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
+#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
+#define MSTR_DEVICETYPE_DDR4 BIT(4)
+#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
+#define MSTR_2TMODE BIT(10)
+#define MSTR_BUSWIDTH_FULL (0 << 12)
+#define MSTR_BUSWIDTH_HALF (1 << 12)
+#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24)
+#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16)
+
+/*
+ * The following register information is based on Zynq UltraScale+
+ * MPSoC Register Reference, as it's the currently only known
+ * DDR PHY similar to the one used in H6; however although the
+ * map is similar, the bit fields definitions are different.
+ *
+ * Other DesignWare DDR PHY's have similar register names, but the
+ * offset and definitions are both different.
+ */
+struct sunxi_mctl_phy_reg {
+ u32 ver; /* 0x000 guess based on similar PHYs */
+ u32 pir; /* 0x004 */
+ u8 reserved_0x008[8]; /* 0x008 */
+ /*
+ * The ZynqMP manual didn't document PGCR1, however this register
+ * exists on H6 and referenced by libdram.
+ */
+ u32 pgcr[8]; /* 0x010 */
+ /*
+ * By comparing the hardware and the ZynqMP manual, the PGSR seems
+ * to start at 0x34 on H6.
+ */
+ u8 reserved_0x030[4]; /* 0x030 */
+ u32 pgsr[3]; /* 0x034 */
+ u32 ptr[7]; /* 0x040 */
+ /*
+ * According to ZynqMP reference there's PLLCR0~6 in this area,
+ * but they're tagged "Type B PLL Only" and H6 seems to have
+ * no them.
+ * 0x080 is not present in ZynqMP reference but it seems to be
+ * present on H6.
+ */
+ u8 reserved_0x05c[36]; /* 0x05c */
+ u32 unk_0x080; /* 0x080 */
+ u8 reserved_0x084[4]; /* 0x084 */
+ u32 dxccr; /* 0x088 */
+ u8 reserved_0x08c[4]; /* 0x08c */
+ u32 dsgcr; /* 0x090 */
+ u8 reserved_0x094[4]; /* 0x094 */
+ u32 odtcr; /* 0x098 */
+ u8 reserved_0x09c[4]; /* 0x09c */
+ u32 aacr; /* 0x0a0 */
+ u8 reserved_0x0a4[32]; /* 0x0a4 */
+ u32 gpr1; /* 0x0c4 */
+ u8 reserved_0x0c8[56]; /* 0x0c8 */
+ u32 dcr; /* 0x100 */
+ u8 reserved_0x104[12]; /* 0x104 */
+ u32 dtpr[7]; /* 0x110 */
+ u8 reserved_0x12c[20]; /* 0x12c */
+ u32 rdimmgcr[3]; /* 0x140 */
+ u8 reserved_0x14c[4]; /* 0x14c */
+ u32 rdimmcr[5]; /* 0x150 */
+ u8 reserved_0x164[4]; /* 0x164 */
+ u32 schcr[2]; /* 0x168 */
+ u8 reserved_0x170[16]; /* 0x170 */
+ /*
+ * The ZynqMP manual documents MR0~7, 11~14 and 22.
+ */
+ u32 mr[23]; /* 0x180 */
+ u8 reserved_0x1dc[36]; /* 0x1dc */
+ u32 dtcr[2]; /* 0x200 */
+ u32 dtar[3]; /* 0x208 */
+ u8 reserved_0x214[4]; /* 0x214 */
+ u32 dtdr[2]; /* 0x218 */
+ u8 reserved_0x220[16]; /* 0x220 */
+ u32 dtedr0; /* 0x230 */
+ u32 dtedr1; /* 0x234 */
+ u32 dtedr2; /* 0x238 */
+ u32 vtdr; /* 0x23c */
+ u32 catr[2]; /* 0x240 */
+ u8 reserved_0x248[8];
+ u32 dqsdr[3]; /* 0x250 */
+ u32 dtedr3; /* 0x25c */
+ u8 reserved_0x260[160]; /* 0x260 */
+ u32 dcuar; /* 0x300 */
+ u32 dcudr; /* 0x304 */
+ u32 dcurr; /* 0x308 */
+ u32 dculr; /* 0x30c */
+ u32 dcugcr; /* 0x310 */
+ u32 dcutpr; /* 0x314 */
+ u32 dcusr[2]; /* 0x318 */
+ u8 reserved_0x320[444]; /* 0x320 */
+ u32 rankidr; /* 0x4dc */
+ u32 riocr[6]; /* 0x4e0 */
+ u8 reserved_0x4f8[8]; /* 0x4f8 */
+ u32 aciocr[6]; /* 0x500 */
+ u8 reserved_0x518[8]; /* 0x518 */
+ u32 iovcr[2]; /* 0x520 */
+ u32 vtcr[2]; /* 0x528 */
+ u8 reserved_0x530[16]; /* 0x530 */
+ u32 acbdlr[17]; /* 0x540 */
+ u32 aclcdlr; /* 0x584 */
+ u8 reserved_0x588[24]; /* 0x588 */
+ u32 acmdlr[2]; /* 0x5a0 */
+ u8 reserved_0x5a8[216]; /* 0x5a8 */
+ struct {
+ u32 zqcr; /* 0x00 only the first one valid */
+ u32 zqpr[2]; /* 0x04 */
+ u32 zqdr[2]; /* 0x0c */
+ u32 zqor[2]; /* 0x14 */
+ u32 zqsr; /* 0x1c */
+ } zq[2]; /* 0x680, 0x6a0 */
+ u8 reserved_0x6c0[64]; /* 0x6c0 */
+ struct {
+ u32 gcr[7]; /* 0x00 */
+ u8 reserved_0x1c[36]; /* 0x1c */
+ u32 bdlr0; /* 0x40 */
+ u32 bdlr1; /* 0x44 */
+ u32 bdlr2; /* 0x48 */
+ u8 reserved_0x4c[4]; /* 0x4c */
+ u32 bdlr3; /* 0x50 */
+ u32 bdlr4; /* 0x54 */
+ u32 bdlr5; /* 0x58 */
+ u8 reserved_0x5c[4]; /* 0x5c */
+ u32 bdlr6; /* 0x60 */
+ u8 reserved_0x64[28]; /* 0x64 */
+ u32 lcdlr[6]; /* 0x80 */
+ u8 reserved_0x98[8]; /* 0x98 */
+ u32 mdlr[2]; /* 0xa0 */
+ u8 reserved_0xa8[24]; /* 0xa8 */
+ u32 gtr0; /* 0xc0 */
+ u8 reserved_0xc4[12]; /* 0xc4 */
+ /*
+ * DXnRSR0 is not documented in ZynqMP manual but
+ * it's used in libdram.
+ */
+ u32 rsr[4]; /* 0xd0 */
+ u32 gsr[4]; /* 0xe0 */
+ u8 reserved_0xf0[16]; /* 0xf0 */
+ } dx[4]; /* 0x700, 0x800, 0x900, 0xa00 */
+};
+check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
+
+#define PIR_INIT BIT(0)
+#define PIR_ZCAL BIT(1)
+#define PIR_CA BIT(2)
+#define PIR_PLLINIT BIT(4)
+#define PIR_DCAL BIT(5)
+#define PIR_PHYRST BIT(6)
+#define PIR_DRAMRST BIT(7)
+#define PIR_DRAMINIT BIT(8)
+#define PIR_WL BIT(9)
+#define PIR_QSGATE BIT(10)
+#define PIR_WLADJ BIT(11)
+#define PIR_RDDSKW BIT(12)
+#define PIR_WRDSKW BIT(13)
+#define PIR_RDEYE BIT(14)
+#define PIR_WREYE BIT(15)
+#define PIR_VREF BIT(17)
+#define PIR_CTLDINIT BIT(18)
+#define PIR_DQS2DQ BIT(20)
+#define PIR_DCALPSE BIT(29)
+#define PIR_ZCALBYP BIT(30)
+
+#define DCR_LPDDR3 (1 << 0)
+#define DCR_DDR3 (3 << 0)
+#define DCR_DDR4 (4 << 0)
+#define DCR_DDR8BANK BIT(3)
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+ return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+#endif /* _SUNXI_DRAM_SUN50I_H6_H */
#define SUN6I_GPH_TWI2 2
#define SUN6I_GPH_UART0 2
#define SUN9I_GPH_UART0 2
+#define SUN50I_H6_GPH_UART0 2
#define SUNXI_GPI_SDC3 2
#define SUN7I_GPI_TWI3 3
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res2[26];
-#ifdef CONFIG_SUNXI_GEN_SUN6I
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
u32 res3[64];
#endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */
#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
#define SPL_HEADER_VERSION 2
-#ifdef CONFIG_SUNXI_HIGH_SRAM
-#define SPL_ADDR 0x10000
-#else
-#define SPL_ADDR 0x0
-#endif
+#define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS
/* The low 8-bits of the 'boot_media' field in the SPL header */
#define SUNXI_BOOTED_FROM_MMC0 0
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
-#elif defined(CONFIG_SUNXI_GEN_SUN6I)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif
u32 flow_dbg_cnt0; /* offset 0x48 */
u32 flow_dbg_cnt1; /* offset 0x4c */
u32 flow_dbg_qual; /* offset 0x50 */
- u32 flow_ctlr_spare; /* offset 0x54 */
+ u32 flow_ctrl_spare; /* offset 0x54 */
u32 ram_repair_cluster1;/* offset 0x58 */
};
#define CSR_WAIT_WFI_SHIFT 8
#define CSR_PWR_OFF_STS (1 << 16)
-/* RAM_REPAIR, 0x40, 0x58 */
-enum {
- RAM_REPAIR_REQ = 0x1 << 0,
- RAM_REPAIR_STS = 0x1 << 1,
-};
+#define RAM_REPAIR_REQ BIT(0)
+#define RAM_REPAIR_STS BIT(1)
+#define RAM_REPAIR_BYPASS_EN BIT(2)
#endif /* _TEGRA124_FLOW_H_ */
#define FIQ_MODE 0x11
#define IRQ_MODE 0x12
#define SVC_MODE 0x13
+#define MON_MODE 0x16
#define ABT_MODE 0x17
#define HYP_MODE 0x1a
#define UND_MODE 0x1b
psci_ver = sec_firmware_support_psci_version();
#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
+#elif defined(CONFIG_ARMV7_PSCI_0_2)
+ psci_ver = ARM_PSCI_VER_0_2;
#endif
if (psci_ver >= ARM_PSCI_VER_1_0) {
tmp = fdt_setprop_string(fdt, nodeoff,
if (tmp)
return tmp;
+ tmp = fdt_setprop_string(fdt, nodeoff, "status", "okay");
+ if (tmp)
+ return tmp;
+
#endif
return 0;
}
bool "Support snapper9260"
select AT91SAM9260
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_GURNARD
bool "Support gurnard"
select AT91SAM9G45
select BOARD_LATE_INIT
select DM
+ select DM_ETH
+ select DM_GPIO
select DM_SERIAL
select DM_SPI
- select DM_GPIO
- select DM_ETH
select SPI
+ imply CMD_DM
config TARGET_AT91SAM9261EK
bool "Atmel at91sam9261 reference board"
config TARGET_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK board"
select AT91SAM9M10G45
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
config TARGET_PM9G45
bool "Ronetix pm9g45 board"
config TARGET_AT91SAM9N12EK
bool "Atmel AT91SAM9N12-EK board"
select AT91SAM9N12
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
config TARGET_AT91SAM9RLEK
bool "Atmel at91sam9rl reference board"
config TARGET_AT91SAM9X5EK
bool "Atmel AT91SAM9X5-EK board"
select AT91SAM9X5
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SUPPORT_SPL
config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
- select SAMA5D2
select BOARD_EARLY_INIT_F
+ select SAMA5D2
config TARGET_SAMA5D2_XPLAINED
bool "SAMA5D2 Xplained board"
- select SAMA5D2
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SAMA5D2
+ select SUPPORT_SPL
config TARGET_SAMA5D27_SOM1_EK
bool "SAMA5D27 SOM1 EK board"
- select CPU_V7A
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select CPU_V7A
+ select SUPPORT_SPL
help
The SAMA5D27 SOM1 embeds SAMA5D2 SiP(System in Package),
a 64Mbit QSPI flash, KSZ8081 Phy and a Mac-address EEPROM
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
+ select BOARD_EARLY_INIT_F
select SAMA5D3
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
config TARGET_SAMA5D3XEK
bool "SAMA5D3X-EK board"
- select SAMA5D3
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SAMA5D3
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
config TARGET_SAMA5D4_XPLAINED
bool "SAMA5D4 Xplained board"
- select SAMA5D4
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SAMA5D4
+ select SUPPORT_SPL
config TARGET_SAMA5D4EK
bool "SAMA5D4 Evaluation Kit"
- select SAMA5D4
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SAMA5D4
+ select SUPPORT_SPL
config TARGET_MEESC
bool "Support meesc"
config TARGET_CORVUS
bool "Support corvus"
select AT91SAM9M10G45
- select SUPPORT_SPL
select DM
- select DM_SERIAL
- select DM_GPIO
select DM_ETH
+ select DM_GPIO
+ select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_TAURUS
bool "Support taurus"
select AT91SAM9G20
- select SUPPORT_SPL
select DM
+ select DM_ETH
+ select DM_GPIO
select DM_SERIAL
select DM_SPI
- select DM_GPIO
- select DM_ETH
select SPI
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_SMARTWEB
bool "Support smartweb"
select AT91SAM9260
- select SUPPORT_SPL
select DM
- select DM_SERIAL
- select DM_GPIO
select DM_ETH
+ select DM_GPIO
+ select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_VINCO
bool "Support VINCO"
- select SAMA5D4
- select SUPPORT_SPL
select DM
select DM_SPI
+ select SAMA5D4
select SPI
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_WB45N
bool "Support Laird WB45N"
config TARGET_WB50N
bool "Support Laird WB50N"
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
endchoice
config TARGET_EA20
bool "EA20 board"
+ select BOARD_LATE_INIT
select MACH_DAVINCI_DA850_EVM
select SOC_DA850
- select BOARD_LATE_INIT
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
config SOC_DA8XX
bool
- select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
+ select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
config MACH_DAVINCI_DA850_EVM
bool
config ARCH_EXYNOS4
bool "Exynos4 SoC family"
- select CPU_V7A
select BOARD_EARLY_INIT_F
+ select CPU_V7A
help
Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
are multiple SoCs in this family including Exynos4210, Exynos4412,
config ARCH_EXYNOS5
bool "Exynos5 SoC family"
- select CPU_V7A
select BOARD_EARLY_INIT_F
+ select CPU_V7A
select SHA_HW_ACCEL
- imply CRC32_VERIFY
imply CMD_HASH
+ imply CRC32_VERIFY
imply HASH_VERIFY
- imply USB_ETHER_RTL8152
imply USB_ETHER_ASIX
+ imply USB_ETHER_RTL8152
imply USB_ETHER_SMSC95XX
help
Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
prompt "EXYNOS4 board select"
config TARGET_SMDKV310
- select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_TRATS
bool "Exynos4210 Trats board"
select ARM_ERRATA_774769
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_SMDK5250
bool "SMDK5250 board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_SNOW
bool "Snow board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_SPRING
bool "Spring board"
- select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
+ select SUPPORT_SPL
config TARGET_SMDK5420
bool "SMDK5420 board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_PEACH_PI
bool "Peach Pi board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_PEACH_PIT
bool "Peach Pit board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
endchoice
endif
bool "ESPRESSO7420 board"
select ARM64
select ARMV8_MULTIENTRY
- select SUPPORT_SPL
+ select CLK_EXYNOS
select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
select PINCTRL
select PINCTRL_EXYNOS7420
- select CLK_EXYNOS
+ select SPL_DISABLE_OF_CONTROL
+ select SUPPORT_SPL
endchoice
endif
config TARGET_MX31PDK
bool "Support the i.MX31 PDK board from Freescale/NXP"
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
endchoice
if ARCH_MX5
config MX5
- select GPT_TIMER
bool
default y
+ select GPT_TIMER
config MX51
bool
- select SYS_FSL_ERRATUM_ESDHC_A001
select ARM_CORTEX_A8_CVE_2017_5715
+ select SYS_FSL_ERRATUM_ESDHC_A001
config MX53
bool
config TARGET_KP_IMX53
bool "Support K+P imx53 board"
select BOARD_LATE_INIT
- select MX53
select DM
- select DM_SERIAL
select DM_ETH
- select DM_I2C
select DM_GPIO
+ select DM_I2C
select DM_PMIC
+ select DM_SERIAL
+ select MX53
+ imply CMD_DM
config TARGET_MX51EVK
bool "Support mx51evk"
config TARGET_MX53CX9020
bool "Support CX9020"
select BOARD_LATE_INIT
- select MX53
select DM
select DM_SERIAL
+ select MX53
+ imply CMD_DM
config TARGET_MX53EVK
bool "Support mx53evk"
if ARCH_MX6
config MX6_SMP
+ bool
select ARM_ERRATA_751472
select ARM_ERRATA_761320
select ARM_ERRATA_794072
select ARM_ERRATA_845369
select MP
- bool
config MX6
- select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
- select GPT_TIMER if !MX6UL && !MX6ULL
bool
default y
+ select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
+ select GPT_TIMER if !MX6UL && !MX6ULL
imply CMD_FUSE
config MX6D
+ bool
select HAS_CAAM
select MX6_SMP
- bool
config MX6DL
+ bool
select HAS_CAAM
select MX6_SMP
- bool
config MX6Q
+ bool
select HAS_CAAM
select MX6_SMP
- bool
config MX6QDL
+ bool
select HAS_CAAM
select MX6_SMP
- bool
config MX6S
- select HAS_CAAM
bool
+ select HAS_CAAM
config MX6SL
bool
config MX6SX
+ bool
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
- bool
config MX6SLL
- select ROM_UNIFIED_SECTIONS
bool
+ select ROM_UNIFIED_SECTIONS
config MX6UL
+ bool
select HAS_CAAM
- select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
select SYSCOUNTER_TIMER
- bool
+ select SYS_L2CACHE_OFF
config MX6UL_LITESOM
bool
- select MX6UL
select DM
select DM_THERMAL
+ select MX6UL
select SUPPORT_SPL
+ imply CMD_DM
config MX6UL_OPOS6UL
bool
- select MX6UL
select BOARD_LATE_INIT
select DM
select DM_GPIO
select DM_MMC
select DM_THERMAL
- select SUPPORT_SPL
+ select MX6UL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
- select SPL_SEPARATE_BSS if SPL
select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SUPPORT_SPL
+ imply CMD_DM
config MX6ULL
- select SYS_L2CACHE_OFF
+ bool
select ROM_UNIFIED_SECTIONS
select SYSCOUNTER_TIMER
- bool
+ select SYS_L2CACHE_OFF
config MX6_DDRCAL
bool "Include dynamic DDR calibration routines"
config TARGET_APALIS_IMX6
bool "Toradex Apalis iMX6 board"
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_SERIAL
select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
imply CMD_SATA
config TARGET_ARISTAINETOS
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
- select MX6QDL
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_CM_FX6
bool "CM-FX6"
- select SUPPORT_SPL
- select MX6QDL
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_COLIBRI_IMX6
bool "Toradex Colibri iMX6 board"
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_SERIAL
select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_COLIBRI_IMX6ULL
bool "Toradex Colibri iMX6ULL"
config TARGET_DHCOMIMX6
bool "dh_imx6"
- select MX6QDL
- select BOARD_LATE_INIT
select BOARD_EARLY_INIT_F
- select SUPPORT_SPL
+ select BOARD_LATE_INIT
select DM
select DM_THERMAL
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
imply CMD_SPL
config TARGET_DISPLAY5
bool "LWN DISPLAY5 board"
- select SUPPORT_SPL
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
- select MX6QDL
select BOARD_LATE_INIT
+ select MX6QDL
select SUPPORT_SPL
config TARGET_MX6LOGICPD
select DM_MMC
select DM_PMIC
select OF_CONTROL
+ imply CMD_DM
config TARGET_MX6MEMCAL
bool "mx6memcal"
config TARGET_MX6DL_MAMOJ
bool "Support BTicino Mamoj"
- select MX6QDL
- select OF_CONTROL
- select PINCTRL
select DM
select DM_ETH
select DM_GPIO
select DM_PMIC
select DM_PMIC_PFUZE100
select DM_THERMAL
+ select MX6QDL
+ select OF_CONTROL
+ select PINCTRL
select SPL
- select SUPPORT_SPL
select SPL_DM if SPL
- select SPL_OF_LIBFDT if SPL
- select SPL_OF_CONTROL if SPL
- select SPL_PINCTRL if SPL
- select SPL_SEPARATE_BSS if SPL
select SPL_GPIO_SUPPORT if SPL
select SPL_LIBCOMMON_SUPPORT if SPL
select SPL_LIBDISK_SUPPORT if SPL
select SPL_LIBGENERIC_SUPPORT if SPL
select SPL_MMC_SUPPORT if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_OF_LIBFDT if SPL
+ select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
select SPL_SERIAL_SUPPORT if SPL
- select SPL_USB_HOST_SUPPORT if SPL
select SPL_USB_GADGET_SUPPORT if SPL
+ select SPL_USB_HOST_SUPPORT if SPL
select SPL_USB_SDP_SUPPORT if SPL
select SPL_WATCHDOG_SUPPORT if SPL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6Q_ENGICAM
bool "Support Engicam i.Core(RQS)"
select BOARD_LATE_INIT
- select MX6QDL
- select OF_CONTROL
- select SPL_OF_LIBFDT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_THERMAL
- select SUPPORT_SPL
+ select MX6QDL
+ select OF_CONTROL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
- select SPL_SEPARATE_BSS if SPL
+ select SPL_OF_LIBFDT
select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6SABREAUTO
bool "mx6sabreauto"
- select MX6QDL
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
- select BOARD_EARLY_INIT_F
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6SABRESD
bool "mx6sabresd"
- select MX6QDL
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
- select BOARD_EARLY_INIT_F
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6SLEVK
bool "mx6slevk"
select SUPPORT_SPL
config TARGET_MX6SLLEVK
- bool "mx6sll evk"
+ bool "mx6sll evk"
select BOARD_LATE_INIT
- select MX6SLL
- select DM
- select DM_THERMAL
+ select DM
+ select DM_THERMAL
+ select MX6SLL
+ imply CMD_DM
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select MX6SX
- select SUPPORT_SPL
select DM
select DM_THERMAL
- select BOARD_EARLY_INIT_F
+ select MX6SX
+ select SUPPORT_SPL
config TARGET_MX6SXSABREAUTO
- bool "mx6sxsabreauto"
+ bool "mx6sxsabreauto"
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
select MX6SX
- select DM
- select DM_THERMAL
- select BOARD_EARLY_INIT_F
+ imply CMD_DM
config TARGET_MX6UL_9X9_EVK
bool "mx6ul_9x9_evk"
select BOARD_LATE_INIT
- select MX6UL
select DM
select DM_THERMAL
+ select MX6UL
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6UL_14X14_EVK
- select BOARD_LATE_INIT
bool "mx6ul_14x14_evk"
- select MX6UL
+ select BOARD_LATE_INIT
select DM
select DM_THERMAL
+ select MX6UL
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
select BOARD_LATE_INIT
- select MX6UL
- select OF_CONTROL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_THERMAL
- select SUPPORT_SPL
+ select MX6UL
+ select OF_CONTROL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
- select SPL_SEPARATE_BSS if SPL
select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
select BOARD_LATE_INIT
- select MX6ULL
select DM
select DM_THERMAL
+ select MX6ULL
+ imply CMD_DM
config TARGET_NITROGEN6X
bool "nitrogen6x"
- imply USB_HOST_ETHER
imply USB_ETHER_ASIX
- imply USB_ETHER_SMSC95XX
imply USB_ETHER_MCS7830
+ imply USB_ETHER_SMSC95XX
+ imply USB_HOST_ETHER
config TARGET_OPOS6ULDEV
bool "Armadeus OPOS6ULDev board"
config TARGET_PFLA02
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
- select MX6QDL
select BOARD_LATE_INIT
+ select MX6QDL
select SUPPORT_SPL
config TARGET_SECOMX6
config TARGET_KP_IMX6Q_TPC
bool "K+P KP_IMX6Q_TPC i.MX6 Quad"
- select MX6QDL
- select BOARD_LATE_INIT
select BOARD_EARLY_INIT_F
- select SUPPORT_SPL
+ select BOARD_LATE_INIT
select DM
select DM_THERMAL
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
imply CMD_SPL
config TARGET_TQMA6
config TARGET_UDOO
bool "udoo"
- select MX6QDL
select BOARD_LATE_INIT
+ select MX6QDL
select SUPPORT_SPL
config TARGET_UDOO_NEO
bool "UDOO Neo"
select BOARD_LATE_INIT
- select SUPPORT_SPL
- select MX6SX
select DM
select DM_THERMAL
+ select MX6SX
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_SAMTEC_VINING_2000
bool "samtec VIN|ING 2000"
select BOARD_LATE_INIT
- select MX6SX
select DM
select DM_THERMAL
+ select MX6SX
+ imply CMD_DM
config TARGET_WANDBOARD
bool "wandboard"
- select MX6QDL
select BOARD_LATE_INIT
+ select MX6QDL
select SUPPORT_SPL
config TARGET_WARP
bool "WaRP"
- select MX6SL
select BOARD_LATE_INIT
+ select MX6SL
config TARGET_XPRESS
bool "CCV xPress"
select BOARD_LATE_INIT
- select MX6UL
select DM
select DM_THERMAL
+ select MX6UL
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_ZC5202
bool "zc5202"
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_ZC5601
bool "zc5601"
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
endchoice
config MX7
bool
+ default y
+ select ARCH_SUPPORT_PSCI
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select ROM_UNIFIED_SECTIONS
select SYSCOUNTER_TIMER
- select CPU_V7_HAS_VIRT
- select CPU_V7_HAS_NONSEC
- select ARCH_SUPPORT_PSCI
imply CMD_FUSE
- default y
config MX7D
+ bool
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
imply CMD_FUSE
- bool
choice
prompt "MX7 board select"
config TARGET_CL_SOM_IMX7
bool "CL-SOM-iMX7"
- select MX7D
select DM
select DM_THERMAL
+ select MX7D
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX7DSABRESD
bool "mx7dsabresd"
select BOARD_LATE_INIT
- select MX7D
select DM
select DM_THERMAL
+ select MX7D
+ imply CMD_DM
config TARGET_PICO_IMX7D
bool "pico-imx7d"
select BOARD_LATE_INIT
- select MX7D
select DM
select DM_THERMAL
+ select MX7D
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_WARP7
bool "warp7"
select BOARD_LATE_INIT
- select MX7D
select DM
select DM_THERMAL
+ select MX7D
+ imply CMD_DM
config TARGET_COLIBRI_IMX7
bool "Support Colibri iMX7S/iMX7D modules"
select DM
select DM_SERIAL
select DM_THERMAL
+ imply CMD_DM
endchoice
config TARGET_SBx81LIFKW
bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
+config TARGET_SBx81LIFXCAT
+ bool "Allied Telesis SBx81GP24/SBx81GT24"
+
endchoice
config SYS_SOC
source "board/Seagate/nas220/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
+source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
endif
select CLK
select DM
select DM_SERIAL
+ imply CMD_DM
help
The Amlogic Meson GXBaby (S905) is an ARM SoC with a
quad-core Cortex-A53 CPU and a Mali-450 GPU.
select CLK
select DM
select DM_SERIAL
+ imply CMD_DM
help
The Amlogic Meson GXL (S905X and S905D) is an ARM SoC with a
quad-core Cortex-A53 CPU and a Mali-450 GPU.
--- /dev/null
+kwbimage.cfg
config ARMADA_32BIT
bool
+ select ARCH_MISC_INIT
+ select BOARD_EARLY_INIT_F
select CPU_V7A
- select SUPPORT_SPL
select SPL_DM
select SPL_DM_SEQ_ALIAS
select SPL_OF_CONTROL
select SPL_SIMPLE_BUS
- select BOARD_EARLY_INIT_F
- select ARCH_MISC_INIT
+ select SUPPORT_SPL
config ARMADA_64BIT
bool
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
default "theadorable" if TARGET_THEADORABLE
+ default "a38x" if TARGET_CONTROLCENTERDC
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
default "theadorable" if TARGET_THEADORABLE
default "turris_omnia" if TARGET_TURRIS_OMNIA
default "turris_mox" if TARGET_TURRIS_MOX
+ default "controlcenterdc" if TARGET_CONTROLCENTERDC
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
default "Synology" if TARGET_DS414
default "CZ.NIC" if TARGET_TURRIS_OMNIA
default "CZ.NIC" if TARGET_TURRIS_MOX
+ default "gdsys" if TARGET_CONTROLCENTERDC
config SYS_SOC
default "mvebu"
-if TARGET_TURRIS_OMNIA
-
choice
- prompt "Turris Omnia boot method"
+ prompt "Boot method"
-config TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI
+config MVEBU_SPL_BOOT_DEVICE_SPI
bool "SPI NOR flash"
-config TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC
+config MVEBU_SPL_BOOT_DEVICE_MMC
bool "SDIO/MMC card"
+ select SPL_LIBDISK_SUPPORT
-endchoice
+config MVEBU_SPL_BOOT_DEVICE_UART
+ bool "UART"
-endif
+endchoice
config MVEBU_EFUSE
bool "Enable eFuse support"
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
+
+extra-y += kwbimage.cfg
+
+KWB_REPLACE += BOOT_FROM
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI),)
+ KWB_CFG_BOOT_FROM=spi
+endif
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC),)
+ KWB_CFG_BOOT_FROM=sdio
+endif
+ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_UART),)
+ KWB_CFG_BOOT_FROM=uart
+endif
+
+ifneq ($(CONFIG_SECURED_MODE_IMAGE),)
+KWB_REPLACE += CSK_INDEX
+KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)
+
+KWB_REPLACE += SEC_BOOT_DEV
+KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \
+ $(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \
+ $(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \
+ )
+
+KWB_REPLACE += SEC_FUSE_DUMP
+KWB_CFG_SEC_FUSE_DUMP = a38x
+endif
+
+$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+ include/config/auto.conf
+ $(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \
+ <$< >$(dir $<)$(@F)
+
endif # CONFIG_SPL_BUILD
obj-y += gpio.o
obj-y += mbus.o
#endif
/*
- * By default kwbimage.cfg from board specific folder is used
+ * By default the generated mvebu kwbimage.cfg is used
* If for some board, different configuration file need to be used,
* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
*/
#ifndef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_SYS_KWD_CONFIG arch/arm/mach-mvebu/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */
/* Add target to build it automatically upon "make" */
--- /dev/null
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada 38x uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+#@BOOT_FROM
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl.bin 0000005b 00000068
config OMAP34XX
bool "OMAP34XX SoC"
+ select ARM_CORTEX_A8_CVE_2017_5715
select ARM_ERRATA_430973
select ARM_ERRATA_454179
select ARM_ERRATA_621766
select ARM_ERRATA_725233
- select ARM_CORTEX_A8_CVE_2017_5715
select USE_TINY_PRINTF
imply NAND_OMAP_GPMC
imply SPL_EXT_SUPPORT
config OMAP54XX
bool "OMAP54XX SoC"
+ select ARM_CORTEX_A15_CVE_2017_5715
select ARM_ERRATA_798870
select SYS_THUMB_BUILD
- select ARM_CORTEX_A15_CVE_2017_5715
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_DISPLAY_PRINT
config AM33XX
bool "AM33XX SoC"
- select SPECIFY_CONSOLE_INDEX
select ARM_CORTEX_A8_CVE_2017_5715
+ select SPECIFY_CONSOLE_INDEX
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_NAND_AM33XX_BCH
bool "Support am335x_evm"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select TI_I2C_BOARD_DETECT
+ imply CMD_DM
+ imply SPL_DM
+ imply SPL_DM_SEQ_ALIAS
imply SPL_ENV_SUPPORT
imply SPL_EXT_SUPPORT
imply SPL_FAT_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC_SUPPORT
imply SPL_NAND_SUPPORT
+ imply SPL_OF_LIBFDT
imply SPL_POWER_SUPPORT
+ imply SPL_SEPARATE_BSS
imply SPL_SERIAL_SUPPORT
+ imply SPL_SYS_MALLOC_SIMPLE
imply SPL_WATCHDOG_SUPPORT
imply SPL_YMODEM_SUPPORT
- imply SPL_SYS_MALLOC_SIMPLE
- imply SPL_SEPARATE_BSS
- imply SPL_DM
- imply SPL_DM_SEQ_ALIAS
- imply SPL_OF_LIBFDT
help
This option specifies support for the AM335x
GP and HS EVM development platforms. The AM335x
bool "Support am335x_baltos"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_AM335X_IGEP003X
bool "Support am335x_igep003x"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_AM335X_SHC
bool "Support am335x based shc board from bosch"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
imply CMD_SPL
config TARGET_AM335X_SL50
bool "Support am335x_sl50"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_BAV335X
bool "Support bav335x"
select BOARD_LATE_INIT
select DM
select DM_SERIAL
+ imply CMD_DM
help
The BAV335x OEM Network Processor integrates all the functions of an
embedded network computer in a small, easy to use SODIMM module which
select BOARD_LATE_INIT
select DM
select DM_SERIAL
+ imply CMD_DM
config TARGET_CM_T335
bool "Support cm_t335"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_DRACO
bool "Support draco"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_ETAMIN
bool "Support etamin"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PCM051
bool "Support pcm051"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PENGWYN
bool "Support pengwyn"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PEPPER
bool "Support pepper"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PXM2
bool "Support pxm2"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_RASTABAN
bool "Support rastaban"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_RUT
bool "Support rut"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_THUBAN
bool "Support thuban"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PDU001
bool "Support PDU001"
select DM
select DM_SERIAL
+ imply CMD_DM
help
Support for PDU001 platform developed by EETS GmbH.
The PDU001 is a processor and display unit developed around
if AM43XX || AM33XX
config ISW_ENTRY_ADDR
hex "Address in memory or XIP flash of bootloader entry point"
+ default 0x402F4000 if AM43XX
+ default 0x402F0400 if AM33XX
help
After any reset, the boot ROM on the AM43XX SOC
searches the boot media for a valid boot image.
point address depending on the device type
(secure/non-secure), boot media (xip/non-xip) and
image headers.
- default 0x402F4000 if AM43XX
- default 0x402F0400 if AM33XX
config PUB_ROM_DATA_SIZE
hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+ default 0x8400
help
During the device boot, the public ROM uses the top of
the public L3 OCMC RAM to store r/w data like stack,
boot image. Once the ROM transfers control to the boot
image, this area is no longer used, and can be reclaimed
for run time use by the boot image.
- default 0x8400
endif
config TARGET_AM3517_EVM
bool "AM3517 EVM"
select DM
- select DM_SERIAL
select DM_GPIO
select DM_I2C
select DM_MMC
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_5
select OMAP3_GPIO_6
+ imply CMD_DM
config TARGET_CM_T35
bool "CompuLab CM-T3530 and CM-T3730 boards"
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_OMAP3_EVM
bool "TI OMAP3 EVM"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_3
+ imply CMD_DM
config TARGET_OMAP3_IGEP00X0
bool "IGEP"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_3
select OMAP3_GPIO_5
select OMAP3_GPIO_6
+ imply CMD_DM
config TARGET_OMAP3_OVERO
bool "OMAP35xx Gumstix Overo"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_2
select OMAP3_GPIO_3
select OMAP3_GPIO_4
select OMAP3_GPIO_5
select OMAP3_GPIO_6
+ imply CMD_DM
config TARGET_OMAP3_ZOOM1
bool "TI Zoom1"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_AM3517_CRANE
bool "am3517_crane"
bool "OMAP3 Logic"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_3
select OMAP3_GPIO_4
select OMAP3_GPIO_6
+ imply CMD_DM
config TARGET_NOKIA_RX51
bool "Nokia RX51"
config TARGET_OMAP3_CAIRO
bool "QUIPOS CAIRO"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_SNIPER
bool "LG Optimus Black"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_2
select OMAP3_GPIO_3
select OMAP3_GPIO_4
select OMAP3_GPIO_5
select OMAP3_GPIO_6
+ imply CMD_DM
endchoice
bool "TI DRA7XX"
select BOARD_LATE_INIT
select DRA7XX
- select TI_I2C_BOARD_DETECT
select PHYS_64BIT
- imply SCSI
+ select TI_I2C_BOARD_DETECT
imply DM_PMIC
- imply PMIC_LP87565
imply DM_REGULATOR
imply DM_REGULATOR_LP87565
- imply SPL_THERMAL
imply DM_THERMAL
+ imply PMIC_LP87565
+ imply SCSI
+ imply SPL_THERMAL
imply TI_DRA7_THERMAL
config TARGET_AM57XX_EVM
bool "AM57XX"
select BOARD_LATE_INIT
+ select CMD_DDR3
select DRA7XX
select TI_I2C_BOARD_DETECT
- select CMD_DDR3
+ imply DM_THERMAL
imply SCSI
imply SPL_THERMAL
- imply DM_THERMAL
imply TI_DRA7_THERMAL
endchoice
config TARGET_QEMU_ARM_32BIT
bool "Support qemu_arm"
depends on ARCH_QEMU
- select CPU_V7A
select ARCH_SUPPORT_PSCI
+ select CPU_V7A
select SYS_ARCH_TIMER
config TARGET_QEMU_ARM_64BIT
select DM
select DM_SERIAL
select USE_TINY_PRINTF
+ imply CMD_DM
config TARGET_GOSE
bool "Gose board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_KOELSCH
bool "Koelsch board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_LAGER
bool "Lager board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_KZM9G
bool "KZM9D board"
bool "Alt board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_SILK
bool "Silk board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_PORTER
bool "Porter board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_STOUT
bool "Stout board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
endchoice
config TARGET_VYASA_RK3288
bool "Vyasa-RK3288"
select BOARD_LATE_INIT
- select TPL
+ select ROCKCHIP_BROM_HELPER
select SUPPORT_TPL
- select TPL_DM
- select TPL_REGMAP
- select TPL_SYSCON
- select TPL_CLK
- select TPL_RAM
- select TPL_OF_PLATDATA
- select TPL_OF_CONTROL
+ select TPL
select TPL_BOOTROM_SUPPORT
- select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
- select ROCKCHIP_BROM_HELPER
+ select TPL_CLK
+ select TPL_DM
select TPL_DRIVERS_MISC_SUPPORT
select TPL_LIBCOMMON_SUPPORT
select TPL_LIBGENERIC_SUPPORT
+ select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
+ select TPL_OF_CONTROL
+ select TPL_OF_PLATDATA
+ select TPL_RAM
+ select TPL_REGMAP
select TPL_SERIAL_SUPPORT
+ select TPL_SYSCON
help
Vyasa is a RK3288-based development board with 2 USB ports,
HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
config TARGET_SOCFPGA_ARRIA10
bool
- select SPL_BOARD_INIT if SPL
select ALTERA_SDRAM
+ select SPL_BOARD_INIT if SPL
config TARGET_SOCFPGA_CYCLONE5
bool
config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
- select ARMV8_SPIN_TABLE
select ARMV8_SET_SMPEN
+ select ARMV8_SPIN_TABLE
choice
prompt "Altera SOCFPGA board select"
select PINCTRL
select PINCTRL_STM32
select RAM
- select STM32_SDRAM
select STM32_RCC
select STM32_RESET
+ select STM32_SDRAM
select STM32_SERIAL
select STM32_TIMER
select TIMER
select PINCTRL
select PINCTRL_STM32
select RAM
- select STM32_SDRAM
- select STM32_RCC
- select STM32_RESET
- select STM32_SERIAL
- select STM32_TIMER
- select TIMER
- select SUPPORT_SPL
select SPL
select SPL_BOARD_INIT
select SPL_CLK
select SPL_OF_CONTROL
select SPL_OF_LIBFDT
select SPL_OF_TRANSLATE
- imply SPL_OS_BOOT
select SPL_PINCTRL
select SPL_RAM
select SPL_SERIAL_SUPPORT
select SPL_SYS_MALLOC_SIMPLE
select SPL_TIMER
select SPL_XIP_SUPPORT
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SDRAM
+ select STM32_SERIAL
+ select STM32_TIMER
+ select SUPPORT_SPL
+ select TIMER
+ imply SPL_OS_BOOT
config STM32H7
bool "stm32h7 family"
select PINCTRL_STM32
select RAM
select REGMAP
- select STM32_SDRAM
select STM32_RCC
select STM32_RESET
+ select STM32_SDRAM
select STM32_SERIAL
select STM32_TIMER
select SYSCON
Select this dram controller driver for Sun9i platforms,
like A80.
+config DRAM_SUN50I_H6
+ bool
+ help
+ Select this dram controller driver for some sun50i platforms,
+ like H6.
+
config SUN6I_P2WI
bool "Allwinner sun6i internal P2WI controller"
help
with various RSB based devices, such as AXP223, AXP8XX PMICs,
and AC100/AC200 ICs.
-config SUNXI_HIGH_SRAM
- bool
- default n
+config SUNXI_SRAM_ADDRESS
+ hex
+ default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
+ default 0x20000 if MACH_SUN50I_H6
+ default 0x0
---help---
Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
with the first SRAM region being located at address 0.
Some newer SoCs map the boot ROM at address 0 instead and move the
- SRAM to 64KB, just behind the mask ROM.
- Chips using the latter setup are supposed to select this option to
- adjust the addresses accordingly.
+ SRAM to a different address.
config SUNXI_A64_TIMER_ERRATUM
bool
select CPU_V7A
select DRAM_SUN9I
select SUN6I_PRCM
- select SUNXI_HIGH_SRAM
select SUNXI_GEN_SUN6I
select SUN8I_RSB
select SUPPORT_SPL
select PHY_SUN4I_USB
select SUNXI_DE2
select SUNXI_GEN_SUN6I
- select SUNXI_HIGH_SRAM
select SUPPORT_SPL
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_32BIT
bool "sun50i (Allwinner H5)"
select ARM64
select MACH_SUNXI_H3_H5
- select SUNXI_HIGH_SRAM
select FIT
select SPL_LOAD_FIT
+config MACH_SUN50I_H6
+ bool "sun50i (Allwinner H6)"
+ select ARM64
+ select SUPPORT_SPL
+ select FIT
+ select SPL_LOAD_FIT
+ select DRAM_SUN50I_H6
+
endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
MACH_SUN8I_V3S
default 672 if MACH_SUN50I
+ default 744 if MACH_SUN50I_H6
---help---
Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
must be a multiple of 24. For the sun9i (A80), the tested values
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
default 14779 if MACH_SUN8I_V3S
- default 3881979 if MACH_SUN8I_R40
+ default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
default 4145117 if MACH_SUN9I
default 3881915 if MACH_SUN50I
---help---
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_R40
default y if MACH_SUN50I
+ default y if MACH_SUN50I_H6
---help---
Select this to enable dram odt (on die termination).
default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
default 1008000000 if MACH_SUN8I
default 1008000000 if MACH_SUN9I
+ default 888000000 if MACH_SUN50I_H6
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
default "sun8i" if MACH_SUN8I
default "sun9i" if MACH_SUN9I
default "sun50i" if MACH_SUN50I
+ default "sun50i" if MACH_SUN50I_H6
config SYS_BOARD
default "sunxi"
depends on !MACH_SUN8I_V3S
depends on !MACH_SUN9I
depends on !MACH_SUN50I
+ depends on !MACH_SUN50I_H6
select VIDEO
imply VIDEO_DT_SIMPLEFB
default y
default 0x4fe00000 if MACH_SUN8I
default 0x2fe00000 if MACH_SUN9I
default 0x4fe00000 if MACH_SUN50I
+ default 0x4fe00000 if MACH_SUN50I_H6
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
endif
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
+obj-$(CONFIG_MACH_SUN50I_H6) += clock_sun50i_h6.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/
+obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o
endif
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
-#elif defined(CONFIG_SUNXI_GEN_SUN6I)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
--- /dev/null
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ clock_set_pll1(408000000);
+
+ writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
+ while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK))
+ ;
+
+ clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK,
+ CCM_CPU_AXI_DEFAULT_FACTORS);
+
+ writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
+ writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
+ writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
+
+ /*
+ * The mux and factor are set, but the clock will be enabled in
+ * DRAM initialization code.
+ */
+ writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
+}
+#endif
+
+void clock_init_uart(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* uart clock source is apb2 */
+ writel(APB2_CLK_SRC_OSC24M|
+ APB2_CLK_RATE_N_1|
+ APB2_CLK_RATE_M(1),
+ &ccm->apb2_cfg);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->uart_gate_reset,
+ 1 << (CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->uart_gate_reset,
+ 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
+}
+
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ u32 val;
+
+ /* Do not support clocks < 288MHz as they need factor P */
+ if (clk < 288000000) clk = 288000000;
+
+ /* Switch to 24MHz clock while changing PLL1 */
+ val = readl(&ccm->cpu_axi_cfg);
+ val &= ~CCM_CPU_AXI_MUX_MASK;
+ val |= CCM_CPU_AXI_MUX_OSC24M;
+ writel(val, &ccm->cpu_axi_cfg);
+
+ /* clk = 24*n/p, p is ignored if clock is >288MHz */
+ writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
+ CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
+ while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
+
+ /* Switch CPU to PLL1 */
+ val = readl(&ccm->cpu_axi_cfg);
+ val &= ~CCM_CPU_AXI_MUX_MASK;
+ val |= CCM_CPU_AXI_MUX_PLL_CPUX;
+ writel(val, &ccm->cpu_axi_cfg);
+}
+#endif
+
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ uint32_t rval = readl(&ccm->pll6_cfg);
+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
+ int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+ CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+ int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
+ CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
+ /* The register defines PLL6-4X, not plain PLL6 */
+ return 24000000 / 4 * n / div1 / div2;
+}
puts("CPU: Allwinner A64 (SUN50I)\n");
#elif defined CONFIG_MACH_SUN50I_H5
puts("CPU: Allwinner H5 (SUN50I)\n");
+#elif defined CONFIG_MACH_SUN50I_H6
+ puts("CPU: Allwinner H6 (SUN50I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
--- /dev/null
+/*
+ * sun50i H6 platform dram controller init
+ *
+ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+#include <linux/bitops.h>
+#include <linux/kconfig.h>
+
+/*
+ * The DRAM controller structure on H6 is similar to the ones on A23/A80:
+ * they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64
+ * /H5/R40 CTL and PHY is composed).
+ *
+ * COM is allwinner-specific. On H6, the address mapping function is moved
+ * from COM to CTL (with the standard ADDRMAP registers on DesignWare memory
+ * controller).
+ *
+ * CTL (controller) and PHY is from DesignWare.
+ *
+ * The CTL part is a bit similar to the one on A23/A80 (because they all
+ * originate from DesignWare), but gets more registers added.
+ *
+ * The PHY part is quite new, not seen in any previous Allwinner SoCs, and
+ * not seen on other SoCs in U-Boot. The only SoC that is also known to have
+ * similar PHY is ZynqMP.
+ */
+
+/*
+ * The delay parameters below allow to allegedly specify delay times of some
+ * unknown unit for each individual bit trace in each of the four data bytes
+ * the 32-bit wide access consists of. Also three control signals can be
+ * adjusted individually.
+ */
+#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */
+#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4)
+/*
+ * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN,
+ * Termination and Power down
+ */
+#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6)
+struct dram_para {
+ u32 clk;
+ enum sunxi_dram_type type;
+ u8 cols;
+ u8 rows;
+ u8 ranks;
+ const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
+ const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
+};
+
+static void mctl_sys_init(struct dram_para *para);
+static void mctl_com_init(struct dram_para *para);
+static void mctl_set_timing_lpddr3(struct dram_para *para);
+static void mctl_channel_init(struct dram_para *para);
+
+static void mctl_core_init(struct dram_para *para)
+{
+ mctl_sys_init(para);
+ mctl_com_init(para);
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_LPDDR3:
+ mctl_set_timing_lpddr3(para);
+ break;
+ default:
+ panic("Unsupported DRAM type!");
+ };
+ mctl_channel_init(para);
+}
+
+static void mctl_phy_pir_init(u32 val)
+{
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+
+ writel(val | BIT(0), &mctl_phy->pir);
+ mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
+}
+
+enum {
+ MBUS_PORT_CPU = 0,
+ MBUS_PORT_GPU = 1,
+ MBUS_PORT_MAHB = 2,
+ MBUS_PORT_DMA = 3,
+ MBUS_PORT_VE = 4,
+ MBUS_PORT_CE = 5,
+ MBUS_PORT_TSC0 = 6,
+ MBUS_PORT_NDFC0 = 8,
+ MBUS_PORT_CSI0 = 11,
+ MBUS_PORT_DI0 = 14,
+ MBUS_PORT_DI1 = 15,
+ MBUS_PORT_DE300 = 16,
+ MBUS_PORT_IOMMU = 25,
+ MBUS_PORT_VE2 = 26,
+ MBUS_PORT_USB3 = 37,
+ MBUS_PORT_PCIE = 38,
+ MBUS_PORT_VP9 = 39,
+ MBUS_PORT_HDCP2 = 40,
+};
+
+enum {
+ MBUS_QOS_LOWEST = 0,
+ MBUS_QOS_LOW,
+ MBUS_QOS_HIGH,
+ MBUS_QOS_HIGHEST
+};
+inline void mbus_configure_port(u8 port,
+ bool bwlimit,
+ bool priority,
+ u8 qos,
+ u8 waittime,
+ u8 acs,
+ u16 bwl0,
+ u16 bwl1,
+ u16 bwl2)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
+ | (priority ? (1 << 1) : 0)
+ | ((qos & 0x3) << 2)
+ | ((waittime & 0xf) << 4)
+ | ((acs & 0xff) << 8)
+ | (bwl0 << 16) );
+ const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
+
+ debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
+ writel(cfg0, &mctl_com->master[port].cfg0);
+ writel(cfg1, &mctl_com->master[port].cfg1);
+}
+
+#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
+ mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
+ MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
+
+static void mctl_set_master_priority(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel(399, &mctl_com->tmr);
+ writel(BIT(16), &mctl_com->bwcr);
+
+ MBUS_CONF( CPU, true, HIGHEST, 0, 256, 128, 100);
+ MBUS_CONF( GPU, true, HIGH, 0, 1536, 1400, 256);
+ MBUS_CONF( MAHB, true, HIGHEST, 0, 512, 256, 96);
+ MBUS_CONF( DMA, true, HIGH, 0, 256, 100, 80);
+ MBUS_CONF( VE, true, HIGH, 2, 8192, 5500, 5000);
+ MBUS_CONF( CE, true, HIGH, 2, 100, 64, 32);
+ MBUS_CONF( TSC0, true, HIGH, 2, 100, 64, 32);
+ MBUS_CONF(NDFC0, true, HIGH, 0, 256, 128, 64);
+ MBUS_CONF( CSI0, true, HIGH, 0, 256, 128, 100);
+ MBUS_CONF( DI0, true, HIGH, 0, 1024, 256, 64);
+ MBUS_CONF(DE300, true, HIGHEST, 6, 8192, 2800, 2400);
+ MBUS_CONF(IOMMU, true, HIGHEST, 0, 100, 64, 32);
+ MBUS_CONF( VE2, true, HIGH, 2, 8192, 5500, 5000);
+ MBUS_CONF( USB3, true, HIGH, 0, 256, 128, 64);
+ MBUS_CONF( PCIE, true, HIGH, 2, 100, 64, 32);
+ MBUS_CONF( VP9, true, HIGH, 2, 8192, 5500, 5000);
+ MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
+}
+
+static u32 mr_lpddr3[12] = {
+ 0x00000000, 0x00000043, 0x0000001a, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000048, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000003,
+};
+
+/* TODO: flexible timing */
+static void mctl_set_timing_lpddr3(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+
+ u8 tccd = 2;
+ u8 tfaw = max(ns_to_t(50), 4);
+ u8 trrd = max(ns_to_t(10), 2);
+ u8 trcd = max(ns_to_t(24), 2);
+ u8 trc = ns_to_t(70);
+ u8 txp = max(ns_to_t(8), 2);
+ u8 twtr = max(ns_to_t(8), 2);
+ u8 trtp = max(ns_to_t(8), 2);
+ u8 twr = max(ns_to_t(15), 2);
+ u8 trp = ns_to_t(18);
+ u8 tras = ns_to_t(42);
+ u8 twtr_sa = ns_to_t(5);
+ u8 tcksrea = ns_to_t(11);
+ u16 trefi = ns_to_t(3900) / 32;
+ u16 trfc = ns_to_t(210);
+ u16 txsr = ns_to_t(220);
+
+ if (CONFIG_DRAM_CLK % 400 == 0) {
+ /* Round up these parameters */
+ twtr_sa++;
+ tcksrea++;
+ }
+
+ u8 tmrw = 5;
+ u8 tmrd = 5;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 5;
+ u8 trasmax = CONFIG_DRAM_CLK / 60;
+ u8 txs = 4;
+ u8 txsdll = 4;
+ u8 txsabort = 4;
+ u8 txsfast = 4;
+
+ u8 tcl = 5; /* CL 10 */
+ u8 tcwl = 3; /* CWL 6 */
+ u8 t_rdata_en = twtr_sa + 8;
+
+ u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
+ u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 4 + twr + 1;
+ /*
+ * The code below for twr2rd and trd2wr follows the IP core's
+ * document from ZynqMP and i.MX7. The BSP has both number
+ * substracted by 2.
+ */
+ u8 twr2rd = tcwl + 4 + 1 + twtr;
+ u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1;
+
+ /* set mode register */
+ memcpy(mctl_phy->mr, mr_lpddr3, sizeof(mr_lpddr3));
+
+ /* set DRAM timing */
+ writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
+ &mctl_ctl->dramtmg[0]);
+ writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
+ writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
+ &mctl_ctl->dramtmg[2]);
+ writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
+ writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
+ &mctl_ctl->dramtmg[4]);
+ writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
+ &mctl_ctl->dramtmg[5]);
+ /* Value suggested by ZynqMP manual and used by libdram */
+ writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
+ writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
+ &mctl_ctl->dramtmg[8]);
+ writel(txsr, &mctl_ctl->dramtmg[14]);
+
+ clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
+ writel(0, &mctl_ctl->dfimisc);
+ clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
+
+ /*
+ * Set timing registers of the PHY.
+ * Note: the PHY is clocked 2x from the DRAM frequency.
+ */
+ writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
+ &mctl_phy->dtpr[0]);
+ writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
+ writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
+ writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
+ &mctl_phy->dtpr[3]);
+ writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
+ writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
+ writel(0x0505, &mctl_phy->dtpr[6]);
+
+ /* Configure DFI timing */
+ writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
+ &mctl_ctl->dfitmg0);
+ writel(0x040201, &mctl_ctl->dfitmg1);
+
+ /* Configure PHY timing */
+ writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
+ writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
+
+ /* set refresh timing */
+ writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
+}
+
+static void mctl_sys_init(struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ /* Put all DRAM-related blocks to reset state */
+ clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
+ writel(0, &ccm->dram_gate_reset);
+ clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+ clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+
+ udelay(5);
+
+ /* Set PLL5 rate to doubled DRAM clock rate */
+ writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
+ CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
+ mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
+
+ /* Configure DRAM mod clock */
+ writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
+ setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
+ writel(BIT(0) | BIT(RESET_SHIFT), &ccm->dram_gate_reset);
+
+ /* Disable all channels */
+ writel(0, &mctl_com->maer0);
+ writel(0, &mctl_com->maer1);
+ writel(0, &mctl_com->maer2);
+
+ /* Configure MBUS and enable DRAM mod reset */
+ setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
+ setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
+ setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
+ udelay(5);
+
+ /* Unknown hack from the BSP, which enables access of mctl_ctl regs */
+ writel(0x8000, &mctl_ctl->unk_0x00c);
+}
+
+static void mctl_set_addrmap(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ u8 cols = para->cols;
+ u8 rows = para->rows;
+ u8 ranks = para->ranks;
+
+ /* Ranks */
+ if (ranks == 2)
+ mctl_ctl->addrmap[0] = rows + cols - 3;
+ else
+ mctl_ctl->addrmap[0] = 0x1F;
+
+ /* Banks, hardcoded to 8 banks now */
+ mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
+
+ /* Columns */
+ mctl_ctl->addrmap[2] = 0;
+ switch (cols) {
+ case 8:
+ mctl_ctl->addrmap[3] = 0x1F1F0000;
+ mctl_ctl->addrmap[4] = 0x1F1F;
+ break;
+ case 9:
+ mctl_ctl->addrmap[3] = 0x1F000000;
+ mctl_ctl->addrmap[4] = 0x1F1F;
+ break;
+ case 10:
+ mctl_ctl->addrmap[3] = 0;
+ mctl_ctl->addrmap[4] = 0x1F1F;
+ break;
+ case 11:
+ mctl_ctl->addrmap[3] = 0;
+ mctl_ctl->addrmap[4] = 0x1F00;
+ break;
+ case 12:
+ mctl_ctl->addrmap[3] = 0;
+ mctl_ctl->addrmap[4] = 0;
+ break;
+ default:
+ panic("Unsupported DRAM configuration: column number invalid\n");
+ }
+
+ /* Rows */
+ mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
+ switch (rows) {
+ case 13:
+ mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
+ mctl_ctl->addrmap[7] = 0x0F0F;
+ break;
+ case 14:
+ mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
+ mctl_ctl->addrmap[7] = 0x0F0F;
+ break;
+ case 15:
+ mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
+ mctl_ctl->addrmap[7] = 0x0F0F;
+ break;
+ case 16:
+ mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
+ mctl_ctl->addrmap[7] = 0x0F0F;
+ break;
+ case 17:
+ mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
+ mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
+ break;
+ case 18:
+ mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
+ mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
+ break;
+ default:
+ panic("Unsupported DRAM configuration: row number invalid\n");
+ }
+
+ /* Bank groups, DDR4 only */
+ mctl_ctl->addrmap[8] = 0x3F3F;
+}
+
+static void mctl_com_init(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ u32 reg_val, tmp;
+
+ mctl_set_addrmap(para);
+
+ setbits_le32(&mctl_com->cr, BIT(31));
+ /*
+ * This address is magic; it's in SID memory area, but there's no
+ * known definition of it.
+ * On my Pine H64 board it has content 7.
+ */
+ if (readl(0x03006100) == 7)
+ clrbits_le32(&mctl_com->cr, BIT(27));
+ else if (readl(0x03006100) == 3)
+ setbits_le32(&mctl_com->cr, BIT(27));
+
+ if (para->clk > 408)
+ reg_val = 0xf00;
+ else if (para->clk > 246)
+ reg_val = 0x1f00;
+ else
+ reg_val = 0x3f00;
+ clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
+
+ /* TODO: half DQ, non-LPDDR3 types */
+ writel(MSTR_DEVICETYPE_LPDDR3 | MSTR_BUSWIDTH_FULL |
+ MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks) |
+ 0x80000000, &mctl_ctl->mstr);
+ writel(DCR_LPDDR3 | DCR_DDR8BANK | 0x400, &mctl_phy->dcr);
+
+ if (para->ranks == 2)
+ writel(0x0303, &mctl_ctl->odtmap);
+ else
+ writel(0x0201, &mctl_ctl->odtmap);
+
+ /* TODO: non-LPDDR3 types */
+ tmp = para->clk * 7 / 2000;
+ reg_val = 0x0400;
+ reg_val |= (tmp + 7) << 24;
+ reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
+ writel(reg_val, &mctl_ctl->odtcfg);
+
+ /* TODO: half DQ */
+}
+
+static void mctl_bit_delay_set(struct dram_para *para)
+{
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ int i, j;
+ u32 val;
+
+ for (i = 0; i < 4; i++) {
+ val = readl(&mctl_phy->dx[i].bdlr0);
+ for (j = 0; j < 4; j++)
+ val += para->dx_write_delays[i][j] << (j * 8);
+ writel(val, &mctl_phy->dx[i].bdlr0);
+
+ val = readl(&mctl_phy->dx[i].bdlr1);
+ for (j = 0; j < 4; j++)
+ val += para->dx_write_delays[i][j + 4] << (j * 8);
+ writel(val, &mctl_phy->dx[i].bdlr1);
+
+ val = readl(&mctl_phy->dx[i].bdlr2);
+ for (j = 0; j < 4; j++)
+ val += para->dx_write_delays[i][j + 8] << (j * 8);
+ writel(val, &mctl_phy->dx[i].bdlr2);
+ }
+ clrbits_le32(&mctl_phy->pgcr[0], BIT(26));
+
+ for (i = 0; i < 4; i++) {
+ val = readl(&mctl_phy->dx[i].bdlr3);
+ for (j = 0; j < 4; j++)
+ val += para->dx_read_delays[i][j] << (j * 8);
+ writel(val, &mctl_phy->dx[i].bdlr3);
+
+ val = readl(&mctl_phy->dx[i].bdlr4);
+ for (j = 0; j < 4; j++)
+ val += para->dx_read_delays[i][j + 4] << (j * 8);
+ writel(val, &mctl_phy->dx[i].bdlr4);
+
+ val = readl(&mctl_phy->dx[i].bdlr5);
+ for (j = 0; j < 4; j++)
+ val += para->dx_read_delays[i][j + 8] << (j * 8);
+ writel(val, &mctl_phy->dx[i].bdlr5);
+
+ val = readl(&mctl_phy->dx[i].bdlr6);
+ val += (para->dx_read_delays[i][12] << 8) |
+ (para->dx_read_delays[i][13] << 16);
+ writel(val, &mctl_phy->dx[i].bdlr6);
+ }
+ setbits_le32(&mctl_phy->pgcr[0], BIT(26));
+ udelay(1);
+
+ for (i = 1; i < 14; i++) {
+ val = readl(&mctl_phy->acbdlr[i]);
+ val += 0x0a0a0a0a;
+ writel(val, &mctl_phy->acbdlr[i]);
+ }
+}
+
+static void mctl_channel_init(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ int i;
+ u32 val;
+
+ setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
+ setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
+ writel(0x2f05, &mctl_ctl->sched[0]);
+ setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
+ setbits_le32(&mctl_ctl->dfimisc, BIT(0));
+ setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));
+ clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);
+ /* TODO: non-LPDDR3 types */
+ clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));
+ clrbits_le32(&mctl_phy->pgcr[6], BIT(0));
+ clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);
+ /* TODO: VT compensation */
+ clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);
+ clrbits_le32(&mctl_phy->vtcr[1], BIT(1));
+
+ for (i = 0; i < 4; i++)
+ clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);
+ for (i = 0; i < 4; i++)
+ clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);
+ for (i = 0; i < 4; i++)
+ clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);
+
+ udelay(100);
+
+ if (para->ranks == 2)
+ setbits_le32(&mctl_phy->dtcr[1], 0x30000);
+ else
+ clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
+
+ clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
+ if (para->ranks == 2) {
+ writel(0x00010001, &mctl_phy->rankidr);
+ writel(0x20000, &mctl_phy->odtcr);
+ } else {
+ writel(0x0, &mctl_phy->rankidr);
+ writel(0x10000, &mctl_phy->odtcr);
+ }
+
+ /* TODO: non-LPDDR3 types */
+ clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
+ if (para->clk <= 792) {
+ if (para->clk <= 672) {
+ if (para->clk <= 600)
+ val = 0x300;
+ else
+ val = 0x400;
+ } else {
+ val = 0x500;
+ }
+ } else {
+ val = 0x600;
+ }
+ /* FIXME: NOT REVIEWED YET */
+ clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);
+ clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,
+ CONFIG_DRAM_ZQ & 0xff);
+ clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);
+ setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);
+ setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);
+ setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);
+ clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);
+ setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);
+ setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);
+ setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+ for (i = 1; i < 14; i++)
+ writel(0x06060606, &mctl_phy->acbdlr[i]);
+ }
+
+ /* TODO: non-LPDDR3 types */
+ mctl_phy_pir_init(PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT |
+ PIR_QSGATE | PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE |
+ PIR_WREYE);
+
+ /* TODO: non-LPDDR3 types */
+ for (i = 0; i < 4; i++)
+ writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
+
+ for (i = 0; i < 4; i++) {
+ if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
+ val = 0x0;
+ else
+ val = 0xaaaa;
+ clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);
+
+ if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
+ val = 0x0;
+ else
+ val = 0x2020;
+ clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);
+ }
+
+ mctl_bit_delay_set(para);
+ udelay(1);
+
+ setbits_le32(&mctl_phy->pgcr[6], BIT(0));
+ clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);
+ for (i = 0; i < 4; i++)
+ clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
+ udelay(10);
+
+ if (readl(&mctl_phy->pgsr[0]) & 0x400000)
+ {
+ /*
+ * Detect single rank.
+ * TODO: also detect half DQ.
+ */
+ if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
+ (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 &&
+ (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 &&
+ (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) {
+ para->ranks = 1;
+ /* Restart DRAM initialization from scratch. */
+ mctl_core_init(para);
+ return;
+ }
+ else {
+ panic("This DRAM setup is currently not supported.\n");
+ }
+ }
+
+ if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
+ /* Oops! There's something wrong! */
+ debug("PLL = %x\n", readl(0x3001010));
+ debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
+ for (i = 0; i < 4; i++)
+ debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
+ panic("Error while initializing DRAM PHY!\n");
+ }
+
+ clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
+ clrbits_le32(&mctl_phy->pgcr[1], 0x40);
+ clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
+ writel(1, &mctl_ctl->swctl);
+ mctl_await_completion(&mctl_ctl->swstat, 1, 1);
+ clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
+
+ setbits_le32(&mctl_com->unk_0x014, BIT(31));
+ writel(0xffffffff, &mctl_com->maer0);
+ writel(0x7ff, &mctl_com->maer1);
+ writel(0xffff, &mctl_com->maer2);
+}
+
+static void mctl_auto_detect_dram_size(struct dram_para *para)
+{
+ /* TODO: non-LPDDR3, half DQ */
+ /*
+ * Detect rank number by the code in mctl_channel_init. Furtherly
+ * when DQ detection is available it will also be executed there.
+ */
+ mctl_core_init(para);
+
+ /* detect row address bits */
+ para->cols = 8;
+ para->rows = 18;
+ mctl_core_init(para);
+
+ for (para->rows = 13; para->rows < 18; para->rows++) {
+ /* 8 banks, 8 bit per byte and 32 bit width */
+ if (mctl_mem_matches((1 << (para->rows + para->cols + 5))))
+ break;
+ }
+
+ /* detect column address bits */
+ para->cols = 11;
+ mctl_core_init(para);
+
+ for (para->cols = 8; para->cols < 11; para->cols++) {
+ /* 8 bits per byte and 32 bit width */
+ if (mctl_mem_matches(1 << (para->cols + 2)))
+ break;
+ }
+}
+
+unsigned long mctl_calc_size(struct dram_para *para)
+{
+ /* TODO: non-LPDDR3, half DQ */
+
+ /* 8 banks, 32-bit (4 byte) data width */
+ return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
+}
+
+#define SUN50I_H6_DX_WRITE_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
+#define SUN50I_H6_DX_READ_DELAYS \
+ {{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
+ { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
+ { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
+ { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct dram_para para = {
+ .clk = CONFIG_DRAM_CLK,
+ .type = SUNXI_DRAM_TYPE_LPDDR3,
+ .ranks = 2,
+ .cols = 11,
+ .rows = 14,
+ .dx_read_delays = SUN50I_H6_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
+ };
+
+ unsigned long size;
+
+ /* RES_CAL_CTRL_REG in BSP U-boot*/
+ setbits_le32(0x7010310, BIT(8));
+ clrbits_le32(0x7010318, 0x3f);
+
+ mctl_auto_detect_dram_size(¶);
+
+ mctl_core_init(¶);
+
+ size = mctl_calc_size(¶);
+
+ clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
+
+ mctl_set_master_priority();
+
+ return size;
+};
@ reference and to be able to regenerate a (probably fixed) version of this
@ code found in encoded form in boot0.h.
+#include <config.h>
+
.text
+#ifndef CONFIG_MACH_SUN50I_H6
ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register
+#else
+ ldr r1, =0x09010040 @ MMIO mapped RVBAR[0] register
+#endif
ldr r0, =0x57aA7add @ start address, to be replaced
str r0, [r1]
dsb sy
config TEGRA_COMMON
bool "Tegra common options"
+ select BINMAN
+ select BOARD_EARLY_INIT_F
select CLK
select DM
select DM_ETH
select DM_SPI
select DM_SPI_FLASH
select MISC
- select SPI
select OF_CONTROL
+ select SPI
select VIDCONSOLE_AS_LCD if DM_VIDEO
- select BOARD_EARLY_INIT_F
- select BINMAN
+ imply CMD_DM
imply CRC32_VERIFY
config TEGRA_NO_BPMP
config TEGRA210
bool "Tegra210 family"
- select TEGRA_GPIO
select TEGRA_ARMV8_COMMON
+ select TEGRA_GPIO
select TEGRA_NO_BPMP
config TEGRA186
{
#ifdef CONFIG_ARM64
return SZ_512M;
+#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
+ // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
+ // from BASE to 4GB, not BASE to BASE+SIZE.
+ return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
#else
return 0;
#endif
#include <asm/io.h>
#include <asm/types.h>
-#include <asm/arch/flow.h>
+
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
return 0;
}
-static void tegra_powergate_ram_repair(void)
-{
-#ifdef CONFIG_TEGRA124
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
- /* Request RAM repair for cluster 0 and wait until complete */
- setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
- ;
-
- /* Same for cluster 1 */
- setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
- ;
-#endif
-}
-
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph)
{
int err;
- tegra_powergate_ram_repair();
reset_set_enable(periph, 1);
err = tegra_powergate_power_on(id);
config TARGET_APALIS_TK1
bool "Toradex Apalis TK1 module"
+ select ARCH_SUPPORT_PSCI
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select ARCH_SUPPORT_PSCI
config TARGET_JETSON_TK1
bool "NVIDIA Tegra124 Jetson TK1 board"
+ select ARCH_SUPPORT_PSCI
select BOARD_LATE_INIT
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select ARCH_SUPPORT_PSCI
config TARGET_CEI_TK1_SOM
bool "Colorado Engineering Inc Tegra124 TK1-som board"
writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
}
+static void tegra124_ram_repair(void)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ u32 ram_repair_timeout; /*usec*/
+ u32 val;
+
+ /*
+ * Request the Flow Controller perform RAM repair whenever it turns on
+ * a power rail that requires RAM repair.
+ */
+ clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN);
+
+ /* Request SW trigerred RAM repair by setting req bit */
+ /* cluster 0 */
+ setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+ /* Wait for completion (status == 0) */
+ ram_repair_timeout = 500;
+ do {
+ udelay(1);
+ val = readl(&flow->ram_repair);
+ } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
+ if (!ram_repair_timeout)
+ debug("Ram Repair cluster0 failed\n");
+
+ /* cluster 1 */
+ setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+ /* Wait for completion (status == 0) */
+ ram_repair_timeout = 500;
+ do {
+ udelay(1);
+ val = readl(&flow->ram_repair_cluster1);
+ } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
+
+ if (!ram_repair_timeout)
+ debug("Ram Repair cluster1 failed\n");
+}
+
/**
* Tegra124 requires some special clock initialization, including setting up
* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
&pmc->pmc_pwrgate_timer_mult);
enable_cpu_power_rail();
+ powerup_cpus();
+ tegra124_ram_repair();
enable_cpu_clocks();
clock_enable_coresight(1);
- remove_cpu_resets();
writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
- powerup_cpus();
+ remove_cpu_resets();
debug("%s exit, should continue @ reset_vector\n", __func__);
}
config ARCH_UNIPHIER_32BIT
bool
+ select ARCH_SUPPORT_PSCI
+ select ARMV7_NONSEC
select CPU_V7A
select CPU_V7_HAS_NONSEC
- select ARMV7_NONSEC
- select ARCH_SUPPORT_PSCI
choice
prompt "UniPhier SoC select"
bool "Enable UniPhier LD20 SoC support"
depends on ARCH_UNIPHIER_V8_MULTI
default y
+ select OF_BOARD_SETUP
config ARCH_UNIPHIER_PXS3
bool "Enable UniPhier PXs3 SoC support"
config CACHE_UNIPHIER
bool "Enable the UniPhier L2 cache controller"
depends on ARCH_UNIPHIER_32BIT
- select SYS_CACHE_SHIFT_7
default y
+ select SYS_CACHE_SHIFT_7
help
This option allows to use the UniPhier System Cache as L2 cache.
config SYS_MALLOC_F_LEN
default 0x600
+config SYS_MALLOC_LEN
+ default 0x1400000
+
config BOOT_INIT_FILE
string "boot.bin init register filename"
default ""
*(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(4);
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
config TARGET_MICROBLAZE_GENERIC
bool "Support microblaze-generic"
select BOARD_LATE_INIT
- select SUPPORT_SPL
- select OF_CONTROL
select DM
select DM_SERIAL
+ select OF_CONTROL
+ select SUPPORT_SPL
select SYSRESET
+ imply CMD_DM
endchoice
config TARGET_QEMU_MIPS
bool "Support qemu-mips"
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
- select ROM_EXCEPTION_VECTORS
+ select SUPPORTS_LITTLE_ENDIAN
config TARGET_MALTA
bool "Support malta"
select DM_SERIAL
select DYNAMIC_IO_PORT_BASE
select MIPS_CM
+ select MIPS_L1_CACHE_SHIFT_6
select MIPS_L2_CACHE
select OF_CONTROL
select OF_ISA_BUS
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS32_R6
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
select SUPPORTS_CPU_MIPS64_R6
+ select SUPPORTS_LITTLE_ENDIAN
select SWAP_IO_SPACE
- select MIPS_L1_CACHE_SHIFT_6
- select ROM_EXCEPTION_VECTORS
+ imply CMD_DM
config TARGET_VCT
bool "Support vct"
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
- select ROM_EXCEPTION_VECTORS
config TARGET_DBAU1X00
bool "Support dbau1x00"
+ select MIPS_TUNE_4KC
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_LITTLE_ENDIAN
select SYS_MIPS_CACHE_INIT_RAM_LOAD
- select ROM_EXCEPTION_VECTORS
- select MIPS_TUNE_4KC
config TARGET_PB1X00
bool "Support pb1x00"
- select SUPPORTS_LITTLE_ENDIAN
+ select MIPS_TUNE_4KC
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_LITTLE_ENDIAN
select SYS_MIPS_CACHE_INIT_RAM_LOAD
- select ROM_EXCEPTION_VECTORS
- select MIPS_TUNE_4KC
config ARCH_ATH79
bool "Support QCA/Atheros ath79"
- select OF_CONTROL
select DM
+ select OF_CONTROL
+ imply CMD_DM
config ARCH_BMIPS
bool "Support BMIPS SoCs"
- select OF_CONTROL
- select DM
select CLK
select CPU
+ select DM
+ select OF_CONTROL
select RAM
select SYSRESET
+ imply CMD_DM
config MACH_PIC32
bool "Support Microchip PIC32"
- select OF_CONTROL
select DM
+ select OF_CONTROL
+ imply CMD_DM
config TARGET_BOSTON
bool "Support Boston"
select DM
select DM_SERIAL
- select OF_CONTROL
select MIPS_CM
select MIPS_L1_CACHE_SHIFT_6
select MIPS_L2_CACHE
select OF_BOARD_SETUP
+ select OF_CONTROL
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS32_R6
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
select SUPPORTS_CPU_MIPS64_R6
- select ROM_EXCEPTION_VECTORS
+ select SUPPORTS_LITTLE_ENDIAN
+ imply CMD_DM
config TARGET_XILFPGA
bool "Support Imagination Xilfpga"
- select OF_CONTROL
select DM
- select DM_SERIAL
- select DM_GPIO
select DM_ETH
- select SUPPORTS_LITTLE_ENDIAN
- select SUPPORTS_CPU_MIPS32_R1
- select SUPPORTS_CPU_MIPS32_R2
+ select DM_GPIO
+ select DM_SERIAL
select MIPS_L1_CACHE_SHIFT_4
+ select OF_CONTROL
select ROM_EXCEPTION_VECTORS
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_LITTLE_ENDIAN
+ imply CMD_DM
help
This supports IMGTEC MIPSfpga platform
config SOC_AR933X
bool
+ select MIPS_TUNE_24KC
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
- select ROM_EXCEPTION_VECTORS
- select MIPS_TUNE_24KC
help
This supports QCA/Atheros ar933x family SOCs.
config SOC_AR934X
bool
+ select MIPS_TUNE_74KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
- select MIPS_TUNE_74KC
help
This supports QCA/Atheros ar934x family SOCs.
config SOC_QCA953X
bool
+ select MIPS_TUNE_24KC
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
- select ROM_EXCEPTION_VECTORS
- select MIPS_TUNE_24KC
help
This supports QCA/Atheros qca953x family SOCs.
config SOC_BMIPS_BCM3380
bool "BMIPS BCM3380 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_WATCHDOG
help
config SOC_BMIPS_BCM6318
bool "BMIPS BCM6318 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6328
bool "BMIPS BCM6328 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6338
bool "BMIPS BCM6338 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6348
bool "BMIPS BCM6348 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_WATCHDOG
help
config SOC_BMIPS_BCM6358
bool "BMIPS BCM6358 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6368
bool "BMIPS BCM6368 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6362
bool "BMIPS BCM6362 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM63268
bool "BMIPS BCM63268 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_PIC32MZDA
bool "Microchip PIC32MZ[DA] family"
- select SUPPORTS_LITTLE_ENDIAN
+ select MIPS_L1_CACHE_SHIFT_4
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
- select MIPS_L1_CACHE_SHIFT_4
+ select SUPPORTS_LITTLE_ENDIAN
select SYS_MIPS_CACHE_INIT_RAM_LOAD
- select ROM_EXCEPTION_VECTORS
help
This supports Microchip PIC32MZ[DA] family of microcontrollers.
select CREATE_ARCH_SYMLINK
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
- imply USB_EHCI_HCD if USB
imply CMD_HASH
imply CMD_IRQ
+ imply USB_EHCI_HCD if USB
config MPC86xx
bool "MPC86xx"
config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
+ select BOARD_EARLY_INIT_F
select SYS_FSL_DDR
- select SYS_FSL_HAS_DDR2
select SYS_FSL_DDR_BE
- select BOARD_EARLY_INIT_F
+ select SYS_FSL_HAS_DDR2
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
config TARGET_IDS8313
bool "Support ids8313"
select DM
+ imply CMD_DM
config TARGET_KM8360
bool "Support km8360"
.text :
{
arch/riscv/cpu/ax25/start.o (.text)
- *(.text)
+ }
+
+ /* This needs to come before *(.text*) */
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ __efi_runtime_stop = .;
+ }
+
+ .text_rest :
+ {
+ *(.text*)
}
. = ALIGN(4);
. = ALIGN(4);
- .efi_runtime : {
- __efi_runtime_start = .;
- *(efi_runtime_text)
- *(efi_runtime_data)
- __efi_runtime_stop = .;
- }
-
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
- *(.relaefi_runtime_text)
- *(.relaefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM
PLATFORM_LIBS += -lrt
+LDFLAGS_FINAL += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
# Define this to avoid linking with SDL, which requires SDL libraries
# This can solve 'sdl-config: Command not found' errors
ifneq ($(NO_SDL),)
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2015 National Instruments
- *
- * (C) Copyright 2015
- * Joe Hershberger <joe.hershberger@ni.com>
+ * Copyright (c) 2015-2018 National Instruments
+ * Copyright (c) 2015-2018 Joe Hershberger <joe.hershberger@ni.com>
*/
#include <asm/eth-raw-os.h>
#include <linux/if_ether.h>
#include <linux/if_packet.h>
-static int _raw_packet_start(const char *ifname, unsigned char *ethmac,
- struct eth_sandbox_raw_priv *priv)
+struct sandbox_eth_raw_if_nameindex *sandbox_eth_raw_if_nameindex(void)
+{
+ return (struct sandbox_eth_raw_if_nameindex *)if_nameindex();
+}
+
+void sandbox_eth_raw_if_freenameindex(struct sandbox_eth_raw_if_nameindex *ptr)
+{
+ if_freenameindex((struct if_nameindex *)ptr);
+}
+
+int sandbox_eth_raw_os_is_local(const char *ifname)
+{
+ int fd = socket(AF_INET, SOCK_DGRAM, 0);
+ struct ifreq ifr;
+ int ret = 0;
+
+ if (fd < 0)
+ return -errno;
+ memset(&ifr, 0, sizeof(ifr));
+ strncpy(ifr.ifr_name, ifname, IFNAMSIZ);
+ ret = ioctl(fd, SIOCGIFFLAGS, &ifr);
+ if (ret < 0) {
+ ret = -errno;
+ goto out;
+ }
+ ret = !!(ifr.ifr_flags & IFF_LOOPBACK);
+out:
+ close(fd);
+ return ret;
+}
+
+int sandbox_eth_raw_os_idx_to_name(struct eth_sandbox_raw_priv *priv)
+{
+ if (!if_indextoname(priv->host_ifindex, priv->host_ifname))
+ return -errno;
+ return 0;
+}
+
+static int _raw_packet_start(struct eth_sandbox_raw_priv *priv,
+ unsigned char *ethmac)
{
struct sockaddr_ll *device;
struct packet_mreq mr;
int flags;
/* Prepare device struct */
+ priv->local_bind_sd = -1;
priv->device = malloc(sizeof(struct sockaddr_ll));
if (priv->device == NULL)
return -ENOMEM;
device = priv->device;
memset(device, 0, sizeof(struct sockaddr_ll));
- device->sll_ifindex = if_nametoindex(ifname);
+ device->sll_ifindex = if_nametoindex(priv->host_ifname);
+ priv->host_ifindex = device->sll_ifindex;
device->sll_family = AF_PACKET;
memcpy(device->sll_addr, ethmac, 6);
device->sll_halen = htons(6);
return -errno;
}
/* Bind to the specified interface */
- ret = setsockopt(priv->sd, SOL_SOCKET, SO_BINDTODEVICE, ifname,
- strlen(ifname) + 1);
+ ret = setsockopt(priv->sd, SOL_SOCKET, SO_BINDTODEVICE,
+ priv->host_ifname, strlen(priv->host_ifname) + 1);
if (ret < 0) {
- printf("Failed to bind to '%s': %d %s\n", ifname, errno,
- strerror(errno));
+ printf("Failed to bind to '%s': %d %s\n", priv->host_ifname,
+ errno, strerror(errno));
return -errno;
}
printf("Failed to set promiscuous mode: %d %s\n"
"Falling back to the old \"flags\" way...\n",
errno, strerror(errno));
- if (strlen(ifname) >= IFNAMSIZ) {
- printf("Interface name %s is too long.\n", ifname);
+ if (strlen(priv->host_ifname) >= IFNAMSIZ) {
+ printf("Interface name %s is too long.\n",
+ priv->host_ifname);
return -EINVAL;
}
- strncpy(ifr.ifr_name, ifname, IFNAMSIZ);
+ strncpy(ifr.ifr_name, priv->host_ifname, IFNAMSIZ);
if (ioctl(priv->sd, SIOCGIFFLAGS, &ifr) < 0) {
printf("Failed to read flags: %d %s\n", errno,
strerror(errno));
int one = 1;
/* Prepare device struct */
+ priv->local_bind_sd = -1;
+ priv->local_bind_udp_port = 0;
priv->device = malloc(sizeof(struct sockaddr_in));
if (priv->device == NULL)
return -ENOMEM;
strerror(errno));
return -errno;
}
- priv->local_bind_sd = -1;
- priv->local_bind_udp_port = 0;
return 0;
}
-int sandbox_eth_raw_os_start(const char *ifname, unsigned char *ethmac,
- struct eth_sandbox_raw_priv *priv)
+int sandbox_eth_raw_os_start(struct eth_sandbox_raw_priv *priv,
+ unsigned char *ethmac)
{
if (priv->local)
return _local_inet_start(priv);
else
- return _raw_packet_start(ifname, ethmac, priv);
+ return _raw_packet_start(priv, ethmac);
}
int sandbox_eth_raw_os_send(void *packet, int length,
int retval;
struct udphdr *udph = packet + sizeof(struct iphdr);
- if (!priv->sd || !priv->device)
+ if (priv->sd < 0 || !priv->device)
return -EINVAL;
/*
int retval;
int saddr_size;
- if (!priv->sd || !priv->device)
+ if (priv->sd < 0 || !priv->device)
return -EINVAL;
saddr_size = sizeof(struct sockaddr);
retval = recvfrom(priv->sd, packet, 1536, 0,
}
.efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
}
.__efi_runtime_stop : {
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
model = "sandbox";
aliases {
- eth5 = "/eth@90000000";
i2c0 = &i2c_0;
pci0 = &pci;
rtc0 = &rtc_0;
};
};
+ ethrawbus {
+ compatible = "sandbox,eth-raw-bus";
+ skip-localhost = <0>;
+ };
+
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
fake-host-hwaddr = [00 00 66 44 22 00];
};
- eth@80000000 {
- compatible = "sandbox,eth-raw";
- reg = <0x80000000 0x1000>;
- host-raw-interface = "eth0";
- };
-
- eth@90000000 {
- compatible = "sandbox,eth-raw";
- reg = <0x90000000 0x1000>;
- host-raw-interface = "lo";
- };
-
gpio_a: gpios@0 {
gpio-controller;
compatible = "sandbox,gpio";
model = "sandbox";
aliases {
- eth5 = "/eth@90000000";
i2c0 = &i2c_0;
pci0 = &pci;
rtc0 = &rtc_0;
};
};
+ ethrawbus {
+ compatible = "sandbox,eth-raw-bus";
+ skip-localhost = <1>;
+ };
+
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x0 0x10002000 0x0 0x1000>;
fake-host-hwaddr = [00 00 66 44 22 00];
};
- eth@80000000 {
- compatible = "sandbox,eth-raw";
- reg = <0x0 0x80000000 0x0 0x1000>;
- host-raw-interface = "eth0";
- };
-
- eth@90000000 {
- compatible = "sandbox,eth-raw";
- reg = <0x0 0x90000000 0x0 0x1000>;
- host-raw-interface = "lo";
- };
-
gpio_a: gpios@0 {
gpio-controller;
compatible = "sandbox,gpio";
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
- fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
+ fake-host-hwaddr = [00 00 66 44 22 00];
};
eth_5: eth@10003000 {
compatible = "sandbox,eth";
reg = <0x10003000 0x1000>;
- fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
+ fake-host-hwaddr = [00 00 66 44 22 11];
};
eth_3: sbe5 {
compatible = "sandbox,eth";
reg = <0x10005000 0x1000>;
- fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>;
+ fake-host-hwaddr = [00 00 66 44 22 33];
};
eth@10004000 {
compatible = "sandbox,eth";
reg = <0x10004000 0x1000>;
- fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
+ fake-host-hwaddr = [00 00 66 44 22 22];
};
gpio_a: base-gpios {
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_release_bulk(struct udevice *dev);
+/**
+ * sandbox_clk_test_valid - Ask the sandbox clock test device to check its
+ * clocks are valid.
+ *
+ * @dev: The sandbox clock test (client) devivce.
+ * @return: 0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_valid(struct udevice *dev);
#endif
#ifndef __ETH_RAW_OS_H
#define __ETH_RAW_OS_H
+#define IFNAMSIZ 16
+
/**
* struct eth_sandbox_raw_priv - raw socket session
*
* sd: socket descriptor - the open socket during a session
+ * host_ifname: interface name on the host to use for sending our packets
+ * host_ifindex: interface index number on the host
* device: struct sockaddr_ll - the host interface packets move to/from
* local: 1 or 0 to select the local interface ('lo') or not
* local_bindsd: socket descriptor to prevent the kernel from sending
*/
struct eth_sandbox_raw_priv {
int sd;
+ char host_ifname[IFNAMSIZ];
+ unsigned int host_ifindex;
void *device;
int local;
int local_bind_sd;
unsigned short local_bind_udp_port;
};
-int sandbox_eth_raw_os_start(const char *ifname, unsigned char *ethmac,
- struct eth_sandbox_raw_priv *priv);
+/* A struct to mimic if_nameindex but that does not depend on Linux headers */
+struct sandbox_eth_raw_if_nameindex {
+ unsigned int if_index; /* Index of interface (1, 2, ...) */
+ char *if_name; /* Null-terminated name ("eth0", etc.) */
+};
+
+/* Enumerate host network interfaces */
+struct sandbox_eth_raw_if_nameindex *sandbox_eth_raw_if_nameindex(void);
+/* Free the data structure of enumerated network interfaces */
+void sandbox_eth_raw_if_freenameindex(struct sandbox_eth_raw_if_nameindex *ptr);
+
+/*
+ * Check if the interface named "ifname" is a localhost interface or not.
+ * ifname - the interface name on the host to check
+ *
+ * returns - 0 if real interface, 1 if local, negative if error
+ */
+int sandbox_eth_raw_os_is_local(const char *ifname);
+
+/*
+ * Look up the name of the interface based on the ifindex populated in priv.
+ *
+ * Overwrite the host_ifname member in priv based on looking up host_ifindex
+ *
+ * returns - 0 if success, negative if error
+ */
+int sandbox_eth_raw_os_idx_to_name(struct eth_sandbox_raw_priv *priv);
+
+int sandbox_eth_raw_os_start(struct eth_sandbox_raw_priv *priv,
+ unsigned char *ethmac);
int sandbox_eth_raw_os_send(void *packet, int length,
struct eth_sandbox_raw_priv *priv);
int sandbox_eth_raw_os_recv(void *packet, int *length,
ifeq ($(IS_32BIT),y)
PLATFORM_CPPFLAGS += -march=i386 -m32
+# TODO: These break on x86_64; need to debug further
+PLATFORM_RELFLAGS += -fdata-sections
else
PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -m64
endif
#include <generated/generic-asm-offsets.h>
#include <generated/asm-offsets.h>
-.section .text
+.section .text.start
.code32
.globl _start
.type _start, @function
#include <config.h>
-.section .text
+.section .text.start
.code64
.globl _start
.type _start, @function
. = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
+
+ .text.start : { *(.text.start); }
+
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
.text : { *(.text*); }
. = ALIGN(4);
}
. = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ KEEP(*(.rodata.efi.init));
+ }
. = ALIGN(4);
.data : { *(.data*) }
. = ALIGN(4);
.got : { *(.got*) }
+ .efi_runtime_rel_start :
+ {
+ *(.__efi_runtime_rel_start)
+ }
+
+ .efi_runtime_rel : {
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
+ }
+
+ .efi_runtime_rel_stop :
+ {
+ *(.__efi_runtime_rel_stop)
+ }
+
. = ALIGN(4);
__data_end = .;
__init_end = .;
. = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
+
+ .text.start : { *(.text.start); }
+
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
.text : { *(.text*); }
. = ALIGN(4);
. = ALIGN(4);
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
binman {
filename = "u-boot.rom";
end-at-4gb;
- sort-by-pos;
+ sort-by-offset;
pad-byte = <0xff>;
size = <CONFIG_ROM_SIZE>;
#ifdef CONFIG_HAVE_INTEL_ME
#endif
#ifdef CONFIG_SPL
u-boot-spl-with-ucode-ptr {
- pos = <CONFIG_SPL_TEXT_BASE>;
+ offset = <CONFIG_SPL_TEXT_BASE>;
};
u-boot-dtb-with-ucode2 {
type = "u-boot-dtb-with-ucode";
};
u-boot {
- pos = <0xfff00000>;
+ offset = <0xfff00000>;
};
#else
u-boot-with-ucode-ptr {
- pos = <CONFIG_SYS_TEXT_BASE>;
+ offset = <CONFIG_SYS_TEXT_BASE>;
};
#endif
u-boot-dtb-with-ucode {
};
#ifdef CONFIG_HAVE_MRC
intel-mrc {
- pos = <CONFIG_X86_MRC_ADDR>;
+ offset = <CONFIG_X86_MRC_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_FSP
intel-fsp {
filename = CONFIG_FSP_FILE;
- pos = <CONFIG_FSP_ADDR>;
+ offset = <CONFIG_FSP_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_CMC
intel-cmc {
filename = CONFIG_CMC_FILE;
- pos = <CONFIG_CMC_ADDR>;
+ offset = <CONFIG_CMC_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_VGA_BIOS
intel-vga {
filename = CONFIG_VGA_BIOS_FILE;
- pos = <CONFIG_VGA_BIOS_ADDR>;
+ offset = <CONFIG_VGA_BIOS_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_VBT
intel-vbt {
filename = CONFIG_VBT_FILE;
- pos = <CONFIG_VBT_ADDR>;
+ offset = <CONFIG_VBT_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_REFCODE
intel-refcode {
- pos = <CONFIG_X86_REFCODE_ADDR>;
+ offset = <CONFIG_X86_REFCODE_ADDR>;
};
#endif
#ifdef CONFIG_SPL
x86-start16-spl {
- pos = <CONFIG_SYS_X86_START16>;
+ offset = <CONFIG_SYS_X86_START16>;
};
#else
x86-start16 {
- pos = <CONFIG_SYS_X86_START16>;
+ offset = <CONFIG_SYS_X86_START16>;
};
#endif
};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Brought in from Linux 4.1, removed things not useful to U-Boot.
- * The definitions perhaps came from the GNU Library which is GPL.
- */
-
-#ifndef _ASM_X86_ELF_H
-#define _ASM_X86_ELF_H
-
-/* ELF register definitions */
-#define R_386_NONE 0
-#define R_386_32 1
-#define R_386_PC32 2
-#define R_386_GOT32 3
-#define R_386_PLT32 4
-#define R_386_COPY 5
-#define R_386_GLOB_DAT 6
-#define R_386_JMP_SLOT 7
-#define R_386_RELATIVE 8
-#define R_386_GOTOFF 9
-#define R_386_GOTPC 10
-#define R_386_NUM 11
-
-/* x86-64 relocation types */
-#define R_X86_64_NONE 0 /* No reloc */
-#define R_X86_64_64 1 /* Direct 64 bit */
-#define R_X86_64_PC32 2 /* PC relative 32 bit signed */
-#define R_X86_64_GOT32 3 /* 32 bit GOT entry */
-#define R_X86_64_PLT32 4 /* 32 bit PLT address */
-#define R_X86_64_COPY 5 /* Copy symbol at runtime */
-#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */
-#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
-#define R_X86_64_RELATIVE 8 /* Adjust by program base */
-/* 32 bit signed pc relative offset to GOT */
-#define R_X86_64_GOTPCREL 9
-#define R_X86_64_32 10 /* Direct 32 bit zero extended */
-#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
-#define R_X86_64_16 12 /* Direct 16 bit zero extended */
-#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */
-#define R_X86_64_8 14 /* Direct 8 bit sign extended */
-#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */
-
-#define R_X86_64_NUM 16
-
-#endif
#include <common.h>
#include <efi.h>
#include <elf.h>
-#include <asm/elf.h>
efi_status_t EFIAPI _relocate(long ldbase, Elf32_Dyn *dyn)
{
#include <common.h>
#include <efi.h>
#include <elf.h>
-#include <asm/elf.h>
efi_status_t EFIAPI _relocate(long ldbase, Elf64_Dyn *dyn)
{
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
-OPENRD BOARD
-
M: Albert ARIBAUD <albert-u-boot@aribaud.net>
-S: Maintained
+OPENRD / OPENRD_CLIENT BOARD
+
#M: Albert ARIBAUD <albert-u-boot@aribaud.net>
+S: Orphaned (Since 2018-09)
F: board/Marvell/openrd/
F: include/configs/openrd.h
F: configs/openrd_base_defconfig
-
-OPENRD_CLIENT BOARD
-M: Albert ARIBAUD <albert-u-boot@aribaud.net>
-S: Maintained
F: configs/openrd_client_defconfig
F: configs/openrd_ultimate_defconfig
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
--- /dev/null
+if TARGET_SBx81LIFXCAT
+
+config SYS_BOARD
+ default "SBx81LIFXCAT"
+
+config SYS_VENDOR
+ default "alliedtelesis"
+
+config SYS_CONFIG_NAME
+ default "SBx81LIFXCAT"
+
+endif
--- /dev/null
+SBx81LIFXCAT BOARD
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: board/alliedtelesis/SBx81LIFXCAT/
+F: include/configs/SBx81LIFXCAT
+F: configs/SBx81LIFXCAT_defconfig
+F: arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010, 2018
+# Allied Telesis <www.alliedtelesis.com>
+#
+
+obj-y += sbx81lifxcat.o
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018 Allied Telesis
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+DATA 0xffd100e0 0x1b1b1b1b
+DATA 0xffd20134 0xffffffff
+DATA 0xffd20138 0x009fffff
+DATA 0xffd20154 0x00000000
+DATA 0xffd2014c 0x00000000
+DATA 0xffd20148 0x00000001
+
+# Dram initalization for 1 x x16
+# DDR II Micron part number MT47H64M16HR-3
+# MClk 333MHz, Size 128MB, ECC disable
+#
+DATA 0xffd01400 0x43000618
+DATA 0xffd01404 0x38543000
+DATA 0xffd01408 0x23125441
+DATA 0xffd0140c 0x00000832
+DATA 0xffd01410 0x0000000D
+DATA 0xffd01414 0x00000000
+DATA 0xffd01418 0x00000000
+DATA 0xffd0141c 0x00000652
+DATA 0xffd01420 0x00000042
+DATA 0xffd01424 0x0000F0FF
+DATA 0xffd01428 0x00074410
+DATA 0xffd0147C 0x00007441
+DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
+DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
+DATA 0xffd01508 0x10000000
+DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
+DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
+DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
+DATA 0xffd01494 0x84210000
+DATA 0xffd01498 0x00000000
+DATA 0xffd0149c 0x0000F80F
+DATA 0xffd01480 0x00000001
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010, 2018
+ * Allied Telesis <www.alliedtelesis.com>
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <led.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define SBX81LIFXCAT_OE_LOW (~0)
+#define SBX81LIFXCAT_OE_HIGH (~BIT(11))
+#define SBX81LIFXCAT_OE_VAL_LOW (0)
+#define SBX81LIFXCAT_OE_VAL_HIGH (BIT(11))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(SBX81LIFXCAT_OE_VAL_LOW,
+ SBX81LIFXCAT_OE_VAL_HIGH,
+ SBX81LIFXCAT_OE_LOW, SBX81LIFXCAT_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_UART1_TXD,
+ MPP14_UART1_RXD,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GE1_8,
+ MPP29_GE1_9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
+void reset_phy(void)
+{
+}
+#endif
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+ phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = led_get_by_label("status:ledp", &dev);
+ if (!ret)
+ led_set_state(dev, LEDST_ON);
+
+ ret = led_get_by_label("status:ledn", &dev);
+ if (!ret)
+ led_set_state(dev, LEDST_OFF);
+
+ return 0;
+}
+#endif
F: board/freescale/ls1046ardb/ls1046ardb.c
F: include/configs/ls1046ardb.h
F: configs/ls1046ardb_qspi_defconfig
+F: configs/ls1046ardb_qspi_spl_defconfig
F: configs/ls1046ardb_sdcard_defconfig
F: configs/ls1046ardb_emmc_defconfig
--- /dev/null
+#QSPI clk
+0957015c 40100000
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#Serdes SATA
+09eb1300 80104e20
+09eb08dc 00502880
+#PEX gen3 link
+09570158 00000300
+89400890 01048000
+89500890 01048000
+89600890 01048000
+#Alt base register
+09570158 00001000
+#flush PBI data
+096100c0 000fffff
+#Change endianness
+09550000 000f400c
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0c150010 0e000000 00000000 00000000
+11335559 40005012 40025000 c1000000
+00000000 00000000 00000000 00238800
+20124000 00003101 00000096 00000001
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 NXP Semiconductors
* Copyright 2015 Freescale Semiconductor
+ * Copyright 2017 NXP
*/
#include <common.h>
#include <malloc.h>
+++ /dev/null
-kwbimage.cfg
+++ /dev/null
-if TARGET_CONTROLCENTERDC
-
-config SYS_BOARD
- default "a38x"
-
-config SYS_VENDOR
- default "gdsys"
-
-config SYS_SOC
- default "mvebu"
-
-config SYS_CONFIG_NAME
- default "controlcenterdc"
-
-menu "Controlcenter DC board options"
-
-choice
- prompt "Select boot method"
-
-config SPL_BOOT_DEVICE_SPI
- bool "SPI"
-
-config SPL_BOOT_DEVICE_MMC
- bool "MMC"
- select SPL_LIBDISK_SUPPORT
-
-endchoice
-
-#config SPL_BOOT_DEVICE
-# int
-# default 1 if SPL_BOOT_DEVICE_SPI
-# default 2 if SPL_BOOT_DEVICE_MMC
-
-endmenu
-
-endif
obj-$(CONFIG_TARGET_CONTROLCENTERDC) += controlcenterdc.o hre.o spl.o keyprogram.o dt_helpers.o
ifeq ($(CONFIG_SPL_BUILD),)
-
obj-$(CONFIG_TARGET_CONTROLCENTERDC) += hydra.o ihs_phys.o
-
-extra-$(CONFIG_TARGET_CONTROLCENTERDC) += kwbimage.cfg
-
-KWB_REPLACE += BOOT_FROM
-ifneq ($(CONFIG_SPL_BOOT_DEVICE_SPI),)
- KWB_CFG_BOOT_FROM=spi
-endif
-ifneq ($(CONFIG_SPL_BOOT_DEVICE_MMC),)
- KWB_CFG_BOOT_FROM=sdio
-endif
-
-ifneq ($(CONFIG_SECURED_MODE_IMAGE),)
-KWB_REPLACE += CSK_INDEX
-KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)
-
-KWB_REPLACE += SEC_BOOT_DEV
-KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \
- $(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \
- $(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \
- )
-
-KWB_REPLACE += SEC_FUSE_DUMP
-KWB_CFG_SEC_FUSE_DUMP = a38x
-endif
-
-$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
- include/config/auto.conf
- $(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \
- <$< >$(dir $<)$(@F)
-
endif
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada 38x uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-#@BOOT_FROM
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Stefan Roese <sr@denx.de>
-#
-
-# Armada 38x use version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM sdio
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
*(.__image_copy_start)
board/qualcomm/dragonboard410c/head.o (.text*)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ __efi_runtime_stop = .;
+ }
+
+ .text_rest :
+ {
*(.text*)
}
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
- *(.relaefi_runtime_text)
- *(.relaefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
*(.__image_copy_start)
board/qualcomm/dragonboard820c/head.o (.text*)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ __efi_runtime_stop = .;
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(8);
- .efi_runtime : {
- __efi_runtime_start = .;
- *(efi_runtime_text)
- *(efi_runtime_data)
- __efi_runtime_stop = .;
- }
-
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
- *(.relaefi_runtime_text)
- *(.relaefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
+++ /dev/null
-#
-# Copyright (C) 2015 Stefan Roese <sr@denx.de>
-#
-
-# Armada 38x use version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM sdio
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
F: configs/A20-Olimex-SOM204-EVB_defconfig
F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+ORANGEPI ONE PLUS BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: configs/orangepi_one_plus_defconfig
+
ORANGEPI WIN/WIN PLUS BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
S: Maintained
F: configs/pine64_plus_defconfig
+PINE H64 BOARD
+M: Icenowy Zheng <icenowy@aosc.io>
+S: Maintained
+F: configs/pine_h64_defconfig
+
R16 EVB PARROT BOARD
M: Quentin Schulz <quentin.schulz@free-electrons.com>
S: Maintained
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN50I_H6)
+ /* SDC2: PC4-PC14 */
+ for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
#elif defined(CONFIG_MACH_SUN9I)
/* SDC2: PC6-PC16 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
BL31=/dev/null
fi
+if grep -q "^CONFIG_MACH_SUN50I_H6=y" .config; then
+ BL31_ADDR=0x104000
+else
+ BL31_ADDR=0x44000
+fi
+
cat << __HEADER_EOF
/dts-v1/;
type = "firmware";
arch = "arm64";
compression = "none";
- load = <0x44000>;
- entry = <0x44000>;
+ load = <$BL31_ADDR>;
+ entry = <$BL31_ADDR>;
};
__HEADER_EOF
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+
+bsp-generate: u-boot u-boot.bin
+ifdef CONFIG_ISA_ARCV2
+ $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-axs.py \
+ --header-type v2 \
+ --arc-id 0x53 \
+ --spi-flash-offset 0x200000 \
+ --image $(srctree)/u-boot.bin \
+ --elf $(srctree)/u-boot
+else
+ $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-axs.py \
+ --header-type v1 \
+ --arc-id 0x434 \
+ --spi-flash-offset 0x0 \
+ --image $(srctree)/u-boot.bin \
+ --elf $(srctree)/u-boot
+endif
+ $(Q)tools/mkimage -T script -C none -n 'uboot update script' \
+ -d $(srctree)/u-boot-update.txt \
+ $(srctree)/u-boot-update.img &> /dev/null
--- /dev/null
+#!/usr/bin/env python3
+
+#we can use binascii instead of zlib
+import os, getopt, sys, zlib
+from elftools.elf.elffile import ELFFile
+
+
+def usage(exit_code):
+ print("typical usage:")
+ print("AXS101:")
+ print(sys.argv[0] + \
+ " --header-type v1 --arc-id 0x434 --spi-flash-offset 0x0 --image u-boot.bin --elf u-boot")
+ print("AXS103:")
+ print(sys.argv[0] + \
+ " --header-type v2 --arc-id 0x53 --spi-flash-offset 0x200000 --image u-boot.bin --elf u-boot")
+ sys.exit(exit_code)
+
+
+def elf_get_entry(filename):
+ with open(filename, 'rb') as f:
+ elffile = ELFFile(f)
+ return elffile.header['e_entry']
+
+
+def calc_check_sum(filename):
+ # Calculate u-boot image check_sum: it is sum of all u-boot binary bytes
+ with open(filename, "rb") as file:
+ ba = bytearray(file.read())
+ return sum(ba) & 0xFF
+
+
+def arg_verify(uboot_bin_filename, uboot_elf_filename, header_type):
+ if not os.path.isfile(uboot_bin_filename):
+ print("uboot bin file not exists: " + uboot_bin_filename)
+ sys.exit(2)
+
+ if not os.path.isfile(uboot_elf_filename):
+ print("uboot elf file not exists: " + uboot_elf_filename)
+ sys.exit(2)
+
+ if header_type not in ("v1", "v2"):
+ print("unknown header type: " + header_type)
+ print("choose between 'v1' (most likely AXS101) and 'v2' (most likely AXS103)")
+ sys.exit(2)
+
+
+def main():
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],
+ "ht:a:s:i:l:e:",
+ ["help", "header-type=", "arc-id=", "spi-flash-offset=", "image=", "elf="])
+ except getopt.GetoptError as err:
+ print(err)
+ usage(2)
+
+ # default filenames
+ uboot_elf_filename = "u-boot"
+ uboot_bin_filename = "u-boot.bin"
+ headerised_filename = "u-boot.head"
+ uboot_scrypt_file = "u-boot-update.txt"
+
+ # default values
+ spi_flash_offset = 0x200000
+ header_type = "v2"
+ arc_id = 0x53
+
+ # initial header values: place where preloader will store u-boot binary,
+ # should be equal to CONFIG_SYS_TEXT_BASE
+ image_copy_adr = 0x81000000
+
+ # initial constant header values, do not change these values
+ magic1 = 0xdeadbeafaf # big endian byte order
+ magic2 = [ # big endian byte order
+ 0x20202a2020202020202020202a20202020207c5c2e20202020202e2f7c20202020207c2d,
+ 0x2e5c2020202f2e2d7c20202020205c2020602d2d2d6020202f20202020202f205f202020,
+ 0x205f20205c20202020207c205f60712070205f207c2020202020272e5f3d2f205c3d5f2e,
+ 0x272020202020202020605c202f60202020202020202020202020206f2020202020202020]
+
+ for opt, arg in opts:
+ if opt in ('-h', "--help"): usage(0)
+ if opt in ('-t', "--header-type"): header_type = arg
+ if opt in ('-a', "--arc-id"): arc_id = int(arg, 16)
+ if opt in ('-s', "--spi-flash-offset"): spi_flash_offset = int(arg, 16)
+ if opt in ('-i', "--image"): uboot_bin_filename = arg
+ if opt in ('-e', "--elf"): uboot_elf_filename = arg
+
+ arg_verify(uboot_bin_filename, uboot_elf_filename, header_type)
+
+ uboot_img_size = os.path.getsize(uboot_bin_filename)
+ jump_address = elf_get_entry(uboot_elf_filename)
+ check_sum = calc_check_sum(uboot_bin_filename)
+
+ # Calculate header adresses depend on header type
+ if header_type == "v2":
+ image_copy_adr -= 0x4
+ uboot_img_size += 0x4
+ # we append image so we need to append checksum
+ jmpchk_sum = sum(jump_address.to_bytes(4, byteorder='big'))
+ check_sum = (check_sum + jmpchk_sum) & 0xFF
+ imade_jump_append = True
+ else:
+ imade_jump_append = False
+
+ # write header to file
+ with open(headerised_filename, "wb") as file:
+ file.write(arc_id.to_bytes(2, byteorder='little'))
+ file.write(uboot_img_size.to_bytes(4, byteorder='little'))
+ file.write(check_sum.to_bytes(1, byteorder='little'))
+ file.write(image_copy_adr.to_bytes(4, byteorder='little'))
+ file.write(magic1.to_bytes(5, byteorder='big'))
+ for i in range(16): file.write(0x00.to_bytes(1, byteorder='little'))
+ for byte in magic2: file.write(byte.to_bytes(36, byteorder='big'))
+ for i in range(224 - len(magic2) * 36):
+ file.write(0x00.to_bytes(1, byteorder='little'))
+ if imade_jump_append:
+ file.write(jump_address.to_bytes(4, byteorder='little'))
+
+ # append u-boot image to header
+ with open(headerised_filename, "ab") as fo:
+ with open(uboot_bin_filename,'rb') as fi:
+ fo.write(fi.read())
+
+ # calc u-boot headerised image CRC32 (will be used by uboot update
+ # command for check)
+ headerised_image_crc = ""
+ with open(headerised_filename, "rb") as fi:
+ headerised_image_crc = hex(zlib.crc32(fi.read()) & 0xffffffff)
+
+ load_addr = 0x81000000
+ crc_store_adr = load_addr - 0x8
+ crc_calc_adr = crc_store_adr - 0x4
+ load_size = os.path.getsize(headerised_filename)
+ crc_calc_cmd = \
+ "crc32 " + hex(load_addr) + " " + hex(load_size) + " " + hex(crc_calc_adr)
+ crc_check_cmd = \
+ "mw.l " + hex(crc_store_adr) + " " + headerised_image_crc + " && " + \
+ crc_calc_cmd + " && " + \
+ "cmp.l " + hex(crc_store_adr) + " " + hex(crc_calc_adr) + " 1"
+
+ # make errase size to be allighned by 64K
+ if load_size & 0xFFFF == 0:
+ errase_size = load_size
+ else:
+ errase_size = load_size - (load_size & 0xFFFF) + 0x10000
+
+ # Hack to handle n25*** flash protect ops weirdness:
+ # protect unlock return fail status is region is already unlock (entire or
+ # partially). Same for lock ops.
+ # As there is no possibility to check current flash status pretend
+ # unlock & lock always success.
+ sf_unlock_cmd = \
+ "if sf protect unlock 0x0 0x4000000 ; then true ; else true ; fi"
+ sf_lock_cmd = \
+ "if sf protect lock 0x0 0x4000000 ; then true ; else true ; fi"
+
+ # u-bood CMD to load u-bood with header to SPI flash
+ sf_load_image_cmd = \
+ "fatload mmc 0:1 " + hex(load_addr) + " " + headerised_filename + " && " + \
+ "sf probe 0:0 && " + \
+ sf_unlock_cmd + " && " + \
+ "sf erase " + hex(spi_flash_offset) + " " + hex(errase_size) + " && " + \
+ "sf write " + hex(load_addr) + " " + hex(spi_flash_offset) + " " + hex(load_size) + " && " + \
+ sf_lock_cmd
+
+ update_uboot_cmd = sf_load_image_cmd + " && echo \"u-boot update: OK\""
+
+ with open(uboot_scrypt_file, "wb") as fo:
+ fo.write(update_uboot_cmd.encode('ascii'))
+
+
+if __name__ == "__main__":
+ try:
+ main()
+ except Exception as err:
+ print(err)
+ sys.exit(2)
be put on the first FAT partition of micro SD-card to be inserted in the
HSDK board.
+ Note that Python3 script is used for generation of a header, thus
+ to get that done it's required to have Python3 with elftools installed.
+ On CentOS/RHEL/Fedora this could be installed with:
+ ------------------------->8----------------------
+ sudo dnf install python3-pyelftools
+ ------------------------->8----------------------
EXECUTING U-BOOT
1. Create `u-boot.head` and `u-boot-update.scr` as discribed above with
`make bsp-generate` command.
- 2. Copy `u-boot.head` and `u-boot-update.scr` to the first the first FAT
- partition of micro SD-card.
+ 2. Copy `u-boot.head` and `u-boot-update.scr` to the first FAT partition
+ of micro SD-card.
3. Connect USB cable from the HSDK board to the developemnt host and
fire-up serial terminal.
$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
--arc-id 0x52 --image $(srctree)/u-boot.bin \
--elf $(srctree)/u-boot
- $(Q)mkimage -T script -C none -n 'uboot update script' \
+ $(Q)tools/mkimage -T script -C none -n 'uboot update script' \
-d $(srctree)/u-boot-update.txt \
$(srctree)/u-boot-update.scr &> /dev/null
F: board/technexion/pico-imx7d/
F: include/configs/pico-imx7d.h
F: configs/pico-imx7d_defconfig
+
+Technexion PICO-PI-IMX7
+M: Otavio Salvador <otavio@ossystems.com.br>
+S: Maintained
+F: configs/pico-pi-imx7d_defconfig
+++ /dev/null
-#
-# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
-#
-
-# Armada XP uses version 1 image format
-VERSION 1
-
-# Boot Media configurations
-BOOT_FROM spi
-
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
if (board_is_bbg1())
name = "BBG1";
+ if (board_is_bben())
+ name = "BBEN";
set_board_info_env(name);
/*
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
#ifdef CONFIG_DRIVER_TI_CPSW
- if (board_is_bone() || board_is_bone_lt() ||
+ if (board_is_bone() || board_is_bone_lt() || board_is_bben() ||
board_is_idk()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
#define AR8051_RGMII_TX_CLK_DLY 0x100
- if (board_is_evm_sk() || board_is_gp_evm()) {
+ if (board_is_evm_sk() || board_is_gp_evm() || board_is_bben()) {
const char *devname;
devname = miiphy_get_current_dev();
return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
}
+static inline int board_is_bben(void)
+{
+ return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "SE", 2);
+}
+
static inline int board_is_beaglebonex(void)
{
- return board_is_pb() || board_is_bone() || board_is_bone_lt() || board_is_bbg1();
+ return board_is_pb() || board_is_bone() || board_is_bone_lt() ||
+ board_is_bbg1() || board_is_bben();
}
static inline int board_is_evm_sk(void)
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux_sk_evm);
} else if (board_is_bone_lt()) {
+ if (board_is_bben()) {
+ /* SanCloud Beaglebone LT Enhanced pinmux */
+ configure_module_pin_mux(rgmii1_pin_mux);
+ } else {
+ /* Beaglebone LT pinmux */
+ configure_module_pin_mux(mii1_pin_mux);
+ }
/* Beaglebone LT pinmux */
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
*(.vectors)
CPUDIR/start.o (.text*)
board/ti/am335x/built-in.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(4);
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
config XILINX_MICROBLAZE0_HW_VER
string "Core version number"
- default 7.10.d
+ default "7.10.d"
endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * Procedure to generate this file (using Vivado Webpack 2018.2):
+ * + Install board files from digilent/vivado-boards repository
+ * (commit 6a45981 from 2018-06-05)
+ * + Start Vivado and create a new RTL project with the Zybo-z7-20 board
+ * + Create a block design
+ * - Add "ZYNQ7 Processing System" IP
+ * - Run "Block Automation" (Check "Apply Board Preset")
+ * - Connect ports FCLK_CLK0 and M_AXI_GP0_ACLK
+ * - Save diagram changes
+ * - Go to sources view, select the block diagram,
+ * and select "Generate Output Products"
+ * + Copy the generated "ps7_init_gpl.c" file
+ * + Perform manual editions based on existing Zynq boards
+ * and the checkpatch.pl script
+ *
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00027000U),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00027000U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C00U),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00028800U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x0000007AU),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000073U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F1U),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F1U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F7U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000BAU),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000BCU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000B3U),
+ EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001302U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001303U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001305U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001305U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001305U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001304U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002F0037U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U),
+ EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00004000U),
+ EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_WRITE(0xF8000004, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ int ret = -1;
+
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ int ret;
+
+ ret = ps7_config(ps7_mio_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
F: board/xilinx/zynqmp/
F: include/configs/xilinx_zynqmp*
F: configs/xilinx_zynqmp*
+F: configs/avnet_ultra96_rev1_defconfig
--- /dev/null
+zynqmp-zcu100-revC
\ No newline at end of file
config CMD_CONFIG
bool "config"
- select BUILD_BIN2C
default SANDBOX
+ select BUILD_BIN2C
help
Print ".config" contents.
config CMD_CRC32
bool "crc32"
- select HASH
default y
+ select HASH
help
Compute CRC32.
config CMD_DM
bool "dm - Access to driver model information"
depends on DM
- default y
help
Provides access to driver model data structures and information,
such as a list of devices, list of uclasses and the state of each
config CMD_GPT
bool "GPT (GUID Partition Table) command"
- select PARTITION_UUIDS
select EFI_PARTITION
select HAVE_BLOCK_DEVICE
+ select PARTITION_UUIDS
imply RANDOM_UUID
help
Enable the 'gpt' command to ready and write GPT style partition
config CMD_PART
bool "part"
- select PARTITION_UUIDS
select HAVE_BLOCK_DEVICE
+ select PARTITION_UUIDS
help
Read and display information about the partition table on
various media.
help
Enables the command "sdp" which is used to have U-Boot emulating the
Serial Download Protocol (SDP) via USB.
+
config CMD_ROCKUSB
bool "rockusb"
depends on USB_FUNCTION_ROCKUSB
help
- Rockusb protocol is widely used by Rockchip SoC based devices. It can
+ Rockusb protocol is widely used by Rockchip SoC based devices. It can
read/write info, image to/from devices. This enable rockusb command
support to communication with rockusb device. for more detail about
this command, please read doc/README.rockusb.
the original data.
Sub-commands:
- blob enc - encapsulating data as a cryptgraphic blob
+ blob enc - encapsulating data as a cryptgraphic blob
blob dec - decapsulating cryptgraphic blob to get the data
Syntax:
config CMD_TPM_V2
bool
+ select CMD_LOG
config CMD_TPM
bool "Enable the 'tpm' command"
config CMD_UBI
tristate "Enable UBI - Unsorted block images commands"
+ default y if NAND_SUNXI
+ select CMD_MTDPARTS
select CRC32
select MTD_UBI
- select CMD_MTDPARTS
- default y if NAND_SUNXI
help
UBI is a software layer above MTD layer which admits use of LVM-like
logical volumes on top of MTD devices, hides some complexities of
config CMD_UBIFS
tristate "Enable UBIFS - Unsorted block images filesystem commands"
depends on CMD_UBI
+ default y if CMD_UBI
select CRC32
select LZO
- default y if CMD_UBI
help
UBIFS is a file system for flash devices which works on top of UBI.
#include <errno.h>
#include <linux/libfdt.h>
#include <linux/libfdt_env.h>
+#include <mapmem.h>
#include <memalign.h>
#include <asm/global_data.h>
#include <asm-generic/sections.h>
#include <asm-generic/unaligned.h>
#include <linux/linkage.h>
+#ifdef CONFIG_ARMV7_NONSEC
+#include <asm/armv7.h>
+#include <asm/secure.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#define OBJ_LIST_NOT_INITIALIZED 1
if (efi_obj_list_initialized != OBJ_LIST_NOT_INITIALIZED)
return efi_obj_list_initialized;
+ /* Initialize system table */
+ ret = efi_initialize_system_table();
+ if (ret != EFI_SUCCESS)
+ goto out;
+
/* Initialize EFI driver uclass */
ret = efi_driver_init();
if (ret != EFI_SUCCESS)
ret = efi_reset_system_init();
if (ret != EFI_SUCCESS)
goto out;
- ret = efi_get_time_init();
- if (ret != EFI_SUCCESS)
- goto out;
out:
efi_obj_list_initialized = ret;
fdt_ram_start = ram_start;
}
- /* Give us at least 4kb breathing room */
- fdt_size = ALIGN(fdt_size + 4096, EFI_PAGE_SIZE);
+ /*
+ * Give us at least 4KB of breathing room in case the device tree needs
+ * to be expanded later. Round up to the nearest EFI page boundary.
+ */
+ fdt_size += 4096;
+ fdt_size = ALIGN(fdt_size + EFI_PAGE_SIZE - 1, EFI_PAGE_SIZE);
fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
/* Safe fdt location is at 128MB */
}
#endif
-/* Carve out DT reserved memory ranges */
-static efi_status_t efi_carve_out_dt_rsv(void *fdt)
+#ifdef CONFIG_ARMV7_NONSEC
+static bool is_nonsec;
+
+static efi_status_t efi_run_in_hyp(EFIAPI efi_status_t (*entry)(
+ efi_handle_t image_handle, struct efi_system_table *st),
+ efi_handle_t image_handle, struct efi_system_table *st)
+{
+ /* Enable caches again */
+ dcache_enable();
+
+ is_nonsec = true;
+
+ return efi_do_enter(image_handle, st, entry);
+}
+#endif
+
+/*
+ * efi_carve_out_dt_rsv() - Carve out DT reserved memory ranges
+ *
+ * The mem_rsv entries of the FDT are added to the memory map. Any failures are
+ * ignored because this is not critical and we would rather continue to try to
+ * boot.
+ *
+ * @fdt: Pointer to device tree
+ */
+static void efi_carve_out_dt_rsv(void *fdt)
{
int nr_rsv, i;
uint64_t addr, size, pages;
continue;
pages = ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT;
- efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
- false);
+ if (!efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
+ false))
+ printf("FDT memrsv map %d: Failed to add to map\n", i);
}
-
- return EFI_SUCCESS;
}
static efi_status_t efi_install_fdt(void *fdt)
return EFI_LOAD_ERROR;
}
- if (efi_carve_out_dt_rsv(fdt) != EFI_SUCCESS) {
- printf("ERROR: failed to carve out memory\n");
- return EFI_LOAD_ERROR;
- }
+ efi_carve_out_dt_rsv(fdt);
/* Link to it in the efi tables */
ret = efi_install_configuration_table(&efi_guid_fdt, fdt);
}
#endif
+#ifdef CONFIG_ARMV7_NONSEC
+ if (armv7_boot_nonsec() && !is_nonsec) {
+ dcache_disable(); /* flush cache before switch to HYP */
+
+ armv7_init_nonsec();
+ secure_ram_addr(_do_nonsec_entry)(
+ efi_run_in_hyp,
+ (uintptr_t)entry,
+ (uintptr_t)loaded_image_info_obj.handle,
+ (uintptr_t)&systab);
+
+ /* Should never reach here, efi exits with longjmp */
+ while (1) { }
+ }
+#endif
+
ret = efi_do_enter(loaded_image_info_obj.handle, &systab, entry);
exit:
unsigned long addr;
char *saddr;
efi_status_t r;
- void *fdt_addr;
+ unsigned long fdt_addr;
+ void *fdt;
/* Allow unaligned memory access */
allow_unaligned();
return CMD_RET_USAGE;
if (argc > 2) {
- fdt_addr = (void *)simple_strtoul(argv[2], NULL, 16);
+ fdt_addr = simple_strtoul(argv[2], NULL, 16);
if (!fdt_addr && *argv[2] != '0')
return CMD_RET_USAGE;
/* Install device tree */
- r = efi_install_fdt(fdt_addr);
+ fdt = map_sysmem(fdt_addr, 0);
+ r = efi_install_fdt(fdt);
if (r != EFI_SUCCESS) {
printf("ERROR: failed to install device tree\n");
return CMD_RET_FAILURE;
addr = simple_strtoul(saddr, NULL, 16);
else
addr = CONFIG_SYS_LOAD_ADDR;
- memcpy((char *)addr, __efi_helloworld_begin, size);
+ memcpy(map_sysmem(addr, size), __efi_helloworld_begin, size);
} else
#endif
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
}
printf("## Starting EFI application at %08lx ...\n", addr);
- r = do_bootefi_exec((void *)addr, bootefi_device_path,
+ r = do_bootefi_exec(map_sysmem(addr, 0), bootefi_device_path,
bootefi_image_path);
printf("## Application terminated, r = %lu\n",
r & ~EFI_ERROR_MASK);
switch (argc) {
case 1:
+ /* refresh bootfile name from env */
+ copy_filename(net_boot_file_name, env_get("bootfile"),
+ sizeof(net_boot_file_name));
break;
case 2: /*
addr = simple_strtoul(argv[1], &end, 16);
if (end == (argv[1] + strlen(argv[1]))) {
load_addr = addr;
+ /* refresh bootfile name from env */
+ copy_filename(net_boot_file_name, env_get("bootfile"),
+ sizeof(net_boot_file_name));
} else {
net_boot_file_name_explicit = true;
copy_filename(net_boot_file_name, argv[1],
int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *tpm_commands, *cmd;
+ struct tpm_chip_priv *priv;
+ struct udevice *dev;
unsigned int size;
+ int ret;
if (argc < 2)
return CMD_RET_USAGE;
- tpm_commands = get_tpm_commands(&size);
+ ret = get_tpm(&dev);
+ if (ret)
+ return ret;
+
+ priv = dev_get_uclass_priv(dev);
+
+ /* Below getters return NULL if the desired stack is not built */
+ switch (priv->version) {
+ case TPM_V1:
+ tpm_commands = get_tpm1_commands(&size);
+ break;
+ case TPM_V2:
+ tpm_commands = get_tpm2_commands(&size);
+ break;
+ default:
+ tpm_commands = NULL;
+ }
+
+ if (!tpm_commands)
+ return CMD_RET_USAGE;
cmd = find_cmd_tbl(argv[1], tpm_commands, size);
if (!cmd)
#endif /* CONFIG_TPM_LIST_RESOURCES */
};
-cmd_tbl_t *get_tpm_commands(unsigned int *size)
+cmd_tbl_t *get_tpm1_commands(unsigned int *size)
{
*size = ARRAY_SIZE(tpm1_commands);
do_tpm_pcr_setauthvalue, "", ""),
};
-cmd_tbl_t *get_tpm_commands(unsigned int *size)
+cmd_tbl_t *get_tpm2_commands(unsigned int *size)
{
*size = ARRAY_SIZE(tpm2_commands);
return tpm2_commands;
}
-U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command",
+U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command",
"<command> [<arguments>]\n"
"\n"
"info\n"
config LOG
bool "Enable logging support"
- select DM
+ depends on DM
help
This enables support for logging of status and debug messages. These
can be displayed on the console, recorded in a memory buffer, or
{
int i, ret;
struct stdio_dev *dev;
+ int prev;
- disable_ctrlc(1);
+ prev = disable_ctrlc(1);
for (i = 0; i < cd_count[file]; i++) {
dev = console_devices[file][i];
if (dev->tstc != NULL) {
ret = dev->tstc(dev);
if (ret > 0) {
tstcdev = dev;
- disable_ctrlc(0);
+ disable_ctrlc(prev);
return ret;
}
}
}
- disable_ctrlc(0);
+ disable_ctrlc(prev);
return 0;
}
static int ctrlc_was_pressed = 0;
int ctrlc(void)
{
-#ifndef CONFIG_SANDBOX
if (!ctrlc_disabled && gd->have_console) {
if (tstc()) {
switch (getc()) {
}
}
}
-#endif
return 0;
}
return p - (char *)buf;
}
-#ifdef CONFIG_NR_DRAM_BANKS
-#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
-#else
#define MEMORY_BANKS_MAX 4
-#endif
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
{
int err, nodeoffset;
unsigned int r1;
};
-int fdt_del_subnodes(const void *blob, int parent_offset)
+static int fdt_del_subnodes(const void *blob, int parent_offset)
{
int off, ndepth;
int ret;
return 0;
}
-int fdt_del_partitions(void *blob, int parent_offset)
+static int fdt_del_partitions(void *blob, int parent_offset)
{
const void *prop;
int ndepth = 0;
config SPL_FIT_IMAGE_TINY
bool "Remove functionality from SPL FIT loading to reduce size"
depends on SPL_FIT
- default y if MACH_SUN50I || MACH_SUN50I_H5
+ default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
help
Enable this to reduce the size of the FIT image loading code
in SPL, if space for the SPL binary is very tight.
endif # SPL_OS_BOOT
+config SPL_PAYLOAD
+ string "SPL payload"
+ default "tpl/u-boot-with-tpl.bin" if TPL
+ default "u-boot.bin"
+ help
+ Payload for SPL boot. For backward compability, default to
+ u-boot.bin, i.e. RAW image without any header. In case of
+ TPL, tpl/u-boot-with-tpl.bin. For new boards, suggest to
+ use u-boot.img.
+
config SPL_PCI_SUPPORT
bool "Support PCI drivers"
help
in drivers/power, drivers/power/pmic and drivers/power/regulator
as part of an SPL build.
+config SPL_POWER_DOMAIN
+ bool "Support power domain drivers"
+ help
+ Enable support for power domain control in SPL. Many SoCs allow
+ power to be applied to or removed from portions of the SoC (power
+ domains). This may be used to save power. This API provides the
+ means to control such power management hardware. This enables
+ the drivers in drivers/power/domain as part of a SPL build.
+
config SPL_RAM_SUPPORT
bool "Support booting from RAM"
default y if MICROBLAZE || ARCH_SOCFPGA || TEGRA || ARCH_ZYNQ
u32 *boot_params_ptr = NULL;
/* See spl.h for information about this */
-binman_sym_declare(ulong, u_boot_any, pos);
+binman_sym_declare(ulong, u_boot_any, image_pos);
/* Define board data structure */
static bd_t bdata __attribute__ ((section(".data")));
void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
{
- ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
+ ulong u_boot_pos = binman_sym(ulong, u_boot_any, image_pos);
spl_image->size = CONFIG_SYS_MONITOR_LEN;
load.read = spl_ram_load_read;
spl_load_simple_fit(spl_image, &load, 0, header);
} else {
- ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
+ ulong u_boot_pos = binman_sym(ulong, u_boot_any, image_pos);
debug("Legacy image\n");
/*
CONFIG_MV88E61XX_CPU_PORT=10
CONFIG_MV88E61XX_PHY_PORTS=0x003
CONFIG_MV88E61XX_FIXED_PORTS=0x300
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_TEXT_BASE=0x00600000
+CONFIG_TARGET_SBx81LIFXCAT=y
+CONFIG_IDENT_STRING="\nSBx81LIFXCAT"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifxcat"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SILENT_U_BOOT_ONLY=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_NTPSERVER=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+# CONFIG_CMD_LED is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_MV88E61XX_SWITCH=y
+CONFIG_MV88E61XX_CPU_PORT=10
+CONFIG_MV88E61XX_PHY_PORTS=0x003
+CONFIG_MV88E61XX_FIXED_PORTS=0x300
+CONFIG_MV88E61XX_RGMII_DELAY=y
+CONFIG_SPI=y
+CONFIG_KIRKWOOD_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_MP=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C1=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_WDT=y
+CONFIG_WDT_CDNS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_OHCI_HCD=y
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry"
+CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
+CONFIG_SCSI_AHCI=y
CONFIG_AXP_DLDO4_VOLT=2500
CONFIG_AXP_ELDO3_VOLT=1200
+CONFIG_SCSI=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CLEARFOG=y
+CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_TARGET_DNS325=y
CONFIG_IDENT_STRING="\nD-Link DNS-325"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TARGET_DREAMPLUG=y
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DS109=y
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TARGET_GURUPLUG=y
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_HELIOS4=y
+CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_OS_BASE=0x40980000
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_SPL_GZIP=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_TARGET_NAS220=y
CONFIG_IDENT_STRING="\nNAS 220"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_OF_PLATDATA=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
-# CONFIG_BLK is not set
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_DM_I2C=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="TI"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H6=y
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-one-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H6=y
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_TPM2_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_FS_CRAMFS=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
+CONFIG_TPM_V1=y
+CONFIG_TPM_V2=y
CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_TARGET_SHEEVAPLUG=y
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug"
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_NETDEVICES=y
CONFIG_MVGBE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
-# CONFIG_BLK is not set
CONFIG_DM_MMC=y
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
-# CONFIG_BLK is not set
CONFIG_DM_MMC=y
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
-# CONFIG_BLK is not set
CONFIG_DM_MMC=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_ARM_PL180_MMCI=y
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_ADC=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_STM32_ADC=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_DM_MMC=y
# CONFIG_NET is not set
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_SPI=y
CONFIG_CF_SPI=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C1=y
CONFIG_LED=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C0=y
CONFIG_ZYNQ_I2C1=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C0=y
CONFIG_ZYNQ_I2C1=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
CONFIG_SYS_I2C_ZYNQ=y
CONFIG_ZYNQ_I2C0=y
CONFIG_ZYNQ_I2C1=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ENV_SIZE=0x190
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
CONFIG_ENV_SIZE=0x190
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_SYS_MALLOC_LEN=0x1000
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
CONFIG_BOOTDELAY=-1
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_ZYNQ_DDRC_INIT is not set
+CONFIG_SYS_MALLOC_LEN=0x1000
# CONFIG_CMD_ZYNQ is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
CONFIG_DEBUG_UART=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo-z7"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_REALTEK=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_THOR=y
* persistence
* runtime support
-* support bootefi booting ARMv7 in non-secure mode (CONFIG_ARMV7_NONSEC=y)
-
## Links
* [1](http://uefi.org/specifications)
--- /dev/null
+STMicroelectronics STM32 ADC device
+
+STM32 ADC is a successive approximation analog-to-digital converter.
+It has several multiplexed input channels. Conversions can be performed
+in single, continuous, scan or discontinuous mode. Result of the ADC is
+stored in a left-aligned or right-aligned 32-bit data register.
+Conversions can be launched in software or using hardware triggers.
+
+The analog watchdog feature allows the application to detect if the input
+voltage goes beyond the user-defined, higher or lower thresholds.
+
+Each STM32 ADC block can have up to 3 ADC instances.
+
+Each instance supports two contexts to manage conversions, each one has its
+own configurable sequence and trigger:
+- regular conversion can be done in sequence, running in background
+- injected conversions have higher priority, and so have the ability to
+ interrupt regular conversion sequence (either triggered in SW or HW).
+ Regular sequence is resumed, in case it has been interrupted.
+
+Contents of a stm32 adc root node:
+-----------------------------------
+Required properties:
+- compatible: Should be one of:
+ "st,stm32f4-adc-core"
+ "st,stm32h7-adc-core"
+ "st,stm32mp1-adc-core"
+- reg: Offset and length of the ADC block register set.
+- interrupts: One or more interrupts for ADC block. Some parts like stm32f4
+ and stm32h7 share a common ADC interrupt line. stm32mp1 has two separate
+ interrupt lines, one for each ADC within ADC block.
+- clocks: Core can use up to two clocks, depending on part used:
+ - "adc" clock: for the analog circuitry, common to all ADCs.
+ It's required on stm32f4.
+ It's optional on stm32h7.
+ - "bus" clock: for registers access, common to all ADCs.
+ It's not present on stm32f4.
+ It's required on stm32h7.
+- clock-names: Must be "adc" and/or "bus" depending on part used.
+- interrupt-controller: Identifies the controller node as interrupt-parent
+- vref-supply: Phandle to the vref input analog reference voltage.
+- #interrupt-cells = <1>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties:
+- A pinctrl state named "default" for each ADC channel may be defined to set
+ inX ADC pins in mode of operation for analog input on external pin.
+
+Contents of a stm32 adc child node:
+-----------------------------------
+An ADC block node should contain at least one subnode, representing an
+ADC instance available on the machine.
+
+Required properties:
+- compatible: Should be one of:
+ "st,stm32f4-adc"
+ "st,stm32h7-adc"
+ "st,stm32mp1-adc"
+- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
+- clocks: Input clock private to this ADC instance. It's required only on
+ stm32f4, that has per instance clock input for registers access.
+- interrupt-parent: Phandle to the parent interrupt controller.
+- interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
+ 2 for adc@200).
+- st,adc-channels: List of single-ended channels muxed for this ADC.
+ It can have up to 16 channels on stm32f4 or 20 channels on stm32h7, numbered
+ from 0 to 15 or 19 (resp. for in0..in15 or in0..in19).
+- st,adc-diff-channels: List of differential channels muxed for this ADC.
+ Depending on part used, some channels can be configured as differential
+ instead of single-ended (e.g. stm32h7). List here positive and negative
+ inputs pairs as <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered
+ from 0 to 19 on stm32h7)
+ Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is required.
+ Both properties can be used together. Some channels can be used as
+ single-ended and some other ones as differential (mixed). But channels
+ can't be configured both as single-ended and differential (invalid).
+- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
+ Documentation/devicetree/bindings/iio/iio-bindings.txt
+
+Optional properties:
+- dmas: Phandle to dma channel for this ADC instance.
+ See ../../dma/dma.txt for details.
+- dma-names: Must be "rx" when dmas property is being used.
+- assigned-resolution-bits: Resolution (bits) to use for conversions. Must
+ match device available resolutions:
+ * can be 6, 8, 10 or 12 on stm32f4
+ * can be 8, 10, 12, 14 or 16 on stm32h7
+ Default is maximum resolution if unset.
+- st,min-sample-time-nsecs: Minimum sampling time in nanoseconds.
+ Depending on hardware (board) e.g. high/low analog input source impedance,
+ fine tune of ADC sampling time may be recommended.
+ This can be either one value or an array that matches 'st,adc-channels' list,
+ to set sample time resp. for all channels, or independently for each channel.
+
+Example:
+ adc: adc@40012000 {
+ compatible = "st,stm32f4-adc-core";
+ reg = <0x40012000 0x400>;
+ interrupts = <18>;
+ clocks = <&rcc 0 168>;
+ clock-names = "adc";
+ vref-supply = <®_vref>;
+ interrupt-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc3_in8_pin>;
+
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "st,stm32f4-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ clocks = <&rcc 0 168>;
+ interrupt-parent = <&adc>;
+ interrupts = <0>;
+ st,adc-channels = <8>;
+ dmas = <&dma2 0 0 0x400 0x0>;
+ dma-names = "rx";
+ assigned-resolution-bits = <8>;
+ };
+ ...
+ other adc child nodes follow...
+ };
+
+Example to setup:
+- channel 1 as single-ended
+- channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
+
+ adc: adc@40022000 {
+ compatible = "st,stm32h7-adc-core";
+ ...
+ adc1: adc@0 {
+ compatible = "st,stm32h7-adc";
+ ...
+ st,adc-channels = <1>;
+ st,adc-diff-channels = <2 6>, <3 7>;
+ };
+ };
--- /dev/null
+GPIO via CREG (control registers) driver
+
+31 9 7 5 0 < bit number
+| | | | |
+[ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register
+ ^ ^
+ | |
+ write 0x2 == set output to "1" (activate)
+ write 0x3 == set output to "0" (deactivate)
+
+Required properties:
+- compatible : "snps,creg-gpio"
+- reg : Exactly one register range with length 0x4.
+- #gpio-cells : Should be one - the pin number.
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-count: Number of GPIO pins.
+- gpio-bit-per-line: Number of bits per gpio line (see picture).
+- gpio-first-shift: Shift (in bits) of the first GPIO field in register
+ (see picture).
+- gpio-activate-val: Value should be set in corresponding field to set
+ output to "1" (see picture). Applied to all GPIO ports.
+- gpio-deactivate-val: Value should be set in corresponding field to set
+ output to "0" (see picture). Applied to all GPIO ports.
+
+Optional properties:
+- gpio-bank-name: name of bank (as default driver name is used is used)
+- gpio-default-val: array of default output values (must me 0 or 1)
+
+Example (see picture):
+
+gpio: gpio@f00014b0 {
+ compatible = "snps,creg-gpio";
+ reg = <0xf00014b0 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "hsdk-spi-cs";
+ gpio-count = <2>;
+ gpio-first-shift = <5>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <2>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1 1>;
+};
allocate it yourself in ofdata_to_platdata(). Note that it is preferable
to do all the device tree decoding in ofdata_to_platdata() rather than
in probe(). (Apart from the ugliness of mixing configuration and run-time
- data, one day it is possible that U-Boot will cache platformat data for
+ data, one day it is possible that U-Boot will cache platform data for
devices which are regularly de/activated).
h. The device's probe() method is called. This should do anything that
alias angelo_ts Angelo Dureghello <angelo@sysam.it>
alias bmeng Bin Meng <bmeng.cn@gmail.com>
alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-alias dinh Dinh Nguyen <dinguyen@kernel.org>
+alias dinh Dinh Nguyen <dinguyen@kernel.org>
alias hs Heiko Schocher <hs@denx.de>
alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
alias jaehoon Jaehoon Chung <jh80.chung@samsung.com>
alias mariosix Mario Six <mario.six@gdsys.cc>
alias masahiro Masahiro Yamada <yamada.masahiro@socionext.com>
alias mateusz Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
-alias maxime Maxime Ripard <maxime.ripard@free-electrons.com>
+alias maxime Maxime Ripard <maxime.ripard@free-electrons.com>
alias monstr Michal Simek <monstr@monstr.eu>
alias prafulla Prafulla Wadaskar <prafulla@marvell.com>
alias prom Minkyu Kang <mk7.kang@samsung.com>
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
+obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/
obj-$(CONFIG_SPL_DM_RESET) += reset/
obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
- 2~6 analog input channels
- 1O or 12 bits resolution
- Up to 1MSPS of sample rate
+
+config STM32_ADC
+ bool "Enable STMicroelectronics STM32 ADC driver"
+ depends on ADC && (STM32H7 || ARCH_STM32MP)
+ help
+ This enables driver for STMicroelectronics STM32 analog-to-digital
+ converter (ADC).
+ A STM32 ADC block can be composed of several individual ADCs.
+ Each has its own private registers, but shares some resources:
+ - clock selection and prescaler
+ - voltage reference
+ - common registers area.
+ STM32 ADC driver is composed of:
+ - core driver to deal with common resources
+ - child driver to deal with individual ADC resources (declare ADC
+ device and associated channels, start/stop conversions)
obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o
obj-$(CONFIG_SARADC_MESON) += meson-saradc.o
+obj-$(CONFIG_STM32_ADC) += stm32-adc.o stm32-adc-core.o
* will bind before its supply regulator device, then the below 'get'
* will return an error.
*/
- ret = device_get_supply_regulator(dev, "vdd-supply",
- &uc_pdata->vdd_supply);
- if (ret)
- return ret;
+ if (!uc_pdata->vdd_supply)
+ return 0;
ret = regulator_get_value(uc_pdata->vdd_supply);
if (ret < 0)
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
int ret;
- ret = device_get_supply_regulator(dev, "vss-supply",
- &uc_pdata->vss_supply);
- if (ret)
- return ret;
+ if (!uc_pdata->vss_supply)
+ return 0;
ret = regulator_get_value(uc_pdata->vss_supply);
if (ret < 0)
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
int ret, value_sign = uc_pdata->vdd_polarity_negative ? -1 : 1;
- if (!uc_pdata->vdd_supply)
- goto nodev;
-
/* Update the regulator Value. */
ret = adc_vdd_platdata_update(dev);
if (ret)
return ret;
-nodev:
+
if (uc_pdata->vdd_microvolts == -ENODATA)
return -ENODATA;
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
int ret, value_sign = uc_pdata->vss_polarity_negative ? -1 : 1;
- if (!uc_pdata->vss_supply)
- goto nodev;
-
/* Update the regulator Value. */
ret = adc_vss_platdata_update(dev);
if (ret)
return ret;
-nodev:
+
if (uc_pdata->vss_microvolts == -ENODATA)
return -ENODATA;
prop = "vdd-polarity-negative";
uc_pdata->vdd_polarity_negative = dev_read_bool(dev, prop);
- ret = adc_vdd_platdata_update(dev);
+ /* Optionally get regulators */
+ ret = device_get_supply_regulator(dev, "vdd-supply",
+ &uc_pdata->vdd_supply);
+ if (!ret)
+ return adc_vdd_platdata_update(dev);
+
if (ret != -ENOENT)
return ret;
prop = "vss-polarity-negative";
uc_pdata->vss_polarity_negative = dev_read_bool(dev, prop);
- ret = adc_vss_platdata_update(dev);
+ ret = device_get_supply_regulator(dev, "vss-supply",
+ &uc_pdata->vss_supply);
+ if (!ret)
+ return adc_vss_platdata_update(dev);
+
if (ret != -ENOENT)
return ret;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
+ *
+ * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.c.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <power/regulator.h>
+#include "stm32-adc-core.h"
+
+/* STM32H7 - common registers for all ADC instances */
+#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
+
+/* STM32H7_ADC_CCR - bit fields */
+#define STM32H7_PRESC_SHIFT 18
+#define STM32H7_PRESC_MASK GENMASK(21, 18)
+#define STM32H7_CKMODE_SHIFT 16
+#define STM32H7_CKMODE_MASK GENMASK(17, 16)
+
+/* STM32 H7 maximum analog clock rate (from datasheet) */
+#define STM32H7_ADC_MAX_CLK_RATE 36000000
+
+/**
+ * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
+ * @ckmode: ADC clock mode, Async or sync with prescaler.
+ * @presc: prescaler bitfield for async clock mode
+ * @div: prescaler division ratio
+ */
+struct stm32h7_adc_ck_spec {
+ u32 ckmode;
+ u32 presc;
+ int div;
+};
+
+static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
+ /* 00: CK_ADC[1..3]: Asynchronous clock modes */
+ { 0, 0, 1 },
+ { 0, 1, 2 },
+ { 0, 2, 4 },
+ { 0, 3, 6 },
+ { 0, 4, 8 },
+ { 0, 5, 10 },
+ { 0, 6, 12 },
+ { 0, 7, 16 },
+ { 0, 8, 32 },
+ { 0, 9, 64 },
+ { 0, 10, 128 },
+ { 0, 11, 256 },
+ /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
+ { 1, 0, 1 },
+ { 2, 0, 2 },
+ { 3, 0, 4 },
+};
+
+static int stm32h7_adc_clk_sel(struct udevice *dev,
+ struct stm32_adc_common *common)
+{
+ u32 ckmode, presc;
+ unsigned long rate;
+ int i, div;
+
+ /* stm32h7 bus clock is common for all ADC instances (mandatory) */
+ if (!clk_valid(&common->bclk)) {
+ dev_err(dev, "No bclk clock found\n");
+ return -ENOENT;
+ }
+
+ /*
+ * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
+ * So, choice is to have bus clock mandatory and adc clock optional.
+ * If optional 'adc' clock has been found, then try to use it first.
+ */
+ if (clk_valid(&common->aclk)) {
+ /*
+ * Asynchronous clock modes (e.g. ckmode == 0)
+ * From spec: PLL output musn't exceed max rate
+ */
+ rate = clk_get_rate(&common->aclk);
+ if (!rate) {
+ dev_err(dev, "Invalid aclk rate: 0\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
+ ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
+ presc = stm32h7_adc_ckmodes_spec[i].presc;
+ div = stm32h7_adc_ckmodes_spec[i].div;
+
+ if (ckmode)
+ continue;
+
+ if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
+ goto out;
+ }
+ }
+
+ /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
+ rate = clk_get_rate(&common->bclk);
+ if (!rate) {
+ dev_err(dev, "Invalid bus clock rate: 0\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
+ ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
+ presc = stm32h7_adc_ckmodes_spec[i].presc;
+ div = stm32h7_adc_ckmodes_spec[i].div;
+
+ if (!ckmode)
+ continue;
+
+ if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
+ goto out;
+ }
+
+ dev_err(dev, "clk selection failed\n");
+ return -EINVAL;
+
+out:
+ /* rate used later by each ADC instance to control BOOST mode */
+ common->rate = rate / div;
+
+ /* Set common clock mode and prescaler */
+ clrsetbits_le32(common->base + STM32H7_ADC_CCR,
+ STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK,
+ ckmode << STM32H7_CKMODE_SHIFT |
+ presc << STM32H7_PRESC_SHIFT);
+
+ dev_dbg(dev, "Using %s clock/%d source at %ld kHz\n",
+ ckmode ? "bus" : "adc", div, common->rate / 1000);
+
+ return 0;
+}
+
+static int stm32_adc_core_probe(struct udevice *dev)
+{
+ struct stm32_adc_common *common = dev_get_priv(dev);
+ int ret;
+
+ common->base = dev_read_addr_ptr(dev);
+ if (!common->base) {
+ dev_err(dev, "can't get address\n");
+ return -ENOENT;
+ }
+
+ ret = device_get_supply_regulator(dev, "vref-supply", &common->vref);
+ if (ret) {
+ dev_err(dev, "can't get vref-supply: %d\n", ret);
+ return ret;
+ }
+
+ ret = regulator_get_value(common->vref);
+ if (ret < 0) {
+ dev_err(dev, "can't get vref-supply value: %d\n", ret);
+ return ret;
+ }
+ common->vref_uv = ret;
+
+ ret = clk_get_by_name(dev, "adc", &common->aclk);
+ if (!ret) {
+ ret = clk_enable(&common->aclk);
+ if (ret) {
+ dev_err(dev, "Can't enable aclk: %d\n", ret);
+ return ret;
+ }
+ }
+
+ ret = clk_get_by_name(dev, "bus", &common->bclk);
+ if (!ret) {
+ ret = clk_enable(&common->bclk);
+ if (ret) {
+ dev_err(dev, "Can't enable bclk: %d\n", ret);
+ goto err_aclk_disable;
+ }
+ }
+
+ ret = stm32h7_adc_clk_sel(dev, common);
+ if (ret)
+ goto err_bclk_disable;
+
+ return ret;
+
+err_bclk_disable:
+ if (clk_valid(&common->bclk))
+ clk_disable(&common->bclk);
+
+err_aclk_disable:
+ if (clk_valid(&common->aclk))
+ clk_disable(&common->aclk);
+
+ return ret;
+}
+
+static const struct udevice_id stm32_adc_core_ids[] = {
+ { .compatible = "st,stm32h7-adc-core" },
+ { .compatible = "st,stm32mp1-adc-core" },
+ {}
+};
+
+U_BOOT_DRIVER(stm32_adc_core) = {
+ .name = "stm32-adc-core",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = stm32_adc_core_ids,
+ .probe = stm32_adc_core_probe,
+ .priv_auto_alloc_size = sizeof(struct stm32_adc_common),
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
+ *
+ * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.h.
+ */
+
+#ifndef __STM32_ADC_H
+#define __STM32_ADC_H
+
+/*
+ * STM32 - ADC global register map
+ * ________________________________________________________
+ * | Offset | Register |
+ * --------------------------------------------------------
+ * | 0x000 | Master ADC1 |
+ * --------------------------------------------------------
+ * | 0x100 | Slave ADC2 |
+ * --------------------------------------------------------
+ * | 0x200 | Slave ADC3 |
+ * --------------------------------------------------------
+ * | 0x300 | Master & Slave common regs |
+ * --------------------------------------------------------
+ */
+#define STM32_ADC_MAX_ADCS 3
+#define STM32_ADCX_COMN_OFFSET 0x300
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+
+/**
+ * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
+ * @base: control registers base cpu addr
+ * @rate: clock rate used for analog circuitry
+ * @aclk: clock for the analog circuitry
+ * @bclk: bus clock common for all ADCs
+ * @vref: regulator reference
+ * @vref_uv: reference supply voltage (uV)
+ */
+struct stm32_adc_common {
+ void __iomem *base;
+ unsigned long rate;
+ struct clk aclk;
+ struct clk bclk;
+ struct udevice *vref;
+ int vref_uv;
+};
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
+ *
+ * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc.c.
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include "stm32-adc-core.h"
+
+/* STM32H7 - Registers for each ADC instance */
+#define STM32H7_ADC_ISR 0x00
+#define STM32H7_ADC_CR 0x08
+#define STM32H7_ADC_CFGR 0x0C
+#define STM32H7_ADC_SMPR1 0x14
+#define STM32H7_ADC_SMPR2 0x18
+#define STM32H7_ADC_PCSEL 0x1C
+#define STM32H7_ADC_SQR1 0x30
+#define STM32H7_ADC_DR 0x40
+#define STM32H7_ADC_DIFSEL 0xC0
+
+/* STM32H7_ADC_ISR - bit fields */
+#define STM32MP1_VREGREADY BIT(12)
+#define STM32H7_EOC BIT(2)
+#define STM32H7_ADRDY BIT(0)
+
+/* STM32H7_ADC_CR - bit fields */
+#define STM32H7_DEEPPWD BIT(29)
+#define STM32H7_ADVREGEN BIT(28)
+#define STM32H7_BOOST BIT(8)
+#define STM32H7_ADSTART BIT(2)
+#define STM32H7_ADDIS BIT(1)
+#define STM32H7_ADEN BIT(0)
+
+/* STM32H7_ADC_CFGR bit fields */
+#define STM32H7_EXTEN GENMASK(11, 10)
+#define STM32H7_DMNGT GENMASK(1, 0)
+
+/* STM32H7_ADC_SQR1 - bit fields */
+#define STM32H7_SQ1_SHIFT 6
+
+/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
+#define STM32H7_BOOST_CLKRATE 20000000UL
+
+#define STM32_ADC_CH_MAX 20 /* max number of channels */
+#define STM32_ADC_TIMEOUT_US 100000
+
+struct stm32_adc_cfg {
+ unsigned int max_channels;
+ unsigned int num_bits;
+ bool has_vregready;
+};
+
+struct stm32_adc {
+ void __iomem *regs;
+ int active_channel;
+ const struct stm32_adc_cfg *cfg;
+};
+
+static int stm32_adc_stop(struct udevice *dev)
+{
+ struct stm32_adc *adc = dev_get_priv(dev);
+
+ setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADDIS);
+ clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
+ /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
+ setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
+ adc->active_channel = -1;
+
+ return 0;
+}
+
+static int stm32_adc_start_channel(struct udevice *dev, int channel)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
+ struct stm32_adc *adc = dev_get_priv(dev);
+ int ret;
+ u32 val;
+
+ /* Exit deep power down, then enable ADC voltage regulator */
+ clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
+ setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADVREGEN);
+ if (common->rate > STM32H7_BOOST_CLKRATE)
+ setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
+
+ /* Wait for startup time */
+ if (!adc->cfg->has_vregready) {
+ udelay(20);
+ } else {
+ ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
+ val & STM32MP1_VREGREADY,
+ STM32_ADC_TIMEOUT_US);
+ if (ret < 0) {
+ stm32_adc_stop(dev);
+ dev_err(dev, "Failed to enable vreg: %d\n", ret);
+ return ret;
+ }
+ }
+
+ /* Only use single ended channels */
+ writel(0, adc->regs + STM32H7_ADC_DIFSEL);
+
+ /* Enable ADC, Poll for ADRDY to be set (after adc startup time) */
+ setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADEN);
+ ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
+ val & STM32H7_ADRDY, STM32_ADC_TIMEOUT_US);
+ if (ret < 0) {
+ stm32_adc_stop(dev);
+ dev_err(dev, "Failed to enable ADC: %d\n", ret);
+ return ret;
+ }
+
+ /* Preselect channels */
+ writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL);
+
+ /* Set sampling time to max value by default */
+ writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR1);
+ writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR2);
+
+ /* Program regular sequence: chan in SQ1 & len = 0 for one channel */
+ writel(channel << STM32H7_SQ1_SHIFT, adc->regs + STM32H7_ADC_SQR1);
+
+ /* Trigger detection disabled (conversion can be launched in SW) */
+ clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN |
+ STM32H7_DMNGT);
+ adc->active_channel = channel;
+
+ return 0;
+}
+
+static int stm32_adc_channel_data(struct udevice *dev, int channel,
+ unsigned int *data)
+{
+ struct stm32_adc *adc = dev_get_priv(dev);
+ int ret;
+ u32 val;
+
+ if (channel != adc->active_channel) {
+ dev_err(dev, "Requested channel is not active!\n");
+ return -EINVAL;
+ }
+
+ setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADSTART);
+ ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
+ val & STM32H7_EOC, STM32_ADC_TIMEOUT_US);
+ if (ret < 0) {
+ dev_err(dev, "conversion timed out: %d\n", ret);
+ return ret;
+ }
+
+ *data = readl(adc->regs + STM32H7_ADC_DR);
+
+ return 0;
+}
+
+static int stm32_adc_chan_of_init(struct udevice *dev)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct stm32_adc *adc = dev_get_priv(dev);
+ u32 chans[STM32_ADC_CH_MAX];
+ int i, num_channels, ret;
+
+ /* Retrieve single ended channels listed in device tree */
+ num_channels = dev_read_size(dev, "st,adc-channels");
+ if (num_channels < 0) {
+ dev_err(dev, "can't get st,adc-channels: %d\n", num_channels);
+ return num_channels;
+ }
+ num_channels /= sizeof(u32);
+
+ if (num_channels > adc->cfg->max_channels) {
+ dev_err(dev, "too many st,adc-channels: %d\n", num_channels);
+ return -EINVAL;
+ }
+
+ ret = dev_read_u32_array(dev, "st,adc-channels", chans, num_channels);
+ if (ret < 0) {
+ dev_err(dev, "can't read st,adc-channels: %d\n", ret);
+ return ret;
+ }
+
+ for (i = 0; i < num_channels; i++) {
+ if (chans[i] >= adc->cfg->max_channels) {
+ dev_err(dev, "bad channel %u\n", chans[i]);
+ return -EINVAL;
+ }
+ uc_pdata->channel_mask |= 1 << chans[i];
+ }
+
+ uc_pdata->data_mask = (1 << adc->cfg->num_bits) - 1;
+ uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
+ uc_pdata->data_timeout_us = 100000;
+
+ return 0;
+}
+
+static int stm32_adc_probe(struct udevice *dev)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
+ struct stm32_adc *adc = dev_get_priv(dev);
+ int offset;
+
+ offset = dev_read_u32_default(dev, "reg", -ENODATA);
+ if (offset < 0) {
+ dev_err(dev, "Can't read reg property\n");
+ return offset;
+ }
+ adc->regs = common->base + offset;
+ adc->cfg = (const struct stm32_adc_cfg *)dev_get_driver_data(dev);
+
+ /* VDD supplied by common vref pin */
+ uc_pdata->vdd_supply = common->vref;
+ uc_pdata->vdd_microvolts = common->vref_uv;
+ uc_pdata->vss_microvolts = 0;
+
+ return stm32_adc_chan_of_init(dev);
+}
+
+static const struct adc_ops stm32_adc_ops = {
+ .start_channel = stm32_adc_start_channel,
+ .channel_data = stm32_adc_channel_data,
+ .stop = stm32_adc_stop,
+};
+
+static const struct stm32_adc_cfg stm32h7_adc_cfg = {
+ .num_bits = 16,
+ .max_channels = STM32_ADC_CH_MAX,
+};
+
+static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
+ .num_bits = 16,
+ .max_channels = STM32_ADC_CH_MAX,
+ .has_vregready = true,
+};
+
+static const struct udevice_id stm32_adc_ids[] = {
+ { .compatible = "st,stm32h7-adc",
+ .data = (ulong)&stm32h7_adc_cfg },
+ { .compatible = "st,stm32mp1-adc",
+ .data = (ulong)&stm32mp1_adc_cfg },
+ {}
+};
+
+U_BOOT_DRIVER(stm32_adc) = {
+ .name = "stm32-adc",
+ .id = UCLASS_ADC,
+ .of_match = stm32_adc_ids,
+ .probe = stm32_adc_probe,
+ .ops = &stm32_adc_ops,
+ .priv_auto_alloc_size = sizeof(struct stm32_adc),
+};
#include <dm.h>
#include <ahci.h>
#include <scsi.h>
-#include <asm/arch/hardware.h>
-
#include <asm/io.h>
/* Vendor Specific Register Offsets */
#define AHCI_VEND_PP3C 0xB0
#define AHCI_VEND_PP4C 0xB4
#define AHCI_VEND_PP5C 0xB8
+#define AHCI_VEND_AXICC 0xBc
#define AHCI_VEND_PAXIC 0xC0
#define AHCI_VEND_PTC 0xC8
#define DRV_NAME "ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2 1
+/* flag bit definition */
+#define FLAG_COHERENT 1
+
+/* register config value */
+#define CEVA_PHY1_CFG 0xa003fffe
+#define CEVA_PHY2_CFG 0x28184d1f
+#define CEVA_PHY3_CFG 0x0e081509
+#define CEVA_TRANS_CFG 0x08000029
+#define CEVA_AXICC_CFG 0x3fffffff
+
+/* ecc addr-val pair */
+#define ECC_DIS_ADDR_CH2 0x80000000
+#define ECC_DIS_VAL_CH2 0x20140520
+
+enum ceva_soc {
+ CEVA_1V84,
+ CEVA_LS1012A,
+};
+
struct ceva_sata_priv {
ulong base;
+ enum ceva_soc soc;
+ ulong flag;
};
-static int ceva_init_sata(ulong mmio)
+static int ceva_init_sata(struct ceva_sata_priv *priv)
{
+ ulong base = priv->base;
ulong tmp;
- int i;
-
- /*
- * AXI Data bus width to 64
- * Set Mem Addr Read, Write ID for data transfers
- * Transfer limit to 72 DWord
- */
- tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
- writel(tmp, mmio + AHCI_VEND_PAXIC);
-
- /* Set AHCI Enable */
- tmp = readl(mmio + HOST_CTL);
- tmp |= HOST_AHCI_EN;
- writel(tmp, mmio + HOST_CTL);
-
- for (i = 0; i < NR_PORTS; i++) {
- /* TPSS TPRS scalars, CISE and Port Addr */
- tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
- writel(tmp, mmio + AHCI_VEND_PCFG);
-
- /* Port Phy Cfg register enables */
- tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
- writel(tmp, mmio + AHCI_VEND_PPCFG);
- /* Rx Watermark setting */
+ switch (priv->soc) {
+ case CEVA_1V84:
+ tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+ writel(tmp, base + AHCI_VEND_PAXIC);
+ tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
+ writel(tmp, base + AHCI_VEND_PCFG);
+ tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
+ writel(tmp, base + AHCI_VEND_PPCFG);
tmp = PTC_RX_WM_VAL | PTC_RSVD;
- writel(tmp, mmio + AHCI_VEND_PTC);
-
- /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
- tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
- writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
+ writel(tmp, base + AHCI_VEND_PTC);
+ break;
+
+ case CEVA_LS1012A:
+ writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
+ writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
+ writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
+ if (priv->flag & FLAG_COHERENT)
+ writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
+ break;
}
+
return 0;
}
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
- ceva_init_sata(priv->base);
+ ceva_init_sata(priv);
return ahci_probe_scsi(dev, priv->base);
}
static const struct udevice_id sata_ceva_ids[] = {
- { .compatible = "ceva,ahci-1v84" },
+ { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
+ { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
{ }
};
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ if (dev_read_bool(dev, "dma-coherent"))
+ priv->flag |= FLAG_COHERENT;
+
+ priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
+ priv->soc = dev_get_driver_data(dev);
+
return 0;
}
__weak void bootcount_store(ulong a)
{
void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR;
+ uintptr_t flush_start = rounddown(CONFIG_SYS_BOOTCOUNT_ADDR,
+ CONFIG_SYS_CACHELINE_SIZE);
+ uintptr_t flush_end;
#if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD)
raw_bootcount_store(reg, (BOOTCOUNT_MAGIC & 0xffff0000) | a);
+
+ flush_end = roundup(CONFIG_SYS_BOOTCOUNT_ADDR + 4,
+ CONFIG_SYS_CACHELINE_SIZE);
#else
raw_bootcount_store(reg, a);
raw_bootcount_store(reg + 4, BOOTCOUNT_MAGIC);
+
+ flush_end = roundup(CONFIG_SYS_BOOTCOUNT_ADDR + 8,
+ CONFIG_SYS_CACHELINE_SIZE);
#endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD */
- flush_dcache_range(CONFIG_SYS_BOOTCOUNT_ADDR,
- CONFIG_SYS_BOOTCOUNT_ADDR +
- CONFIG_SYS_CACHELINE_SIZE);
+ flush_dcache_range(flush_start, flush_end);
}
__weak ulong bootcount_load(void)
for (index = 0; index < num_parents; index++) {
ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
index, &parent_clk);
+ /* If -ENOENT, this is a no-op entry */
+ if (ret == -ENOENT)
+ continue;
+
if (ret) {
debug("%s: could not get parent clock %d for %s\n",
__func__, index, dev_read_name(dev));
goto fail;
for (index = 0; index < num_rates; index++) {
+ /* If 0 is passed, this is a no-op */
+ if (!rates[index])
+ continue;
+
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
if (ret) {
return clk_release_bulk(&sbct->bulk);
}
+int sandbox_clk_test_valid(struct udevice *dev)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < SANDBOX_CLK_TEST_ID_COUNT; i++) {
+ if (!clk_valid(&sbct->clks[i]))
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct udevice_id sandbox_clk_test_ids[] = {
{ .compatible = "sandbox,clk-test" },
{ }
#include <dm/util.h>
#include <linux/err.h>
#include <linux/list.h>
+#include <power-domain.h>
DECLARE_GLOBAL_DATA_PTR;
int device_probe(struct udevice *dev)
{
+ struct power_domain pd;
const struct driver *drv;
int size = 0;
int ret;
if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL)
pinctrl_select_state(dev, "default");
+ if (dev->parent && device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) {
+ if (!power_domain_get(dev, &pd))
+ power_domain_on(&pd);
+ }
+
ret = uclass_pre_probe_device(dev);
if (ret)
goto fail;
unsigned int ctrl_num)
{
unsigned int i;
- char buffer[HWCONFIG_BUFFER_SIZE];
- char *buf = NULL;
+ char buf[HWCONFIG_BUFFER_SIZE];
#if defined(CONFIG_SYS_FSL_DDR3) || \
defined(CONFIG_SYS_FSL_DDR2) || \
defined(CONFIG_SYS_FSL_DDR4)
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
- if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
- buf = buffer;
+ if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
+ buf[0] = '\0';
#if defined(CONFIG_SYS_FSL_DDR3) || \
defined(CONFIG_SYS_FSL_DDR2) || \
int use_spd = 0;
#ifdef CONFIG_DDR_SPD
- char buffer[HWCONFIG_BUFFER_SIZE];
- char *buf = NULL;
+ char buf[HWCONFIG_BUFFER_SIZE];
/*
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
- if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
- buf = buffer;
+ if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
+ buf[0] = '\0';
/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
#include <errno.h>
#include <linux/printk.h>
-#define HSDK_CREG_MAX_GPIO 8
-
-#define GPIO_ACTIVATE 0x2
-#define GPIO_DEACTIVATE 0x3
-#define GPIO_PIN_MASK 0x3
-#define BIT_PER_GPIO 2
+#define DRV_NAME "gpio_creg"
struct hsdk_creg_gpio {
- uint32_t *regs;
+ u32 *regs;
+ u8 shift;
+ u8 activate;
+ u8 deactivate;
+ u8 bit_per_gpio;
};
static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
{
struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
- uint32_t reg = readl(hcg->regs);
- uint32_t cmd = val ? GPIO_DEACTIVATE : GPIO_ACTIVATE;
+ u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift;
+ u32 reg = readl(hcg->regs);
- reg &= ~(GPIO_PIN_MASK << (oft * BIT_PER_GPIO));
- reg |= (cmd << (oft * BIT_PER_GPIO));
+ reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift);
+ reg |= ((val ? hcg->deactivate : hcg->activate) << reg_shift);
writel(reg, hcg->regs);
static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
{
- pr_err("hsdk-creg-gpio can't be used as input!\n");
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ pr_err("%s can't be used as input!\n", uc_priv->bank_name);
return -ENOTSUPP;
}
static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
{
struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
- uint32_t val = readl(hcg->regs);
+ u32 val = readl(hcg->regs);
- val = (val >> (oft * BIT_PER_GPIO)) & GPIO_PIN_MASK;
- return (val == GPIO_DEACTIVATE) ? 1 : 0;
+ val >>= oft * hcg->bit_per_gpio + hcg->shift;
+ val &= GENMASK(hcg->bit_per_gpio - 1, 0);
+ return (val == hcg->deactivate) ? 1 : 0;
}
static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+ u32 shift, bit_per_gpio, activate, deactivate, gpio_count;
+ const u8 *defaults;
- hcg->regs = (uint32_t *)devfdt_get_addr_ptr(dev);
-
- uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
- if (uc_priv->gpio_count > HSDK_CREG_MAX_GPIO)
- uc_priv->gpio_count = HSDK_CREG_MAX_GPIO;
+ hcg->regs = (u32 *)devfdt_get_addr_ptr(dev);
+ gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
+ shift = dev_read_u32_default(dev, "gpio-first-shift", 0);
+ bit_per_gpio = dev_read_u32_default(dev, "gpio-bit-per-line", 1);
+ activate = dev_read_u32_default(dev, "gpio-activate-val", 1);
+ deactivate = dev_read_u32_default(dev, "gpio-deactivate-val", 0);
+ defaults = dev_read_u8_array_ptr(dev, "gpio-default-val", gpio_count);
uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
if (!uc_priv->bank_name)
uc_priv->bank_name = dev_read_name(dev);
+ if (!bit_per_gpio) {
+ pr_err("%s: 'gpio-bit-per-line' can't be 0\n",
+ uc_priv->bank_name);
+
+ return -EINVAL;
+ }
+
+ if (!gpio_count) {
+ pr_err("%s: 'gpio-count' can't be 0\n",
+ uc_priv->bank_name);
+
+ return -EINVAL;
+ }
+
+ if ((gpio_count * bit_per_gpio + shift) > 32) {
+ pr_err("%s: u32 io register overflow: try to use %u bits\n",
+ uc_priv->bank_name, gpio_count * bit_per_gpio + shift);
+
+ return -EINVAL;
+ }
+
+ if (GENMASK(31, bit_per_gpio) & activate) {
+ pr_err("%s: 'gpio-activate-val' can't be more than %lu\n",
+ uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));
+
+ return -EINVAL;
+ }
+
+ if (GENMASK(31, bit_per_gpio) & deactivate) {
+ pr_err("%s: 'gpio-deactivate-val' can't be more than %lu\n",
+ uc_priv->bank_name, GENMASK(bit_per_gpio - 1, 0));
+
+ return -EINVAL;
+ }
+
+ if (activate == deactivate) {
+ pr_err("%s: 'gpio-deactivate-val' and 'gpio-activate-val' can't be equal\n",
+ uc_priv->bank_name);
+
+ return -EINVAL;
+ }
+
+ hcg->shift = (u8)shift;
+ hcg->bit_per_gpio = (u8)bit_per_gpio;
+ hcg->activate = (u8)activate;
+ hcg->deactivate = (u8)deactivate;
+ uc_priv->gpio_count = gpio_count;
+
+ /* Setup default GPIO value if we have "gpio-default-val" array */
+ if (defaults)
+ for (u8 i = 0; i < gpio_count; i++)
+ hsdk_creg_gpio_set_value(dev, i, defaults[i]);
+
pr_debug("%s GPIO [0x%p] controller with %d gpios probed\n",
uc_priv->bank_name, hcg->regs, uc_priv->gpio_count);
}
static const struct udevice_id hsdk_creg_gpio_ids[] = {
- { .compatible = "snps,hsdk-creg-gpio" },
+ { .compatible = "snps,creg-gpio" },
{ }
};
U_BOOT_DRIVER(gpio_hsdk_creg) = {
- .name = "gpio_hsdk_creg",
+ .name = DRV_NAME,
.id = UCLASS_GPIO,
.ops = &hsdk_creg_gpio_ops,
.probe = hsdk_creg_gpio_probe,
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm.h>
+#include <dt-bindings/gpio/gpio.h>
-static LIST_HEAD(gpio_list);
-
-enum gpio_direction {
- GPIO_DIRECTION_OUT = 0,
- GPIO_DIRECTION_IN = 1,
-};
+#define XILINX_GPIO_MAX_BANK 2
/* Gpio simple map */
struct gpio_regs {
u32 gpiodir;
};
-#if !defined(CONFIG_DM_GPIO)
-
-#define GPIO_NAME_SIZE 10
-
-struct gpio_names {
- char name[GPIO_NAME_SIZE];
-};
-
-/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
-struct xilinx_gpio_priv {
- struct gpio_regs *regs;
- u32 gpio_min;
- u32 gpio_max;
- u32 gpiodata_store;
- char name[GPIO_NAME_SIZE];
- struct list_head list;
- struct gpio_names *gpio_name;
-};
-
-/* Store number of allocated gpio pins */
-static u32 xilinx_gpio_max;
-
-/* Get associated gpio controller */
-static struct xilinx_gpio_priv *gpio_get_controller(unsigned gpio)
-{
- struct list_head *entry;
- struct xilinx_gpio_priv *priv = NULL;
-
- list_for_each(entry, &gpio_list) {
- priv = list_entry(entry, struct xilinx_gpio_priv, list);
- if (gpio >= priv->gpio_min && gpio <= priv->gpio_max) {
- debug("%s: reg: %x, min-max: %d-%d\n", __func__,
- (u32)priv->regs, priv->gpio_min, priv->gpio_max);
- return priv;
- }
- }
- puts("!!!Can't get gpio controller!!!\n");
- return NULL;
-}
-
-/* Get gpio pin name if used/setup */
-static char *get_name(unsigned gpio)
-{
- u32 gpio_priv;
- struct xilinx_gpio_priv *priv;
-
- debug("%s\n", __func__);
-
- priv = gpio_get_controller(gpio);
- if (priv) {
- gpio_priv = gpio - priv->gpio_min;
-
- return *priv->gpio_name[gpio_priv].name ?
- priv->gpio_name[gpio_priv].name : "UNKNOWN";
- }
- return "UNKNOWN";
-}
-
-/* Get output value */
-static int gpio_get_output_value(unsigned gpio)
-{
- u32 val, gpio_priv;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- gpio_priv = gpio - priv->gpio_min;
- val = !!(priv->gpiodata_store & (1 << gpio_priv));
- debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
-
- return val;
- }
- return -1;
-}
-
-/* Get input value */
-static int gpio_get_input_value(unsigned gpio)
-{
- u32 val, gpio_priv;
- struct gpio_regs *regs;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- regs = priv->regs;
- gpio_priv = gpio - priv->gpio_min;
- val = readl(®s->gpiodata);
- val = !!(val & (1 << gpio_priv));
- debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
-
- return val;
- }
- return -1;
-}
-
-/* Set gpio direction */
-static int gpio_set_direction(unsigned gpio, enum gpio_direction direction)
-{
- u32 val, gpio_priv;
- struct gpio_regs *regs;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- regs = priv->regs;
- val = readl(®s->gpiodir);
-
- gpio_priv = gpio - priv->gpio_min;
- if (direction == GPIO_DIRECTION_OUT)
- val &= ~(1 << gpio_priv);
- else
- val |= 1 << gpio_priv;
-
- writel(val, ®s->gpiodir);
- debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
-
- return 0;
- }
-
- return -1;
-}
-
-/* Get gpio direction */
-static int gpio_get_direction(unsigned gpio)
-{
- u32 val, gpio_priv;
- struct gpio_regs *regs;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- regs = priv->regs;
- gpio_priv = gpio - priv->gpio_min;
- val = readl(®s->gpiodir);
- val = !!(val & (1 << gpio_priv));
- debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
-
- return val;
- }
-
- return -1;
-}
-
-/*
- * Get input value
- * for example gpio setup to output only can't get input value
- * which is breaking gpio toggle command
- */
-int gpio_get_value(unsigned gpio)
-{
- u32 val;
-
- if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
- val = gpio_get_output_value(gpio);
- else
- val = gpio_get_input_value(gpio);
-
- return val;
-}
-
-/* Set output value */
-static int gpio_set_output_value(unsigned gpio, int value)
-{
- u32 val, gpio_priv;
- struct gpio_regs *regs;
- struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
- if (priv) {
- regs = priv->regs;
- gpio_priv = gpio - priv->gpio_min;
- val = priv->gpiodata_store;
- if (value)
- val |= 1 << gpio_priv;
- else
- val &= ~(1 << gpio_priv);
-
- writel(val, ®s->gpiodata);
- debug("%s: reg: %x, gpio_no: %d, output_val: %d\n", __func__,
- (u32)priv->regs, gpio_priv, val);
- priv->gpiodata_store = val;
-
- return 0;
- }
-
- return -1;
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
- if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
- return gpio_set_output_value(gpio, value);
-
- return -1;
-}
-
-/* Set GPIO as input */
-int gpio_direction_input(unsigned gpio)
-{
- debug("%s\n", __func__);
- return gpio_set_direction(gpio, GPIO_DIRECTION_IN);
-}
-
-/* Setup GPIO as output and set output value */
-int gpio_direction_output(unsigned gpio, int value)
-{
- int ret = gpio_set_direction(gpio, GPIO_DIRECTION_OUT);
-
- debug("%s\n", __func__);
-
- if (ret < 0)
- return ret;
-
- return gpio_set_output_value(gpio, value);
-}
-
-/* Show gpio status */
-void gpio_info(void)
-{
- unsigned gpio;
-
- struct list_head *entry;
- struct xilinx_gpio_priv *priv = NULL;
-
- list_for_each(entry, &gpio_list) {
- priv = list_entry(entry, struct xilinx_gpio_priv, list);
- printf("\n%s: %s/%x (%d-%d)\n", __func__, priv->name,
- (u32)priv->regs, priv->gpio_min, priv->gpio_max);
-
- for (gpio = priv->gpio_min; gpio <= priv->gpio_max; gpio++) {
- printf("GPIO_%d:\t%s is an ", gpio, get_name(gpio));
- if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
- printf("OUTPUT value = %d\n",
- gpio_get_output_value(gpio));
- else
- printf("INPUT value = %d\n",
- gpio_get_input_value(gpio));
- }
- }
-}
-
-int gpio_request(unsigned gpio, const char *label)
-{
- u32 gpio_priv;
- struct xilinx_gpio_priv *priv;
-
- if (gpio >= xilinx_gpio_max)
- return -EINVAL;
-
- priv = gpio_get_controller(gpio);
- if (priv) {
- gpio_priv = gpio - priv->gpio_min;
-
- if (label != NULL) {
- strncpy(priv->gpio_name[gpio_priv].name, label,
- GPIO_NAME_SIZE);
- priv->gpio_name[gpio_priv].name[GPIO_NAME_SIZE - 1] =
- '\0';
- }
- return 0;
- }
-
- return -1;
-}
-
-int gpio_free(unsigned gpio)
-{
- u32 gpio_priv;
- struct xilinx_gpio_priv *priv;
-
- if (gpio >= xilinx_gpio_max)
- return -EINVAL;
-
- priv = gpio_get_controller(gpio);
- if (priv) {
- gpio_priv = gpio - priv->gpio_min;
- priv->gpio_name[gpio_priv].name[0] = '\0';
-
- /* Do nothing here */
- return 0;
- }
-
- return -1;
-}
-
-int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no)
-{
- struct xilinx_gpio_priv *priv;
-
- priv = calloc(1, sizeof(struct xilinx_gpio_priv));
-
- /* Setup gpio name */
- if (name != NULL) {
- strncpy(priv->name, name, GPIO_NAME_SIZE);
- priv->name[GPIO_NAME_SIZE - 1] = '\0';
- }
- priv->regs = (struct gpio_regs *)baseaddr;
-
- priv->gpio_min = xilinx_gpio_max;
- xilinx_gpio_max = priv->gpio_min + gpio_no;
- priv->gpio_max = xilinx_gpio_max - 1;
-
- priv->gpio_name = calloc(gpio_no, sizeof(struct gpio_names));
-
- INIT_LIST_HEAD(&priv->list);
- list_add_tail(&priv->list, &gpio_list);
-
- printf("%s: Add %s (%d-%d)\n", __func__, name,
- priv->gpio_min, priv->gpio_max);
-
- /* Return the first gpio allocated for this device */
- return priv->gpio_min;
-}
-
-/* Dual channel gpio is one IP with two independent channels */
-int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0, u32 gpio_no1)
-{
- int ret;
-
- ret = gpio_alloc(baseaddr, name, gpio_no0);
- gpio_alloc(baseaddr + 8, strcat((char *)name, "_1"), gpio_no1);
-
- /* Return the first gpio allocated for this device */
- return ret;
-}
-#else
-#include <dt-bindings/gpio/gpio.h>
-
-#define XILINX_GPIO_MAX_BANK 2
-
struct xilinx_gpio_platdata {
struct gpio_regs *regs;
int bank_max[XILINX_GPIO_MAX_BANK];
int bank_input[XILINX_GPIO_MAX_BANK];
int bank_output[XILINX_GPIO_MAX_BANK];
+ u32 dout_default[XILINX_GPIO_MAX_BANK];
+};
+
+struct xilinx_gpio_privdata {
+ u32 output_val[XILINX_GPIO_MAX_BANK];
};
static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
int value)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
if (ret)
return ret;
- debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x\n",
- __func__, (ulong)platdata->regs, value, offset, bank, pin);
+ val = priv->output_val[bank];
- if (value) {
- val = readl(&platdata->regs->gpiodata + bank * 2);
+ debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
+ __func__, (ulong)platdata->regs, value, offset, bank, pin, val);
+
+ if (value)
val = val | (1 << pin);
- writel(val, &platdata->regs->gpiodata + bank * 2);
- } else {
- val = readl(&platdata->regs->gpiodata + bank * 2);
+ else
val = val & ~(1 << pin);
- writel(val, &platdata->regs->gpiodata + bank * 2);
- }
- return val;
+ writel(val, &platdata->regs->gpiodata + bank * 2);
+
+ priv->output_val[bank] = val;
+
+ return 0;
};
static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
int val, ret;
u32 bank, pin;
debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
(ulong)platdata->regs, offset, bank, pin);
- val = readl(&platdata->regs->gpiodata + bank * 2);
+ if (platdata->bank_output[bank]) {
+ debug("%s: Read saved output value\n", __func__);
+ val = priv->output_val[bank];
+ } else {
+ debug("%s: Read input value from reg\n", __func__);
+ val = readl(&platdata->regs->gpiodata + bank * 2);
+ }
+
val = !!(val & (1 << pin));
return val;
int val, ret;
u32 bank, pin;
+ ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
+ if (ret)
+ return ret;
+
/* Check if all pins are inputs */
if (platdata->bank_input[bank])
return GPIOF_INPUT;
if (platdata->bank_output[bank])
return GPIOF_OUTPUT;
- ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
- if (ret)
- return ret;
-
/* FIXME test on dual */
val = readl(&platdata->regs->gpiodir + bank * 2);
val = !(val & (1 << pin));
if (platdata->bank_input[bank])
return -EINVAL;
+ xilinx_gpio_set_value(dev, offset, value);
+
if (!platdata->bank_output[bank]) {
val = readl(&platdata->regs->gpiodir + bank * 2);
val = val & ~(1 << pin);
writel(val, &platdata->regs->gpiodir + bank * 2);
}
- xilinx_gpio_set_value(dev, offset, value);
-
return 0;
}
static int xilinx_gpio_probe(struct udevice *dev)
{
struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+ struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const void *label_ptr;
- uc_priv->bank_name = dev->name;
+ label_ptr = dev_read_prop(dev, "label", NULL);
+ if (label_ptr) {
+ uc_priv->bank_name = strdup(label_ptr);
+ if (!uc_priv->bank_name)
+ return -ENOMEM;
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
+ priv->output_val[0] = platdata->dout_default[0];
+
+ if (platdata->bank_max[1])
+ priv->output_val[1] = platdata->dout_default[1];
+
return 0;
}
"xlnx,all-inputs", 0);
platdata->bank_output[0] = dev_read_u32_default(dev,
"xlnx,all-outputs", 0);
+ platdata->dout_default[0] = dev_read_u32_default(dev,
+ "xlnx,dout-default",
+ 0);
is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
if (is_dual) {
"xlnx,all-inputs-2", 0);
platdata->bank_output[1] = dev_read_u32_default(dev,
"xlnx,all-outputs-2", 0);
+ platdata->dout_default[1] = dev_read_u32_default(dev,
+ "xlnx,dout-default-2", 0);
}
return 0;
.ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
.probe = xilinx_gpio_probe,
.platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
+ .priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata),
};
-#endif
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
-struct zynq_gpio_privdata {
+struct zynq_gpio_platdata {
phys_addr_t base;
const struct zynq_platform_data *p_data;
};
unsigned int *bank_pin_num,
struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
u32 bank;
- for (bank = 0; bank < priv->p_data->max_bank; bank++) {
- if ((pin_num >= priv->p_data->bank_min[bank]) &&
- (pin_num <= priv->p_data->bank_max[bank])) {
- *bank_num = bank;
- *bank_pin_num = pin_num -
- priv->p_data->bank_min[bank];
- return;
+ for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
+ if (pin_num >= platdata->p_data->bank_min[bank] &&
+ pin_num <= platdata->p_data->bank_max[bank]) {
+ *bank_num = bank;
+ *bank_pin_num = pin_num -
+ platdata->p_data->bank_min[bank];
+ return;
}
}
- if (bank >= priv->p_data->max_bank) {
+ if (bank >= platdata->p_data->max_bank) {
printf("Invalid bank and pin num\n");
*bank_num = 0;
*bank_pin_num = 0;
static int gpio_is_valid(unsigned gpio, struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
- return gpio < priv->p_data->ngpio;
+ return gpio < platdata->p_data->ngpio;
}
static int check_gpio(unsigned gpio, struct udevice *dev)
{
u32 data;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
- data = readl(priv->base +
+ data = readl(platdata->base +
ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
return (data >> bank_pin_num) & 1;
static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
{
unsigned int reg_offset, bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
- writel(value, priv->base + reg_offset);
+ writel(value, platdata->base + reg_offset);
return 0;
}
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
return -1;
/* clear the bit in direction mode reg to set the pin as input */
- reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= ~BIT(bank_pin_num);
- writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
return 0;
}
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
/* configure the output enable reg for the pin */
- reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
/* set the state of the pin */
gpio_set_value(gpio, value);
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(offset, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= BIT(bank_pin_num);
if (reg)
return GPIOF_OUTPUT;
static int zynq_gpio_probe(struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const void *label_ptr;
- uc_priv->bank_name = dev->name;
+ label_ptr = dev_read_prop(dev, "label", NULL);
+ if (label_ptr) {
+ uc_priv->bank_name = strdup(label_ptr);
+ if (!uc_priv->bank_name)
+ return -ENOMEM;
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
- if (priv->p_data)
- uc_priv->gpio_count = priv->p_data->ngpio;
+ if (platdata->p_data)
+ uc_priv->gpio_count = platdata->p_data->ngpio;
return 0;
}
static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
- priv->base = (phys_addr_t)dev_read_addr(dev);
+ platdata->base = (phys_addr_t)dev_read_addr(dev);
- priv->p_data = (struct zynq_platform_data *)dev_get_driver_data(dev);
+ platdata->p_data =
+ (struct zynq_platform_data *)dev_get_driver_data(dev);
return 0;
}
.of_match = zynq_gpio_ids,
.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
.probe = zynq_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
+ .platdata_auto_alloc_size = sizeof(struct zynq_gpio_platdata),
};
}
+u32 __weak imx_get_i2cclk(u32 i2c_num)
+{
+ return 0;
+}
+
static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
{
+ struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
struct imx_lpi2c_reg *regs;
u32 val;
u32 preescale = 0, best_pre = 0, clkhi = 0;
int i;
regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
- clock_rate = imx_get_i2cclk(bus->seq);
- if (!clock_rate)
- return -EPERM;
+
+ if (IS_ENABLED(CONFIG_CLK)) {
+ clock_rate = clk_get_rate(&i2c_bus->per_clk);
+ if (clock_rate <= 0) {
+ dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
+ return clock_rate;
+ }
+ } else {
+ clock_rate = imx_get_i2cclk(bus->seq);
+ if (!clock_rate)
+ return -EPERM;
+ }
mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
/* disable master mode */
return bus_i2c_set_bus_speed(bus, speed);
}
+__weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+{
+ return 0;
+}
+
static int imx_lpi2c_probe(struct udevice *bus)
{
struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
return ret;
}
- /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
- ret = enable_i2c_clk(1, bus->seq);
- if (ret < 0)
- return ret;
+ if (IS_ENABLED(CONFIG_CLK)) {
+ ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
+ if (ret) {
+ dev_err(bus, "Failed to get per clk\n");
+ return ret;
+ }
+ ret = clk_enable(&i2c_bus->per_clk);
+ if (ret) {
+ dev_err(bus, "Failed to enable per clk\n");
+ return ret;
+ }
+ } else {
+ /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
+ ret = enable_i2c_clk(1, bus->seq);
+ if (ret < 0)
+ return ret;
+ }
ret = bus_i2c_init(bus, 100000);
if (ret < 0)
enum pca_type {
PCA9544,
PCA9547,
- PCA9548
+ PCA9548,
+ PCA9646
};
struct chip_desc {
.muxtype = pca954x_isswi,
.width = 8,
},
+ [PCA9646] = {
+ .enable = 0x0,
+ .muxtype = pca954x_isswi,
+ .width = 4,
+ },
};
static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
{ .compatible = "nxp,pca9544", .data = PCA9544 },
{ .compatible = "nxp,pca9547", .data = PCA9547 },
{ .compatible = "nxp,pca9548", .data = PCA9548 },
+ { .compatible = "nxp,pca9646", .data = PCA9646 },
{ }
};
.set_ios = host_set_ios,
.init = mmc_host_reset,
};
-#endif
/*
* mmc_host_init - initialize the mmc controller.
* Set initial clock and power for mmc slot.
* Initialize mmc struct and register with mmc framework.
*/
+
int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc)
{
u32 sdi_u32;
writel(sdi_u32, &host->base->mask0);
host->cfg.name = host->name;
-#ifndef CONFIG_DM_MMC
host->cfg.ops = &arm_pl180_mmci_ops;
-#endif
+
/* TODO remove the duplicates */
host->cfg.host_caps = host->caps;
host->cfg.voltages = host->voltages;
*mmc = mmc_create(&host->cfg, host);
if (!*mmc)
return -1;
-
debug("registered mmc interface number is:%d\n",
(*mmc)->block_dev.devnum);
return 0;
}
+#endif
#ifdef CONFIG_DM_MMC
+static void arm_pl180_mmc_init(struct pl180_mmc_host *host)
+{
+ u32 sdi_u32;
+
+ writel(host->pwr_init, &host->base->power);
+ writel(host->clkdiv_init, &host->base->clock);
+ udelay(CLK_CHANGE_DELAY);
+
+ /* Disable mmc interrupts */
+ sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
+ writel(sdi_u32, &host->base->mask0);
+}
+
static int arm_pl180_mmc_probe(struct udevice *dev)
{
struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = &pdata->mmc;
- struct pl180_mmc_host *host = mmc->priv;
+ struct pl180_mmc_host *host = dev->priv;
+ struct mmc_config *cfg = &pdata->cfg;
struct clk clk;
u32 bus_width;
int ret;
ret = clk_enable(&clk);
if (ret) {
+ clk_free(&clk);
dev_err(dev, "failed to enable clock\n");
return ret;
}
- strcpy(host->name, "MMC");
host->pwr_init = INIT_PWR;
host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN |
SDI_CLKCR_HWFC_EN;
- host->voltages = VOLTAGE_WINDOW_SD;
- host->caps = 0;
host->clock_in = clk_get_rate(&clk);
- host->clock_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
- host->clock_max = dev_read_u32_default(dev, "max-frequency",
- MMC_CLOCK_MAX);
host->version2 = dev_get_driver_data(dev);
+ cfg->name = dev->name;
+ cfg->voltages = VOLTAGE_WINDOW_SD;
+ cfg->host_caps = 0;
+ cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
+ cfg->f_max = dev_read_u32_default(dev, "max-frequency", MMC_CLOCK_MAX);
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
bus_width = dev_read_u32_default(dev, "bus-width", 1);
switch (bus_width) {
case 8:
- host->caps |= MMC_MODE_8BIT;
+ cfg->host_caps |= MMC_MODE_8BIT;
/* Hosts capable of 8-bit transfers can also do 4 bits */
case 4:
- host->caps |= MMC_MODE_4BIT;
+ cfg->host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
dev_err(dev, "Invalid bus-width value %u\n", bus_width);
}
- ret = arm_pl180_mmci_init(host, &mmc);
- if (ret) {
- dev_err(dev, "arm_pl180_mmci init failed\n");
- return ret;
- }
-
+ arm_pl180_mmc_init(host);
+ mmc->priv = host;
mmc->dev = dev;
- dev->priv = host;
upriv->mmc = mmc;
return 0;
}
+int arm_pl180_mmc_bind(struct udevice *dev)
+{
+ struct arm_pl180_mmc_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
static int dm_host_request(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
static int dm_mmc_getcd(struct udevice *dev)
{
- struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev);
- struct mmc *mmc = &pdata->mmc;
- struct pl180_mmc_host *host = mmc->priv;
+ struct pl180_mmc_host *host = dev->priv;
int value = 1;
- if (dm_gpio_is_valid(&host->cd_gpio)) {
+ if (dm_gpio_is_valid(&host->cd_gpio))
value = dm_gpio_get_value(&host->cd_gpio);
- if (host->cd_inverted)
- return !value;
- }
return value;
}
static int arm_pl180_mmc_ofdata_to_platdata(struct udevice *dev)
{
- struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev);
- struct mmc *mmc = &pdata->mmc;
- struct pl180_mmc_host *host = mmc->priv;
+ struct pl180_mmc_host *host = dev->priv;
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
.ops = &arm_pl180_dm_mmc_ops,
.probe = arm_pl180_mmc_probe,
.ofdata_to_platdata = arm_pl180_mmc_ofdata_to_platdata,
+ .bind = arm_pl180_mmc_bind,
.priv_auto_alloc_size = sizeof(struct pl180_mmc_host),
.platdata_auto_alloc_size = sizeof(struct arm_pl180_mmc_plat),
};
struct mmc_config cfg;
#ifdef CONFIG_DM_MMC
struct gpio_desc cd_gpio;
- bool cd_inverted;
#endif
};
priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
priv->mclkreg = &ccm->sd2_clk_cfg;
break;
+#ifdef SUNXI_MMC3_BASE
case 3:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
priv->mclkreg = &ccm->sd3_clk_cfg;
break;
+#endif
default:
printf("Wrong mmc number %d\n", sdc_no);
return -1;
#ifdef CONFIG_MACH_SUN9I
pll = CCM_MMC_CTRL_PLL_PERIPH0;
pll_hz = clock_get_pll4_periph0();
+#elif defined(CONFIG_MACH_SUN50I_H6)
+ pll = CCM_MMC_CTRL_PLL6X2;
+ pll_hz = clock_get_pll6() * 2;
#else
pll = CCM_MMC_CTRL_PLL6;
pll_hz = clock_get_pll6();
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
-#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
if (sdc_no == 2)
cfg->host_caps = MMC_MODE_8BIT;
#endif
/* config ahb clock */
debug("init mmc %d clock and io\n", sdc_no);
+#if !defined(CONFIG_MACH_SUN50I_H6)
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
#ifdef CONFIG_SUNXI_GEN_SUN6I
/* sun9i has a mmc-common module, also set the gate and reset there */
writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
+#endif
+#else /* CONFIG_MACH_SUN50I_H6 */
+ setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
+ /* unassert reset */
+ setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
#endif
ret = mmc_set_mod_clk(priv, 24000000);
if (ret)
if (!chip->onfi_version ||
!(le16_to_cpu(chip->onfi_params.opt_cmd)
& ONFI_OPT_CMD_SET_GET_FEATURES))
- return -EINVAL;
+ return -ENOTSUPP;
#endif
chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
if (!chip->onfi_version ||
!(le16_to_cpu(chip->onfi_params.opt_cmd)
& ONFI_OPT_CMD_SET_GET_FEATURES))
- return -EINVAL;
+ return -ENOTSUPP;
#endif
chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
ONFI_FEATURE_ADDR_TIMING_MODE,
feature);
chip->nand.select_chip(mtd, -1);
- if (ret)
+ if (ret && ret != -ENOTSUPP)
return ret;
}
}
help
Add support for various GigaDevice SPI flash chips (GD25xxx)
+config SPI_FLASH_ISSI
+ bool "ISSI SPI flash support"
+ help
+ Add support for various ISSI SPI flash chips (ISxxx)
+
config SPI_FLASH_MACRONIX
bool "Macronix SPI flash support"
help
{"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) },
{"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) },
{"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) },
+ {"s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, RD_FULL | WR_QPP) },
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) },
{"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
{"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) },
help
Enable driver model for Ethernet.
- The eth_*() interface will be implemented by the UC_ETH class
- This is currently implemented in net/eth.c
+ The eth_*() interface will be implemented by the UCLASS_ETH class
+ This is currently implemented in net/eth-uclass.c
Look in include/net.h for details.
config DRIVER_TI_CPSW
config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on KIRKWOOD || ORION5X
+ select PHYLIB if DM_ETH
help
This driver supports the network interface units in the
Marvell Orion5x and Kirkwood SoCs
obj-$(CONFIG_RTL8169) += rtl8169.o
obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
+obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o
obj-$(CONFIG_SH_ETHER) += sh_eth.o
obj-$(CONFIG_RENESAS_RAVB) += ravb.o
obj-$(CONFIG_SMC91111) += smc91111.o
#ifdef CONFIG_DM_ETH
if (slave->data->phy_of_handle)
- dev_set_of_offset(phydev->dev, slave->data->phy_of_handle);
+ phydev->node = offset_to_ofnode(slave->data->phy_of_handle);
#endif
priv->phydev = phydev;
*/
#include <common.h>
+#include <dm.h>
#include <net.h>
#include <malloc.h>
#include <miiphy.h>
return 0;
}
-/*
- * smi_reg_read - miiphy_read callback function.
- *
- * Returns 16bit phy register value, or -EFAULT on error
- */
-static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
- int reg_ofs)
+static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr,
+ int devad, int reg_ofs)
{
- u16 data = 0;
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
u32 timeout;
+ u16 data = 0;
/* Phyadr read request */
if (phy_adr == MV_PHY_ADR_REQUEST &&
}
/*
- * smi_reg_write - miiphy_write callback function.
+ * smi_reg_read - miiphy_read callback function.
*
- * Returns 0 if write succeed, -EFAULT on error
+ * Returns 16bit phy register value, or -EFAULT on error
*/
-static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
- int reg_ofs, u16 data)
+static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
+ int reg_ofs)
{
+#ifdef CONFIG_DM_ETH
+ struct mvgbe_device *dmvgbe = bus->priv;
+#else
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+#endif
+
+ return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs);
+}
+
+static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr,
+ int devad, int reg_ofs, u16 data)
+{
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
return 0;
}
+
+/*
+ * smi_reg_write - miiphy_write callback function.
+ *
+ * Returns 0 if write succeed, -EFAULT on error
+ */
+static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
+ int reg_ofs, u16 data)
+{
+#ifdef CONFIG_DM_ETH
+ struct mvgbe_device *dmvgbe = bus->priv;
+#else
+ struct eth_device *dev = eth_get_dev_by_name(bus->name);
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+#endif
+
+ return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data);
+}
#endif
/* Stop and checks all queues */
/*
* port_uc_addr_set - This function Set the port Unicast address.
*/
-static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
+static void port_uc_addr_set(struct mvgbe_device *dmvgbe, u8 *p_addr)
{
+ struct mvgbe_registers *regs = dmvgbe->regs;
u32 mac_h;
u32 mac_l;
dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
}
-static int mvgbe_init(struct eth_device *dev)
+static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
+ const char *name)
{
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
!defined(CONFIG_PHYLIB) && \
+ !defined(CONFIG_DM_ETH) && \
defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
set_dram_access(regs);
port_init_mac_tables(regs);
- port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
+ port_uc_addr_set(dmvgbe, enetaddr);
/* Assign port configuration and command. */
MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
!defined(CONFIG_PHYLIB) && \
+ !defined(CONFIG_DM_ETH) && \
defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
/* Wait up to 5s for the link status */
for (i = 0; i < 5; i++) {
u16 phyadr;
- miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
+ miiphy_read(name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
- if (miiphy_link(dev->name, phyadr))
+ if (miiphy_link(name, phyadr))
return 0;
udelay(1000000);
}
- printf("No link on %s\n", dev->name);
+ printf("No link on %s\n", name);
return -1;
#endif
return 0;
}
-static int mvgbe_halt(struct eth_device *dev)
+#ifndef CONFIG_DM_ETH
+static int mvgbe_init(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+
+ return __mvgbe_init(dmvgbe, dmvgbe->dev.enetaddr, dmvgbe->dev.name);
+}
+#endif
+
+static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
+{
struct mvgbe_registers *regs = dmvgbe->regs;
/* Disable all gigE address decoder */
MVGBE_REG_WR(regs->ice, 0);
MVGBE_REG_WR(regs->pim, 0);
MVGBE_REG_WR(regs->peim, 0);
+}
+
+#ifndef CONFIG_DM_ETH
+static int mvgbe_halt(struct eth_device *dev)
+{
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+
+ __mvgbe_halt(dmvgbe);
return 0;
}
+#endif
+
+#ifdef CONFIG_DM_ETH
+static int mvgbe_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ port_uc_addr_set(dev_get_priv(dev), pdata->enetaddr);
+
+ return 0;
+}
+#else
static int mvgbe_write_hwaddr(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
- struct mvgbe_registers *regs = dmvgbe->regs;
/* Programs net device MAC address after initialization */
- port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
+ port_uc_addr_set(dmvgbe, dmvgbe->dev.enetaddr);
return 0;
}
+#endif
-static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
+static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
+ int datasize)
{
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
void *p = (void *)dataptr;
return 0;
}
-static int mvgbe_recv(struct eth_device *dev)
+#ifndef CONFIG_DM_ETH
+static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+
+ return __mvgbe_send(dmvgbe, dataptr, datasize);
+}
+#endif
+
+static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
+{
struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
u32 rxdesc_curr_addr;
+ unsigned char *data;
+ int rx_bytes = 0;
+
+ *packetp = NULL;
/* wait untill rx packet available or timeout */
do {
" upper layer (net_process_received_packet)\n",
__func__);
- /* let the upper layer handle the packet */
- net_process_received_packet((p_rxdesc_curr->buf_ptr +
- RX_BUF_OFFSET),
- (int)(p_rxdesc_curr->byte_cnt -
- RX_BUF_OFFSET));
+ data = (p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET);
+ rx_bytes = (int)(p_rxdesc_curr->byte_cnt -
+ RX_BUF_OFFSET);
+
+ *packetp = data;
}
/*
* free these descriptors and point next in the ring
rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
+ return rx_bytes;
+}
+
+#ifndef CONFIG_DM_ETH
+static int mvgbe_recv(struct eth_device *dev)
+{
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+ uchar *packet;
+ int ret;
+
+ ret = __mvgbe_recv(dmvgbe, &packet);
+ if (ret < 0)
+ return ret;
+
+ net_process_received_packet(packet, ret);
+
return 0;
}
+#endif
-#if defined(CONFIG_PHYLIB)
+#if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH)
+#if defined(CONFIG_DM_ETH)
+static struct phy_device *__mvgbe_phy_init(struct udevice *dev,
+ struct mii_dev *bus,
+ phy_interface_t phy_interface,
+ int phyid)
+#else
+static struct phy_device *__mvgbe_phy_init(struct eth_device *dev,
+ struct mii_dev *bus,
+ phy_interface_t phy_interface,
+ int phyid)
+#endif
+{
+ struct phy_device *phydev;
+
+ /* Set phy address of the port */
+ miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST,
+ phyid);
+
+ phydev = phy_connect(bus, phyid, dev, phy_interface);
+ if (!phydev) {
+ printf("phy_connect failed\n");
+ return NULL;
+ }
+
+ phy_config(phydev);
+ phy_startup(phydev);
+
+ return phydev;
+}
+#endif /* CONFIG_PHYLIB || CONFIG_DM_ETH */
+
+#if defined(CONFIG_PHYLIB) && !defined(CONFIG_DM_ETH)
int mvgbe_phylib_init(struct eth_device *dev, int phyid)
{
struct mii_dev *bus;
return -ENOMEM;
}
- /* Set phy address of the port */
- smi_reg_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
-
- phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
- if (!phydev) {
- printf("phy_connect failed\n");
+ phydev = __mvgbe_phy_init(dev, bus, PHY_INTERFACE_MODE_RGMII, phyid);
+ if (!phydev)
return -ENODEV;
- }
-
- phy_config(phydev);
- phy_startup(phydev);
return 0;
}
#endif
+static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe)
+{
+ dmvgbe->p_rxdesc = memalign(PKTALIGN,
+ MV_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
+ if (!dmvgbe->p_rxdesc)
+ goto error1;
+
+ dmvgbe->p_rxbuf = memalign(PKTALIGN,
+ RINGSZ * PKTSIZE_ALIGN + 1);
+ if (!dmvgbe->p_rxbuf)
+ goto error2;
+
+ dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
+ if (!dmvgbe->p_aligned_txbuf)
+ goto error3;
+
+ dmvgbe->p_txdesc = memalign(PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
+ if (!dmvgbe->p_txdesc)
+ goto error4;
+
+ return 0;
+
+error4:
+ free(dmvgbe->p_aligned_txbuf);
+error3:
+ free(dmvgbe->p_rxbuf);
+error2:
+ free(dmvgbe->p_rxdesc);
+error1:
+ return -ENOMEM;
+}
+
+#ifndef CONFIG_DM_ETH
int mvgbe_initialize(bd_t *bis)
{
struct mvgbe_device *dmvgbe;
struct eth_device *dev;
int devnum;
+ int ret;
u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
continue;
dmvgbe = malloc(sizeof(struct mvgbe_device));
-
if (!dmvgbe)
- goto error1;
+ return -ENOMEM;
memset(dmvgbe, 0, sizeof(struct mvgbe_device));
-
- dmvgbe->p_rxdesc =
- (struct mvgbe_rxdesc *)memalign(PKTALIGN,
- MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
-
- if (!dmvgbe->p_rxdesc)
- goto error2;
-
- dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
- RINGSZ*PKTSIZE_ALIGN + 1);
-
- if (!dmvgbe->p_rxbuf)
- goto error3;
-
- dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
-
- if (!dmvgbe->p_aligned_txbuf)
- goto error4;
-
- dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
- PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
-
- if (!dmvgbe->p_txdesc) {
- free(dmvgbe->p_aligned_txbuf);
-error4:
- free(dmvgbe->p_rxbuf);
-error3:
- free(dmvgbe->p_rxdesc);
-error2:
- free(dmvgbe);
-error1:
+ ret = mvgbe_alloc_buffers(dmvgbe);
+ if (ret) {
printf("Err.. %s Failed to allocate memory\n",
__func__);
- return -1;
+ free(dmvgbe);
+ return ret;
}
dev = &dmvgbe->dev;
}
return 0;
}
+#endif
+
+#ifdef CONFIG_DM_ETH
+static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe)
+{
+ return dmvgbe->phyaddr > PHY_MAX_ADDR;
+}
+
+static int mvgbe_start(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+ int ret;
+
+ ret = __mvgbe_init(dmvgbe, pdata->enetaddr, dev->name);
+ if (ret)
+ return ret;
+
+ if (!mvgbe_port_is_fixed_link(dmvgbe)) {
+ dmvgbe->phydev = __mvgbe_phy_init(dev, dmvgbe->bus,
+ dmvgbe->phy_interface,
+ dmvgbe->phyaddr);
+ if (!dmvgbe->phydev)
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int mvgbe_send(struct udevice *dev, void *packet, int length)
+{
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+
+ return __mvgbe_send(dmvgbe, packet, length);
+}
+
+static int mvgbe_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+
+ return __mvgbe_recv(dmvgbe, packetp);
+}
+
+static void mvgbe_stop(struct udevice *dev)
+{
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+
+ __mvgbe_halt(dmvgbe);
+}
+
+static int mvgbe_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+ struct mii_dev *bus;
+ int ret;
+
+ ret = mvgbe_alloc_buffers(dmvgbe);
+ if (ret)
+ return ret;
+
+ dmvgbe->regs = (void __iomem *)pdata->iobase;
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = smi_reg_read;
+ bus->write = smi_reg_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+ bus->priv = dmvgbe;
+ dmvgbe->bus = bus;
+
+ ret = mdio_register(bus);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static const struct eth_ops mvgbe_ops = {
+ .start = mvgbe_start,
+ .send = mvgbe_send,
+ .recv = mvgbe_recv,
+ .stop = mvgbe_stop,
+ .write_hwaddr = mvgbe_write_hwaddr,
+};
+
+static int mvgbe_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+ void *blob = (void *)gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ const char *phy_mode;
+ int fl_node;
+ int pnode;
+ unsigned long addr;
+
+ pdata->iobase = devfdt_get_addr(dev);
+ pdata->phy_interface = -1;
+
+ pnode = fdt_node_offset_by_compatible(blob, node,
+ "marvell,kirkwood-eth-port");
+
+ /* Get phy-mode / phy_interface from DT */
+ phy_mode = fdt_getprop(gd->fdt_blob, pnode, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ dmvgbe->phy_interface = pdata->phy_interface;
+
+ /* fetch 'fixed-link' property */
+ fl_node = fdt_subnode_offset(blob, pnode, "fixed-link");
+ if (fl_node != -FDT_ERR_NOTFOUND) {
+ /* set phy_addr to invalid value for fixed link */
+ dmvgbe->phyaddr = PHY_MAX_ADDR + 1;
+ dmvgbe->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
+ dmvgbe->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
+ } else {
+ /* Now read phyaddr from DT */
+ addr = fdtdec_lookup_phandle(blob, pnode, "phy-handle");
+ if (addr > 0)
+ dmvgbe->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mvgbe_ids[] = {
+ { .compatible = "marvell,kirkwood-eth" },
+ { }
+};
+
+U_BOOT_DRIVER(mvgbe) = {
+ .name = "mvgbe",
+ .id = UCLASS_ETH,
+ .of_match = mvgbe_ids,
+ .ofdata_to_platdata = mvgbe_ofdata_to_platdata,
+ .probe = mvgbe_probe,
+ .ops = &mvgbe_ops,
+ .priv_auto_alloc_size = sizeof(struct mvgbe_device),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+#endif /* CONFIG_DM_ETH */
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
+#ifndef CONFIG_DM_ETH
#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
+#endif
#define MVGBE_REG_WR(adr, val) writel(val, &adr)
#define MVGBE_REG_RD(adr) readl(&adr)
#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
/* port device data struct */
struct mvgbe_device {
+#ifndef CONFIG_DM_ETH
struct eth_device dev;
+#endif
struct mvgbe_registers *regs;
struct mvgbe_txdesc *p_txdesc;
struct mvgbe_rxdesc *p_rxdesc;
struct mvgbe_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
+
+#ifdef CONFIG_DM_ETH
+ phy_interface_t phy_interface;
+ unsigned int link;
+ unsigned int duplex;
+ unsigned int speed;
+
+ int init;
+ int phyaddr;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+#endif
};
#endif /* __MVGBE_H__ */
* Copyright 2011, 2013 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
+#include <common.h>
#include <phy.h>
#define AR803x_PHY_DEBUG_ADDR_REG 0x1d
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
-#include <config.h>
#include <common.h>
#include <phy.h>
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
+#include <common.h>
#include <phy.h>
#define MIIM_DM9161_SCR 0x10
*
* Based loosely off of Linux's PHY Lib
*/
-
-#include <config.h>
#include <common.h>
#include <miiphy.h>
#include <phy.h>
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
+#include <common.h>
#include <phy.h>
/* LXT971 Status 2 registers */
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
-#include <config.h>
#include <common.h>
#include <errno.h>
#include <phy.h>
* author Andy Fleming
* (C) 2012 NetModule AG, David Andrey, added KSZ9031
*/
-#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
* (C) Copyright 2017 Adaptrum, Inc.
* Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
*/
-
-#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
+#include <common.h>
#include <phy.h>
/* NatSemi DP83630 */
*
* Based loosely off of Linux's PHY Lib
*/
-
-#include <config.h>
#include <common.h>
#include <console.h>
#include <dm.h>
dev->link = 0;
dev->interface = interface;
+#ifdef CONFIG_DM_ETH
+ dev->node = ofnode_null();
+#endif
+
dev->autoneg = AUTONEG_ENABLE;
dev->addr = addr;
* author Andy Fleming
* Copyright 2016 Karsten Merker <merker@debian.org>
*/
-#include <config.h>
#include <common.h>
#include <linux/bitops.h>
#include <phy.h>
* Some code copied from linux kernel
* Copyright (c) 2006 Herbert Valerio Riedel <hvr@gnu.org>
*/
+#include <common.h>
#include <miiphy.h>
/* This code does not check the partner abilities. */
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
-#include <config.h>
#include <common.h>
#include <phy.h>
#include <linux/compat.h>
#include <malloc.h>
-#include <fdtdec.h>
#include <dm.h>
#include <dt-bindings/net/ti-dp83867.h>
-DECLARE_GLOBAL_DATA_PTR;
/* TI DP83867 */
#define DP83867_DEVADDR 0x1f
#define DP83867_CTRL 0x1f
/* Extended Registers */
+#define DP83867_CFG4 0x0031
#define DP83867_RGMIICTL 0x0032
#define DP83867_RGMIIDCTL 0x0086
#define DP83867_IO_MUX_CFG 0x0170
int tx_id_delay;
int fifo_depth;
int io_impedance;
+ bool rxctrl_strap_quirk;
};
/**
static int dp83867_of_init(struct phy_device *phydev)
{
struct dp83867_private *dp83867 = phydev->priv;
- struct udevice *dev = phydev->dev;
- int node = dev_of_offset(dev);
- const void *fdt = gd->fdt_blob;
+ ofnode node;
- if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
+ node = phy_get_ofnode(phydev);
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ if (ofnode_read_bool(node, "ti,max-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
- else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))
+ else if (ofnode_read_bool(node, "ti,min-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
else
dp83867->io_impedance = -EINVAL;
- dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "ti,rx-internal-delay", -1);
+ if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
+ dp83867->rxctrl_strap_quirk = true;
+ dp83867->rx_id_delay = ofnode_read_u32_default(node,
+ "ti,rx-internal-delay",
+ -1);
- dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "ti,tx-internal-delay", -1);
+ dp83867->tx_id_delay = ofnode_read_u32_default(node,
+ "ti,tx-internal-delay",
+ -1);
- dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "ti,fifo-depth", -1);
+ dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
+ -1);
return 0;
}
phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
val | DP83867_SW_RESTART);
+ /* Mode 1 or 2 workaround */
+ if (dp83867->rxctrl_strap_quirk) {
+ val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
+ DP83867_DEVADDR, phydev->addr);
+ val &= ~BIT(7);
+ phy_write_mmd_indirect(phydev, DP83867_CFG4,
+ DP83867_DEVADDR, phydev->addr, val);
+ }
+
if (phy_interface_is_rgmii(phydev)) {
ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
* Original Author: Andy Fleming
* Add vsc8662 phy support - Priyanka Jain
*/
+#include <common.h>
#include <miiphy.h>
/* Cicada Auxiliary Control/Status Register */
#include <phy.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MII_PHY_STATUS_SPD_MASK 0x0C00
#define MII_PHY_STATUS_FULLDUPLEX 0x1000
#define MII_PHY_STATUS_1000 0x0800
static int xilinxphy_of_init(struct phy_device *phydev)
{
u32 phytype;
+ ofnode node;
debug("%s\n", __func__);
- phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
- "xlnx,phy-type", -1);
+ node = phy_get_ofnode(phydev);
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ phytype = ofnode_read_u32_default(node, "xlnx,phy-type", -1);
if (phytype == XAE_PHY_TYPE_1000BASE_X)
phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 National Instruments
+ * Copyright (c) 2018 Joe Hershberger <joe.hershberger@ni.com>
+ */
+
+#include <common.h>
+#include <asm/eth-raw-os.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+static int eth_raw_bus_post_bind(struct udevice *dev)
+{
+ struct sandbox_eth_raw_if_nameindex *ni, *i;
+ struct udevice *child;
+ struct eth_sandbox_raw_priv *priv;
+ char *ub_ifname;
+ static const char ub_ifname_pfx[] = "host_";
+ u32 skip_localhost = 0;
+
+ ni = sandbox_eth_raw_if_nameindex();
+ if (!ni)
+ return -EINVAL;
+
+ dev_read_u32(dev, "skip-localhost", &skip_localhost);
+ for (i = ni; !(i->if_index == 0 && !i->if_name); i++) {
+ int local = sandbox_eth_raw_os_is_local(i->if_name);
+
+ if (local < 0)
+ continue;
+ if (skip_localhost && local)
+ continue;
+
+ ub_ifname = calloc(IFNAMSIZ + sizeof(ub_ifname_pfx), 1);
+ strcpy(ub_ifname, ub_ifname_pfx);
+ strncat(ub_ifname, i->if_name, IFNAMSIZ);
+ device_bind_driver(dev, "eth_sandbox_raw", ub_ifname, &child);
+
+ device_set_name_alloced(child);
+ device_probe(child);
+ priv = dev_get_priv(child);
+ if (priv) {
+ memcpy(priv->host_ifname, i->if_name, IFNAMSIZ);
+ priv->host_ifindex = i->if_index;
+ priv->local = local;
+ }
+ }
+
+ sandbox_eth_raw_if_freenameindex(ni);
+
+ return 0;
+}
+
+static const struct udevice_id sandbox_eth_raw_bus_ids[] = {
+ { .compatible = "sandbox,eth-raw-bus" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_eth_raw_bus) = {
+ .name = "sb_eth_raw_bus",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = sandbox_eth_raw_bus_ids,
+ .bind = eth_raw_bus_post_bind,
+};
{
struct eth_sandbox_raw_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
- const char *interface;
+ int ret;
debug("eth_sandbox_raw: Start\n");
- interface = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
- "host-raw-interface", NULL);
- if (interface == NULL)
- return -EINVAL;
-
- if (strcmp(interface, "lo") == 0) {
- priv->local = 1;
+ ret = sandbox_eth_raw_os_start(priv, pdata->enetaddr);
+ if (priv->local) {
env_set("ipaddr", "127.0.0.1");
env_set("serverip", "127.0.0.1");
+ net_ip = string_to_ip("127.0.0.1");
+ net_server_ip = net_ip;
}
- return sandbox_eth_raw_os_start(interface, pdata->enetaddr, priv);
+ return ret;
}
static int sb_eth_raw_send(struct udevice *dev, void *packet, int length)
sandbox_eth_raw_os_stop(priv);
}
+static int sb_eth_raw_read_rom_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ net_random_ethaddr(pdata->enetaddr);
+
+ return 0;
+}
+
static const struct eth_ops sb_eth_raw_ops = {
.start = sb_eth_raw_start,
.send = sb_eth_raw_send,
.recv = sb_eth_raw_recv,
.stop = sb_eth_raw_stop,
+ .read_rom_hwaddr = sb_eth_raw_read_rom_hwaddr,
};
static int sb_eth_raw_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_sandbox_raw_priv *priv = dev_get_priv(dev);
+ const char *ifname;
+ u32 local;
+ int ret;
+
+ pdata->iobase = dev_read_addr(dev);
+
+ ifname = dev_read_string(dev, "host-raw-interface");
+ if (ifname) {
+ strncpy(priv->host_ifname, ifname, IFNAMSIZ);
+ printf(": Using %s from DT\n", priv->host_ifname);
+ }
+ if (dev_read_u32(dev, "host-raw-interface-idx",
+ &priv->host_ifindex) < 0) {
+ priv->host_ifindex = 0;
+ } else {
+ ret = sandbox_eth_raw_os_idx_to_name(priv);
+ if (ret < 0)
+ return ret;
+ printf(": Using interface index %d from DT (%s)\n",
+ priv->host_ifindex, priv->host_ifname);
+ }
+
+ local = sandbox_eth_raw_os_is_local(priv->host_ifname);
+ if (local < 0)
+ return local;
+ priv->local = local;
- pdata->iobase = devfdt_get_addr(dev);
return 0;
}
debug("eth_sandbox: Start\n");
- fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(dev),
- "fake-host-hwaddr", priv->fake_host_hwaddr,
- ARP_HLEN);
priv->recv_packet_buffer = net_rx_packets[0];
+
return 0;
}
static int sb_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_sandbox_priv *priv = dev_get_priv(dev);
+ const u8 *mac;
+
+ pdata->iobase = dev_read_addr(dev);
+
+ mac = dev_read_u8_array_ptr(dev, "fake-host-hwaddr", ARP_HLEN);
+ if (!mac) {
+ printf("'fake-host-hwaddr' is missing from the DT\n");
+ return -EINVAL;
+ }
+ memcpy(priv->fake_host_hwaddr, mac, ARP_HLEN);
- pdata->iobase = devfdt_get_addr(dev);
return 0;
}
struct zynq_gem_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
- int phy_of_handle;
+ ofnode phy_of_node;
struct mii_dev *bus;
struct clk clk;
u32 max_speed;
}
priv->phydev->advertising = priv->phydev->supported;
-
- if (priv->phy_of_handle > 0)
- dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
+ priv->phydev->node = priv->phy_of_node;
return phy_config(priv->phydev);
}
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
- int node = dev_of_offset(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
- pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
+ pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->phyaddr = -1;
- priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "phy-handle");
- if (priv->phy_of_handle > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
- priv->phy_of_handle, "reg", -1);
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args)) {
+ debug("phy-handle does not exist %s\n", dev->name);
+ return -ENOENT;
+ }
- phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
+ priv->phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1);
+ priv->phy_of_node = phandle_args.node;
+ phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
}
priv->interface = pdata->phy_interface;
- priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle,
- "max-speed", SPEED_1000);
- priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
- "is-internal-pcspma");
+ priv->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
+ priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
.gpio_vbus = CONFIG_USB3_VBUS_PIN,
.gpio_vbus_det = NULL,
.gpio_id_det = NULL,
-#ifdef CONFIG_MACH_SUN6I
- .rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK),
-#endif
},
};
data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
}
- if (usb_phy->id != 0)
- sun4i_usb_phy_passby(phy, true);
+ sun4i_usb_phy_passby(phy, true);
sun4i_usb_phy0_reroute(data, true);
phy->id = i;
phy->rst_mask = info->rst_mask;
+ if ((data->cfg->type == sun8i_h3_phy) && (phy->id == 3))
+ phy->rst_mask = (BIT(3) | BIT(11));
};
- setbits_le32(&data->ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
-
debug("Allwinner Sun4I USB PHY driver loaded\n");
return 0;
}
#
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_POWER_DOMAIN) += power-domain-uclass.o
+obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
Binding info: doc/device-tree-bindings/pmic/s2mps11.txt
config DM_PMIC_SANDBOX
- bool "Enable Driver Model for emulated Sandbox PMIC "
+ bool "Enable Driver Model for emulated Sandbox PMIC"
depends on DM_PMIC
---help---
Enable the driver for Sandbox PMIC emulation. The emulated PMIC device
#include <asm/arch/at91_rtt.h>
#include <asm/arch/at91_gpbr.h>
-#if defined(CONFIG_CMD_DATE)
-
int rtc_get (struct rtc_time *tmp)
{
at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
while (readl(&rtt->vr) != 0)
;
}
-
-#endif
#include <asm/io.h>
#include <asm/davinci_rtc.h>
-#if defined(CONFIG_CMD_DATE)
int rtc_get(struct rtc_time *tmp)
{
struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
/* run RTC counter */
writel(0x01, &rtc->ctrl);
}
-#endif
#include <command.h>
#include <rtc.h>
-#if defined(CONFIG_CMD_DATE)
-
/* GPP Pins */
#define DATA 0x200
#define SCLK 0x400
return 0;
}
-
-#endif
#include <rtc.h>
#include <spi.h>
-#if defined(CONFIG_CMD_DATE)
-
#define RTC_SECONDS 0x00
#define RTC_MINUTES 0x01
#define RTC_HOURS 0x02
}
#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */
-
-#endif
#ifndef CONFIG_DM_RTC
-#if defined(CONFIG_CMD_DATE)
-
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-#endif /* CONFIG_CMD_DATE*/
-
#endif /* !CONFIG_DM_RTC */
#ifdef CONFIG_DM_RTC
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
/*
* RTC register addresses
*/
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
#define DEBUG_RTC
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-#endif
#include <rtc.h>
-#if defined(CONFIG_CMD_DATE)
-
static uchar rtc_read(unsigned int addr );
static void rtc_write(unsigned int addr, uchar val);
#endif
*(volatile unsigned char*)(addr) = val;
}
-
-#endif
#include <command.h>
#include <rtc.h>
-#if defined(CONFIG_CMD_DATE)
-
static uchar rtc_read( unsigned int addr );
static void rtc_write( unsigned int addr, uchar val);
#endif
out8( addr, val );
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
/*
* RTC register addresses
*/
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-
-#endif
#include <linux/compat.h>
#include <rtc.h>
-#if defined(CONFIG_CMD_DATE)
-
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
{
di_init();
}
-
-#endif
#endif
*/
-#if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE)
-
/* ------------------------------------------------------------------------- */
/*
these are simple defines for the chip local to here so they aren't too
val = val & 0x3F;/*turn off freq test keep calibration*/
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1);
}
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE)
-
/*
* Convert between century and "century bits" (CB1 and CB0). These routines
* assume years are in the range 1900 - 2299.
}
rtc_dump("end reset");
}
-#endif /* CONFIG_RTC_M41T60 && CONFIG_SYS_I2C_RTC_ADDR && CONFIG_CMD_DATE */
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
#define M41T62_REG_SSEC 0
#define M41T62_REG_SEC 1
#define M41T62_REG_MIN 2
val &= ~M41T80_ALHOUR_HT;
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
}
-
-#endif
#include <rtc.h>
#include <config.h>
-#if defined(CONFIG_CMD_DATE)
-
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
*(unsigned char *)
((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val;
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
#ifndef CONFIG_SYS_I2C_RTC_ADDR
#define CONFIG_SYS_I2C_RTC_ADDR 0x50
#endif
void rtc_reset (void)
{
}
-
-#endif
#define out8(p, v) outb(v, p)
#endif
-#if defined(CONFIG_CMD_DATE)
-
/* Set this to 1 to clear the CMOS RAM */
#define CLEAR_CMOS 0
mc146818_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100));
mc146818_write8(RTC_MONTH, bin2bcd(tmp->tm_mon));
- mc146818_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
+ /* Sunday = 1, Saturday = 7 */
+ mc146818_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday + 1));
mc146818_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday));
mc146818_write8(RTC_HOURS, bin2bcd(tmp->tm_hour));
mc146818_write8(RTC_MINUTES, bin2bcd(tmp->tm_min));
/* Clear any pending interrupts */
mc146818_read8(RTC_CONFIG_C);
}
-#endif /* CONFIG_CMD_DATE */
#ifdef CONFIG_DM_RTC
#include <common.h>
-#if defined(CONFIG_CMD_DATE)
-
#include <command.h>
#include <rtc.h>
#include <asm/immap.h>
rtc->cr |= RTC_CR_SWR;
}
-
-#endif /* CONFIG_MCFRTC && CONFIG_CMD_DATE */
rtc_write(d++, *s++);
}
-#if defined(CONFIG_CMD_DATE)
-
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
wd_value = RTC_WDS | ((multi & 0x1F) << 2) | (res & 0x3);
rtc_write(RTC_WATCHDOG, wd_value);
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
/*
* Reads are always done starting with register 15, which requires some
* jumping-through-hoops to access the data correctly.
if (!setup_done)
rs5c372_enable();
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
printf("Error writing to RTC\n");
}
-
-#endif /* CONFIG_RTC_RX8025 && CONFIG_CMD_DATE */
#include <common.h>
#include <command.h>
-#if (defined(CONFIG_CMD_DATE))
-
#include <asm/arch/s3c24x0_cpu.h>
#include <rtc.h>
writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon);
writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon);
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
#define CCR_SEC 0
#define CCR_MIN 1
#define CCR_HOUR 2
* Nothing to do
*/
}
-
-#endif
*/
#include <common.h>
+#include <console.h>
#include <dm.h>
#include <fdtdec.h>
#include <lcd.h>
os_tty_raw(0, state->term_raw == STATE_TERM_RAW_WITH_SIGS);
priv->start_of_line = 0;
+ if (state->term_raw != STATE_TERM_RAW)
+ disable_ctrlc(1);
+
return 0;
}
used to access the SPI NOR flash chips on platforms embedding
this ST IP core.
+config SUN4I_SPI
+ bool "Allwinner A10 SoCs SPI controller"
+ help
+ SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
+
config TEGRA114_SPI
bool "nVidia Tegra114 SPI driver"
help
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
+obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o
obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
struct mvebu_spi_platdata {
struct kwspi_registers *spireg;
+ bool is_errata_50mhz_ac;
};
struct mvebu_spi_priv {
{
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
struct kwspi_registers *reg = plat->spireg;
- const struct mvebu_spi_dev *drvdata;
u32 data = readl(®->cfg);
data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
writel(data, ®->cfg);
- drvdata = (struct mvebu_spi_dev *)dev_get_driver_data(bus);
- if (drvdata->is_errata_50mhz_ac)
+ if (plat->is_errata_50mhz_ac)
mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
return 0;
static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
{
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+ const struct mvebu_spi_dev *drvdata =
+ (struct mvebu_spi_dev *)dev_get_driver_data(bus);
plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus);
+ plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac;
return 0;
}
*/
};
+static const struct mvebu_spi_dev armada_spi_dev_data = {
+ .is_errata_50mhz_ac = false,
+};
+
static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
.is_errata_50mhz_ac = false,
};
};
static const struct udevice_id mvebu_spi_ids[] = {
+ {
+ .compatible = "marvell,orion-spi",
+ .data = (ulong)&armada_spi_dev_data,
+ },
{
.compatible = "marvell,armada-375-spi",
.data = (ulong)&armada_375_spi_dev_data
--- /dev/null
+/*
+ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
+ * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
+ * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
+ *
+ * (C) Copyright 2017 Olimex Ltd..
+ * Stefan Mavrodiev <stefan@olimex.com>
+ *
+ * Based on linux spi driver. Original copyright follows:
+ * linux/drivers/spi/spi-sun4i.c
+ *
+ * Copyright (C) 2012 - 2014 Allwinner Tech
+ * Pan Nan <pannan@allwinnertech.com>
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <wait_bit.h>
+
+#include <asm/bitops.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#include <asm/arch/clock.h>
+
+#define SUN4I_FIFO_DEPTH 64
+
+#define SUN4I_RXDATA_REG 0x00
+
+#define SUN4I_TXDATA_REG 0x04
+
+#define SUN4I_CTL_REG 0x08
+#define SUN4I_CTL_ENABLE BIT(0)
+#define SUN4I_CTL_MASTER BIT(1)
+#define SUN4I_CTL_CPHA BIT(2)
+#define SUN4I_CTL_CPOL BIT(3)
+#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
+#define SUN4I_CTL_LMTF BIT(6)
+#define SUN4I_CTL_TF_RST BIT(8)
+#define SUN4I_CTL_RF_RST BIT(9)
+#define SUN4I_CTL_XCH_MASK 0x0400
+#define SUN4I_CTL_XCH BIT(10)
+#define SUN4I_CTL_CS_MASK 0x3000
+#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
+#define SUN4I_CTL_DHB BIT(15)
+#define SUN4I_CTL_CS_MANUAL BIT(16)
+#define SUN4I_CTL_CS_LEVEL BIT(17)
+#define SUN4I_CTL_TP BIT(18)
+
+#define SUN4I_INT_CTL_REG 0x0c
+#define SUN4I_INT_CTL_RF_F34 BIT(4)
+#define SUN4I_INT_CTL_TF_E34 BIT(12)
+#define SUN4I_INT_CTL_TC BIT(16)
+
+#define SUN4I_INT_STA_REG 0x10
+
+#define SUN4I_DMA_CTL_REG 0x14
+
+#define SUN4I_WAIT_REG 0x18
+
+#define SUN4I_CLK_CTL_REG 0x1c
+#define SUN4I_CLK_CTL_CDR2_MASK 0xff
+#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
+#define SUN4I_CLK_CTL_CDR1_MASK 0xf
+#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
+#define SUN4I_CLK_CTL_DRS BIT(12)
+
+#define SUN4I_MAX_XFER_SIZE 0xffffff
+
+#define SUN4I_BURST_CNT_REG 0x20
+#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_XMIT_CNT_REG 0x24
+#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_FIFO_STA_REG 0x28
+#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_RF_CNT_BITS 0
+#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_TF_CNT_BITS 16
+
+#define SUN4I_SPI_MAX_RATE 24000000
+#define SUN4I_SPI_MIN_RATE 3000
+#define SUN4I_SPI_DEFAULT_RATE 1000000
+#define SUN4I_SPI_TIMEOUT_US 1000000
+
+/* sun4i spi register set */
+struct sun4i_spi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctl;
+ u32 intctl;
+ u32 st;
+ u32 dmactl;
+ u32 wait;
+ u32 cctl;
+ u32 bc;
+ u32 tc;
+ u32 fifo_sta;
+};
+
+struct sun4i_spi_platdata {
+ u32 base_addr;
+ u32 max_hz;
+};
+
+struct sun4i_spi_priv {
+ struct sun4i_spi_regs *regs;
+ u32 freq;
+ u32 mode;
+
+ const u8 *tx_buf;
+ u8 *rx_buf;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
+{
+ u8 byte;
+
+ while (len--) {
+ byte = readb(&priv->regs->rxdata);
+ *priv->rx_buf++ = byte;
+ }
+}
+
+static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
+{
+ u8 byte;
+
+ while (len--) {
+ byte = priv->tx_buf ? *priv->tx_buf++ : 0;
+ writeb(byte, &priv->regs->txdata);
+ }
+}
+
+static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(bus);
+ u32 reg;
+
+ reg = readl(&priv->regs->ctl);
+
+ reg &= ~SUN4I_CTL_CS_MASK;
+ reg |= SUN4I_CTL_CS(cs);
+
+ if (enable)
+ reg &= ~SUN4I_CTL_CS_LEVEL;
+ else
+ reg |= SUN4I_CTL_CS_LEVEL;
+
+ writel(reg, &priv->regs->ctl);
+}
+
+static int sun4i_spi_parse_pins(struct udevice *dev)
+{
+ const void *fdt = gd->fdt_blob;
+ const char *pin_name;
+ const fdt32_t *list;
+ u32 phandle;
+ int drive, pull = 0, pin, i;
+ int offset;
+ int size;
+
+ list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
+ if (!list) {
+ printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
+ return -EINVAL;
+ }
+
+ while (size) {
+ phandle = fdt32_to_cpu(*list++);
+ size -= sizeof(*list);
+
+ offset = fdt_node_offset_by_phandle(fdt, phandle);
+ if (offset < 0)
+ return offset;
+
+ drive = fdt_getprop_u32_default_node(fdt, offset, 0,
+ "drive-strength", 0);
+ if (drive) {
+ if (drive <= 10)
+ drive = 0;
+ else if (drive <= 20)
+ drive = 1;
+ else if (drive <= 30)
+ drive = 2;
+ else
+ drive = 3;
+ } else {
+ drive = fdt_getprop_u32_default_node(fdt, offset, 0,
+ "allwinner,drive",
+ 0);
+ drive = min(drive, 3);
+ }
+
+ if (fdt_get_property(fdt, offset, "bias-disable", NULL))
+ pull = 0;
+ else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
+ pull = 1;
+ else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
+ pull = 2;
+ else
+ pull = fdt_getprop_u32_default_node(fdt, offset, 0,
+ "allwinner,pull",
+ 0);
+ pull = min(pull, 2);
+
+ for (i = 0; ; i++) {
+ pin_name = fdt_stringlist_get(fdt, offset,
+ "pins", i, NULL);
+ if (!pin_name) {
+ pin_name = fdt_stringlist_get(fdt, offset,
+ "allwinner,pins",
+ i, NULL);
+ if (!pin_name)
+ break;
+ }
+
+ pin = name_to_gpio(pin_name);
+ if (pin < 0)
+ break;
+
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
+ sunxi_gpio_set_drv(pin, drive);
+ sunxi_gpio_set_pull(pin, pull);
+ }
+ }
+ return 0;
+}
+
+static inline void sun4i_spi_enable_clock(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
+
+ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
+ writel((1 << 31), &ccm->spi0_clk_cfg);
+}
+
+static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
+ int node = dev_of_offset(bus);
+
+ plat->base_addr = devfdt_get_addr(bus);
+ plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
+ "spi-max-frequency",
+ SUN4I_SPI_DEFAULT_RATE);
+
+ if (plat->max_hz > SUN4I_SPI_MAX_RATE)
+ plat->max_hz = SUN4I_SPI_MAX_RATE;
+
+ return 0;
+}
+
+static int sun4i_spi_probe(struct udevice *bus)
+{
+ struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
+ struct sun4i_spi_priv *priv = dev_get_priv(bus);
+
+ sun4i_spi_enable_clock();
+ sun4i_spi_parse_pins(bus);
+
+ priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr;
+ priv->freq = plat->max_hz;
+
+ return 0;
+}
+
+static int sun4i_spi_claim_bus(struct udevice *dev)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
+
+ writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP |
+ SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW,
+ &priv->regs->ctl);
+ return 0;
+}
+
+static int sun4i_spi_release_bus(struct udevice *dev)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
+ u32 reg;
+
+ reg = readl(&priv->regs->ctl);
+ reg &= ~SUN4I_CTL_ENABLE;
+ writel(reg, &priv->regs->ctl);
+
+ return 0;
+}
+
+static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct sun4i_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ u32 len = bitlen / 8;
+ u32 reg;
+ u8 nbytes;
+ int ret;
+
+ priv->tx_buf = dout;
+ priv->rx_buf = din;
+
+ if (bitlen % 8) {
+ debug("%s: non byte-aligned SPI transfer.\n", __func__);
+ return -ENAVAIL;
+ }
+
+ if (flags & SPI_XFER_BEGIN)
+ sun4i_spi_set_cs(bus, slave_plat->cs, true);
+
+ reg = readl(&priv->regs->ctl);
+
+ /* Reset FIFOs */
+ writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);
+
+ while (len) {
+ /* Setup the transfer now... */
+ nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));
+
+ /* Setup the counters */
+ writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
+ writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);
+
+ /* Fill the TX FIFO */
+ sun4i_spi_fill_fifo(priv, nbytes);
+
+ /* Start the transfer */
+ reg = readl(&priv->regs->ctl);
+ writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);
+
+ /* Wait transfer to complete */
+ ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
+ false, SUN4I_SPI_TIMEOUT_US, false);
+ if (ret) {
+ printf("ERROR: sun4i_spi: Timeout transferring data\n");
+ sun4i_spi_set_cs(bus, slave_plat->cs, false);
+ return ret;
+ }
+
+ /* Drain the RX FIFO */
+ sun4i_spi_drain_fifo(priv, nbytes);
+
+ len -= nbytes;
+ }
+
+ if (flags & SPI_XFER_END)
+ sun4i_spi_set_cs(bus, slave_plat->cs, false);
+
+ return 0;
+}
+
+static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
+{
+ struct sun4i_spi_platdata *plat = dev_get_platdata(dev);
+ struct sun4i_spi_priv *priv = dev_get_priv(dev);
+ unsigned int div;
+ u32 reg;
+
+ if (speed > plat->max_hz)
+ speed = plat->max_hz;
+
+ if (speed < SUN4I_SPI_MIN_RATE)
+ speed = SUN4I_SPI_MIN_RATE;
+ /*
+ * Setup clock divider.
+ *
+ * We have two choices there. Either we can use the clock
+ * divide rate 1, which is calculated thanks to this formula:
+ * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
+ * Or we can use CDR2, which is calculated with the formula:
+ * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
+ * Whether we use the former or the latter is set through the
+ * DRS bit.
+ *
+ * First try CDR2, and if we can't reach the expected
+ * frequency, fall back to CDR1.
+ */
+
+ div = SUN4I_SPI_MAX_RATE / (2 * speed);
+ reg = readl(&priv->regs->cctl);
+
+ if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
+ if (div > 0)
+ div--;
+
+ reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
+ } else {
+ div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
+ reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR1(div);
+ }
+
+ priv->freq = speed;
+ writel(reg, &priv->regs->cctl);
+
+ return 0;
+}
+
+static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(dev);
+ u32 reg;
+
+ reg = readl(&priv->regs->ctl);
+ reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA);
+
+ if (mode & SPI_CPOL)
+ reg |= SUN4I_CTL_CPOL;
+
+ if (mode & SPI_CPHA)
+ reg |= SUN4I_CTL_CPHA;
+
+ priv->mode = mode;
+ writel(reg, &priv->regs->ctl);
+
+ return 0;
+}
+
+static const struct dm_spi_ops sun4i_spi_ops = {
+ .claim_bus = sun4i_spi_claim_bus,
+ .release_bus = sun4i_spi_release_bus,
+ .xfer = sun4i_spi_xfer,
+ .set_speed = sun4i_spi_set_speed,
+ .set_mode = sun4i_spi_set_mode,
+};
+
+static const struct udevice_id sun4i_spi_ids[] = {
+ { .compatible = "allwinner,sun4i-a10-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(sun4i_spi) = {
+ .name = "sun4i_spi",
+ .id = UCLASS_SPI,
+ .of_match = sun4i_spi_ids,
+ .ops = &sun4i_spi_ops,
+ .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv),
+ .probe = sun4i_spi_probe,
+};
menu "TPM support"
-comment "Please select only one TPM revision"
- depends on TPM_V1 && TPM_V2
-
config TPM_V1
bool "TPMv1.x support"
depends on TPM
Major TPM versions are not compatible at all, choose either
one or the other. This option enables TPMv1.x drivers/commands.
-if TPM_V1 && !TPM_V2
+if TPM_V1
config TPM_TIS_SANDBOX
bool "Enable sandbox TPM driver"
depends on TPM_V1 && SANDBOX
+ default y
help
This driver emulates a TPMv1.x, providing access to base functions
such as reading and writing TPM private data. This is enough to
config TPM_TIS_LPC
bool "Enable support for Infineon SLB9635/45 TPMs on LPC"
depends on TPM_V1 && X86
- select TPM_DRIVER_SELECTED
help
This driver supports Infineon TPM devices connected on the LPC bus.
The usual tpm operations and the 'tpm' command can be used to talk
config TPM_V2
bool "TPMv2.x support"
depends on TPM
+ default y
help
Major TPM versions are not compatible at all, choose either
one or the other. This option enables TPMv2.x drivers/commands.
-if TPM_V2 && !TPM_V1
+if TPM_V2
config TPM2_TIS_SANDBOX
bool "Enable sandbox TPMv2.x driver"
depends on TPM_V2 && SANDBOX
- select TPM_DRIVER_SELECTED
+ default y
help
This driver emulates a TPMv2.x, providing access to base functions
such as basic configuration, PCR extension and PCR read. Extended
config TPM2_TIS_SPI
bool "Enable support for TPMv2.x SPI chips"
depends on TPM_V2 && DM_SPI
- select TPM_DRIVER_SELECTED
help
This driver supports TPMv2.x devices connected on the SPI bus.
The usual TPM operations and the 'tpm' command can be used to talk
#include <common.h>
#include <dm.h>
#include <linux/unaligned/be_byteshift.h>
-#if defined(CONFIG_TPM_V1)
#include <tpm-v1.h>
-#elif defined(CONFIG_TPM_V2)
#include <tpm-v2.h>
-#endif
#include "tpm_internal.h"
int tpm_open(struct udevice *dev)
*recv += sizeof(rc);
/* Add trailing \0 */
- *recv = '\0';
+ *recv = NULL;
return 0;
}
struct sandbox_tpm2 *tpm = dev_get_priv(dev);
struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
+ /* Use the TPM v2 stack */
+ priv->version = TPM_V2;
+
memset(tpm, 0, sizeof(*tpm));
priv->pcr_count = 32;
static int tpm_tis_spi_open(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
if (chip->is_open)
return -EBUSY;
struct tpm_chip *chip = dev_get_priv(dev);
int ret;
+ /* Use the TPM v2 stack */
+ priv->version = TPM_V2;
+
if (IS_ENABLED(CONFIG_DM_GPIO)) {
struct gpio_desc reset_gpio;
config I2C_EDID
bool "Enable EDID library"
- depends on DM_I2C
default n
help
This enables library for accessing EDID data from an LCD panel.
return ops->enable_backlight(dev);
}
+int panel_get_display_timing(struct udevice *dev,
+ struct display_timing *timings)
+{
+ struct panel_ops *ops = panel_get_ops(dev);
+
+ if (!ops->get_display_timing)
+ return -ENOSYS;
+
+ return ops->get_display_timing(dev, timings);
+}
+
UCLASS_DRIVER(panel) = {
.id = UCLASS_PANEL,
.name = "panel",
if (ret) {
debug("DE2 not present\n");
return 0;
+ } else if (!device_active(de2)) {
+ debug("DE2 present but not probed\n");
+ return 0;
}
ret = uclass_find_device_by_name(UCLASS_DISPLAY,
endchoice
choice
- prompt "Location of uncompressed DTBs "
+ prompt "Location of uncompressed DTBs"
depends on (SPL_MULTI_DTB_FIT_GZIP || SPL_MULTI_DTB_FIT_LZO)
default SPL_MULTI_DTB_FIT_DYN_ALLOC if SYS_MALLOC_F
*/
__weak enum env_location env_get_location(enum env_operation op, int prio)
{
- switch (op) {
- case ENVOP_GET_CHAR:
- case ENVOP_INIT:
- case ENVOP_LOAD:
- if (prio >= ARRAY_SIZE(env_locations))
- return ENVL_UNKNOWN;
-
- gd->env_load_location = env_locations[prio];
- return gd->env_load_location;
-
- case ENVOP_SAVE:
- return gd->env_load_location;
- }
+ if (prio >= ARRAY_SIZE(env_locations))
+ return ENVL_UNKNOWN;
+
+ gd->env_load_prio = prio;
- return ENVL_UNKNOWN;
+ return env_locations[prio];
}
return 0;
}
+ /*
+ * In case of invalid environment, we set the 'default' env location
+ * to the highest priority. In this way, next calls to env_save()
+ * will restore the environment at the right place.
+ */
+ env_get_location(ENVOP_LOAD, 0);
+
return -ENODEV;
}
int env_save(void)
{
struct env_driver *drv;
- int prio;
- for (prio = 0; (drv = env_driver_lookup(ENVOP_SAVE, prio)); prio++) {
+ drv = env_driver_lookup(ENVOP_SAVE, gd->env_load_prio);
+ if (drv) {
int ret;
if (!drv->save)
- continue;
+ return -ENODEV;
if (!env_has_inited(drv->location))
- continue;
+ return -ENODEV;
printf("Saving Environment to %s... ", drv->name);
ret = drv->save();
volume_info volinfo;
fsdata datablock;
fsdata *mydata = &datablock;
- int cursect;
+ int cursect, i;
int ret = -1, name_len;
char l_filename[VFAT_MAXLEN_BYTES];
+ char bad[2] = " ";
+ const char illegal[] = "<>:\"/\\|?*";
*actwrite = size;
dir_curclust = 0;
}
dentptr = (dir_entry *) do_fat_read_at_block;
+ /* Strip leading (back-)slashes */
+ while ISDIRDELIM(*filename)
+ ++filename;
+ /* Check that the filename is valid */
+ for (i = 0; i < strlen(illegal); ++i) {
+ *bad = illegal[i];
+ if (strstr(filename, bad)) {
+ printf("FAT: illegal filename (%s)\n", filename);
+ return -1;
+ }
+ }
+
name_len = strlen(filename);
if (name_len >= VFAT_MAXLEN_BYTES)
name_len = VFAT_MAXLEN_BYTES - 1;
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Environment valid? enum env_valid */
unsigned long env_has_init; /* Bitmask of boolean of struct env_location offsets */
- int env_load_location;
+ int env_load_prio; /* Priority of the loaded environment */
unsigned long ram_base; /* Base address of RAM used by U-Boot */
unsigned long ram_top; /* Top address of RAM used by U-Boot */
int soc_clk_dump(void);
+/**
+ * clk_valid() - check if clk is valid
+ *
+ * @clk: the clock to check
+ * @return true if valid, or false
+ */
+static inline bool clk_valid(struct clk *clk)
+{
+ return !!clk->dev;
+}
#endif
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif /* CONFIG_CMD_NET */
-/*
- * Time settings
- */
-#define CONFIG_RTC_MV
-
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
#endif /* _CONFIG_SBX81LIFKW_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Allied Telesis <www.alliedtelesis.co.nz>
+ */
+
+#ifndef _CONFIG_SBX81LIFXCAT_H
+#define _CONFIG_SBX81LIFXCAT_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_BUILD_TARGET "u-boot.kwb"
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_GPIO 1
+
+#define CONFIG_MISC_INIT_R /* call misc_init_r */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
+#define MTDPARTS_MTDOOPS "errlog"
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
+#define CONFIG_ENV_SIZE 0x02000
+#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here - 768K */
+
+/*
+ * U-Boot bootcode configuration
+ */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
+
+/* size in bytes reserved for initial data */
+
+#include <asm/arch/config.h>
+/* There is no PHY directly connected so don't ask it for link status */
+#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi over miiphy interface */
+#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
+#define CONFIG_PHY_BASE_ADR 0x01
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
+
+#endif /* _CONFIG_SBX81LIFXCAT_H */
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#endif
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
#endif
#endif
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
"setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \
"if test $board_name = BBBL; then " \
"setenv fdtfile am335x-boneblue.dtb; fi; " \
+ "if test $board_name = BBEN; then " \
+ "setenv fdtfile am335x-sancloud-bbe.dtb; fi; " \
"if test $board_name = A33515BB; then " \
"setenv fdtfile am335x-evm.dtb; fi; " \
"if test $board_name = A335X_SK; then " \
* Environment settings
*/
#define CONFIG_ENV_SIZE SZ_16K
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "upgrade=if mmc rescan && " \
+ "fatload mmc 0:1 ${loadaddr} u-boot-update.img && " \
+ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
+ "\"Fail to upgrade.\n" \
+ "Do you have u-boot-update.img and u-boot.head on first (FAT) SD card partition?\"" \
+ "; fi\0"
/*
* Environment configuration
"initrd_high=0x10000000\0"
/* SPL */
-/*
- * Select the boot device here
- *
- * Currently supported are:
- * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
- * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
- */
-#define SPL_BOOT_SPI_NOR_FLASH 1
-#define SPL_BOOT_SDIO_MMC_CARD 2
-#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
/* Defines for SPL */
#define CONFIG_SPL_SIZE (140 << 10)
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
/* SPL related SPI defines */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
-#endif
-
-#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC)
/* SPL related MMC defines */
#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif
-/*
- * RTC driver configuration
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif
-
/*
* Enable GPI0 support
*/
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
-/*
- * * RTC driver configuration
- * */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#endif /* _CONFIG_GOFLEXHOME_H */
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x17000
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#define SPL_NO_USB
#define SPL_NO_SATA
#endif
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
+#if defined(CONFIG_SPL_BUILD) && \
+ (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
#define SPL_NO_MMC
#endif
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
+#if defined(CONFIG_SPL_BUILD) && \
+ !defined(CONFIG_SPL_FSL_LS_PPA)
#define SPL_NO_IFC
#endif
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
#define CONFIG_SPL_STACK 0x10020000
#endif /* ifdef CONFIG_SECURE_BOOT */
#endif
+#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
+#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1f000
+#define CONFIG_SPL_STACK 0x10020000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SYS_MONITOR_LEN 0x100000
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#endif
+
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
-#endif
-
#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
#ifdef CONFIG_EMMC_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
#endif
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI \
+ board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
+#define CONFIG_SYS_UBOOT_BASE 0x40100000
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
#endif
#ifndef SPL_NO_IFC
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
- "sf read 0x80200000 0xd00000 0x100000;"\
- " fsl_mc apply dpl 0x80200000 &&" \
+ "sf read 0x80001000 0xd00000 0x100000;"\
+ " fsl_mc lazyapply dpl 0x80001000 &&" \
" sf read $kernel_load $kernel_start" \
" $kernel_size && bootm $kernel_load"
#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80200000 0x6800 0x800;"\
- " fsl_mc apply dpl 0x80200000 &&" \
+#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
+ " fsl_mc lazyapply dpl 0x80001000 &&" \
" mmc read $kernel_load $kernel_start" \
" $kernel_size && bootm $kernel_load"
#else /* NOR BOOT*/
-#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
+#define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#endif
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"env exists mcinitcmd && run mcinitcmd && " \
- "mmc read 0x80200000 0x6800 0x800;" \
- "fsl_mc apply dpl 0x80200000;" \
+ "mmc read 0x80001000 0x6800 0x800;" \
+ "fsl_mc lazyapply dpl 0x80001000;" \
"bootm $load_addr#ls1088ardb\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
#if defined(CONFIG_QSPI_BOOT)
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND \
- "sf read 0x80200000 0xd00000 0x100000;" \
+ "sf read 0x80001000 0xd00000 0x100000;" \
"env exists mcinitcmd && env exists secureboot " \
" && sf read 0x80780000 0x780000 0x100000 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
- "&& fsl_mc apply dpl 0x80200000;" \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run qspi_bootcmd;" \
"env exists secureboot && esbc_halt;"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND \
"env exists mcinitcmd && mmcinfo; " \
- "mmc read 0x80200000 0x6800 0x800; " \
+ "mmc read 0x80001000 0x6800 0x800; " \
"env exists mcinitcmd && env exists secureboot " \
- " && mmc read 0x80780000 0x3800 0x10 " \
+ " && mmc read 0x80780000 0x3C00 0x10 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
- "&& fsl_mc apply dpl 0x80200000;" \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run sd_bootcmd;" \
"env exists secureboot && esbc_halt;"
#endif
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
#ifdef CONFIG_NAND_BOOT
/* SPI */
#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
-#define CONFIG_SPI_FLASH
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#endif
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
#define FSL_QSPI_FLASH_NUM 2
#endif
#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200,230400, 460800, 921600 }
/* auto boot */
#define CONFIG_PREBOOT
*/
#include "mv-common.h"
-/*
- * RTC driver configuration
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#endif /* _CONFIG_MARVELL_PLUG_H */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
* EFI partition
*/
-/*
- * Date Time
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_MV
-#endif /* CONFIG_CMD_DATE */
-
#define CONFIG_KIRKWOOD_GPIO
#endif /* _CONFIG_NAS220_H */
* function per_clocks_enable().
*/
#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_SYS_NS16550_COM3
-#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
#undef CONFIG_SERIAL3
#define CONFIG_SERIAL2
#endif
#include <configs/ti_omap3_common.h>
-#ifdef CONFIG_SPL_BUILD
-/* select serial console configuration for SPL */
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#endif
-
-
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
"x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
- "mtdids="CONFIG_MTDIDS_DEFAULT"\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
+ "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"
/*
* Ethernet Driver configuration
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
#endif
#endif
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
-#define CONFIG_SPI_FLASH_ISSI
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 1
#define CONFIG_USB_EHCI_SUNXI
#endif
-#define CONFIG_SUNXI_USB_PHYS 3
-
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
-#define CONFIG_SUNXI_USB_PHYS 1
-
+#ifndef CONFIG_MACH_SUN50I_H6
#define GICD_BASE 0x1c81000
#define GICC_BASE 0x1c82000
+#else
+#define GICD_BASE 0x3021000
+#define GICC_BASE 0x3022000
+#endif
/*
* Include common sunxi configuration where most the settings are
#define CONFIG_USB_EHCI_SUNXI
#endif
-#define CONFIG_SUNXI_USB_PHYS 2
-
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_USB_EHCI_SUNXI
#endif
-#define CONFIG_SUNXI_USB_PHYS 3
-
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */
#define CONFIG_USB_EHCI_SUNXI
#endif
-#define CONFIG_SUNXI_USB_PHYS 3
-
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */
#define CONFIG_USB_EHCI_SUNXI
#endif
-#ifdef CONFIG_MACH_SUN8I_H3
- #define CONFIG_SUNXI_USB_PHYS 4
-#elif defined CONFIG_MACH_SUN8I_A83T
- #define CONFIG_SUNXI_USB_PHYS 3
-#elif defined CONFIG_MACH_SUN8I_V3S
- #define CONFIG_SUNXI_USB_PHYS 1
-#else
- #define CONFIG_SUNXI_USB_PHYS 2
-#endif
-
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
-#ifdef CONFIG_SUNXI_HIGH_SRAM
/*
* The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
* slightly bigger. Note that it is possible to map the first 32 KiB of the
* A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
* undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
* the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
+ * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register
+ * is known yet.
+ * H6 has SRAM A1 at 0x00020000.
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR 0x0
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
-#endif
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
+/* FIXME: this may be larger on some SoCs */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#endif
-#ifdef CONFIG_SUNXI_HIGH_SRAM
+/*
+ * We cannot use expressions here, because expressions won't be evaluated in
+ * autoconf.mk.
+ */
+#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000
#define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
#ifdef CONFIG_ARM64
#else
#define LOW_LEVEL_SRAM_STACK 0x00018000
#endif /* !CONFIG_ARM64 */
+#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000
+#define CONFIG_SPL_TEXT_BASE 0x20060 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
+/* end of SRAM A2 on H6 for now */
+#define LOW_LEVEL_SRAM_STACK 0x00118000
#else
#define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */
/* Select serial console configuration */
#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
#endif
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#undef CONFIG_SPI_FLASH_WINBOND
-#undef CONFIG_SPI_FLASH_ISSI
/* Setup proper boot sequences for Miami boards */
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
/* SPL related SPI defines */
# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
-#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
/* SPL related MMC defines */
# define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
#undef CONFIG_BOOTP_MAY_FAIL
#undef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS 1
#endif /* __CONFIG_ZYNQMP_MINI_H */
#include <configs/xilinx_zynqmp_mini.h>
#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x800000
#include <configs/xilinx_zynqmp_mini.h>
#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000)
#include <configs/xilinx_zynqmp_mini.h>
#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000)
#define CONFIG_SYS_MALLOC_LEN 0x2000
/* QSPI */
#ifdef CONFIG_ZYNQ_QSPI
# define CONFIG_SF_DEFAULT_SPEED 30000000
-# define CONFIG_SPI_FLASH_ISSI
#endif
/* NOR */
#define CONFIG_SYS_MEMTEST_START 0
#define CONFIG_SYS_MEMTEST_END 0x1000
-#define CONFIG_SYS_MALLOC_LEN 0x1400000
-
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
#define CONFIG_SPL_BSS_START_ADDR 0x20000
#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
-#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_MALLOC_LEN 0x1000
-
#endif /* __CONFIG_ZYNQ_CSE_H */
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_H_
+
+#define CLK_PLL_PERIPH0 3
+
+#define CLK_CPUX 21
+
+#define CLK_APB1 26
+
+#define CLK_DE 29
+#define CLK_BUS_DE 30
+#define CLK_DEINTERLACE 31
+#define CLK_BUS_DEINTERLACE 32
+#define CLK_GPU 33
+#define CLK_BUS_GPU 34
+#define CLK_CE 35
+#define CLK_BUS_CE 36
+#define CLK_VE 37
+#define CLK_BUS_VE 38
+#define CLK_EMCE 39
+#define CLK_BUS_EMCE 40
+#define CLK_VP9 41
+#define CLK_BUS_VP9 42
+#define CLK_BUS_DMA 43
+#define CLK_BUS_MSGBOX 44
+#define CLK_BUS_SPINLOCK 45
+#define CLK_BUS_HSTIMER 46
+#define CLK_AVS 47
+#define CLK_BUS_DBG 48
+#define CLK_BUS_PSI 49
+#define CLK_BUS_PWM 50
+#define CLK_BUS_IOMMU 51
+
+#define CLK_MBUS_DMA 53
+#define CLK_MBUS_VE 54
+#define CLK_MBUS_CE 55
+#define CLK_MBUS_TS 56
+#define CLK_MBUS_NAND 57
+#define CLK_MBUS_CSI 58
+#define CLK_MBUS_DEINTERLACE 59
+
+#define CLK_NAND0 61
+#define CLK_NAND1 62
+#define CLK_BUS_NAND 63
+#define CLK_MMC0 64
+#define CLK_MMC1 65
+#define CLK_MMC2 66
+#define CLK_BUS_MMC0 67
+#define CLK_BUS_MMC1 68
+#define CLK_BUS_MMC2 69
+#define CLK_BUS_UART0 70
+#define CLK_BUS_UART1 71
+#define CLK_BUS_UART2 72
+#define CLK_BUS_UART3 73
+#define CLK_BUS_I2C0 74
+#define CLK_BUS_I2C1 75
+#define CLK_BUS_I2C2 76
+#define CLK_BUS_I2C3 77
+#define CLK_BUS_SCR0 78
+#define CLK_BUS_SCR1 79
+#define CLK_SPI0 80
+#define CLK_SPI1 81
+#define CLK_BUS_SPI0 82
+#define CLK_BUS_SPI1 83
+#define CLK_BUS_EMAC 84
+#define CLK_TS 85
+#define CLK_BUS_TS 86
+#define CLK_IR_TX 87
+#define CLK_BUS_IR_TX 88
+#define CLK_BUS_THS 89
+#define CLK_I2S3 90
+#define CLK_I2S0 91
+#define CLK_I2S1 92
+#define CLK_I2S2 93
+#define CLK_BUS_I2S0 94
+#define CLK_BUS_I2S1 95
+#define CLK_BUS_I2S2 96
+#define CLK_BUS_I2S3 97
+#define CLK_SPDIF 98
+#define CLK_BUS_SPDIF 99
+#define CLK_DMIC 100
+#define CLK_BUS_DMIC 101
+#define CLK_AUDIO_HUB 102
+#define CLK_BUS_AUDIO_HUB 103
+#define CLK_USB_OHCI0 104
+#define CLK_USB_PHY0 105
+#define CLK_USB_PHY1 106
+#define CLK_USB_OHCI3 107
+#define CLK_USB_PHY3 108
+#define CLK_USB_HSIC_12M 109
+#define CLK_USB_HSIC 110
+#define CLK_BUS_OHCI0 111
+#define CLK_BUS_OHCI3 112
+#define CLK_BUS_EHCI0 113
+#define CLK_BUS_XHCI 114
+#define CLK_BUS_EHCI3 115
+#define CLK_BUS_OTG 116
+#define CLK_PCIE_REF_100M 117
+#define CLK_PCIE_REF 118
+#define CLK_PCIE_REF_OUT 119
+#define CLK_PCIE_MAXI 120
+#define CLK_PCIE_AUX 121
+#define CLK_BUS_PCIE 122
+#define CLK_HDMI 123
+#define CLK_HDMI_SLOW 124
+#define CLK_HDMI_CEC 125
+#define CLK_BUS_HDMI 126
+#define CLK_BUS_TCON_TOP 127
+#define CLK_TCON_LCD0 128
+#define CLK_BUS_TCON_LCD0 129
+#define CLK_TCON_TV0 130
+#define CLK_BUS_TCON_TV0 131
+#define CLK_CSI_CCI 132
+#define CLK_CSI_TOP 133
+#define CLK_CSI_MCLK 134
+#define CLK_BUS_CSI 135
+#define CLK_HDCP 136
+#define CLK_BUS_HDCP 137
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+
+#define CLK_AR100 0
+
+#define CLK_R_APB1 2
+
+#define CLK_R_APB1_TIMER 4
+#define CLK_R_APB1_TWD 5
+#define CLK_R_APB1_PWM 6
+#define CLK_R_APB2_UART 7
+#define CLK_R_APB2_I2C 8
+#define CLK_R_APB1_IR 9
+#define CLK_R_APB1_W1 10
+
+#define CLK_IR 11
+#define CLK_W1 12
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
+#define _DT_BINDINGS_RESET_SUN50I_H6_H_
+
+#define RST_MBUS 0
+#define RST_BUS_DE 1
+#define RST_BUS_DEINTERLACE 2
+#define RST_BUS_GPU 3
+#define RST_BUS_CE 4
+#define RST_BUS_VE 5
+#define RST_BUS_EMCE 6
+#define RST_BUS_VP9 7
+#define RST_BUS_DMA 8
+#define RST_BUS_MSGBOX 9
+#define RST_BUS_SPINLOCK 10
+#define RST_BUS_HSTIMER 11
+#define RST_BUS_DBG 12
+#define RST_BUS_PSI 13
+#define RST_BUS_PWM 14
+#define RST_BUS_IOMMU 15
+#define RST_BUS_DRAM 16
+#define RST_BUS_NAND 17
+#define RST_BUS_MMC0 18
+#define RST_BUS_MMC1 19
+#define RST_BUS_MMC2 20
+#define RST_BUS_UART0 21
+#define RST_BUS_UART1 22
+#define RST_BUS_UART2 23
+#define RST_BUS_UART3 24
+#define RST_BUS_I2C0 25
+#define RST_BUS_I2C1 26
+#define RST_BUS_I2C2 27
+#define RST_BUS_I2C3 28
+#define RST_BUS_SCR0 29
+#define RST_BUS_SCR1 30
+#define RST_BUS_SPI0 31
+#define RST_BUS_SPI1 32
+#define RST_BUS_EMAC 33
+#define RST_BUS_TS 34
+#define RST_BUS_IR_TX 35
+#define RST_BUS_THS 36
+#define RST_BUS_I2S0 37
+#define RST_BUS_I2S1 38
+#define RST_BUS_I2S2 39
+#define RST_BUS_I2S3 40
+#define RST_BUS_SPDIF 41
+#define RST_BUS_DMIC 42
+#define RST_BUS_AUDIO_HUB 43
+#define RST_USB_PHY0 44
+#define RST_USB_PHY1 45
+#define RST_USB_PHY3 46
+#define RST_USB_HSIC 47
+#define RST_BUS_OHCI0 48
+#define RST_BUS_OHCI3 49
+#define RST_BUS_EHCI0 50
+#define RST_BUS_XHCI 51
+#define RST_BUS_EHCI3 52
+#define RST_BUS_OTG 53
+#define RST_BUS_PCIE 54
+#define RST_PCIE_POWERUP 55
+#define RST_BUS_HDMI 56
+#define RST_BUS_HDMI_SUB 57
+#define RST_BUS_TCON_TOP 58
+#define RST_BUS_TCON_LCD0 59
+#define RST_BUS_TCON_TV0 60
+#define RST_BUS_CSI 61
+#define RST_BUS_HDCP 62
+
+#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+
+#define RST_R_APB1_TIMER 0
+#define RST_R_APB1_TWD 1
+#define RST_R_APB1_PWM 2
+#define RST_R_APB2_UART 3
+#define RST_R_APB2_I2C 4
+#define RST_R_APB1_IR 5
+#define RST_R_APB1_W1 6
+
+#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */
*/
#ifdef __x86_64__
#define EFIAPI __attribute__((ms_abi))
+#define efi_va_list __builtin_ms_va_list
+#define efi_va_start __builtin_ms_va_start
+#define efi_va_arg __builtin_va_arg
+#define efi_va_end __builtin_ms_va_end
#else
#define EFIAPI asmlinkage
+#define efi_va_list va_list
+#define efi_va_start va_start
+#define efi_va_arg va_arg
+#define efi_va_end va_end
#endif /* __x86_64__ */
struct efi_device_path;
#include <asm/setjmp.h>
#endif
+/* UEFI spec version 2.7 */
+#define EFI_SPECIFICATION_VERSION (2 << 16 | 70)
+
/* Types and defines for EFI CreateEvent */
enum efi_timer_delay {
EFI_TIMER_STOP = 0,
struct efi_event;
/* EFI Boot Services table */
+#define EFI_BOOT_SERVICES_SIGNATURE 0x56524553544f4f42
struct efi_boot_services {
struct efi_table_hdr hdr;
efi_status_t (EFIAPI *raise_tpl)(efi_uintn_t new_tpl);
void **handle, ...);
efi_status_t (EFIAPI *uninstall_multiple_protocol_interfaces)(
void *handle, ...);
- efi_status_t (EFIAPI *calculate_crc32)(void *data,
- unsigned long data_size, uint32_t *crc32);
+ efi_status_t (EFIAPI *calculate_crc32)(const void *data,
+ efi_uintn_t data_size,
+ u32 *crc32);
void (EFIAPI *copy_mem)(void *destination, const void *source,
size_t length);
void (EFIAPI *set_mem)(void *buffer, size_t size, uint8_t value);
};
/* EFI Runtime Services table */
-#define EFI_RUNTIME_SERVICES_SIGNATURE 0x5652453544e5552ULL
-#define EFI_RUNTIME_SERVICES_REVISION 0x00010000
+#define EFI_RUNTIME_SERVICES_SIGNATURE 0x56524553544e5552ULL
#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000
#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE 0x00020000
struct efi_system_table {
struct efi_table_hdr hdr;
- unsigned long fw_vendor; /* physical addr of wchar_t vendor string */
+ u16 *fw_vendor; /* physical addr of wchar_t vendor string */
u32 fw_revision;
efi_handle_t con_in_handle;
struct efi_simple_input_interface *con_in;
EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, \
0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+#define EFI_LOADED_IMAGE_PROTOCOL_REVISION 0x1000
+
struct efi_loaded_image {
u32 revision;
void *parent_handle;
#include <linux/list.h>
+/* Maximum number of configuration tables */
+#define EFI_MAX_CONFIGURATION_TABLES 16
+
int __efi_entry_check(void);
int __efi_exit_check(void);
const char *__efi_nesting(void);
#define EFI_CACHELINE_SIZE 128
#endif
+/* Key identifying current memory map */
+extern efi_uintn_t efi_memory_map_key;
+
extern struct efi_runtime_services efi_runtime_services;
extern struct efi_system_table systab;
/* List of all events */
extern struct list_head efi_events;
+/* Called by bootefi to initialize runtime */
+efi_status_t efi_initialize_system_table(void);
/* Called by bootefi to make console interface available */
int efi_console_register(void);
/* Called by bootefi to make all disk storage accessible as EFI objects */
* Use these to indicate that your code / data should go into the EFI runtime
* section and thus still be available when the OS is running
*/
-#define __efi_runtime_data __attribute__ ((section ("efi_runtime_data")))
-#define __efi_runtime __attribute__ ((section ("efi_runtime_text")))
+#define __efi_runtime_data __attribute__ ((section (".data.efi_runtime")))
+#define __efi_runtime __attribute__ ((section (".text.efi_runtime")))
/* Call this with mmio_ptr as the _pointer_ to a pointer to an MMIO region
* to make it available at runtime */
efi_status_t __efi_runtime EFIAPI efi_get_time(
struct efi_time *time,
struct efi_time_cap *capabilities);
-efi_status_t efi_get_time_init(void);
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
/*
#endif /* __ASSEMBLER */
+/* ELF register definitions */
+#define R_386_NONE 0
+#define R_386_32 1
+#define R_386_PC32 2
+#define R_386_GOT32 3
+#define R_386_PLT32 4
+#define R_386_COPY 5
+#define R_386_GLOB_DAT 6
+#define R_386_JMP_SLOT 7
+#define R_386_RELATIVE 8
+#define R_386_GOTOFF 9
+#define R_386_GOTPC 10
+#define R_386_NUM 11
+
+/* x86-64 relocation types */
+#define R_X86_64_NONE 0 /* No reloc */
+#define R_X86_64_64 1 /* Direct 64 bit */
+#define R_X86_64_PC32 2 /* PC relative 32 bit signed */
+#define R_X86_64_GOT32 3 /* 32 bit GOT entry */
+#define R_X86_64_PLT32 4 /* 32 bit PLT address */
+#define R_X86_64_COPY 5 /* Copy symbol at runtime */
+#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */
+#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
+#define R_X86_64_RELATIVE 8 /* Adjust by program base */
+/* 32 bit signed pc relative offset to GOT */
+#define R_X86_64_GOTPCREL 9
+#define R_X86_64_32 10 /* Direct 32 bit zero extended */
+#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
+#define R_X86_64_16 12 /* Direct 16 bit zero extended */
+#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */
+#define R_X86_64_8 14 /* Direct 8 bit sign extended */
+#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */
+
+#define R_X86_64_NUM 16
+
/*
* XXX - PowerPC defines really don't belong in here,
* but we'll put them in for simplicity.
#ifndef __ASSEMBLY__
#ifdef CONFIG_PHY_AQUANTIA
-#include <miiphy.h>
-#include <phy.h>
+#include <phy_interface.h>
#endif
struct spi_slave;
#ifndef __IMX_LPI2C_H__
#define __IMX_LPI2C_H__
+#include <clk.h>
+
struct imx_lpi2c_bus {
int index;
ulong base;
int speed;
struct i2c_pads_info *pads_info;
struct udevice *bus;
+ struct clk per_clk;
};
struct imx_lpi2c_reg {
/* copy a filename (allow for "..." notation, limit length) */
void copy_filename(char *dst, const char *src, int size);
+/* check if serverip is specified in filename from the command line */
+int is_serverip_in_cmd(void);
+
+/**
+ * net_parse_bootfile - Parse the bootfile env var / cmd line param
+ *
+ * @param ipaddr - a pointer to the ipaddr to populate if included in bootfile
+ * @param filename - a pointer to the string to save the filename part
+ * @param max_len - The longest - 1 that the filename part can be
+ *
+ * return 1 if parsed, 0 if bootfile is empty
+ */
+int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len);
+
/* get a random source port */
unsigned int random_port(void);
* @return 0 if OK, -ve on error
*/
int (*enable_backlight)(struct udevice *dev);
+ /**
+ * get_timings() - Get display timings from panel.
+ *
+ * @dev: Panel device containing the display timings
+ * @tim: Place to put timings
+ * @return 0 if OK, -ve on error
+ */
+ int (*get_display_timing)(struct udevice *dev,
+ struct display_timing *timing);
};
#define panel_get_ops(dev) ((struct panel_ops *)(dev)->driver->ops)
*/
int panel_enable_backlight(struct udevice *dev);
+/**
+ * panel_get_display_timing() - Get display timings from panel.
+ *
+ * @dev: Panel device containing the display timings
+ * @return 0 if OK, -ve on error
+ */
+int panel_get_display_timing(struct udevice *dev,
+ struct display_timing *timing);
+
#endif
#ifndef _PHY_H
#define _PHY_H
+#include <dm.h>
#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>
+#include <phy_interface.h>
#define PHY_FIXED_ID 0xa5a55a5a
#endif
-typedef enum {
- PHY_INTERFACE_MODE_MII,
- PHY_INTERFACE_MODE_GMII,
- PHY_INTERFACE_MODE_SGMII,
- PHY_INTERFACE_MODE_SGMII_2500,
- PHY_INTERFACE_MODE_QSGMII,
- PHY_INTERFACE_MODE_TBI,
- PHY_INTERFACE_MODE_RMII,
- PHY_INTERFACE_MODE_RGMII,
- PHY_INTERFACE_MODE_RGMII_ID,
- PHY_INTERFACE_MODE_RGMII_RXID,
- PHY_INTERFACE_MODE_RGMII_TXID,
- PHY_INTERFACE_MODE_RTBI,
- PHY_INTERFACE_MODE_XGMII,
- PHY_INTERFACE_MODE_XAUI,
- PHY_INTERFACE_MODE_RXAUI,
- PHY_INTERFACE_MODE_SFI,
- PHY_INTERFACE_MODE_INTERNAL,
- PHY_INTERFACE_MODE_NONE, /* Must be last */
-
- PHY_INTERFACE_MODE_COUNT,
-} phy_interface_t;
-
-static const char *phy_interface_strings[] = {
- [PHY_INTERFACE_MODE_MII] = "mii",
- [PHY_INTERFACE_MODE_GMII] = "gmii",
- [PHY_INTERFACE_MODE_SGMII] = "sgmii",
- [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
- [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
- [PHY_INTERFACE_MODE_TBI] = "tbi",
- [PHY_INTERFACE_MODE_RMII] = "rmii",
- [PHY_INTERFACE_MODE_RGMII] = "rgmii",
- [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
- [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
- [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
- [PHY_INTERFACE_MODE_RTBI] = "rtbi",
- [PHY_INTERFACE_MODE_XGMII] = "xgmii",
- [PHY_INTERFACE_MODE_XAUI] = "xaui",
- [PHY_INTERFACE_MODE_RXAUI] = "rxaui",
- [PHY_INTERFACE_MODE_SFI] = "sfi",
- [PHY_INTERFACE_MODE_INTERNAL] = "internal",
- [PHY_INTERFACE_MODE_NONE] = "",
-};
-
-static inline const char *phy_string_for_interface(phy_interface_t i)
-{
- /* Default to unknown */
- if (i > PHY_INTERFACE_MODE_NONE)
- i = PHY_INTERFACE_MODE_NONE;
-
- return phy_interface_strings[i];
-}
-
-
struct phy_device;
#define MDIO_NAME_LEN 32
#ifdef CONFIG_DM_ETH
struct udevice *dev;
+ ofnode node;
#else
struct eth_device *dev;
#endif
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct udevice *dev,
phy_interface_t interface);
+static inline ofnode phy_get_ofnode(struct phy_device *phydev)
+{
+ if (ofnode_valid(phydev->node))
+ return phydev->node;
+ else
+ return dev_ofnode(phydev->dev);
+}
#else
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
phy_interface_t interface);
+static inline ofnode phy_get_ofnode(struct phy_device *phydev)
+{
+ return ofnode_null();
+}
#endif
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Andy Fleming <afleming@gmail.com>
+ *
+ * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
+ */
+
+#ifndef _PHY_INTERFACE_H
+#define _PHY_INTERFACE_H
+
+typedef enum {
+ PHY_INTERFACE_MODE_MII,
+ PHY_INTERFACE_MODE_GMII,
+ PHY_INTERFACE_MODE_SGMII,
+ PHY_INTERFACE_MODE_SGMII_2500,
+ PHY_INTERFACE_MODE_QSGMII,
+ PHY_INTERFACE_MODE_TBI,
+ PHY_INTERFACE_MODE_RMII,
+ PHY_INTERFACE_MODE_RGMII,
+ PHY_INTERFACE_MODE_RGMII_ID,
+ PHY_INTERFACE_MODE_RGMII_RXID,
+ PHY_INTERFACE_MODE_RGMII_TXID,
+ PHY_INTERFACE_MODE_RTBI,
+ PHY_INTERFACE_MODE_XGMII,
+ PHY_INTERFACE_MODE_XAUI,
+ PHY_INTERFACE_MODE_RXAUI,
+ PHY_INTERFACE_MODE_SFI,
+ PHY_INTERFACE_MODE_INTERNAL,
+ PHY_INTERFACE_MODE_NONE, /* Must be last */
+
+ PHY_INTERFACE_MODE_COUNT,
+} phy_interface_t;
+
+static const char * const phy_interface_strings[] = {
+ [PHY_INTERFACE_MODE_MII] = "mii",
+ [PHY_INTERFACE_MODE_GMII] = "gmii",
+ [PHY_INTERFACE_MODE_SGMII] = "sgmii",
+ [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
+ [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
+ [PHY_INTERFACE_MODE_TBI] = "tbi",
+ [PHY_INTERFACE_MODE_RMII] = "rmii",
+ [PHY_INTERFACE_MODE_RGMII] = "rgmii",
+ [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
+ [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
+ [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
+ [PHY_INTERFACE_MODE_RTBI] = "rtbi",
+ [PHY_INTERFACE_MODE_XGMII] = "xgmii",
+ [PHY_INTERFACE_MODE_XAUI] = "xaui",
+ [PHY_INTERFACE_MODE_RXAUI] = "rxaui",
+ [PHY_INTERFACE_MODE_SFI] = "sfi",
+ [PHY_INTERFACE_MODE_INTERNAL] = "internal",
+ [PHY_INTERFACE_MODE_NONE] = "",
+};
+
+static inline const char *phy_string_for_interface(phy_interface_t i)
+{
+ /* Default to unknown */
+ if (i > PHY_INTERFACE_MODE_NONE)
+ i = PHY_INTERFACE_MODE_NONE;
+
+ return phy_interface_strings[i];
+}
+
+#endif /* _PHY_INTERFACE_H */
* @power_domain A pointer to a power domain struct to initialize.
* @return 0 if OK, or a negative error code.
*/
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
int power_domain_get(struct udevice *dev, struct power_domain *power_domain);
+#else
+static inline
+int power_domain_get(struct udevice *dev, struct power_domain *power_domain)
+{
+ return -ENOSYS;
+}
+#endif
/**
* power_domain_free - Free a previously requested power domain.
* requested by power_domain_get().
* @return 0 if OK, or a negative error code.
*/
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
int power_domain_free(struct power_domain *power_domain);
+#else
+static inline int power_domain_free(struct power_domain *power_domain)
+{
+ return -ENOSYS;
+}
+#endif
/**
* power_domain_on - Enable power to a power domain.
* requested by power_domain_get().
* @return 0 if OK, or a negative error code.
*/
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
int power_domain_on(struct power_domain *power_domain);
+#else
+static inline int power_domain_on(struct power_domain *power_domain)
+{
+ return -ENOSYS;
+}
+#endif
/**
* power_domain_off - Disable power ot a power domain.
* requested by power_domain_get().
* @return 0 if OK, or a negative error code.
*/
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
int power_domain_off(struct power_domain *power_domain);
+#else
+static inline int power_domain_off(struct power_domain *power_domain)
+{
+ return -ENOSYS;
+}
+#endif
#endif
* image is found. For * example if u-boot.img is used we don't check that
* spl_parse_image_header() can parse a valid header.
*/
-binman_sym_extern(ulong, u_boot_any, pos);
+binman_sym_extern(ulong, u_boot_any, image_pos);
/**
* spl_load_simple_fit() - Loads a fit image from a device.
/* Max buffer size supported by our tpm */
#define TPM_DEV_BUFSIZE 1260
+/**
+ * enum tpm_version - The version of the TPM stack to be used
+ * @TPM_V1: Use TPM v1.x stack
+ * @TPM_V2: Use TPM v2.x stack
+ */
+enum tpm_version {
+ TPM_V1 = 0,
+ TPM_V2,
+};
+
/**
* struct tpm_chip_priv - Information about a TPM, stored by the uclass
*
* communcation is attempted. If the device has an xfer() method, this is
* not needed. There is no need to set up @buf.
*
+ * @version: TPM stack to be used
* @duration_ms: Length of each duration type in milliseconds
* @retry_time_ms: Time to wait before retrying receive
+ * @buf: Buffer used during the exchanges with the chip
* @pcr_count: Number of PCR per bank
* @pcr_select_min: Minimum size in bytes of the pcrSelect array
- * @buf: Buffer used during the exchanges with the chip
*/
struct tpm_chip_priv {
+ enum tpm_version version;
+
uint duration_ms[TPM_DURATION_COUNT];
uint retry_time_ms;
-#if defined(CONFIG_TPM_V2)
+ u8 buf[TPM_DEV_BUFSIZE + sizeof(u8)]; /* Max buffer size + addr */
+
+ /* TPM v2 specific data */
uint pcr_count;
uint pcr_select_min;
-#endif
- u8 buf[TPM_DEV_BUFSIZE + sizeof(u8)]; /* Max buffer size + addr */
};
/**
* After all commands have been completed the caller should call
* close().
*
- * @dev: Device to close
+ * @dev: Device to open
* @return 0 ok OK, -ve on error
*/
int (*open)(struct udevice *dev);
int tpm_init(void);
/**
- * Retrieve the array containing all the commands.
+ * Retrieve the array containing all the v1 (resp. v2) commands.
*
* @return a cmd_tbl_t array.
*/
-cmd_tbl_t *get_tpm_commands(unsigned int *size);
+#if defined(CONFIG_TPM_V1)
+cmd_tbl_t *get_tpm1_commands(unsigned int *size);
+#else
+static inline cmd_tbl_t *get_tpm1_commands(unsigned int *size)
+{
+ return NULL;
+}
+#endif
+#if defined(CONFIG_TPM_V2)
+cmd_tbl_t *get_tpm2_commands(unsigned int *size);
+#else
+static inline cmd_tbl_t *get_tpm2_commands(unsigned int *size)
+{
+ return NULL;
+}
+#endif
#endif /* __TPM_COMMON_H */
config FDT_FIXUP_PARTITIONS
bool "overwrite MTD partitions in DTS through defined in 'mtdparts'"
depends on OF_LIBFDT
- default n
+ depends on CMD_MTDPARTS
help
Allow overwriting defined partitions in the device tree blob
using partition info defined in the 'mtdparts' environment
return ret;
if (!bdev)
return -ENOENT;
+ /* Set the DM_FLAG_NAME_ALLOCED flag to avoid a memory leak */
+ device_set_name_alloced(bdev);
/* Allocate priv */
ret = device_probe(bdev);
if (ret)
config EFI_LOADER
bool "Support running EFI Applications in U-Boot"
depends on (ARM || X86 || RISCV) && OF_LIBFDT
- # We do not support bootefi booting ARMv7 in non-secure mode
- depends on !ARMV7_NONSEC
# We need EFI_STUB_64BIT to be set on x86_64 with EFI_STUB
depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
+CFLAGS_efi_boottime.o += \
+ -DFW_VERSION="0x$(VERSION)" \
+ -DFW_PATCHLEVEL="0x$(PATCHLEVEL)"
CFLAGS_helloworld.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI) -Os
*/
static bool efi_is_direct_boot = true;
-/*
- * EFI can pass arbitrary additional "tables" containing vendor specific
- * information to the payload. One such table is the FDT table which contains
- * a pointer to a flattened device tree blob.
- *
- * In most cases we want to pass an FDT to the payload, so reserve one slot of
- * config table space for it. The pointer gets populated by do_bootefi_exec().
- */
-static struct efi_configuration_table __efi_runtime_data efi_conf_table[16];
-
#ifdef CONFIG_ARM
/*
* The "gd" pointer lives in a register on ARM and AArch64 that we declare
return indent_string(--nesting_level);
}
+/**
+ * efi_update_table_header_crc32() - Update CRC32 in table header
+ *
+ * @table: EFI table
+ */
+static void efi_update_table_header_crc32(struct efi_table_hdr *table)
+{
+ table->crc32 = 0;
+ table->crc32 = crc32(0, (const unsigned char *)table,
+ table->headersize);
+}
+
/**
* efi_queue_event() - queue an EFI event
* @event: event to signal
event->is_queued = false;
}
+/**
+ * is_valid_tpl() - check if the task priority level is valid
+ *
+ * @tpl: TPL level to check
+ * ReturnValue: status code
+ */
+efi_status_t is_valid_tpl(efi_uintn_t tpl)
+{
+ switch (tpl) {
+ case TPL_APPLICATION:
+ case TPL_CALLBACK:
+ case TPL_NOTIFY:
+ case TPL_HIGH_LEVEL:
+ return EFI_SUCCESS;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+}
+
/**
* efi_signal_event() - signal an EFI event
* @event: event to signal
if (event == NULL)
return EFI_INVALID_PARAMETER;
- if ((type & EVT_NOTIFY_SIGNAL) && (type & EVT_NOTIFY_WAIT))
+ switch (type) {
+ case 0:
+ case EVT_TIMER:
+ case EVT_NOTIFY_SIGNAL:
+ case EVT_TIMER | EVT_NOTIFY_SIGNAL:
+ case EVT_NOTIFY_WAIT:
+ case EVT_TIMER | EVT_NOTIFY_WAIT:
+ case EVT_SIGNAL_EXIT_BOOT_SERVICES:
+ case EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE:
+ break;
+ default:
return EFI_INVALID_PARAMETER;
+ }
- if ((type & (EVT_NOTIFY_SIGNAL | EVT_NOTIFY_WAIT)) &&
- notify_function == NULL)
+ if (is_valid_tpl(notify_tpl) != EFI_SUCCESS)
return EFI_INVALID_PARAMETER;
evt = calloc(1, sizeof(struct efi_event));
*/
static void efi_remove_configuration_table(int i)
{
- struct efi_configuration_table *this = &efi_conf_table[i];
- struct efi_configuration_table *next = &efi_conf_table[i + 1];
- struct efi_configuration_table *end = &efi_conf_table[systab.nr_tables];
+ struct efi_configuration_table *this = &systab.tables[i];
+ struct efi_configuration_table *next = &systab.tables[i + 1];
+ struct efi_configuration_table *end = &systab.tables[systab.nr_tables];
memmove(this, next, (ulong)end - (ulong)next);
systab.nr_tables--;
/* Check for guid override */
for (i = 0; i < systab.nr_tables; i++) {
- if (!guidcmp(guid, &efi_conf_table[i].guid)) {
+ if (!guidcmp(guid, &systab.tables[i].guid)) {
if (table)
- efi_conf_table[i].table = table;
+ systab.tables[i].table = table;
else
efi_remove_configuration_table(i);
goto out;
return EFI_NOT_FOUND;
/* No override, check for overflow */
- if (i >= ARRAY_SIZE(efi_conf_table))
+ if (i >= EFI_MAX_CONFIGURATION_TABLES)
return EFI_OUT_OF_RESOURCES;
/* Add a new entry */
- memcpy(&efi_conf_table[i].guid, guid, sizeof(*guid));
- efi_conf_table[i].table = table;
+ memcpy(&systab.tables[i].guid, guid, sizeof(*guid));
+ systab.tables[i].table = table;
systab.nr_tables = i + 1;
out:
+ /* systab.nr_tables may have changed. So we need to update the crc32 */
+ efi_update_table_header_crc32(&systab.hdr);
+
/* Notify that the configuration table was changed */
list_for_each_entry(evt, &efi_events, link) {
if (evt->group && !guidcmp(evt->group, guid)) {
/* efi_exit() assumes that the handle points to the info */
obj->handle = info;
+ info->revision = EFI_LOADED_IMAGE_PROTOCOL_REVISION;
info->file_path = file_path;
if (device_path) {
EFI_ENTRY("%p, %ld", image_handle, map_key);
+ /* Check that the caller has read the current memory map */
+ if (map_key != efi_memory_map_key)
+ return EFI_INVALID_PARAMETER;
+
/* Make sure that notification functions are not called anymore */
efi_tpl = TPL_HIGH_LEVEL;
systab.boottime = NULL;
/* Recalculate CRC32 */
- systab.hdr.crc32 = 0;
- systab.hdr.crc32 = crc32(0, (const unsigned char *)&systab,
- sizeof(struct efi_system_table));
+ efi_update_table_header_crc32(&systab.hdr);
/* Give the payload some time to boot */
efi_set_watchdog(0);
{
EFI_ENTRY("%p", handle);
- va_list argptr;
+ efi_va_list argptr;
const efi_guid_t *protocol;
void *protocol_interface;
efi_status_t r = EFI_SUCCESS;
if (!handle)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- va_start(argptr, handle);
+ efi_va_start(argptr, handle);
for (;;) {
- protocol = va_arg(argptr, efi_guid_t*);
+ protocol = efi_va_arg(argptr, efi_guid_t*);
if (!protocol)
break;
- protocol_interface = va_arg(argptr, void*);
+ protocol_interface = efi_va_arg(argptr, void*);
r = EFI_CALL(efi_install_protocol_interface(
handle, protocol,
EFI_NATIVE_INTERFACE,
break;
i++;
}
- va_end(argptr);
+ efi_va_end(argptr);
if (r == EFI_SUCCESS)
return EFI_EXIT(r);
/* If an error occurred undo all changes. */
- va_start(argptr, handle);
+ efi_va_start(argptr, handle);
for (; i; --i) {
- protocol = va_arg(argptr, efi_guid_t*);
- protocol_interface = va_arg(argptr, void*);
+ protocol = efi_va_arg(argptr, efi_guid_t*);
+ protocol_interface = efi_va_arg(argptr, void*);
EFI_CALL(efi_uninstall_protocol_interface(handle, protocol,
protocol_interface));
}
- va_end(argptr);
+ efi_va_end(argptr);
return EFI_EXIT(r);
}
{
EFI_ENTRY("%p", handle);
- va_list argptr;
+ efi_va_list argptr;
const efi_guid_t *protocol;
void *protocol_interface;
efi_status_t r = EFI_SUCCESS;
if (!handle)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- va_start(argptr, handle);
+ efi_va_start(argptr, handle);
for (;;) {
- protocol = va_arg(argptr, efi_guid_t*);
+ protocol = efi_va_arg(argptr, efi_guid_t*);
if (!protocol)
break;
- protocol_interface = va_arg(argptr, void*);
+ protocol_interface = efi_va_arg(argptr, void*);
r = EFI_CALL(efi_uninstall_protocol_interface(
handle, protocol,
protocol_interface));
break;
i++;
}
- va_end(argptr);
+ efi_va_end(argptr);
if (r == EFI_SUCCESS)
return EFI_EXIT(r);
/* If an error occurred undo all changes. */
- va_start(argptr, handle);
+ efi_va_start(argptr, handle);
for (; i; --i) {
- protocol = va_arg(argptr, efi_guid_t*);
- protocol_interface = va_arg(argptr, void*);
+ protocol = efi_va_arg(argptr, efi_guid_t*);
+ protocol_interface = efi_va_arg(argptr, void*);
EFI_CALL(efi_install_protocol_interface(&handle, protocol,
EFI_NATIVE_INTERFACE,
protocol_interface));
}
- va_end(argptr);
+ efi_va_end(argptr);
return EFI_EXIT(r);
}
*
* Return: status code
*/
-static efi_status_t EFIAPI efi_calculate_crc32(void *data,
- unsigned long data_size,
- uint32_t *crc32_p)
+static efi_status_t EFIAPI efi_calculate_crc32(const void *data,
+ efi_uintn_t data_size,
+ u32 *crc32_p)
{
- EFI_ENTRY("%p, %ld", data, data_size);
+ EFI_ENTRY("%p, %zu", data, data_size);
*crc32_p = crc32(0, data, data_size);
return EFI_EXIT(EFI_SUCCESS);
}
return EFI_EXIT(r);
}
-static const struct efi_boot_services efi_boot_services = {
+static struct efi_boot_services efi_boot_services = {
.hdr = {
- .headersize = sizeof(struct efi_table_hdr),
+ .signature = EFI_BOOT_SERVICES_SIGNATURE,
+ .revision = EFI_SPECIFICATION_VERSION,
+ .headersize = sizeof(struct efi_boot_services),
},
.raise_tpl = efi_raise_tpl,
.restore_tpl = efi_restore_tpl,
.create_event_ex = efi_create_event_ex,
};
-static uint16_t __efi_runtime_data firmware_vendor[] = L"Das U-Boot";
+static u16 __efi_runtime_data firmware_vendor[] = L"Das U-Boot";
struct efi_system_table __efi_runtime_data systab = {
.hdr = {
.signature = EFI_SYSTEM_TABLE_SIGNATURE,
- .revision = 2 << 16 | 70, /* 2.7 */
- .headersize = sizeof(struct efi_table_hdr),
+ .revision = EFI_SPECIFICATION_VERSION,
+ .headersize = sizeof(struct efi_system_table),
},
- .fw_vendor = (long)firmware_vendor,
+ .fw_vendor = firmware_vendor,
+ .fw_revision = FW_VERSION << 16 | FW_PATCHLEVEL << 8,
.con_in = (void *)&efi_con_in,
.con_out = (void *)&efi_con_out,
.std_err = (void *)&efi_con_out,
.runtime = (void *)&efi_runtime_services,
.boottime = (void *)&efi_boot_services,
.nr_tables = 0,
- .tables = (void *)efi_conf_table,
+ .tables = NULL,
};
+
+/**
+ * efi_initialize_system_table() - Initialize system table
+ *
+ * Return Value: status code
+ */
+efi_status_t efi_initialize_system_table(void)
+{
+ efi_status_t ret;
+
+ /* Allocate configuration table array */
+ ret = efi_allocate_pool(EFI_RUNTIME_SERVICES_DATA,
+ EFI_MAX_CONFIGURATION_TABLES *
+ sizeof(struct efi_configuration_table),
+ (void **)&systab.tables);
+
+ /* Set crc32 field in table headers */
+ efi_update_table_header_crc32(&systab.hdr);
+ efi_update_table_header_crc32(&efi_runtime_services.hdr);
+ efi_update_table_header_crc32(&efi_boot_services.hdr);
+
+ return ret;
+}
EFI_ENTRY("%p", this);
printf(ESC"[2J");
+ efi_con_mode.cursor_column = 0;
+ efi_con_mode.cursor_row = 0;
return EFI_EXIT(EFI_SUCCESS);
}
bool extended_verification)
{
EFI_ENTRY("%p, %d", this, extended_verification);
- return EFI_EXIT(EFI_UNSUPPORTED);
+
+ /* Empty input buffer */
+ while (tstc())
+ getc();
+
+ return EFI_EXIT(EFI_SUCCESS);
}
/*
const efi_guid_t efi_file_info_guid = EFI_FILE_INFO_GUID;
static int machines[] = {
-#if defined(CONFIG_ARM64)
+#if defined(__aarch64__)
IMAGE_FILE_MACHINE_ARM64,
-#elif defined(CONFIG_ARM)
+#elif defined(__arm__)
IMAGE_FILE_MACHINE_ARM,
IMAGE_FILE_MACHINE_THUMB,
IMAGE_FILE_MACHINE_ARMNT,
#endif
-#if defined(CONFIG_X86_64)
+#if defined(__x86_64__)
IMAGE_FILE_MACHINE_AMD64,
-#elif defined(CONFIG_X86)
+#elif defined(__i386__)
IMAGE_FILE_MACHINE_I386,
#endif
-#if defined(CONFIG_CPU_RISCV_32)
+#if defined(__riscv) && (__riscv_xlen == 32)
IMAGE_FILE_MACHINE_RISCV32,
#endif
-#if defined(CONFIG_CPU_RISCV_64)
+#if defined(__riscv) && (__riscv_xlen == 64)
IMAGE_FILE_MACHINE_RISCV64,
#endif
0 };
#include <efi_loader.h>
#include <inttypes.h>
#include <malloc.h>
+#include <mapmem.h>
#include <watchdog.h>
#include <linux/list_sort.h>
DECLARE_GLOBAL_DATA_PTR;
+efi_uintn_t efi_memory_map_key;
+
struct efi_mem_list {
struct list_head link;
struct efi_mem_desc desc;
debug("%s: 0x%" PRIx64 " 0x%" PRIx64 " %d %s\n", __func__,
start, pages, memory_type, overlap_only_ram ? "yes" : "no");
+ if (memory_type >= EFI_MAX_MEMORY_TYPE)
+ return EFI_INVALID_PARAMETER;
+
if (!pages)
return start;
+ ++efi_memory_map_key;
newlist = calloc(1, sizeof(*newlist));
newlist->desc.type = memory_type;
newlist->desc.physical_start = start;
efi_status_t r = EFI_SUCCESS;
uint64_t addr;
+ if (!memory)
+ return EFI_INVALID_PARAMETER;
+
switch (type) {
case EFI_ALLOCATE_ANY_PAGES:
/* Any page */
- addr = efi_find_free_memory(len, gd->start_addr_sp);
+ addr = efi_find_free_memory(len, -1ULL);
if (!addr) {
r = EFI_NOT_FOUND;
break;
/* Reserve that map in our memory maps */
ret = efi_add_memory_map(addr, pages, memory_type, true);
if (ret == addr) {
- *memory = addr;
+ *memory = (uintptr_t)map_sysmem(addr, len);
} else {
/* Map would overlap, bail out */
r = EFI_OUT_OF_RESOURCES;
efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
{
uint64_t r = 0;
+ uint64_t addr = map_to_sysmem((void *)(uintptr_t)memory);
- r = efi_add_memory_map(memory, pages, EFI_CONVENTIONAL_MEMORY, false);
+ r = efi_add_memory_map(addr, pages, EFI_CONVENTIONAL_MEMORY, false);
/* Merging of adjacent free regions is missing */
- if (r == memory)
+ if (r == addr)
return EFI_SUCCESS;
return EFI_NOT_FOUND;
efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer)
{
efi_status_t r;
- efi_physical_addr_t t;
+ struct efi_pool_allocation *alloc;
u64 num_pages = (size + sizeof(struct efi_pool_allocation) +
EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
+ if (!buffer)
+ return EFI_INVALID_PARAMETER;
+
if (size == 0) {
*buffer = NULL;
return EFI_SUCCESS;
}
r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, pool_type, num_pages,
- &t);
+ (uint64_t *)&alloc);
if (r == EFI_SUCCESS) {
- struct efi_pool_allocation *alloc = (void *)(uintptr_t)t;
alloc->num_pages = num_pages;
*buffer = alloc->data;
}
struct list_head *lhandle;
efi_uintn_t provided_map_size = *memory_map_size;
+ if (!memory_map_size)
+ return EFI_INVALID_PARAMETER;
+
list_for_each(lhandle, &efi_mem)
map_entries++;
if (provided_map_size < map_size)
return EFI_BUFFER_TOO_SMALL;
+ if (!memory_map)
+ return EFI_INVALID_PARAMETER;
+
if (descriptor_size)
*descriptor_size = sizeof(struct efi_mem_desc);
*descriptor_version = EFI_MEMORY_DESCRIPTOR_VERSION;
/* Copy list into array */
- if (memory_map) {
- /* Return the list in ascending order */
- memory_map = &memory_map[map_entries - 1];
- list_for_each(lhandle, &efi_mem) {
- struct efi_mem_list *lmem;
+ /* Return the list in ascending order */
+ memory_map = &memory_map[map_entries - 1];
+ list_for_each(lhandle, &efi_mem) {
+ struct efi_mem_list *lmem;
- lmem = list_entry(lhandle, struct efi_mem_list, link);
- *memory_map = lmem->desc;
- memory_map--;
- }
+ lmem = list_entry(lhandle, struct efi_mem_list, link);
+ *memory_map = lmem->desc;
+ memory_map--;
}
- *map_key = 0;
+ if (map_key)
+ *map_key = efi_memory_map_key;
return EFI_SUCCESS;
}
}
}
-int efi_memory_init(void)
+/* Add memory regions for U-Boot's memory and for the runtime services code */
+static void add_u_boot_and_runtime(void)
{
unsigned long runtime_start, runtime_end, runtime_pages;
unsigned long uboot_start, uboot_pages;
unsigned long uboot_stack_size = 16 * 1024 * 1024;
- efi_add_known_memory();
-
/* Add U-Boot */
uboot_start = (gd->start_addr_sp - uboot_stack_size) & ~EFI_PAGE_MASK;
uboot_pages = (gd->ram_top - uboot_start) >> EFI_PAGE_SHIFT;
runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
efi_add_memory_map(runtime_start, runtime_pages,
EFI_RUNTIME_SERVICES_CODE, false);
+}
+
+int efi_memory_init(void)
+{
+ efi_add_known_memory();
+
+ if (!IS_ENABLED(CONFIG_SANDBOX))
+ add_u_boot_and_runtime();
#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
/* Request a 32bit 64MB bounce buffer region */
memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
netobj->net_mode.hwaddr_size = ARP_HLEN;
netobj->net_mode.max_packet_size = PKTSIZE;
+ netobj->net_mode.if_type = ARP_ETHER;
netobj->pxe.mode = &netobj->pxe_mode;
if (dhcp_ack)
#include <common.h>
#include <command.h>
#include <dm.h>
+#include <elf.h>
#include <efi_loader.h>
#include <rtc.h>
* TODO(sjg@chromium.org): These defines and structs should come from the elf
* header for each arch (or a generic header) rather than being repeated here.
*/
-#if defined(CONFIG_ARM64)
-#define R_RELATIVE 1027
+#if defined(__aarch64__)
+#define R_RELATIVE R_AARCH64_RELATIVE
#define R_MASK 0xffffffffULL
#define IS_RELA 1
-#elif defined(CONFIG_ARM)
-#define R_RELATIVE 23
+#elif defined(__arm__)
+#define R_RELATIVE R_ARM_RELATIVE
#define R_MASK 0xffULL
-#elif defined(CONFIG_X86)
-#include <asm/elf.h>
+#elif defined(__x86_64__) || defined(__i386__)
#define R_RELATIVE R_386_RELATIVE
#define R_MASK 0xffULL
-#elif defined(CONFIG_RISCV)
-#include <elf.h>
+#elif defined(__riscv)
#define R_RELATIVE R_RISCV_RELATIVE
#define R_MASK 0xffULL
#define IS_RELA 1
u32 foo2;
u32 foo3;
};
-#ifdef CONFIG_CPU_RISCV_32
+#if (__riscv_xlen == 32)
#define R_ABSOLUTE R_RISCV_32
#define SYM_INDEX 8
-#else
+#elif (__riscv_xlen == 64)
#define R_ABSOLUTE R_RISCV_64
#define SYM_INDEX 32
+#else
+#error unknown riscv target
#endif
#else
#error Need to add relocation awareness
while (1) { }
}
+/**
+ * efi_get_time_boottime - get current time
+ *
+ * This function implements the GetTime runtime service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @time: pointer to structure to receive current time
+ * @capabilities: pointer to structure to receive RTC properties
+ * Return Value: status code
+ */
static efi_status_t EFIAPI efi_get_time_boottime(
struct efi_time *time,
struct efi_time_cap *capabilities)
{
-#if defined(CONFIG_CMD_DATE) && defined(CONFIG_DM_RTC)
- struct rtc_time tm;
+#ifdef CONFIG_DM_RTC
+ efi_status_t ret = EFI_SUCCESS;
int r;
+ struct rtc_time tm;
struct udevice *dev;
EFI_ENTRY("%p %p", time, capabilities);
- r = uclass_get_device(UCLASS_RTC, 0, &dev);
- if (r)
- return EFI_EXIT(EFI_DEVICE_ERROR);
+ if (!time) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
- r = dm_rtc_get(dev, &tm);
- if (r)
- return EFI_EXIT(EFI_DEVICE_ERROR);
+ r = uclass_get_device(UCLASS_RTC, 0, &dev);
+ if (!r)
+ r = dm_rtc_get(dev, &tm);
+ if (r) {
+ ret = EFI_DEVICE_ERROR;
+ goto out;
+ }
memset(time, 0, sizeof(*time));
time->year = tm.tm_year;
time->day = tm.tm_mday;
time->hour = tm.tm_hour;
time->minute = tm.tm_min;
- time->daylight = tm.tm_isdst;
-
- return EFI_EXIT(EFI_SUCCESS);
+ time->second = tm.tm_sec;
+ time->daylight = EFI_TIME_ADJUST_DAYLIGHT;
+ if (tm.tm_isdst > 0)
+ time->daylight |= EFI_TIME_IN_DAYLIGHT;
+ time->timezone = EFI_UNSPECIFIED_TIMEZONE;
+
+ if (capabilities) {
+ /* Set reasonable dummy values */
+ capabilities->resolution = 1; /* 1 Hz */
+ capabilities->accuracy = 100000000; /* 100 ppm */
+ capabilities->sets_to_zero = false;
+ }
+out:
+ return EFI_EXIT(ret);
#else
- return EFI_DEVICE_ERROR;
+ EFI_ENTRY("%p %p", time, capabilities);
+ return EFI_EXIT(EFI_DEVICE_ERROR);
#endif
}
return EFI_DEVICE_ERROR;
}
-efi_status_t __weak efi_get_time_init(void)
-{
- return EFI_SUCCESS;
-}
-
struct efi_runtime_detach_list_struct {
void *ptr;
void *patchto;
struct efi_runtime_services __efi_runtime_data efi_runtime_services = {
.hdr = {
.signature = EFI_RUNTIME_SERVICES_SIGNATURE,
- .revision = EFI_RUNTIME_SERVICES_REVISION,
- .headersize = sizeof(struct efi_table_hdr),
+ .revision = EFI_SPECIFICATION_VERSION,
+ .headersize = sizeof(struct efi_runtime_services),
},
.get_time = &efi_get_time_boottime,
.set_time = (void *)&efi_device_error,
/* Reserve 4kiB page for SMBIOS */
ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
EFI_RUNTIME_SERVICES_DATA, 1, &dmi);
- if (ret != EFI_SUCCESS)
- return ret;
+
+ if (ret != EFI_SUCCESS) {
+ /* Could not find space in lowmem, use highmem instead */
+ ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_RUNTIME_SERVICES_DATA, 1, &dmi);
+
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
/*
* Generate SMBIOS tables - we know that efi_allocate_pages() returns
-efi_miniapp_file_image.h
+efi_miniapp_file_image_exit.h
+efi_miniapp_file_image_return.h
*.efi
+*.so
obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += \
efi_selftest.o \
efi_selftest_bitblt.o \
+efi_selftest_config_table.o \
efi_selftest_controllers.o \
efi_selftest_console.o \
+efi_selftest_crc32.o \
efi_selftest_devicepath.o \
efi_selftest_devicepath_util.o \
efi_selftest_events.o \
efi_selftest_fdt.o \
efi_selftest_gop.o \
efi_selftest_manageprotocols.o \
+efi_selftest_rtc.o \
efi_selftest_snp.o \
efi_selftest_textinput.o \
efi_selftest_textoutput.o \
# TODO: As of v2018.01 the relocation code for the EFI application cannot
# be built on x86_64.
-ifeq ($(CONFIG_X86_64),)
+ifeq ($(CONFIG_X86_64)$(CONFIG_SANDBOX),)
ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST),)
#include <efi_selftest.h>
#include <vsprintf.h>
-/*
- * Constants for test step bitmap
- */
+/* Constants for test step bitmap */
#define EFI_ST_SETUP 1
#define EFI_ST_EXECUTE 2
#define EFI_ST_TEARDOWN 4
*
* The size of the memory map is determined.
* Pool memory is allocated to copy the memory map.
- * The memory amp is copied and the map key is obtained.
+ * The memory map is copied and the map key is obtained.
* The map key is used to exit the boot services.
*/
void efi_st_exit_boot_services(void)
* Check that a test exists.
*
* @testname: name of the test
- * @return: test
+ * @return: test, or NULL if not found
*/
static struct efi_unit_test *find_test(const u16 *testname)
{
*
* @testname name of a single selected test or NULL
* @phase test phase
- * @steps steps to execute
+ * @steps steps to execute (mask with bits from EFI_ST_...)
* failures returns EFI_ST_SUCCESS if all test steps succeeded
*/
void efi_st_do_tests(const u16 *testname, unsigned int phase,
efi_st_printc(EFI_WHITE, "\nSummary: %u failures\n\n", failures);
/* Reset system */
- efi_st_printf("Preparing for reset. Press any key.\n");
+ efi_st_printf("Preparing for reset. Press any key...\n");
efi_st_get_key();
runtime->reset_system(EFI_RESET_WARM, EFI_NOT_READY,
sizeof(reset_message), reset_message);
efi_st_printf("\n");
- efi_st_error("Reset failed.\n");
+ efi_st_error("Reset failed\n");
return EFI_UNSUPPORTED;
}
efi_uintn_t buf_size;
char buf[16] __aligned(ARCH_DMA_MINALIGN);
+ /* Connect controller to virtual disk */
ret = boottime->connect_controller(disk_handle, NULL, NULL, 1);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to connect controller\n");
return EFI_ST_FAILURE;
}
+
+ /* Get the handle for the partition */
ret = boottime->locate_handle_buffer(
BY_PROTOCOL, &guid_device_path, NULL,
&no_handles, &handles);
efi_st_error("Partition handle not found\n");
return EFI_ST_FAILURE;
}
+
+ /* Open the simple file system protocol */
ret = boottime->open_protocol(handle_partition,
&guid_simple_file_system_protocol,
(void **)&file_system, NULL, NULL,
efi_st_error("Failed to open simple file system protocol\n");
return EFI_ST_FAILURE;
}
+
+ /* Open volume */
ret = file_system->open_volume(file_system, &root);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to open volume\n");
"Wrong volume label '%ps', expected 'U-BOOT TEST'\n",
system_info.info.volume_label);
}
+
+ /* Read file */
ret = root->open(root, &file, (s16 *)L"hello.txt", EFI_FILE_MODE_READ,
0);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to read file\n");
return EFI_ST_FAILURE;
}
+ if (buf_size != 13) {
+ efi_st_error("Wrong number of bytes read: %u\n",
+ (unsigned int)buf_size);
+ return EFI_ST_FAILURE;
+ }
if (efi_st_memcmp(buf, "Hello world!", 12)) {
efi_st_error("Unexpected file content\n");
return EFI_ST_FAILURE;
efi_st_error("Failed to close file\n");
return EFI_ST_FAILURE;
}
+
+#ifdef CONFIG_FAT_WRITE
+ /* Write file */
+ ret = root->open(root, &file, (s16 *)L"u-boot.txt",
+ EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE, 0);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open file\n");
+ return EFI_ST_FAILURE;
+ }
+ buf_size = 7;
+ boottime->set_mem(buf, sizeof(buf), 0);
+ boottime->copy_mem(buf, "U-Boot", buf_size);
+ ret = file->write(file, &buf_size, buf);
+ if (ret != EFI_SUCCESS || buf_size != 7) {
+ efi_st_error("Failed to write file\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = file->close(file);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close file\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Verify file */
+ boottime->set_mem(buf, sizeof(buf), 0);
+ ret = root->open(root, &file, (s16 *)L"u-boot.txt", EFI_FILE_MODE_READ,
+ 0);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open file\n");
+ return EFI_ST_FAILURE;
+ }
+ buf_size = sizeof(buf) - 1;
+ ret = file->read(file, &buf_size, buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to read file\n");
+ return EFI_ST_FAILURE;
+ }
+ if (buf_size != 7) {
+ efi_st_error("Wrong number of bytes read: %u\n",
+ (unsigned int)buf_size);
+ return EFI_ST_FAILURE;
+ }
+ if (efi_st_memcmp(buf, "U-Boot", 7)) {
+ efi_st_error("Unexpected file content %s\n", buf);
+ return EFI_ST_FAILURE;
+ }
+ ret = file->close(file);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close file\n");
+ return EFI_ST_FAILURE;
+ }
+#else
+ efi_st_todo("CONFIG_FAT_WRITE is not set\n");
+#endif /* CONFIG_FAT_WRITE */
+
+ /* Close volume */
ret = root->close(root);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to close volume\n");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_config_tables
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This test checks the following service:
+ * InstallConfigurationTable.
+ */
+
+#include <efi_selftest.h>
+
+static const struct efi_system_table *sys_table;
+static struct efi_boot_services *boottime;
+
+static efi_guid_t table_guid =
+ EFI_GUID(0xff1c3f9e, 0x795b, 0x1529, 0xf1, 0x55,
+ 0x17, 0x2e, 0x51, 0x6b, 0x49, 0x75);
+
+/*
+ * Notification function, increments the notfication count if parameter
+ * context is provided.
+ *
+ * @event notified event
+ * @context pointer to the notification count
+ */
+static void EFIAPI notify(struct efi_event *event, void *context)
+{
+ unsigned int *count = context;
+
+ if (count)
+ ++*count;
+}
+
+/*
+ * Check crc32 of a table.
+ */
+static int check_table(const void *table)
+{
+ efi_status_t ret;
+ u32 crc32, res;
+ /* Casting from const to not const */
+ struct efi_table_hdr *hdr = (struct efi_table_hdr *)table;
+
+ crc32 = hdr->crc32;
+ /*
+ * Setting the crc32 of the 'const' table to zero is easier than
+ * copying
+ */
+ hdr->crc32 = 0;
+ ret = boottime->calculate_crc32(table, hdr->headersize, &res);
+ /* Reset table crc32 so it stays constant */
+ hdr->crc32 = crc32;
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("CalculateCrc32 failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (res != crc32) {
+ efi_st_error("Incorrect CRC32\n");
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ sys_table = systable;
+ boottime = systable->boottime;
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * A table is installed, updated, removed. The table entry and the
+ * triggering of events is checked.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ unsigned int counter = 0;
+ struct efi_event *event;
+ void *table;
+ const unsigned int tables[2];
+ efi_uintn_t i;
+ efi_uintn_t tabcnt;
+ efi_uintn_t table_count = sys_table->nr_tables;
+
+ ret = boottime->create_event_ex(0, TPL_NOTIFY,
+ notify, (void *)&counter,
+ &table_guid, &event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to create event\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Try to delete non-existent table */
+ ret = boottime->install_configuration_table(&table_guid, NULL);
+ if (ret != EFI_NOT_FOUND) {
+ efi_st_error("Failed to detect missing table\n");
+ return EFI_ST_FAILURE;
+ }
+ if (counter) {
+ efi_st_error("Notification function was called.\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check if the event was signaled */
+ ret = boottime->check_event(event);
+ if (ret == EFI_SUCCESS) {
+ efi_st_error("Event was signaled on EFI_NOT_FOUND\n");
+ return EFI_ST_FAILURE;
+ }
+ if (counter != 1) {
+ efi_st_error("Notification function was not called.\n");
+ return EFI_ST_FAILURE;
+ }
+ if (table_count != sys_table->nr_tables) {
+ efi_st_error("Incorrect table count %u, expected %u\n",
+ (unsigned int)sys_table->nr_tables,
+ (unsigned int)table_count);
+ return EFI_ST_FAILURE;
+ }
+
+ /* Install table */
+ ret = boottime->install_configuration_table(&table_guid,
+ (void *)&tables[0]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to install table\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check signaled state */
+ ret = boottime->check_event(event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Event was not signaled on insert\n");
+ return EFI_ST_FAILURE;
+ }
+ if (++table_count != sys_table->nr_tables) {
+ efi_st_error("Incorrect table count %u, expected %u\n",
+ (unsigned int)sys_table->nr_tables,
+ (unsigned int)table_count);
+ return EFI_ST_FAILURE;
+ }
+ table = NULL;
+ for (i = 0; i < sys_table->nr_tables; ++i) {
+ if (!efi_st_memcmp(&sys_table->tables[i].guid, &table_guid,
+ sizeof(efi_guid_t)))
+ table = sys_table->tables[i].table;
+ }
+ if (!table) {
+ efi_st_error("Installed table not found\n");
+ return EFI_ST_FAILURE;
+ }
+ if (table != &tables[0]) {
+ efi_st_error("Incorrect table address\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(sys_table) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Update table */
+ ret = boottime->install_configuration_table(&table_guid,
+ (void *)&tables[1]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to update table\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check signaled state */
+ ret = boottime->check_event(event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Event was not signaled on update\n");
+ return EFI_ST_FAILURE;
+ }
+ if (table_count != sys_table->nr_tables) {
+ efi_st_error("Incorrect table count %u, expected %u\n",
+ (unsigned int)sys_table->nr_tables,
+ (unsigned int)table_count);
+ return EFI_ST_FAILURE;
+ }
+ table = NULL;
+ tabcnt = 0;
+ for (i = 0; i < sys_table->nr_tables; ++i) {
+ if (!efi_st_memcmp(&sys_table->tables[i].guid, &table_guid,
+ sizeof(efi_guid_t))) {
+ table = sys_table->tables[i].table;
+ ++tabcnt;
+ }
+ }
+ if (!table) {
+ efi_st_error("Installed table not found\n");
+ return EFI_ST_FAILURE;
+ }
+ if (tabcnt > 1) {
+ efi_st_error("Duplicate table guid\n");
+ return EFI_ST_FAILURE;
+ }
+ if (table != &tables[1]) {
+ efi_st_error("Incorrect table address\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(sys_table) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Delete table */
+ ret = boottime->install_configuration_table(&table_guid, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to delete table\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check signaled state */
+ ret = boottime->check_event(event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Event was not signaled on delete\n");
+ return EFI_ST_FAILURE;
+ }
+ if (--table_count != sys_table->nr_tables) {
+ efi_st_error("Incorrect table count %u, expected %u\n",
+ (unsigned int)sys_table->nr_tables,
+ (unsigned int)table_count);
+ return EFI_ST_FAILURE;
+ }
+ table = NULL;
+ for (i = 0; i < sys_table->nr_tables; ++i) {
+ if (!efi_st_memcmp(&sys_table->tables[i].guid, &table_guid,
+ sizeof(efi_guid_t))) {
+ table = sys_table->tables[i].table;
+ }
+ }
+ if (table) {
+ efi_st_error("Wrong table deleted\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->close_event(event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close event\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(sys_table) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(configtables) = {
+ .name = "configuration tables",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
/*
* Print an unsigned 32bit value as decimal number to an u16 string
*
- * @value: value to be printed
- * @buf: pointer to buffer address
- * on return position of terminating zero word
+ * @value: value to be printed
+ * @prec: minimum number of digits to display
+ * @buf: pointer to buffer address
+ * on return position of terminating zero word
*/
-static void uint2dec(u32 value, u16 **buf)
+static void uint2dec(u32 value, int prec, u16 **buf)
{
u16 *pos = *buf;
int i;
for (i = 0; i < 10; ++i) {
/* Write current digit */
c = f >> 60;
- if (c || pos != *buf)
+ if (c || pos != *buf || 10 - i <= prec)
*pos++ = c + '0';
/* Eliminate current digit */
f &= 0xfffffffffffffff;
/*
* Print a signed 32bit value as decimal number to an u16 string
*
- * @value: value to be printed
- * @buf: pointer to buffer address
+ * @value: value to be printed
+ * @prec: minimum number of digits to display
+ * @buf: pointer to buffer address
* on return position of terminating zero word
*/
-static void int2dec(s32 value, u16 **buf)
+static void int2dec(s32 value, int prec, u16 **buf)
{
u32 u;
u16 *pos = *buf;
} else {
u = value;
}
- uint2dec(u, &pos);
+ uint2dec(u, prec, &pos);
*buf = pos;
}
u16 *pos = buf;
const char *s;
u16 *u;
+ int prec;
va_start(args, fmt);
break;
case '%':
++c;
+ /* Parse precision */
+ if (*c == '.') {
+ ++c;
+ prec = *c - '0';
+ ++c;
+ } else {
+ prec = 0;
+ }
switch (*c) {
case '\0':
--c;
break;
case 'd':
- int2dec(va_arg(args, s32), &pos);
+ int2dec(va_arg(args, s32), prec, &pos);
break;
case 'p':
++c;
*pos++ = *s;
break;
case 'u':
- uint2dec(va_arg(args, u32), &pos);
+ uint2dec(va_arg(args, u32), prec, &pos);
break;
default:
break;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_crc32
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This unit test checks the CalculateCrc32 bootservice and checks the
+ * headers of the system table, the boot services tablle, and the runtime
+ * services table before and after ExitBootServices().
+ */
+
+#include <efi_selftest.h>
+
+const struct efi_system_table *st;
+efi_status_t (EFIAPI *bs_crc32)(const void *data, efi_uintn_t data_size,
+ u32 *crc32);
+
+static int check_table(const void *table)
+{
+ efi_status_t ret;
+ u32 crc32, res;
+ /* Casting from const to not const */
+ struct efi_table_hdr *hdr = (struct efi_table_hdr *)table;
+
+ if (!hdr->signature) {
+ efi_st_error("Missing header signature\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!hdr->revision) {
+ efi_st_error("Missing header revision\n");
+ return EFI_ST_FAILURE;
+ }
+ if (hdr->headersize <= sizeof(struct efi_table_hdr)) {
+ efi_st_error("Incorrect headersize value\n");
+ return EFI_ST_FAILURE;
+ }
+ if (hdr->reserved) {
+ efi_st_error("Reserved header field is not zero\n");
+ return EFI_ST_FAILURE;
+ }
+
+ crc32 = hdr->crc32;
+ /*
+ * Setting the crc32 of the 'const' table to zero is easier than
+ * copying
+ */
+ hdr->crc32 = 0;
+ ret = bs_crc32(table, hdr->headersize, &res);
+ /* Reset table crc32 so it stays constant */
+ hdr->crc32 = crc32;
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("CalculateCrc32 failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (res != crc32) {
+ efi_st_error("Incorrect CRC32\n");
+ // return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Setup unit test.
+ *
+ * Check that CalculateCrc32 is working correctly.
+ * Check tables before ExitBootServices().
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+ u32 res;
+
+ st = systable;
+ bs_crc32 = systable->boottime->calculate_crc32;
+
+ /* Check that CalculateCrc32 is working */
+ ret = bs_crc32("U-Boot", 6, &res);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("CalculateCrc32 failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (res != 0x134b0db4) {
+ efi_st_error("Incorrect CRC32\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Check tables before ExitBootServices() */
+ if (check_table(st) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(st->boottime) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking boottime table\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(st->runtime) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking runtime table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test
+ *
+ * Check tables after ExitBootServices()
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ if (check_table(st) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(st->runtime) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking runtime table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * We cannot call SetVirtualAddressMap() and recheck the runtime
+ * table afterwards because this would invalidate the addresses of the
+ * unit tests.
+ */
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(crc32) = {
+ .name = "crc32",
+ .phase = EFI_SETUP_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_rtc
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * Test the real time clock runtime services.
+ */
+
+#include <efi_selftest.h>
+
+#define EFI_ST_NO_RTC "Could not read real time clock\n"
+
+static struct efi_runtime_services *runtime;
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ runtime = systable->runtime;
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Display current time.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ struct efi_time tm;
+
+ /* Display current time */
+ ret = runtime->get_time(&tm, NULL);
+ if (ret != EFI_SUCCESS) {
+#ifdef CONFIG_CMD_DATE
+ efi_st_error(EFI_ST_NO_RTC);
+ return EFI_ST_FAILURE;
+#else
+ efi_st_todo(EFI_ST_NO_RTC);
+ return EFI_ST_SUCCESS;
+#endif
+ } else {
+ efi_st_printf("Time according to real time clock: "
+ "%.4u-%.2u-%.2u %.2u:%.2u:%.2u\n",
+ tm.year, tm.month, tm.day,
+ tm.hour, tm.minute, tm.second);
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(rtc) = {
+ .name = "real time clock",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
}
#if defined(CONFIG_NR_DRAM_BANKS)
+
+static int get_next_memory_node(const void *blob, int startoffset)
+{
+ int mem = -1;
+
+ do {
+ mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
+ "device_type", "memory", 7);
+ } while (!fdtdec_get_is_enabled(blob, mem));
+
+ return mem;
+}
+
int fdtdec_setup_memory_banksize(void)
{
int bank, ret, mem, reg = 0;
struct fdt_resource res;
- mem = fdt_node_offset_by_prop_value(gd->fdt_blob, -1, "device_type",
- "memory", 7);
+ mem = get_next_memory_node(gd->fdt_blob, -1);
if (mem < 0) {
debug("%s: Missing /memory node\n", __func__);
return -EINVAL;
ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
if (ret == -FDT_ERR_NOTFOUND) {
reg = 0;
- mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
- "device_type",
- "memory", 7);
+ mem = get_next_memory_node(gd->fdt_blob, mem);
if (mem == -FDT_ERR_NOTFOUND)
break;
break;
}
- uuid_bin_to_str(addr, uuid, str_format);
+ if (addr)
+ uuid_bin_to_str(addr, uuid, str_format);
+ else
+ strcpy(uuid, "<NULL>");
return string(buf, end, uuid, field_width, precision, flags);
}
struct eth_device_priv *priv;
current = eth_get_dev();
- if (!current || !device_active(current))
+ if (!current || !eth_is_active(current))
return;
eth_get_ops(current)->stop(current);
/**********************************************************************/
-static int on_bootfile(const char *name, const char *value, enum env_op op,
- int flags)
-{
- if (flags & H_PROGRAMMATIC)
- return 0;
-
- switch (op) {
- case env_op_create:
- case env_op_overwrite:
- copy_filename(net_boot_file_name, value,
- sizeof(net_boot_file_name));
- break;
- default:
- break;
- }
-
- return 0;
-}
-U_BOOT_ENV_CALLBACK(bootfile, on_bootfile);
-
static int on_ipaddr(const char *name, const char *value, enum env_op op,
int flags)
{
const char *s = env_get("autoload");
if (s != NULL && strcmp(s, "NFS") == 0) {
+ if (net_check_prereq(NFS)) {
+/* We aren't expecting to get a serverip, so just accept the assigned IP */
+#ifdef CONFIG_BOOTP_SERVERIP
+ net_set_state(NETLOOP_SUCCESS);
+#else
+ printf("Cannot autoload with NFS\n");
+ net_set_state(NETLOOP_FAIL);
+#endif
+ return;
+ }
/*
* Use NFS to load the bootfile.
*/
net_set_state(NETLOOP_SUCCESS);
return;
}
+ if (net_check_prereq(TFTPGET)) {
+/* We aren't expecting to get a serverip, so just accept the assigned IP */
+#ifdef CONFIG_BOOTP_SERVERIP
+ net_set_state(NETLOOP_SUCCESS);
+#else
+ printf("Cannot autoload with TFTPGET\n");
+ net_set_state(NETLOOP_FAIL);
+#endif
+ return;
+ }
tftp_start(TFTPGET);
}
/* Fall through */
case TFTPGET:
case TFTPPUT:
- if (net_server_ip.s_addr == 0) {
+ if (net_server_ip.s_addr == 0 && !is_serverip_in_cmd()) {
puts("*** ERROR: `serverip' not set\n");
return 1;
}
void copy_filename(char *dst, const char *src, int size)
{
- if (*src && (*src == '"')) {
+ if (src && *src && (*src == '"')) {
++src;
--size;
}
- while ((--size > 0) && *src && (*src != '"'))
+ while ((--size > 0) && src && *src && (*src != '"'))
*dst++ = *src++;
*dst = '\0';
}
+int is_serverip_in_cmd(void)
+{
+ return !!strchr(net_boot_file_name, ':');
+}
+
+int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len)
+{
+ char *colon;
+
+ if (net_boot_file_name[0] == '\0')
+ return 0;
+
+ colon = strchr(net_boot_file_name, ':');
+ if (colon) {
+ if (ipaddr)
+ *ipaddr = string_to_ip(net_boot_file_name);
+ strncpy(filename, colon + 1, max_len);
+ } else {
+ strncpy(filename, net_boot_file_name, max_len);
+ }
+ filename[max_len - 1] = '\0';
+
+ return 1;
+}
+
#if defined(CONFIG_CMD_NFS) || \
defined(CONFIG_CMD_SNTP) || \
defined(CONFIG_CMD_DNS)
switch (ntohl(rpc_pkt.u.reply.data[0])) {
/* Minimal supported NFS version */
case 3:
- debug("*** Waring: NFS version not supported: Requested: V%d, accepted: min V%d - max V%d\n",
+ debug("*** Warning: NFS version not supported: Requested: V%d, accepted: min V%d - max V%d\n",
(supported_nfs_versions & NFSV2_FLAG) ?
2 : 3,
ntohl(rpc_pkt.u.reply.data[0]),
if (nfs_path == NULL) {
net_set_state(NETLOOP_FAIL);
- debug("*** ERROR: Fail allocate memory\n");
+ printf("*** ERROR: Fail allocate memory\n");
return;
}
- if (net_boot_file_name[0] == '\0') {
+ if (!net_parse_bootfile(&nfs_server_ip, nfs_path,
+ sizeof(nfs_path_buff))) {
sprintf(nfs_path, "/nfsroot/%02X%02X%02X%02X.img",
net_ip.s_addr & 0xFF,
(net_ip.s_addr >> 8) & 0xFF,
(net_ip.s_addr >> 16) & 0xFF,
(net_ip.s_addr >> 24) & 0xFF);
- debug("*** Warning: no boot file name; using '%s'\n",
- nfs_path);
- } else {
- char *p = net_boot_file_name;
-
- p = strchr(p, ':');
-
- if (p != NULL) {
- nfs_server_ip = string_to_ip(net_boot_file_name);
- ++p;
- strcpy(nfs_path, p);
- } else {
- strcpy(nfs_path, net_boot_file_name);
- }
+ printf("*** Warning: no boot file name; using '%s'\n",
+ nfs_path);
}
nfs_filename = basename(nfs_path);
nfs_path = dirname(nfs_path);
- debug("Using %s device\n", eth_get_name());
+ printf("Using %s device\n", eth_get_name());
- debug("File transfer via NFS from server %pI4; our IP address is %pI4",
- &nfs_server_ip, &net_ip);
+ printf("File transfer via NFS from server %pI4; our IP address is %pI4",
+ &nfs_server_ip, &net_ip);
/* Check if we need to send across this subnet */
if (net_gateway.s_addr && net_netmask.s_addr) {
struct in_addr server_net;
our_net.s_addr = net_ip.s_addr & net_netmask.s_addr;
- server_net.s_addr = net_server_ip.s_addr & net_netmask.s_addr;
+ server_net.s_addr = nfs_server_ip.s_addr & net_netmask.s_addr;
if (our_net.s_addr != server_net.s_addr)
- debug("; sending through gateway %pI4",
- &net_gateway);
+ printf("; sending through gateway %pI4",
+ &net_gateway);
}
- debug("\nFilename '%s/%s'.", nfs_path, nfs_filename);
+ printf("\nFilename '%s/%s'.", nfs_path, nfs_filename);
if (net_boot_file_expected_size_in_blocks) {
- debug(" Size is 0x%x Bytes = ",
- net_boot_file_expected_size_in_blocks << 9);
+ printf(" Size is 0x%x Bytes = ",
+ net_boot_file_expected_size_in_blocks << 9);
print_size(net_boot_file_expected_size_in_blocks << 9, "");
}
- debug("\nLoad address: 0x%lx\nLoading: *\b", load_addr);
+ printf("\nLoad address: 0x%lx\nLoading: *\b", load_addr);
net_set_timeout_handler(nfs_timeout, nfs_timeout_handler);
net_set_udp_handler(nfs_handler);
* case, most NFS servers are optimized for a power of 2.
*/
#define NFS_READ_SIZE 1024 /* biggest power of two that fits Ether frame */
+#define NFS_MAX_ATTRS 26
/* Values for Accept State flag on RPC answers (See: rfc1831) */
enum rpc_accept_stat {
struct rpc_t {
union {
- uint8_t data[2048];
+ uint8_t data[NFS_READ_SIZE + (6 + NFS_MAX_ATTRS) *
+ sizeof(uint32_t)];
struct {
uint32_t id;
uint32_t type;
uint32_t verifier;
uint32_t v2;
uint32_t astatus;
- uint32_t data[NFS_READ_SIZE];
+ uint32_t data[NFS_READ_SIZE / sizeof(uint32_t) +
+ NFS_MAX_ATTRS];
} reply;
} u;
} __attribute__((packed));
tftp_block_size_option, timeout_ms);
tftp_remote_ip = net_server_ip;
- if (net_boot_file_name[0] == '\0') {
+ if (!net_parse_bootfile(&tftp_remote_ip, tftp_filename, MAX_LEN)) {
sprintf(default_filename, "%02X%02X%02X%02X.img",
net_ip.s_addr & 0xFF,
(net_ip.s_addr >> 8) & 0xFF,
printf("*** Warning: no boot file name; using '%s'\n",
tftp_filename);
- } else {
- char *p = strchr(net_boot_file_name, ':');
-
- if (p == NULL) {
- strncpy(tftp_filename, net_boot_file_name, MAX_LEN);
- tftp_filename[MAX_LEN - 1] = 0;
- } else {
- tftp_remote_ip = string_to_ip(net_boot_file_name);
- strncpy(tftp_filename, p + 1, MAX_LEN);
- tftp_filename[MAX_LEN - 1] = 0;
- }
}
printf("Using %s device\n", eth_get_name());
# Generated files
#
bin2c
-docproc
# scripts contains sources for various helper programs used throughout
# the kernel for the build process.
# ---------------------------------------------------------------------------
-# docproc: Used in Documentation/DocBook
hostprogs-$(CONFIG_BUILD_BIN2C) += bin2c
always := $(hostprogs-y)
-# The following hostprogs-y programs are only build on demand
-hostprogs-y += docproc
-
-# These targets are used internally to avoid "is up to date" messages
-PHONY += build_docproc
-build_docproc: $(obj)/docproc
- @:
-
# Let clean descend into subdirs
subdir- += basic kconfig
subdir-$(CONFIG_DTC) += dtc
CONFIG_ARMADA100_FEC
CONFIG_ARMADA168
CONFIG_ARMADA_39X
+CONFIG_ARMV7_PSCI_0_2
CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE
CONFIG_SUNXI_AHCI
CONFIG_SUNXI_GPIO
CONFIG_SUNXI_MAX_FB_SIZE
-CONFIG_SUNXI_USB_PHYS
CONFIG_SUPERH_ON_CHIP_R8A66597
CONFIG_SUPPORT_EMMC_BOOT
CONFIG_SUVD3
+++ /dev/null
-/*
- * docproc is a simple preprocessor for the template files
- * used as placeholders for the kernel internal documentation.
- * docproc is used for documentation-frontend and
- * dependency-generator.
- * The two usages have in common that they require
- * some knowledge of the .tmpl syntax, therefore they
- * are kept together.
- *
- * documentation-frontend
- * Scans the template file and call kernel-doc for
- * all occurrences of ![EIF]file
- * Beforehand each referenced file is scanned for
- * any symbols that are exported via these macros:
- * EXPORT_SYMBOL(), EXPORT_SYMBOL_GPL(), &
- * EXPORT_SYMBOL_GPL_FUTURE()
- * This is used to create proper -function and
- * -nofunction arguments in calls to kernel-doc.
- * Usage: docproc doc file.tmpl
- *
- * dependency-generator:
- * Scans the template file and list all files
- * referenced in a format recognized by make.
- * Usage: docproc depend file.tmpl
- * Writes dependency information to stdout
- * in the following format:
- * file.tmpl src.c src2.c
- * The filenames are obtained from the following constructs:
- * !Efilename
- * !Ifilename
- * !Dfilename
- * !Ffilename
- * !Pfilename
- *
- */
-
-#define _GNU_SOURCE
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-#include <unistd.h>
-#include <limits.h>
-#include <errno.h>
-#include <sys/types.h>
-#include <sys/wait.h>
-
-/* exitstatus is used to keep track of any failing calls to kernel-doc,
- * but execution continues. */
-int exitstatus = 0;
-
-typedef void DFL(char *);
-DFL *defaultline;
-
-typedef void FILEONLY(char * file);
-FILEONLY *internalfunctions;
-FILEONLY *externalfunctions;
-FILEONLY *symbolsonly;
-FILEONLY *findall;
-
-typedef void FILELINE(char * file, char * line);
-FILELINE * singlefunctions;
-FILELINE * entity_system;
-FILELINE * docsection;
-
-#define MAXLINESZ 2048
-#define MAXFILES 250
-#define KERNELDOCPATH "scripts/"
-#define KERNELDOC "kernel-doc"
-#define DOCBOOK "-docbook"
-#define LIST "-list"
-#define FUNCTION "-function"
-#define NOFUNCTION "-nofunction"
-#define NODOCSECTIONS "-no-doc-sections"
-#define SHOWNOTFOUND "-show-not-found"
-
-static char *srctree, *kernsrctree;
-
-static char **all_list = NULL;
-static int all_list_len = 0;
-
-static void consume_symbol(const char *sym)
-{
- int i;
-
- for (i = 0; i < all_list_len; i++) {
- if (!all_list[i])
- continue;
- if (strcmp(sym, all_list[i]))
- continue;
- all_list[i] = NULL;
- break;
- }
-}
-
-static void usage (void)
-{
- fprintf(stderr, "Usage: docproc {doc|depend} file\n");
- fprintf(stderr, "Input is read from file.tmpl. Output is sent to stdout\n");
- fprintf(stderr, "doc: frontend when generating kernel documentation\n");
- fprintf(stderr, "depend: generate list of files referenced within file\n");
- fprintf(stderr, "Environment variable SRCTREE: absolute path to sources.\n");
- fprintf(stderr, " KBUILD_SRC: absolute path to kernel source tree.\n");
-}
-
-/*
- * Execute kernel-doc with parameters given in svec
- */
-static void exec_kernel_doc(char **svec)
-{
- pid_t pid;
- int ret;
- char real_filename[PATH_MAX + 1];
- /* Make sure output generated so far are flushed */
- fflush(stdout);
- switch (pid=fork()) {
- case -1:
- perror("fork");
- exit(1);
- case 0:
- memset(real_filename, 0, sizeof(real_filename));
- strncat(real_filename, kernsrctree, PATH_MAX);
- strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
- PATH_MAX - strlen(real_filename));
- execvp(real_filename, svec);
- fprintf(stderr, "exec ");
- perror(real_filename);
- exit(1);
- default:
- waitpid(pid, &ret ,0);
- }
- if (WIFEXITED(ret))
- exitstatus |= WEXITSTATUS(ret);
- else
- exitstatus = 0xff;
-}
-
-/* Types used to create list of all exported symbols in a number of files */
-struct symbols
-{
- char *name;
-};
-
-struct symfile
-{
- char *filename;
- struct symbols *symbollist;
- int symbolcnt;
-};
-
-struct symfile symfilelist[MAXFILES];
-int symfilecnt = 0;
-
-static void add_new_symbol(struct symfile *sym, char * symname)
-{
- sym->symbollist =
- realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *));
- sym->symbollist[sym->symbolcnt++].name = strdup(symname);
-}
-
-/* Add a filename to the list */
-static struct symfile * add_new_file(char * filename)
-{
- symfilelist[symfilecnt++].filename = strdup(filename);
- return &symfilelist[symfilecnt - 1];
-}
-
-/* Check if file already are present in the list */
-static struct symfile * filename_exist(char * filename)
-{
- int i;
- for (i=0; i < symfilecnt; i++)
- if (strcmp(symfilelist[i].filename, filename) == 0)
- return &symfilelist[i];
- return NULL;
-}
-
-/*
- * List all files referenced within the template file.
- * Files are separated by tabs.
- */
-static void adddep(char * file) { printf("\t%s", file); }
-static void adddep2(char * file, char * line) { line = line; adddep(file); }
-static void noaction(char * line) { line = line; }
-static void noaction2(char * file, char * line) { file = file; line = line; }
-
-/* Echo the line without further action */
-static void printline(char * line) { printf("%s", line); }
-
-/*
- * Find all symbols in filename that are exported with EXPORT_SYMBOL &
- * EXPORT_SYMBOL_GPL (& EXPORT_SYMBOL_GPL_FUTURE implicitly).
- * All symbols located are stored in symfilelist.
- */
-static void find_export_symbols(char * filename)
-{
- FILE * fp;
- struct symfile *sym;
- char line[MAXLINESZ];
- if (filename_exist(filename) == NULL) {
- char real_filename[PATH_MAX + 1];
- memset(real_filename, 0, sizeof(real_filename));
- strncat(real_filename, srctree, PATH_MAX);
- strncat(real_filename, "/", PATH_MAX - strlen(real_filename));
- strncat(real_filename, filename,
- PATH_MAX - strlen(real_filename));
- sym = add_new_file(filename);
- fp = fopen(real_filename, "r");
- if (fp == NULL) {
- fprintf(stderr, "docproc: ");
- perror(real_filename);
- exit(1);
- }
- while (fgets(line, MAXLINESZ, fp)) {
- char *p;
- char *e;
- if (((p = strstr(line, "EXPORT_SYMBOL_GPL")) != NULL) ||
- ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) {
- /* Skip EXPORT_SYMBOL{_GPL} */
- while (isalnum(*p) || *p == '_')
- p++;
- /* Remove parentheses & additional whitespace */
- while (isspace(*p))
- p++;
- if (*p != '(')
- continue; /* Syntax error? */
- else
- p++;
- while (isspace(*p))
- p++;
- e = p;
- while (isalnum(*e) || *e == '_')
- e++;
- *e = '\0';
- add_new_symbol(sym, p);
- }
- }
- fclose(fp);
- }
-}
-
-/*
- * Document all external or internal functions in a file.
- * Call kernel-doc with following parameters:
- * kernel-doc -docbook -nofunction function_name1 filename
- * Function names are obtained from all the src files
- * by find_export_symbols.
- * intfunc uses -nofunction
- * extfunc uses -function
- */
-static void docfunctions(char * filename, char * type)
-{
- int i,j;
- int symcnt = 0;
- int idx = 0;
- char **vec;
-
- for (i=0; i <= symfilecnt; i++)
- symcnt += symfilelist[i].symbolcnt;
- vec = malloc((2 + 2 * symcnt + 3) * sizeof(char *));
- if (vec == NULL) {
- perror("docproc: ");
- exit(1);
- }
- vec[idx++] = KERNELDOC;
- vec[idx++] = DOCBOOK;
- vec[idx++] = NODOCSECTIONS;
- for (i=0; i < symfilecnt; i++) {
- struct symfile * sym = &symfilelist[i];
- for (j=0; j < sym->symbolcnt; j++) {
- vec[idx++] = type;
- consume_symbol(sym->symbollist[j].name);
- vec[idx++] = sym->symbollist[j].name;
- }
- }
- vec[idx++] = filename;
- vec[idx] = NULL;
- printf("<!-- %s -->\n", filename);
- exec_kernel_doc(vec);
- fflush(stdout);
- free(vec);
-}
-static void intfunc(char * filename) { docfunctions(filename, NOFUNCTION); }
-static void extfunc(char * filename) { docfunctions(filename, FUNCTION); }
-
-/*
- * Document specific function(s) in a file.
- * Call kernel-doc with the following parameters:
- * kernel-doc -docbook -function function1 [-function function2]
- */
-static void singfunc(char * filename, char * line)
-{
- char *vec[200]; /* Enough for specific functions */
- int i, idx = 0;
- int startofsym = 1;
- vec[idx++] = KERNELDOC;
- vec[idx++] = DOCBOOK;
- vec[idx++] = SHOWNOTFOUND;
-
- /* Split line up in individual parameters preceded by FUNCTION */
- for (i=0; line[i]; i++) {
- if (isspace(line[i])) {
- line[i] = '\0';
- startofsym = 1;
- continue;
- }
- if (startofsym) {
- startofsym = 0;
- vec[idx++] = FUNCTION;
- vec[idx++] = &line[i];
- }
- }
- for (i = 0; i < idx; i++) {
- if (strcmp(vec[i], FUNCTION))
- continue;
- consume_symbol(vec[i + 1]);
- }
- vec[idx++] = filename;
- vec[idx] = NULL;
- exec_kernel_doc(vec);
-}
-
-/*
- * Insert specific documentation section from a file.
- * Call kernel-doc with the following parameters:
- * kernel-doc -docbook -function "doc section" filename
- */
-static void docsect(char *filename, char *line)
-{
- /* kerneldoc -docbook -show-not-found -function "section" file NULL */
- char *vec[7];
- char *s;
-
- for (s = line; *s; s++)
- if (*s == '\n')
- *s = '\0';
-
- if (asprintf(&s, "DOC: %s", line) < 0) {
- perror("asprintf");
- exit(1);
- }
- consume_symbol(s);
- free(s);
-
- vec[0] = KERNELDOC;
- vec[1] = DOCBOOK;
- vec[2] = SHOWNOTFOUND;
- vec[3] = FUNCTION;
- vec[4] = line;
- vec[5] = filename;
- vec[6] = NULL;
- exec_kernel_doc(vec);
-}
-
-static void find_all_symbols(char *filename)
-{
- char *vec[4]; /* kerneldoc -list file NULL */
- pid_t pid;
- int ret, i, count, start;
- char real_filename[PATH_MAX + 1];
- int pipefd[2];
- char *data, *str;
- size_t data_len = 0;
-
- vec[0] = KERNELDOC;
- vec[1] = LIST;
- vec[2] = filename;
- vec[3] = NULL;
-
- if (pipe(pipefd)) {
- perror("pipe");
- exit(1);
- }
-
- switch (pid=fork()) {
- case -1:
- perror("fork");
- exit(1);
- case 0:
- close(pipefd[0]);
- dup2(pipefd[1], 1);
- memset(real_filename, 0, sizeof(real_filename));
- strncat(real_filename, kernsrctree, PATH_MAX);
- strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
- PATH_MAX - strlen(real_filename));
- execvp(real_filename, vec);
- fprintf(stderr, "exec ");
- perror(real_filename);
- exit(1);
- default:
- close(pipefd[1]);
- data = malloc(4096);
- do {
- while ((ret = read(pipefd[0],
- data + data_len,
- 4096)) > 0) {
- data_len += ret;
- data = realloc(data, data_len + 4096);
- }
- } while (ret == -EAGAIN);
- if (ret != 0) {
- perror("read");
- exit(1);
- }
- waitpid(pid, &ret ,0);
- }
- if (WIFEXITED(ret))
- exitstatus |= WEXITSTATUS(ret);
- else
- exitstatus = 0xff;
-
- count = 0;
- /* poor man's strtok, but with counting */
- for (i = 0; i < data_len; i++) {
- if (data[i] == '\n') {
- count++;
- data[i] = '\0';
- }
- }
- start = all_list_len;
- all_list_len += count;
- all_list = realloc(all_list, sizeof(char *) * all_list_len);
- str = data;
- for (i = 0; i < data_len && start != all_list_len; i++) {
- if (data[i] == '\0') {
- all_list[start] = str;
- str = data + i + 1;
- start++;
- }
- }
-}
-
-/*
- * Parse file, calling action specific functions for:
- * 1) Lines containing !E
- * 2) Lines containing !I
- * 3) Lines containing !D
- * 4) Lines containing !F
- * 5) Lines containing !P
- * 6) Lines containing !C
- * 7) Default lines - lines not matching the above
- */
-static void parse_file(FILE *infile)
-{
- char line[MAXLINESZ];
- char * s;
- while (fgets(line, MAXLINESZ, infile)) {
- if (line[0] == '!') {
- s = line + 2;
- switch (line[1]) {
- case 'E':
- while (*s && !isspace(*s)) s++;
- *s = '\0';
- externalfunctions(line+2);
- break;
- case 'I':
- while (*s && !isspace(*s)) s++;
- *s = '\0';
- internalfunctions(line+2);
- break;
- case 'D':
- while (*s && !isspace(*s)) s++;
- *s = '\0';
- symbolsonly(line+2);
- break;
- case 'F':
- /* filename */
- while (*s && !isspace(*s)) s++;
- *s++ = '\0';
- /* function names */
- while (isspace(*s))
- s++;
- singlefunctions(line +2, s);
- break;
- case 'P':
- /* filename */
- while (*s && !isspace(*s)) s++;
- *s++ = '\0';
- /* DOC: section name */
- while (isspace(*s))
- s++;
- docsection(line + 2, s);
- break;
- case 'C':
- while (*s && !isspace(*s)) s++;
- *s = '\0';
- if (findall)
- findall(line+2);
- break;
- default:
- defaultline(line);
- }
- } else {
- defaultline(line);
- }
- }
- fflush(stdout);
-}
-
-
-int main(int argc, char *argv[])
-{
- FILE * infile;
- int i;
-
- srctree = getenv("SRCTREE");
- if (!srctree)
- srctree = getcwd(NULL, 0);
- kernsrctree = getenv("KBUILD_SRC");
- if (!kernsrctree || !*kernsrctree)
- kernsrctree = srctree;
- if (argc != 3) {
- usage();
- exit(1);
- }
- /* Open file, exit on error */
- infile = fopen(argv[2], "r");
- if (infile == NULL) {
- fprintf(stderr, "docproc: ");
- perror(argv[2]);
- exit(2);
- }
-
- if (strcmp("doc", argv[1]) == 0) {
- /* Need to do this in two passes.
- * First pass is used to collect all symbols exported
- * in the various files;
- * Second pass generate the documentation.
- * This is required because some functions are declared
- * and exported in different files :-((
- */
- /* Collect symbols */
- defaultline = noaction;
- internalfunctions = find_export_symbols;
- externalfunctions = find_export_symbols;
- symbolsonly = find_export_symbols;
- singlefunctions = noaction2;
- docsection = noaction2;
- findall = find_all_symbols;
- parse_file(infile);
-
- /* Rewind to start from beginning of file again */
- fseek(infile, 0, SEEK_SET);
- defaultline = printline;
- internalfunctions = intfunc;
- externalfunctions = extfunc;
- symbolsonly = printline;
- singlefunctions = singfunc;
- docsection = docsect;
- findall = NULL;
-
- parse_file(infile);
-
- for (i = 0; i < all_list_len; i++) {
- if (!all_list[i])
- continue;
- fprintf(stderr, "Warning: didn't use docs for %s\n",
- all_list[i]);
- }
- } else if (strcmp("depend", argv[1]) == 0) {
- /* Create first part of dependency chain
- * file.tmpl */
- printf("%s\t", argv[2]);
- defaultline = noaction;
- internalfunctions = adddep;
- externalfunctions = adddep;
- symbolsonly = adddep;
- singlefunctions = adddep2;
- docsection = adddep2;
- findall = adddep;
- parse_file(infile);
- printf("\n");
- } else {
- fprintf(stderr, "Unknown option: %s\n", argv[1]);
- exit(1);
- }
- fclose(infile);
- fflush(stdout);
- return exitstatus;
-}
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
&dev_test));
ut_assertok(sandbox_clk_test_get(dev_test));
+ ut_assertok(sandbox_clk_test_valid(dev_test));
ut_asserteq(1234,
sandbox_clk_test_get_rate(dev_test,
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "power-domain-test",
&dev_test));
+ ut_asserteq(1, sandbox_power_domain_query(dev_power_domain,
+ TEST_POWER_DOMAIN));
ut_assertok(sandbox_power_domain_test_get(dev_test));
ut_assertok(sandbox_power_domain_test_on(dev_test));
# fs-test.fs.ext4.out: Summary: PASS: 24 FAIL: 0
# FAT16 tests:
# fs-test.sb.fat16.out: Summary: PASS: 24 FAIL: 0
-# fs-test.fat16.out: Summary: PASS: 21 FAIL: 3
-# fs-test.fs.fat16.out: Summary: PASS: 21 FAIL: 3
+# fs-test.fat16.out: Summary: PASS: 20 FAIL: 4
+# fs-test.fs.fat16.out: Summary: PASS: 20 FAIL: 4
# FAT32 tests:
# fs-test.sb.fat32.out: Summary: PASS: 24 FAIL: 0
-# fs-test.fat32.out: Summary: PASS: 21 FAIL: 3
-# fs-test.fs.fat32.out: Summary: PASS: 21 FAIL: 3
-# Total Summary: TOTAL PASS: 204 TOTAL FAIL: 12
+# fs-test.fat32.out: Summary: PASS: 20 FAIL: 4
+# fs-test.fs.fat32.out: Summary: PASS: 20 FAIL: 4
+# Total Summary: TOTAL PASS: 200 TOTAL FAIL: 16
# pre-requisite binaries list.
PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir"
twice will spawn an error used to detect that the TPM was not reset and no
initialization code should be run.
"""
- output = u_boot_console.run_command('tpm init')
+ output = u_boot_console.run_command('tpm2 init')
if force or not 'Error' in output:
u_boot_console.run_command('echo --- start of init ---')
- u_boot_console.run_command('tpm startup TPM2_SU_CLEAR')
- u_boot_console.run_command('tpm self_test full')
- u_boot_console.run_command('tpm clear TPM2_RH_LOCKOUT')
+ u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
+ u_boot_console.run_command('tpm2 self_test full')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT')
output = u_boot_console.run_command('echo $?')
if not output.endswith('0'):
- u_boot_console.run_command('tpm clear TPM2_RH_PLATFORM')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
u_boot_console.run_command('echo --- end of init ---')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
def test_tpm2_init(u_boot_console):
"""Init the software stack to use TPMv2 commands."""
- u_boot_console.run_command('tpm init')
+ u_boot_console.run_command('tpm2 init')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
Initiate the TPM internal state machine.
"""
- u_boot_console.run_command('tpm startup TPM2_SU_CLEAR')
+ u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
Ask the TPM to perform all self tests to also enable full capabilities.
"""
- u_boot_console.run_command('tpm self_test full')
+ u_boot_console.run_command('tpm2 self_test full')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
to enter a fully operational state.
"""
- u_boot_console.run_command('tpm self_test continue')
+ u_boot_console.run_command('tpm2 self_test continue')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
PLATFORM hierarchies are also available.
"""
- u_boot_console.run_command('tpm clear TPM2_RH_LOCKOUT')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
- u_boot_console.run_command('tpm clear TPM2_RH_PLATFORM')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
force_init(u_boot_console)
- u_boot_console.run_command('tpm change_auth TPM2_RH_LOCKOUT unicorn')
+ u_boot_console.run_command('tpm2 change_auth TPM2_RH_LOCKOUT unicorn')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
- u_boot_console.run_command('tpm clear TPM2_RH_LOCKOUT unicorn')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT unicorn')
output = u_boot_console.run_command('echo $?')
- u_boot_console.run_command('tpm clear TPM2_RH_PLATFORM')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
- read_cap = u_boot_console.run_command('tpm get_capability 0x6 0x20e 0x200 1') #0x%x 1' % ram)
+ read_cap = u_boot_console.run_command('tpm2 get_capability 0x6 0x20e 0x200 1') #0x%x 1' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
assert 'Property 0x0000020e: 0x00000000' in read_cap
ram = u_boot_utils.find_ram_base(u_boot_console)
# Set the DAM parameters to known values
- u_boot_console.run_command('tpm dam_parameters 3 10 0')
+ u_boot_console.run_command('tpm2 dam_parameters 3 10 0')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
# Check the values have been saved
- read_cap = u_boot_console.run_command('tpm get_capability 0x6 0x20f 0x%x 3' % ram)
+ read_cap = u_boot_console.run_command('tpm2 get_capability 0x6 0x20f 0x%x 3' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
assert 'Property 0x0000020f: 0x00000003' in read_cap
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
- read_pcr = u_boot_console.run_command('tpm pcr_read 0 0x%x' % ram)
+ read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
- u_boot_console.run_command('tpm pcr_extend 0 0x%x' % ram)
+ u_boot_console.run_command('tpm2 pcr_extend 0 0x%x' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
- read_pcr = u_boot_console.run_command('tpm pcr_read 0 0x%x' % ram)
+ read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
assert 'f5 a5 fd 42 d1 6a 20 30 27 98 ef 6e d3 09 97 9b' in read_pcr
filename = "spl/sunxi-spl.bin";
};
u-boot {
- pos = <CONFIG_SPL_PAD_TO>;
+ offset = <CONFIG_SPL_PAD_TO>;
};
};
Entries are normally placed into the image sequentially, one after the other.
The image size is the total size of all entries. As you can see, you can
-specify the start position of an entry using the 'pos' property.
+specify the start offset of an entry using the 'offset' property.
Note that due to a device tree requirement, all entries must have a unique
name. If you want to put the same binary in the image multiple times, you can
The attributes supported for entries are described below.
-pos:
- This sets the position of an entry within the image. The first byte
- of the image is normally at position 0. If 'pos' is not provided,
- binman sets it to the end of the previous region, or the start of
- the image's entry area (normally 0) if there is no previous region.
+offset:
+ This sets the offset of an entry within the image or section containing
+ it. The first byte of the image is normally at offset 0. If 'offset' is
+ not provided, binman sets it to the end of the previous region, or the
+ start of the image's entry area (normally 0) if there is no previous
+ region.
align:
- This sets the alignment of the entry. The entry position is adjusted
+ This sets the alignment of the entry. The entry offset is adjusted
so that the entry starts on an aligned boundary within the image. For
example 'align = <16>' means that the entry will start on a 16-byte
boundary. Alignment shold be a power of 2. If 'align' is not
possible to use any name, and then add (for example) 'type = "u-boot"'
to specify the type.
-pos-unset:
- Indicates that the position of this entry should not be set by placing
+offset-unset:
+ Indicates that the offset of this entry should not be set by placing
it immediately after the entry before. Instead, is set by another
entry which knows where this entry should go. When this boolean
property is present, binman will give an error if another entry does
- not set the position (with the GetPositions() method).
+ not set the offset (with the GetOffsets() method).
+
+image-pos:
+ This cannot be set on entry (or at least it is ignored if it is), but
+ with the -u option, binman will set it to the absolute image position
+ for each entry. This makes it easy to find out exactly where the entry
+ ended up in the image, regardless of parent sections, etc.
The attributes supported for images are described below. Several are similar
pad-before:
This sets the padding before the image entries. The first entry will
- be positionad after the padding. This defaults to 0.
+ be positioned after the padding. This defaults to 0.
pad-after:
This sets the padding after the image entries. The padding will be
filename:
This specifies the image filename. It defaults to 'image.bin'.
-sort-by-pos:
+sort-by-offset:
This causes binman to reorder the entries as needed to make sure they
are in increasing positional order. This can be used when your entry
order may not match the positional order. A common situation is where
- the 'pos' properties are set by CONFIG options, so their ordering is
+ the 'offset' properties are set by CONFIG options, so their ordering is
not known a priori.
This is a boolean property so needs no value. To enable it, add a
- line 'sort-by-pos;' to your description.
+ line 'sort-by-offset;' to your description.
multiple-images:
Normally only a single image is generated. To create more than one
};
end-at-4gb:
- For x86 machines the ROM positions start just before 4GB and extend
+ For x86 machines the ROM offsets start just before 4GB and extend
up so that the image finished at the 4GB boundary. This boolean
option can be enabled to support this. The image size must be
provided so that binman knows when the image should start. For an
- 8MB ROM, the position of the first entry would be 0xfff80000 with
+ 8MB ROM, the offset of the first entry would be 0xfff80000 with
this option, instead of 0 without this option.
distinguish binaries with otherwise identical names.
+Entry Documentation
+-------------------
+
+For details on the various entry types supported by binman and how to use them,
+see README.entries. This is generated from the source code using:
+
+ binman -E >tools/binman/README.entries
+
+
Special properties
------------------
Image creation proceeds in the following order, for each entry in the image.
1. AddMissingProperties() - binman can add calculated values to the device
-tree as part of its processing, for example the position and size of each
+tree as part of its processing, for example the offset and size of each
entry. This method adds any properties associated with this, expanding the
device tree as needed. These properties can have placeholder values which are
set later by SetCalculatedProperties(). By that stage the size of sections
retry calling the functions a few times if False is returned, allowing
dependencies between the contents of different entries.
-4. GetEntryPositions() - calls Entry.GetPositions() for each entry. This can
+4. GetEntryOffsets() - calls Entry.GetOffsets() for each entry. This can
return a dict containing entries that need updating. The key should be the
-entry name and the value is a tuple (pos, size). This allows an entry to
-provide the position and size for other entries. The default implementation
-of GetEntryPositions() returns {}.
+entry name and the value is a tuple (offset, size). This allows an entry to
+provide the offset and size for other entries. The default implementation
+of GetEntryOffsets() returns {}.
-5. PackEntries() - calls Entry.Pack() which figures out the position and
-size of an entry. The 'current' image position is passed in, and the function
-returns the position immediately after the entry being packed. The default
+5. PackEntries() - calls Entry.Pack() which figures out the offset and
+size of an entry. The 'current' image offset is passed in, and the function
+returns the offset immediately after the entry being packed. The default
implementation of Pack() is usually sufficient.
6. CheckSize() - checks that the contents of all the entries fits within
outside the image.
8. SetCalculatedProperties() - update any calculated properties in the device
-tree. This sets the correct 'pos' and 'size' vaues, for example.
+tree. This sets the correct 'offset' and 'size' vaues, for example.
9. ProcessEntryContents() - this calls Entry.ProcessContents() on each entry.
The default implementatoin does nothing. This can be overriden to adjust the
contents of an entry in some way. For example, it would be possible to create
an entry containing a hash of the contents of some other entries. At this
-stage the position and size of entries should not be adjusted.
+stage the offset and size of entries should not be adjusted.
10. WriteSymbols() - write the value of symbols into the U-Boot SPL binary.
-See 'Access to binman entry positions at run time' below for a description of
+See 'Access to binman entry offsets at run time' below for a description of
what happens in this stage.
11. BuildImage() - builds the image and writes it to a file. This is the final
# u_boot_dtsi_options_debug = $(u_boot_dtsi_options_raw)
-Access to binman entry positions at run time
---------------------------------------------
+Access to binman entry offsets at run time (symbols)
+----------------------------------------------------
Binman assembles images and determines where each entry is placed in the image.
This information may be useful to U-Boot at run time. For example, in SPL it
Binman allows you to declare symbols in the SPL image which are filled in
with their correct values during the build. For example:
- binman_sym_declare(ulong, u_boot_any, pos);
+ binman_sym_declare(ulong, u_boot_any, offset);
-declares a ulong value which will be assigned to the position of any U-Boot
+declares a ulong value which will be assigned to the offset of any U-Boot
image (u-boot.bin, u-boot.img, u-boot-nodtb.bin) that is present in the image.
You can access this value with something like:
- ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
+ ulong u_boot_offset = binman_sym(ulong, u_boot_any, offset);
-Thus u_boot_pos will be set to the position of U-Boot in memory, assuming that
+Thus u_boot_offset will be set to the offset of U-Boot in memory, assuming that
the whole image has been loaded, or is available in flash. You can then jump to
that address to start U-Boot.
to fill in such symbols in U-Boot proper, as well.
+Access to binman entry offsets at run time (fdt)
+------------------------------------------------
+
+Binman can update the U-Boot FDT to include the final position and size of
+each entry in the images it processes. The option to enable this is -u and it
+causes binman to make sure that the 'offset', 'image-pos' and 'size' properties
+are set correctly for every entry. Since it is not necessary to specify these in
+the image definition, binman calculates the final values and writes these to
+the device tree. These can be used by U-Boot at run-time to find the location
+of each entry.
+
+
Map files
---------
The -m option causes binman to output a .map file for each image that it
-generates. This shows the position and size of each entry. For example:
+generates. This shows the offset and size of each entry. For example:
- Position Size Name
- 00000000 00000010 section@0
- 00000000 00000004 u-boot
- 00000010 00000010 section@1
- 00000000 00000004 u-boot
+ Offset Size Name
+ 00000000 00000028 main-section
+ 00000000 00000010 section@0
+ 00000000 00000004 u-boot
+ 00000010 00000010 section@1
+ 00000000 00000004 u-boot
This shows a hierarchical image with two sections, each with a single entry. The
-positions of the sections are absolute hex byte offsets within the image. The
-positions of the entries are relative to their respective sections. The size of
+offsets of the sections are absolute hex byte offsets within the image. The
+offsets of the entries are relative to their respective sections. The size of
each entry is also shown, in bytes (hex). The indentation shows the entries
nested inside their sections.
+Passing command-line arguments to entries
+-----------------------------------------
+
+Sometimes it is useful to pass binman the value of an entry property from the
+command line. For example some entries need access to files and it is not
+always convenient to put these filenames in the image definition (device tree).
+
+The-a option supports this:
+
+ -a<prop>=<value>
+
+where
+
+ <prop> is the property to set
+ <value> is the value to set it to
+
+Not all properties can be provided this way. Only some entries support it,
+typically for filenames.
+
+
Code coverage
-------------
to change the values of properties to support special behaviour. For example,
when Entry_blob loads a file, it sets content_size to the size of the file.
Entry classes can adjust other entries. For example, an entry that knows
-where other entries should be positioned can set up those entries' positions
+where other entries should be positioned can set up those entries' offsets
so they don't need to be set in the binman decription. It can also adjust
entry contents.
--- /dev/null
+Binman Entry Documentation
+===========================
+
+This file describes the entry types supported by binman. These entry types can
+be placed in an image one by one to build up a final firmware image. It is
+fairly easy to create new entry types. Just add a new file to the 'etype'
+directory. You can use the existing entries as examples.
+
+Note that some entries are subclasses of others, using and extending their
+features to produce new behaviours.
+
+
+
+Entry: blob: Entry containing an arbitrary binary blob
+------------------------------------------------------
+
+Note: This should not be used by itself. It is normally used as a parent
+class by other entry types.
+
+Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+This entry reads data from a file and places it in the entry. The
+default filename is often specified specified by the subclass. See for
+example the 'u_boot' entry which provides the filename 'u-boot.bin'.
+
+
+
+Entry: blob-named-by-arg: A blob entry which gets its filename property from its subclass
+-----------------------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - <xxx>-path: Filename containing the contents of this entry (optional,
+ defaults to 0)
+
+where <xxx> is the blob_fname argument to the constructor.
+
+This entry cannot be used directly. Instead, it is used as a parent class
+for another entry, which defined blob_fname. This parameter is used to
+set the entry-arg or property containing the filename. The entry-arg or
+property is in turn used to set the actual filename.
+
+See cros_ec_rw for an example of this.
+
+
+
+Entry: cros-ec-rw: A blob entry which contains a Chromium OS read-write EC image
+--------------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - cros-ec-rw-path: Filename containing the EC image
+
+This entry holds a Chromium OS EC (embedded controller) image, for use in
+updating the EC on startup via software sync.
+
+
+
+Entry: fill: An entry which is filled to a particular byte value
+----------------------------------------------------------------
+
+Properties / Entry arguments:
+ - fill-byte: Byte to use to fill the entry
+
+Note that the size property must be set since otherwise this entry does not
+know how large it should be.
+
+You can often achieve the same effect using the pad-byte property of the
+overall image, in that the space between entries will then be padded with
+that byte. But this entry is sometimes useful for explicitly setting the
+byte value of a region.
+
+
+
+Entry: fmap: An entry which contains an Fmap section
+----------------------------------------------------
+
+Properties / Entry arguments:
+ None
+
+FMAP is a simple format used by flashrom, an open-source utility for
+reading and writing the SPI flash, typically on x86 CPUs. The format
+provides flashrom with a list of areas, so it knows what it in the flash.
+It can then read or write just a single area, instead of the whole flash.
+
+The format is defined by the flashrom project, in the file lib/fmap.h -
+see www.flashrom.org/Flashrom for more information.
+
+When used, this entry will be populated with an FMAP which reflects the
+entries in the current image. Note that any hierarchy is squashed, since
+FMAP does not support this.
+
+
+
+Entry: gbb: An entry which contains a Chromium OS Google Binary Block
+---------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - hardware-id: Hardware ID to use for this build (a string)
+ - keydir: Directory containing the public keys to use
+ - bmpblk: Filename containing images used by recovery
+
+Chromium OS uses a GBB to store various pieces of information, in particular
+the root and recovery keys that are used to verify the boot process. Some
+more details are here:
+
+ https://www.chromium.org/chromium-os/firmware-porting-guide/2-concepts
+
+but note that the page dates from 2013 so is quite out of date. See
+README.chromium for how to obtain the required keys and tools.
+
+
+
+Entry: intel-cmc: Entry containing an Intel Chipset Micro Code (CMC) file
+-------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+This file contains microcode for some devices in a special format. An
+example filename is 'Microcode/C0_22211.BIN'.
+
+See README.x86 for information about x86 binary blobs.
+
+
+
+Entry: intel-descriptor: Intel flash descriptor block (4KB)
+-----------------------------------------------------------
+
+Properties / Entry arguments:
+ filename: Filename of file containing the descriptor. This is typically
+ a 4KB binary file, sometimes called 'descriptor.bin'
+
+This entry is placed at the start of flash and provides information about
+the SPI flash regions. In particular it provides the base address and
+size of the ME (Management Engine) region, allowing us to place the ME
+binary in the right place.
+
+With this entry in your image, the position of the 'intel-me' entry will be
+fixed in the image, which avoids you needed to specify an offset for that
+region. This is useful, because it is not possible to change the position
+of the ME region without updating the descriptor.
+
+See README.x86 for information about x86 binary blobs.
+
+
+
+Entry: intel-fsp: Entry containing an Intel Firmware Support Package (FSP) file
+-------------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+This file contains binary blobs which are used on some devices to make the
+platform work. U-Boot executes this code since it is not possible to set up
+the hardware using U-Boot open-source code. Documentation is typically not
+available in sufficient detail to allow this.
+
+An example filename is 'FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd'
+
+See README.x86 for information about x86 binary blobs.
+
+
+
+Entry: intel-me: Entry containing an Intel Management Engine (ME) file
+----------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+This file contains code used by the SoC that is required to make it work.
+The Management Engine is like a background task that runs things that are
+not clearly documented, but may include keyboard, deplay and network
+access. For platform that use ME it is not possible to disable it. U-Boot
+does not directly execute code in the ME binary.
+
+A typical filename is 'me.bin'.
+
+See README.x86 for information about x86 binary blobs.
+
+
+
+Entry: intel-mrc: Entry containing an Intel Memory Reference Code (MRC) file
+----------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+This file contains code for setting up the SDRAM on some Intel systems. This
+is executed by U-Boot when needed early during startup. A typical filename
+is 'mrc.bin'.
+
+See README.x86 for information about x86 binary blobs.
+
+
+
+Entry: intel-vbt: Entry containing an Intel Video BIOS Table (VBT) file
+-----------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+This file contains code that sets up the integrated graphics subsystem on
+some Intel SoCs. U-Boot executes this when the display is started up.
+
+See README.x86 for information about Intel binary blobs.
+
+
+
+Entry: intel-vga: Entry containing an Intel Video Graphics Adaptor (VGA) file
+-----------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+This file contains code that sets up the integrated graphics subsystem on
+some Intel SoCs. U-Boot executes this when the display is started up.
+
+This is similar to the VBT file but in a different format.
+
+See README.x86 for information about Intel binary blobs.
+
+
+
+Entry: section: Entry that contains other entries
+-------------------------------------------------
+
+Properties / Entry arguments: (see binman README for more information)
+ - size: Size of section in bytes
+ - align-size: Align size to a particular power of two
+ - pad-before: Add padding before the entry
+ - pad-after: Add padding after the entry
+ - pad-byte: Pad byte to use when padding
+ - sort-by-offset: Reorder the entries by offset
+ - end-at-4gb: Used to build an x86 ROM which ends at 4GB (2^32)
+ - name-prefix: Adds a prefix to the name of every entry in the section
+ when writing out the map
+
+A section is an entry which can contain other entries, thus allowing
+hierarchical images to be created. See 'Sections and hierarchical images'
+in the binman README for more information.
+
+
+
+Entry: text: An entry which contains text
+-----------------------------------------
+
+The text can be provided either in the node itself or by a command-line
+argument. There is a level of indirection to allow multiple text strings
+and sharing of text.
+
+Properties / Entry arguments:
+ text-label: The value of this string indicates the property / entry-arg
+ that contains the string to place in the entry
+ <xxx> (actual name is the value of text-label): contains the string to
+ place in the entry.
+
+Example node:
+
+ text {
+ size = <50>;
+ text-label = "message";
+ };
+
+You can then use:
+
+ binman -amessage="this is my message"
+
+and binman will insert that string into the entry.
+
+It is also possible to put the string directly in the node:
+
+ text {
+ size = <8>;
+ text-label = "message";
+ message = "a message directly in the node"
+ };
+
+The text is not itself nul-terminated. This can be achieved, if required,
+by setting the size of the entry to something larger than the text.
+
+
+
+Entry: u-boot: U-Boot flat binary
+---------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot.bin (default 'u-boot.bin')
+
+This is the U-Boot binary, containing relocation information to allow it
+to relocate itself at runtime. The binary typically includes a device tree
+blob at the end of it. Use u_boot_nodtb if you want to package the device
+tree separately.
+
+U-Boot can access binman symbols at runtime. See:
+
+ 'Access to binman entry offsets at run time (fdt)'
+
+in the binman README for more information.
+
+
+
+Entry: u-boot-dtb: U-Boot device tree
+-------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot.dtb (default 'u-boot.dtb')
+
+This is the U-Boot device tree, containing configuration information for
+U-Boot. U-Boot needs this to know what devices are present and which drivers
+to activate.
+
+
+
+Entry: u-boot-dtb-with-ucode: A U-Boot device tree file, with the microcode removed
+-----------------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot.dtb (default 'u-boot.dtb')
+
+See Entry_u_boot_ucode for full details of the three entries involved in
+this process. This entry provides the U-Boot device-tree file, which
+contains the microcode. If the microcode is not being collated into one
+place then the offset and size of the microcode is recorded by this entry,
+for use by u_boot_with_ucode_ptr. If it is being collated, then this
+entry deletes the microcode from the device tree (to save space) and makes
+it available to u_boot_ucode.
+
+
+
+Entry: u-boot-img: U-Boot legacy image
+--------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot.img (default 'u-boot.img')
+
+This is the U-Boot binary as a packaged image, in legacy format. It has a
+header which allows it to be loaded at the correct address for execution.
+
+You should use FIT (Flat Image Tree) instead of the legacy image for new
+applications.
+
+
+
+Entry: u-boot-nodtb: U-Boot flat binary without device tree appended
+--------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot.bin (default 'u-boot-nodtb.bin')
+
+This is the U-Boot binary, containing relocation information to allow it
+to relocate itself at runtime. It does not include a device tree blob at
+the end of it so normally cannot work without it. You can add a u_boot_dtb
+entry after this one, or use a u_boot entry instead (which contains both
+U-Boot and the device tree).
+
+
+
+Entry: u-boot-spl: U-Boot SPL binary
+------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot-spl.bin (default 'spl/u-boot-spl.bin')
+
+This is the U-Boot SPL (Secondary Program Loader) binary. This is a small
+binary which loads before U-Boot proper, typically into on-chip SRAM. It is
+responsible for locating, loading and jumping to U-Boot. Note that SPL is
+not relocatable so must be loaded to the correct address in SRAM, or written
+to run from the correct address if direct flash execution is possible (e.g.
+on x86 devices).
+
+SPL can access binman symbols at runtime. See:
+
+ 'Access to binman entry offsets at run time (symbols)'
+
+in the binman README for more information.
+
+The ELF file 'spl/u-boot-spl' must also be available for this to work, since
+binman uses that to look up symbols to write into the SPL binary.
+
+
+
+Entry: u-boot-spl-bss-pad: U-Boot SPL binary padded with a BSS region
+---------------------------------------------------------------------
+
+Properties / Entry arguments:
+ None
+
+This is similar to u_boot_spl except that padding is added after the SPL
+binary to cover the BSS (Block Started by Symbol) region. This region holds
+the various used by SPL. It is set to 0 by SPL when it starts up. If you
+want to append data to the SPL image (such as a device tree file), you must
+pad out the BSS region to avoid the data overlapping with U-Boot variables.
+This entry is useful in that case. It automatically pads out the entry size
+to cover both the code, data and BSS.
+
+The ELF file 'spl/u-boot-spl' must also be available for this to work, since
+binman uses that to look up the BSS address.
+
+
+
+Entry: u-boot-spl-dtb: U-Boot SPL device tree
+---------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot.dtb (default 'spl/u-boot-spl.dtb')
+
+This is the SPL device tree, containing configuration information for
+SPL. SPL needs this to know what devices are present and which drivers
+to activate.
+
+
+
+Entry: u-boot-spl-nodtb: SPL binary without device tree appended
+----------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of spl/u-boot-spl-nodtb.bin (default
+ 'spl/u-boot-spl-nodtb.bin')
+
+This is the U-Boot SPL binary, It does not include a device tree blob at
+the end of it so may not be able to work without it, assuming SPL needs
+a device tree to operation on your platform. You can add a u_boot_spl_dtb
+entry after this one, or use a u_boot_spl entry instead (which contains
+both SPL and the device tree).
+
+
+
+Entry: u-boot-spl-with-ucode-ptr: U-Boot SPL with embedded microcode pointer
+----------------------------------------------------------------------------
+
+See Entry_u_boot_ucode for full details of the entries involved in this
+process.
+
+
+
+Entry: u-boot-tpl: U-Boot TPL binary
+------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot-tpl.bin (default 'tpl/u-boot-tpl.bin')
+
+This is the U-Boot TPL (Tertiary Program Loader) binary. This is a small
+binary which loads before SPL, typically into on-chip SRAM. It is
+responsible for locating, loading and jumping to SPL, the next-stage
+loader. Note that SPL is not relocatable so must be loaded to the correct
+address in SRAM, or written to run from the correct address if direct
+flash execution is possible (e.g. on x86 devices).
+
+SPL can access binman symbols at runtime. See:
+
+ 'Access to binman entry offsets at run time (symbols)'
+
+in the binman README for more information.
+
+The ELF file 'tpl/u-boot-tpl' must also be available for this to work, since
+binman uses that to look up symbols to write into the TPL binary.
+
+
+
+Entry: u-boot-tpl-dtb: U-Boot TPL device tree
+---------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot.dtb (default 'tpl/u-boot-tpl.dtb')
+
+This is the TPL device tree, containing configuration information for
+TPL. TPL needs this to know what devices are present and which drivers
+to activate.
+
+
+
+Entry: u-boot-ucode: U-Boot microcode block
+-------------------------------------------
+
+Properties / Entry arguments:
+ None
+
+The contents of this entry are filled in automatically by other entries
+which must also be in the image.
+
+U-Boot on x86 needs a single block of microcode. This is collected from
+the various microcode update nodes in the device tree. It is also unable
+to read the microcode from the device tree on platforms that use FSP
+(Firmware Support Package) binaries, because the API requires that the
+microcode is supplied before there is any SRAM available to use (i.e.
+the FSP sets up the SRAM / cache-as-RAM but does so in the call that
+requires the microcode!). To keep things simple, all x86 platforms handle
+microcode the same way in U-Boot (even non-FSP platforms). This is that
+a table is placed at _dt_ucode_base_size containing the base address and
+size of the microcode. This is either passed to the FSP (for FSP
+platforms), or used to set up the microcode (for non-FSP platforms).
+This all happens in the build system since it is the only way to get
+the microcode into a single blob and accessible without SRAM.
+
+There are two cases to handle. If there is only one microcode blob in
+the device tree, then the ucode pointer it set to point to that. This
+entry (u-boot-ucode) is empty. If there is more than one update, then
+this entry holds the concatenation of all updates, and the device tree
+entry (u-boot-dtb-with-ucode) is updated to remove the microcode. This
+last step ensures that that the microcode appears in one contiguous
+block in the image and is not unnecessarily duplicated in the device
+tree. It is referred to as 'collation' here.
+
+Entry types that have a part to play in handling microcode:
+
+ Entry_u_boot_with_ucode_ptr:
+ Contains u-boot-nodtb.bin (i.e. U-Boot without the device tree).
+ It updates it with the address and size of the microcode so that
+ U-Boot can find it early on start-up.
+ Entry_u_boot_dtb_with_ucode:
+ Contains u-boot.dtb. It stores the microcode in a
+ 'self.ucode_data' property, which is then read by this class to
+ obtain the microcode if needed. If collation is performed, it
+ removes the microcode from the device tree.
+ Entry_u_boot_ucode:
+ This class. If collation is enabled it reads the microcode from
+ the Entry_u_boot_dtb_with_ucode entry, and uses it as the
+ contents of this entry.
+
+
+
+Entry: u-boot-with-ucode-ptr: U-Boot with embedded microcode pointer
+--------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot-nodtb.dtb (default 'u-boot-nodtb.dtb')
+
+See Entry_u_boot_ucode for full details of the three entries involved in
+this process. This entry updates U-Boot with the offset and size of the
+microcode, to allow early x86 boot code to find it without doing anything
+complicated. Otherwise it is the same as the u_boot entry.
+
+
+
+Entry: vblock: An entry which contains a Chromium OS verified boot block
+------------------------------------------------------------------------
+
+Properties / Entry arguments:
+ - keydir: Directory containing the public keys to use
+ - keyblock: Name of the key file to use (inside keydir)
+ - signprivate: Name of provide key file to use (inside keydir)
+ - version: Version number of the vblock (typically 1)
+ - kernelkey: Name of the kernel key to use (inside keydir)
+ - preamble-flags: Value of the vboot preamble flags (typically 0)
+
+Chromium OS signs the read-write firmware and kernel, writing the signature
+in this block. This allows U-Boot to verify that the next firmware stage
+and kernel are genuine.
+
+
+
+Entry: x86-start16: x86 16-bit start-up code for U-Boot
+-------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of u-boot-x86-16bit.bin (default
+ 'u-boot-x86-16bit.bin')
+
+x86 CPUs start up in 16-bit mode, even if they are 32-bit CPUs. This code
+must be placed at a particular address. This entry holds that code. It is
+typically placed at offset CONFIG_SYS_X86_START16. The code is responsible
+for changing to 32-bit mode and jumping to U-Boot's entry point, which
+requires 32-bit mode (for 32-bit U-Boot).
+
+For 64-bit U-Boot, the 'x86_start16_spl' entry type is used instead.
+
+
+
+Entry: x86-start16-spl: x86 16-bit start-up code for SPL
+--------------------------------------------------------
+
+Properties / Entry arguments:
+ - filename: Filename of spl/u-boot-x86-16bit-spl.bin (default
+ 'spl/u-boot-x86-16bit-spl.bin')
+
+x86 CPUs start up in 16-bit mode, even if they are 64-bit CPUs. This code
+must be placed at a particular address. This entry holds that code. It is
+typically placed at offset CONFIG_SYS_X86_START16. The code is responsible
+for changing to 32-bit mode and starting SPL, which in turn changes to
+64-bit mode and jumps to U-Boot (for 64-bit U-Boot).
+
+For 32-bit U-Boot, the 'x86_start16' entry type is used instead.
+
+
+
return 1
return 0
+def GetEntryModules(include_testing=True):
+ """Get a set of entry class implementations
+
+ Returns:
+ Set of paths to entry class filenames
+ """
+ glob_list = glob.glob(os.path.join(our_path, 'etype/*.py'))
+ return set([os.path.splitext(os.path.basename(item))[0]
+ for item in glob_list
+ if include_testing or '_testing' not in item])
+
def RunTestCoverage():
"""Run the tests and check that we get 100% coverage"""
- glob_list = glob.glob(os.path.join(our_path, 'etype/*.py'))
+ glob_list = GetEntryModules(False)
all_set = set([os.path.splitext(os.path.basename(item))[0]
for item in glob_list if '_testing' not in item])
test_util.RunTestCoverage('tools/binman/binman.py', None,
elif options.test_coverage:
RunTestCoverage()
- elif options.full_help:
- pager = os.getenv('PAGER')
- if not pager:
- pager = 'more'
- fname = os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])),
- 'README')
- command.Run(pager, fname)
+ elif options.entry_docs:
+ control.WriteEntryDocs(GetEntryModules())
else:
try:
_size: Section size in bytes, or None if not known yet
_align_size: Section size alignment, or None
_pad_before: Number of bytes before the first entry starts. This
- effectively changes the place where entry position 0 starts
+ effectively changes the place where entry offset 0 starts
_pad_after: Number of bytes after the last entry ends. The last
entry will finish on or before this boundary
_pad_byte: Byte to use to pad the section where there is no entry
- _sort: True if entries should be sorted by position, False if they
+ _sort: True if entries should be sorted by offset, False if they
must be in-order in the device tree description
_skip_at_start: Number of bytes before the first entry starts. These
- effectively adjust the starting position of entries. For example,
+ effectively adjust the starting offset of entries. For example,
if _pad_before is 16, then the first entry would start at 16.
- An entry with pos = 20 would in fact be written at position 4
+ An entry with offset = 20 would in fact be written at offset 4
in the image file.
_end_4gb: Indicates that the section ends at the 4GB boundary. This is
- used for x86 images, which want to use positions such that a
- memory address (like 0xff800000) is the first entry position.
- This causes _skip_at_start to be set to the starting memory
- address.
+ used for x86 images, which want to use offsets such that a memory
+ address (like 0xff800000) is the first entry offset. This causes
+ _skip_at_start to be set to the starting memory address.
_name_prefix: Prefix to add to the name of all entries within this
section
_entries: OrderedDict() of entries
import entry
from entry import Entry
+ self._name = name
self._node = node
+ self._offset = 0
self._size = None
self._align_size = None
self._pad_before = 0
self._pad_before = fdt_util.GetInt(self._node, 'pad-before', 0)
self._pad_after = fdt_util.GetInt(self._node, 'pad-after', 0)
self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0)
- self._sort = fdt_util.GetBool(self._node, 'sort-by-pos')
+ self._sort = fdt_util.GetBool(self._node, 'sort-by-offset')
self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb')
if self._end_4gb and not self._size:
self._Raise("Section size must be provided when using end-at-4gb")
entry.SetPrefix(self._name_prefix)
self._entries[node.name] = entry
+ def SetOffset(self, offset):
+ self._offset = offset
+
def AddMissingProperties(self):
+ """Add new properties to the device tree as needed for this entry"""
+ for prop in ['offset', 'size', 'image-pos']:
+ if not prop in self._node.props:
+ self._node.AddZeroProp(prop)
for entry in self._entries.values():
entry.AddMissingProperties()
def SetCalculatedProperties(self):
+ self._node.SetInt('offset', self._offset)
+ self._node.SetInt('size', self._size)
+ self._node.SetInt('image-pos', self._image_pos)
for entry in self._entries.values():
entry.SetCalculatedProperties()
"""Check that the section contents does not exceed its size, etc."""
contents_size = 0
for entry in self._entries.values():
- contents_size = max(contents_size, entry.pos + entry.size)
+ contents_size = max(contents_size, entry.offset + entry.size)
contents_size -= self._skip_at_start
'contents: remaining %s' % todo)
return True
- def _SetEntryPosSize(self, name, pos, size):
- """Set the position and size of an entry
+ def _SetEntryOffsetSize(self, name, offset, size):
+ """Set the offset and size of an entry
Args:
name: Entry name to update
- pos: New position
+ offset: New offset
size: New size
"""
entry = self._entries.get(name)
if not entry:
- self._Raise("Unable to set pos/size for unknown entry '%s'" % name)
- entry.SetPositionSize(self._skip_at_start + pos, size)
+ self._Raise("Unable to set offset/size for unknown entry '%s'" %
+ name)
+ entry.SetOffsetSize(self._skip_at_start + offset, size)
- def GetEntryPositions(self):
- """Handle entries that want to set the position/size of other entries
+ def GetEntryOffsets(self):
+ """Handle entries that want to set the offset/size of other entries
- This calls each entry's GetPositions() method. If it returns a list
+ This calls each entry's GetOffsets() method. If it returns a list
of entries to update, it updates them.
"""
for entry in self._entries.values():
- pos_dict = entry.GetPositions()
- for name, info in pos_dict.iteritems():
- self._SetEntryPosSize(name, *info)
+ offset_dict = entry.GetOffsets()
+ for name, info in offset_dict.iteritems():
+ self._SetEntryOffsetSize(name, *info)
def PackEntries(self):
"""Pack all entries into the section"""
- pos = self._skip_at_start
+ offset = self._skip_at_start
for entry in self._entries.values():
- pos = entry.Pack(pos)
+ offset = entry.Pack(offset)
+ self._size = self.CheckSize()
def _SortEntries(self):
- """Sort entries by position"""
- entries = sorted(self._entries.values(), key=lambda entry: entry.pos)
+ """Sort entries by offset"""
+ entries = sorted(self._entries.values(), key=lambda entry: entry.offset)
self._entries.clear()
for entry in entries:
self._entries[entry._node.name] = entry
"""Check that entries do not overlap or extend outside the section"""
if self._sort:
self._SortEntries()
- pos = 0
+ offset = 0
prev_name = 'None'
for entry in self._entries.values():
- entry.CheckPosition()
- if (entry.pos < self._skip_at_start or
- entry.pos >= self._skip_at_start + self._size):
- entry.Raise("Position %#x (%d) is outside the section starting "
+ entry.CheckOffset()
+ if (entry.offset < self._skip_at_start or
+ entry.offset >= self._skip_at_start + self._size):
+ entry.Raise("Offset %#x (%d) is outside the section starting "
"at %#x (%d)" %
- (entry.pos, entry.pos, self._skip_at_start,
+ (entry.offset, entry.offset, self._skip_at_start,
self._skip_at_start))
- if entry.pos < pos:
- entry.Raise("Position %#x (%d) overlaps with previous entry '%s' "
+ if entry.offset < offset:
+ entry.Raise("Offset %#x (%d) overlaps with previous entry '%s' "
"ending at %#x (%d)" %
- (entry.pos, entry.pos, prev_name, pos, pos))
- pos = entry.pos + entry.size
+ (entry.offset, entry.offset, prev_name, offset, offset))
+ offset = entry.offset + entry.size
prev_name = entry.GetPath()
+ def SetImagePos(self, image_pos):
+ self._image_pos = image_pos
+ for entry in self._entries.values():
+ entry.SetImagePos(image_pos)
+
def ProcessEntryContents(self):
"""Call the ProcessContents() method for each entry
for entry in self._entries.values():
entry.WriteSymbols(self)
- def BuildSection(self, fd, base_pos):
+ def BuildSection(self, fd, base_offset):
"""Write the section to a file"""
- fd.seek(base_pos)
+ fd.seek(base_offset)
fd.write(self.GetData())
def GetData(self):
- """Write the section to a file"""
+ """Get the contents of the section"""
section_data = chr(self._pad_byte) * self._size
for entry in self._entries.values():
data = entry.GetData()
- base = self._pad_before + entry.pos - self._skip_at_start
+ base = self._pad_before + entry.offset - self._skip_at_start
section_data = (section_data[:base] + data +
section_data[base + len(data):])
return section_data
Looks up a symbol in an ELF file. Only entry types which come from an
ELF image can be used by this function.
- At present the only entry property supported is pos.
+ At present the only entry property supported is offset.
Args:
sym_name: Symbol name in the ELF file to look up in the format
_binman_<entry>_prop_<property> where <entry> is the name of
the entry and <property> is the property to find (e.g.
- _binman_u_boot_prop_pos). As a special case, you can append
+ _binman_u_boot_prop_offset). As a special case, you can append
_any to <entry> to have it search for any matching entry. E.g.
- _binman_u_boot_any_prop_pos will match entries called u-boot,
+ _binman_u_boot_any_prop_offset will match entries called u-boot,
u-boot-img and u-boot-nodtb)
optional: True if the symbol is optional. If False this function
will raise if the symbol is not found
print('Warning: %s' % err, file=sys.stderr)
return None
raise ValueError(err)
- if prop_name == 'pos':
- return entry.pos
+ if prop_name == 'offset':
+ return entry.offset
+ elif prop_name == 'image_pos':
+ return entry.image_pos
else:
raise ValueError("%s: No such property '%s'" % (msg, prop_name))
def GetEntries(self):
+ """Get the number of entries in a section
+
+ Returns:
+ Number of entries in a section
+ """
return self._entries
+ def GetSize(self):
+ """Get the size of a section in bytes
+
+ This is only meaningful if the section has a pre-defined size, or the
+ entries within it have been packed, so that the size has been
+ calculated.
+
+ Returns:
+ Entry size in bytes
+ """
+ return self._size
+
def WriteMap(self, fd, indent):
"""Write a map of the section to a .map file
Args:
fd: File to write the map to
"""
+ Entry.WriteMapLine(fd, indent, self._name, self._offset, self._size,
+ self._image_pos)
+ for entry in self._entries.values():
+ entry.WriteMap(fd, indent + 1)
+
+ def GetContentsByPhandle(self, phandle, source_entry):
+ """Get the data contents of an entry specified by a phandle
+
+ This uses a phandle to look up a node and and find the entry
+ associated with it. Then it returnst he contents of that entry.
+
+ Args:
+ phandle: Phandle to look up (integer)
+ source_entry: Entry containing that phandle (used for error
+ reporting)
+
+ Returns:
+ data from associated entry (as a string), or None if not found
+ """
+ node = self._node.GetFdt().LookupPhandle(phandle)
+ if not node:
+ source_entry.Raise("Cannot find node for phandle %d" % phandle)
for entry in self._entries.values():
- entry.WriteMap(fd, indent)
+ if entry._node == node:
+ if entry.data is None:
+ return None
+ return entry.data
+ source_entry.Raise("Cannot find entry for node '%s'" % node.name)
args is a list of string arguments
"""
parser = OptionParser()
+ parser.add_option('-a', '--entry-arg', type='string', action='append',
+ help='Set argument value arg=value')
parser.add_option('-b', '--board', type='string',
help='Board name to build')
parser.add_option('-B', '--build-dir', type='string', default='b',
help='Configuration file (.dtb) to use')
parser.add_option('-D', '--debug', action='store_true',
help='Enabling debugging (provides a full traceback on error)')
+ parser.add_option('-E', '--entry-docs', action='store_true',
+ help='Write out entry documentation (see README.entries)')
parser.add_option('-I', '--indir', action='append',
help='Add a path to a directory to use for input files')
parser.add_option('-H', '--full-help', action='store_true',
parser.add_option('-T', '--test-coverage', action='store_true',
default=False, help='run tests and check for 100% coverage')
parser.add_option('-u', '--update-fdt', action='store_true',
- default=False, help='Update the binman node with position/size info')
+ default=False, help='Update the binman node with offset/size info')
parser.add_option('-v', '--verbosity', default=1,
type='int', help='Control verbosity: 0=silent, 1=progress, 3=full, '
'4=debug')
from collections import OrderedDict
import os
+import re
import sys
import tools
import command
import elf
-import fdt
-import fdt_util
from image import Image
import tout
# 'u-boot-spl.dtb')
fdt_files = {}
+# Arguments passed to binman to provide arguments to entries
+entry_args = {}
+
def _ReadImageDesc(binman_node):
"""Read the image descriptions from the /binman node
def GetFdtPath(fname):
return fdt_files[fname]._fname
+def SetEntryArgs(args):
+ global entry_args
+
+ entry_args = {}
+ if args:
+ for arg in args:
+ m = re.match('([^=]*)=(.*)', arg)
+ if not m:
+ raise ValueError("Invalid entry arguemnt '%s'" % arg)
+ entry_args[m.group(1)] = m.group(2)
+
+def GetEntryArg(name):
+ return entry_args.get(name)
+
+def WriteEntryDocs(modules, test_missing=None):
+ from entry import Entry
+ Entry.WriteDocs(modules, test_missing)
+
def Binman(options, args):
"""The main control code for binman
options.indir.append(board_pathname)
try:
+ # Import these here in case libfdt.py is not available, in which case
+ # the above help option still works.
+ import fdt
+ import fdt_util
+
tout.Init(options.verbosity)
elf.debug = options.debug
try:
tools.SetInputDirs(options.indir)
tools.PrepareOutputDir(options.outdir, options.preserve)
+ SetEntryArgs(options.entry_arg)
# Get the device tree ready by compiling it and copying the compiled
# output into a file in our output directly. Then scan it for use
# size of the device tree is correct. Later, in
# SetCalculatedProperties() we will insert the correct values
# without changing the device-tree size, thus ensuring that our
- # entry positions remain the same.
+ # entry offsets remain the same.
for image in images.values():
if options.update_fdt:
image.AddMissingProperties()
# image will be reported after earlier images are already
# completed and written, but that does not seem important.
image.GetEntryContents()
- image.GetEntryPositions()
+ image.GetEntryOffsets()
image.PackEntries()
image.CheckSize()
image.CheckEntries()
+ image.SetImagePos()
if options.update_fdt:
image.SetCalculatedProperties()
image.ProcessEntryContents()
name = parts[2]
syms[name] = Symbol(section, int(value, 16), int(size,16),
flags[1] == 'w')
- return syms
+
+ # Sort dict by address
+ return OrderedDict(sorted(syms.iteritems(), key=lambda x: x[1].address))
def GetSymbolAddress(fname, sym_name):
"""Get a value of a symbol from an ELF file
"""Replace all symbols in an entry with their correct values
The entry contents is updated so that values for referenced symbols will be
- visible at run time. This is done by finding out the symbols positions in
- the entry (using the ELF file) and replacing them with values from binman's
- data structures.
+ visible at run time. This is done by finding out the symbols offsets in the
+ entry (using the ELF file) and replacing them with values from binman's data
+ structures.
Args:
elf_fname: Filename of ELF image containing the symbol information for
class FakeEntry:
+ """A fake Entry object, usedfor testing
+
+ This supports an entry with a given size.
+ """
def __init__(self, contents_size):
self.contents_size = contents_size
self.data = 'a' * contents_size
def GetPath(self):
return 'entry_path'
+
class FakeSection:
+ """A fake Section object, used for testing
+
+ This has the minimum feature set needed to support testing elf functions.
+ A LookupSymbol() function is provided which returns a fake value for amu
+ symbol requested.
+ """
def __init__(self, sym_value=1):
self.sym_value = sym_value
return 'section_path'
def LookupSymbol(self, name, weak, msg):
+ """Fake implementation which returns the same value for all symbols"""
return self.sym_value
+
class TestElf(unittest.TestCase):
def testAllSymbols(self):
+ """Test that we can obtain a symbol from the ELF file"""
fname = os.path.join(binman_dir, 'test', 'u_boot_ucode_ptr')
syms = elf.GetSymbols(fname, [])
self.assertIn('.ucode', syms)
def testRegexSymbols(self):
+ """Test that we can obtain from the ELF file by regular expression"""
fname = os.path.join(binman_dir, 'test', 'u_boot_ucode_ptr')
syms = elf.GetSymbols(fname, ['ucode'])
self.assertIn('.ucode', syms)
self.assertIn('.ucode', syms)
def testMissingFile(self):
+ """Test that a missing file is detected"""
entry = FakeEntry(10)
section = FakeSection()
with self.assertRaises(ValueError) as e:
str(e.exception))
def testOutsideFile(self):
+ """Test a symbol which extends outside the entry area is detected"""
entry = FakeEntry(10)
section = FakeSection()
elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
'is a', str(e.exception))
def testMissingImageStart(self):
+ """Test that we detect a missing __image_copy_start symbol
+
+ This is needed to mark the start of the image. Without it we cannot
+ locate the offset of a binman symbol within the image.
+ """
entry = FakeEntry(10)
section = FakeSection()
elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms_bad')
None)
def testBadSymbolSize(self):
+ """Test that an attempt to use an 8-bit symbol are detected
+
+ Only 32 and 64 bits are supported, since we need to store an offset
+ into the image.
+ """
entry = FakeEntry(10)
section = FakeSection()
elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms_size')
str(e.exception))
def testNoValue(self):
+ """Test the case where we have no value for the symbol
+
+ This should produce -1 values for all thress symbols, taking up the
+ first 16 bytes of the image.
+ """
entry = FakeEntry(20)
section = FakeSection(sym_value=None)
elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
self.assertEqual(chr(255) * 16 + 'a' * 4, entry.data)
def testDebug(self):
+ """Check that enabling debug in the elf module produced debug output"""
elf.debug = True
entry = FakeEntry(20)
section = FakeSection()
from __future__ import print_function
+from collections import namedtuple
+
# importlib was introduced in Python 2.7 but there was a report of it not
# working in 2.7.12, so we work around this:
# http://lists.denx.de/pipermail/u-boot/2016-October/269729.html
have_importlib = False
import fdt_util
+import control
import os
import sys
import tools
our_path = os.path.dirname(os.path.realpath(__file__))
+
+# An argument which can be passed to entries on the command line, in lieu of
+# device-tree properties.
+EntryArg = namedtuple('EntryArg', ['name', 'datatype'])
+
+
class Entry(object):
"""An Entry in the section
Entry.
Attributes:
- section: The section containing this entry
+ section: Section object containing this entry
node: The node that created this entry
- pos: Absolute position of entry within the section, None if not known
+ offset: Offset of entry within the section, None if not known yet (in
+ which case it will be calculated by Pack())
size: Entry size in bytes, None if not known
contents_size: Size of contents in bytes, 0 by default
- align: Entry start position alignment, or None
+ align: Entry start offset alignment, or None
align_size: Entry size alignment, or None
- align_end: Entry end position alignment, or None
+ align_end: Entry end offset alignment, or None
pad_before: Number of pad bytes before the contents, 0 if none
pad_after: Number of pad bytes after the contents, 0 if none
data: Contents of entry (string of bytes)
self.etype = etype
self._node = node
self.name = node and (name_prefix + node.name) or 'none'
- self.pos = None
+ self.offset = None
self.size = None
- self.data = ''
+ self.data = None
self.contents_size = 0
self.align = None
self.align_size = None
self.align_end = None
self.pad_before = 0
self.pad_after = 0
- self.pos_unset = False
+ self.offset_unset = False
+ self.image_pos = None
if read_node:
self.ReadNode()
@staticmethod
- def Create(section, node, etype=None):
- """Create a new entry for a node.
+ def Lookup(section, node_path, etype):
+ """Look up the entry class for a node.
Args:
- section: Image object containing this node
- node: Node object containing information about the entry to create
- etype: Entry type to use, or None to work it out (used for tests)
+ section: Section object containing this node
+ node_node: Path name of Node object containing information about
+ the entry to create (used for errors)
+ etype: Entry type to use
Returns:
- A new Entry object of the correct type (a subclass of Entry)
+ The entry class object if found, else None
"""
- if not etype:
- etype = fdt_util.GetString(node, 'type', node.name)
-
# Convert something like 'u-boot@0' to 'u_boot' since we are only
# interested in the type.
module_name = etype.replace('-', '_')
module = importlib.import_module(module_name)
else:
module = __import__(module_name)
- except ImportError:
- raise ValueError("Unknown entry type '%s' in node '%s'" %
- (etype, node.path))
+ except ImportError as e:
+ raise ValueError("Unknown entry type '%s' in node '%s' (expected etype/%s.py, error '%s'" %
+ (etype, node_path, module_name, e))
finally:
sys.path = old_path
modules[module_name] = module
+ # Look up the expected class name
+ return getattr(module, 'Entry_%s' % module_name)
+
+ @staticmethod
+ def Create(section, node, etype=None):
+ """Create a new entry for a node.
+
+ Args:
+ section: Section object containing this node
+ node: Node object containing information about the entry to
+ create
+ etype: Entry type to use, or None to work it out (used for tests)
+
+ Returns:
+ A new Entry object of the correct type (a subclass of Entry)
+ """
+ if not etype:
+ etype = fdt_util.GetString(node, 'type', node.name)
+ obj = Entry.Lookup(section, node.path, etype)
+
# Call its constructor to get the object we want.
- obj = getattr(module, 'Entry_%s' % module_name)
return obj(section, etype, node)
def ReadNode(self):
This reads all the fields we recognise from the node, ready for use.
"""
- self.pos = fdt_util.GetInt(self._node, 'pos')
+ if 'pos' in self._node.props:
+ self.Raise("Please use 'offset' instead of 'pos'")
+ self.offset = fdt_util.GetInt(self._node, 'offset')
self.size = fdt_util.GetInt(self._node, 'size')
self.align = fdt_util.GetInt(self._node, 'align')
if tools.NotPowerOfTwo(self.align):
raise ValueError("Node '%s': Alignment size %s must be a power "
"of two" % (self._node.path, self.align_size))
self.align_end = fdt_util.GetInt(self._node, 'align-end')
- self.pos_unset = fdt_util.GetBool(self._node, 'pos-unset')
+ self.offset_unset = fdt_util.GetBool(self._node, 'offset-unset')
def AddMissingProperties(self):
"""Add new properties to the device tree as needed for this entry"""
- for prop in ['pos', 'size']:
+ for prop in ['offset', 'size', 'image-pos']:
if not prop in self._node.props:
self._node.AddZeroProp(prop)
def SetCalculatedProperties(self):
"""Set the value of device-tree properties calculated by binman"""
- self._node.SetInt('pos', self.pos)
+ self._node.SetInt('offset', self.offset)
self._node.SetInt('size', self.size)
+ self._node.SetInt('image-pos', self.image_pos)
def ProcessFdt(self, fdt):
return True
# No contents by default: subclasses can implement this
return True
- def Pack(self, pos):
+ def Pack(self, offset):
"""Figure out how to pack the entry into the section
Most of the time the entries are not fully specified. There may be
an alignment but no size. In that case we take the size from the
contents of the entry.
- If an entry has no hard-coded position, it will be placed at @pos.
+ If an entry has no hard-coded offset, it will be placed at @offset.
- Once this function is complete, both the position and size of the
+ Once this function is complete, both the offset and size of the
entry will be know.
Args:
- Current section position pointer
+ Current section offset pointer
Returns:
- New section position pointer (after this entry)
+ New section offset pointer (after this entry)
"""
- if self.pos is None:
- if self.pos_unset:
- self.Raise('No position set with pos-unset: should another '
- 'entry provide this correct position?')
- self.pos = tools.Align(pos, self.align)
+ if self.offset is None:
+ if self.offset_unset:
+ self.Raise('No offset set with offset-unset: should another '
+ 'entry provide this correct offset?')
+ self.offset = tools.Align(offset, self.align)
needed = self.pad_before + self.contents_size + self.pad_after
needed = tools.Align(needed, self.align_size)
size = self.size
if not size:
size = needed
- new_pos = self.pos + size
- aligned_pos = tools.Align(new_pos, self.align_end)
- if aligned_pos != new_pos:
- size = aligned_pos - self.pos
- new_pos = aligned_pos
+ new_offset = self.offset + size
+ aligned_offset = tools.Align(new_offset, self.align_end)
+ if aligned_offset != new_offset:
+ size = aligned_offset - self.offset
+ new_offset = aligned_offset
if not self.size:
self.size = size
self.Raise("Entry contents size is %#x (%d) but entry size is "
"%#x (%d)" % (needed, needed, self.size, self.size))
# Check that the alignment is correct. It could be wrong if the
- # and pos or size values were provided (i.e. not calculated), but
+ # and offset or size values were provided (i.e. not calculated), but
# conflict with the provided alignment values
if self.size != tools.Align(self.size, self.align_size):
self.Raise("Size %#x (%d) does not match align-size %#x (%d)" %
(self.size, self.size, self.align_size, self.align_size))
- if self.pos != tools.Align(self.pos, self.align):
- self.Raise("Position %#x (%d) does not match align %#x (%d)" %
- (self.pos, self.pos, self.align, self.align))
+ if self.offset != tools.Align(self.offset, self.align):
+ self.Raise("Offset %#x (%d) does not match align %#x (%d)" %
+ (self.offset, self.offset, self.align, self.align))
- return new_pos
+ return new_offset
def Raise(self, msg):
"""Convenience function to raise an error referencing a node"""
raise ValueError("Node '%s': %s" % (self._node.path, msg))
+ def GetEntryArgsOrProps(self, props, required=False):
+ """Return the values of a set of properties
+
+ Args:
+ props: List of EntryArg objects
+
+ Raises:
+ ValueError if a property is not found
+ """
+ values = []
+ missing = []
+ for prop in props:
+ python_prop = prop.name.replace('-', '_')
+ if hasattr(self, python_prop):
+ value = getattr(self, python_prop)
+ else:
+ value = None
+ if value is None:
+ value = self.GetArg(prop.name, prop.datatype)
+ if value is None and required:
+ missing.append(prop.name)
+ values.append(value)
+ if missing:
+ self.Raise('Missing required properties/entry args: %s' %
+ (', '.join(missing)))
+ return values
+
def GetPath(self):
"""Get the path of a node
def GetData(self):
return self.data
- def GetPositions(self):
+ def GetOffsets(self):
return {}
- def SetPositionSize(self, pos, size):
- self.pos = pos
+ def SetOffsetSize(self, pos, size):
+ self.offset = pos
self.size = size
+ def SetImagePos(self, image_pos):
+ """Set the position in the image
+
+ Args:
+ image_pos: Position of this entry in the image
+ """
+ self.image_pos = image_pos + self.offset
+
def ProcessContents(self):
pass
"""
pass
- def CheckPosition(self):
- """Check that the entry positions are correct
+ def CheckOffset(self):
+ """Check that the entry offsets are correct
- This is used for entries which have extra position requirements (other
+ This is used for entries which have extra offset requirements (other
than having to be fully inside their section). Sub-classes can implement
this function and raise if there is a problem.
"""
pass
+ @staticmethod
+ def WriteMapLine(fd, indent, name, offset, size, image_pos):
+ print('%08x %s%08x %08x %s' % (image_pos, ' ' * indent, offset,
+ size, name), file=fd)
+
def WriteMap(self, fd, indent):
"""Write a map of the entry to a .map file
fd: File to write the map to
indent: Curent indent level of map (0=none, 1=one level, etc.)
"""
- print('%s%08x %08x %s' % (' ' * indent, self.pos, self.size,
- self.name), file=fd)
+ self.WriteMapLine(fd, indent, self.name, self.offset, self.size,
+ self.image_pos)
+
+ def GetEntries(self):
+ """Return a list of entries contained by this entry
+
+ Returns:
+ List of entries, or None if none. A normal entry has no entries
+ within it so will return None
+ """
+ return None
+
+ def GetArg(self, name, datatype=str):
+ """Get the value of an entry argument or device-tree-node property
+
+ Some node properties can be provided as arguments to binman. First check
+ the entry arguments, and fall back to the device tree if not found
+
+ Args:
+ name: Argument name
+ datatype: Data type (str or int)
+
+ Returns:
+ Value of argument as a string or int, or None if no value
+
+ Raises:
+ ValueError if the argument cannot be converted to in
+ """
+ value = control.GetEntryArg(name)
+ if value is not None:
+ if datatype == int:
+ try:
+ value = int(value)
+ except ValueError:
+ self.Raise("Cannot convert entry arg '%s' (value '%s') to integer" %
+ (name, value))
+ elif datatype == str:
+ pass
+ else:
+ raise ValueError("GetArg() internal error: Unknown data type '%s'" %
+ datatype)
+ else:
+ value = fdt_util.GetDatatype(self._node, name, datatype)
+ return value
+
+ @staticmethod
+ def WriteDocs(modules, test_missing=None):
+ """Write out documentation about the various entry types to stdout
+
+ Args:
+ modules: List of modules to include
+ test_missing: Used for testing. This is a module to report
+ as missing
+ """
+ print('''Binman Entry Documentation
+===========================
+
+This file describes the entry types supported by binman. These entry types can
+be placed in an image one by one to build up a final firmware image. It is
+fairly easy to create new entry types. Just add a new file to the 'etype'
+directory. You can use the existing entries as examples.
+
+Note that some entries are subclasses of others, using and extending their
+features to produce new behaviours.
+
+
+''')
+ modules = sorted(modules)
+
+ # Don't show the test entry
+ if '_testing' in modules:
+ modules.remove('_testing')
+ missing = []
+ for name in modules:
+ module = Entry.Lookup(name, name, name)
+ docs = getattr(module, '__doc__')
+ if test_missing == name:
+ docs = None
+ if docs:
+ lines = docs.splitlines()
+ first_line = lines[0]
+ rest = [line[4:] for line in lines[1:]]
+ hdr = 'Entry: %s: %s' % (name.replace('_', '-'), first_line)
+ print(hdr)
+ print('-' * len(hdr))
+ print('\n'.join(rest))
+ print()
+ print()
+ else:
+ missing.append(name)
+
+ if missing:
+ raise ValueError('Documentation is missing for modules: %s' %
+ ', '.join(missing))
# Entry-type module for testing purposes. Not used in real images.
#
-from entry import Entry
+from collections import OrderedDict
+
+from entry import Entry, EntryArg
import fdt_util
import tools
class Entry__testing(Entry):
"""A fake entry used for testing
+ This entry should not be used in normal images. It is a special entry with
+ strange features used for testing.
+
+ Properties / Entry arguments
+ test-str-fdt: Test string, normally in the node
+ test-int-fdt: Test integer, normally in the node
+ test-str-arg: Test string, normally in the entry arguments
+ test-int-arg: Test integer, normally in the entry arguments
+
+ The entry has a single 'a' byte as its contents. Operation is controlled by
+ a number of properties in the node, as follows:
+
Properties:
- return_invalid_entry: Return an invalid entry from GetPositions()
+ return-invalid-entry: Return an invalid entry from GetOffsets()
+ return-unknown-contents: Refuse to provide any contents (to cause a
+ failure)
+ bad-update-contents: Implement ProcessContents() incorrectly so as to
+ cause a failure
+ never-complete-process-fdt: Refund to process the FDT (to cause a
+ failure)
+ require-args: Require that all used args are present (generating an
+ error if not)
+ force-bad-datatype: Force a call to GetEntryArgsOrProps() with a bad
+ data type (generating an error)
"""
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
'return-unknown-contents')
self.bad_update_contents = fdt_util.GetBool(self._node,
'bad-update-contents')
+
+ # Set to True when the entry is ready to process the FDT.
self.process_fdt_ready = False
self.never_complete_process_fdt = fdt_util.GetBool(self._node,
'never-complete-process-fdt')
+ self.require_args = fdt_util.GetBool(self._node, 'require-args')
+
+ # This should be picked up by GetEntryArgsOrProps()
+ self.test_existing_prop = 'existing'
+ self.force_bad_datatype = fdt_util.GetBool(self._node,
+ 'force-bad-datatype')
+ (self.test_str_fdt, self.test_str_arg, self.test_int_fdt,
+ self.test_int_arg, existing) = self.GetEntryArgsOrProps([
+ EntryArg('test-str-fdt', str),
+ EntryArg('test-str-arg', str),
+ EntryArg('test-int-fdt', int),
+ EntryArg('test-int-arg', int),
+ EntryArg('test-existing-prop', str)], self.require_args)
+ if self.force_bad_datatype:
+ self.GetEntryArgsOrProps([EntryArg('test-bad-datatype-arg', bool)])
def ObtainContents(self):
if self.return_unknown_contents:
self.contents_size = len(self.data)
return True
- def GetPositions(self):
+ def GetOffsets(self):
if self.return_invalid_entry :
return {'invalid-entry': [1, 2]}
return {}
import tools
class Entry_blob(Entry):
+ """Entry containing an arbitrary binary blob
+
+ Note: This should not be used by itself. It is normally used as a parent
+ class by other entry types.
+
+ Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+ This entry reads data from a file and places it in the entry. The
+ default filename is often specified specified by the subclass. See for
+ example the 'u_boot' entry which provides the filename 'u-boot.bin'.
+ """
def __init__(self, section, etype, node):
Entry.__init__(self, section, etype, node)
self._filename = fdt_util.GetString(self._node, "filename", self.etype)
def ObtainContents(self):
self._filename = self.GetDefaultFilename()
self._pathname = tools.GetInputFilename(self._filename)
- self.ReadContents()
+ self.ReadBlobContents()
return True
- def ReadContents(self):
+ def ReadBlobContents(self):
with open(self._pathname) as fd:
# We assume the data is small enough to fit into memory. If this
# is used for large filesystem image that might not be true.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for a blob where the filename comes from a property in the
+# node or an entry argument. The property is called '<blob_fname>-path' where
+# <blob_fname> is provided by the subclass using this entry type.
+
+from collections import OrderedDict
+
+from blob import Entry_blob
+from entry import EntryArg
+
+
+class Entry_blob_named_by_arg(Entry_blob):
+ """A blob entry which gets its filename property from its subclass
+
+ Properties / Entry arguments:
+ - <xxx>-path: Filename containing the contents of this entry (optional,
+ defaults to 0)
+
+ where <xxx> is the blob_fname argument to the constructor.
+
+ This entry cannot be used directly. Instead, it is used as a parent class
+ for another entry, which defined blob_fname. This parameter is used to
+ set the entry-arg or property containing the filename. The entry-arg or
+ property is in turn used to set the actual filename.
+
+ See cros_ec_rw for an example of this.
+ """
+ def __init__(self, section, etype, node, blob_fname):
+ Entry_blob.__init__(self, section, etype, node)
+ self._filename, = self.GetEntryArgsOrProps(
+ [EntryArg('%s-path' % blob_fname, str)])
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for a Chromium OS EC image (read-write section)
+#
+
+from blob_named_by_arg import Entry_blob_named_by_arg
+
+
+class Entry_cros_ec_rw(Entry_blob_named_by_arg):
+ """A blob entry which contains a Chromium OS read-write EC image
+
+ Properties / Entry arguments:
+ - cros-ec-rw-path: Filename containing the EC image
+
+ This entry holds a Chromium OS EC (embedded controller) image, for use in
+ updating the EC on startup via software sync.
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob_named_by_arg.__init__(self, section, etype, node,
+ 'cros-ec-rw')
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+from entry import Entry
+import fdt_util
+
+
+class Entry_fill(Entry):
+ """An entry which is filled to a particular byte value
+
+ Properties / Entry arguments:
+ - fill-byte: Byte to use to fill the entry
+
+ Note that the size property must be set since otherwise this entry does not
+ know how large it should be.
+
+ You can often achieve the same effect using the pad-byte property of the
+ overall image, in that the space between entries will then be padded with
+ that byte. But this entry is sometimes useful for explicitly setting the
+ byte value of a region.
+ """
+ def __init__(self, section, etype, node):
+ Entry.__init__(self, section, etype, node)
+ if not self.size:
+ self.Raise("'fill' entry must have a size property")
+ self.fill_value = fdt_util.GetByte(self._node, 'fill-byte', 0)
+
+ def ObtainContents(self):
+ self.SetContents(chr(self.fill_value) * self.size)
+ return True
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for a Flash map, as used by the flashrom SPI flash tool
+#
+
+from entry import Entry
+import fmap_util
+
+
+class Entry_fmap(Entry):
+ """An entry which contains an Fmap section
+
+ Properties / Entry arguments:
+ None
+
+ FMAP is a simple format used by flashrom, an open-source utility for
+ reading and writing the SPI flash, typically on x86 CPUs. The format
+ provides flashrom with a list of areas, so it knows what it in the flash.
+ It can then read or write just a single area, instead of the whole flash.
+
+ The format is defined by the flashrom project, in the file lib/fmap.h -
+ see www.flashrom.org/Flashrom for more information.
+
+ When used, this entry will be populated with an FMAP which reflects the
+ entries in the current image. Note that any hierarchy is squashed, since
+ FMAP does not support this.
+ """
+ def __init__(self, section, etype, node):
+ Entry.__init__(self, section, etype, node)
+
+ def _GetFmap(self):
+ """Build an FMAP from the entries in the current image
+
+ Returns:
+ FMAP binary data
+ """
+ def _AddEntries(areas, entry):
+ entries = entry.GetEntries()
+ if entries:
+ for subentry in entries.values():
+ _AddEntries(areas, subentry)
+ else:
+ areas.append(fmap_util.FmapArea(entry.image_pos or 0,
+ entry.size or 0, entry.name, 0))
+
+ entries = self.section.GetEntries()
+ areas = []
+ for entry in entries.values():
+ _AddEntries(areas, entry)
+ return fmap_util.EncodeFmap(self.section.GetSize() or 0, self.name,
+ areas)
+
+ def ObtainContents(self):
+ """Obtain a placeholder for the fmap contents"""
+ self.SetContents(self._GetFmap())
+ return True
+
+ def ProcessContents(self):
+ self.SetContents(self._GetFmap())
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+# Support for a Chromium OS Google Binary Block, used to record read-only
+# information mostly used by firmware.
+
+from collections import OrderedDict
+
+import command
+from entry import Entry, EntryArg
+
+import fdt_util
+import tools
+
+# Build GBB flags.
+# (src/platform/vboot_reference/firmware/include/gbb_header.h)
+gbb_flag_properties = {
+ 'dev-screen-short-delay': 0x1,
+ 'load-option-roms': 0x2,
+ 'enable-alternate-os': 0x4,
+ 'force-dev-switch-on': 0x8,
+ 'force-dev-boot-usb': 0x10,
+ 'disable-fw-rollback-check': 0x20,
+ 'enter-triggers-tonorm': 0x40,
+ 'force-dev-boot-legacy': 0x80,
+ 'faft-key-override': 0x100,
+ 'disable-ec-software-sync': 0x200,
+ 'default-dev-boot-legacy': 0x400,
+ 'disable-pd-software-sync': 0x800,
+ 'disable-lid-shutdown': 0x1000,
+ 'force-dev-boot-fastboot-full-cap': 0x2000,
+ 'enable-serial': 0x4000,
+ 'disable-dwmp': 0x8000,
+}
+
+
+class Entry_gbb(Entry):
+ """An entry which contains a Chromium OS Google Binary Block
+
+ Properties / Entry arguments:
+ - hardware-id: Hardware ID to use for this build (a string)
+ - keydir: Directory containing the public keys to use
+ - bmpblk: Filename containing images used by recovery
+
+ Chromium OS uses a GBB to store various pieces of information, in particular
+ the root and recovery keys that are used to verify the boot process. Some
+ more details are here:
+
+ https://www.chromium.org/chromium-os/firmware-porting-guide/2-concepts
+
+ but note that the page dates from 2013 so is quite out of date. See
+ README.chromium for how to obtain the required keys and tools.
+ """
+ def __init__(self, section, etype, node):
+ Entry.__init__(self, section, etype, node)
+ self.hardware_id, self.keydir, self.bmpblk = self.GetEntryArgsOrProps(
+ [EntryArg('hardware-id', str),
+ EntryArg('keydir', str),
+ EntryArg('bmpblk', str)])
+
+ # Read in the GBB flags from the config
+ self.gbb_flags = 0
+ flags_node = node.FindNode('flags')
+ if flags_node:
+ for flag, value in gbb_flag_properties.iteritems():
+ if fdt_util.GetBool(flags_node, flag):
+ self.gbb_flags |= value
+
+ def ObtainContents(self):
+ gbb = 'gbb.bin'
+ fname = tools.GetOutputFilename(gbb)
+ if not self.size:
+ self.Raise('GBB must have a fixed size')
+ gbb_size = self.size
+ bmpfv_size = gbb_size - 0x2180
+ if bmpfv_size < 0:
+ self.Raise('GBB is too small (minimum 0x2180 bytes)')
+ sizes = [0x100, 0x1000, bmpfv_size, 0x1000]
+ sizes = ['%#x' % size for size in sizes]
+ keydir = tools.GetInputFilename(self.keydir)
+ gbb_set_command = [
+ 'gbb_utility', '-s',
+ '--hwid=%s' % self.hardware_id,
+ '--rootkey=%s/root_key.vbpubk' % keydir,
+ '--recoverykey=%s/recovery_key.vbpubk' % keydir,
+ '--flags=%d' % self.gbb_flags,
+ '--bmpfv=%s' % tools.GetInputFilename(self.bmpblk),
+ fname]
+
+ tools.Run('futility', 'gbb_utility', '-c', ','.join(sizes), fname)
+ tools.Run('futility', *gbb_set_command)
+
+ self.SetContents(tools.ReadFile(fname))
+ return True
from blob import Entry_blob
class Entry_intel_cmc(Entry_blob):
+ """Entry containing an Intel Chipset Micro Code (CMC) file
+
+ Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+ This file contains microcode for some devices in a special format. An
+ example filename is 'Microcode/C0_22211.BIN'.
+
+ See README.x86 for information about x86 binary blobs.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
FD_SIGNATURE = struct.pack('<L', 0x0ff0a55a)
MAX_REGIONS = 5
+# Region numbers supported by the Intel firmware format
(REGION_DESCRIPTOR, REGION_BIOS, REGION_ME, REGION_GBE,
REGION_PDATA) = range(5)
class Entry_intel_descriptor(Entry_blob):
"""Intel flash descriptor block (4KB)
- This is placed at the start of flash and provides information about
+ Properties / Entry arguments:
+ filename: Filename of file containing the descriptor. This is typically
+ a 4KB binary file, sometimes called 'descriptor.bin'
+
+ This entry is placed at the start of flash and provides information about
the SPI flash regions. In particular it provides the base address and
- size of the ME region, allowing us to place the ME binary in the right
- place.
+ size of the ME (Management Engine) region, allowing us to place the ME
+ binary in the right place.
+
+ With this entry in your image, the position of the 'intel-me' entry will be
+ fixed in the image, which avoids you needed to specify an offset for that
+ region. This is useful, because it is not possible to change the position
+ of the ME region without updating the descriptor.
+
+ See README.x86 for information about x86 binary blobs.
"""
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
self._regions = []
- def GetPositions(self):
- pos = self.data.find(FD_SIGNATURE)
- if pos == -1:
+ def GetOffsets(self):
+ offset = self.data.find(FD_SIGNATURE)
+ if offset == -1:
self.Raise('Cannot find FD signature')
flvalsig, flmap0, flmap1, flmap2 = struct.unpack('<LLLL',
- self.data[pos:pos + 16])
+ self.data[offset:offset + 16])
frba = ((flmap0 >> 16) & 0xff) << 4
for i in range(MAX_REGIONS):
self._regions.append(Region(self.data, frba, i))
from blob import Entry_blob
class Entry_intel_fsp(Entry_blob):
+ """Entry containing an Intel Firmware Support Package (FSP) file
+
+ Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+ This file contains binary blobs which are used on some devices to make the
+ platform work. U-Boot executes this code since it is not possible to set up
+ the hardware using U-Boot open-source code. Documentation is typically not
+ available in sufficient detail to allow this.
+
+ An example filename is 'FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd'
+
+ See README.x86 for information about x86 binary blobs.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
from blob import Entry_blob
class Entry_intel_me(Entry_blob):
+ """Entry containing an Intel Management Engine (ME) file
+
+ Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+ This file contains code used by the SoC that is required to make it work.
+ The Management Engine is like a background task that runs things that are
+ not clearly documented, but may include keyboard, deplay and network
+ access. For platform that use ME it is not possible to disable it. U-Boot
+ does not directly execute code in the ME binary.
+
+ A typical filename is 'me.bin'.
+
+ See README.x86 for information about x86 binary blobs.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
from blob import Entry_blob
class Entry_intel_mrc(Entry_blob):
+ """Entry containing an Intel Memory Reference Code (MRC) file
+
+ Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+ This file contains code for setting up the SDRAM on some Intel systems. This
+ is executed by U-Boot when needed early during startup. A typical filename
+ is 'mrc.bin'.
+
+ See README.x86 for information about x86 binary blobs.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
from blob import Entry_blob
class Entry_intel_vbt(Entry_blob):
+ """Entry containing an Intel Video BIOS Table (VBT) file
+
+ Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+ This file contains code that sets up the integrated graphics subsystem on
+ some Intel SoCs. U-Boot executes this when the display is started up.
+
+ See README.x86 for information about Intel binary blobs.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
from blob import Entry_blob
class Entry_intel_vga(Entry_blob):
+ """Entry containing an Intel Video Graphics Adaptor (VGA) file
+
+ Properties / Entry arguments:
+ - filename: Filename of file to read into entry
+
+ This file contains code that sets up the integrated graphics subsystem on
+ some Intel SoCs. U-Boot executes this when the display is started up.
+
+ This is similar to the VBT file but in a different format.
+
+ See README.x86 for information about Intel binary blobs.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
import bsection
class Entry_section(Entry):
- def __init__(self, image, etype, node):
- Entry.__init__(self, image, etype, node)
+ """Entry that contains other entries
+
+ Properties / Entry arguments: (see binman README for more information)
+ - size: Size of section in bytes
+ - align-size: Align size to a particular power of two
+ - pad-before: Add padding before the entry
+ - pad-after: Add padding after the entry
+ - pad-byte: Pad byte to use when padding
+ - sort-by-offset: Reorder the entries by offset
+ - end-at-4gb: Used to build an x86 ROM which ends at 4GB (2^32)
+ - name-prefix: Adds a prefix to the name of every entry in the section
+ when writing out the map
+
+ A section is an entry which can contain other entries, thus allowing
+ hierarchical images to be created. See 'Sections and hierarchical images'
+ in the binman README for more information.
+ """
+ def __init__(self, section, etype, node):
+ Entry.__init__(self, section, etype, node)
self._section = bsection.Section(node.name, node)
def ProcessFdt(self, fdt):
def GetData(self):
return self._section.GetData()
- def GetPositions(self):
- """Handle entries that want to set the position/size of other entries
+ def GetOffsets(self):
+ """Handle entries that want to set the offset/size of other entries
- This calls each entry's GetPositions() method. If it returns a list
+ This calls each entry's GetOffsets() method. If it returns a list
of entries to update, it updates them.
"""
- self._section.GetEntryPositions()
+ self._section.GetEntryOffsets()
return {}
- def Pack(self, pos):
+ def Pack(self, offset):
"""Pack all entries into the section"""
self._section.PackEntries()
- self.size = self._section.CheckSize()
- return super(Entry_section, self).Pack(pos)
+ self._section.SetOffset(offset)
+ self.size = self._section.GetSize()
+ return super(Entry_section, self).Pack(offset)
+
+ def SetImagePos(self, image_pos):
+ Entry.SetImagePos(self, image_pos)
+ self._section.SetImagePos(image_pos + self.offset)
def WriteSymbols(self, section):
"""Write symbol values into binary files for access at run time"""
self._section.ProcessEntryContents()
super(Entry_section, self).ProcessContents()
- def CheckPosition(self):
+ def CheckOffset(self):
self._section.CheckEntries()
def WriteMap(self, fd, indent):
Args:
fd: File to write the map to
"""
- super(Entry_section, self).WriteMap(fd, indent)
- self._section.WriteMap(fd, indent + 1)
+ self._section.WriteMap(fd, indent)
+
+ def GetEntries(self):
+ return self._section.GetEntries()
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+from collections import OrderedDict
+
+from entry import Entry, EntryArg
+import fdt_util
+
+
+class Entry_text(Entry):
+ """An entry which contains text
+
+ The text can be provided either in the node itself or by a command-line
+ argument. There is a level of indirection to allow multiple text strings
+ and sharing of text.
+
+ Properties / Entry arguments:
+ text-label: The value of this string indicates the property / entry-arg
+ that contains the string to place in the entry
+ <xxx> (actual name is the value of text-label): contains the string to
+ place in the entry.
+
+ Example node:
+
+ text {
+ size = <50>;
+ text-label = "message";
+ };
+
+ You can then use:
+
+ binman -amessage="this is my message"
+
+ and binman will insert that string into the entry.
+
+ It is also possible to put the string directly in the node:
+
+ text {
+ size = <8>;
+ text-label = "message";
+ message = "a message directly in the node"
+ };
+
+ The text is not itself nul-terminated. This can be achieved, if required,
+ by setting the size of the entry to something larger than the text.
+ """
+ def __init__(self, section, etype, node):
+ Entry.__init__(self, section, etype, node)
+ self.text_label, = self.GetEntryArgsOrProps(
+ [EntryArg('text-label', str)])
+ self.value, = self.GetEntryArgsOrProps([EntryArg(self.text_label, str)])
+
+ def ObtainContents(self):
+ self.SetContents(self.value)
+ return True
from blob import Entry_blob
class Entry_u_boot(Entry_blob):
+ """U-Boot flat binary
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot.bin (default 'u-boot.bin')
+
+ This is the U-Boot binary, containing relocation information to allow it
+ to relocate itself at runtime. The binary typically includes a device tree
+ blob at the end of it. Use u_boot_nodtb if you want to package the device
+ tree separately.
+
+ U-Boot can access binman symbols at runtime. See:
+
+ 'Access to binman entry offsets at run time (fdt)'
+
+ in the binman README for more information.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
from blob import Entry_blob
class Entry_u_boot_dtb(Entry_blob):
+ """U-Boot device tree
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot.dtb (default 'u-boot.dtb')
+
+ This is the U-Boot device tree, containing configuration information for
+ U-Boot. U-Boot needs this to know what devices are present and which drivers
+ to activate.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
#
import control
-import fdt
from entry import Entry
from blob import Entry_blob
import tools
class Entry_u_boot_dtb_with_ucode(Entry_blob):
"""A U-Boot device tree file, with the microcode removed
- See Entry_u_boot_ucode for full details of the 3 entries involved in this
- process.
+ Properties / Entry arguments:
+ - filename: Filename of u-boot.dtb (default 'u-boot.dtb')
+
+ See Entry_u_boot_ucode for full details of the three entries involved in
+ this process. This entry provides the U-Boot device-tree file, which
+ contains the microcode. If the microcode is not being collated into one
+ place then the offset and size of the microcode is recorded by this entry,
+ for use by u_boot_with_ucode_ptr. If it is being collated, then this
+ entry deletes the microcode from the device tree (to save space) and makes
+ it available to u_boot_ucode.
"""
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
return 'u-boot.dtb'
def ProcessFdt(self, fdt):
+ # So the module can be loaded without it
+ import fdt
+
# If the section does not need microcode, there is nothing to do
ucode_dest_entry = self.section.FindEntryType(
'u-boot-spl-with-ucode-ptr')
- if not ucode_dest_entry or not ucode_dest_entry.target_pos:
+ if not ucode_dest_entry or not ucode_dest_entry.target_offset:
ucode_dest_entry = self.section.FindEntryType(
'u-boot-with-ucode-ptr')
- if not ucode_dest_entry or not ucode_dest_entry.target_pos:
+ if not ucode_dest_entry or not ucode_dest_entry.target_offset:
return True
# Remove the microcode
# Call the base class just in case it does something important.
Entry_blob.ObtainContents(self)
self._pathname = control.GetFdtPath(self._filename)
- self.ReadContents()
+ self.ReadBlobContents()
if self.ucode:
for node in self.ucode.subnodes:
data_prop = node.props.get('data')
from blob import Entry_blob
class Entry_u_boot_img(Entry_blob):
+ """U-Boot legacy image
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot.img (default 'u-boot.img')
+
+ This is the U-Boot binary as a packaged image, in legacy format. It has a
+ header which allows it to be loaded at the correct address for execution.
+
+ You should use FIT (Flat Image Tree) instead of the legacy image for new
+ applications.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
from blob import Entry_blob
class Entry_u_boot_nodtb(Entry_blob):
+ """U-Boot flat binary without device tree appended
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot.bin (default 'u-boot-nodtb.bin')
+
+ This is the U-Boot binary, containing relocation information to allow it
+ to relocate itself at runtime. It does not include a device tree blob at
+ the end of it so normally cannot work without it. You can add a u_boot_dtb
+ entry after this one, or use a u_boot entry instead (which contains both
+ U-Boot and the device tree).
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
from blob import Entry_blob
class Entry_u_boot_spl(Entry_blob):
+ """U-Boot SPL binary
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot-spl.bin (default 'spl/u-boot-spl.bin')
+
+ This is the U-Boot SPL (Secondary Program Loader) binary. This is a small
+ binary which loads before U-Boot proper, typically into on-chip SRAM. It is
+ responsible for locating, loading and jumping to U-Boot. Note that SPL is
+ not relocatable so must be loaded to the correct address in SRAM, or written
+ to run from the correct address if direct flash execution is possible (e.g.
+ on x86 devices).
+
+ SPL can access binman symbols at runtime. See:
+
+ 'Access to binman entry offsets at run time (symbols)'
+
+ in the binman README for more information.
+
+ The ELF file 'spl/u-boot-spl' must also be available for this to work, since
+ binman uses that to look up symbols to write into the SPL binary.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
self.elf_fname = 'spl/u-boot-spl'
import tools
class Entry_u_boot_spl_bss_pad(Entry_blob):
+ """U-Boot SPL binary padded with a BSS region
+
+ Properties / Entry arguments:
+ None
+
+ This is similar to u_boot_spl except that padding is added after the SPL
+ binary to cover the BSS (Block Started by Symbol) region. This region holds
+ the various used by SPL. It is set to 0 by SPL when it starts up. If you
+ want to append data to the SPL image (such as a device tree file), you must
+ pad out the BSS region to avoid the data overlapping with U-Boot variables.
+ This entry is useful in that case. It automatically pads out the entry size
+ to cover both the code, data and BSS.
+
+ The ELF file 'spl/u-boot-spl' must also be available for this to work, since
+ binman uses that to look up the BSS address.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
# Copyright (c) 2016 Google, Inc
# Written by Simon Glass <sjg@chromium.org>
#
-# Entry-type module for U-Boot device tree
+# Entry-type module for U-Boot device tree in SPL (Secondary Program Loader)
#
from entry import Entry
from blob import Entry_blob
class Entry_u_boot_spl_dtb(Entry_blob):
+ """U-Boot SPL device tree
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot.dtb (default 'spl/u-boot-spl.dtb')
+
+ This is the SPL device tree, containing configuration information for
+ SPL. SPL needs this to know what devices are present and which drivers
+ to activate.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
from blob import Entry_blob
class Entry_u_boot_spl_nodtb(Entry_blob):
+ """SPL binary without device tree appended
+
+ Properties / Entry arguments:
+ - filename: Filename of spl/u-boot-spl-nodtb.bin (default
+ 'spl/u-boot-spl-nodtb.bin')
+
+ This is the U-Boot SPL binary, It does not include a device tree blob at
+ the end of it so may not be able to work without it, assuming SPL needs
+ a device tree to operation on your platform. You can add a u_boot_spl_dtb
+ entry after this one, or use a u_boot_spl entry instead (which contains
+ both SPL and the device tree).
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for tpl/u-boot-tpl.bin
+#
+
+import elf
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_tpl(Entry_blob):
+ """U-Boot TPL binary
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot-tpl.bin (default 'tpl/u-boot-tpl.bin')
+
+ This is the U-Boot TPL (Tertiary Program Loader) binary. This is a small
+ binary which loads before SPL, typically into on-chip SRAM. It is
+ responsible for locating, loading and jumping to SPL, the next-stage
+ loader. Note that SPL is not relocatable so must be loaded to the correct
+ address in SRAM, or written to run from the correct address if direct
+ flash execution is possible (e.g. on x86 devices).
+
+ SPL can access binman symbols at runtime. See:
+
+ 'Access to binman entry offsets at run time (symbols)'
+
+ in the binman README for more information.
+
+ The ELF file 'tpl/u-boot-tpl' must also be available for this to work, since
+ binman uses that to look up symbols to write into the TPL binary.
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+ self.elf_fname = 'tpl/u-boot-tpl'
+
+ def GetDefaultFilename(self):
+ return 'tpl/u-boot-tpl.bin'
+
+ def WriteSymbols(self, section):
+ elf.LookupAndWriteSymbols(self.elf_fname, self, section)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Entry-type module for U-Boot device tree in TPL (Tertiary Program Loader)
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_tpl_dtb(Entry_blob):
+ """U-Boot TPL device tree
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot.dtb (default 'tpl/u-boot-tpl.dtb')
+
+ This is the TPL device tree, containing configuration information for
+ TPL. TPL needs this to know what devices are present and which drivers
+ to activate.
+ """
+ def __init__(self, section, etype, node):
+ Entry_blob.__init__(self, section, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'tpl/u-boot-tpl.dtb'
class Entry_u_boot_ucode(Entry_blob):
"""U-Boot microcode block
+ Properties / Entry arguments:
+ None
+
+ The contents of this entry are filled in automatically by other entries
+ which must also be in the image.
+
U-Boot on x86 needs a single block of microcode. This is collected from
the various microcode update nodes in the device tree. It is also unable
to read the microcode from the device tree on platforms that use FSP
ucode_dest_entry = self.section.FindEntryType('u-boot-with-ucode-ptr')
ucode_dest_entry_spl = self.section.FindEntryType(
'u-boot-spl-with-ucode-ptr')
- if ((not ucode_dest_entry or not ucode_dest_entry.target_pos) and
- (not ucode_dest_entry_spl or not ucode_dest_entry_spl.target_pos)):
+ if ((not ucode_dest_entry or not ucode_dest_entry.target_offset) and
+ (not ucode_dest_entry_spl or not ucode_dest_entry_spl.target_offset)):
self.data = ''
return True
fd.write(fdt_entry.ucode_data)
self._pathname = fname
- self.ReadContents()
+ self.ReadBlobContents()
return True
class Entry_u_boot_with_ucode_ptr(Entry_blob):
"""U-Boot with embedded microcode pointer
- See Entry_u_boot_ucode for full details of the 3 entries involved in this
- process.
+ Properties / Entry arguments:
+ - filename: Filename of u-boot-nodtb.dtb (default 'u-boot-nodtb.dtb')
+
+ See Entry_u_boot_ucode for full details of the three entries involved in
+ this process. This entry updates U-Boot with the offset and size of the
+ microcode, to allow early x86 boot code to find it without doing anything
+ complicated. Otherwise it is the same as the u_boot entry.
"""
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
self.elf_fname = 'u-boot'
- self.target_pos = None
+ self.target_offset = None
def GetDefaultFilename(self):
return 'u-boot-nodtb.bin'
fname = tools.GetInputFilename(self.elf_fname)
sym = elf.GetSymbolAddress(fname, '_dt_ucode_base_size')
if sym:
- self.target_pos = sym
+ self.target_offset = sym
elif not fdt_util.GetBool(self._node, 'optional-ucode'):
self.Raise('Cannot locate _dt_ucode_base_size symbol in u-boot')
return True
def ProcessContents(self):
# If the image does not need microcode, there is nothing to do
- if not self.target_pos:
+ if not self.target_offset:
return
- # Get the position of the microcode
+ # Get the offset of the microcode
ucode_entry = self.section.FindEntryType('u-boot-ucode')
if not ucode_entry:
self.Raise('Cannot find microcode region u-boot-ucode')
# Check the target pos is in the section. If it is not, then U-Boot is
- # being linked incorrectly, or is being placed at the wrong position
+ # being linked incorrectly, or is being placed at the wrong offset
# in the section.
#
# The section must be set up so that U-Boot is placed at the
# flash address to which it is linked. For example, if
# CONFIG_SYS_TEXT_BASE is 0xfff00000, and the ROM is 8MB, then
- # the U-Boot region must start at position 7MB in the section. In this
- # case the ROM starts at 0xff800000, so the position of the first
+ # the U-Boot region must start at offset 7MB in the section. In this
+ # case the ROM starts at 0xff800000, so the offset of the first
# entry in the section corresponds to that.
- if (self.target_pos < self.pos or
- self.target_pos >= self.pos + self.size):
+ if (self.target_offset < self.offset or
+ self.target_offset >= self.offset + self.size):
self.Raise('Microcode pointer _dt_ucode_base_size at %08x is '
'outside the section ranging from %08x to %08x' %
- (self.target_pos, self.pos, self.pos + self.size))
+ (self.target_offset, self.offset, self.offset + self.size))
# Get the microcode, either from u-boot-ucode or u-boot-dtb-with-ucode.
# If we have left the microcode in the device tree, then it will be
# in the former. If we extracted the microcode from the device tree
# and collated it in one place, it will be in the latter.
if ucode_entry.size:
- pos, size = ucode_entry.pos, ucode_entry.size
+ offset, size = ucode_entry.offset, ucode_entry.size
else:
dtb_entry = self.section.FindEntryType('u-boot-dtb-with-ucode')
if not dtb_entry or not dtb_entry.ready:
self.Raise('Cannot find microcode region u-boot-dtb-with-ucode')
- pos = dtb_entry.pos + dtb_entry.ucode_offset
+ offset = dtb_entry.offset + dtb_entry.ucode_offset
size = dtb_entry.ucode_size
- # Write the microcode position and size into the entry
- pos_and_size = struct.pack('<2L', pos, size)
- self.target_pos -= self.pos
- self.ProcessContentsUpdate(self.data[:self.target_pos] + pos_and_size +
- self.data[self.target_pos + 8:])
+ # Write the microcode offset and size into the entry
+ offset_and_size = struct.pack('<2L', offset, size)
+ self.target_offset -= self.offset
+ self.ProcessContentsUpdate(self.data[:self.target_offset] +
+ offset_and_size +
+ self.data[self.target_offset + 8:])
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+# Support for a Chromium OS verified boot block, used to sign a read-write
+# section of the image.
+
+from collections import OrderedDict
+import os
+
+from entry import Entry, EntryArg
+
+import fdt_util
+import tools
+
+class Entry_vblock(Entry):
+ """An entry which contains a Chromium OS verified boot block
+
+ Properties / Entry arguments:
+ - keydir: Directory containing the public keys to use
+ - keyblock: Name of the key file to use (inside keydir)
+ - signprivate: Name of provide key file to use (inside keydir)
+ - version: Version number of the vblock (typically 1)
+ - kernelkey: Name of the kernel key to use (inside keydir)
+ - preamble-flags: Value of the vboot preamble flags (typically 0)
+
+ Chromium OS signs the read-write firmware and kernel, writing the signature
+ in this block. This allows U-Boot to verify that the next firmware stage
+ and kernel are genuine.
+ """
+ def __init__(self, section, etype, node):
+ Entry.__init__(self, section, etype, node)
+ self.content = fdt_util.GetPhandleList(self._node, 'content')
+ if not self.content:
+ self.Raise("Vblock must have a 'content' property")
+ (self.keydir, self.keyblock, self.signprivate, self.version,
+ self.kernelkey, self.preamble_flags) = self.GetEntryArgsOrProps([
+ EntryArg('keydir', str),
+ EntryArg('keyblock', str),
+ EntryArg('signprivate', str),
+ EntryArg('version', int),
+ EntryArg('kernelkey', str),
+ EntryArg('preamble-flags', int)])
+
+ def ObtainContents(self):
+ # Join up the data files to be signed
+ input_data = ''
+ for entry_phandle in self.content:
+ data = self.section.GetContentsByPhandle(entry_phandle, self)
+ if data is None:
+ # Data not available yet
+ return False
+ input_data += data
+
+ output_fname = tools.GetOutputFilename('vblock.%s' % self.name)
+ input_fname = tools.GetOutputFilename('input.%s' % self.name)
+ tools.WriteFile(input_fname, input_data)
+ prefix = self.keydir + '/'
+ args = [
+ 'vbutil_firmware',
+ '--vblock', output_fname,
+ '--keyblock', prefix + self.keyblock,
+ '--signprivate', prefix + self.signprivate,
+ '--version', '%d' % self.version,
+ '--fv', input_fname,
+ '--kernelkey', prefix + self.kernelkey,
+ '--flags', '%d' % self.preamble_flags,
+ ]
+ #out.Notice("Sign '%s' into %s" % (', '.join(self.value), self.label))
+ stdout = tools.Run('futility', *args)
+ #out.Debug(stdout)
+ self.SetContents(tools.ReadFile(output_fname))
+ return True
from blob import Entry_blob
class Entry_x86_start16(Entry_blob):
+ """x86 16-bit start-up code for U-Boot
+
+ Properties / Entry arguments:
+ - filename: Filename of u-boot-x86-16bit.bin (default
+ 'u-boot-x86-16bit.bin')
+
+ x86 CPUs start up in 16-bit mode, even if they are 32-bit CPUs. This code
+ must be placed at a particular address. This entry holds that code. It is
+ typically placed at offset CONFIG_SYS_X86_START16. The code is responsible
+ for changing to 32-bit mode and jumping to U-Boot's entry point, which
+ requires 32-bit mode (for 32-bit U-Boot).
+
+ For 64-bit U-Boot, the 'x86_start16_spl' entry type is used instead.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
from blob import Entry_blob
class Entry_x86_start16_spl(Entry_blob):
+ """x86 16-bit start-up code for SPL
+
+ Properties / Entry arguments:
+ - filename: Filename of spl/u-boot-x86-16bit-spl.bin (default
+ 'spl/u-boot-x86-16bit-spl.bin')
+
+ x86 CPUs start up in 16-bit mode, even if they are 64-bit CPUs. This code
+ must be placed at a particular address. This entry holds that code. It is
+ typically placed at offset CONFIG_SYS_X86_START16. The code is responsible
+ for changing to 32-bit mode and starting SPL, which in turn changes to
+ 64-bit mode and jumps to U-Boot (for 64-bit U-Boot).
+
+ For 32-bit U-Boot, the 'x86_start16' entry type is used instead.
+ """
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# Support for flashrom's FMAP format. This supports a header followed by a
+# number of 'areas', describing regions of a firmware storage device,
+# generally SPI flash.
+
+import collections
+import struct
+
+# constants imported from lib/fmap.h
+FMAP_SIGNATURE = '__FMAP__'
+FMAP_VER_MAJOR = 1
+FMAP_VER_MINOR = 0
+FMAP_STRLEN = 32
+
+FMAP_AREA_STATIC = 1 << 0
+FMAP_AREA_COMPRESSED = 1 << 1
+FMAP_AREA_RO = 1 << 2
+
+FMAP_HEADER_LEN = 56
+FMAP_AREA_LEN = 42
+
+FMAP_HEADER_FORMAT = '<8sBBQI%dsH'% (FMAP_STRLEN)
+FMAP_AREA_FORMAT = '<II%dsH' % (FMAP_STRLEN)
+
+FMAP_HEADER_NAMES = (
+ 'signature',
+ 'ver_major',
+ 'ver_minor',
+ 'base',
+ 'image_size',
+ 'name',
+ 'nareas',
+)
+
+FMAP_AREA_NAMES = (
+ 'offset',
+ 'size',
+ 'name',
+ 'flags',
+)
+
+# These are the two data structures supported by flashrom, a header (which
+# appears once at the start) and an area (which is repeated until the end of
+# the list of areas)
+FmapHeader = collections.namedtuple('FmapHeader', FMAP_HEADER_NAMES)
+FmapArea = collections.namedtuple('FmapArea', FMAP_AREA_NAMES)
+
+
+def ConvertName(field_names, fields):
+ """Convert a name to something flashrom likes
+
+ Flashrom requires upper case, underscores instead of hyphens. We remove any
+ null characters as well. This updates the 'name' value in fields.
+
+ Args:
+ field_names: List of field names for this struct
+ fields: Dict:
+ key: Field name
+ value: value of that field (string for the ones we support)
+ """
+ name_index = field_names.index('name')
+ fields[name_index] = fields[name_index].replace('\0', '').replace('-', '_').upper()
+
+def DecodeFmap(data):
+ """Decode a flashmap into a header and list of areas
+
+ Args:
+ data: Data block containing the FMAP
+
+ Returns:
+ Tuple:
+ header: FmapHeader object
+ List of FmapArea objects
+ """
+ fields = list(struct.unpack(FMAP_HEADER_FORMAT, data[:FMAP_HEADER_LEN]))
+ ConvertName(FMAP_HEADER_NAMES, fields)
+ header = FmapHeader(*fields)
+ areas = []
+ data = data[FMAP_HEADER_LEN:]
+ for area in range(header.nareas):
+ fields = list(struct.unpack(FMAP_AREA_FORMAT, data[:FMAP_AREA_LEN]))
+ ConvertName(FMAP_AREA_NAMES, fields)
+ areas.append(FmapArea(*fields))
+ data = data[FMAP_AREA_LEN:]
+ return header, areas
+
+def EncodeFmap(image_size, name, areas):
+ """Create a new FMAP from a list of areas
+
+ Args:
+ image_size: Size of image, to put in the header
+ name: Name of image, to put in the header
+ areas: List of FmapArea objects
+
+ Returns:
+ String containing the FMAP created
+ """
+ def _FormatBlob(fmt, names, obj):
+ params = [getattr(obj, name) for name in names]
+ return struct.pack(fmt, *params)
+
+ values = FmapHeader(FMAP_SIGNATURE, 1, 0, 0, image_size, name, len(areas))
+ blob = _FormatBlob(FMAP_HEADER_FORMAT, FMAP_HEADER_NAMES, values)
+ for area in areas:
+ blob += _FormatBlob(FMAP_AREA_FORMAT, FMAP_AREA_NAMES, area)
+ return blob
import elf
import fdt
import fdt_util
+import fmap_util
+import test_util
import tools
import tout
U_BOOT_DATA = '1234'
U_BOOT_IMG_DATA = 'img'
U_BOOT_SPL_DATA = '56780123456789abcde'
+U_BOOT_TPL_DATA = 'tpl'
BLOB_DATA = '89'
ME_DATA = '0abcd'
VGA_DATA = 'vga'
U_BOOT_DTB_DATA = 'udtb'
U_BOOT_SPL_DTB_DATA = 'spldtb'
+U_BOOT_TPL_DTB_DATA = 'tpldtb'
X86_START16_DATA = 'start16'
X86_START16_SPL_DATA = 'start16spl'
U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here'
CMC_DATA = 'cmc'
VBT_DATA = 'vbt'
MRC_DATA = 'mrc'
+TEXT_DATA = 'text'
+TEXT_DATA2 = 'text2'
+TEXT_DATA3 = 'text3'
+CROS_EC_RW_DATA = 'ecrw'
+GBB_DATA = 'gbbd'
+BMPBLK_DATA = 'bmp'
+VBLOCK_DATA = 'vblk'
+
class TestFunctional(unittest.TestCase):
"""Functional tests for binman
TestFunctional._MakeInputFile('u-boot.bin', U_BOOT_DATA)
TestFunctional._MakeInputFile('u-boot.img', U_BOOT_IMG_DATA)
TestFunctional._MakeInputFile('spl/u-boot-spl.bin', U_BOOT_SPL_DATA)
+ TestFunctional._MakeInputFile('tpl/u-boot-tpl.bin', U_BOOT_TPL_DATA)
TestFunctional._MakeInputFile('blobfile', BLOB_DATA)
TestFunctional._MakeInputFile('me.bin', ME_DATA)
TestFunctional._MakeInputFile('vga.bin', VGA_DATA)
- TestFunctional._MakeInputFile('u-boot.dtb', U_BOOT_DTB_DATA)
- TestFunctional._MakeInputFile('spl/u-boot-spl.dtb', U_BOOT_SPL_DTB_DATA)
+ self._ResetDtbs()
TestFunctional._MakeInputFile('u-boot-x86-16bit.bin', X86_START16_DATA)
TestFunctional._MakeInputFile('spl/u-boot-x86-16bit-spl.bin',
X86_START16_SPL_DATA)
TestFunctional._MakeInputFile('cmc.bin', CMC_DATA)
TestFunctional._MakeInputFile('vbt.bin', VBT_DATA)
TestFunctional._MakeInputFile('mrc.bin', MRC_DATA)
+ TestFunctional._MakeInputFile('ecrw.bin', CROS_EC_RW_DATA)
+ TestFunctional._MakeInputDir('devkeys')
+ TestFunctional._MakeInputFile('bmpblk.bin', BMPBLK_DATA)
self._output_setup = False
# ELF file with a '_dt_ucode_base_size' symbol
"""Remove the temporary output directory"""
tools._FinaliseForTest()
+ @classmethod
+ def _ResetDtbs(self):
+ TestFunctional._MakeInputFile('u-boot.dtb', U_BOOT_DTB_DATA)
+ TestFunctional._MakeInputFile('spl/u-boot-spl.dtb', U_BOOT_SPL_DTB_DATA)
+ TestFunctional._MakeInputFile('tpl/u-boot-tpl.dtb', U_BOOT_TPL_DTB_DATA)
+
def _RunBinman(self, *args, **kwargs):
"""Run binman using the command line
# options.verbosity = tout.DEBUG
return control.Binman(options, args)
- def _DoTestFile(self, fname, debug=False, map=False, update_dtb=False):
+ def _DoTestFile(self, fname, debug=False, map=False, update_dtb=False,
+ entry_args=None):
"""Run binman with a given test file
Args:
fname: Device-tree source filename to use (e.g. 05_simple.dts)
debug: True to enable debugging output
map: True to output map files for the images
- update_dtb: Update the position and size of each entry in the device
+ update_dtb: Update the offset and size of each entry in the device
tree before packing it into the image
"""
args = ['-p', '-I', self._indir, '-d', self.TestFile(fname)]
args.append('-m')
if update_dtb:
args.append('-up')
+ if entry_args:
+ for arg, value in entry_args.iteritems():
+ args.append('-a%s=%s' % (arg, value))
return self._DoBinman(*args)
def _SetupDtb(self, fname, outfile='u-boot.dtb'):
return data
def _DoReadFileDtb(self, fname, use_real_dtb=False, map=False,
- update_dtb=False):
+ update_dtb=False, entry_args=None):
"""Run binman and return the resulting image
This runs binman with a given test file and then reads the resulting
test contents (the U_BOOT_DTB_DATA string) can be used.
But in some test we need the real contents.
map: True to output map files for the images
- update_dtb: Update the position and size of each entry in the device
+ update_dtb: Update the offset and size of each entry in the device
tree before packing it into the image
Returns:
Resulting image contents
Device tree contents
Map data showing contents of image (or None if none)
+ Output device tree binary filename ('u-boot.dtb' path)
"""
dtb_data = None
# Use the compiled test file as the u-boot-dtb input
dtb_data = self._SetupDtb(fname)
try:
- retcode = self._DoTestFile(fname, map=map, update_dtb=update_dtb)
+ retcode = self._DoTestFile(fname, map=map, update_dtb=update_dtb,
+ entry_args=entry_args)
self.assertEqual(0, retcode)
out_dtb_fname = control.GetFdtPath('u-boot.dtb')
finally:
# Put the test file back
if use_real_dtb:
- TestFunctional._MakeInputFile('u-boot.dtb', U_BOOT_DTB_DATA)
+ self._ResetDtbs()
def _DoReadFile(self, fname, use_real_dtb=False):
"""Helper function which discards the device-tree binary
the u-boot-dtb entry. Normally this is not needed and the
test contents (the U_BOOT_DTB_DATA string) can be used.
But in some test we need the real contents.
+
+ Returns:
+ Resulting image contents
"""
return self._DoReadFileDtb(fname, use_real_dtb)[0]
"""Create a new test input file, creating directories as needed
Args:
- fname: Filenaem to create
+ fname: Filename to create
contents: File contents to write in to the file
Returns:
Full pathname of file created
fd.write(contents)
return pathname
+ @classmethod
+ def _MakeInputDir(self, dirname):
+ """Create a new test input directory, creating directories as needed
+
+ Args:
+ dirname: Directory name to create
+
+ Returns:
+ Full pathname of directory created
+ """
+ pathname = os.path.join(self._indir, dirname)
+ if not os.path.exists(pathname):
+ os.makedirs(pathname)
+ return pathname
+
@classmethod
def TestFile(self, fname):
return os.path.join(self._binman_dir, 'test', fname)
Args:
entries: List of entries to check
"""
- pos = 0
+ offset = 0
for entry in entries.values():
- self.assertEqual(pos, entry.pos)
- pos += entry.size
+ self.assertEqual(offset, entry.offset)
+ offset += entry.size
def GetFdtLen(self, dtb):
"""Get the totalsize field from a device-tree binary
"""
return struct.unpack('>L', dtb[4:8])[0]
- def _GetPropTree(self, dtb_data, node_names):
+ def _GetPropTree(self, dtb, prop_names):
def AddNode(node, path):
if node.name != '/':
path += '/' + node.name
- #print 'path', path
for subnode in node.subnodes:
for prop in subnode.props.values():
- if prop.name in node_names:
+ if prop.name in prop_names:
prop_path = path + '/' + subnode.name + ':' + prop.name
tree[prop_path[len('/binman/'):]] = fdt_util.fdt32_to_cpu(
prop.value)
- #print ' ', prop.name
AddNode(subnode, path)
tree = {}
- dtb = fdt.Fdt(dtb_data)
- dtb.Scan()
AddNode(dtb.GetRoot(), '')
return tree
with self.assertRaises(Exception) as e:
result = self._RunBinman('-d',
self.TestFile('04_invalid_entry.dts'))
- #print e.exception
self.assertIn("Unknown entry type 'not-a-valid-type' in node "
"'/binman/not-a-valid-type'", str(e.exception))
# First u-boot
self.assertIn('u-boot', entries)
entry = entries['u-boot']
- self.assertEqual(0, entry.pos)
+ self.assertEqual(0, entry.offset)
self.assertEqual(len(U_BOOT_DATA), entry.size)
# Second u-boot, aligned to 16-byte boundary
self.assertIn('u-boot-align', entries)
entry = entries['u-boot-align']
- self.assertEqual(16, entry.pos)
+ self.assertEqual(16, entry.offset)
self.assertEqual(len(U_BOOT_DATA), entry.size)
# Third u-boot, size 23 bytes
self.assertIn('u-boot-size', entries)
entry = entries['u-boot-size']
- self.assertEqual(20, entry.pos)
+ self.assertEqual(20, entry.offset)
self.assertEqual(len(U_BOOT_DATA), entry.contents_size)
self.assertEqual(23, entry.size)
# Fourth u-boot, placed immediate after the above
self.assertIn('u-boot-next', entries)
entry = entries['u-boot-next']
- self.assertEqual(43, entry.pos)
+ self.assertEqual(43, entry.offset)
self.assertEqual(len(U_BOOT_DATA), entry.size)
- # Fifth u-boot, placed at a fixed position
+ # Fifth u-boot, placed at a fixed offset
self.assertIn('u-boot-fixed', entries)
entry = entries['u-boot-fixed']
- self.assertEqual(61, entry.pos)
+ self.assertEqual(61, entry.offset)
self.assertEqual(len(U_BOOT_DATA), entry.size)
self.assertEqual(65, image._size)
# First u-boot with padding before and after
self.assertIn('u-boot', entries)
entry = entries['u-boot']
- self.assertEqual(0, entry.pos)
+ self.assertEqual(0, entry.offset)
self.assertEqual(3, entry.pad_before)
self.assertEqual(3 + 5 + len(U_BOOT_DATA), entry.size)
# Second u-boot has an aligned size, but it has no effect
self.assertIn('u-boot-align-size-nop', entries)
entry = entries['u-boot-align-size-nop']
- self.assertEqual(12, entry.pos)
+ self.assertEqual(12, entry.offset)
self.assertEqual(4, entry.size)
# Third u-boot has an aligned size too
self.assertIn('u-boot-align-size', entries)
entry = entries['u-boot-align-size']
- self.assertEqual(16, entry.pos)
+ self.assertEqual(16, entry.offset)
self.assertEqual(32, entry.size)
# Fourth u-boot has an aligned end
self.assertIn('u-boot-align-end', entries)
entry = entries['u-boot-align-end']
- self.assertEqual(48, entry.pos)
+ self.assertEqual(48, entry.offset)
self.assertEqual(16, entry.size)
# Fifth u-boot immediately afterwards
self.assertIn('u-boot-align-both', entries)
entry = entries['u-boot-align-both']
- self.assertEqual(64, entry.pos)
+ self.assertEqual(64, entry.offset)
self.assertEqual(64, entry.size)
self.CheckNoGaps(entries)
"power of two", str(e.exception))
def testPackInvalidAlign(self):
- """Test detection of an position that does not match its alignment"""
+ """Test detection of an offset that does not match its alignment"""
with self.assertRaises(ValueError) as e:
self._DoTestFile('12_pack_inv_align.dts')
- self.assertIn("Node '/binman/u-boot': Position 0x5 (5) does not match "
+ self.assertIn("Node '/binman/u-boot': Offset 0x5 (5) does not match "
"align 0x4 (4)", str(e.exception))
def testPackInvalidSizeAlign(self):
"""Test that overlapping regions are detected"""
with self.assertRaises(ValueError) as e:
self._DoTestFile('14_pack_overlap.dts')
- self.assertIn("Node '/binman/u-boot-align': Position 0x3 (3) overlaps "
+ self.assertIn("Node '/binman/u-boot-align': Offset 0x3 (3) overlaps "
"with previous entry '/binman/u-boot' ending at 0x4 (4)",
str(e.exception))
self.assertEqual(chr(0) * 1 + U_BOOT_SPL_DATA + chr(0) * 2 +
U_BOOT_DATA, data)
- def testPackZeroPosition(self):
- """Test that an entry at position 0 is not given a new position"""
+ def testPackZeroOffset(self):
+ """Test that an entry at offset 0 is not given a new offset"""
with self.assertRaises(ValueError) as e:
self._DoTestFile('25_pack_zero_size.dts')
- self.assertIn("Node '/binman/u-boot-spl': Position 0x0 (0) overlaps "
+ self.assertIn("Node '/binman/u-boot-spl': Offset 0x0 (0) overlaps "
"with previous entry '/binman/u-boot' ending at 0x4 (4)",
str(e.exception))
"using end-at-4gb", str(e.exception))
def testPackX86RomOutside(self):
- """Test that the end-at-4gb property checks for position boundaries"""
+ """Test that the end-at-4gb property checks for offset boundaries"""
with self.assertRaises(ValueError) as e:
self._DoTestFile('28_pack_4gb_outside.dts')
- self.assertIn("Node '/binman/u-boot': Position 0x0 (0) is outside "
+ self.assertIn("Node '/binman/u-boot': Offset 0x0 (0) is outside "
"the section starting at 0xffffffe0 (4294967264)",
str(e.exception))
"""Test that the Intel requires a descriptor entry"""
with self.assertRaises(ValueError) as e:
self._DoTestFile('30_x86-rom-me-no-desc.dts')
- self.assertIn("Node '/binman/intel-me': No position set with "
- "pos-unset: should another entry provide this correct "
- "position?", str(e.exception))
+ self.assertIn("Node '/binman/intel-me': No offset set with "
+ "offset-unset: should another entry provide this correct "
+ "offset?", str(e.exception))
def testPackX86RomMe(self):
"""Test that an x86 ROM with an ME region can be created"""
Returns:
Tuple:
Contents of first region (U-Boot or SPL)
- Position and size components of microcode pointer, as inserted
+ Offset and size components of microcode pointer, as inserted
in the above (two 4-byte words)
"""
data = self._DoReadFile(dts_fname, True)
self.assertEqual(ucode_data, ucode_content[:len(ucode_data)])
# Check that the microcode pointer was inserted. It should match the
- # expected position and size
+ # expected offset and size
pos_and_size = struct.pack('<2L', 0xfffffe00 + ucode_pos,
len(ucode_data))
u_boot = data[:len(nodtb_data)]
ucode_pos = second.find(ucode_data) + len(U_BOOT_NODTB_DATA)
# Check that the microcode pointer was inserted. It should match the
- # expected position and size
+ # expected offset and size
pos_and_size = struct.pack('<2L', 0xfffffe00 + ucode_pos,
len(ucode_data))
first = data[:len(U_BOOT_NODTB_DATA)]
"""Test that microcode must be placed within the image"""
with self.assertRaises(ValueError) as e:
self._DoReadFile('41_unknown_pos_size.dts', True)
- self.assertIn("Section '/binman': Unable to set pos/size for unknown "
+ self.assertIn("Section '/binman': Unable to set offset/size for unknown "
"entry 'invalid-entry'", str(e.exception))
def testPackFsp(self):
elf_fname = self.TestFile('u_boot_binman_syms')
syms = elf.GetSymbols(elf_fname, ['binman', 'image'])
addr = elf.GetSymbolAddress(elf_fname, '__image_copy_start')
- self.assertEqual(syms['_binman_u_boot_spl_prop_pos'].address, addr)
+ self.assertEqual(syms['_binman_u_boot_spl_prop_offset'].address, addr)
with open(self.TestFile('u_boot_binman_syms')) as fd:
TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
def testSections(self):
"""Basic test of sections"""
data = self._DoReadFile('55_sections.dts')
- expected = U_BOOT_DATA + '!' * 12 + U_BOOT_DATA + 'a' * 12 + '&' * 8
+ expected = (U_BOOT_DATA + '!' * 12 + U_BOOT_DATA + 'a' * 12 +
+ U_BOOT_DATA + '&' * 4)
self.assertEqual(expected, data)
def testMap(self):
"""Tests outputting a map of the images"""
_, _, map_data, _ = self._DoReadFileDtb('55_sections.dts', map=True)
- self.assertEqual('''Position Size Name
-00000000 00000010 section@0
- 00000000 00000004 u-boot
-00000010 00000010 section@1
- 00000000 00000004 u-boot
+ self.assertEqual('''ImagePos Offset Size Name
+00000000 00000000 00000028 main-section
+00000000 00000000 00000010 section@0
+00000000 00000000 00000004 u-boot
+00000010 00000010 00000010 section@1
+00000010 00000000 00000004 u-boot
+00000020 00000020 00000004 section@2
+00000020 00000000 00000004 u-boot
''', map_data)
def testNamePrefix(self):
"""Tests that name prefixes are used"""
_, _, map_data, _ = self._DoReadFileDtb('56_name_prefix.dts', map=True)
- self.assertEqual('''Position Size Name
-00000000 00000010 section@0
- 00000000 00000004 ro-u-boot
-00000010 00000010 section@1
- 00000000 00000004 rw-u-boot
+ self.assertEqual('''ImagePos Offset Size Name
+00000000 00000000 00000028 main-section
+00000000 00000000 00000010 section@0
+00000000 00000000 00000004 ro-u-boot
+00000010 00000010 00000010 section@1
+00000010 00000000 00000004 rw-u-boot
''', map_data)
def testUnknownContents(self):
'2 to 1', str(e.exception))
def testUpdateFdt(self):
- """Test that we can update the device tree with pos/size info"""
+ """Test that we can update the device tree with offset/size info"""
_, _, _, out_dtb_fname = self._DoReadFileDtb('60_fdt_update.dts',
update_dtb=True)
- props = self._GetPropTree(out_dtb_fname, ['pos', 'size'])
- with open('/tmp/x.dtb', 'wb') as outf:
- with open(out_dtb_fname) as inf:
- outf.write(inf.read())
+ dtb = fdt.Fdt(out_dtb_fname)
+ dtb.Scan()
+ props = self._GetPropTree(dtb, ['offset', 'size', 'image-pos'])
self.assertEqual({
- '_testing:pos': 32,
+ 'image-pos': 0,
+ 'offset': 0,
+ '_testing:offset': 32,
'_testing:size': 1,
- 'section@0/u-boot:pos': 0,
+ '_testing:image-pos': 32,
+ 'section@0/u-boot:offset': 0,
'section@0/u-boot:size': len(U_BOOT_DATA),
- 'section@0:pos': 0,
+ 'section@0/u-boot:image-pos': 0,
+ 'section@0:offset': 0,
'section@0:size': 16,
+ 'section@0:image-pos': 0,
- 'section@1/u-boot:pos': 0,
+ 'section@1/u-boot:offset': 0,
'section@1/u-boot:size': len(U_BOOT_DATA),
- 'section@1:pos': 16,
+ 'section@1/u-boot:image-pos': 16,
+ 'section@1:offset': 16,
'section@1:size': 16,
+ 'section@1:image-pos': 16,
'size': 40
}, props)
self.assertIn('Could not complete processing of Fdt: remaining '
'[<_testing.Entry__testing', str(e.exception))
+ def testEntryArgs(self):
+ """Test passing arguments to entries from the command line"""
+ entry_args = {
+ 'test-str-arg': 'test1',
+ 'test-int-arg': '456',
+ }
+ self._DoReadFileDtb('62_entry_args.dts', entry_args=entry_args)
+ self.assertIn('image', control.images)
+ entry = control.images['image'].GetEntries()['_testing']
+ self.assertEqual('test0', entry.test_str_fdt)
+ self.assertEqual('test1', entry.test_str_arg)
+ self.assertEqual(123, entry.test_int_fdt)
+ self.assertEqual(456, entry.test_int_arg)
+
+ def testEntryArgsMissing(self):
+ """Test missing arguments and properties"""
+ entry_args = {
+ 'test-int-arg': '456',
+ }
+ self._DoReadFileDtb('63_entry_args_missing.dts', entry_args=entry_args)
+ entry = control.images['image'].GetEntries()['_testing']
+ self.assertEqual('test0', entry.test_str_fdt)
+ self.assertEqual(None, entry.test_str_arg)
+ self.assertEqual(None, entry.test_int_fdt)
+ self.assertEqual(456, entry.test_int_arg)
+
+ def testEntryArgsRequired(self):
+ """Test missing arguments and properties"""
+ entry_args = {
+ 'test-int-arg': '456',
+ }
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('64_entry_args_required.dts')
+ self.assertIn("Node '/binman/_testing': Missing required "
+ 'properties/entry args: test-str-arg, test-int-fdt, test-int-arg',
+ str(e.exception))
+
+ def testEntryArgsInvalidFormat(self):
+ """Test that an invalid entry-argument format is detected"""
+ args = ['-d', self.TestFile('64_entry_args_required.dts'), '-ano-value']
+ with self.assertRaises(ValueError) as e:
+ self._DoBinman(*args)
+ self.assertIn("Invalid entry arguemnt 'no-value'", str(e.exception))
+
+ def testEntryArgsInvalidInteger(self):
+ """Test that an invalid entry-argument integer is detected"""
+ entry_args = {
+ 'test-int-arg': 'abc',
+ }
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('62_entry_args.dts', entry_args=entry_args)
+ self.assertIn("Node '/binman/_testing': Cannot convert entry arg "
+ "'test-int-arg' (value 'abc') to integer",
+ str(e.exception))
+
+ def testEntryArgsInvalidDatatype(self):
+ """Test that an invalid entry-argument datatype is detected
+
+ This test could be written in entry_test.py except that it needs
+ access to control.entry_args, which seems more than that module should
+ be able to see.
+ """
+ entry_args = {
+ 'test-bad-datatype-arg': '12',
+ }
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('65_entry_args_unknown_datatype.dts',
+ entry_args=entry_args)
+ self.assertIn('GetArg() internal error: Unknown data type ',
+ str(e.exception))
+
+ def testText(self):
+ """Test for a text entry type"""
+ entry_args = {
+ 'test-id': TEXT_DATA,
+ 'test-id2': TEXT_DATA2,
+ 'test-id3': TEXT_DATA3,
+ }
+ data, _, _, _ = self._DoReadFileDtb('66_text.dts',
+ entry_args=entry_args)
+ expected = (TEXT_DATA + chr(0) * (8 - len(TEXT_DATA)) + TEXT_DATA2 +
+ TEXT_DATA3 + 'some text')
+ self.assertEqual(expected, data)
+
+ def testEntryDocs(self):
+ """Test for creation of entry documentation"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ control.WriteEntryDocs(binman.GetEntryModules())
+ self.assertTrue(len(stdout.getvalue()) > 0)
+
+ def testEntryDocsMissing(self):
+ """Test handling of missing entry documentation"""
+ with self.assertRaises(ValueError) as e:
+ with test_util.capture_sys_output() as (stdout, stderr):
+ control.WriteEntryDocs(binman.GetEntryModules(), 'u_boot')
+ self.assertIn('Documentation is missing for modules: u_boot',
+ str(e.exception))
+
+ def testFmap(self):
+ """Basic test of generation of a flashrom fmap"""
+ data = self._DoReadFile('67_fmap.dts')
+ fhdr, fentries = fmap_util.DecodeFmap(data[32:])
+ expected = U_BOOT_DATA + '!' * 12 + U_BOOT_DATA + 'a' * 12
+ self.assertEqual(expected, data[:32])
+ self.assertEqual('__FMAP__', fhdr.signature)
+ self.assertEqual(1, fhdr.ver_major)
+ self.assertEqual(0, fhdr.ver_minor)
+ self.assertEqual(0, fhdr.base)
+ self.assertEqual(16 + 16 +
+ fmap_util.FMAP_HEADER_LEN +
+ fmap_util.FMAP_AREA_LEN * 3, fhdr.image_size)
+ self.assertEqual('FMAP', fhdr.name)
+ self.assertEqual(3, fhdr.nareas)
+ for fentry in fentries:
+ self.assertEqual(0, fentry.flags)
+
+ self.assertEqual(0, fentries[0].offset)
+ self.assertEqual(4, fentries[0].size)
+ self.assertEqual('RO_U_BOOT', fentries[0].name)
+
+ self.assertEqual(16, fentries[1].offset)
+ self.assertEqual(4, fentries[1].size)
+ self.assertEqual('RW_U_BOOT', fentries[1].name)
+
+ self.assertEqual(32, fentries[2].offset)
+ self.assertEqual(fmap_util.FMAP_HEADER_LEN +
+ fmap_util.FMAP_AREA_LEN * 3, fentries[2].size)
+ self.assertEqual('FMAP', fentries[2].name)
+
+ def testBlobNamedByArg(self):
+ """Test we can add a blob with the filename coming from an entry arg"""
+ entry_args = {
+ 'cros-ec-rw-path': 'ecrw.bin',
+ }
+ data, _, _, _ = self._DoReadFileDtb('68_blob_named_by_arg.dts',
+ entry_args=entry_args)
+
+ def testFill(self):
+ """Test for an fill entry type"""
+ data = self._DoReadFile('69_fill.dts')
+ expected = 8 * chr(0xff) + 8 * chr(0)
+ self.assertEqual(expected, data)
+
+ def testFillNoSize(self):
+ """Test for an fill entry type with no size"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('70_fill_no_size.dts')
+ self.assertIn("'fill' entry must have a size property",
+ str(e.exception))
+
+ def _HandleGbbCommand(self, pipe_list):
+ """Fake calls to the futility utility"""
+ if pipe_list[0][0] == 'futility':
+ fname = pipe_list[0][-1]
+ # Append our GBB data to the file, which will happen every time the
+ # futility command is called.
+ with open(fname, 'a') as fd:
+ fd.write(GBB_DATA)
+ return command.CommandResult()
+
+ def testGbb(self):
+ """Test for the Chromium OS Google Binary Block"""
+ command.test_result = self._HandleGbbCommand
+ entry_args = {
+ 'keydir': 'devkeys',
+ 'bmpblk': 'bmpblk.bin',
+ }
+ data, _, _, _ = self._DoReadFileDtb('71_gbb.dts', entry_args=entry_args)
+
+ # Since futility
+ expected = GBB_DATA + GBB_DATA + 8 * chr(0) + (0x2180 - 16) * chr(0)
+ self.assertEqual(expected, data)
+
+ def testGbbTooSmall(self):
+ """Test for the Chromium OS Google Binary Block being large enough"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('72_gbb_too_small.dts')
+ self.assertIn("Node '/binman/gbb': GBB is too small",
+ str(e.exception))
+
+ def testGbbNoSize(self):
+ """Test for the Chromium OS Google Binary Block having a size"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFileDtb('73_gbb_no_size.dts')
+ self.assertIn("Node '/binman/gbb': GBB must have a fixed size",
+ str(e.exception))
+
+ def _HandleVblockCommand(self, pipe_list):
+ """Fake calls to the futility utility"""
+ if pipe_list[0][0] == 'futility':
+ fname = pipe_list[0][3]
+ with open(fname, 'w') as fd:
+ fd.write(VBLOCK_DATA)
+ return command.CommandResult()
+
+ def testVblock(self):
+ """Test for the Chromium OS Verified Boot Block"""
+ command.test_result = self._HandleVblockCommand
+ entry_args = {
+ 'keydir': 'devkeys',
+ }
+ data, _, _, _ = self._DoReadFileDtb('74_vblock.dts',
+ entry_args=entry_args)
+ expected = U_BOOT_DATA + VBLOCK_DATA + U_BOOT_DTB_DATA
+ self.assertEqual(expected, data)
+
+ def testVblockNoContent(self):
+ """Test we detect a vblock which has no content to sign"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('75_vblock_no_content.dts')
+ self.assertIn("Node '/binman/vblock': Vblock must have a 'content' "
+ 'property', str(e.exception))
+
+ def testVblockBadPhandle(self):
+ """Test that we detect a vblock with an invalid phandle in contents"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('76_vblock_bad_phandle.dts')
+ self.assertIn("Node '/binman/vblock': Cannot find node for phandle "
+ '1000', str(e.exception))
+
+ def testVblockBadEntry(self):
+ """Test that we detect an entry that points to a non-entry"""
+ with self.assertRaises(ValueError) as e:
+ self._DoReadFile('77_vblock_bad_entry.dts')
+ self.assertIn("Node '/binman/vblock': Cannot find entry for node "
+ "'other'", str(e.exception))
+
+ def testTpl(self):
+ """Test that an image with TPL and ots device tree can be created"""
+ # ELF file with a '__bss_size' symbol
+ with open(self.TestFile('bss_data')) as fd:
+ TestFunctional._MakeInputFile('tpl/u-boot-tpl', fd.read())
+ data = self._DoReadFile('78_u_boot_tpl.dts')
+ self.assertEqual(U_BOOT_TPL_DATA + U_BOOT_TPL_DTB_DATA, data)
+
+ def testUsesPos(self):
+ """Test that the 'pos' property cannot be used anymore"""
+ with self.assertRaises(ValueError) as e:
+ data = self._DoReadFile('79_uses_pos.dts')
+ self.assertIn("Node '/binman/u-boot': Please use 'offset' instead of "
+ "'pos'", str(e.exception))
+
+
if __name__ == "__main__":
unittest.main()
def AddMissingProperties(self):
"""Add properties that are not present in the device tree
- When binman has completed packing the entries the position and size of
+ When binman has completed packing the entries the offset and size of
each entry are known. But before this the device tree may not specify
these. Add any missing properties, with a dummy value, so that the
size of the entry is correct. That way we can insert the correct values
"""
self._section.GetEntryContents()
- def GetEntryPositions(self):
- """Handle entries that want to set the position/size of other entries
+ def GetEntryOffsets(self):
+ """Handle entries that want to set the offset/size of other entries
- This calls each entry's GetPositions() method. If it returns a list
+ This calls each entry's GetOffsets() method. If it returns a list
of entries to update, it updates them.
"""
- self._section.GetEntryPositions()
+ self._section.GetEntryOffsets()
def PackEntries(self):
"""Pack all entries into the image"""
def SetCalculatedProperties(self):
self._section.SetCalculatedProperties()
+ def SetImagePos(self):
+ self._section.SetImagePos(0)
+
def ProcessEntryContents(self):
"""Call the ProcessContents() method for each entry
filename = '%s.map' % self._name
fname = tools.GetOutputFilename(filename)
with open(fname, 'w') as fd:
- print('%8s %8s %s' % ('Position', 'Size', 'Name'), file=fd)
+ print('%8s %8s %8s %s' % ('ImagePos', 'Offset', 'Size', 'Name'),
+ file=fd)
self._section.WriteMap(fd, 0)
u-boot-fixed {
type = "u-boot";
- pos = <61>;
+ offset = <61>;
};
};
};
binman {
u-boot {
- pos = <5>;
+ offset = <5>;
align = <4>;
};
};
u-boot-align {
type = "u-boot";
- pos = <3>;
+ offset = <3>;
};
};
};
};
u-boot {
- pos = <20>;
+ offset = <20>;
};
};
};
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
u-boot {
- pos = <22>;
+ offset = <22>;
};
u-boot-spl {
- pos = <1>;
+ offset = <1>;
};
};
};
};
u-boot-spl {
- pos = <0>;
+ offset = <0>;
};
};
};
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
u-boot {
- pos = <0xfffffff0>;
+ offset = <0xfffffff0>;
};
u-boot-spl {
- pos = <0xfffffff7>;
+ offset = <0xfffffff7>;
};
};
};
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <32>;
u-boot {
- pos = <0>;
+ offset = <0>;
};
u-boot-spl {
- pos = <0xffffffeb>;
+ offset = <0xffffffeb>;
};
};
};
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <32>;
u-boot {
- pos = <0xffffffe0>;
+ offset = <0xffffffe0>;
};
u-boot-spl {
- pos = <0xffffffeb>;
+ offset = <0xffffffeb>;
};
};
};
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <16>;
intel-me {
filename = "me.bin";
- pos-unset;
+ offset-unset;
};
};
};
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <0x800000>;
intel-descriptor {
intel-me {
filename = "me.bin";
- pos-unset;
+ offset-unset;
};
};
};
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <0x200>;
u-boot-with-ucode-ptr {
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <0x200>;
u-boot-with-ucode-ptr {
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <0x200>;
u-boot-with-ucode-ptr {
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <0x200>;
u-boot-with-ucode-ptr {
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <0x200>;
u-boot-with-ucode-ptr {
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
size = <0x200>;
u-boot-with-ucode-ptr {
};
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <0x200>;
u-boot-with-ucode-ptr {
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <16>;
intel-me {
filename = "me.bin";
- pos-unset;
+ offset-unset;
intval = <3>;
intarray = <5 6>;
byteval = [08];
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <0x200>;
u-boot-spl-with-ucode-ptr {
};
u-boot {
- pos = <20>;
+ offset = <20>;
};
u-boot-spl2 {
u-boot {
};
};
+ section@2 {
+ u-boot {
+ };
+ };
};
};
#size-cells = <1>;
binman {
- sort-by-pos;
+ sort-by-offset;
end-at-4gb;
size = <0x200>;
u-boot-spl-with-ucode-ptr {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ _testing {
+ test-str-fdt = "test0";
+ test-int-fdt = <123>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ _testing {
+ test-str-fdt = "test0";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ _testing {
+ require-args;
+ test-str-fdt = "test0";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ _testing {
+ test-str-fdt = "test0";
+ test-int-fdt = <123>;
+ force-bad-datatype;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ text {
+ size = <8>;
+ text-label = "test-id";
+ };
+ text2 {
+ type = "text";
+ text-label = "test-id2";
+ };
+ text3 {
+ type = "text";
+ text-label = "test-id3";
+ };
+ /* This one does not use command-line args */
+ text4 {
+ type = "text";
+ text-label = "test-id4";
+ test-id4 = "some text";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ section@0 {
+ read-only;
+ name-prefix = "ro-";
+ size = <0x10>;
+ pad-byte = <0x21>;
+
+ u-boot {
+ };
+ };
+ section@1 {
+ name-prefix = "rw-";
+ size = <0x10>;
+ pad-byte = <0x61>;
+
+ u-boot {
+ };
+ };
+ fmap {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ cros-ec-rw {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+ fill {
+ size = <8>;
+ fill-byte = [ff];
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+ fill {
+ fill-byte = [ff];
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ gbb {
+ size = <0x2180>;
+ flags {
+ dev-screen-short-delay;
+ load-option-roms;
+ enable-alternate-os;
+ force-dev-switch-on;
+ force-dev-boot-usb;
+ disable-fw-rollback-check;
+ enter-triggers-tonorm;
+ force-dev-boot-legacy;
+ faft-key-override;
+ disable-ec-software-sync;
+ default-dev-boot-legacy;
+ disable-pd-software-sync;
+ disable-lid-shutdown;
+ force-dev-boot-fastboot-full-cap;
+ enable-serial;
+ disable-dwmp;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ gbb {
+ size = <0x200>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ gbb {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u_boot: u-boot {
+ };
+
+ vblock {
+ content = <&u_boot &dtb>;
+ keyblock = "firmware.keyblock";
+ signprivate = "firmware_data_key.vbprivk";
+ version = <1>;
+ kernelkey = "kernel_subkey.vbpubk";
+ preamble-flags = <1>;
+ };
+
+ /*
+ * Put this after the vblock so that its contents are not
+ * available when the vblock first tries to obtain its contents
+ */
+ dtb: u-boot-dtb {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u_boot: u-boot {
+ };
+
+ vblock {
+ keyblock = "firmware.keyblock";
+ signprivate = "firmware_data_key.vbprivk";
+ version = <1>;
+ kernelkey = "kernel_subkey.vbpubk";
+ preamble-flags = <1>;
+ };
+
+ dtb: u-boot-dtb {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u_boot: u-boot {
+ };
+
+ vblock {
+ content = <1000>;
+ keyblock = "firmware.keyblock";
+ signprivate = "firmware_data_key.vbprivk";
+ version = <1>;
+ kernelkey = "kernel_subkey.vbpubk";
+ preamble-flags = <1>;
+ };
+
+ dtb: u-boot-dtb {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u_boot: u-boot {
+ };
+
+ vblock {
+ content = <&u_boot &other>;
+ keyblock = "firmware.keyblock";
+ signprivate = "firmware_data_key.vbprivk";
+ version = <1>;
+ kernelkey = "kernel_subkey.vbpubk";
+ preamble-flags = <1>;
+ };
+
+ dtb: u-boot-dtb {
+ };
+ };
+
+ other: other {
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ u-boot-tpl {
+ };
+ u-boot-tpl-dtb {
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+/ {
+ binman {
+ u-boot {
+ pos = <10>;
+ };
+ };
+};
#define CONFIG_BINMAN
#include <binman_sym.h>
-binman_sym_declare(unsigned long, u_boot_spl, pos);
-binman_sym_declare(unsigned long long, u_boot_spl2, pos);
-binman_sym_declare(unsigned long, u_boot_any, pos);
+binman_sym_declare(unsigned long, u_boot_spl, offset);
+binman_sym_declare(unsigned long long, u_boot_spl2, offset);
+binman_sym_declare(unsigned long, u_boot_any, image_pos);
self.subnodes = []
self.props = {}
- def _FindNode(self, name):
+ def GetFdt(self):
+ """Get the Fdt object for this node
+
+ Returns:
+ Fdt object
+ """
+ return self._fdt
+
+ def FindNode(self, name):
"""Find a node given its name
Args:
with open(self._fname) as fd:
self._fdt_obj = libfdt.Fdt(fd.read())
+ def LookupPhandle(self, phandle):
+ """Look up a phandle
+
+ Args:
+ phandle: Phandle to look up (int)
+
+ Returns:
+ Node object the phandle points to
+ """
+ return self.phandle_to_node.get(phandle)
+
def Scan(self, root='/'):
"""Scan a device tree, building up a tree of Node objects
if len(parts) < 2:
return None
for part in parts[1:]:
- node = node._FindNode(part)
+ node = node.FindNode(part)
if not node:
return None
return node
# Written by Simon Glass <sjg@chromium.org>
#
+# Utility functions for reading from a device tree. Once the upstream pylibfdt
+# implementation advances far enough, we should be able to drop these.
+
import os
import struct
import sys
return dtb_output
def GetInt(node, propname, default=None):
+ """Get an integer from a property
+
+ Args:
+ node: Node object to read from
+ propname: property name to read
+ default: Default value to use if the node/property do not exist
+
+ Returns:
+ Integer value read, or default if none
+ """
prop = node.props.get(propname)
if not prop:
return default
return value
def GetString(node, propname, default=None):
+ """Get a string from a property
+
+ Args:
+ node: Node object to read from
+ propname: property name to read
+ default: Default value to use if the node/property do not exist
+
+ Returns:
+ String value read, or default if none
+ """
prop = node.props.get(propname)
if not prop:
return default
return value
def GetBool(node, propname, default=False):
+ """Get an boolean from a property
+
+ Args:
+ node: Node object to read from
+ propname: property name to read
+ default: Default value to use if the node/property do not exist
+
+ Returns:
+ Boolean value read, or default if none (if you set this to True the
+ function will always return True)
+ """
if propname in node.props:
return True
return default
+
+def GetByte(node, propname, default=None):
+ """Get an byte from a property
+
+ Args:
+ node: Node object to read from
+ propname: property name to read
+ default: Default value to use if the node/property do not exist
+
+ Returns:
+ Byte value read, or default if none
+ """
+ prop = node.props.get(propname)
+ if not prop:
+ return default
+ value = prop.value
+ if isinstance(value, list):
+ raise ValueError("Node '%s' property '%s' has list value: expecting "
+ "a single byte" % (node.name, propname))
+ if len(value) != 1:
+ raise ValueError("Node '%s' property '%s' has length %d, expecting %d" %
+ (node.name, propname, len(value), 1))
+ return ord(value[0])
+
+def GetPhandleList(node, propname):
+ """Get a list of phandles from a property
+
+ Args:
+ node: Node object to read from
+ propname: property name to read
+
+ Returns:
+ List of phandles read, each an integer
+ """
+ prop = node.props.get(propname)
+ if not prop:
+ return None
+ value = prop.value
+ if not isinstance(value, list):
+ value = [value]
+ return [fdt32_to_cpu(v) for v in value]
+
+def GetDatatype(node, propname, datatype):
+ """Get a value of a given type from a property
+
+ Args:
+ node: Node object to read from
+ propname: property name to read
+ datatype: Type to read (str or int)
+
+ Returns:
+ value read, or None if none
+
+ Raises:
+ ValueError if datatype is not str or int
+ """
+ if datatype == str:
+ return GetString(node, propname)
+ elif datatype == int:
+ return GetInt(node, propname)
+ raise ValueError("fdt_util internal error: Unknown data type '%s'" %
+ datatype)
fdt.CheckErr(-libfdt.NOTFOUND, 'hello')
self.assertIn('FDT_ERR_NOTFOUND: hello', str(e.exception))
+ def testGetFdt(self):
+ node = self.dtb.GetNode('/spl-test')
+ self.assertEqual(self.dtb, node.GetFdt())
class TestNode(unittest.TestCase):
"""Test operation of the Node class"""
self.assertEqual(prop.value, value)
def testFindNode(self):
- """Tests that we can find a node using the _FindNode() functoin"""
- node = self.dtb.GetRoot()._FindNode('i2c@0')
+ """Tests that we can find a node using the FindNode() functoin"""
+ node = self.dtb.GetRoot().FindNode('i2c@0')
self.assertEqual('i2c@0', node.name)
- subnode = node._FindNode('pmic@9')
+ subnode = node.FindNode('pmic@9')
self.assertEqual('pmic@9', subnode.name)
- self.assertEqual(None, node._FindNode('missing'))
+ self.assertEqual(None, node.FindNode('missing'))
def testRefreshMissingNode(self):
"""Test refreshing offsets when an extra node is present in dtb"""
self.assertIn("Internal error, property 'notstring' missing, offset ",
str(e.exception))
+ def testLookupPhandle(self):
+ """Test looking up a single phandle"""
+ dtb = fdt.FdtScan('tools/dtoc/dtoc_test_phandle.dts')
+ node = dtb.GetNode('/phandle-source2')
+ prop = node.props['clocks']
+ target = dtb.GetNode('/phandle-target')
+ self.assertEqual(target, dtb.LookupPhandle(fdt32_to_cpu(prop.value)))
+
class TestProp(unittest.TestCase):
"""Test operation of the Prop class"""
self.assertEqual(True, fdt_util.GetBool(self.node, 'missing', True))
self.assertEqual(False, fdt_util.GetBool(self.node, 'missing', False))
+ def testGetByte(self):
+ self.assertEqual(5, fdt_util.GetByte(self.node, 'byteval'))
+ self.assertEqual(3, fdt_util.GetByte(self.node, 'missing', 3))
+
+ with self.assertRaises(ValueError) as e:
+ fdt_util.GetByte(self.node, 'longbytearray')
+ self.assertIn("property 'longbytearray' has list value: expecting a "
+ 'single byte', str(e.exception))
+
+ with self.assertRaises(ValueError) as e:
+ fdt_util.GetByte(self.node, 'intval')
+ self.assertIn("property 'intval' has length 4, expecting 1",
+ str(e.exception))
+
+ def testGetPhandleList(self):
+ dtb = fdt.FdtScan('tools/dtoc/dtoc_test_phandle.dts')
+ node = dtb.GetNode('/phandle-source2')
+ self.assertEqual([1], fdt_util.GetPhandleList(node, 'clocks'))
+ node = dtb.GetNode('/phandle-source')
+ self.assertEqual([1, 2, 11, 3, 12, 13, 1],
+ fdt_util.GetPhandleList(node, 'clocks'))
+ self.assertEqual(None, fdt_util.GetPhandleList(node, 'missing'))
+
+ def testGetDataType(self):
+ self.assertEqual(1, fdt_util.GetDatatype(self.node, 'intval', int))
+ self.assertEqual('message', fdt_util.GetDatatype(self.node, 'stringval',
+ str))
+ with self.assertRaises(ValueError) as e:
+ self.assertEqual(3, fdt_util.GetDatatype(self.node, 'boolval',
+ bool))
def testFdtCellsToCpu(self):
val = self.node.props['intarray'].value
self.assertEqual(0, fdt_util.fdt_cells_to_cpu(val, 0))
import tempfile
import time
-sys.path.append(os.path.join(os.path.dirname(__file__), 'buildman'))
+sys.path.insert(1, os.path.join(os.path.dirname(__file__), 'buildman'))
import kconfiglib
### constant variables ###
}
n = read(fd, buf, len);
- if (n < 0)
+ if (n <= 0)
goto out;
buf = (char *)buf + n;
char _buf[128], *buf = _buf;
nin = read(in, buf, sizeof(buf));
- if (nin < 0)
+ if (nin <= 0)
return -1;
if (quit) {
perror("debugmsg");
goto out;
}
- } else {
+ } else if (bootmsg) {
rc = kwboot_bootmsg(tty, bootmsg);
if (rc) {
perror("bootmsg");
"""
if test_result:
if hasattr(test_result, '__call__'):
- return test_result(pipe_list=pipe_list)
- return test_result
+ result = test_result(pipe_list=pipe_list)
+ if result:
+ return result
+ else:
+ return test_result
+ # No result: fall through to normal processing
result = CommandResult()
last_pipe = None
pipeline = list(pipe_list)
line = line.strip()
if not line or line.startswith('#'):
continue
- words = line.split(' ', 2)
+ words = line.split(None, 2)
if len(words) < 3 or words[0] != 'alias':
if not bad_line:
bad_line = "%s:%d:Invalid line '%s'" % (fname, linenum,
# Copyright (c) 2016 Google, Inc
#
+import command
import os
import shutil
import tempfile
import tout
+# Output directly (generally this is temporary)
outdir = None
-indirs = None
+
+# True to keep the output directory around after exiting
preserve_outdir = False
+# Path to the Chrome OS chroot, if we know it
+chroot_path = None
+
+# Search paths to use for Filename(), used to find files
+search_paths = []
+
+
def PrepareOutputDir(dirname, preserve=False):
"""Select an output directory, ensuring it exists.
if os.path.exists(pathname):
return pathname
- raise ValueError("Filename '%s' not found in input path (%s)" %
- (fname, ','.join(indir)))
+ raise ValueError("Filename '%s' not found in input path (%s) (cwd='%s')" %
+ (fname, ','.join(indir), os.getcwd()))
def Align(pos, align):
if align:
def NotPowerOfTwo(num):
return num and (num & (num - 1))
+
+def Run(name, *args):
+ command.Run(name, *args, cwd=outdir)
+
+def Filename(fname):
+ """Resolve a file path to an absolute path.
+
+ If fname starts with ##/ and chroot is available, ##/ gets replaced with
+ the chroot path. If chroot is not available, this file name can not be
+ resolved, `None' is returned.
+
+ If fname is not prepended with the above prefix, and is not an existing
+ file, the actual file name is retrieved from the passed in string and the
+ search_paths directories (if any) are searched to for the file. If found -
+ the path to the found file is returned, `None' is returned otherwise.
+
+ Args:
+ fname: a string, the path to resolve.
+
+ Returns:
+ Absolute path to the file or None if not found.
+ """
+ if fname.startswith('##/'):
+ if chroot_path:
+ fname = os.path.join(chroot_path, fname[3:])
+ else:
+ return None
+
+ # Search for a pathname that exists, and return it if found
+ if fname and not os.path.exists(fname):
+ for path in search_paths:
+ pathname = os.path.join(path, os.path.basename(fname))
+ if os.path.exists(pathname):
+ return pathname
+
+ # If not found, just return the standard, unchanged path
+ return fname
+
+def ReadFile(fname):
+ """Read and return the contents of a file.
+
+ Args:
+ fname: path to filename to read, where ## signifiies the chroot.
+
+ Returns:
+ data read from file, as a string.
+ """
+ with open(Filename(fname), 'rb') as fd:
+ data = fd.read()
+ #self._out.Info("Read file '%s' size %d (%#0x)" %
+ #(fname, len(data), len(data)))
+ return data
+
+def WriteFile(fname, data):
+ """Write data into a file.
+
+ Args:
+ fname: path to filename to write
+ data: data to write to file, as a string
+ """
+ #self._out.Info("Write file '%s' size %d (%#0x)" %
+ #(fname, len(data), len(data)))
+ with open(Filename(fname), 'wb') as fd:
+ fd.write(data)
projects / project / bcm63xx / u-boot.git / commitdiff