From: David Bauer <mail@david-bauer.net>
Date: Sun, 6 Jun 2021 17:45:24 +0000 (+0200)
Subject: ramips: make PHY initialization more descriptive
X-Git-Tag: v22.03.0-rc1~2392
X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=6a15abbc753ca728d798cec9153fc532fce3791d;p=openwrt%2Fopenwrt.git

ramips: make PHY initialization more descriptive

The basic mode control register of the ESW PHYs is modified in this
codeblock. Use the respective macros to make this code more readable.

Signed-off-by: David Bauer <mail@david-bauer.net>
---

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
index bd379e6c7d..451881fc73 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
@@ -13,6 +13,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/mii.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/platform_device.h>
@@ -168,9 +169,9 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
 
 		/* turn on all PHYs */
 		for (i = 0; i <= 4; i++) {
-			val = _mt7620_mii_read(gsw, gsw->ephy_base + i, 0);
-			val &= ~BIT(11);
-			_mt7620_mii_write(gsw, gsw->ephy_base + i, 0, val);
+			val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);
+			val &= ~BMCR_PDOWN;
+			_mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);
 		}
 	}